[INFO] fetching crate mspm0l130x 0.1.5...
[INFO] checking mspm0l130x-0.1.5 against master#6eda7419e71fdbc1185ed5be7e6bff1a474ab5cd for pr-153721
[INFO] extracting crate mspm0l130x 0.1.5 into /workspace/builds/worker-4-tc1/source
[INFO] started tweaking crates.io crate mspm0l130x 0.1.5
[INFO] finished tweaking crates.io crate mspm0l130x 0.1.5
[INFO] tweaked toml for crates.io crate mspm0l130x 0.1.5 written to /workspace/builds/worker-4-tc1/source/Cargo.toml
[INFO] validating manifest of crates.io crate mspm0l130x 0.1.5 on toolchain 6eda7419e71fdbc1185ed5be7e6bff1a474ab5cd
[INFO] running `Command { std: CARGO_HOME="/workspace/cargo-home" RUSTUP_HOME="/workspace/rustup-home" "/workspace/cargo-home/bin/cargo" "+6eda7419e71fdbc1185ed5be7e6bff1a474ab5cd" "metadata" "--manifest-path" "Cargo.toml" "--no-deps", kill_on_drop: false }`
[INFO] running `Command { std: CARGO_HOME="/workspace/cargo-home" RUSTUP_HOME="/workspace/rustup-home" "/workspace/cargo-home/bin/cargo" "+6eda7419e71fdbc1185ed5be7e6bff1a474ab5cd" "generate-lockfile" "--manifest-path" "Cargo.toml", kill_on_drop: false }`
[INFO] [stderr]     Updating crates.io index
[INFO] [stderr]      Locking 28 packages to latest compatible versions
[INFO] [stderr]       Adding cortex-m v0.6.7 (available: v0.7.7)
[INFO] [stderr]       Adding cortex-m-rt v0.6.15 (available: v0.7.5)
[INFO] running `Command { std: CARGO_HOME="/workspace/cargo-home" RUSTUP_HOME="/workspace/rustup-home" "/workspace/cargo-home/bin/cargo" "+6eda7419e71fdbc1185ed5be7e6bff1a474ab5cd" "fetch" "--manifest-path" "Cargo.toml", kill_on_drop: false }`
[INFO] [stderr]  Downloading crates ...
[INFO] [stderr]   Downloaded cortex-m-rt v0.6.15
[INFO] [stderr]   Downloaded cortex-m-rt-macros v0.6.15
[INFO] [stderr]   Downloaded cortex-m v0.6.7
[INFO] [stderr]   Downloaded as-slice v0.1.5
[INFO] [stderr]   Downloaded generic-array v0.13.3
[INFO] [stderr]   Downloaded aligned v0.3.5
[INFO] [stderr]   Downloaded r0 v0.2.2
[INFO] running `Command { std: "docker" "create" "-v" "/var/lib/crater-agent-workspace/builds/worker-4-tc1/source:/opt/rustwide/workdir:ro,Z" "-v" "/var/lib/crater-agent-workspace/builds/worker-4-tc1/target:/opt/rustwide/target:rw,Z" "-v" "/var/lib/crater-agent-workspace/cargo-home:/opt/rustwide/cargo-home:ro,Z" "-v" "/var/lib/crater-agent-workspace/rustup-home:/opt/rustwide/rustup-home:ro,Z" "-m" "1610612736" "--network" "none" "ghcr.io/rust-lang/crates-build-env/linux@sha256:3e793bdf10248eb2ddbd6b0faebed8155c11b4589982e2893733958d93e8d540" "sleep" "infinity", kill_on_drop: false }`
[INFO] [stdout] c5146ddbd57f788f97ddfb4b4f2a47377903b3cfc879629f0a382a5cbe4fd977
[INFO] running `Command { std: "docker" "start" "c5146ddbd57f788f97ddfb4b4f2a47377903b3cfc879629f0a382a5cbe4fd977", kill_on_drop: false }`
[INFO] running `Command { std: "docker" "exec" "-e" "SOURCE_DIR=/opt/rustwide/workdir" "-e" "CARGO_HOME=/opt/rustwide/cargo-home" "-e" "RUSTUP_HOME=/opt/rustwide/rustup-home" "-e" "CARGO_TARGET_DIR=/opt/rustwide/target" "-w" "/opt/rustwide/workdir" "--user" "0:0" "c5146ddbd57f788f97ddfb4b4f2a47377903b3cfc879629f0a382a5cbe4fd977" "/opt/rustwide/cargo-home/bin/cargo" "+6eda7419e71fdbc1185ed5be7e6bff1a474ab5cd" "metadata" "--no-deps" "--format-version=1", kill_on_drop: false }`
[INFO] running `Command { std: "docker" "inspect" "c5146ddbd57f788f97ddfb4b4f2a47377903b3cfc879629f0a382a5cbe4fd977", kill_on_drop: false }`
[INFO] running `Command { std: "docker" "exec" "-e" "SOURCE_DIR=/opt/rustwide/workdir" "-e" "CARGO_HOME=/opt/rustwide/cargo-home" "-e" "RUSTUP_HOME=/opt/rustwide/rustup-home" "-e" "CARGO_TARGET_DIR=/opt/rustwide/target" "-e" "CARGO_INCREMENTAL=0" "-e" "RUST_BACKTRACE=full" "-e" "RUSTFLAGS=--cap-lints=forbid" "-e" "RUSTDOCFLAGS=--cap-lints=forbid" "-w" "/opt/rustwide/workdir" "--user" "0:0" "c5146ddbd57f788f97ddfb4b4f2a47377903b3cfc879629f0a382a5cbe4fd977" "/opt/rustwide/cargo-home/bin/cargo" "+6eda7419e71fdbc1185ed5be7e6bff1a474ab5cd" "check" "--frozen" "--all" "--all-targets" "--message-format=json", kill_on_drop: false }`
[INFO] [stderr]    Compiling cortex-m v0.7.7
[INFO] [stderr]     Checking vcell v0.1.3
[INFO] [stderr]     Checking bitfield v0.13.2
[INFO] [stderr]    Compiling cortex-m v0.6.7
[INFO] [stderr]    Compiling mspm0l130x v0.1.5 (/opt/rustwide/workdir)
[INFO] [stderr]     Checking generic-array v0.12.4
[INFO] [stderr]     Checking generic-array v0.13.3
[INFO] [stderr]    Compiling bare-metal v0.2.5
[INFO] [stderr]     Checking embedded-hal v0.2.7
[INFO] [stderr]     Checking volatile-register v0.2.2
[INFO] [stderr]     Checking as-slice v0.1.5
[INFO] [stderr]     Checking aligned v0.3.5
[INFO] [stdout] warning: unexpected `cfg` condition value: `critical-section`
[INFO] [stdout]  --> src/lib.rs:2:42742
[INFO] [stdout]   |
[INFO] [stdout] 2 | ...= r" Returns all the peripherals *once*."] # [cfg (feature = "critical-section")] # [inline] pub fn take () -> Option < Self > { c...
[INFO] [stdout]   |                                                       ^^^^^^^^^^^^^^^^^^^^^^^^^^^^
[INFO] [stdout]   |
[INFO] [stdout]   = note: expected values for `feature` are: `cortex-m-rt` and `rt`
[INFO] [stdout]   = help: consider adding `critical-section` as a feature in `Cargo.toml`
[INFO] [stdout]   = note: see <https://doc.rust-lang.org/nightly/rustc/check-cfg/cargo-specifics.html> for more information about checking conditional configuration
[INFO] [stdout]   = note: `#[warn(unexpected_cfgs)]` on by default
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: unexpected `cfg` condition value: `critical-section`
[INFO] [stdout]  --> src/lib.rs:2:42742
[INFO] [stdout]   |
[INFO] [stdout] 2 | ...= r" Returns all the peripherals *once*."] # [cfg (feature = "critical-section")] # [inline] pub fn take () -> Option < Self > { c...
[INFO] [stdout]   |                                                       ^^^^^^^^^^^^^^^^^^^^^^^^^^^^
[INFO] [stdout]   |
[INFO] [stdout]   = note: expected values for `feature` are: `cortex-m-rt` and `rt`
[INFO] [stdout]   = help: consider adding `critical-section` as a feature in `Cargo.toml`
[INFO] [stdout]   = note: see <https://doc.rust-lang.org/nightly/rustc/check-cfg/cargo-specifics.html> for more information about checking conditional configuration
[INFO] [stdout]   = note: `#[warn(unexpected_cfgs)]` on by default
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing
[INFO] [stdout]  --> src/uart0/pwren.rs:1:2941
[INFO] [stdout]   |
[INFO] [stdout] 1 | ...e] pub fn pwren_enable (& mut self) -> PWREN_ENABLE_W < PWREN_SPEC , 0 > { PWREN_ENABLE_W :: new (self) } # [doc = "Bits 24:31 - K...
[INFO] [stdout]   |                            ^^^^^^^^^^     ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here
[INFO] [stdout]   |                            |
[INFO] [stdout]   |                            the lifetime is elided here
[INFO] [stdout]   |
[INFO] [stdout]   = help: the same lifetime is referred to in inconsistent ways, making the signature confusing
[INFO] [stdout]   = note: `#[warn(mismatched_lifetime_syntaxes)]` on by default
[INFO] [stdout] help: use `'_` for type paths
[INFO] [stdout]   |
[INFO] [stdout] 1 | # [doc = "Register `PWREN` reader"] pub type R = crate :: R < PWREN_SPEC > ; # [doc = "Register `PWREN` writer"] pub type W = crate :: W < PWREN_SPEC > ; # [doc = "Field `PWREN_ENABLE` reader - Enable the power"] pub type PWREN_ENABLE_R = crate :: BitReader < PWREN_ENABLE_A > ; # [doc = "Enable the power\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum PWREN_ENABLE_A { # [doc = "0: DISABLE"] PWREN_ENABLE_DISABLE = 0 , # [doc = "1: ENABLE"] PWREN_ENABLE_ENABLE = 1 , } impl From < PWREN_ENABLE_A > for bool { # [inline (always)] fn from (variant : PWREN_ENABLE_A) -> Self { variant as u8 != 0 } } impl PWREN_ENABLE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> PWREN_ENABLE_A { match self . bits { false => PWREN_ENABLE_A :: PWREN_ENABLE_DISABLE , true => PWREN_ENABLE_A :: PWREN_ENABLE_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_pwren_enable_disable (& self) -> bool { * self == PWREN_ENABLE_A :: PWREN_ENABLE_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_pwren_enable_enable (& self) -> bool { * self == PWREN_ENABLE_A :: PWREN_ENABLE_ENABLE } } # [doc = "Field `PWREN_ENABLE` writer - Enable the power"] pub type PWREN_ENABLE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , PWREN_ENABLE_A > ; impl < 'a , REG , const O : u8 > PWREN_ENABLE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn pwren_enable_disable (self) -> & 'a mut crate :: W < REG > { self . variant (PWREN_ENABLE_A :: PWREN_ENABLE_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn pwren_enable_enable (self) -> & 'a mut crate :: W < REG > { self . variant (PWREN_ENABLE_A :: PWREN_ENABLE_ENABLE) } } # [doc = "KEY to allow Power State Change\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum PWREN_KEY_AW { # [doc = "38: _TO_UNLOCK_W_"] PWREN_KEY_UNLOCK_W = 38 , } impl From < PWREN_KEY_AW > for u8 { # [inline (always)] fn from (variant : PWREN_KEY_AW) -> Self { variant as _ } } impl crate :: FieldSpec for PWREN_KEY_AW { type Ux = u8 ; } # [doc = "Field `PWREN_KEY` writer - KEY to allow Power State Change"] pub type PWREN_KEY_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 8 , O , PWREN_KEY_AW > ; impl < 'a , REG , const O : u8 > PWREN_KEY_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "_TO_UNLOCK_W_"] # [inline (always)] pub fn pwren_key_unlock_w (self) -> & 'a mut crate :: W < REG > { self . variant (PWREN_KEY_AW :: PWREN_KEY_UNLOCK_W) } } impl R { # [doc = "Bit 0 - Enable the power"] # [inline (always)] pub fn pwren_enable (& self) -> PWREN_ENABLE_R { PWREN_ENABLE_R :: new ((self . bits & 1) != 0) } } impl W { # [doc = "Bit 0 - Enable the power"] # [inline (always)] # [must_use] pub fn pwren_enable (& mut self) -> PWREN_ENABLE_W <'_,  PWREN_SPEC , 0 > { PWREN_ENABLE_W :: new (self) } # [doc = "Bits 24:31 - KEY to allow Power State Change"] # [inline (always)] # [must_use] pub fn pwren_key (& mut self) -> PWREN_KEY_W < PWREN_SPEC , 24 > { PWREN_KEY_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Power enable\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pwren::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pwren::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PWREN_SPEC ; impl crate :: RegisterSpec for PWREN_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`pwren::R`](R) reader structure"] impl crate :: Readable for PWREN_SPEC { } # [doc = "`write(|w| ..)` method takes [`pwren::W`](W) writer structure"] impl crate :: Writable for PWREN_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets PWREN to value 0"] impl crate :: Resettable for PWREN_SPEC { const RESET_VALUE : Self :: Ux = 0 ; }
[INFO] [stdout]   |                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                            +++
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing
[INFO] [stdout]  --> src/uart0/pwren.rs:1:3131
[INFO] [stdout]   |
[INFO] [stdout] 1 | ...t_use] pub fn pwren_key (& mut self) -> PWREN_KEY_W < PWREN_SPEC , 24 > { PWREN_KEY_W :: new (self) } # [doc = r" Writes raw bits ...
[INFO] [stdout]   |                             ^^^^^^^^^^     ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here
[INFO] [stdout]   |                             |
[INFO] [stdout]   |                             the lifetime is elided here
[INFO] [stdout]   |
[INFO] [stdout]   = help: the same lifetime is referred to in inconsistent ways, making the signature confusing
[INFO] [stdout] help: use `'_` for type paths
[INFO] [stdout]   |
[INFO] [stdout] 1 | # [doc = "Register `PWREN` reader"] pub type R = crate :: R < PWREN_SPEC > ; # [doc = "Register `PWREN` writer"] pub type W = crate :: W < PWREN_SPEC > ; # [doc = "Field `PWREN_ENABLE` reader - Enable the power"] pub type PWREN_ENABLE_R = crate :: BitReader < PWREN_ENABLE_A > ; # [doc = "Enable the power\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum PWREN_ENABLE_A { # [doc = "0: DISABLE"] PWREN_ENABLE_DISABLE = 0 , # [doc = "1: ENABLE"] PWREN_ENABLE_ENABLE = 1 , } impl From < PWREN_ENABLE_A > for bool { # [inline (always)] fn from (variant : PWREN_ENABLE_A) -> Self { variant as u8 != 0 } } impl PWREN_ENABLE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> PWREN_ENABLE_A { match self . bits { false => PWREN_ENABLE_A :: PWREN_ENABLE_DISABLE , true => PWREN_ENABLE_A :: PWREN_ENABLE_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_pwren_enable_disable (& self) -> bool { * self == PWREN_ENABLE_A :: PWREN_ENABLE_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_pwren_enable_enable (& self) -> bool { * self == PWREN_ENABLE_A :: PWREN_ENABLE_ENABLE } } # [doc = "Field `PWREN_ENABLE` writer - Enable the power"] pub type PWREN_ENABLE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , PWREN_ENABLE_A > ; impl < 'a , REG , const O : u8 > PWREN_ENABLE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn pwren_enable_disable (self) -> & 'a mut crate :: W < REG > { self . variant (PWREN_ENABLE_A :: PWREN_ENABLE_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn pwren_enable_enable (self) -> & 'a mut crate :: W < REG > { self . variant (PWREN_ENABLE_A :: PWREN_ENABLE_ENABLE) } } # [doc = "KEY to allow Power State Change\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum PWREN_KEY_AW { # [doc = "38: _TO_UNLOCK_W_"] PWREN_KEY_UNLOCK_W = 38 , } impl From < PWREN_KEY_AW > for u8 { # [inline (always)] fn from (variant : PWREN_KEY_AW) -> Self { variant as _ } } impl crate :: FieldSpec for PWREN_KEY_AW { type Ux = u8 ; } # [doc = "Field `PWREN_KEY` writer - KEY to allow Power State Change"] pub type PWREN_KEY_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 8 , O , PWREN_KEY_AW > ; impl < 'a , REG , const O : u8 > PWREN_KEY_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "_TO_UNLOCK_W_"] # [inline (always)] pub fn pwren_key_unlock_w (self) -> & 'a mut crate :: W < REG > { self . variant (PWREN_KEY_AW :: PWREN_KEY_UNLOCK_W) } } impl R { # [doc = "Bit 0 - Enable the power"] # [inline (always)] pub fn pwren_enable (& self) -> PWREN_ENABLE_R { PWREN_ENABLE_R :: new ((self . bits & 1) != 0) } } impl W { # [doc = "Bit 0 - Enable the power"] # [inline (always)] # [must_use] pub fn pwren_enable (& mut self) -> PWREN_ENABLE_W < PWREN_SPEC , 0 > { PWREN_ENABLE_W :: new (self) } # [doc = "Bits 24:31 - KEY to allow Power State Change"] # [inline (always)] # [must_use] pub fn pwren_key (& mut self) -> PWREN_KEY_W <'_,  PWREN_SPEC , 24 > { PWREN_KEY_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Power enable\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pwren::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pwren::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PWREN_SPEC ; impl crate :: RegisterSpec for PWREN_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`pwren::R`](R) reader structure"] impl crate :: Readable for PWREN_SPEC { } # [doc = "`write(|w| ..)` method takes [`pwren::W`](W) writer structure"] impl crate :: Writable for PWREN_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets PWREN to value 0"] impl crate :: Resettable for PWREN_SPEC { const RESET_VALUE : Self :: Ux = 0 ; }
[INFO] [stdout]   |                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                       +++
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing
[INFO] [stdout]  --> src/uart0/rstctl.rs:1:3243
[INFO] [stdout]   |
[INFO] [stdout] 1 | ... rstctl_resetassert (& mut self) -> RSTCTL_RESETASSERT_W < RSTCTL_SPEC , 0 > { RSTCTL_RESETASSERT_W :: new (self) } # [doc = "Bit ...
[INFO] [stdout]   |                         ^^^^^^^^^^     ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here
[INFO] [stdout]   |                         |
[INFO] [stdout]   |                         the lifetime is elided here
[INFO] [stdout]   |
[INFO] [stdout]   = help: the same lifetime is referred to in inconsistent ways, making the signature confusing
[INFO] [stdout] help: use `'_` for type paths
[INFO] [stdout]   |
[INFO] [stdout] 1 | # [doc = "Register `RSTCTL` writer"] pub type W = crate :: W < RSTCTL_SPEC > ; # [doc = "Assert reset to the peripheral\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum RSTCTL_RESETASSERT_AW { # [doc = "0: NOP"] RSTCTL_RESETASSERT_NOP = 0 , # [doc = "1: ASSERT"] RSTCTL_RESETASSERT_ASSERT = 1 , } impl From < RSTCTL_RESETASSERT_AW > for bool { # [inline (always)] fn from (variant : RSTCTL_RESETASSERT_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `RSTCTL_RESETASSERT` writer - Assert reset to the peripheral"] pub type RSTCTL_RESETASSERT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , RSTCTL_RESETASSERT_AW > ; impl < 'a , REG , const O : u8 > RSTCTL_RESETASSERT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NOP"] # [inline (always)] pub fn rstctl_resetassert_nop (self) -> & 'a mut crate :: W < REG > { self . variant (RSTCTL_RESETASSERT_AW :: RSTCTL_RESETASSERT_NOP) } # [doc = "ASSERT"] # [inline (always)] pub fn rstctl_resetassert_assert (self) -> & 'a mut crate :: W < REG > { self . variant (RSTCTL_RESETASSERT_AW :: RSTCTL_RESETASSERT_ASSERT) } } # [doc = "Clear the RESETSTKY bit in the STAT register\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum RSTCTL_RESETSTKYCLR_AW { # [doc = "0: NOP"] RSTCTL_RESETSTKYCLR_NOP = 0 , # [doc = "1: CLR"] RSTCTL_RESETSTKYCLR_CLR = 1 , } impl From < RSTCTL_RESETSTKYCLR_AW > for bool { # [inline (always)] fn from (variant : RSTCTL_RESETSTKYCLR_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `RSTCTL_RESETSTKYCLR` writer - Clear the RESETSTKY bit in the STAT register"] pub type RSTCTL_RESETSTKYCLR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , RSTCTL_RESETSTKYCLR_AW > ; impl < 'a , REG , const O : u8 > RSTCTL_RESETSTKYCLR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NOP"] # [inline (always)] pub fn rstctl_resetstkyclr_nop (self) -> & 'a mut crate :: W < REG > { self . variant (RSTCTL_RESETSTKYCLR_AW :: RSTCTL_RESETSTKYCLR_NOP) } # [doc = "CLR"] # [inline (always)] pub fn rstctl_resetstkyclr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (RSTCTL_RESETSTKYCLR_AW :: RSTCTL_RESETSTKYCLR_CLR) } } # [doc = "Unlock key\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum RSTCTL_KEY_AW { # [doc = "177: _TO_UNLOCK_W_"] RSTCTL_KEY_UNLOCK_W = 177 , } impl From < RSTCTL_KEY_AW > for u8 { # [inline (always)] fn from (variant : RSTCTL_KEY_AW) -> Self { variant as _ } } impl crate :: FieldSpec for RSTCTL_KEY_AW { type Ux = u8 ; } # [doc = "Field `RSTCTL_KEY` writer - Unlock key"] pub type RSTCTL_KEY_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 8 , O , RSTCTL_KEY_AW > ; impl < 'a , REG , const O : u8 > RSTCTL_KEY_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "_TO_UNLOCK_W_"] # [inline (always)] pub fn rstctl_key_unlock_w (self) -> & 'a mut crate :: W < REG > { self . variant (RSTCTL_KEY_AW :: RSTCTL_KEY_UNLOCK_W) } } impl W { # [doc = "Bit 0 - Assert reset to the peripheral"] # [inline (always)] # [must_use] pub fn rstctl_resetassert (& mut self) -> RSTCTL_RESETASSERT_W <'_,  RSTCTL_SPEC , 0 > { RSTCTL_RESETASSERT_W :: new (self) } # [doc = "Bit 1 - Clear the RESETSTKY bit in the STAT register"] # [inline (always)] # [must_use] pub fn rstctl_resetstkyclr (& mut self) -> RSTCTL_RESETSTKYCLR_W < RSTCTL_SPEC , 1 > { RSTCTL_RESETSTKYCLR_W :: new (self) } # [doc = "Bits 24:31 - Unlock key"] # [inline (always)] # [must_use] pub fn rstctl_key (& mut self) -> RSTCTL_KEY_W < RSTCTL_SPEC , 24 > { RSTCTL_KEY_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Reset Control\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rstctl::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct RSTCTL_SPEC ; impl crate :: RegisterSpec for RSTCTL_SPEC { type Ux = u32 ; } # [doc = "`write(|w| ..)` method takes [`rstctl::W`](W) writer structure"] impl crate :: Writable for RSTCTL_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets RSTCTL to value 0"] impl crate :: Resettable for RSTCTL_SPEC { const RESET_VALUE : Self :: Ux = 0 ; }
[INFO] [stdout]   |                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                +++
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing
[INFO] [stdout]  --> src/uart0/rstctl.rs:1:3464
[INFO] [stdout]   |
[INFO] [stdout] 1 | ...stctl_resetstkyclr (& mut self) -> RSTCTL_RESETSTKYCLR_W < RSTCTL_SPEC , 1 > { RSTCTL_RESETSTKYCLR_W :: new (self) } # [doc = "Bit...
[INFO] [stdout]   |                        ^^^^^^^^^^     ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here
[INFO] [stdout]   |                        |
[INFO] [stdout]   |                        the lifetime is elided here
[INFO] [stdout]   |
[INFO] [stdout]   = help: the same lifetime is referred to in inconsistent ways, making the signature confusing
[INFO] [stdout] help: use `'_` for type paths
[INFO] [stdout]   |
[INFO] [stdout] 1 | # [doc = "Register `RSTCTL` writer"] pub type W = crate :: W < RSTCTL_SPEC > ; # [doc = "Assert reset to the peripheral\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum RSTCTL_RESETASSERT_AW { # [doc = "0: NOP"] RSTCTL_RESETASSERT_NOP = 0 , # [doc = "1: ASSERT"] RSTCTL_RESETASSERT_ASSERT = 1 , } impl From < RSTCTL_RESETASSERT_AW > for bool { # [inline (always)] fn from (variant : RSTCTL_RESETASSERT_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `RSTCTL_RESETASSERT` writer - Assert reset to the peripheral"] pub type RSTCTL_RESETASSERT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , RSTCTL_RESETASSERT_AW > ; impl < 'a , REG , const O : u8 > RSTCTL_RESETASSERT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NOP"] # [inline (always)] pub fn rstctl_resetassert_nop (self) -> & 'a mut crate :: W < REG > { self . variant (RSTCTL_RESETASSERT_AW :: RSTCTL_RESETASSERT_NOP) } # [doc = "ASSERT"] # [inline (always)] pub fn rstctl_resetassert_assert (self) -> & 'a mut crate :: W < REG > { self . variant (RSTCTL_RESETASSERT_AW :: RSTCTL_RESETASSERT_ASSERT) } } # [doc = "Clear the RESETSTKY bit in the STAT register\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum RSTCTL_RESETSTKYCLR_AW { # [doc = "0: NOP"] RSTCTL_RESETSTKYCLR_NOP = 0 , # [doc = "1: CLR"] RSTCTL_RESETSTKYCLR_CLR = 1 , } impl From < RSTCTL_RESETSTKYCLR_AW > for bool { # [inline (always)] fn from (variant : RSTCTL_RESETSTKYCLR_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `RSTCTL_RESETSTKYCLR` writer - Clear the RESETSTKY bit in the STAT register"] pub type RSTCTL_RESETSTKYCLR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , RSTCTL_RESETSTKYCLR_AW > ; impl < 'a , REG , const O : u8 > RSTCTL_RESETSTKYCLR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NOP"] # [inline (always)] pub fn rstctl_resetstkyclr_nop (self) -> & 'a mut crate :: W < REG > { self . variant (RSTCTL_RESETSTKYCLR_AW :: RSTCTL_RESETSTKYCLR_NOP) } # [doc = "CLR"] # [inline (always)] pub fn rstctl_resetstkyclr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (RSTCTL_RESETSTKYCLR_AW :: RSTCTL_RESETSTKYCLR_CLR) } } # [doc = "Unlock key\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum RSTCTL_KEY_AW { # [doc = "177: _TO_UNLOCK_W_"] RSTCTL_KEY_UNLOCK_W = 177 , } impl From < RSTCTL_KEY_AW > for u8 { # [inline (always)] fn from (variant : RSTCTL_KEY_AW) -> Self { variant as _ } } impl crate :: FieldSpec for RSTCTL_KEY_AW { type Ux = u8 ; } # [doc = "Field `RSTCTL_KEY` writer - Unlock key"] pub type RSTCTL_KEY_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 8 , O , RSTCTL_KEY_AW > ; impl < 'a , REG , const O : u8 > RSTCTL_KEY_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "_TO_UNLOCK_W_"] # [inline (always)] pub fn rstctl_key_unlock_w (self) -> & 'a mut crate :: W < REG > { self . variant (RSTCTL_KEY_AW :: RSTCTL_KEY_UNLOCK_W) } } impl W { # [doc = "Bit 0 - Assert reset to the peripheral"] # [inline (always)] # [must_use] pub fn rstctl_resetassert (& mut self) -> RSTCTL_RESETASSERT_W < RSTCTL_SPEC , 0 > { RSTCTL_RESETASSERT_W :: new (self) } # [doc = "Bit 1 - Clear the RESETSTKY bit in the STAT register"] # [inline (always)] # [must_use] pub fn rstctl_resetstkyclr (& mut self) -> RSTCTL_RESETSTKYCLR_W <'_,  RSTCTL_SPEC , 1 > { RSTCTL_RESETSTKYCLR_W :: new (self) } # [doc = "Bits 24:31 - Unlock key"] # [inline (always)] # [must_use] pub fn rstctl_key (& mut self) -> RSTCTL_KEY_W < RSTCTL_SPEC , 24 > { RSTCTL_KEY_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Reset Control\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rstctl::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct RSTCTL_SPEC ; impl crate :: RegisterSpec for RSTCTL_SPEC { type Ux = u32 ; } # [doc = "`write(|w| ..)` method takes [`rstctl::W`](W) writer structure"] impl crate :: Writable for RSTCTL_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets RSTCTL to value 0"] impl crate :: Resettable for RSTCTL_SPEC { const RESET_VALUE : Self :: Ux = 0 ; }
[INFO] [stdout]   |                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                              +++
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing
[INFO] [stdout]  --> src/uart0/rstctl.rs:1:3649
[INFO] [stdout]   |
[INFO] [stdout] 1 | ...use] pub fn rstctl_key (& mut self) -> RSTCTL_KEY_W < RSTCTL_SPEC , 24 > { RSTCTL_KEY_W :: new (self) } # [doc = r" Writes raw bit...
[INFO] [stdout]   |                            ^^^^^^^^^^     ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here
[INFO] [stdout]   |                            |
[INFO] [stdout]   |                            the lifetime is elided here
[INFO] [stdout]   |
[INFO] [stdout]   = help: the same lifetime is referred to in inconsistent ways, making the signature confusing
[INFO] [stdout] help: use `'_` for type paths
[INFO] [stdout]   |
[INFO] [stdout] 1 | # [doc = "Register `RSTCTL` writer"] pub type W = crate :: W < RSTCTL_SPEC > ; # [doc = "Assert reset to the peripheral\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum RSTCTL_RESETASSERT_AW { # [doc = "0: NOP"] RSTCTL_RESETASSERT_NOP = 0 , # [doc = "1: ASSERT"] RSTCTL_RESETASSERT_ASSERT = 1 , } impl From < RSTCTL_RESETASSERT_AW > for bool { # [inline (always)] fn from (variant : RSTCTL_RESETASSERT_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `RSTCTL_RESETASSERT` writer - Assert reset to the peripheral"] pub type RSTCTL_RESETASSERT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , RSTCTL_RESETASSERT_AW > ; impl < 'a , REG , const O : u8 > RSTCTL_RESETASSERT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NOP"] # [inline (always)] pub fn rstctl_resetassert_nop (self) -> & 'a mut crate :: W < REG > { self . variant (RSTCTL_RESETASSERT_AW :: RSTCTL_RESETASSERT_NOP) } # [doc = "ASSERT"] # [inline (always)] pub fn rstctl_resetassert_assert (self) -> & 'a mut crate :: W < REG > { self . variant (RSTCTL_RESETASSERT_AW :: RSTCTL_RESETASSERT_ASSERT) } } # [doc = "Clear the RESETSTKY bit in the STAT register\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum RSTCTL_RESETSTKYCLR_AW { # [doc = "0: NOP"] RSTCTL_RESETSTKYCLR_NOP = 0 , # [doc = "1: CLR"] RSTCTL_RESETSTKYCLR_CLR = 1 , } impl From < RSTCTL_RESETSTKYCLR_AW > for bool { # [inline (always)] fn from (variant : RSTCTL_RESETSTKYCLR_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `RSTCTL_RESETSTKYCLR` writer - Clear the RESETSTKY bit in the STAT register"] pub type RSTCTL_RESETSTKYCLR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , RSTCTL_RESETSTKYCLR_AW > ; impl < 'a , REG , const O : u8 > RSTCTL_RESETSTKYCLR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NOP"] # [inline (always)] pub fn rstctl_resetstkyclr_nop (self) -> & 'a mut crate :: W < REG > { self . variant (RSTCTL_RESETSTKYCLR_AW :: RSTCTL_RESETSTKYCLR_NOP) } # [doc = "CLR"] # [inline (always)] pub fn rstctl_resetstkyclr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (RSTCTL_RESETSTKYCLR_AW :: RSTCTL_RESETSTKYCLR_CLR) } } # [doc = "Unlock key\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum RSTCTL_KEY_AW { # [doc = "177: _TO_UNLOCK_W_"] RSTCTL_KEY_UNLOCK_W = 177 , } impl From < RSTCTL_KEY_AW > for u8 { # [inline (always)] fn from (variant : RSTCTL_KEY_AW) -> Self { variant as _ } } impl crate :: FieldSpec for RSTCTL_KEY_AW { type Ux = u8 ; } # [doc = "Field `RSTCTL_KEY` writer - Unlock key"] pub type RSTCTL_KEY_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 8 , O , RSTCTL_KEY_AW > ; impl < 'a , REG , const O : u8 > RSTCTL_KEY_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "_TO_UNLOCK_W_"] # [inline (always)] pub fn rstctl_key_unlock_w (self) -> & 'a mut crate :: W < REG > { self . variant (RSTCTL_KEY_AW :: RSTCTL_KEY_UNLOCK_W) } } impl W { # [doc = "Bit 0 - Assert reset to the peripheral"] # [inline (always)] # [must_use] pub fn rstctl_resetassert (& mut self) -> RSTCTL_RESETASSERT_W < RSTCTL_SPEC , 0 > { RSTCTL_RESETASSERT_W :: new (self) } # [doc = "Bit 1 - Clear the RESETSTKY bit in the STAT register"] # [inline (always)] # [must_use] pub fn rstctl_resetstkyclr (& mut self) -> RSTCTL_RESETSTKYCLR_W < RSTCTL_SPEC , 1 > { RSTCTL_RESETSTKYCLR_W :: new (self) } # [doc = "Bits 24:31 - Unlock key"] # [inline (always)] # [must_use] pub fn rstctl_key (& mut self) -> RSTCTL_KEY_W <'_,  RSTCTL_SPEC , 24 > { RSTCTL_KEY_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Reset Control\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rstctl::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct RSTCTL_SPEC ; impl crate :: RegisterSpec for RSTCTL_SPEC { type Ux = u32 ; } # [doc = "`write(|w| ..)` method takes [`rstctl::W`](W) writer structure"] impl crate :: Writable for RSTCTL_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets RSTCTL to value 0"] impl crate :: Resettable for RSTCTL_SPEC { const RESET_VALUE : Self :: Ux = 0 ; }
[INFO] [stdout]   |                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                              +++
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing
[INFO] [stdout]  --> src/uart0/clkcfg.rs:1:3453
[INFO] [stdout]   |
[INFO] [stdout] 1 | ...n clkcfg_blockasync (& mut self) -> CLKCFG_BLOCKASYNC_W < CLKCFG_SPEC , 8 > { CLKCFG_BLOCKASYNC_W :: new (self) } # [doc = "Bits 2...
[INFO] [stdout]   |                         ^^^^^^^^^^     ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here
[INFO] [stdout]   |                         |
[INFO] [stdout]   |                         the lifetime is elided here
[INFO] [stdout]   |
[INFO] [stdout]   = help: the same lifetime is referred to in inconsistent ways, making the signature confusing
[INFO] [stdout] help: use `'_` for type paths
[INFO] [stdout]   |
[INFO] [stdout] 1 | # [doc = "Register `CLKCFG` reader"] pub type R = crate :: R < CLKCFG_SPEC > ; # [doc = "Register `CLKCFG` writer"] pub type W = crate :: W < CLKCFG_SPEC > ; # [doc = "Field `CLKCFG_BLOCKASYNC` reader - Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz"] pub type CLKCFG_BLOCKASYNC_R = crate :: BitReader < CLKCFG_BLOCKASYNC_A > ; # [doc = "Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CLKCFG_BLOCKASYNC_A { # [doc = "0: DISABLE"] CLKCFG_BLOCKASYNC_DISABLE = 0 , # [doc = "1: ENABLE"] CLKCFG_BLOCKASYNC_ENABLE = 1 , } impl From < CLKCFG_BLOCKASYNC_A > for bool { # [inline (always)] fn from (variant : CLKCFG_BLOCKASYNC_A) -> Self { variant as u8 != 0 } } impl CLKCFG_BLOCKASYNC_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CLKCFG_BLOCKASYNC_A { match self . bits { false => CLKCFG_BLOCKASYNC_A :: CLKCFG_BLOCKASYNC_DISABLE , true => CLKCFG_BLOCKASYNC_A :: CLKCFG_BLOCKASYNC_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_clkcfg_blockasync_disable (& self) -> bool { * self == CLKCFG_BLOCKASYNC_A :: CLKCFG_BLOCKASYNC_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_clkcfg_blockasync_enable (& self) -> bool { * self == CLKCFG_BLOCKASYNC_A :: CLKCFG_BLOCKASYNC_ENABLE } } # [doc = "Field `CLKCFG_BLOCKASYNC` writer - Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz"] pub type CLKCFG_BLOCKASYNC_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CLKCFG_BLOCKASYNC_A > ; impl < 'a , REG , const O : u8 > CLKCFG_BLOCKASYNC_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn clkcfg_blockasync_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CLKCFG_BLOCKASYNC_A :: CLKCFG_BLOCKASYNC_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn clkcfg_blockasync_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CLKCFG_BLOCKASYNC_A :: CLKCFG_BLOCKASYNC_ENABLE) } } # [doc = "KEY to Allow State Change -- 0xA9\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum CLKCFG_KEY_AW { # [doc = "169: _UNLOCK_W_"] CLKCFG_KEY_UNLOCK = 169 , } impl From < CLKCFG_KEY_AW > for u8 { # [inline (always)] fn from (variant : CLKCFG_KEY_AW) -> Self { variant as _ } } impl crate :: FieldSpec for CLKCFG_KEY_AW { type Ux = u8 ; } # [doc = "Field `CLKCFG_KEY` writer - KEY to Allow State Change -- 0xA9"] pub type CLKCFG_KEY_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 8 , O , CLKCFG_KEY_AW > ; impl < 'a , REG , const O : u8 > CLKCFG_KEY_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "_UNLOCK_W_"] # [inline (always)] pub fn clkcfg_key_unlock (self) -> & 'a mut crate :: W < REG > { self . variant (CLKCFG_KEY_AW :: CLKCFG_KEY_UNLOCK) } } impl R { # [doc = "Bit 8 - Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz"] # [inline (always)] pub fn clkcfg_blockasync (& self) -> CLKCFG_BLOCKASYNC_R { CLKCFG_BLOCKASYNC_R :: new (((self . bits >> 8) & 1) != 0) } } impl W { # [doc = "Bit 8 - Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz"] # [inline (always)] # [must_use] pub fn clkcfg_blockasync (& mut self) -> CLKCFG_BLOCKASYNC_W <'_,  CLKCFG_SPEC , 8 > { CLKCFG_BLOCKASYNC_W :: new (self) } # [doc = "Bits 24:31 - KEY to Allow State Change -- 0xA9"] # [inline (always)] # [must_use] pub fn clkcfg_key (& mut self) -> CLKCFG_KEY_W < CLKCFG_SPEC , 24 > { CLKCFG_KEY_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Peripheral Clock Configuration Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clkcfg::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clkcfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CLKCFG_SPEC ; impl crate :: RegisterSpec for CLKCFG_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`clkcfg::R`](R) reader structure"] impl crate :: Readable for CLKCFG_SPEC { } # [doc = "`write(|w| ..)` method takes [`clkcfg::W`](W) writer structure"] impl crate :: Writable for CLKCFG_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets CLKCFG to value 0"] impl crate :: Resettable for CLKCFG_SPEC { const RESET_VALUE : Self :: Ux = 0 ; }
[INFO] [stdout]   |                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                 +++
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing
[INFO] [stdout]  --> src/uart0/clkcfg.rs:1:3657
[INFO] [stdout]   |
[INFO] [stdout] 1 | ...use] pub fn clkcfg_key (& mut self) -> CLKCFG_KEY_W < CLKCFG_SPEC , 24 > { CLKCFG_KEY_W :: new (self) } # [doc = r" Writes raw bit...
[INFO] [stdout]   |                            ^^^^^^^^^^     ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here
[INFO] [stdout]   |                            |
[INFO] [stdout]   |                            the lifetime is elided here
[INFO] [stdout]   |
[INFO] [stdout]   = help: the same lifetime is referred to in inconsistent ways, making the signature confusing
[INFO] [stdout] help: use `'_` for type paths
[INFO] [stdout]   |
[INFO] [stdout] 1 | # [doc = "Register `CLKCFG` reader"] pub type R = crate :: R < CLKCFG_SPEC > ; # [doc = "Register `CLKCFG` writer"] pub type W = crate :: W < CLKCFG_SPEC > ; # [doc = "Field `CLKCFG_BLOCKASYNC` reader - Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz"] pub type CLKCFG_BLOCKASYNC_R = crate :: BitReader < CLKCFG_BLOCKASYNC_A > ; # [doc = "Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CLKCFG_BLOCKASYNC_A { # [doc = "0: DISABLE"] CLKCFG_BLOCKASYNC_DISABLE = 0 , # [doc = "1: ENABLE"] CLKCFG_BLOCKASYNC_ENABLE = 1 , } impl From < CLKCFG_BLOCKASYNC_A > for bool { # [inline (always)] fn from (variant : CLKCFG_BLOCKASYNC_A) -> Self { variant as u8 != 0 } } impl CLKCFG_BLOCKASYNC_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CLKCFG_BLOCKASYNC_A { match self . bits { false => CLKCFG_BLOCKASYNC_A :: CLKCFG_BLOCKASYNC_DISABLE , true => CLKCFG_BLOCKASYNC_A :: CLKCFG_BLOCKASYNC_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_clkcfg_blockasync_disable (& self) -> bool { * self == CLKCFG_BLOCKASYNC_A :: CLKCFG_BLOCKASYNC_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_clkcfg_blockasync_enable (& self) -> bool { * self == CLKCFG_BLOCKASYNC_A :: CLKCFG_BLOCKASYNC_ENABLE } } # [doc = "Field `CLKCFG_BLOCKASYNC` writer - Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz"] pub type CLKCFG_BLOCKASYNC_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CLKCFG_BLOCKASYNC_A > ; impl < 'a , REG , const O : u8 > CLKCFG_BLOCKASYNC_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn clkcfg_blockasync_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CLKCFG_BLOCKASYNC_A :: CLKCFG_BLOCKASYNC_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn clkcfg_blockasync_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CLKCFG_BLOCKASYNC_A :: CLKCFG_BLOCKASYNC_ENABLE) } } # [doc = "KEY to Allow State Change -- 0xA9\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum CLKCFG_KEY_AW { # [doc = "169: _UNLOCK_W_"] CLKCFG_KEY_UNLOCK = 169 , } impl From < CLKCFG_KEY_AW > for u8 { # [inline (always)] fn from (variant : CLKCFG_KEY_AW) -> Self { variant as _ } } impl crate :: FieldSpec for CLKCFG_KEY_AW { type Ux = u8 ; } # [doc = "Field `CLKCFG_KEY` writer - KEY to Allow State Change -- 0xA9"] pub type CLKCFG_KEY_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 8 , O , CLKCFG_KEY_AW > ; impl < 'a , REG , const O : u8 > CLKCFG_KEY_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "_UNLOCK_W_"] # [inline (always)] pub fn clkcfg_key_unlock (self) -> & 'a mut crate :: W < REG > { self . variant (CLKCFG_KEY_AW :: CLKCFG_KEY_UNLOCK) } } impl R { # [doc = "Bit 8 - Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz"] # [inline (always)] pub fn clkcfg_blockasync (& self) -> CLKCFG_BLOCKASYNC_R { CLKCFG_BLOCKASYNC_R :: new (((self . bits >> 8) & 1) != 0) } } impl W { # [doc = "Bit 8 - Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz"] # [inline (always)] # [must_use] pub fn clkcfg_blockasync (& mut self) -> CLKCFG_BLOCKASYNC_W < CLKCFG_SPEC , 8 > { CLKCFG_BLOCKASYNC_W :: new (self) } # [doc = "Bits 24:31 - KEY to Allow State Change -- 0xA9"] # [inline (always)] # [must_use] pub fn clkcfg_key (& mut self) -> CLKCFG_KEY_W <'_,  CLKCFG_SPEC , 24 > { CLKCFG_KEY_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Peripheral Clock Configuration Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clkcfg::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clkcfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CLKCFG_SPEC ; impl crate :: RegisterSpec for CLKCFG_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`clkcfg::R`](R) reader structure"] impl crate :: Readable for CLKCFG_SPEC { } # [doc = "`write(|w| ..)` method takes [`clkcfg::W`](W) writer structure"] impl crate :: Writable for CLKCFG_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets CLKCFG to value 0"] impl crate :: Resettable for CLKCFG_SPEC { const RESET_VALUE : Self :: Ux = 0 ; }
[INFO] [stdout]   |                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                      +++
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing
[INFO] [stdout]  --> src/uart0/clkdiv.rs:1:4791
[INFO] [stdout]   |
[INFO] [stdout] 1 | ...e] pub fn clkdiv_ratio (& mut self) -> CLKDIV_RATIO_W < CLKDIV_SPEC , 0 > { CLKDIV_RATIO_W :: new (self) } # [doc = r" Writes raw ...
[INFO] [stdout]   |                            ^^^^^^^^^^     ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here
[INFO] [stdout]   |                            |
[INFO] [stdout]   |                            the lifetime is elided here
[INFO] [stdout]   |
[INFO] [stdout]   = help: the same lifetime is referred to in inconsistent ways, making the signature confusing
[INFO] [stdout] help: use `'_` for type paths
[INFO] [stdout]   |
[INFO] [stdout] 1 | # [doc = "Register `CLKDIV` reader"] pub type R = crate :: R < CLKDIV_SPEC > ; # [doc = "Register `CLKDIV` writer"] pub type W = crate :: W < CLKDIV_SPEC > ; # [doc = "Field `CLKDIV_RATIO` reader - Selects divide ratio of module clock"] pub type CLKDIV_RATIO_R = crate :: FieldReader < CLKDIV_RATIO_A > ; # [doc = "Selects divide ratio of module clock\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum CLKDIV_RATIO_A { # [doc = "0: DIV_BY_1"] CLKDIV_RATIO_DIV_BY_1 = 0 , # [doc = "1: DIV_BY_2"] CLKDIV_RATIO_DIV_BY_2 = 1 , # [doc = "2: DIV_BY_3"] CLKDIV_RATIO_DIV_BY_3 = 2 , # [doc = "3: DIV_BY_4"] CLKDIV_RATIO_DIV_BY_4 = 3 , # [doc = "4: DIV_BY_5"] CLKDIV_RATIO_DIV_BY_5 = 4 , # [doc = "5: DIV_BY_6"] CLKDIV_RATIO_DIV_BY_6 = 5 , # [doc = "6: DIV_BY_7"] CLKDIV_RATIO_DIV_BY_7 = 6 , # [doc = "7: DIV_BY_8"] CLKDIV_RATIO_DIV_BY_8 = 7 , } impl From < CLKDIV_RATIO_A > for u8 { # [inline (always)] fn from (variant : CLKDIV_RATIO_A) -> Self { variant as _ } } impl crate :: FieldSpec for CLKDIV_RATIO_A { type Ux = u8 ; } impl CLKDIV_RATIO_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CLKDIV_RATIO_A { match self . bits { 0 => CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_1 , 1 => CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_2 , 2 => CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_3 , 3 => CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_4 , 4 => CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_5 , 5 => CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_6 , 6 => CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_7 , 7 => CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_8 , _ => unreachable ! () , } } # [doc = "DIV_BY_1"] # [inline (always)] pub fn is_clkdiv_ratio_div_by_1 (& self) -> bool { * self == CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_1 } # [doc = "DIV_BY_2"] # [inline (always)] pub fn is_clkdiv_ratio_div_by_2 (& self) -> bool { * self == CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_2 } # [doc = "DIV_BY_3"] # [inline (always)] pub fn is_clkdiv_ratio_div_by_3 (& self) -> bool { * self == CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_3 } # [doc = "DIV_BY_4"] # [inline (always)] pub fn is_clkdiv_ratio_div_by_4 (& self) -> bool { * self == CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_4 } # [doc = "DIV_BY_5"] # [inline (always)] pub fn is_clkdiv_ratio_div_by_5 (& self) -> bool { * self == CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_5 } # [doc = "DIV_BY_6"] # [inline (always)] pub fn is_clkdiv_ratio_div_by_6 (& self) -> bool { * self == CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_6 } # [doc = "DIV_BY_7"] # [inline (always)] pub fn is_clkdiv_ratio_div_by_7 (& self) -> bool { * self == CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_7 } # [doc = "DIV_BY_8"] # [inline (always)] pub fn is_clkdiv_ratio_div_by_8 (& self) -> bool { * self == CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_8 } } # [doc = "Field `CLKDIV_RATIO` writer - Selects divide ratio of module clock"] pub type CLKDIV_RATIO_W < 'a , REG , const O : u8 > = crate :: FieldWriterSafe < 'a , REG , 3 , O , CLKDIV_RATIO_A > ; impl < 'a , REG , const O : u8 > CLKDIV_RATIO_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "DIV_BY_1"] # [inline (always)] pub fn clkdiv_ratio_div_by_1 (self) -> & 'a mut crate :: W < REG > { self . variant (CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_1) } # [doc = "DIV_BY_2"] # [inline (always)] pub fn clkdiv_ratio_div_by_2 (self) -> & 'a mut crate :: W < REG > { self . variant (CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_2) } # [doc = "DIV_BY_3"] # [inline (always)] pub fn clkdiv_ratio_div_by_3 (self) -> & 'a mut crate :: W < REG > { self . variant (CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_3) } # [doc = "DIV_BY_4"] # [inline (always)] pub fn clkdiv_ratio_div_by_4 (self) -> & 'a mut crate :: W < REG > { self . variant (CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_4) } # [doc = "DIV_BY_5"] # [inline (always)] pub fn clkdiv_ratio_div_by_5 (self) -> & 'a mut crate :: W < REG > { self . variant (CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_5) } # [doc = "DIV_BY_6"] # [inline (always)] pub fn clkdiv_ratio_div_by_6 (self) -> & 'a mut crate :: W < REG > { self . variant (CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_6) } # [doc = "DIV_BY_7"] # [inline (always)] pub fn clkdiv_ratio_div_by_7 (self) -> & 'a mut crate :: W < REG > { self . variant (CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_7) } # [doc = "DIV_BY_8"] # [inline (always)] pub fn clkdiv_ratio_div_by_8 (self) -> & 'a mut crate :: W < REG > { self . variant (CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_8) } } impl R { # [doc = "Bits 0:2 - Selects divide ratio of module clock"] # [inline (always)] pub fn clkdiv_ratio (& self) -> CLKDIV_RATIO_R { CLKDIV_RATIO_R :: new ((self . bits & 7) as u8) } } impl W { # [doc = "Bits 0:2 - Selects divide ratio of module clock"] # [inline (always)] # [must_use] pub fn clkdiv_ratio (& mut self) -> CLKDIV_RATIO_W <'_,  CLKDIV_SPEC , 0 > { CLKDIV_RATIO_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Clock Divider\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clkdiv::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clkdiv::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CLKDIV_SPEC ; impl crate :: RegisterSpec for CLKDIV_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`clkdiv::R`](R) reader structure"] impl crate :: Readable for CLKDIV_SPEC { } # [doc = "`write(|w| ..)` method takes [`clkdiv::W`](W) writer structure"] impl crate :: Writable for CLKDIV_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets CLKDIV to value 0"] impl crate :: Resettable for CLKDIV_SPEC { const RESET_VALUE : Self :: Ux = 0 ; }
[INFO] [stdout]   |                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                      +++
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing
[INFO] [stdout]  --> src/uart0/clksel.rs:1:6426
[INFO] [stdout]   |
[INFO] [stdout] 1 | ... fn clksel_lfclk_sel (& mut self) -> CLKSEL_LFCLK_SEL_W < CLKSEL_SPEC , 1 > { CLKSEL_LFCLK_SEL_W :: new (self) } # [doc = "Bit 2 -...
[INFO] [stdout]   |                          ^^^^^^^^^^     ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here
[INFO] [stdout]   |                          |
[INFO] [stdout]   |                          the lifetime is elided here
[INFO] [stdout]   |
[INFO] [stdout]   = help: the same lifetime is referred to in inconsistent ways, making the signature confusing
[INFO] [stdout] help: use `'_` for type paths
[INFO] [stdout]   |
[INFO] [stdout] 1 | # [doc = "Register `CLKSEL` reader"] pub type R = crate :: R < CLKSEL_SPEC > ; # [doc = "Register `CLKSEL` writer"] pub type W = crate :: W < CLKSEL_SPEC > ; # [doc = "Field `CLKSEL_LFCLK_SEL` reader - Selects LFCLK as clock source if enabled"] pub type CLKSEL_LFCLK_SEL_R = crate :: BitReader < CLKSEL_LFCLK_SEL_A > ; # [doc = "Selects LFCLK as clock source if enabled\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CLKSEL_LFCLK_SEL_A { # [doc = "0: DISABLE"] CLKSEL_LFCLK_SEL_DISABLE = 0 , # [doc = "1: ENABLE"] CLKSEL_LFCLK_SEL_ENABLE = 1 , } impl From < CLKSEL_LFCLK_SEL_A > for bool { # [inline (always)] fn from (variant : CLKSEL_LFCLK_SEL_A) -> Self { variant as u8 != 0 } } impl CLKSEL_LFCLK_SEL_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CLKSEL_LFCLK_SEL_A { match self . bits { false => CLKSEL_LFCLK_SEL_A :: CLKSEL_LFCLK_SEL_DISABLE , true => CLKSEL_LFCLK_SEL_A :: CLKSEL_LFCLK_SEL_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_clksel_lfclk_sel_disable (& self) -> bool { * self == CLKSEL_LFCLK_SEL_A :: CLKSEL_LFCLK_SEL_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_clksel_lfclk_sel_enable (& self) -> bool { * self == CLKSEL_LFCLK_SEL_A :: CLKSEL_LFCLK_SEL_ENABLE } } # [doc = "Field `CLKSEL_LFCLK_SEL` writer - Selects LFCLK as clock source if enabled"] pub type CLKSEL_LFCLK_SEL_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CLKSEL_LFCLK_SEL_A > ; impl < 'a , REG , const O : u8 > CLKSEL_LFCLK_SEL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn clksel_lfclk_sel_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CLKSEL_LFCLK_SEL_A :: CLKSEL_LFCLK_SEL_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn clksel_lfclk_sel_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CLKSEL_LFCLK_SEL_A :: CLKSEL_LFCLK_SEL_ENABLE) } } # [doc = "Field `CLKSEL_MFCLK_SEL` reader - Selects MFCLK as clock source if enabled"] pub type CLKSEL_MFCLK_SEL_R = crate :: BitReader < CLKSEL_MFCLK_SEL_A > ; # [doc = "Selects MFCLK as clock source if enabled\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CLKSEL_MFCLK_SEL_A { # [doc = "0: DISABLE"] CLKSEL_MFCLK_SEL_DISABLE = 0 , # [doc = "1: ENABLE"] CLKSEL_MFCLK_SEL_ENABLE = 1 , } impl From < CLKSEL_MFCLK_SEL_A > for bool { # [inline (always)] fn from (variant : CLKSEL_MFCLK_SEL_A) -> Self { variant as u8 != 0 } } impl CLKSEL_MFCLK_SEL_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CLKSEL_MFCLK_SEL_A { match self . bits { false => CLKSEL_MFCLK_SEL_A :: CLKSEL_MFCLK_SEL_DISABLE , true => CLKSEL_MFCLK_SEL_A :: CLKSEL_MFCLK_SEL_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_clksel_mfclk_sel_disable (& self) -> bool { * self == CLKSEL_MFCLK_SEL_A :: CLKSEL_MFCLK_SEL_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_clksel_mfclk_sel_enable (& self) -> bool { * self == CLKSEL_MFCLK_SEL_A :: CLKSEL_MFCLK_SEL_ENABLE } } # [doc = "Field `CLKSEL_MFCLK_SEL` writer - Selects MFCLK as clock source if enabled"] pub type CLKSEL_MFCLK_SEL_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CLKSEL_MFCLK_SEL_A > ; impl < 'a , REG , const O : u8 > CLKSEL_MFCLK_SEL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn clksel_mfclk_sel_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CLKSEL_MFCLK_SEL_A :: CLKSEL_MFCLK_SEL_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn clksel_mfclk_sel_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CLKSEL_MFCLK_SEL_A :: CLKSEL_MFCLK_SEL_ENABLE) } } # [doc = "Field `CLKSEL_BUSCLK_SEL` reader - Selects BUS CLK as clock source if enabled"] pub type CLKSEL_BUSCLK_SEL_R = crate :: BitReader < CLKSEL_BUSCLK_SEL_A > ; # [doc = "Selects BUS CLK as clock source if enabled\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CLKSEL_BUSCLK_SEL_A { # [doc = "0: DISABLE"] CLKSEL_BUSCLK_SEL_DISABLE = 0 , # [doc = "1: ENABLE"] CLKSEL_BUSCLK_SEL_ENABLE = 1 , } impl From < CLKSEL_BUSCLK_SEL_A > for bool { # [inline (always)] fn from (variant : CLKSEL_BUSCLK_SEL_A) -> Self { variant as u8 != 0 } } impl CLKSEL_BUSCLK_SEL_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CLKSEL_BUSCLK_SEL_A { match self . bits { false => CLKSEL_BUSCLK_SEL_A :: CLKSEL_BUSCLK_SEL_DISABLE , true => CLKSEL_BUSCLK_SEL_A :: CLKSEL_BUSCLK_SEL_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_clksel_busclk_sel_disable (& self) -> bool { * self == CLKSEL_BUSCLK_SEL_A :: CLKSEL_BUSCLK_SEL_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_clksel_busclk_sel_enable (& self) -> bool { * self == CLKSEL_BUSCLK_SEL_A :: CLKSEL_BUSCLK_SEL_ENABLE } } # [doc = "Field `CLKSEL_BUSCLK_SEL` writer - Selects BUS CLK as clock source if enabled"] pub type CLKSEL_BUSCLK_SEL_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CLKSEL_BUSCLK_SEL_A > ; impl < 'a , REG , const O : u8 > CLKSEL_BUSCLK_SEL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn clksel_busclk_sel_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CLKSEL_BUSCLK_SEL_A :: CLKSEL_BUSCLK_SEL_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn clksel_busclk_sel_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CLKSEL_BUSCLK_SEL_A :: CLKSEL_BUSCLK_SEL_ENABLE) } } impl R { # [doc = "Bit 1 - Selects LFCLK as clock source if enabled"] # [inline (always)] pub fn clksel_lfclk_sel (& self) -> CLKSEL_LFCLK_SEL_R { CLKSEL_LFCLK_SEL_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - Selects MFCLK as clock source if enabled"] # [inline (always)] pub fn clksel_mfclk_sel (& self) -> CLKSEL_MFCLK_SEL_R { CLKSEL_MFCLK_SEL_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - Selects BUS CLK as clock source if enabled"] # [inline (always)] pub fn clksel_busclk_sel (& self) -> CLKSEL_BUSCLK_SEL_R { CLKSEL_BUSCLK_SEL_R :: new (((self . bits >> 3) & 1) != 0) } } impl W { # [doc = "Bit 1 - Selects LFCLK as clock source if enabled"] # [inline (always)] # [must_use] pub fn clksel_lfclk_sel (& mut self) -> CLKSEL_LFCLK_SEL_W <'_,  CLKSEL_SPEC , 1 > { CLKSEL_LFCLK_SEL_W :: new (self) } # [doc = "Bit 2 - Selects MFCLK as clock source if enabled"] # [inline (always)] # [must_use] pub fn clksel_mfclk_sel (& mut self) -> CLKSEL_MFCLK_SEL_W < CLKSEL_SPEC , 2 > { CLKSEL_MFCLK_SEL_W :: new (self) } # [doc = "Bit 3 - Selects BUS CLK as clock source if enabled"] # [inline (always)] # [must_use] pub fn clksel_busclk_sel (& mut self) -> CLKSEL_BUSCLK_SEL_W < CLKSEL_SPEC , 3 > { CLKSEL_BUSCLK_SEL_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Clock Select for Ultra Low Power peripherals\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clksel::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clksel::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CLKSEL_SPEC ; impl crate :: RegisterSpec for CLKSEL_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`clksel::R`](R) reader structure"] impl crate :: Readable for CLKSEL_SPEC { } # [doc = "`write(|w| ..)` method takes [`clksel::W`](W) writer structure"] impl crate :: Writable for CLKSEL_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets CLKSEL to value 0"] impl crate :: Resettable for CLKSEL_SPEC { const RESET_VALUE : Self :: Ux = 0 ; }
[INFO] [stdout]   |                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                   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[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing
[INFO] [stdout]  --> src/uart0/clksel.rs:1:6636
[INFO] [stdout]   |
[INFO] [stdout] 1 | ... fn clksel_mfclk_sel (& mut self) -> CLKSEL_MFCLK_SEL_W < CLKSEL_SPEC , 2 > { CLKSEL_MFCLK_SEL_W :: new (self) } # [doc = "Bit 3 -...
[INFO] [stdout]   |                          ^^^^^^^^^^     ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here
[INFO] [stdout]   |                          |
[INFO] [stdout]   |                          the lifetime is elided here
[INFO] [stdout]   |
[INFO] [stdout]   = help: the same lifetime is referred to in inconsistent ways, making the signature confusing
[INFO] [stdout] help: use `'_` for type paths
[INFO] [stdout]   |
[INFO] [stdout] 1 | # [doc = "Register `CLKSEL` reader"] pub type R = crate :: R < CLKSEL_SPEC > ; # [doc = "Register `CLKSEL` writer"] pub type W = crate :: W < CLKSEL_SPEC > ; # [doc = "Field `CLKSEL_LFCLK_SEL` reader - Selects LFCLK as clock source if enabled"] pub type CLKSEL_LFCLK_SEL_R = crate :: BitReader < CLKSEL_LFCLK_SEL_A > ; # [doc = "Selects LFCLK as clock source if enabled\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CLKSEL_LFCLK_SEL_A { # [doc = "0: DISABLE"] CLKSEL_LFCLK_SEL_DISABLE = 0 , # [doc = "1: ENABLE"] CLKSEL_LFCLK_SEL_ENABLE = 1 , } impl From < CLKSEL_LFCLK_SEL_A > for bool { # [inline (always)] fn from (variant : CLKSEL_LFCLK_SEL_A) -> Self { variant as u8 != 0 } } impl CLKSEL_LFCLK_SEL_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CLKSEL_LFCLK_SEL_A { match self . bits { false => CLKSEL_LFCLK_SEL_A :: CLKSEL_LFCLK_SEL_DISABLE , true => CLKSEL_LFCLK_SEL_A :: CLKSEL_LFCLK_SEL_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_clksel_lfclk_sel_disable (& self) -> bool { * self == CLKSEL_LFCLK_SEL_A :: CLKSEL_LFCLK_SEL_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_clksel_lfclk_sel_enable (& self) -> bool { * self == CLKSEL_LFCLK_SEL_A :: CLKSEL_LFCLK_SEL_ENABLE } } # [doc = "Field `CLKSEL_LFCLK_SEL` writer - Selects LFCLK as clock source if enabled"] pub type CLKSEL_LFCLK_SEL_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CLKSEL_LFCLK_SEL_A > ; impl < 'a , REG , const O : u8 > CLKSEL_LFCLK_SEL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn clksel_lfclk_sel_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CLKSEL_LFCLK_SEL_A :: CLKSEL_LFCLK_SEL_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn clksel_lfclk_sel_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CLKSEL_LFCLK_SEL_A :: CLKSEL_LFCLK_SEL_ENABLE) } } # [doc = "Field `CLKSEL_MFCLK_SEL` reader - Selects MFCLK as clock source if enabled"] pub type CLKSEL_MFCLK_SEL_R = crate :: BitReader < CLKSEL_MFCLK_SEL_A > ; # [doc = "Selects MFCLK as clock source if enabled\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CLKSEL_MFCLK_SEL_A { # [doc = "0: DISABLE"] CLKSEL_MFCLK_SEL_DISABLE = 0 , # [doc = "1: ENABLE"] CLKSEL_MFCLK_SEL_ENABLE = 1 , } impl From < CLKSEL_MFCLK_SEL_A > for bool { # [inline (always)] fn from (variant : CLKSEL_MFCLK_SEL_A) -> Self { variant as u8 != 0 } } impl CLKSEL_MFCLK_SEL_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CLKSEL_MFCLK_SEL_A { match self . bits { false => CLKSEL_MFCLK_SEL_A :: CLKSEL_MFCLK_SEL_DISABLE , true => CLKSEL_MFCLK_SEL_A :: CLKSEL_MFCLK_SEL_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_clksel_mfclk_sel_disable (& self) -> bool { * self == CLKSEL_MFCLK_SEL_A :: CLKSEL_MFCLK_SEL_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_clksel_mfclk_sel_enable (& self) -> bool { * self == CLKSEL_MFCLK_SEL_A :: CLKSEL_MFCLK_SEL_ENABLE } } # [doc = "Field `CLKSEL_MFCLK_SEL` writer - Selects MFCLK as clock source if enabled"] pub type CLKSEL_MFCLK_SEL_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CLKSEL_MFCLK_SEL_A > ; impl < 'a , REG , const O : u8 > CLKSEL_MFCLK_SEL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn clksel_mfclk_sel_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CLKSEL_MFCLK_SEL_A :: CLKSEL_MFCLK_SEL_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn clksel_mfclk_sel_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CLKSEL_MFCLK_SEL_A :: CLKSEL_MFCLK_SEL_ENABLE) } } # [doc = "Field `CLKSEL_BUSCLK_SEL` reader - Selects BUS CLK as clock source if enabled"] pub type CLKSEL_BUSCLK_SEL_R = crate :: BitReader < CLKSEL_BUSCLK_SEL_A > ; # [doc = "Selects BUS CLK as clock source if enabled\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CLKSEL_BUSCLK_SEL_A { # [doc = "0: DISABLE"] CLKSEL_BUSCLK_SEL_DISABLE = 0 , # [doc = "1: ENABLE"] CLKSEL_BUSCLK_SEL_ENABLE = 1 , } impl From < CLKSEL_BUSCLK_SEL_A > for bool { # [inline (always)] fn from (variant : CLKSEL_BUSCLK_SEL_A) -> Self { variant as u8 != 0 } } impl CLKSEL_BUSCLK_SEL_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CLKSEL_BUSCLK_SEL_A { match self . bits { false => CLKSEL_BUSCLK_SEL_A :: CLKSEL_BUSCLK_SEL_DISABLE , true => CLKSEL_BUSCLK_SEL_A :: CLKSEL_BUSCLK_SEL_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_clksel_busclk_sel_disable (& self) -> bool { * self == CLKSEL_BUSCLK_SEL_A :: CLKSEL_BUSCLK_SEL_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_clksel_busclk_sel_enable (& self) -> bool { * self == CLKSEL_BUSCLK_SEL_A :: CLKSEL_BUSCLK_SEL_ENABLE } } # [doc = "Field `CLKSEL_BUSCLK_SEL` writer - Selects BUS CLK as clock source if enabled"] pub type CLKSEL_BUSCLK_SEL_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CLKSEL_BUSCLK_SEL_A > ; impl < 'a , REG , const O : u8 > CLKSEL_BUSCLK_SEL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn clksel_busclk_sel_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CLKSEL_BUSCLK_SEL_A :: CLKSEL_BUSCLK_SEL_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn clksel_busclk_sel_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CLKSEL_BUSCLK_SEL_A :: CLKSEL_BUSCLK_SEL_ENABLE) } } impl R { # [doc = "Bit 1 - Selects LFCLK as clock source if enabled"] # [inline (always)] pub fn clksel_lfclk_sel (& self) -> CLKSEL_LFCLK_SEL_R { CLKSEL_LFCLK_SEL_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - Selects MFCLK as clock source if enabled"] # [inline (always)] pub fn clksel_mfclk_sel (& self) -> CLKSEL_MFCLK_SEL_R { CLKSEL_MFCLK_SEL_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - Selects BUS CLK as clock source if enabled"] # [inline (always)] pub fn clksel_busclk_sel (& self) -> CLKSEL_BUSCLK_SEL_R { CLKSEL_BUSCLK_SEL_R :: new (((self . bits >> 3) & 1) != 0) } } impl W { # [doc = "Bit 1 - Selects LFCLK as clock source if enabled"] # [inline (always)] # [must_use] pub fn clksel_lfclk_sel (& mut self) -> CLKSEL_LFCLK_SEL_W < CLKSEL_SPEC , 1 > { CLKSEL_LFCLK_SEL_W :: new (self) } # [doc = "Bit 2 - Selects MFCLK as clock source if enabled"] # [inline (always)] # [must_use] pub fn clksel_mfclk_sel (& mut self) -> CLKSEL_MFCLK_SEL_W <'_,  CLKSEL_SPEC , 2 > { CLKSEL_MFCLK_SEL_W :: new (self) } # [doc = "Bit 3 - Selects BUS CLK as clock source if enabled"] # [inline (always)] # [must_use] pub fn clksel_busclk_sel (& mut self) -> CLKSEL_BUSCLK_SEL_W < CLKSEL_SPEC , 3 > { CLKSEL_BUSCLK_SEL_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Clock Select for Ultra Low Power peripherals\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clksel::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clksel::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CLKSEL_SPEC ; impl crate :: RegisterSpec for CLKSEL_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`clksel::R`](R) reader structure"] impl crate :: Readable for CLKSEL_SPEC { } # [doc = "`write(|w| ..)` method takes [`clksel::W`](W) writer structure"] impl crate :: Writable for CLKSEL_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets CLKSEL to value 0"] impl crate :: Resettable for CLKSEL_SPEC { const RESET_VALUE : Self :: Ux = 0 ; }
[INFO] [stdout]   |                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                               +++
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing
[INFO] [stdout]  --> src/uart0/clksel.rs:1:6849
[INFO] [stdout]   |
[INFO] [stdout] 1 | ...n clksel_busclk_sel (& mut self) -> CLKSEL_BUSCLK_SEL_W < CLKSEL_SPEC , 3 > { CLKSEL_BUSCLK_SEL_W :: new (self) } # [doc = r" Writ...
[INFO] [stdout]   |                         ^^^^^^^^^^     ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here
[INFO] [stdout]   |                         |
[INFO] [stdout]   |                         the lifetime is elided here
[INFO] [stdout]   |
[INFO] [stdout]   = help: the same lifetime is referred to in inconsistent ways, making the signature confusing
[INFO] [stdout] help: use `'_` for type paths
[INFO] [stdout]   |
[INFO] [stdout] 1 | # [doc = "Register `CLKSEL` reader"] pub type R = crate :: R < CLKSEL_SPEC > ; # [doc = "Register `CLKSEL` writer"] pub type W = crate :: W < CLKSEL_SPEC > ; # [doc = "Field `CLKSEL_LFCLK_SEL` reader - Selects LFCLK as clock source if enabled"] pub type CLKSEL_LFCLK_SEL_R = crate :: BitReader < CLKSEL_LFCLK_SEL_A > ; # [doc = "Selects LFCLK as clock source if enabled\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CLKSEL_LFCLK_SEL_A { # [doc = "0: DISABLE"] CLKSEL_LFCLK_SEL_DISABLE = 0 , # [doc = "1: ENABLE"] CLKSEL_LFCLK_SEL_ENABLE = 1 , } impl From < CLKSEL_LFCLK_SEL_A > for bool { # [inline (always)] fn from (variant : CLKSEL_LFCLK_SEL_A) -> Self { variant as u8 != 0 } } impl CLKSEL_LFCLK_SEL_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CLKSEL_LFCLK_SEL_A { match self . bits { false => CLKSEL_LFCLK_SEL_A :: CLKSEL_LFCLK_SEL_DISABLE , true => CLKSEL_LFCLK_SEL_A :: CLKSEL_LFCLK_SEL_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_clksel_lfclk_sel_disable (& self) -> bool { * self == CLKSEL_LFCLK_SEL_A :: CLKSEL_LFCLK_SEL_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_clksel_lfclk_sel_enable (& self) -> bool { * self == CLKSEL_LFCLK_SEL_A :: CLKSEL_LFCLK_SEL_ENABLE } } # [doc = "Field `CLKSEL_LFCLK_SEL` writer - Selects LFCLK as clock source if enabled"] pub type CLKSEL_LFCLK_SEL_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CLKSEL_LFCLK_SEL_A > ; impl < 'a , REG , const O : u8 > CLKSEL_LFCLK_SEL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn clksel_lfclk_sel_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CLKSEL_LFCLK_SEL_A :: CLKSEL_LFCLK_SEL_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn clksel_lfclk_sel_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CLKSEL_LFCLK_SEL_A :: CLKSEL_LFCLK_SEL_ENABLE) } } # [doc = "Field `CLKSEL_MFCLK_SEL` reader - Selects MFCLK as clock source if enabled"] pub type CLKSEL_MFCLK_SEL_R = crate :: BitReader < CLKSEL_MFCLK_SEL_A > ; # [doc = "Selects MFCLK as clock source if enabled\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CLKSEL_MFCLK_SEL_A { # [doc = "0: DISABLE"] CLKSEL_MFCLK_SEL_DISABLE = 0 , # [doc = "1: ENABLE"] CLKSEL_MFCLK_SEL_ENABLE = 1 , } impl From < CLKSEL_MFCLK_SEL_A > for bool { # [inline (always)] fn from (variant : CLKSEL_MFCLK_SEL_A) -> Self { variant as u8 != 0 } } impl CLKSEL_MFCLK_SEL_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CLKSEL_MFCLK_SEL_A { match self . bits { false => CLKSEL_MFCLK_SEL_A :: CLKSEL_MFCLK_SEL_DISABLE , true => CLKSEL_MFCLK_SEL_A :: CLKSEL_MFCLK_SEL_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_clksel_mfclk_sel_disable (& self) -> bool { * self == CLKSEL_MFCLK_SEL_A :: CLKSEL_MFCLK_SEL_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_clksel_mfclk_sel_enable (& self) -> bool { * self == CLKSEL_MFCLK_SEL_A :: CLKSEL_MFCLK_SEL_ENABLE } } # [doc = "Field `CLKSEL_MFCLK_SEL` writer - Selects MFCLK as clock source if enabled"] pub type CLKSEL_MFCLK_SEL_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CLKSEL_MFCLK_SEL_A > ; impl < 'a , REG , const O : u8 > CLKSEL_MFCLK_SEL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn clksel_mfclk_sel_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CLKSEL_MFCLK_SEL_A :: CLKSEL_MFCLK_SEL_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn clksel_mfclk_sel_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CLKSEL_MFCLK_SEL_A :: CLKSEL_MFCLK_SEL_ENABLE) } } # [doc = "Field `CLKSEL_BUSCLK_SEL` reader - Selects BUS CLK as clock source if enabled"] pub type CLKSEL_BUSCLK_SEL_R = crate :: BitReader < CLKSEL_BUSCLK_SEL_A > ; # [doc = "Selects BUS CLK as clock source if enabled\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CLKSEL_BUSCLK_SEL_A { # [doc = "0: DISABLE"] CLKSEL_BUSCLK_SEL_DISABLE = 0 , # [doc = "1: ENABLE"] CLKSEL_BUSCLK_SEL_ENABLE = 1 , } impl From < CLKSEL_BUSCLK_SEL_A > for bool { # [inline (always)] fn from (variant : CLKSEL_BUSCLK_SEL_A) -> Self { variant as u8 != 0 } } impl CLKSEL_BUSCLK_SEL_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CLKSEL_BUSCLK_SEL_A { match self . bits { false => CLKSEL_BUSCLK_SEL_A :: CLKSEL_BUSCLK_SEL_DISABLE , true => CLKSEL_BUSCLK_SEL_A :: CLKSEL_BUSCLK_SEL_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_clksel_busclk_sel_disable (& self) -> bool { * self == CLKSEL_BUSCLK_SEL_A :: CLKSEL_BUSCLK_SEL_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_clksel_busclk_sel_enable (& self) -> bool { * self == CLKSEL_BUSCLK_SEL_A :: CLKSEL_BUSCLK_SEL_ENABLE } } # [doc = "Field `CLKSEL_BUSCLK_SEL` writer - Selects BUS CLK as clock source if enabled"] pub type CLKSEL_BUSCLK_SEL_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CLKSEL_BUSCLK_SEL_A > ; impl < 'a , REG , const O : u8 > CLKSEL_BUSCLK_SEL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn clksel_busclk_sel_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CLKSEL_BUSCLK_SEL_A :: CLKSEL_BUSCLK_SEL_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn clksel_busclk_sel_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CLKSEL_BUSCLK_SEL_A :: CLKSEL_BUSCLK_SEL_ENABLE) } } impl R { # [doc = "Bit 1 - Selects LFCLK as clock source if enabled"] # [inline (always)] pub fn clksel_lfclk_sel (& self) -> CLKSEL_LFCLK_SEL_R { CLKSEL_LFCLK_SEL_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - Selects MFCLK as clock source if enabled"] # [inline (always)] pub fn clksel_mfclk_sel (& self) -> CLKSEL_MFCLK_SEL_R { CLKSEL_MFCLK_SEL_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - Selects BUS CLK as clock source if enabled"] # [inline (always)] pub fn clksel_busclk_sel (& self) -> CLKSEL_BUSCLK_SEL_R { CLKSEL_BUSCLK_SEL_R :: new (((self . bits >> 3) & 1) != 0) } } impl W { # [doc = "Bit 1 - Selects LFCLK as clock source if enabled"] # [inline (always)] # [must_use] pub fn clksel_lfclk_sel (& mut self) -> CLKSEL_LFCLK_SEL_W < CLKSEL_SPEC , 1 > { CLKSEL_LFCLK_SEL_W :: new (self) } # [doc = "Bit 2 - Selects MFCLK as clock source if enabled"] # [inline (always)] # [must_use] pub fn clksel_mfclk_sel (& mut self) -> CLKSEL_MFCLK_SEL_W < CLKSEL_SPEC , 2 > { CLKSEL_MFCLK_SEL_W :: new (self) } # [doc = "Bit 3 - Selects BUS CLK as clock source if enabled"] # [inline (always)] # [must_use] pub fn clksel_busclk_sel (& mut self) -> CLKSEL_BUSCLK_SEL_W <'_,  CLKSEL_SPEC , 3 > { CLKSEL_BUSCLK_SEL_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Clock Select for Ultra Low Power peripherals\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clksel::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clksel::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CLKSEL_SPEC ; impl crate :: RegisterSpec for CLKSEL_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`clksel::R`](R) reader structure"] impl crate :: Readable for CLKSEL_SPEC { } # [doc = "`write(|w| ..)` method takes [`clksel::W`](W) writer structure"] impl crate :: Writable for CLKSEL_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets CLKSEL to value 0"] impl crate :: Resettable for CLKSEL_SPEC { const RESET_VALUE : Self :: Ux = 0 ; }
[INFO] [stdout]   |                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                     +++
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing
[INFO] [stdout]  --> src/uart0/pdbgctl.rs:5:247
[INFO] [stdout]   |
[INFO] [stdout] 5 | ...] pub fn pdbgctl_free (& mut self) -> PDBGCTL_FREE_W < PDBGCTL_SPEC , 0 > { PDBGCTL_FREE_W :: new (self) } # [doc = "Bit 1 - Soft ...
[INFO] [stdout]   |                           ^^^^^^^^^^     ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here
[INFO] [stdout]   |                           |
[INFO] [stdout]   |                           the lifetime is elided here
[INFO] [stdout]   |
[INFO] [stdout]   = help: the same lifetime is referred to in inconsistent ways, making the signature confusing
[INFO] [stdout] help: use `'_` for type paths
[INFO] [stdout]   |
[INFO] [stdout] 5 | is set to 'STOP'"] # [inline (always)] pub fn pdbgctl_soft (& self) -> PDBGCTL_SOFT_R { PDBGCTL_SOFT_R :: new (((self . bits >> 1) & 1) != 0) } } impl W { # [doc = "Bit 0 - Free run control"] # [inline (always)] # [must_use] pub fn pdbgctl_free (& mut self) -> PDBGCTL_FREE_W <'_,  PDBGCTL_SPEC , 0 > { PDBGCTL_FREE_W :: new (self) } # [doc = "Bit 1 - Soft halt boundary control. This function is only available, if \\[FREE\\]
[INFO] [stdout]   |                                                                                                                                                                                                                                                                                      +++
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing
[INFO] [stdout]  --> src/uart0/pdbgctl.rs:6:74
[INFO] [stdout]   |
[INFO] [stdout] 6 | ...] pub fn pdbgctl_soft (& mut self) -> PDBGCTL_SOFT_W < PDBGCTL_SPEC , 1 > { PDBGCTL_SOFT_W :: new (self) } # [doc = r" Writes raw ...
[INFO] [stdout]   |                           ^^^^^^^^^^     ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here
[INFO] [stdout]   |                           |
[INFO] [stdout]   |                           the lifetime is elided here
[INFO] [stdout]   |
[INFO] [stdout]   = help: the same lifetime is referred to in inconsistent ways, making the signature confusing
[INFO] [stdout] help: use `'_` for type paths
[INFO] [stdout]   |
[INFO] [stdout] 6 | is set to 'STOP'"] # [inline (always)] # [must_use] pub fn pdbgctl_soft (& mut self) -> PDBGCTL_SOFT_W <'_,  PDBGCTL_SPEC , 1 > { PDBGCTL_SOFT_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Peripheral Debug Control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pdbgctl::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pdbgctl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PDBGCTL_SPEC ; impl crate :: RegisterSpec for PDBGCTL_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`pdbgctl::R`](R) reader structure"] impl crate :: Readable for PDBGCTL_SPEC { } # [doc = "`write(|w| ..)` method takes [`pdbgctl::W`](W) writer structure"] impl crate :: Writable for PDBGCTL_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets PDBGCTL to value 0"] impl crate :: Resettable for PDBGCTL_SPEC { const RESET_VALUE : Self :: Ux = 0 ; }
[INFO] [stdout]   |                                                                                                         +++
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing
[INFO] [stdout]  --> src/uart0/int_event0_imask.rs:1:40498
[INFO] [stdout]   |
[INFO] [stdout] 1 | ..._imask_rtout (& mut self) -> INT_EVENT0_IMASK_RTOUT_W < INT_EVENT0_IMASK_SPEC , 0 > { INT_EVENT0_IMASK_RTOUT_W :: new (self) } # [...
[INFO] [stdout]   |                  ^^^^^^^^^^     ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here
[INFO] [stdout]   |                  |
[INFO] [stdout]   |                  the lifetime is elided here
[INFO] [stdout]   |
[INFO] [stdout]   = help: the same lifetime is referred to in inconsistent ways, making the signature confusing
[INFO] [stdout] help: use `'_` for type paths
[INFO] [stdout]   |
[INFO] [stdout] 1 | # [doc = "Register `INT_EVENT0_IMASK` reader"] pub type R = crate :: R < INT_EVENT0_IMASK_SPEC > ; # [doc = "Register `INT_EVENT0_IMASK` writer"] pub type W = crate :: W < INT_EVENT0_IMASK_SPEC > ; # [doc = "Field `INT_EVENT0_IMASK_RTOUT` reader - Enable UARTOUT Receive Time-Out Interrupt."] pub type INT_EVENT0_IMASK_RTOUT_R = crate :: BitReader < INT_EVENT0_IMASK_RTOUT_A > ; # [doc = "Enable UARTOUT Receive Time-Out Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_RTOUT_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_RTOUT_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_RTOUT_SET = 1 , } impl From < INT_EVENT0_IMASK_RTOUT_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_RTOUT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_RTOUT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_RTOUT_A { match self . bits { false => INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_CLR , true => INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_rtout_clr (& self) -> bool { * self == INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_rtout_set (& self) -> bool { * self == INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_SET } } # [doc = "Field `INT_EVENT0_IMASK_RTOUT` writer - Enable UARTOUT Receive Time-Out Interrupt."] pub type INT_EVENT0_IMASK_RTOUT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_RTOUT_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_RTOUT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_rtout_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_rtout_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_SET) } } # [doc = "Field `INT_EVENT0_IMASK_FRMERR` reader - Enable UART Framing Error Interrupt."] pub type INT_EVENT0_IMASK_FRMERR_R = crate :: BitReader < INT_EVENT0_IMASK_FRMERR_A > ; # [doc = "Enable UART Framing Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_FRMERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_FRMERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_FRMERR_SET = 1 , } impl From < INT_EVENT0_IMASK_FRMERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_FRMERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_FRMERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_FRMERR_A { match self . bits { false => INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_CLR , true => INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_frmerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_frmerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_FRMERR` writer - Enable UART Framing Error Interrupt."] pub type INT_EVENT0_IMASK_FRMERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_FRMERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_FRMERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_frmerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_frmerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_SET) } } # [doc = "Field `INT_EVENT0_IMASK_PARERR` reader - Enable UART Parity Error Interrupt."] pub type INT_EVENT0_IMASK_PARERR_R = crate :: BitReader < INT_EVENT0_IMASK_PARERR_A > ; # [doc = "Enable UART Parity Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_PARERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_PARERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_PARERR_SET = 1 , } impl From < INT_EVENT0_IMASK_PARERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_PARERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_PARERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_PARERR_A { match self . bits { false => INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_CLR , true => INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_parerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_parerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_PARERR` writer - Enable UART Parity Error Interrupt."] pub type INT_EVENT0_IMASK_PARERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_PARERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_PARERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_parerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_parerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_SET) } } # [doc = "Field `INT_EVENT0_IMASK_BRKERR` reader - Enable UART Break Error Interrupt."] pub type INT_EVENT0_IMASK_BRKERR_R = crate :: BitReader < INT_EVENT0_IMASK_BRKERR_A > ; # [doc = "Enable UART Break Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_BRKERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_BRKERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_BRKERR_SET = 1 , } impl From < INT_EVENT0_IMASK_BRKERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_BRKERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_BRKERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_BRKERR_A { match self . bits { false => INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_CLR , true => INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_brkerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_brkerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_BRKERR` writer - Enable UART Break Error Interrupt."] pub type INT_EVENT0_IMASK_BRKERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_BRKERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_BRKERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_brkerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_brkerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_SET) } } # [doc = "Field `INT_EVENT0_IMASK_OVRERR` reader - Enable UART Receive Overrun Error Interrupt."] pub type INT_EVENT0_IMASK_OVRERR_R = crate :: BitReader < INT_EVENT0_IMASK_OVRERR_A > ; # [doc = "Enable UART Receive Overrun Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_OVRERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_OVRERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_OVRERR_SET = 1 , } impl From < INT_EVENT0_IMASK_OVRERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_OVRERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_OVRERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_OVRERR_A { match self . bits { false => INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_CLR , true => INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_ovrerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_ovrerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_OVRERR` writer - Enable UART Receive Overrun Error Interrupt."] pub type INT_EVENT0_IMASK_OVRERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_OVRERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_OVRERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_ovrerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_ovrerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_SET) } } # [doc = "Field `INT_EVENT0_IMASK_RXNE` reader - Enable Negative Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_IMASK_RXNE_R = crate :: BitReader < INT_EVENT0_IMASK_RXNE_A > ; # [doc = "Enable Negative Edge on UARTxRXD Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_RXNE_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_RXNE_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_RXNE_SET = 1 , } impl From < INT_EVENT0_IMASK_RXNE_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_RXNE_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_RXNE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_RXNE_A { match self . bits { false => INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_CLR , true => INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_rxne_clr (& self) -> bool { * self == INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_rxne_set (& self) -> bool { * self == INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_SET } } # [doc = "Field `INT_EVENT0_IMASK_RXNE` writer - Enable Negative Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_IMASK_RXNE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_RXNE_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_RXNE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_rxne_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_rxne_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_SET) } } # [doc = "Field `INT_EVENT0_IMASK_RXPE` reader - Enable Positive Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_IMASK_RXPE_R = crate :: BitReader < INT_EVENT0_IMASK_RXPE_A > ; # [doc = "Enable Positive Edge on UARTxRXD Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_RXPE_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_RXPE_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_RXPE_SET = 1 , } impl From < INT_EVENT0_IMASK_RXPE_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_RXPE_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_RXPE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_RXPE_A { match self . bits { false => INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_CLR , true => INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_rxpe_clr (& self) -> bool { * self == INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_rxpe_set (& self) -> bool { * self == INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_SET } } # [doc = "Field `INT_EVENT0_IMASK_RXPE` writer - Enable Positive Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_IMASK_RXPE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_RXPE_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_RXPE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_rxpe_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_rxpe_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_SET) } } # [doc = "Field `INT_EVENT0_IMASK_LINC0` reader - Enable LIN Capture 0 / Match Interrupt ."] pub type INT_EVENT0_IMASK_LINC0_R = crate :: BitReader < INT_EVENT0_IMASK_LINC0_A > ; # [doc = "Enable LIN Capture 0 / Match Interrupt .\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_LINC0_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_LINC0_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_LINC0_SET = 1 , } impl From < INT_EVENT0_IMASK_LINC0_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_LINC0_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_LINC0_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_LINC0_A { match self . bits { false => INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_CLR , true => INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_linc0_clr (& self) -> bool { * self == INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_linc0_set (& self) -> bool { * self == INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_SET } } # [doc = "Field `INT_EVENT0_IMASK_LINC0` writer - Enable LIN Capture 0 / Match Interrupt ."] pub type INT_EVENT0_IMASK_LINC0_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_LINC0_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_LINC0_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_linc0_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_linc0_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_SET) } } # [doc = "Field `INT_EVENT0_IMASK_LINC1` reader - Enable LIN Capture 1 Interrupt."] pub type INT_EVENT0_IMASK_LINC1_R = crate :: BitReader < INT_EVENT0_IMASK_LINC1_A > ; # [doc = "Enable LIN Capture 1 Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_LINC1_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_LINC1_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_LINC1_SET = 1 , } impl From < INT_EVENT0_IMASK_LINC1_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_LINC1_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_LINC1_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_LINC1_A { match self . bits { false => INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_CLR , true => INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_linc1_clr (& self) -> bool { * self == INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_linc1_set (& self) -> bool { * self == INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_SET } } # [doc = "Field `INT_EVENT0_IMASK_LINC1` writer - Enable LIN Capture 1 Interrupt."] pub type INT_EVENT0_IMASK_LINC1_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_LINC1_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_LINC1_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_linc1_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_linc1_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_SET) } } # [doc = "Field `INT_EVENT0_IMASK_LINOVF` reader - Enable LIN Hardware Counter Overflow Interrupt."] pub type INT_EVENT0_IMASK_LINOVF_R = crate :: BitReader < INT_EVENT0_IMASK_LINOVF_A > ; # [doc = "Enable LIN Hardware Counter Overflow Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_LINOVF_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_LINOVF_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_LINOVF_SET = 1 , } impl From < INT_EVENT0_IMASK_LINOVF_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_LINOVF_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_LINOVF_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_LINOVF_A { match self . bits { false => INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_CLR , true => INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_linovf_clr (& self) -> bool { * self == INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_linovf_set (& self) -> bool { * self == INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_SET } } # [doc = "Field `INT_EVENT0_IMASK_LINOVF` writer - Enable LIN Hardware Counter Overflow Interrupt."] pub type INT_EVENT0_IMASK_LINOVF_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_LINOVF_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_LINOVF_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_linovf_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_linovf_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_SET) } } # [doc = "Field `INT_EVENT0_IMASK_RXINT` reader - Enable UART Receive Interrupt."] pub type INT_EVENT0_IMASK_RXINT_R = crate :: BitReader < INT_EVENT0_IMASK_RXINT_A > ; # [doc = "Enable UART Receive Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_RXINT_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_RXINT_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_RXINT_SET = 1 , } impl From < INT_EVENT0_IMASK_RXINT_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_RXINT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_RXINT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_RXINT_A { match self . bits { false => INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_CLR , true => INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_rxint_clr (& self) -> bool { * self == INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_rxint_set (& self) -> bool { * self == INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_SET } } # [doc = "Field `INT_EVENT0_IMASK_RXINT` writer - Enable UART Receive Interrupt."] pub type INT_EVENT0_IMASK_RXINT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_RXINT_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_RXINT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_rxint_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_rxint_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_SET) } } # [doc = "Field `INT_EVENT0_IMASK_TXINT` reader - Enable UART Transmit Interrupt."] pub type INT_EVENT0_IMASK_TXINT_R = crate :: BitReader < INT_EVENT0_IMASK_TXINT_A > ; # [doc = "Enable UART Transmit Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_TXINT_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_TXINT_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_TXINT_SET = 1 , } impl From < INT_EVENT0_IMASK_TXINT_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_TXINT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_TXINT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_TXINT_A { match self . bits { false => INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_CLR , true => INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_txint_clr (& self) -> bool { * self == INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_txint_set (& self) -> bool { * self == INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_SET } } # [doc = "Field `INT_EVENT0_IMASK_TXINT` writer - Enable UART Transmit Interrupt."] pub type INT_EVENT0_IMASK_TXINT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_TXINT_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_TXINT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_txint_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_txint_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_SET) } } # [doc = "Field `INT_EVENT0_IMASK_EOT` reader - Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] pub type INT_EVENT0_IMASK_EOT_R = crate :: BitReader < INT_EVENT0_IMASK_EOT_A > ; # [doc = "Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_EOT_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_EOT_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_EOT_SET = 1 , } impl From < INT_EVENT0_IMASK_EOT_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_EOT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_EOT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_EOT_A { match self . bits { false => INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_CLR , true => INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_eot_clr (& self) -> bool { * self == INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_eot_set (& self) -> bool { * self == INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_SET } } # [doc = "Field `INT_EVENT0_IMASK_EOT` writer - Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] pub type INT_EVENT0_IMASK_EOT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_EOT_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_EOT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_eot_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_eot_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_SET) } } # [doc = "Field `INT_EVENT0_IMASK_ADDR_MATCH` reader - Enable Address Match Interrupt."] pub type INT_EVENT0_IMASK_ADDR_MATCH_R = crate :: BitReader < INT_EVENT0_IMASK_ADDR_MATCH_A > ; # [doc = "Enable Address Match Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_ADDR_MATCH_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_ADDR_MATCH_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_ADDR_MATCH_SET = 1 , } impl From < INT_EVENT0_IMASK_ADDR_MATCH_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_ADDR_MATCH_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_ADDR_MATCH_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_ADDR_MATCH_A { match self . bits { false => INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_CLR , true => INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_addr_match_clr (& self) -> bool { * self == INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_addr_match_set (& self) -> bool { * self == INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_SET } } # [doc = "Field `INT_EVENT0_IMASK_ADDR_MATCH` writer - Enable Address Match Interrupt."] pub type INT_EVENT0_IMASK_ADDR_MATCH_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_ADDR_MATCH_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_ADDR_MATCH_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_addr_match_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_addr_match_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_SET) } } # [doc = "Field `INT_EVENT0_IMASK_CTS` reader - Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] pub type INT_EVENT0_IMASK_CTS_R = crate :: BitReader < INT_EVENT0_IMASK_CTS_A > ; # [doc = "Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_CTS_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_CTS_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_CTS_SET = 1 , } impl From < INT_EVENT0_IMASK_CTS_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_CTS_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_CTS_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_CTS_A { match self . bits { false => INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_CLR , true => INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_cts_clr (& self) -> bool { * self == INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_cts_set (& self) -> bool { * self == INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_SET } } # [doc = "Field `INT_EVENT0_IMASK_CTS` writer - Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] pub type INT_EVENT0_IMASK_CTS_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_CTS_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_CTS_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_cts_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_cts_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DMA_DONE_RX` reader - Enable DMA Done on RX Event Channel"] pub type INT_EVENT0_IMASK_DMA_DONE_RX_R = crate :: BitReader < INT_EVENT0_IMASK_DMA_DONE_RX_A > ; # [doc = "Enable DMA Done on RX Event Channel\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DMA_DONE_RX_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DMA_DONE_RX_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DMA_DONE_RX_SET = 1 , } impl From < INT_EVENT0_IMASK_DMA_DONE_RX_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DMA_DONE_RX_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DMA_DONE_RX_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DMA_DONE_RX_A { match self . bits { false => INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_CLR , true => INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dma_done_rx_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dma_done_rx_set (& self) -> bool { * self == INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_SET } } # [doc = "Field `INT_EVENT0_IMASK_DMA_DONE_RX` writer - Enable DMA Done on RX Event Channel"] pub type INT_EVENT0_IMASK_DMA_DONE_RX_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DMA_DONE_RX_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DMA_DONE_RX_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dma_done_rx_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dma_done_rx_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DMA_DONE_TX` reader - Enable DMA Done on TX Event Channel"] pub type INT_EVENT0_IMASK_DMA_DONE_TX_R = crate :: BitReader < INT_EVENT0_IMASK_DMA_DONE_TX_A > ; # [doc = "Enable DMA Done on TX Event Channel\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DMA_DONE_TX_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DMA_DONE_TX_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DMA_DONE_TX_SET = 1 , } impl From < INT_EVENT0_IMASK_DMA_DONE_TX_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DMA_DONE_TX_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DMA_DONE_TX_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DMA_DONE_TX_A { match self . bits { false => INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_CLR , true => INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dma_done_tx_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dma_done_tx_set (& self) -> bool { * self == INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_SET } } # [doc = "Field `INT_EVENT0_IMASK_DMA_DONE_TX` writer - Enable DMA Done on TX Event Channel"] pub type INT_EVENT0_IMASK_DMA_DONE_TX_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DMA_DONE_TX_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DMA_DONE_TX_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dma_done_tx_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dma_done_tx_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_SET) } } # [doc = "Field `INT_EVENT0_IMASK_NERR` reader - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] pub type INT_EVENT0_IMASK_NERR_R = crate :: BitReader < INT_EVENT0_IMASK_NERR_A > ; # [doc = "Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_NERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_NERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_NERR_SET = 1 , } impl From < INT_EVENT0_IMASK_NERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_NERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_NERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_NERR_A { match self . bits { false => INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_CLR , true => INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_nerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_nerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_NERR` writer - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] pub type INT_EVENT0_IMASK_NERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_NERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_NERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_nerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_nerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_SET) } } impl R { # [doc = "Bit 0 - Enable UARTOUT Receive Time-Out Interrupt."] # [inline (always)] pub fn int_event0_imask_rtout (& self) -> INT_EVENT0_IMASK_RTOUT_R { INT_EVENT0_IMASK_RTOUT_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - Enable UART Framing Error Interrupt."] # [inline (always)] pub fn int_event0_imask_frmerr (& self) -> INT_EVENT0_IMASK_FRMERR_R { INT_EVENT0_IMASK_FRMERR_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - Enable UART Parity Error Interrupt."] # [inline (always)] pub fn int_event0_imask_parerr (& self) -> INT_EVENT0_IMASK_PARERR_R { INT_EVENT0_IMASK_PARERR_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - Enable UART Break Error Interrupt."] # [inline (always)] pub fn int_event0_imask_brkerr (& self) -> INT_EVENT0_IMASK_BRKERR_R { INT_EVENT0_IMASK_BRKERR_R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - Enable UART Receive Overrun Error Interrupt."] # [inline (always)] pub fn int_event0_imask_ovrerr (& self) -> INT_EVENT0_IMASK_OVRERR_R { INT_EVENT0_IMASK_OVRERR_R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - Enable Negative Edge on UARTxRXD Interrupt."] # [inline (always)] pub fn int_event0_imask_rxne (& self) -> INT_EVENT0_IMASK_RXNE_R { INT_EVENT0_IMASK_RXNE_R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - Enable Positive Edge on UARTxRXD Interrupt."] # [inline (always)] pub fn int_event0_imask_rxpe (& self) -> INT_EVENT0_IMASK_RXPE_R { INT_EVENT0_IMASK_RXPE_R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - Enable LIN Capture 0 / Match Interrupt ."] # [inline (always)] pub fn int_event0_imask_linc0 (& self) -> INT_EVENT0_IMASK_LINC0_R { INT_EVENT0_IMASK_LINC0_R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - Enable LIN Capture 1 Interrupt."] # [inline (always)] pub fn int_event0_imask_linc1 (& self) -> INT_EVENT0_IMASK_LINC1_R { INT_EVENT0_IMASK_LINC1_R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - Enable LIN Hardware Counter Overflow Interrupt."] # [inline (always)] pub fn int_event0_imask_linovf (& self) -> INT_EVENT0_IMASK_LINOVF_R { INT_EVENT0_IMASK_LINOVF_R :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - Enable UART Receive Interrupt."] # [inline (always)] pub fn int_event0_imask_rxint (& self) -> INT_EVENT0_IMASK_RXINT_R { INT_EVENT0_IMASK_RXINT_R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - Enable UART Transmit Interrupt."] # [inline (always)] pub fn int_event0_imask_txint (& self) -> INT_EVENT0_IMASK_TXINT_R { INT_EVENT0_IMASK_TXINT_R :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] # [inline (always)] pub fn int_event0_imask_eot (& self) -> INT_EVENT0_IMASK_EOT_R { INT_EVENT0_IMASK_EOT_R :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - Enable Address Match Interrupt."] # [inline (always)] pub fn int_event0_imask_addr_match (& self) -> INT_EVENT0_IMASK_ADDR_MATCH_R { INT_EVENT0_IMASK_ADDR_MATCH_R :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 14 - Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] # [inline (always)] pub fn int_event0_imask_cts (& self) -> INT_EVENT0_IMASK_CTS_R { INT_EVENT0_IMASK_CTS_R :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - Enable DMA Done on RX Event Channel"] # [inline (always)] pub fn int_event0_imask_dma_done_rx (& self) -> INT_EVENT0_IMASK_DMA_DONE_RX_R { INT_EVENT0_IMASK_DMA_DONE_RX_R :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bit 16 - Enable DMA Done on TX Event Channel"] # [inline (always)] pub fn int_event0_imask_dma_done_tx (& self) -> INT_EVENT0_IMASK_DMA_DONE_TX_R { INT_EVENT0_IMASK_DMA_DONE_TX_R :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] # [inline (always)] pub fn int_event0_imask_nerr (& self) -> INT_EVENT0_IMASK_NERR_R { INT_EVENT0_IMASK_NERR_R :: new (((self . bits >> 17) & 1) != 0) } } impl W { # [doc = "Bit 0 - Enable UARTOUT Receive Time-Out Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_rtout (& mut self) -> INT_EVENT0_IMASK_RTOUT_W <'_,  INT_EVENT0_IMASK_SPEC , 0 > { INT_EVENT0_IMASK_RTOUT_W :: new (self) } # [doc = "Bit 1 - Enable UART Framing Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_frmerr (& mut self) -> INT_EVENT0_IMASK_FRMERR_W < INT_EVENT0_IMASK_SPEC , 1 > { INT_EVENT0_IMASK_FRMERR_W :: new (self) } # [doc = "Bit 2 - Enable UART Parity Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_parerr (& mut self) -> INT_EVENT0_IMASK_PARERR_W < INT_EVENT0_IMASK_SPEC , 2 > { INT_EVENT0_IMASK_PARERR_W :: new (self) } # [doc = "Bit 3 - Enable UART Break Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_brkerr (& mut self) -> INT_EVENT0_IMASK_BRKERR_W < INT_EVENT0_IMASK_SPEC , 3 > { INT_EVENT0_IMASK_BRKERR_W :: new (self) } # [doc = "Bit 4 - Enable UART Receive Overrun Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_ovrerr (& mut self) -> INT_EVENT0_IMASK_OVRERR_W < INT_EVENT0_IMASK_SPEC , 4 > { INT_EVENT0_IMASK_OVRERR_W :: new (self) } # [doc = "Bit 5 - Enable Negative Edge on UARTxRXD Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_rxne (& mut self) -> INT_EVENT0_IMASK_RXNE_W < INT_EVENT0_IMASK_SPEC , 5 > { INT_EVENT0_IMASK_RXNE_W :: new (self) } # [doc = "Bit 6 - Enable Positive Edge on UARTxRXD Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_rxpe (& mut self) -> INT_EVENT0_IMASK_RXPE_W < INT_EVENT0_IMASK_SPEC , 6 > { INT_EVENT0_IMASK_RXPE_W :: new (self) } # [doc = "Bit 7 - Enable LIN Capture 0 / Match Interrupt ."] # [inline (always)] # [must_use] pub fn int_event0_imask_linc0 (& mut self) -> INT_EVENT0_IMASK_LINC0_W < INT_EVENT0_IMASK_SPEC , 7 > { INT_EVENT0_IMASK_LINC0_W :: new (self) } # [doc = "Bit 8 - Enable LIN Capture 1 Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_linc1 (& mut self) -> INT_EVENT0_IMASK_LINC1_W < INT_EVENT0_IMASK_SPEC , 8 > { INT_EVENT0_IMASK_LINC1_W :: new (self) } # [doc = "Bit 9 - Enable LIN Hardware Counter Overflow Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_linovf (& mut self) -> INT_EVENT0_IMASK_LINOVF_W < INT_EVENT0_IMASK_SPEC , 9 > { INT_EVENT0_IMASK_LINOVF_W :: new (self) } # [doc = "Bit 10 - Enable UART Receive Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_rxint (& mut self) -> INT_EVENT0_IMASK_RXINT_W < INT_EVENT0_IMASK_SPEC , 10 > { INT_EVENT0_IMASK_RXINT_W :: new (self) } # [doc = "Bit 11 - Enable UART Transmit Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_txint (& mut self) -> INT_EVENT0_IMASK_TXINT_W < INT_EVENT0_IMASK_SPEC , 11 > { INT_EVENT0_IMASK_TXINT_W :: new (self) } # [doc = "Bit 12 - Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] # [inline (always)] # [must_use] pub fn int_event0_imask_eot (& mut self) -> INT_EVENT0_IMASK_EOT_W < INT_EVENT0_IMASK_SPEC , 12 > { INT_EVENT0_IMASK_EOT_W :: new (self) } # [doc = "Bit 13 - Enable Address Match Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_addr_match (& mut self) -> INT_EVENT0_IMASK_ADDR_MATCH_W < INT_EVENT0_IMASK_SPEC , 13 > { INT_EVENT0_IMASK_ADDR_MATCH_W :: new (self) } # [doc = "Bit 14 - Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] # [inline (always)] # [must_use] pub fn int_event0_imask_cts (& mut self) -> INT_EVENT0_IMASK_CTS_W < INT_EVENT0_IMASK_SPEC , 14 > { INT_EVENT0_IMASK_CTS_W :: new (self) } # [doc = "Bit 15 - Enable DMA Done on RX Event Channel"] # [inline (always)] # [must_use] pub fn int_event0_imask_dma_done_rx (& mut self) -> INT_EVENT0_IMASK_DMA_DONE_RX_W < INT_EVENT0_IMASK_SPEC , 15 > { INT_EVENT0_IMASK_DMA_DONE_RX_W :: new (self) } # [doc = "Bit 16 - Enable DMA Done on TX Event Channel"] # [inline (always)] # [must_use] pub fn int_event0_imask_dma_done_tx (& mut self) -> INT_EVENT0_IMASK_DMA_DONE_TX_W < INT_EVENT0_IMASK_SPEC , 16 > { INT_EVENT0_IMASK_DMA_DONE_TX_W :: new (self) } # [doc = "Bit 17 - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] # [inline (always)] # [must_use] pub fn int_event0_imask_nerr (& mut self) -> INT_EVENT0_IMASK_NERR_W < INT_EVENT0_IMASK_SPEC , 17 > { INT_EVENT0_IMASK_NERR_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Interrupt mask\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_event0_imask::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_event0_imask::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct INT_EVENT0_IMASK_SPEC ; impl crate :: RegisterSpec for INT_EVENT0_IMASK_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`int_event0_imask::R`](R) reader structure"] impl crate :: Readable for INT_EVENT0_IMASK_SPEC { } # [doc = "`write(|w| ..)` method takes [`int_event0_imask::W`](W) writer structure"] impl crate :: Writable for INT_EVENT0_IMASK_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets INT_EVENT0_IMASK to value 0"] impl crate :: Resettable for INT_EVENT0_IMASK_SPEC { const RESET_VALUE : Self :: Ux = 0 ; }
[INFO] [stdout]   |                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                           +++
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing
[INFO] [stdout]  --> src/uart0/int_event0_imask.rs:1:40733
[INFO] [stdout]   |
[INFO] [stdout] 1 | ...mask_frmerr (& mut self) -> INT_EVENT0_IMASK_FRMERR_W < INT_EVENT0_IMASK_SPEC , 1 > { INT_EVENT0_IMASK_FRMERR_W :: new (self) } # ...
[INFO] [stdout]   |                 ^^^^^^^^^^     ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here
[INFO] [stdout]   |                 |
[INFO] [stdout]   |                 the lifetime is elided here
[INFO] [stdout]   |
[INFO] [stdout]   = help: the same lifetime is referred to in inconsistent ways, making the signature confusing
[INFO] [stdout] help: use `'_` for type paths
[INFO] [stdout]   |
[INFO] [stdout] 1 | # [doc = "Register `INT_EVENT0_IMASK` reader"] pub type R = crate :: R < INT_EVENT0_IMASK_SPEC > ; # [doc = "Register `INT_EVENT0_IMASK` writer"] pub type W = crate :: W < INT_EVENT0_IMASK_SPEC > ; # [doc = "Field `INT_EVENT0_IMASK_RTOUT` reader - Enable UARTOUT Receive Time-Out Interrupt."] pub type INT_EVENT0_IMASK_RTOUT_R = crate :: BitReader < INT_EVENT0_IMASK_RTOUT_A > ; # [doc = "Enable UARTOUT Receive Time-Out Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_RTOUT_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_RTOUT_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_RTOUT_SET = 1 , } impl From < INT_EVENT0_IMASK_RTOUT_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_RTOUT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_RTOUT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_RTOUT_A { match self . bits { false => INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_CLR , true => INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_rtout_clr (& self) -> bool { * self == INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_rtout_set (& self) -> bool { * self == INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_SET } } # [doc = "Field `INT_EVENT0_IMASK_RTOUT` writer - Enable UARTOUT Receive Time-Out Interrupt."] pub type INT_EVENT0_IMASK_RTOUT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_RTOUT_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_RTOUT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_rtout_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_rtout_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_SET) } } # [doc = "Field `INT_EVENT0_IMASK_FRMERR` reader - Enable UART Framing Error Interrupt."] pub type INT_EVENT0_IMASK_FRMERR_R = crate :: BitReader < INT_EVENT0_IMASK_FRMERR_A > ; # [doc = "Enable UART Framing Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_FRMERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_FRMERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_FRMERR_SET = 1 , } impl From < INT_EVENT0_IMASK_FRMERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_FRMERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_FRMERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_FRMERR_A { match self . bits { false => INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_CLR , true => INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_frmerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_frmerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_FRMERR` writer - Enable UART Framing Error Interrupt."] pub type INT_EVENT0_IMASK_FRMERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_FRMERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_FRMERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_frmerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_frmerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_SET) } } # [doc = "Field `INT_EVENT0_IMASK_PARERR` reader - Enable UART Parity Error Interrupt."] pub type INT_EVENT0_IMASK_PARERR_R = crate :: BitReader < INT_EVENT0_IMASK_PARERR_A > ; # [doc = "Enable UART Parity Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_PARERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_PARERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_PARERR_SET = 1 , } impl From < INT_EVENT0_IMASK_PARERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_PARERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_PARERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_PARERR_A { match self . bits { false => INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_CLR , true => INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_parerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_parerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_PARERR` writer - Enable UART Parity Error Interrupt."] pub type INT_EVENT0_IMASK_PARERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_PARERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_PARERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_parerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_parerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_SET) } } # [doc = "Field `INT_EVENT0_IMASK_BRKERR` reader - Enable UART Break Error Interrupt."] pub type INT_EVENT0_IMASK_BRKERR_R = crate :: BitReader < INT_EVENT0_IMASK_BRKERR_A > ; # [doc = "Enable UART Break Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_BRKERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_BRKERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_BRKERR_SET = 1 , } impl From < INT_EVENT0_IMASK_BRKERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_BRKERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_BRKERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_BRKERR_A { match self . bits { false => INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_CLR , true => INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_brkerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_brkerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_BRKERR` writer - Enable UART Break Error Interrupt."] pub type INT_EVENT0_IMASK_BRKERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_BRKERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_BRKERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_brkerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_brkerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_SET) } } # [doc = "Field `INT_EVENT0_IMASK_OVRERR` reader - Enable UART Receive Overrun Error Interrupt."] pub type INT_EVENT0_IMASK_OVRERR_R = crate :: BitReader < INT_EVENT0_IMASK_OVRERR_A > ; # [doc = "Enable UART Receive Overrun Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_OVRERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_OVRERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_OVRERR_SET = 1 , } impl From < INT_EVENT0_IMASK_OVRERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_OVRERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_OVRERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_OVRERR_A { match self . bits { false => INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_CLR , true => INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_ovrerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_ovrerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_OVRERR` writer - Enable UART Receive Overrun Error Interrupt."] pub type INT_EVENT0_IMASK_OVRERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_OVRERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_OVRERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_ovrerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_ovrerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_SET) } } # [doc = "Field `INT_EVENT0_IMASK_RXNE` reader - Enable Negative Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_IMASK_RXNE_R = crate :: BitReader < INT_EVENT0_IMASK_RXNE_A > ; # [doc = "Enable Negative Edge on UARTxRXD Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_RXNE_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_RXNE_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_RXNE_SET = 1 , } impl From < INT_EVENT0_IMASK_RXNE_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_RXNE_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_RXNE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_RXNE_A { match self . bits { false => INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_CLR , true => INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_rxne_clr (& self) -> bool { * self == INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_rxne_set (& self) -> bool { * self == INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_SET } } # [doc = "Field `INT_EVENT0_IMASK_RXNE` writer - Enable Negative Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_IMASK_RXNE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_RXNE_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_RXNE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_rxne_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_rxne_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_SET) } } # [doc = "Field `INT_EVENT0_IMASK_RXPE` reader - Enable Positive Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_IMASK_RXPE_R = crate :: BitReader < INT_EVENT0_IMASK_RXPE_A > ; # [doc = "Enable Positive Edge on UARTxRXD Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_RXPE_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_RXPE_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_RXPE_SET = 1 , } impl From < INT_EVENT0_IMASK_RXPE_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_RXPE_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_RXPE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_RXPE_A { match self . bits { false => INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_CLR , true => INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_rxpe_clr (& self) -> bool { * self == INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_rxpe_set (& self) -> bool { * self == INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_SET } } # [doc = "Field `INT_EVENT0_IMASK_RXPE` writer - Enable Positive Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_IMASK_RXPE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_RXPE_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_RXPE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_rxpe_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_rxpe_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_SET) } } # [doc = "Field `INT_EVENT0_IMASK_LINC0` reader - Enable LIN Capture 0 / Match Interrupt ."] pub type INT_EVENT0_IMASK_LINC0_R = crate :: BitReader < INT_EVENT0_IMASK_LINC0_A > ; # [doc = "Enable LIN Capture 0 / Match Interrupt .\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_LINC0_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_LINC0_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_LINC0_SET = 1 , } impl From < INT_EVENT0_IMASK_LINC0_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_LINC0_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_LINC0_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_LINC0_A { match self . bits { false => INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_CLR , true => INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_linc0_clr (& self) -> bool { * self == INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_linc0_set (& self) -> bool { * self == INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_SET } } # [doc = "Field `INT_EVENT0_IMASK_LINC0` writer - Enable LIN Capture 0 / Match Interrupt ."] pub type INT_EVENT0_IMASK_LINC0_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_LINC0_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_LINC0_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_linc0_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_linc0_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_SET) } } # [doc = "Field `INT_EVENT0_IMASK_LINC1` reader - Enable LIN Capture 1 Interrupt."] pub type INT_EVENT0_IMASK_LINC1_R = crate :: BitReader < INT_EVENT0_IMASK_LINC1_A > ; # [doc = "Enable LIN Capture 1 Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_LINC1_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_LINC1_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_LINC1_SET = 1 , } impl From < INT_EVENT0_IMASK_LINC1_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_LINC1_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_LINC1_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_LINC1_A { match self . bits { false => INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_CLR , true => INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_linc1_clr (& self) -> bool { * self == INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_linc1_set (& self) -> bool { * self == INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_SET } } # [doc = "Field `INT_EVENT0_IMASK_LINC1` writer - Enable LIN Capture 1 Interrupt."] pub type INT_EVENT0_IMASK_LINC1_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_LINC1_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_LINC1_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_linc1_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_linc1_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_SET) } } # [doc = "Field `INT_EVENT0_IMASK_LINOVF` reader - Enable LIN Hardware Counter Overflow Interrupt."] pub type INT_EVENT0_IMASK_LINOVF_R = crate :: BitReader < INT_EVENT0_IMASK_LINOVF_A > ; # [doc = "Enable LIN Hardware Counter Overflow Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_LINOVF_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_LINOVF_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_LINOVF_SET = 1 , } impl From < INT_EVENT0_IMASK_LINOVF_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_LINOVF_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_LINOVF_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_LINOVF_A { match self . bits { false => INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_CLR , true => INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_linovf_clr (& self) -> bool { * self == INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_linovf_set (& self) -> bool { * self == INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_SET } } # [doc = "Field `INT_EVENT0_IMASK_LINOVF` writer - Enable LIN Hardware Counter Overflow Interrupt."] pub type INT_EVENT0_IMASK_LINOVF_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_LINOVF_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_LINOVF_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_linovf_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_linovf_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_SET) } } # [doc = "Field `INT_EVENT0_IMASK_RXINT` reader - Enable UART Receive Interrupt."] pub type INT_EVENT0_IMASK_RXINT_R = crate :: BitReader < INT_EVENT0_IMASK_RXINT_A > ; # [doc = "Enable UART Receive Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_RXINT_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_RXINT_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_RXINT_SET = 1 , } impl From < INT_EVENT0_IMASK_RXINT_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_RXINT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_RXINT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_RXINT_A { match self . bits { false => INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_CLR , true => INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_rxint_clr (& self) -> bool { * self == INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_rxint_set (& self) -> bool { * self == INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_SET } } # [doc = "Field `INT_EVENT0_IMASK_RXINT` writer - Enable UART Receive Interrupt."] pub type INT_EVENT0_IMASK_RXINT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_RXINT_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_RXINT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_rxint_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_rxint_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_SET) } } # [doc = "Field `INT_EVENT0_IMASK_TXINT` reader - Enable UART Transmit Interrupt."] pub type INT_EVENT0_IMASK_TXINT_R = crate :: BitReader < INT_EVENT0_IMASK_TXINT_A > ; # [doc = "Enable UART Transmit Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_TXINT_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_TXINT_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_TXINT_SET = 1 , } impl From < INT_EVENT0_IMASK_TXINT_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_TXINT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_TXINT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_TXINT_A { match self . bits { false => INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_CLR , true => INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_txint_clr (& self) -> bool { * self == INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_txint_set (& self) -> bool { * self == INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_SET } } # [doc = "Field `INT_EVENT0_IMASK_TXINT` writer - Enable UART Transmit Interrupt."] pub type INT_EVENT0_IMASK_TXINT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_TXINT_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_TXINT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_txint_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_txint_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_SET) } } # [doc = "Field `INT_EVENT0_IMASK_EOT` reader - Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] pub type INT_EVENT0_IMASK_EOT_R = crate :: BitReader < INT_EVENT0_IMASK_EOT_A > ; # [doc = "Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_EOT_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_EOT_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_EOT_SET = 1 , } impl From < INT_EVENT0_IMASK_EOT_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_EOT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_EOT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_EOT_A { match self . bits { false => INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_CLR , true => INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_eot_clr (& self) -> bool { * self == INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_eot_set (& self) -> bool { * self == INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_SET } } # [doc = "Field `INT_EVENT0_IMASK_EOT` writer - Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] pub type INT_EVENT0_IMASK_EOT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_EOT_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_EOT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_eot_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_eot_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_SET) } } # [doc = "Field `INT_EVENT0_IMASK_ADDR_MATCH` reader - Enable Address Match Interrupt."] pub type INT_EVENT0_IMASK_ADDR_MATCH_R = crate :: BitReader < INT_EVENT0_IMASK_ADDR_MATCH_A > ; # [doc = "Enable Address Match Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_ADDR_MATCH_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_ADDR_MATCH_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_ADDR_MATCH_SET = 1 , } impl From < INT_EVENT0_IMASK_ADDR_MATCH_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_ADDR_MATCH_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_ADDR_MATCH_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_ADDR_MATCH_A { match self . bits { false => INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_CLR , true => INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_addr_match_clr (& self) -> bool { * self == INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_addr_match_set (& self) -> bool { * self == INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_SET } } # [doc = "Field `INT_EVENT0_IMASK_ADDR_MATCH` writer - Enable Address Match Interrupt."] pub type INT_EVENT0_IMASK_ADDR_MATCH_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_ADDR_MATCH_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_ADDR_MATCH_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_addr_match_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_addr_match_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_SET) } } # [doc = "Field `INT_EVENT0_IMASK_CTS` reader - Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] pub type INT_EVENT0_IMASK_CTS_R = crate :: BitReader < INT_EVENT0_IMASK_CTS_A > ; # [doc = "Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_CTS_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_CTS_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_CTS_SET = 1 , } impl From < INT_EVENT0_IMASK_CTS_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_CTS_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_CTS_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_CTS_A { match self . bits { false => INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_CLR , true => INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_cts_clr (& self) -> bool { * self == INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_cts_set (& self) -> bool { * self == INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_SET } } # [doc = "Field `INT_EVENT0_IMASK_CTS` writer - Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] pub type INT_EVENT0_IMASK_CTS_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_CTS_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_CTS_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_cts_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_cts_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DMA_DONE_RX` reader - Enable DMA Done on RX Event Channel"] pub type INT_EVENT0_IMASK_DMA_DONE_RX_R = crate :: BitReader < INT_EVENT0_IMASK_DMA_DONE_RX_A > ; # [doc = "Enable DMA Done on RX Event Channel\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DMA_DONE_RX_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DMA_DONE_RX_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DMA_DONE_RX_SET = 1 , } impl From < INT_EVENT0_IMASK_DMA_DONE_RX_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DMA_DONE_RX_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DMA_DONE_RX_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DMA_DONE_RX_A { match self . bits { false => INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_CLR , true => INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dma_done_rx_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dma_done_rx_set (& self) -> bool { * self == INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_SET } } # [doc = "Field `INT_EVENT0_IMASK_DMA_DONE_RX` writer - Enable DMA Done on RX Event Channel"] pub type INT_EVENT0_IMASK_DMA_DONE_RX_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DMA_DONE_RX_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DMA_DONE_RX_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dma_done_rx_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dma_done_rx_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DMA_DONE_TX` reader - Enable DMA Done on TX Event Channel"] pub type INT_EVENT0_IMASK_DMA_DONE_TX_R = crate :: BitReader < INT_EVENT0_IMASK_DMA_DONE_TX_A > ; # [doc = "Enable DMA Done on TX Event Channel\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DMA_DONE_TX_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DMA_DONE_TX_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DMA_DONE_TX_SET = 1 , } impl From < INT_EVENT0_IMASK_DMA_DONE_TX_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DMA_DONE_TX_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DMA_DONE_TX_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DMA_DONE_TX_A { match self . bits { false => INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_CLR , true => INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dma_done_tx_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dma_done_tx_set (& self) -> bool { * self == INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_SET } } # [doc = "Field `INT_EVENT0_IMASK_DMA_DONE_TX` writer - Enable DMA Done on TX Event Channel"] pub type INT_EVENT0_IMASK_DMA_DONE_TX_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DMA_DONE_TX_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DMA_DONE_TX_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dma_done_tx_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dma_done_tx_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_SET) } } # [doc = "Field `INT_EVENT0_IMASK_NERR` reader - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] pub type INT_EVENT0_IMASK_NERR_R = crate :: BitReader < INT_EVENT0_IMASK_NERR_A > ; # [doc = "Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_NERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_NERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_NERR_SET = 1 , } impl From < INT_EVENT0_IMASK_NERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_NERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_NERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_NERR_A { match self . bits { false => INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_CLR , true => INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_nerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_nerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_NERR` writer - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] pub type INT_EVENT0_IMASK_NERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_NERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_NERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_nerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_nerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_SET) } } impl R { # [doc = "Bit 0 - Enable UARTOUT Receive Time-Out Interrupt."] # [inline (always)] pub fn int_event0_imask_rtout (& self) -> INT_EVENT0_IMASK_RTOUT_R { INT_EVENT0_IMASK_RTOUT_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - Enable UART Framing Error Interrupt."] # [inline (always)] pub fn int_event0_imask_frmerr (& self) -> INT_EVENT0_IMASK_FRMERR_R { INT_EVENT0_IMASK_FRMERR_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - Enable UART Parity Error Interrupt."] # [inline (always)] pub fn int_event0_imask_parerr (& self) -> INT_EVENT0_IMASK_PARERR_R { INT_EVENT0_IMASK_PARERR_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - Enable UART Break Error Interrupt."] # [inline (always)] pub fn int_event0_imask_brkerr (& self) -> INT_EVENT0_IMASK_BRKERR_R { INT_EVENT0_IMASK_BRKERR_R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - Enable UART Receive Overrun Error Interrupt."] # [inline (always)] pub fn int_event0_imask_ovrerr (& self) -> INT_EVENT0_IMASK_OVRERR_R { INT_EVENT0_IMASK_OVRERR_R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - Enable Negative Edge on UARTxRXD Interrupt."] # [inline (always)] pub fn int_event0_imask_rxne (& self) -> INT_EVENT0_IMASK_RXNE_R { INT_EVENT0_IMASK_RXNE_R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - Enable Positive Edge on UARTxRXD Interrupt."] # [inline (always)] pub fn int_event0_imask_rxpe (& self) -> INT_EVENT0_IMASK_RXPE_R { INT_EVENT0_IMASK_RXPE_R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - Enable LIN Capture 0 / Match Interrupt ."] # [inline (always)] pub fn int_event0_imask_linc0 (& self) -> INT_EVENT0_IMASK_LINC0_R { INT_EVENT0_IMASK_LINC0_R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - Enable LIN Capture 1 Interrupt."] # [inline (always)] pub fn int_event0_imask_linc1 (& self) -> INT_EVENT0_IMASK_LINC1_R { INT_EVENT0_IMASK_LINC1_R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - Enable LIN Hardware Counter Overflow Interrupt."] # [inline (always)] pub fn int_event0_imask_linovf (& self) -> INT_EVENT0_IMASK_LINOVF_R { INT_EVENT0_IMASK_LINOVF_R :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - Enable UART Receive Interrupt."] # [inline (always)] pub fn int_event0_imask_rxint (& self) -> INT_EVENT0_IMASK_RXINT_R { INT_EVENT0_IMASK_RXINT_R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - Enable UART Transmit Interrupt."] # [inline (always)] pub fn int_event0_imask_txint (& self) -> INT_EVENT0_IMASK_TXINT_R { INT_EVENT0_IMASK_TXINT_R :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] # [inline (always)] pub fn int_event0_imask_eot (& self) -> INT_EVENT0_IMASK_EOT_R { INT_EVENT0_IMASK_EOT_R :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - Enable Address Match Interrupt."] # [inline (always)] pub fn int_event0_imask_addr_match (& self) -> INT_EVENT0_IMASK_ADDR_MATCH_R { INT_EVENT0_IMASK_ADDR_MATCH_R :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 14 - Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] # [inline (always)] pub fn int_event0_imask_cts (& self) -> INT_EVENT0_IMASK_CTS_R { INT_EVENT0_IMASK_CTS_R :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - Enable DMA Done on RX Event Channel"] # [inline (always)] pub fn int_event0_imask_dma_done_rx (& self) -> INT_EVENT0_IMASK_DMA_DONE_RX_R { INT_EVENT0_IMASK_DMA_DONE_RX_R :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bit 16 - Enable DMA Done on TX Event Channel"] # [inline (always)] pub fn int_event0_imask_dma_done_tx (& self) -> INT_EVENT0_IMASK_DMA_DONE_TX_R { INT_EVENT0_IMASK_DMA_DONE_TX_R :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] # [inline (always)] pub fn int_event0_imask_nerr (& self) -> INT_EVENT0_IMASK_NERR_R { INT_EVENT0_IMASK_NERR_R :: new (((self . bits >> 17) & 1) != 0) } } impl W { # [doc = "Bit 0 - Enable UARTOUT Receive Time-Out Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_rtout (& mut self) -> INT_EVENT0_IMASK_RTOUT_W < INT_EVENT0_IMASK_SPEC , 0 > { INT_EVENT0_IMASK_RTOUT_W :: new (self) } # [doc = "Bit 1 - Enable UART Framing Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_frmerr (& mut self) -> INT_EVENT0_IMASK_FRMERR_W <'_,  INT_EVENT0_IMASK_SPEC , 1 > { INT_EVENT0_IMASK_FRMERR_W :: new (self) } # [doc = "Bit 2 - Enable UART Parity Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_parerr (& mut self) -> INT_EVENT0_IMASK_PARERR_W < INT_EVENT0_IMASK_SPEC , 2 > { INT_EVENT0_IMASK_PARERR_W :: new (self) } # [doc = "Bit 3 - Enable UART Break Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_brkerr (& mut self) -> INT_EVENT0_IMASK_BRKERR_W < INT_EVENT0_IMASK_SPEC , 3 > { INT_EVENT0_IMASK_BRKERR_W :: new (self) } # [doc = "Bit 4 - Enable UART Receive Overrun Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_ovrerr (& mut self) -> INT_EVENT0_IMASK_OVRERR_W < INT_EVENT0_IMASK_SPEC , 4 > { INT_EVENT0_IMASK_OVRERR_W :: new (self) } # [doc = "Bit 5 - Enable Negative Edge on UARTxRXD Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_rxne (& mut self) -> INT_EVENT0_IMASK_RXNE_W < INT_EVENT0_IMASK_SPEC , 5 > { INT_EVENT0_IMASK_RXNE_W :: new (self) } # [doc = "Bit 6 - Enable Positive Edge on UARTxRXD Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_rxpe (& mut self) -> INT_EVENT0_IMASK_RXPE_W < INT_EVENT0_IMASK_SPEC , 6 > { INT_EVENT0_IMASK_RXPE_W :: new (self) } # [doc = "Bit 7 - Enable LIN Capture 0 / Match Interrupt ."] # [inline (always)] # [must_use] pub fn int_event0_imask_linc0 (& mut self) -> INT_EVENT0_IMASK_LINC0_W < INT_EVENT0_IMASK_SPEC , 7 > { INT_EVENT0_IMASK_LINC0_W :: new (self) } # [doc = "Bit 8 - Enable LIN Capture 1 Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_linc1 (& mut self) -> INT_EVENT0_IMASK_LINC1_W < INT_EVENT0_IMASK_SPEC , 8 > { INT_EVENT0_IMASK_LINC1_W :: new (self) } # [doc = "Bit 9 - Enable LIN Hardware Counter Overflow Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_linovf (& mut self) -> INT_EVENT0_IMASK_LINOVF_W < INT_EVENT0_IMASK_SPEC , 9 > { INT_EVENT0_IMASK_LINOVF_W :: new (self) } # [doc = "Bit 10 - Enable UART Receive Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_rxint (& mut self) -> INT_EVENT0_IMASK_RXINT_W < INT_EVENT0_IMASK_SPEC , 10 > { INT_EVENT0_IMASK_RXINT_W :: new (self) } # [doc = "Bit 11 - Enable UART Transmit Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_txint (& mut self) -> INT_EVENT0_IMASK_TXINT_W < INT_EVENT0_IMASK_SPEC , 11 > { INT_EVENT0_IMASK_TXINT_W :: new (self) } # [doc = "Bit 12 - Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] # [inline (always)] # [must_use] pub fn int_event0_imask_eot (& mut self) -> INT_EVENT0_IMASK_EOT_W < INT_EVENT0_IMASK_SPEC , 12 > { INT_EVENT0_IMASK_EOT_W :: new (self) } # [doc = "Bit 13 - Enable Address Match Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_addr_match (& mut self) -> INT_EVENT0_IMASK_ADDR_MATCH_W < INT_EVENT0_IMASK_SPEC , 13 > { INT_EVENT0_IMASK_ADDR_MATCH_W :: new (self) } # [doc = "Bit 14 - Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] # [inline (always)] # [must_use] pub fn int_event0_imask_cts (& mut self) -> INT_EVENT0_IMASK_CTS_W < INT_EVENT0_IMASK_SPEC , 14 > { INT_EVENT0_IMASK_CTS_W :: new (self) } # [doc = "Bit 15 - Enable DMA Done on RX Event Channel"] # [inline (always)] # [must_use] pub fn int_event0_imask_dma_done_rx (& mut self) -> INT_EVENT0_IMASK_DMA_DONE_RX_W < INT_EVENT0_IMASK_SPEC , 15 > { INT_EVENT0_IMASK_DMA_DONE_RX_W :: new (self) } # [doc = "Bit 16 - Enable DMA Done on TX Event Channel"] # [inline (always)] # [must_use] pub fn int_event0_imask_dma_done_tx (& mut self) -> INT_EVENT0_IMASK_DMA_DONE_TX_W < INT_EVENT0_IMASK_SPEC , 16 > { INT_EVENT0_IMASK_DMA_DONE_TX_W :: new (self) } # [doc = "Bit 17 - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] # [inline (always)] # [must_use] pub fn int_event0_imask_nerr (& mut self) -> INT_EVENT0_IMASK_NERR_W < INT_EVENT0_IMASK_SPEC , 17 > { INT_EVENT0_IMASK_NERR_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Interrupt mask\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_event0_imask::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_event0_imask::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct INT_EVENT0_IMASK_SPEC ; impl crate :: RegisterSpec for INT_EVENT0_IMASK_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`int_event0_imask::R`](R) reader structure"] impl crate :: Readable for INT_EVENT0_IMASK_SPEC { } # [doc = "`write(|w| ..)` method takes [`int_event0_imask::W`](W) writer structure"] impl crate :: Writable for INT_EVENT0_IMASK_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets INT_EVENT0_IMASK to value 0"] impl crate :: Resettable for INT_EVENT0_IMASK_SPEC { const RESET_VALUE : Self :: Ux = 0 ; }
[INFO] [stdout]   |                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                       +++
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing
[INFO] [stdout]  --> src/uart0/int_event0_imask.rs:1:40969
[INFO] [stdout]   |
[INFO] [stdout] 1 | ...mask_parerr (& mut self) -> INT_EVENT0_IMASK_PARERR_W < INT_EVENT0_IMASK_SPEC , 2 > { INT_EVENT0_IMASK_PARERR_W :: new (self) } # ...
[INFO] [stdout]   |                 ^^^^^^^^^^     ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here
[INFO] [stdout]   |                 |
[INFO] [stdout]   |                 the lifetime is elided here
[INFO] [stdout]   |
[INFO] [stdout]   = help: the same lifetime is referred to in inconsistent ways, making the signature confusing
[INFO] [stdout] help: use `'_` for type paths
[INFO] [stdout]   |
[INFO] [stdout] 1 | # [doc = "Register `INT_EVENT0_IMASK` reader"] pub type R = crate :: R < INT_EVENT0_IMASK_SPEC > ; # [doc = "Register `INT_EVENT0_IMASK` writer"] pub type W = crate :: W < INT_EVENT0_IMASK_SPEC > ; # [doc = "Field `INT_EVENT0_IMASK_RTOUT` reader - Enable UARTOUT Receive Time-Out Interrupt."] pub type INT_EVENT0_IMASK_RTOUT_R = crate :: BitReader < INT_EVENT0_IMASK_RTOUT_A > ; # [doc = "Enable UARTOUT Receive Time-Out Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_RTOUT_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_RTOUT_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_RTOUT_SET = 1 , } impl From < INT_EVENT0_IMASK_RTOUT_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_RTOUT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_RTOUT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_RTOUT_A { match self . bits { false => INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_CLR , true => INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_rtout_clr (& self) -> bool { * self == INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_rtout_set (& self) -> bool { * self == INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_SET } } # [doc = "Field `INT_EVENT0_IMASK_RTOUT` writer - Enable UARTOUT Receive Time-Out Interrupt."] pub type INT_EVENT0_IMASK_RTOUT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_RTOUT_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_RTOUT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_rtout_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_rtout_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_SET) } } # [doc = "Field `INT_EVENT0_IMASK_FRMERR` reader - Enable UART Framing Error Interrupt."] pub type INT_EVENT0_IMASK_FRMERR_R = crate :: BitReader < INT_EVENT0_IMASK_FRMERR_A > ; # [doc = "Enable UART Framing Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_FRMERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_FRMERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_FRMERR_SET = 1 , } impl From < INT_EVENT0_IMASK_FRMERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_FRMERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_FRMERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_FRMERR_A { match self . bits { false => INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_CLR , true => INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_frmerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_frmerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_FRMERR` writer - Enable UART Framing Error Interrupt."] pub type INT_EVENT0_IMASK_FRMERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_FRMERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_FRMERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_frmerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_frmerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_SET) } } # [doc = "Field `INT_EVENT0_IMASK_PARERR` reader - Enable UART Parity Error Interrupt."] pub type INT_EVENT0_IMASK_PARERR_R = crate :: BitReader < INT_EVENT0_IMASK_PARERR_A > ; # [doc = "Enable UART Parity Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_PARERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_PARERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_PARERR_SET = 1 , } impl From < INT_EVENT0_IMASK_PARERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_PARERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_PARERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_PARERR_A { match self . bits { false => INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_CLR , true => INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_parerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_parerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_PARERR` writer - Enable UART Parity Error Interrupt."] pub type INT_EVENT0_IMASK_PARERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_PARERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_PARERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_parerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_parerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_SET) } } # [doc = "Field `INT_EVENT0_IMASK_BRKERR` reader - Enable UART Break Error Interrupt."] pub type INT_EVENT0_IMASK_BRKERR_R = crate :: BitReader < INT_EVENT0_IMASK_BRKERR_A > ; # [doc = "Enable UART Break Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_BRKERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_BRKERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_BRKERR_SET = 1 , } impl From < INT_EVENT0_IMASK_BRKERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_BRKERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_BRKERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_BRKERR_A { match self . bits { false => INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_CLR , true => INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_brkerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_brkerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_BRKERR` writer - Enable UART Break Error Interrupt."] pub type INT_EVENT0_IMASK_BRKERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_BRKERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_BRKERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_brkerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_brkerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_SET) } } # [doc = "Field `INT_EVENT0_IMASK_OVRERR` reader - Enable UART Receive Overrun Error Interrupt."] pub type INT_EVENT0_IMASK_OVRERR_R = crate :: BitReader < INT_EVENT0_IMASK_OVRERR_A > ; # [doc = "Enable UART Receive Overrun Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_OVRERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_OVRERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_OVRERR_SET = 1 , } impl From < INT_EVENT0_IMASK_OVRERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_OVRERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_OVRERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_OVRERR_A { match self . bits { false => INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_CLR , true => INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_ovrerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_ovrerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_OVRERR` writer - Enable UART Receive Overrun Error Interrupt."] pub type INT_EVENT0_IMASK_OVRERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_OVRERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_OVRERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_ovrerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_ovrerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_SET) } } # [doc = "Field `INT_EVENT0_IMASK_RXNE` reader - Enable Negative Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_IMASK_RXNE_R = crate :: BitReader < INT_EVENT0_IMASK_RXNE_A > ; # [doc = "Enable Negative Edge on UARTxRXD Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_RXNE_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_RXNE_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_RXNE_SET = 1 , } impl From < INT_EVENT0_IMASK_RXNE_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_RXNE_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_RXNE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_RXNE_A { match self . bits { false => INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_CLR , true => INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_rxne_clr (& self) -> bool { * self == INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_rxne_set (& self) -> bool { * self == INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_SET } } # [doc = "Field `INT_EVENT0_IMASK_RXNE` writer - Enable Negative Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_IMASK_RXNE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_RXNE_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_RXNE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_rxne_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_rxne_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_SET) } } # [doc = "Field `INT_EVENT0_IMASK_RXPE` reader - Enable Positive Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_IMASK_RXPE_R = crate :: BitReader < INT_EVENT0_IMASK_RXPE_A > ; # [doc = "Enable Positive Edge on UARTxRXD Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_RXPE_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_RXPE_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_RXPE_SET = 1 , } impl From < INT_EVENT0_IMASK_RXPE_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_RXPE_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_RXPE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_RXPE_A { match self . bits { false => INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_CLR , true => INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_rxpe_clr (& self) -> bool { * self == INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_rxpe_set (& self) -> bool { * self == INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_SET } } # [doc = "Field `INT_EVENT0_IMASK_RXPE` writer - Enable Positive Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_IMASK_RXPE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_RXPE_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_RXPE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_rxpe_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_rxpe_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_SET) } } # [doc = "Field `INT_EVENT0_IMASK_LINC0` reader - Enable LIN Capture 0 / Match Interrupt ."] pub type INT_EVENT0_IMASK_LINC0_R = crate :: BitReader < INT_EVENT0_IMASK_LINC0_A > ; # [doc = "Enable LIN Capture 0 / Match Interrupt .\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_LINC0_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_LINC0_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_LINC0_SET = 1 , } impl From < INT_EVENT0_IMASK_LINC0_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_LINC0_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_LINC0_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_LINC0_A { match self . bits { false => INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_CLR , true => INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_linc0_clr (& self) -> bool { * self == INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_linc0_set (& self) -> bool { * self == INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_SET } } # [doc = "Field `INT_EVENT0_IMASK_LINC0` writer - Enable LIN Capture 0 / Match Interrupt ."] pub type INT_EVENT0_IMASK_LINC0_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_LINC0_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_LINC0_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_linc0_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_linc0_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_SET) } } # [doc = "Field `INT_EVENT0_IMASK_LINC1` reader - Enable LIN Capture 1 Interrupt."] pub type INT_EVENT0_IMASK_LINC1_R = crate :: BitReader < INT_EVENT0_IMASK_LINC1_A > ; # [doc = "Enable LIN Capture 1 Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_LINC1_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_LINC1_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_LINC1_SET = 1 , } impl From < INT_EVENT0_IMASK_LINC1_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_LINC1_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_LINC1_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_LINC1_A { match self . bits { false => INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_CLR , true => INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_linc1_clr (& self) -> bool { * self == INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_linc1_set (& self) -> bool { * self == INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_SET } } # [doc = "Field `INT_EVENT0_IMASK_LINC1` writer - Enable LIN Capture 1 Interrupt."] pub type INT_EVENT0_IMASK_LINC1_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_LINC1_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_LINC1_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_linc1_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_linc1_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_SET) } } # [doc = "Field `INT_EVENT0_IMASK_LINOVF` reader - Enable LIN Hardware Counter Overflow Interrupt."] pub type INT_EVENT0_IMASK_LINOVF_R = crate :: BitReader < INT_EVENT0_IMASK_LINOVF_A > ; # [doc = "Enable LIN Hardware Counter Overflow Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_LINOVF_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_LINOVF_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_LINOVF_SET = 1 , } impl From < INT_EVENT0_IMASK_LINOVF_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_LINOVF_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_LINOVF_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_LINOVF_A { match self . bits { false => INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_CLR , true => INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_linovf_clr (& self) -> bool { * self == INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_linovf_set (& self) -> bool { * self == INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_SET } } # [doc = "Field `INT_EVENT0_IMASK_LINOVF` writer - Enable LIN Hardware Counter Overflow Interrupt."] pub type INT_EVENT0_IMASK_LINOVF_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_LINOVF_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_LINOVF_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_linovf_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_linovf_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_SET) } } # [doc = "Field `INT_EVENT0_IMASK_RXINT` reader - Enable UART Receive Interrupt."] pub type INT_EVENT0_IMASK_RXINT_R = crate :: BitReader < INT_EVENT0_IMASK_RXINT_A > ; # [doc = "Enable UART Receive Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_RXINT_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_RXINT_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_RXINT_SET = 1 , } impl From < INT_EVENT0_IMASK_RXINT_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_RXINT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_RXINT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_RXINT_A { match self . bits { false => INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_CLR , true => INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_rxint_clr (& self) -> bool { * self == INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_rxint_set (& self) -> bool { * self == INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_SET } } # [doc = "Field `INT_EVENT0_IMASK_RXINT` writer - Enable UART Receive Interrupt."] pub type INT_EVENT0_IMASK_RXINT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_RXINT_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_RXINT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_rxint_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_rxint_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_SET) } } # [doc = "Field `INT_EVENT0_IMASK_TXINT` reader - Enable UART Transmit Interrupt."] pub type INT_EVENT0_IMASK_TXINT_R = crate :: BitReader < INT_EVENT0_IMASK_TXINT_A > ; # [doc = "Enable UART Transmit Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_TXINT_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_TXINT_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_TXINT_SET = 1 , } impl From < INT_EVENT0_IMASK_TXINT_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_TXINT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_TXINT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_TXINT_A { match self . bits { false => INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_CLR , true => INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_txint_clr (& self) -> bool { * self == INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_txint_set (& self) -> bool { * self == INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_SET } } # [doc = "Field `INT_EVENT0_IMASK_TXINT` writer - Enable UART Transmit Interrupt."] pub type INT_EVENT0_IMASK_TXINT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_TXINT_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_TXINT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_txint_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_txint_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_SET) } } # [doc = "Field `INT_EVENT0_IMASK_EOT` reader - Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] pub type INT_EVENT0_IMASK_EOT_R = crate :: BitReader < INT_EVENT0_IMASK_EOT_A > ; # [doc = "Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_EOT_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_EOT_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_EOT_SET = 1 , } impl From < INT_EVENT0_IMASK_EOT_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_EOT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_EOT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_EOT_A { match self . bits { false => INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_CLR , true => INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_eot_clr (& self) -> bool { * self == INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_eot_set (& self) -> bool { * self == INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_SET } } # [doc = "Field `INT_EVENT0_IMASK_EOT` writer - Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] pub type INT_EVENT0_IMASK_EOT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_EOT_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_EOT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_eot_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_eot_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_SET) } } # [doc = "Field `INT_EVENT0_IMASK_ADDR_MATCH` reader - Enable Address Match Interrupt."] pub type INT_EVENT0_IMASK_ADDR_MATCH_R = crate :: BitReader < INT_EVENT0_IMASK_ADDR_MATCH_A > ; # [doc = "Enable Address Match Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_ADDR_MATCH_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_ADDR_MATCH_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_ADDR_MATCH_SET = 1 , } impl From < INT_EVENT0_IMASK_ADDR_MATCH_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_ADDR_MATCH_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_ADDR_MATCH_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_ADDR_MATCH_A { match self . bits { false => INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_CLR , true => INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_addr_match_clr (& self) -> bool { * self == INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_addr_match_set (& self) -> bool { * self == INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_SET } } # [doc = "Field `INT_EVENT0_IMASK_ADDR_MATCH` writer - Enable Address Match Interrupt."] pub type INT_EVENT0_IMASK_ADDR_MATCH_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_ADDR_MATCH_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_ADDR_MATCH_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_addr_match_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_addr_match_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_SET) } } # [doc = "Field `INT_EVENT0_IMASK_CTS` reader - Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] pub type INT_EVENT0_IMASK_CTS_R = crate :: BitReader < INT_EVENT0_IMASK_CTS_A > ; # [doc = "Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_CTS_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_CTS_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_CTS_SET = 1 , } impl From < INT_EVENT0_IMASK_CTS_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_CTS_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_CTS_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_CTS_A { match self . bits { false => INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_CLR , true => INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_cts_clr (& self) -> bool { * self == INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_cts_set (& self) -> bool { * self == INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_SET } } # [doc = "Field `INT_EVENT0_IMASK_CTS` writer - Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] pub type INT_EVENT0_IMASK_CTS_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_CTS_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_CTS_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_cts_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_cts_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DMA_DONE_RX` reader - Enable DMA Done on RX Event Channel"] pub type INT_EVENT0_IMASK_DMA_DONE_RX_R = crate :: BitReader < INT_EVENT0_IMASK_DMA_DONE_RX_A > ; # [doc = "Enable DMA Done on RX Event Channel\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DMA_DONE_RX_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DMA_DONE_RX_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DMA_DONE_RX_SET = 1 , } impl From < INT_EVENT0_IMASK_DMA_DONE_RX_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DMA_DONE_RX_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DMA_DONE_RX_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DMA_DONE_RX_A { match self . bits { false => INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_CLR , true => INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dma_done_rx_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dma_done_rx_set (& self) -> bool { * self == INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_SET } } # [doc = "Field `INT_EVENT0_IMASK_DMA_DONE_RX` writer - Enable DMA Done on RX Event Channel"] pub type INT_EVENT0_IMASK_DMA_DONE_RX_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DMA_DONE_RX_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DMA_DONE_RX_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dma_done_rx_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dma_done_rx_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DMA_DONE_TX` reader - Enable DMA Done on TX Event Channel"] pub type INT_EVENT0_IMASK_DMA_DONE_TX_R = crate :: BitReader < INT_EVENT0_IMASK_DMA_DONE_TX_A > ; # [doc = "Enable DMA Done on TX Event Channel\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DMA_DONE_TX_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DMA_DONE_TX_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DMA_DONE_TX_SET = 1 , } impl From < INT_EVENT0_IMASK_DMA_DONE_TX_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DMA_DONE_TX_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DMA_DONE_TX_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DMA_DONE_TX_A { match self . bits { false => INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_CLR , true => INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dma_done_tx_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dma_done_tx_set (& self) -> bool { * self == INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_SET } } # [doc = "Field `INT_EVENT0_IMASK_DMA_DONE_TX` writer - Enable DMA Done on TX Event Channel"] pub type INT_EVENT0_IMASK_DMA_DONE_TX_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DMA_DONE_TX_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DMA_DONE_TX_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dma_done_tx_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dma_done_tx_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_SET) } } # [doc = "Field `INT_EVENT0_IMASK_NERR` reader - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] pub type INT_EVENT0_IMASK_NERR_R = crate :: BitReader < INT_EVENT0_IMASK_NERR_A > ; # [doc = "Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_NERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_NERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_NERR_SET = 1 , } impl From < INT_EVENT0_IMASK_NERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_NERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_NERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_NERR_A { match self . bits { false => INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_CLR , true => INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_nerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_nerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_NERR` writer - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] pub type INT_EVENT0_IMASK_NERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_NERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_NERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_nerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_nerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_SET) } } impl R { # [doc = "Bit 0 - Enable UARTOUT Receive Time-Out Interrupt."] # [inline (always)] pub fn int_event0_imask_rtout (& self) -> INT_EVENT0_IMASK_RTOUT_R { INT_EVENT0_IMASK_RTOUT_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - Enable UART Framing Error Interrupt."] # [inline (always)] pub fn int_event0_imask_frmerr (& self) -> INT_EVENT0_IMASK_FRMERR_R { INT_EVENT0_IMASK_FRMERR_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - Enable UART Parity Error Interrupt."] # [inline (always)] pub fn int_event0_imask_parerr (& self) -> INT_EVENT0_IMASK_PARERR_R { INT_EVENT0_IMASK_PARERR_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - Enable UART Break Error Interrupt."] # [inline (always)] pub fn int_event0_imask_brkerr (& self) -> INT_EVENT0_IMASK_BRKERR_R { INT_EVENT0_IMASK_BRKERR_R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - Enable UART Receive Overrun Error Interrupt."] # [inline (always)] pub fn int_event0_imask_ovrerr (& self) -> INT_EVENT0_IMASK_OVRERR_R { INT_EVENT0_IMASK_OVRERR_R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - Enable Negative Edge on UARTxRXD Interrupt."] # [inline (always)] pub fn int_event0_imask_rxne (& self) -> INT_EVENT0_IMASK_RXNE_R { INT_EVENT0_IMASK_RXNE_R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - Enable Positive Edge on UARTxRXD Interrupt."] # [inline (always)] pub fn int_event0_imask_rxpe (& self) -> INT_EVENT0_IMASK_RXPE_R { INT_EVENT0_IMASK_RXPE_R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - Enable LIN Capture 0 / Match Interrupt ."] # [inline (always)] pub fn int_event0_imask_linc0 (& self) -> INT_EVENT0_IMASK_LINC0_R { INT_EVENT0_IMASK_LINC0_R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - Enable LIN Capture 1 Interrupt."] # [inline (always)] pub fn int_event0_imask_linc1 (& self) -> INT_EVENT0_IMASK_LINC1_R { INT_EVENT0_IMASK_LINC1_R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - Enable LIN Hardware Counter Overflow Interrupt."] # [inline (always)] pub fn int_event0_imask_linovf (& self) -> INT_EVENT0_IMASK_LINOVF_R { INT_EVENT0_IMASK_LINOVF_R :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - Enable UART Receive Interrupt."] # [inline (always)] pub fn int_event0_imask_rxint (& self) -> INT_EVENT0_IMASK_RXINT_R { INT_EVENT0_IMASK_RXINT_R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - Enable UART Transmit Interrupt."] # [inline (always)] pub fn int_event0_imask_txint (& self) -> INT_EVENT0_IMASK_TXINT_R { INT_EVENT0_IMASK_TXINT_R :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] # [inline (always)] pub fn int_event0_imask_eot (& self) -> INT_EVENT0_IMASK_EOT_R { INT_EVENT0_IMASK_EOT_R :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - Enable Address Match Interrupt."] # [inline (always)] pub fn int_event0_imask_addr_match (& self) -> INT_EVENT0_IMASK_ADDR_MATCH_R { INT_EVENT0_IMASK_ADDR_MATCH_R :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 14 - Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] # [inline (always)] pub fn int_event0_imask_cts (& self) -> INT_EVENT0_IMASK_CTS_R { INT_EVENT0_IMASK_CTS_R :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - Enable DMA Done on RX Event Channel"] # [inline (always)] pub fn int_event0_imask_dma_done_rx (& self) -> INT_EVENT0_IMASK_DMA_DONE_RX_R { INT_EVENT0_IMASK_DMA_DONE_RX_R :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bit 16 - Enable DMA Done on TX Event Channel"] # [inline (always)] pub fn int_event0_imask_dma_done_tx (& self) -> INT_EVENT0_IMASK_DMA_DONE_TX_R { INT_EVENT0_IMASK_DMA_DONE_TX_R :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] # [inline (always)] pub fn int_event0_imask_nerr (& self) -> INT_EVENT0_IMASK_NERR_R { INT_EVENT0_IMASK_NERR_R :: new (((self . bits >> 17) & 1) != 0) } } impl W { # [doc = "Bit 0 - Enable UARTOUT Receive Time-Out Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_rtout (& mut self) -> INT_EVENT0_IMASK_RTOUT_W < INT_EVENT0_IMASK_SPEC , 0 > { INT_EVENT0_IMASK_RTOUT_W :: new (self) } # [doc = "Bit 1 - Enable UART Framing Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_frmerr (& mut self) -> INT_EVENT0_IMASK_FRMERR_W < INT_EVENT0_IMASK_SPEC , 1 > { INT_EVENT0_IMASK_FRMERR_W :: new (self) } # [doc = "Bit 2 - Enable UART Parity Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_parerr (& mut self) -> INT_EVENT0_IMASK_PARERR_W <'_,  INT_EVENT0_IMASK_SPEC , 2 > { INT_EVENT0_IMASK_PARERR_W :: new (self) } # [doc = "Bit 3 - Enable UART Break Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_brkerr (& mut self) -> INT_EVENT0_IMASK_BRKERR_W < INT_EVENT0_IMASK_SPEC , 3 > { INT_EVENT0_IMASK_BRKERR_W :: new (self) } # [doc = "Bit 4 - Enable UART Receive Overrun Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_ovrerr (& mut self) -> INT_EVENT0_IMASK_OVRERR_W < INT_EVENT0_IMASK_SPEC , 4 > { INT_EVENT0_IMASK_OVRERR_W :: new (self) } # [doc = "Bit 5 - Enable Negative Edge on UARTxRXD Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_rxne (& mut self) -> INT_EVENT0_IMASK_RXNE_W < INT_EVENT0_IMASK_SPEC , 5 > { INT_EVENT0_IMASK_RXNE_W :: new (self) } # [doc = "Bit 6 - Enable Positive Edge on UARTxRXD Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_rxpe (& mut self) -> INT_EVENT0_IMASK_RXPE_W < INT_EVENT0_IMASK_SPEC , 6 > { INT_EVENT0_IMASK_RXPE_W :: new (self) } # [doc = "Bit 7 - Enable LIN Capture 0 / Match Interrupt ."] # [inline (always)] # [must_use] pub fn int_event0_imask_linc0 (& mut self) -> INT_EVENT0_IMASK_LINC0_W < INT_EVENT0_IMASK_SPEC , 7 > { INT_EVENT0_IMASK_LINC0_W :: new (self) } # [doc = "Bit 8 - Enable LIN Capture 1 Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_linc1 (& mut self) -> INT_EVENT0_IMASK_LINC1_W < INT_EVENT0_IMASK_SPEC , 8 > { INT_EVENT0_IMASK_LINC1_W :: new (self) } # [doc = "Bit 9 - Enable LIN Hardware Counter Overflow Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_linovf (& mut self) -> INT_EVENT0_IMASK_LINOVF_W < INT_EVENT0_IMASK_SPEC , 9 > { INT_EVENT0_IMASK_LINOVF_W :: new (self) } # [doc = "Bit 10 - Enable UART Receive Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_rxint (& mut self) -> INT_EVENT0_IMASK_RXINT_W < INT_EVENT0_IMASK_SPEC , 10 > { INT_EVENT0_IMASK_RXINT_W :: new (self) } # [doc = "Bit 11 - Enable UART Transmit Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_txint (& mut self) -> INT_EVENT0_IMASK_TXINT_W < INT_EVENT0_IMASK_SPEC , 11 > { INT_EVENT0_IMASK_TXINT_W :: new (self) } # [doc = "Bit 12 - Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] # [inline (always)] # [must_use] pub fn int_event0_imask_eot (& mut self) -> INT_EVENT0_IMASK_EOT_W < INT_EVENT0_IMASK_SPEC , 12 > { INT_EVENT0_IMASK_EOT_W :: new (self) } # [doc = "Bit 13 - Enable Address Match Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_addr_match (& mut self) -> INT_EVENT0_IMASK_ADDR_MATCH_W < INT_EVENT0_IMASK_SPEC , 13 > { INT_EVENT0_IMASK_ADDR_MATCH_W :: new (self) } # [doc = "Bit 14 - Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] # [inline (always)] # [must_use] pub fn int_event0_imask_cts (& mut self) -> INT_EVENT0_IMASK_CTS_W < INT_EVENT0_IMASK_SPEC , 14 > { INT_EVENT0_IMASK_CTS_W :: new (self) } # [doc = "Bit 15 - Enable DMA Done on RX Event Channel"] # [inline (always)] # [must_use] pub fn int_event0_imask_dma_done_rx (& mut self) -> INT_EVENT0_IMASK_DMA_DONE_RX_W < INT_EVENT0_IMASK_SPEC , 15 > { INT_EVENT0_IMASK_DMA_DONE_RX_W :: new (self) } # [doc = "Bit 16 - Enable DMA Done on TX Event Channel"] # [inline (always)] # [must_use] pub fn int_event0_imask_dma_done_tx (& mut self) -> INT_EVENT0_IMASK_DMA_DONE_TX_W < INT_EVENT0_IMASK_SPEC , 16 > { INT_EVENT0_IMASK_DMA_DONE_TX_W :: new (self) } # [doc = "Bit 17 - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] # [inline (always)] # [must_use] pub fn int_event0_imask_nerr (& mut self) -> INT_EVENT0_IMASK_NERR_W < INT_EVENT0_IMASK_SPEC , 17 > { INT_EVENT0_IMASK_NERR_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Interrupt mask\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_event0_imask::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_event0_imask::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct INT_EVENT0_IMASK_SPEC ; impl crate :: RegisterSpec for INT_EVENT0_IMASK_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`int_event0_imask::R`](R) reader structure"] impl crate :: Readable for INT_EVENT0_IMASK_SPEC { } # [doc = "`write(|w| ..)` method takes [`int_event0_imask::W`](W) writer structure"] impl crate :: Writable for INT_EVENT0_IMASK_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets INT_EVENT0_IMASK to value 0"] impl crate :: Resettable for INT_EVENT0_IMASK_SPEC { const RESET_VALUE : Self :: Ux = 0 ; }
[INFO] [stdout]   |                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                   +++
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing
[INFO] [stdout]  --> src/uart0/int_event0_imask.rs:1:41204
[INFO] [stdout]   |
[INFO] [stdout] 1 | ...mask_brkerr (& mut self) -> INT_EVENT0_IMASK_BRKERR_W < INT_EVENT0_IMASK_SPEC , 3 > { INT_EVENT0_IMASK_BRKERR_W :: new (self) } # ...
[INFO] [stdout]   |                 ^^^^^^^^^^     ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here
[INFO] [stdout]   |                 |
[INFO] [stdout]   |                 the lifetime is elided here
[INFO] [stdout]   |
[INFO] [stdout]   = help: the same lifetime is referred to in inconsistent ways, making the signature confusing
[INFO] [stdout] help: use `'_` for type paths
[INFO] [stdout]   |
[INFO] [stdout] 1 | # [doc = "Register `INT_EVENT0_IMASK` reader"] pub type R = crate :: R < INT_EVENT0_IMASK_SPEC > ; # [doc = "Register `INT_EVENT0_IMASK` writer"] pub type W = crate :: W < INT_EVENT0_IMASK_SPEC > ; # [doc = "Field `INT_EVENT0_IMASK_RTOUT` reader - Enable UARTOUT Receive Time-Out Interrupt."] pub type INT_EVENT0_IMASK_RTOUT_R = crate :: BitReader < INT_EVENT0_IMASK_RTOUT_A > ; # [doc = "Enable UARTOUT Receive Time-Out Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_RTOUT_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_RTOUT_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_RTOUT_SET = 1 , } impl From < INT_EVENT0_IMASK_RTOUT_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_RTOUT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_RTOUT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_RTOUT_A { match self . bits { false => INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_CLR , true => INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_rtout_clr (& self) -> bool { * self == INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_rtout_set (& self) -> bool { * self == INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_SET } } # [doc = "Field `INT_EVENT0_IMASK_RTOUT` writer - Enable UARTOUT Receive Time-Out Interrupt."] pub type INT_EVENT0_IMASK_RTOUT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_RTOUT_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_RTOUT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_rtout_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_rtout_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_SET) } } # [doc = "Field `INT_EVENT0_IMASK_FRMERR` reader - Enable UART Framing Error Interrupt."] pub type INT_EVENT0_IMASK_FRMERR_R = crate :: BitReader < INT_EVENT0_IMASK_FRMERR_A > ; # [doc = "Enable UART Framing Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_FRMERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_FRMERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_FRMERR_SET = 1 , } impl From < INT_EVENT0_IMASK_FRMERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_FRMERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_FRMERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_FRMERR_A { match self . bits { false => INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_CLR , true => INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_frmerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_frmerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_FRMERR` writer - Enable UART Framing Error Interrupt."] pub type INT_EVENT0_IMASK_FRMERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_FRMERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_FRMERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_frmerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_frmerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_SET) } } # [doc = "Field `INT_EVENT0_IMASK_PARERR` reader - Enable UART Parity Error Interrupt."] pub type INT_EVENT0_IMASK_PARERR_R = crate :: BitReader < INT_EVENT0_IMASK_PARERR_A > ; # [doc = "Enable UART Parity Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_PARERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_PARERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_PARERR_SET = 1 , } impl From < INT_EVENT0_IMASK_PARERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_PARERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_PARERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_PARERR_A { match self . bits { false => INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_CLR , true => INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_parerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_parerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_PARERR` writer - Enable UART Parity Error Interrupt."] pub type INT_EVENT0_IMASK_PARERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_PARERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_PARERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_parerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_parerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_SET) } } # [doc = "Field `INT_EVENT0_IMASK_BRKERR` reader - Enable UART Break Error Interrupt."] pub type INT_EVENT0_IMASK_BRKERR_R = crate :: BitReader < INT_EVENT0_IMASK_BRKERR_A > ; # [doc = "Enable UART Break Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_BRKERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_BRKERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_BRKERR_SET = 1 , } impl From < INT_EVENT0_IMASK_BRKERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_BRKERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_BRKERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_BRKERR_A { match self . bits { false => INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_CLR , true => INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_brkerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_brkerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_BRKERR` writer - Enable UART Break Error Interrupt."] pub type INT_EVENT0_IMASK_BRKERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_BRKERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_BRKERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_brkerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_brkerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_SET) } } # [doc = "Field `INT_EVENT0_IMASK_OVRERR` reader - Enable UART Receive Overrun Error Interrupt."] pub type INT_EVENT0_IMASK_OVRERR_R = crate :: BitReader < INT_EVENT0_IMASK_OVRERR_A > ; # [doc = "Enable UART Receive Overrun Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_OVRERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_OVRERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_OVRERR_SET = 1 , } impl From < INT_EVENT0_IMASK_OVRERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_OVRERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_OVRERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_OVRERR_A { match self . bits { false => INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_CLR , true => INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_ovrerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_ovrerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_OVRERR` writer - Enable UART Receive Overrun Error Interrupt."] pub type INT_EVENT0_IMASK_OVRERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_OVRERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_OVRERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_ovrerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_ovrerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_SET) } } # [doc = "Field `INT_EVENT0_IMASK_RXNE` reader - Enable Negative Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_IMASK_RXNE_R = crate :: BitReader < INT_EVENT0_IMASK_RXNE_A > ; # [doc = "Enable Negative Edge on UARTxRXD Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_RXNE_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_RXNE_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_RXNE_SET = 1 , } impl From < INT_EVENT0_IMASK_RXNE_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_RXNE_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_RXNE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_RXNE_A { match self . bits { false => INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_CLR , true => INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_rxne_clr (& self) -> bool { * self == INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_rxne_set (& self) -> bool { * self == INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_SET } } # [doc = "Field `INT_EVENT0_IMASK_RXNE` writer - Enable Negative Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_IMASK_RXNE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_RXNE_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_RXNE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_rxne_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_rxne_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_SET) } } # [doc = "Field `INT_EVENT0_IMASK_RXPE` reader - Enable Positive Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_IMASK_RXPE_R = crate :: BitReader < INT_EVENT0_IMASK_RXPE_A > ; # [doc = "Enable Positive Edge on UARTxRXD Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_RXPE_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_RXPE_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_RXPE_SET = 1 , } impl From < INT_EVENT0_IMASK_RXPE_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_RXPE_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_RXPE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_RXPE_A { match self . bits { false => INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_CLR , true => INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_rxpe_clr (& self) -> bool { * self == INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_rxpe_set (& self) -> bool { * self == INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_SET } } # [doc = "Field `INT_EVENT0_IMASK_RXPE` writer - Enable Positive Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_IMASK_RXPE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_RXPE_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_RXPE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_rxpe_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_rxpe_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_SET) } } # [doc = "Field `INT_EVENT0_IMASK_LINC0` reader - Enable LIN Capture 0 / Match Interrupt ."] pub type INT_EVENT0_IMASK_LINC0_R = crate :: BitReader < INT_EVENT0_IMASK_LINC0_A > ; # [doc = "Enable LIN Capture 0 / Match Interrupt .\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_LINC0_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_LINC0_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_LINC0_SET = 1 , } impl From < INT_EVENT0_IMASK_LINC0_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_LINC0_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_LINC0_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_LINC0_A { match self . bits { false => INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_CLR , true => INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_linc0_clr (& self) -> bool { * self == INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_linc0_set (& self) -> bool { * self == INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_SET } } # [doc = "Field `INT_EVENT0_IMASK_LINC0` writer - Enable LIN Capture 0 / Match Interrupt ."] pub type INT_EVENT0_IMASK_LINC0_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_LINC0_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_LINC0_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_linc0_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_linc0_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_SET) } } # [doc = "Field `INT_EVENT0_IMASK_LINC1` reader - Enable LIN Capture 1 Interrupt."] pub type INT_EVENT0_IMASK_LINC1_R = crate :: BitReader < INT_EVENT0_IMASK_LINC1_A > ; # [doc = "Enable LIN Capture 1 Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_LINC1_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_LINC1_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_LINC1_SET = 1 , } impl From < INT_EVENT0_IMASK_LINC1_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_LINC1_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_LINC1_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_LINC1_A { match self . bits { false => INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_CLR , true => INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_linc1_clr (& self) -> bool { * self == INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_linc1_set (& self) -> bool { * self == INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_SET } } # [doc = "Field `INT_EVENT0_IMASK_LINC1` writer - Enable LIN Capture 1 Interrupt."] pub type INT_EVENT0_IMASK_LINC1_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_LINC1_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_LINC1_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_linc1_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_linc1_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_SET) } } # [doc = "Field `INT_EVENT0_IMASK_LINOVF` reader - Enable LIN Hardware Counter Overflow Interrupt."] pub type INT_EVENT0_IMASK_LINOVF_R = crate :: BitReader < INT_EVENT0_IMASK_LINOVF_A > ; # [doc = "Enable LIN Hardware Counter Overflow Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_LINOVF_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_LINOVF_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_LINOVF_SET = 1 , } impl From < INT_EVENT0_IMASK_LINOVF_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_LINOVF_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_LINOVF_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_LINOVF_A { match self . bits { false => INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_CLR , true => INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_linovf_clr (& self) -> bool { * self == INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_linovf_set (& self) -> bool { * self == INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_SET } } # [doc = "Field `INT_EVENT0_IMASK_LINOVF` writer - Enable LIN Hardware Counter Overflow Interrupt."] pub type INT_EVENT0_IMASK_LINOVF_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_LINOVF_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_LINOVF_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_linovf_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_linovf_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_SET) } } # [doc = "Field `INT_EVENT0_IMASK_RXINT` reader - Enable UART Receive Interrupt."] pub type INT_EVENT0_IMASK_RXINT_R = crate :: BitReader < INT_EVENT0_IMASK_RXINT_A > ; # [doc = "Enable UART Receive Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_RXINT_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_RXINT_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_RXINT_SET = 1 , } impl From < INT_EVENT0_IMASK_RXINT_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_RXINT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_RXINT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_RXINT_A { match self . bits { false => INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_CLR , true => INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_rxint_clr (& self) -> bool { * self == INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_rxint_set (& self) -> bool { * self == INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_SET } } # [doc = "Field `INT_EVENT0_IMASK_RXINT` writer - Enable UART Receive Interrupt."] pub type INT_EVENT0_IMASK_RXINT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_RXINT_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_RXINT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_rxint_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_rxint_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_SET) } } # [doc = "Field `INT_EVENT0_IMASK_TXINT` reader - Enable UART Transmit Interrupt."] pub type INT_EVENT0_IMASK_TXINT_R = crate :: BitReader < INT_EVENT0_IMASK_TXINT_A > ; # [doc = "Enable UART Transmit Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_TXINT_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_TXINT_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_TXINT_SET = 1 , } impl From < INT_EVENT0_IMASK_TXINT_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_TXINT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_TXINT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_TXINT_A { match self . bits { false => INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_CLR , true => INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_txint_clr (& self) -> bool { * self == INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_txint_set (& self) -> bool { * self == INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_SET } } # [doc = "Field `INT_EVENT0_IMASK_TXINT` writer - Enable UART Transmit Interrupt."] pub type INT_EVENT0_IMASK_TXINT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_TXINT_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_TXINT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_txint_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_txint_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_SET) } } # [doc = "Field `INT_EVENT0_IMASK_EOT` reader - Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] pub type INT_EVENT0_IMASK_EOT_R = crate :: BitReader < INT_EVENT0_IMASK_EOT_A > ; # [doc = "Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_EOT_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_EOT_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_EOT_SET = 1 , } impl From < INT_EVENT0_IMASK_EOT_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_EOT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_EOT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_EOT_A { match self . bits { false => INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_CLR , true => INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_eot_clr (& self) -> bool { * self == INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_eot_set (& self) -> bool { * self == INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_SET } } # [doc = "Field `INT_EVENT0_IMASK_EOT` writer - Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] pub type INT_EVENT0_IMASK_EOT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_EOT_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_EOT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_eot_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_eot_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_SET) } } # [doc = "Field `INT_EVENT0_IMASK_ADDR_MATCH` reader - Enable Address Match Interrupt."] pub type INT_EVENT0_IMASK_ADDR_MATCH_R = crate :: BitReader < INT_EVENT0_IMASK_ADDR_MATCH_A > ; # [doc = "Enable Address Match Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_ADDR_MATCH_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_ADDR_MATCH_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_ADDR_MATCH_SET = 1 , } impl From < INT_EVENT0_IMASK_ADDR_MATCH_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_ADDR_MATCH_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_ADDR_MATCH_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_ADDR_MATCH_A { match self . bits { false => INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_CLR , true => INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_addr_match_clr (& self) -> bool { * self == INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_addr_match_set (& self) -> bool { * self == INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_SET } } # [doc = "Field `INT_EVENT0_IMASK_ADDR_MATCH` writer - Enable Address Match Interrupt."] pub type INT_EVENT0_IMASK_ADDR_MATCH_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_ADDR_MATCH_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_ADDR_MATCH_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_addr_match_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_addr_match_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_SET) } } # [doc = "Field `INT_EVENT0_IMASK_CTS` reader - Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] pub type INT_EVENT0_IMASK_CTS_R = crate :: BitReader < INT_EVENT0_IMASK_CTS_A > ; # [doc = "Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_CTS_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_CTS_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_CTS_SET = 1 , } impl From < INT_EVENT0_IMASK_CTS_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_CTS_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_CTS_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_CTS_A { match self . bits { false => INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_CLR , true => INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_cts_clr (& self) -> bool { * self == INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_cts_set (& self) -> bool { * self == INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_SET } } # [doc = "Field `INT_EVENT0_IMASK_CTS` writer - Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] pub type INT_EVENT0_IMASK_CTS_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_CTS_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_CTS_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_cts_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_cts_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DMA_DONE_RX` reader - Enable DMA Done on RX Event Channel"] pub type INT_EVENT0_IMASK_DMA_DONE_RX_R = crate :: BitReader < INT_EVENT0_IMASK_DMA_DONE_RX_A > ; # [doc = "Enable DMA Done on RX Event Channel\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DMA_DONE_RX_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DMA_DONE_RX_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DMA_DONE_RX_SET = 1 , } impl From < INT_EVENT0_IMASK_DMA_DONE_RX_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DMA_DONE_RX_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DMA_DONE_RX_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DMA_DONE_RX_A { match self . bits { false => INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_CLR , true => INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dma_done_rx_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dma_done_rx_set (& self) -> bool { * self == INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_SET } } # [doc = "Field `INT_EVENT0_IMASK_DMA_DONE_RX` writer - Enable DMA Done on RX Event Channel"] pub type INT_EVENT0_IMASK_DMA_DONE_RX_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DMA_DONE_RX_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DMA_DONE_RX_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dma_done_rx_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dma_done_rx_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DMA_DONE_TX` reader - Enable DMA Done on TX Event Channel"] pub type INT_EVENT0_IMASK_DMA_DONE_TX_R = crate :: BitReader < INT_EVENT0_IMASK_DMA_DONE_TX_A > ; # [doc = "Enable DMA Done on TX Event Channel\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DMA_DONE_TX_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DMA_DONE_TX_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DMA_DONE_TX_SET = 1 , } impl From < INT_EVENT0_IMASK_DMA_DONE_TX_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DMA_DONE_TX_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DMA_DONE_TX_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DMA_DONE_TX_A { match self . bits { false => INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_CLR , true => INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dma_done_tx_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dma_done_tx_set (& self) -> bool { * self == INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_SET } } # [doc = "Field `INT_EVENT0_IMASK_DMA_DONE_TX` writer - Enable DMA Done on TX Event Channel"] pub type INT_EVENT0_IMASK_DMA_DONE_TX_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DMA_DONE_TX_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DMA_DONE_TX_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dma_done_tx_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dma_done_tx_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_SET) } } # [doc = "Field `INT_EVENT0_IMASK_NERR` reader - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] pub type INT_EVENT0_IMASK_NERR_R = crate :: BitReader < INT_EVENT0_IMASK_NERR_A > ; # [doc = "Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_NERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_NERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_NERR_SET = 1 , } impl From < INT_EVENT0_IMASK_NERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_NERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_NERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_NERR_A { match self . bits { false => INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_CLR , true => INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_nerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_nerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_NERR` writer - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] pub type INT_EVENT0_IMASK_NERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_NERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_NERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_nerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_nerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_SET) } } impl R { # [doc = "Bit 0 - Enable UARTOUT Receive Time-Out Interrupt."] # [inline (always)] pub fn int_event0_imask_rtout (& self) -> INT_EVENT0_IMASK_RTOUT_R { INT_EVENT0_IMASK_RTOUT_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - Enable UART Framing Error Interrupt."] # [inline (always)] pub fn int_event0_imask_frmerr (& self) -> INT_EVENT0_IMASK_FRMERR_R { INT_EVENT0_IMASK_FRMERR_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - Enable UART Parity Error Interrupt."] # [inline (always)] pub fn int_event0_imask_parerr (& self) -> INT_EVENT0_IMASK_PARERR_R { INT_EVENT0_IMASK_PARERR_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - Enable UART Break Error Interrupt."] # [inline (always)] pub fn int_event0_imask_brkerr (& self) -> INT_EVENT0_IMASK_BRKERR_R { INT_EVENT0_IMASK_BRKERR_R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - Enable UART Receive Overrun Error Interrupt."] # [inline (always)] pub fn int_event0_imask_ovrerr (& self) -> INT_EVENT0_IMASK_OVRERR_R { INT_EVENT0_IMASK_OVRERR_R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - Enable Negative Edge on UARTxRXD Interrupt."] # [inline (always)] pub fn int_event0_imask_rxne (& self) -> INT_EVENT0_IMASK_RXNE_R { INT_EVENT0_IMASK_RXNE_R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - Enable Positive Edge on UARTxRXD Interrupt."] # [inline (always)] pub fn int_event0_imask_rxpe (& self) -> INT_EVENT0_IMASK_RXPE_R { INT_EVENT0_IMASK_RXPE_R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - Enable LIN Capture 0 / Match Interrupt ."] # [inline (always)] pub fn int_event0_imask_linc0 (& self) -> INT_EVENT0_IMASK_LINC0_R { INT_EVENT0_IMASK_LINC0_R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - Enable LIN Capture 1 Interrupt."] # [inline (always)] pub fn int_event0_imask_linc1 (& self) -> INT_EVENT0_IMASK_LINC1_R { INT_EVENT0_IMASK_LINC1_R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - Enable LIN Hardware Counter Overflow Interrupt."] # [inline (always)] pub fn int_event0_imask_linovf (& self) -> INT_EVENT0_IMASK_LINOVF_R { INT_EVENT0_IMASK_LINOVF_R :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - Enable UART Receive Interrupt."] # [inline (always)] pub fn int_event0_imask_rxint (& self) -> INT_EVENT0_IMASK_RXINT_R { INT_EVENT0_IMASK_RXINT_R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - Enable UART Transmit Interrupt."] # [inline (always)] pub fn int_event0_imask_txint (& self) -> INT_EVENT0_IMASK_TXINT_R { INT_EVENT0_IMASK_TXINT_R :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] # [inline (always)] pub fn int_event0_imask_eot (& self) -> INT_EVENT0_IMASK_EOT_R { INT_EVENT0_IMASK_EOT_R :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - Enable Address Match Interrupt."] # [inline (always)] pub fn int_event0_imask_addr_match (& self) -> INT_EVENT0_IMASK_ADDR_MATCH_R { INT_EVENT0_IMASK_ADDR_MATCH_R :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 14 - Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] # [inline (always)] pub fn int_event0_imask_cts (& self) -> INT_EVENT0_IMASK_CTS_R { INT_EVENT0_IMASK_CTS_R :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - Enable DMA Done on RX Event Channel"] # [inline (always)] pub fn int_event0_imask_dma_done_rx (& self) -> INT_EVENT0_IMASK_DMA_DONE_RX_R { INT_EVENT0_IMASK_DMA_DONE_RX_R :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bit 16 - Enable DMA Done on TX Event Channel"] # [inline (always)] pub fn int_event0_imask_dma_done_tx (& self) -> INT_EVENT0_IMASK_DMA_DONE_TX_R { INT_EVENT0_IMASK_DMA_DONE_TX_R :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] # [inline (always)] pub fn int_event0_imask_nerr (& self) -> INT_EVENT0_IMASK_NERR_R { INT_EVENT0_IMASK_NERR_R :: new (((self . bits >> 17) & 1) != 0) } } impl W { # [doc = "Bit 0 - Enable UARTOUT Receive Time-Out Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_rtout (& mut self) -> INT_EVENT0_IMASK_RTOUT_W < INT_EVENT0_IMASK_SPEC , 0 > { INT_EVENT0_IMASK_RTOUT_W :: new (self) } # [doc = "Bit 1 - Enable UART Framing Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_frmerr (& mut self) -> INT_EVENT0_IMASK_FRMERR_W < INT_EVENT0_IMASK_SPEC , 1 > { INT_EVENT0_IMASK_FRMERR_W :: new (self) } # [doc = "Bit 2 - Enable UART Parity Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_parerr (& mut self) -> INT_EVENT0_IMASK_PARERR_W < INT_EVENT0_IMASK_SPEC , 2 > { INT_EVENT0_IMASK_PARERR_W :: new (self) } # [doc = "Bit 3 - Enable UART Break Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_brkerr (& mut self) -> INT_EVENT0_IMASK_BRKERR_W <'_,  INT_EVENT0_IMASK_SPEC , 3 > { INT_EVENT0_IMASK_BRKERR_W :: new (self) } # [doc = "Bit 4 - Enable UART Receive Overrun Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_ovrerr (& mut self) -> INT_EVENT0_IMASK_OVRERR_W < INT_EVENT0_IMASK_SPEC , 4 > { INT_EVENT0_IMASK_OVRERR_W :: new (self) } # [doc = "Bit 5 - Enable Negative Edge on UARTxRXD Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_rxne (& mut self) -> INT_EVENT0_IMASK_RXNE_W < INT_EVENT0_IMASK_SPEC , 5 > { INT_EVENT0_IMASK_RXNE_W :: new (self) } # [doc = "Bit 6 - Enable Positive Edge on UARTxRXD Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_rxpe (& mut self) -> INT_EVENT0_IMASK_RXPE_W < INT_EVENT0_IMASK_SPEC , 6 > { INT_EVENT0_IMASK_RXPE_W :: new (self) } # [doc = "Bit 7 - Enable LIN Capture 0 / Match Interrupt ."] # [inline (always)] # [must_use] pub fn int_event0_imask_linc0 (& mut self) -> INT_EVENT0_IMASK_LINC0_W < INT_EVENT0_IMASK_SPEC , 7 > { INT_EVENT0_IMASK_LINC0_W :: new (self) } # [doc = "Bit 8 - Enable LIN Capture 1 Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_linc1 (& mut self) -> INT_EVENT0_IMASK_LINC1_W < INT_EVENT0_IMASK_SPEC , 8 > { INT_EVENT0_IMASK_LINC1_W :: new (self) } # [doc = "Bit 9 - Enable LIN Hardware Counter Overflow Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_linovf (& mut self) -> INT_EVENT0_IMASK_LINOVF_W < INT_EVENT0_IMASK_SPEC , 9 > { INT_EVENT0_IMASK_LINOVF_W :: new (self) } # [doc = "Bit 10 - Enable UART Receive Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_rxint (& mut self) -> INT_EVENT0_IMASK_RXINT_W < INT_EVENT0_IMASK_SPEC , 10 > { INT_EVENT0_IMASK_RXINT_W :: new (self) } # [doc = "Bit 11 - Enable UART Transmit Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_txint (& mut self) -> INT_EVENT0_IMASK_TXINT_W < INT_EVENT0_IMASK_SPEC , 11 > { INT_EVENT0_IMASK_TXINT_W :: new (self) } # [doc = "Bit 12 - Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] # [inline (always)] # [must_use] pub fn int_event0_imask_eot (& mut self) -> INT_EVENT0_IMASK_EOT_W < INT_EVENT0_IMASK_SPEC , 12 > { INT_EVENT0_IMASK_EOT_W :: new (self) } # [doc = "Bit 13 - Enable Address Match Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_addr_match (& mut self) -> INT_EVENT0_IMASK_ADDR_MATCH_W < INT_EVENT0_IMASK_SPEC , 13 > { INT_EVENT0_IMASK_ADDR_MATCH_W :: new (self) } # [doc = "Bit 14 - Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] # [inline (always)] # [must_use] pub fn int_event0_imask_cts (& mut self) -> INT_EVENT0_IMASK_CTS_W < INT_EVENT0_IMASK_SPEC , 14 > { INT_EVENT0_IMASK_CTS_W :: new (self) } # [doc = "Bit 15 - Enable DMA Done on RX Event Channel"] # [inline (always)] # [must_use] pub fn int_event0_imask_dma_done_rx (& mut self) -> INT_EVENT0_IMASK_DMA_DONE_RX_W < INT_EVENT0_IMASK_SPEC , 15 > { INT_EVENT0_IMASK_DMA_DONE_RX_W :: new (self) } # [doc = "Bit 16 - Enable DMA Done on TX Event Channel"] # [inline (always)] # [must_use] pub fn int_event0_imask_dma_done_tx (& mut self) -> INT_EVENT0_IMASK_DMA_DONE_TX_W < INT_EVENT0_IMASK_SPEC , 16 > { INT_EVENT0_IMASK_DMA_DONE_TX_W :: new (self) } # [doc = "Bit 17 - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] # [inline (always)] # [must_use] pub fn int_event0_imask_nerr (& mut self) -> INT_EVENT0_IMASK_NERR_W < INT_EVENT0_IMASK_SPEC , 17 > { INT_EVENT0_IMASK_NERR_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Interrupt mask\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_event0_imask::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_event0_imask::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct INT_EVENT0_IMASK_SPEC ; impl crate :: RegisterSpec for INT_EVENT0_IMASK_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`int_event0_imask::R`](R) reader structure"] impl crate :: Readable for INT_EVENT0_IMASK_SPEC { } # [doc = "`write(|w| ..)` method takes [`int_event0_imask::W`](W) writer structure"] impl crate :: Writable for INT_EVENT0_IMASK_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets INT_EVENT0_IMASK to value 0"] impl crate :: Resettable for INT_EVENT0_IMASK_SPEC { const RESET_VALUE : Self :: Ux = 0 ; }
[INFO] [stdout]   |                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                              +++
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing
[INFO] [stdout]  --> src/uart0/int_event0_imask.rs:1:41449
[INFO] [stdout]   |
[INFO] [stdout] 1 | ...mask_ovrerr (& mut self) -> INT_EVENT0_IMASK_OVRERR_W < INT_EVENT0_IMASK_SPEC , 4 > { INT_EVENT0_IMASK_OVRERR_W :: new (self) } # ...
[INFO] [stdout]   |                 ^^^^^^^^^^     ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here
[INFO] [stdout]   |                 |
[INFO] [stdout]   |                 the lifetime is elided here
[INFO] [stdout]   |
[INFO] [stdout]   = help: the same lifetime is referred to in inconsistent ways, making the signature confusing
[INFO] [stdout] help: use `'_` for type paths
[INFO] [stdout]   |
[INFO] [stdout] 1 | # [doc = "Register `INT_EVENT0_IMASK` reader"] pub type R = crate :: R < INT_EVENT0_IMASK_SPEC > ; # [doc = "Register `INT_EVENT0_IMASK` writer"] pub type W = crate :: W < INT_EVENT0_IMASK_SPEC > ; # [doc = "Field `INT_EVENT0_IMASK_RTOUT` reader - Enable UARTOUT Receive Time-Out Interrupt."] pub type INT_EVENT0_IMASK_RTOUT_R = crate :: BitReader < INT_EVENT0_IMASK_RTOUT_A > ; # [doc = "Enable UARTOUT Receive Time-Out Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_RTOUT_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_RTOUT_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_RTOUT_SET = 1 , } impl From < INT_EVENT0_IMASK_RTOUT_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_RTOUT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_RTOUT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_RTOUT_A { match self . bits { false => INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_CLR , true => INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_rtout_clr (& self) -> bool { * self == INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_rtout_set (& self) -> bool { * self == INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_SET } } # [doc = "Field `INT_EVENT0_IMASK_RTOUT` writer - Enable UARTOUT Receive Time-Out Interrupt."] pub type INT_EVENT0_IMASK_RTOUT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_RTOUT_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_RTOUT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_rtout_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_rtout_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_SET) } } # [doc = "Field `INT_EVENT0_IMASK_FRMERR` reader - Enable UART Framing Error Interrupt."] pub type INT_EVENT0_IMASK_FRMERR_R = crate :: BitReader < INT_EVENT0_IMASK_FRMERR_A > ; # [doc = "Enable UART Framing Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_FRMERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_FRMERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_FRMERR_SET = 1 , } impl From < INT_EVENT0_IMASK_FRMERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_FRMERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_FRMERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_FRMERR_A { match self . bits { false => INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_CLR , true => INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_frmerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_frmerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_FRMERR` writer - Enable UART Framing Error Interrupt."] pub type INT_EVENT0_IMASK_FRMERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_FRMERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_FRMERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_frmerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_frmerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_SET) } } # [doc = "Field `INT_EVENT0_IMASK_PARERR` reader - Enable UART Parity Error Interrupt."] pub type INT_EVENT0_IMASK_PARERR_R = crate :: BitReader < INT_EVENT0_IMASK_PARERR_A > ; # [doc = "Enable UART Parity Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_PARERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_PARERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_PARERR_SET = 1 , } impl From < INT_EVENT0_IMASK_PARERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_PARERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_PARERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_PARERR_A { match self . bits { false => INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_CLR , true => INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_parerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_parerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_PARERR` writer - Enable UART Parity Error Interrupt."] pub type INT_EVENT0_IMASK_PARERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_PARERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_PARERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_parerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_parerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_SET) } } # [doc = "Field `INT_EVENT0_IMASK_BRKERR` reader - Enable UART Break Error Interrupt."] pub type INT_EVENT0_IMASK_BRKERR_R = crate :: BitReader < INT_EVENT0_IMASK_BRKERR_A > ; # [doc = "Enable UART Break Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_BRKERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_BRKERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_BRKERR_SET = 1 , } impl From < INT_EVENT0_IMASK_BRKERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_BRKERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_BRKERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_BRKERR_A { match self . bits { false => INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_CLR , true => INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_brkerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_brkerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_BRKERR` writer - Enable UART Break Error Interrupt."] pub type INT_EVENT0_IMASK_BRKERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_BRKERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_BRKERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_brkerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_brkerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_SET) } } # [doc = "Field `INT_EVENT0_IMASK_OVRERR` reader - Enable UART Receive Overrun Error Interrupt."] pub type INT_EVENT0_IMASK_OVRERR_R = crate :: BitReader < INT_EVENT0_IMASK_OVRERR_A > ; # [doc = "Enable UART Receive Overrun Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_OVRERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_OVRERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_OVRERR_SET = 1 , } impl From < INT_EVENT0_IMASK_OVRERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_OVRERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_OVRERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_OVRERR_A { match self . bits { false => INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_CLR , true => INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_ovrerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_ovrerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_OVRERR` writer - Enable UART Receive Overrun Error Interrupt."] pub type INT_EVENT0_IMASK_OVRERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_OVRERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_OVRERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_ovrerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_ovrerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_SET) } } # [doc = "Field `INT_EVENT0_IMASK_RXNE` reader - Enable Negative Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_IMASK_RXNE_R = crate :: BitReader < INT_EVENT0_IMASK_RXNE_A > ; # [doc = "Enable Negative Edge on UARTxRXD Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_RXNE_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_RXNE_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_RXNE_SET = 1 , } impl From < INT_EVENT0_IMASK_RXNE_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_RXNE_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_RXNE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_RXNE_A { match self . bits { false => INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_CLR , true => INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_rxne_clr (& self) -> bool { * self == INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_rxne_set (& self) -> bool { * self == INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_SET } } # [doc = "Field `INT_EVENT0_IMASK_RXNE` writer - Enable Negative Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_IMASK_RXNE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_RXNE_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_RXNE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_rxne_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_rxne_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_SET) } } # [doc = "Field `INT_EVENT0_IMASK_RXPE` reader - Enable Positive Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_IMASK_RXPE_R = crate :: BitReader < INT_EVENT0_IMASK_RXPE_A > ; # [doc = "Enable Positive Edge on UARTxRXD Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_RXPE_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_RXPE_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_RXPE_SET = 1 , } impl From < INT_EVENT0_IMASK_RXPE_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_RXPE_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_RXPE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_RXPE_A { match self . bits { false => INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_CLR , true => INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_rxpe_clr (& self) -> bool { * self == INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_rxpe_set (& self) -> bool { * self == INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_SET } } # [doc = "Field `INT_EVENT0_IMASK_RXPE` writer - Enable Positive Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_IMASK_RXPE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_RXPE_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_RXPE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_rxpe_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_rxpe_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_SET) } } # [doc = "Field `INT_EVENT0_IMASK_LINC0` reader - Enable LIN Capture 0 / Match Interrupt ."] pub type INT_EVENT0_IMASK_LINC0_R = crate :: BitReader < INT_EVENT0_IMASK_LINC0_A > ; # [doc = "Enable LIN Capture 0 / Match Interrupt .\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_LINC0_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_LINC0_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_LINC0_SET = 1 , } impl From < INT_EVENT0_IMASK_LINC0_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_LINC0_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_LINC0_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_LINC0_A { match self . bits { false => INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_CLR , true => INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_linc0_clr (& self) -> bool { * self == INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_linc0_set (& self) -> bool { * self == INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_SET } } # [doc = "Field `INT_EVENT0_IMASK_LINC0` writer - Enable LIN Capture 0 / Match Interrupt ."] pub type INT_EVENT0_IMASK_LINC0_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_LINC0_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_LINC0_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_linc0_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_linc0_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_SET) } } # [doc = "Field `INT_EVENT0_IMASK_LINC1` reader - Enable LIN Capture 1 Interrupt."] pub type INT_EVENT0_IMASK_LINC1_R = crate :: BitReader < INT_EVENT0_IMASK_LINC1_A > ; # [doc = "Enable LIN Capture 1 Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_LINC1_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_LINC1_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_LINC1_SET = 1 , } impl From < INT_EVENT0_IMASK_LINC1_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_LINC1_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_LINC1_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_LINC1_A { match self . bits { false => INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_CLR , true => INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_linc1_clr (& self) -> bool { * self == INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_linc1_set (& self) -> bool { * self == INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_SET } } # [doc = "Field `INT_EVENT0_IMASK_LINC1` writer - Enable LIN Capture 1 Interrupt."] pub type INT_EVENT0_IMASK_LINC1_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_LINC1_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_LINC1_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_linc1_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_linc1_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_SET) } } # [doc = "Field `INT_EVENT0_IMASK_LINOVF` reader - Enable LIN Hardware Counter Overflow Interrupt."] pub type INT_EVENT0_IMASK_LINOVF_R = crate :: BitReader < INT_EVENT0_IMASK_LINOVF_A > ; # [doc = "Enable LIN Hardware Counter Overflow Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_LINOVF_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_LINOVF_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_LINOVF_SET = 1 , } impl From < INT_EVENT0_IMASK_LINOVF_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_LINOVF_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_LINOVF_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_LINOVF_A { match self . bits { false => INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_CLR , true => INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_linovf_clr (& self) -> bool { * self == INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_linovf_set (& self) -> bool { * self == INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_SET } } # [doc = "Field `INT_EVENT0_IMASK_LINOVF` writer - Enable LIN Hardware Counter Overflow Interrupt."] pub type INT_EVENT0_IMASK_LINOVF_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_LINOVF_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_LINOVF_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_linovf_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_linovf_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_SET) } } # [doc = "Field `INT_EVENT0_IMASK_RXINT` reader - Enable UART Receive Interrupt."] pub type INT_EVENT0_IMASK_RXINT_R = crate :: BitReader < INT_EVENT0_IMASK_RXINT_A > ; # [doc = "Enable UART Receive Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_RXINT_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_RXINT_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_RXINT_SET = 1 , } impl From < INT_EVENT0_IMASK_RXINT_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_RXINT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_RXINT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_RXINT_A { match self . bits { false => INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_CLR , true => INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_rxint_clr (& self) -> bool { * self == INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_rxint_set (& self) -> bool { * self == INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_SET } } # [doc = "Field `INT_EVENT0_IMASK_RXINT` writer - Enable UART Receive Interrupt."] pub type INT_EVENT0_IMASK_RXINT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_RXINT_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_RXINT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_rxint_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_rxint_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_SET) } } # [doc = "Field `INT_EVENT0_IMASK_TXINT` reader - Enable UART Transmit Interrupt."] pub type INT_EVENT0_IMASK_TXINT_R = crate :: BitReader < INT_EVENT0_IMASK_TXINT_A > ; # [doc = "Enable UART Transmit Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_TXINT_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_TXINT_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_TXINT_SET = 1 , } impl From < INT_EVENT0_IMASK_TXINT_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_TXINT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_TXINT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_TXINT_A { match self . bits { false => INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_CLR , true => INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_txint_clr (& self) -> bool { * self == INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_txint_set (& self) -> bool { * self == INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_SET } } # [doc = "Field `INT_EVENT0_IMASK_TXINT` writer - Enable UART Transmit Interrupt."] pub type INT_EVENT0_IMASK_TXINT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_TXINT_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_TXINT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_txint_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_txint_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_SET) } } # [doc = "Field `INT_EVENT0_IMASK_EOT` reader - Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] pub type INT_EVENT0_IMASK_EOT_R = crate :: BitReader < INT_EVENT0_IMASK_EOT_A > ; # [doc = "Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_EOT_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_EOT_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_EOT_SET = 1 , } impl From < INT_EVENT0_IMASK_EOT_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_EOT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_EOT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_EOT_A { match self . bits { false => INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_CLR , true => INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_eot_clr (& self) -> bool { * self == INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_eot_set (& self) -> bool { * self == INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_SET } } # [doc = "Field `INT_EVENT0_IMASK_EOT` writer - Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] pub type INT_EVENT0_IMASK_EOT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_EOT_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_EOT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_eot_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_eot_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_SET) } } # [doc = "Field `INT_EVENT0_IMASK_ADDR_MATCH` reader - Enable Address Match Interrupt."] pub type INT_EVENT0_IMASK_ADDR_MATCH_R = crate :: BitReader < INT_EVENT0_IMASK_ADDR_MATCH_A > ; # [doc = "Enable Address Match Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_ADDR_MATCH_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_ADDR_MATCH_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_ADDR_MATCH_SET = 1 , } impl From < INT_EVENT0_IMASK_ADDR_MATCH_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_ADDR_MATCH_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_ADDR_MATCH_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_ADDR_MATCH_A { match self . bits { false => INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_CLR , true => INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_addr_match_clr (& self) -> bool { * self == INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_addr_match_set (& self) -> bool { * self == INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_SET } } # [doc = "Field `INT_EVENT0_IMASK_ADDR_MATCH` writer - Enable Address Match Interrupt."] pub type INT_EVENT0_IMASK_ADDR_MATCH_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_ADDR_MATCH_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_ADDR_MATCH_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_addr_match_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_addr_match_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_SET) } } # [doc = "Field `INT_EVENT0_IMASK_CTS` reader - Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] pub type INT_EVENT0_IMASK_CTS_R = crate :: BitReader < INT_EVENT0_IMASK_CTS_A > ; # [doc = "Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_CTS_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_CTS_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_CTS_SET = 1 , } impl From < INT_EVENT0_IMASK_CTS_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_CTS_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_CTS_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_CTS_A { match self . bits { false => INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_CLR , true => INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_cts_clr (& self) -> bool { * self == INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_cts_set (& self) -> bool { * self == INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_SET } } # [doc = "Field `INT_EVENT0_IMASK_CTS` writer - Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] pub type INT_EVENT0_IMASK_CTS_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_CTS_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_CTS_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_cts_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_cts_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DMA_DONE_RX` reader - Enable DMA Done on RX Event Channel"] pub type INT_EVENT0_IMASK_DMA_DONE_RX_R = crate :: BitReader < INT_EVENT0_IMASK_DMA_DONE_RX_A > ; # [doc = "Enable DMA Done on RX Event Channel\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DMA_DONE_RX_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DMA_DONE_RX_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DMA_DONE_RX_SET = 1 , } impl From < INT_EVENT0_IMASK_DMA_DONE_RX_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DMA_DONE_RX_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DMA_DONE_RX_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DMA_DONE_RX_A { match self . bits { false => INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_CLR , true => INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dma_done_rx_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dma_done_rx_set (& self) -> bool { * self == INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_SET } } # [doc = "Field `INT_EVENT0_IMASK_DMA_DONE_RX` writer - Enable DMA Done on RX Event Channel"] pub type INT_EVENT0_IMASK_DMA_DONE_RX_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DMA_DONE_RX_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DMA_DONE_RX_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dma_done_rx_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dma_done_rx_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DMA_DONE_TX` reader - Enable DMA Done on TX Event Channel"] pub type INT_EVENT0_IMASK_DMA_DONE_TX_R = crate :: BitReader < INT_EVENT0_IMASK_DMA_DONE_TX_A > ; # [doc = "Enable DMA Done on TX Event Channel\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DMA_DONE_TX_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DMA_DONE_TX_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DMA_DONE_TX_SET = 1 , } impl From < INT_EVENT0_IMASK_DMA_DONE_TX_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DMA_DONE_TX_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DMA_DONE_TX_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DMA_DONE_TX_A { match self . bits { false => INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_CLR , true => INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dma_done_tx_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dma_done_tx_set (& self) -> bool { * self == INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_SET } } # [doc = "Field `INT_EVENT0_IMASK_DMA_DONE_TX` writer - Enable DMA Done on TX Event Channel"] pub type INT_EVENT0_IMASK_DMA_DONE_TX_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DMA_DONE_TX_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DMA_DONE_TX_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dma_done_tx_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dma_done_tx_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_SET) } } # [doc = "Field `INT_EVENT0_IMASK_NERR` reader - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] pub type INT_EVENT0_IMASK_NERR_R = crate :: BitReader < INT_EVENT0_IMASK_NERR_A > ; # [doc = "Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_NERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_NERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_NERR_SET = 1 , } impl From < INT_EVENT0_IMASK_NERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_NERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_NERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_NERR_A { match self . bits { false => INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_CLR , true => INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_nerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_nerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_NERR` writer - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] pub type INT_EVENT0_IMASK_NERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_NERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_NERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_nerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_nerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_SET) } } impl R { # [doc = "Bit 0 - Enable UARTOUT Receive Time-Out Interrupt."] # [inline (always)] pub fn int_event0_imask_rtout (& self) -> INT_EVENT0_IMASK_RTOUT_R { INT_EVENT0_IMASK_RTOUT_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - Enable UART Framing Error Interrupt."] # [inline (always)] pub fn int_event0_imask_frmerr (& self) -> INT_EVENT0_IMASK_FRMERR_R { INT_EVENT0_IMASK_FRMERR_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - Enable UART Parity Error Interrupt."] # [inline (always)] pub fn int_event0_imask_parerr (& self) -> INT_EVENT0_IMASK_PARERR_R { INT_EVENT0_IMASK_PARERR_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - Enable UART Break Error Interrupt."] # [inline (always)] pub fn int_event0_imask_brkerr (& self) -> INT_EVENT0_IMASK_BRKERR_R { INT_EVENT0_IMASK_BRKERR_R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - Enable UART Receive Overrun Error Interrupt."] # [inline (always)] pub fn int_event0_imask_ovrerr (& self) -> INT_EVENT0_IMASK_OVRERR_R { INT_EVENT0_IMASK_OVRERR_R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - Enable Negative Edge on UARTxRXD Interrupt."] # [inline (always)] pub fn int_event0_imask_rxne (& self) -> INT_EVENT0_IMASK_RXNE_R { INT_EVENT0_IMASK_RXNE_R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - Enable Positive Edge on UARTxRXD Interrupt."] # [inline (always)] pub fn int_event0_imask_rxpe (& self) -> INT_EVENT0_IMASK_RXPE_R { INT_EVENT0_IMASK_RXPE_R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - Enable LIN Capture 0 / Match Interrupt ."] # [inline (always)] pub fn int_event0_imask_linc0 (& self) -> INT_EVENT0_IMASK_LINC0_R { INT_EVENT0_IMASK_LINC0_R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - Enable LIN Capture 1 Interrupt."] # [inline (always)] pub fn int_event0_imask_linc1 (& self) -> INT_EVENT0_IMASK_LINC1_R { INT_EVENT0_IMASK_LINC1_R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - Enable LIN Hardware Counter Overflow Interrupt."] # [inline (always)] pub fn int_event0_imask_linovf (& self) -> INT_EVENT0_IMASK_LINOVF_R { INT_EVENT0_IMASK_LINOVF_R :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - Enable UART Receive Interrupt."] # [inline (always)] pub fn int_event0_imask_rxint (& self) -> INT_EVENT0_IMASK_RXINT_R { INT_EVENT0_IMASK_RXINT_R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - Enable UART Transmit Interrupt."] # [inline (always)] pub fn int_event0_imask_txint (& self) -> INT_EVENT0_IMASK_TXINT_R { INT_EVENT0_IMASK_TXINT_R :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] # [inline (always)] pub fn int_event0_imask_eot (& self) -> INT_EVENT0_IMASK_EOT_R { INT_EVENT0_IMASK_EOT_R :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - Enable Address Match Interrupt."] # [inline (always)] pub fn int_event0_imask_addr_match (& self) -> INT_EVENT0_IMASK_ADDR_MATCH_R { INT_EVENT0_IMASK_ADDR_MATCH_R :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 14 - Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] # [inline (always)] pub fn int_event0_imask_cts (& self) -> INT_EVENT0_IMASK_CTS_R { INT_EVENT0_IMASK_CTS_R :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - Enable DMA Done on RX Event Channel"] # [inline (always)] pub fn int_event0_imask_dma_done_rx (& self) -> INT_EVENT0_IMASK_DMA_DONE_RX_R { INT_EVENT0_IMASK_DMA_DONE_RX_R :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bit 16 - Enable DMA Done on TX Event Channel"] # [inline (always)] pub fn int_event0_imask_dma_done_tx (& self) -> INT_EVENT0_IMASK_DMA_DONE_TX_R { INT_EVENT0_IMASK_DMA_DONE_TX_R :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] # [inline (always)] pub fn int_event0_imask_nerr (& self) -> INT_EVENT0_IMASK_NERR_R { INT_EVENT0_IMASK_NERR_R :: new (((self . bits >> 17) & 1) != 0) } } impl W { # [doc = "Bit 0 - Enable UARTOUT Receive Time-Out Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_rtout (& mut self) -> INT_EVENT0_IMASK_RTOUT_W < INT_EVENT0_IMASK_SPEC , 0 > { INT_EVENT0_IMASK_RTOUT_W :: new (self) } # [doc = "Bit 1 - Enable UART Framing Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_frmerr (& mut self) -> INT_EVENT0_IMASK_FRMERR_W < INT_EVENT0_IMASK_SPEC , 1 > { INT_EVENT0_IMASK_FRMERR_W :: new (self) } # [doc = "Bit 2 - Enable UART Parity Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_parerr (& mut self) -> INT_EVENT0_IMASK_PARERR_W < INT_EVENT0_IMASK_SPEC , 2 > { INT_EVENT0_IMASK_PARERR_W :: new (self) } # [doc = "Bit 3 - Enable UART Break Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_brkerr (& mut self) -> INT_EVENT0_IMASK_BRKERR_W < INT_EVENT0_IMASK_SPEC , 3 > { INT_EVENT0_IMASK_BRKERR_W :: new (self) } # [doc = "Bit 4 - Enable UART Receive Overrun Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_ovrerr (& mut self) -> INT_EVENT0_IMASK_OVRERR_W <'_,  INT_EVENT0_IMASK_SPEC , 4 > { INT_EVENT0_IMASK_OVRERR_W :: new (self) } # [doc = "Bit 5 - Enable Negative Edge on UARTxRXD Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_rxne (& mut self) -> INT_EVENT0_IMASK_RXNE_W < INT_EVENT0_IMASK_SPEC , 5 > { INT_EVENT0_IMASK_RXNE_W :: new (self) } # [doc = "Bit 6 - Enable Positive Edge on UARTxRXD Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_rxpe (& mut self) -> INT_EVENT0_IMASK_RXPE_W < INT_EVENT0_IMASK_SPEC , 6 > { INT_EVENT0_IMASK_RXPE_W :: new (self) } # [doc = "Bit 7 - Enable LIN Capture 0 / Match Interrupt ."] # [inline (always)] # [must_use] pub fn int_event0_imask_linc0 (& mut self) -> INT_EVENT0_IMASK_LINC0_W < INT_EVENT0_IMASK_SPEC , 7 > { INT_EVENT0_IMASK_LINC0_W :: new (self) } # [doc = "Bit 8 - Enable LIN Capture 1 Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_linc1 (& mut self) -> INT_EVENT0_IMASK_LINC1_W < INT_EVENT0_IMASK_SPEC , 8 > { INT_EVENT0_IMASK_LINC1_W :: new (self) } # [doc = "Bit 9 - Enable LIN Hardware Counter Overflow Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_linovf (& mut self) -> INT_EVENT0_IMASK_LINOVF_W < INT_EVENT0_IMASK_SPEC , 9 > { INT_EVENT0_IMASK_LINOVF_W :: new (self) } # [doc = "Bit 10 - Enable UART Receive Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_rxint (& mut self) -> INT_EVENT0_IMASK_RXINT_W < INT_EVENT0_IMASK_SPEC , 10 > { INT_EVENT0_IMASK_RXINT_W :: new (self) } # [doc = "Bit 11 - Enable UART Transmit Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_txint (& mut self) -> INT_EVENT0_IMASK_TXINT_W < INT_EVENT0_IMASK_SPEC , 11 > { INT_EVENT0_IMASK_TXINT_W :: new (self) } # [doc = "Bit 12 - Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] # [inline (always)] # [must_use] pub fn int_event0_imask_eot (& mut self) -> INT_EVENT0_IMASK_EOT_W < INT_EVENT0_IMASK_SPEC , 12 > { INT_EVENT0_IMASK_EOT_W :: new (self) } # [doc = "Bit 13 - Enable Address Match Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_addr_match (& mut self) -> INT_EVENT0_IMASK_ADDR_MATCH_W < INT_EVENT0_IMASK_SPEC , 13 > { INT_EVENT0_IMASK_ADDR_MATCH_W :: new (self) } # [doc = "Bit 14 - Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] # [inline (always)] # [must_use] pub fn int_event0_imask_cts (& mut self) -> INT_EVENT0_IMASK_CTS_W < INT_EVENT0_IMASK_SPEC , 14 > { INT_EVENT0_IMASK_CTS_W :: new (self) } # [doc = "Bit 15 - Enable DMA Done on RX Event Channel"] # [inline (always)] # [must_use] pub fn int_event0_imask_dma_done_rx (& mut self) -> INT_EVENT0_IMASK_DMA_DONE_RX_W < INT_EVENT0_IMASK_SPEC , 15 > { INT_EVENT0_IMASK_DMA_DONE_RX_W :: new (self) } # [doc = "Bit 16 - Enable DMA Done on TX Event Channel"] # [inline (always)] # [must_use] pub fn int_event0_imask_dma_done_tx (& mut self) -> INT_EVENT0_IMASK_DMA_DONE_TX_W < INT_EVENT0_IMASK_SPEC , 16 > { INT_EVENT0_IMASK_DMA_DONE_TX_W :: new (self) } # [doc = "Bit 17 - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] # [inline (always)] # [must_use] pub fn int_event0_imask_nerr (& mut self) -> INT_EVENT0_IMASK_NERR_W < INT_EVENT0_IMASK_SPEC , 17 > { INT_EVENT0_IMASK_NERR_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Interrupt mask\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_event0_imask::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_event0_imask::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct INT_EVENT0_IMASK_SPEC ; impl crate :: RegisterSpec for INT_EVENT0_IMASK_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`int_event0_imask::R`](R) reader structure"] impl crate :: Readable for INT_EVENT0_IMASK_SPEC { } # [doc = "`write(|w| ..)` method takes [`int_event0_imask::W`](W) writer structure"] impl crate :: Writable for INT_EVENT0_IMASK_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets INT_EVENT0_IMASK to value 0"] impl crate :: Resettable for INT_EVENT0_IMASK_SPEC { const RESET_VALUE : Self :: Ux = 0 ; }
[INFO] [stdout]   |                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                   +++
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing
[INFO] [stdout]  --> src/uart0/int_event0_imask.rs:1:41691
[INFO] [stdout]   |
[INFO] [stdout] 1 | ...0_imask_rxne (& mut self) -> INT_EVENT0_IMASK_RXNE_W < INT_EVENT0_IMASK_SPEC , 5 > { INT_EVENT0_IMASK_RXNE_W :: new (self) } # [do...
[INFO] [stdout]   |                  ^^^^^^^^^^     ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here
[INFO] [stdout]   |                  |
[INFO] [stdout]   |                  the lifetime is elided here
[INFO] [stdout]   |
[INFO] [stdout]   = help: the same lifetime is referred to in inconsistent ways, making the signature confusing
[INFO] [stdout] help: use `'_` for type paths
[INFO] [stdout]   |
[INFO] [stdout] 1 | # [doc = "Register `INT_EVENT0_IMASK` reader"] pub type R = crate :: R < INT_EVENT0_IMASK_SPEC > ; # [doc = "Register `INT_EVENT0_IMASK` writer"] pub type W = crate :: W < INT_EVENT0_IMASK_SPEC > ; # [doc = "Field `INT_EVENT0_IMASK_RTOUT` reader - Enable UARTOUT Receive Time-Out Interrupt."] pub type INT_EVENT0_IMASK_RTOUT_R = crate :: BitReader < INT_EVENT0_IMASK_RTOUT_A > ; # [doc = "Enable UARTOUT Receive Time-Out Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_RTOUT_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_RTOUT_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_RTOUT_SET = 1 , } impl From < INT_EVENT0_IMASK_RTOUT_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_RTOUT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_RTOUT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_RTOUT_A { match self . bits { false => INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_CLR , true => INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_rtout_clr (& self) -> bool { * self == INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_rtout_set (& self) -> bool { * self == INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_SET } } # [doc = "Field `INT_EVENT0_IMASK_RTOUT` writer - Enable UARTOUT Receive Time-Out Interrupt."] pub type INT_EVENT0_IMASK_RTOUT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_RTOUT_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_RTOUT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_rtout_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_rtout_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_SET) } } # [doc = "Field `INT_EVENT0_IMASK_FRMERR` reader - Enable UART Framing Error Interrupt."] pub type INT_EVENT0_IMASK_FRMERR_R = crate :: BitReader < INT_EVENT0_IMASK_FRMERR_A > ; # [doc = "Enable UART Framing Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_FRMERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_FRMERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_FRMERR_SET = 1 , } impl From < INT_EVENT0_IMASK_FRMERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_FRMERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_FRMERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_FRMERR_A { match self . bits { false => INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_CLR , true => INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_frmerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_frmerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_FRMERR` writer - Enable UART Framing Error Interrupt."] pub type INT_EVENT0_IMASK_FRMERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_FRMERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_FRMERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_frmerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_frmerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_SET) } } # [doc = "Field `INT_EVENT0_IMASK_PARERR` reader - Enable UART Parity Error Interrupt."] pub type INT_EVENT0_IMASK_PARERR_R = crate :: BitReader < INT_EVENT0_IMASK_PARERR_A > ; # [doc = "Enable UART Parity Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_PARERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_PARERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_PARERR_SET = 1 , } impl From < INT_EVENT0_IMASK_PARERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_PARERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_PARERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_PARERR_A { match self . bits { false => INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_CLR , true => INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_parerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_parerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_PARERR` writer - Enable UART Parity Error Interrupt."] pub type INT_EVENT0_IMASK_PARERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_PARERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_PARERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_parerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_parerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_SET) } } # [doc = "Field `INT_EVENT0_IMASK_BRKERR` reader - Enable UART Break Error Interrupt."] pub type INT_EVENT0_IMASK_BRKERR_R = crate :: BitReader < INT_EVENT0_IMASK_BRKERR_A > ; # [doc = "Enable UART Break Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_BRKERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_BRKERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_BRKERR_SET = 1 , } impl From < INT_EVENT0_IMASK_BRKERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_BRKERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_BRKERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_BRKERR_A { match self . bits { false => INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_CLR , true => INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_brkerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_brkerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_BRKERR` writer - Enable UART Break Error Interrupt."] pub type INT_EVENT0_IMASK_BRKERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_BRKERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_BRKERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_brkerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_brkerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_SET) } } # [doc = "Field `INT_EVENT0_IMASK_OVRERR` reader - Enable UART Receive Overrun Error Interrupt."] pub type INT_EVENT0_IMASK_OVRERR_R = crate :: BitReader < INT_EVENT0_IMASK_OVRERR_A > ; # [doc = "Enable UART Receive Overrun Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_OVRERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_OVRERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_OVRERR_SET = 1 , } impl From < INT_EVENT0_IMASK_OVRERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_OVRERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_OVRERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_OVRERR_A { match self . bits { false => INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_CLR , true => INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_ovrerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_ovrerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_OVRERR` writer - Enable UART Receive Overrun Error Interrupt."] pub type INT_EVENT0_IMASK_OVRERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_OVRERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_OVRERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_ovrerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_ovrerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_SET) } } # [doc = "Field `INT_EVENT0_IMASK_RXNE` reader - Enable Negative Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_IMASK_RXNE_R = crate :: BitReader < INT_EVENT0_IMASK_RXNE_A > ; # [doc = "Enable Negative Edge on UARTxRXD Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_RXNE_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_RXNE_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_RXNE_SET = 1 , } impl From < INT_EVENT0_IMASK_RXNE_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_RXNE_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_RXNE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_RXNE_A { match self . bits { false => INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_CLR , true => INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_rxne_clr (& self) -> bool { * self == INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_rxne_set (& self) -> bool { * self == INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_SET } } # [doc = "Field `INT_EVENT0_IMASK_RXNE` writer - Enable Negative Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_IMASK_RXNE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_RXNE_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_RXNE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_rxne_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_rxne_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_SET) } } # [doc = "Field `INT_EVENT0_IMASK_RXPE` reader - Enable Positive Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_IMASK_RXPE_R = crate :: BitReader < INT_EVENT0_IMASK_RXPE_A > ; # [doc = "Enable Positive Edge on UARTxRXD Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_RXPE_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_RXPE_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_RXPE_SET = 1 , } impl From < INT_EVENT0_IMASK_RXPE_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_RXPE_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_RXPE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_RXPE_A { match self . bits { false => INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_CLR , true => INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_rxpe_clr (& self) -> bool { * self == INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_rxpe_set (& self) -> bool { * self == INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_SET } } # [doc = "Field `INT_EVENT0_IMASK_RXPE` writer - Enable Positive Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_IMASK_RXPE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_RXPE_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_RXPE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_rxpe_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_rxpe_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_SET) } } # [doc = "Field `INT_EVENT0_IMASK_LINC0` reader - Enable LIN Capture 0 / Match Interrupt ."] pub type INT_EVENT0_IMASK_LINC0_R = crate :: BitReader < INT_EVENT0_IMASK_LINC0_A > ; # [doc = "Enable LIN Capture 0 / Match Interrupt .\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_LINC0_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_LINC0_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_LINC0_SET = 1 , } impl From < INT_EVENT0_IMASK_LINC0_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_LINC0_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_LINC0_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_LINC0_A { match self . bits { false => INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_CLR , true => INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_linc0_clr (& self) -> bool { * self == INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_linc0_set (& self) -> bool { * self == INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_SET } } # [doc = "Field `INT_EVENT0_IMASK_LINC0` writer - Enable LIN Capture 0 / Match Interrupt ."] pub type INT_EVENT0_IMASK_LINC0_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_LINC0_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_LINC0_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_linc0_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_linc0_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_SET) } } # [doc = "Field `INT_EVENT0_IMASK_LINC1` reader - Enable LIN Capture 1 Interrupt."] pub type INT_EVENT0_IMASK_LINC1_R = crate :: BitReader < INT_EVENT0_IMASK_LINC1_A > ; # [doc = "Enable LIN Capture 1 Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_LINC1_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_LINC1_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_LINC1_SET = 1 , } impl From < INT_EVENT0_IMASK_LINC1_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_LINC1_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_LINC1_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_LINC1_A { match self . bits { false => INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_CLR , true => INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_linc1_clr (& self) -> bool { * self == INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_linc1_set (& self) -> bool { * self == INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_SET } } # [doc = "Field `INT_EVENT0_IMASK_LINC1` writer - Enable LIN Capture 1 Interrupt."] pub type INT_EVENT0_IMASK_LINC1_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_LINC1_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_LINC1_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_linc1_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_linc1_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_SET) } } # [doc = "Field `INT_EVENT0_IMASK_LINOVF` reader - Enable LIN Hardware Counter Overflow Interrupt."] pub type INT_EVENT0_IMASK_LINOVF_R = crate :: BitReader < INT_EVENT0_IMASK_LINOVF_A > ; # [doc = "Enable LIN Hardware Counter Overflow Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_LINOVF_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_LINOVF_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_LINOVF_SET = 1 , } impl From < INT_EVENT0_IMASK_LINOVF_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_LINOVF_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_LINOVF_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_LINOVF_A { match self . bits { false => INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_CLR , true => INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_linovf_clr (& self) -> bool { * self == INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_linovf_set (& self) -> bool { * self == INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_SET } } # [doc = "Field `INT_EVENT0_IMASK_LINOVF` writer - Enable LIN Hardware Counter Overflow Interrupt."] pub type INT_EVENT0_IMASK_LINOVF_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_LINOVF_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_LINOVF_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_linovf_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_linovf_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_SET) } } # [doc = "Field `INT_EVENT0_IMASK_RXINT` reader - Enable UART Receive Interrupt."] pub type INT_EVENT0_IMASK_RXINT_R = crate :: BitReader < INT_EVENT0_IMASK_RXINT_A > ; # [doc = "Enable UART Receive Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_RXINT_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_RXINT_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_RXINT_SET = 1 , } impl From < INT_EVENT0_IMASK_RXINT_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_RXINT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_RXINT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_RXINT_A { match self . bits { false => INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_CLR , true => INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_rxint_clr (& self) -> bool { * self == INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_rxint_set (& self) -> bool { * self == INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_SET } } # [doc = "Field `INT_EVENT0_IMASK_RXINT` writer - Enable UART Receive Interrupt."] pub type INT_EVENT0_IMASK_RXINT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_RXINT_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_RXINT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_rxint_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_rxint_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_SET) } } # [doc = "Field `INT_EVENT0_IMASK_TXINT` reader - Enable UART Transmit Interrupt."] pub type INT_EVENT0_IMASK_TXINT_R = crate :: BitReader < INT_EVENT0_IMASK_TXINT_A > ; # [doc = "Enable UART Transmit Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_TXINT_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_TXINT_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_TXINT_SET = 1 , } impl From < INT_EVENT0_IMASK_TXINT_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_TXINT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_TXINT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_TXINT_A { match self . bits { false => INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_CLR , true => INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_txint_clr (& self) -> bool { * self == INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_txint_set (& self) -> bool { * self == INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_SET } } # [doc = "Field `INT_EVENT0_IMASK_TXINT` writer - Enable UART Transmit Interrupt."] pub type INT_EVENT0_IMASK_TXINT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_TXINT_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_TXINT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_txint_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_txint_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_SET) } } # [doc = "Field `INT_EVENT0_IMASK_EOT` reader - Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] pub type INT_EVENT0_IMASK_EOT_R = crate :: BitReader < INT_EVENT0_IMASK_EOT_A > ; # [doc = "Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_EOT_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_EOT_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_EOT_SET = 1 , } impl From < INT_EVENT0_IMASK_EOT_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_EOT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_EOT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_EOT_A { match self . bits { false => INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_CLR , true => INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_eot_clr (& self) -> bool { * self == INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_eot_set (& self) -> bool { * self == INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_SET } } # [doc = "Field `INT_EVENT0_IMASK_EOT` writer - Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] pub type INT_EVENT0_IMASK_EOT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_EOT_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_EOT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_eot_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_eot_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_SET) } } # [doc = "Field `INT_EVENT0_IMASK_ADDR_MATCH` reader - Enable Address Match Interrupt."] pub type INT_EVENT0_IMASK_ADDR_MATCH_R = crate :: BitReader < INT_EVENT0_IMASK_ADDR_MATCH_A > ; # [doc = "Enable Address Match Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_ADDR_MATCH_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_ADDR_MATCH_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_ADDR_MATCH_SET = 1 , } impl From < INT_EVENT0_IMASK_ADDR_MATCH_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_ADDR_MATCH_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_ADDR_MATCH_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_ADDR_MATCH_A { match self . bits { false => INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_CLR , true => INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_addr_match_clr (& self) -> bool { * self == INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_addr_match_set (& self) -> bool { * self == INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_SET } } # [doc = "Field `INT_EVENT0_IMASK_ADDR_MATCH` writer - Enable Address Match Interrupt."] pub type INT_EVENT0_IMASK_ADDR_MATCH_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_ADDR_MATCH_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_ADDR_MATCH_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_addr_match_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_addr_match_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_SET) } } # [doc = "Field `INT_EVENT0_IMASK_CTS` reader - Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] pub type INT_EVENT0_IMASK_CTS_R = crate :: BitReader < INT_EVENT0_IMASK_CTS_A > ; # [doc = "Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_CTS_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_CTS_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_CTS_SET = 1 , } impl From < INT_EVENT0_IMASK_CTS_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_CTS_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_CTS_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_CTS_A { match self . bits { false => INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_CLR , true => INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_cts_clr (& self) -> bool { * self == INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_cts_set (& self) -> bool { * self == INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_SET } } # [doc = "Field `INT_EVENT0_IMASK_CTS` writer - Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] pub type INT_EVENT0_IMASK_CTS_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_CTS_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_CTS_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_cts_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_cts_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DMA_DONE_RX` reader - Enable DMA Done on RX Event Channel"] pub type INT_EVENT0_IMASK_DMA_DONE_RX_R = crate :: BitReader < INT_EVENT0_IMASK_DMA_DONE_RX_A > ; # [doc = "Enable DMA Done on RX Event Channel\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DMA_DONE_RX_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DMA_DONE_RX_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DMA_DONE_RX_SET = 1 , } impl From < INT_EVENT0_IMASK_DMA_DONE_RX_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DMA_DONE_RX_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DMA_DONE_RX_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DMA_DONE_RX_A { match self . bits { false => INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_CLR , true => INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dma_done_rx_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dma_done_rx_set (& self) -> bool { * self == INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_SET } } # [doc = "Field `INT_EVENT0_IMASK_DMA_DONE_RX` writer - Enable DMA Done on RX Event Channel"] pub type INT_EVENT0_IMASK_DMA_DONE_RX_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DMA_DONE_RX_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DMA_DONE_RX_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dma_done_rx_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dma_done_rx_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DMA_DONE_TX` reader - Enable DMA Done on TX Event Channel"] pub type INT_EVENT0_IMASK_DMA_DONE_TX_R = crate :: BitReader < INT_EVENT0_IMASK_DMA_DONE_TX_A > ; # [doc = "Enable DMA Done on TX Event Channel\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DMA_DONE_TX_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DMA_DONE_TX_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DMA_DONE_TX_SET = 1 , } impl From < INT_EVENT0_IMASK_DMA_DONE_TX_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DMA_DONE_TX_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DMA_DONE_TX_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DMA_DONE_TX_A { match self . bits { false => INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_CLR , true => INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dma_done_tx_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dma_done_tx_set (& self) -> bool { * self == INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_SET } } # [doc = "Field `INT_EVENT0_IMASK_DMA_DONE_TX` writer - Enable DMA Done on TX Event Channel"] pub type INT_EVENT0_IMASK_DMA_DONE_TX_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DMA_DONE_TX_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DMA_DONE_TX_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dma_done_tx_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dma_done_tx_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_SET) } } # [doc = "Field `INT_EVENT0_IMASK_NERR` reader - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] pub type INT_EVENT0_IMASK_NERR_R = crate :: BitReader < INT_EVENT0_IMASK_NERR_A > ; # [doc = "Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_NERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_NERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_NERR_SET = 1 , } impl From < INT_EVENT0_IMASK_NERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_NERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_NERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_NERR_A { match self . bits { false => INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_CLR , true => INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_nerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_nerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_NERR` writer - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] pub type INT_EVENT0_IMASK_NERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_NERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_NERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_nerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_nerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_SET) } } impl R { # [doc = "Bit 0 - Enable UARTOUT Receive Time-Out Interrupt."] # [inline (always)] pub fn int_event0_imask_rtout (& self) -> INT_EVENT0_IMASK_RTOUT_R { INT_EVENT0_IMASK_RTOUT_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - Enable UART Framing Error Interrupt."] # [inline (always)] pub fn int_event0_imask_frmerr (& self) -> INT_EVENT0_IMASK_FRMERR_R { INT_EVENT0_IMASK_FRMERR_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - Enable UART Parity Error Interrupt."] # [inline (always)] pub fn int_event0_imask_parerr (& self) -> INT_EVENT0_IMASK_PARERR_R { INT_EVENT0_IMASK_PARERR_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - Enable UART Break Error Interrupt."] # [inline (always)] pub fn int_event0_imask_brkerr (& self) -> INT_EVENT0_IMASK_BRKERR_R { INT_EVENT0_IMASK_BRKERR_R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - Enable UART Receive Overrun Error Interrupt."] # [inline (always)] pub fn int_event0_imask_ovrerr (& self) -> INT_EVENT0_IMASK_OVRERR_R { INT_EVENT0_IMASK_OVRERR_R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - Enable Negative Edge on UARTxRXD Interrupt."] # [inline (always)] pub fn int_event0_imask_rxne (& self) -> INT_EVENT0_IMASK_RXNE_R { INT_EVENT0_IMASK_RXNE_R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - Enable Positive Edge on UARTxRXD Interrupt."] # [inline (always)] pub fn int_event0_imask_rxpe (& self) -> INT_EVENT0_IMASK_RXPE_R { INT_EVENT0_IMASK_RXPE_R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - Enable LIN Capture 0 / Match Interrupt ."] # [inline (always)] pub fn int_event0_imask_linc0 (& self) -> INT_EVENT0_IMASK_LINC0_R { INT_EVENT0_IMASK_LINC0_R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - Enable LIN Capture 1 Interrupt."] # [inline (always)] pub fn int_event0_imask_linc1 (& self) -> INT_EVENT0_IMASK_LINC1_R { INT_EVENT0_IMASK_LINC1_R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - Enable LIN Hardware Counter Overflow Interrupt."] # [inline (always)] pub fn int_event0_imask_linovf (& self) -> INT_EVENT0_IMASK_LINOVF_R { INT_EVENT0_IMASK_LINOVF_R :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - Enable UART Receive Interrupt."] # [inline (always)] pub fn int_event0_imask_rxint (& self) -> INT_EVENT0_IMASK_RXINT_R { INT_EVENT0_IMASK_RXINT_R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - Enable UART Transmit Interrupt."] # [inline (always)] pub fn int_event0_imask_txint (& self) -> INT_EVENT0_IMASK_TXINT_R { INT_EVENT0_IMASK_TXINT_R :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] # [inline (always)] pub fn int_event0_imask_eot (& self) -> INT_EVENT0_IMASK_EOT_R { INT_EVENT0_IMASK_EOT_R :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - Enable Address Match Interrupt."] # [inline (always)] pub fn int_event0_imask_addr_match (& self) -> INT_EVENT0_IMASK_ADDR_MATCH_R { INT_EVENT0_IMASK_ADDR_MATCH_R :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 14 - Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] # [inline (always)] pub fn int_event0_imask_cts (& self) -> INT_EVENT0_IMASK_CTS_R { INT_EVENT0_IMASK_CTS_R :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - Enable DMA Done on RX Event Channel"] # [inline (always)] pub fn int_event0_imask_dma_done_rx (& self) -> INT_EVENT0_IMASK_DMA_DONE_RX_R { INT_EVENT0_IMASK_DMA_DONE_RX_R :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bit 16 - Enable DMA Done on TX Event Channel"] # [inline (always)] pub fn int_event0_imask_dma_done_tx (& self) -> INT_EVENT0_IMASK_DMA_DONE_TX_R { INT_EVENT0_IMASK_DMA_DONE_TX_R :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] # [inline (always)] pub fn int_event0_imask_nerr (& self) -> INT_EVENT0_IMASK_NERR_R { INT_EVENT0_IMASK_NERR_R :: new (((self . bits >> 17) & 1) != 0) } } impl W { # [doc = "Bit 0 - Enable UARTOUT Receive Time-Out Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_rtout (& mut self) -> INT_EVENT0_IMASK_RTOUT_W < INT_EVENT0_IMASK_SPEC , 0 > { INT_EVENT0_IMASK_RTOUT_W :: new (self) } # [doc = "Bit 1 - Enable UART Framing Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_frmerr (& mut self) -> INT_EVENT0_IMASK_FRMERR_W < INT_EVENT0_IMASK_SPEC , 1 > { INT_EVENT0_IMASK_FRMERR_W :: new (self) } # [doc = "Bit 2 - Enable UART Parity Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_parerr (& mut self) -> INT_EVENT0_IMASK_PARERR_W < INT_EVENT0_IMASK_SPEC , 2 > { INT_EVENT0_IMASK_PARERR_W :: new (self) } # [doc = "Bit 3 - Enable UART Break Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_brkerr (& mut self) -> INT_EVENT0_IMASK_BRKERR_W < INT_EVENT0_IMASK_SPEC , 3 > { INT_EVENT0_IMASK_BRKERR_W :: new (self) } # [doc = "Bit 4 - Enable UART Receive Overrun Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_ovrerr (& mut self) -> INT_EVENT0_IMASK_OVRERR_W < INT_EVENT0_IMASK_SPEC , 4 > { INT_EVENT0_IMASK_OVRERR_W :: new (self) } # [doc = "Bit 5 - Enable Negative Edge on UARTxRXD Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_rxne (& mut self) -> INT_EVENT0_IMASK_RXNE_W <'_,  INT_EVENT0_IMASK_SPEC , 5 > { INT_EVENT0_IMASK_RXNE_W :: new (self) } # [doc = "Bit 6 - Enable Positive Edge on UARTxRXD Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_rxpe (& mut self) -> INT_EVENT0_IMASK_RXPE_W < INT_EVENT0_IMASK_SPEC , 6 > { INT_EVENT0_IMASK_RXPE_W :: new (self) } # [doc = "Bit 7 - Enable LIN Capture 0 / Match Interrupt ."] # [inline (always)] # [must_use] pub fn int_event0_imask_linc0 (& mut self) -> INT_EVENT0_IMASK_LINC0_W < INT_EVENT0_IMASK_SPEC , 7 > { INT_EVENT0_IMASK_LINC0_W :: new (self) } # [doc = "Bit 8 - Enable LIN Capture 1 Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_linc1 (& mut self) -> INT_EVENT0_IMASK_LINC1_W < INT_EVENT0_IMASK_SPEC , 8 > { INT_EVENT0_IMASK_LINC1_W :: new (self) } # [doc = "Bit 9 - Enable LIN Hardware Counter Overflow Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_linovf (& mut self) -> INT_EVENT0_IMASK_LINOVF_W < INT_EVENT0_IMASK_SPEC , 9 > { INT_EVENT0_IMASK_LINOVF_W :: new (self) } # [doc = "Bit 10 - Enable UART Receive Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_rxint (& mut self) -> INT_EVENT0_IMASK_RXINT_W < INT_EVENT0_IMASK_SPEC , 10 > { INT_EVENT0_IMASK_RXINT_W :: new (self) } # [doc = "Bit 11 - Enable UART Transmit Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_txint (& mut self) -> INT_EVENT0_IMASK_TXINT_W < INT_EVENT0_IMASK_SPEC , 11 > { INT_EVENT0_IMASK_TXINT_W :: new (self) } # [doc = "Bit 12 - Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] # [inline (always)] # [must_use] pub fn int_event0_imask_eot (& mut self) -> INT_EVENT0_IMASK_EOT_W < INT_EVENT0_IMASK_SPEC , 12 > { INT_EVENT0_IMASK_EOT_W :: new (self) } # [doc = "Bit 13 - Enable Address Match Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_addr_match (& mut self) -> INT_EVENT0_IMASK_ADDR_MATCH_W < INT_EVENT0_IMASK_SPEC , 13 > { INT_EVENT0_IMASK_ADDR_MATCH_W :: new (self) } # [doc = "Bit 14 - Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] # [inline (always)] # [must_use] pub fn int_event0_imask_cts (& mut self) -> INT_EVENT0_IMASK_CTS_W < INT_EVENT0_IMASK_SPEC , 14 > { INT_EVENT0_IMASK_CTS_W :: new (self) } # [doc = "Bit 15 - Enable DMA Done on RX Event Channel"] # [inline (always)] # [must_use] pub fn int_event0_imask_dma_done_rx (& mut self) -> INT_EVENT0_IMASK_DMA_DONE_RX_W < INT_EVENT0_IMASK_SPEC , 15 > { INT_EVENT0_IMASK_DMA_DONE_RX_W :: new (self) } # [doc = "Bit 16 - Enable DMA Done on TX Event Channel"] # [inline (always)] # [must_use] pub fn int_event0_imask_dma_done_tx (& mut self) -> INT_EVENT0_IMASK_DMA_DONE_TX_W < INT_EVENT0_IMASK_SPEC , 16 > { INT_EVENT0_IMASK_DMA_DONE_TX_W :: new (self) } # [doc = "Bit 17 - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] # [inline (always)] # [must_use] pub fn int_event0_imask_nerr (& mut self) -> INT_EVENT0_IMASK_NERR_W < INT_EVENT0_IMASK_SPEC , 17 > { INT_EVENT0_IMASK_NERR_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Interrupt mask\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_event0_imask::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_event0_imask::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct INT_EVENT0_IMASK_SPEC ; impl crate :: RegisterSpec for INT_EVENT0_IMASK_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`int_event0_imask::R`](R) reader structure"] impl crate :: Readable for INT_EVENT0_IMASK_SPEC { } # [doc = "`write(|w| ..)` method takes [`int_event0_imask::W`](W) writer structure"] impl crate :: Writable for INT_EVENT0_IMASK_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets INT_EVENT0_IMASK to value 0"] impl crate :: Resettable for INT_EVENT0_IMASK_SPEC { const RESET_VALUE : Self :: Ux = 0 ; }
[INFO] [stdout]   |                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                   +++
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing
[INFO] [stdout]  --> src/uart0/int_event0_imask.rs:1:41929
[INFO] [stdout]   |
[INFO] [stdout] 1 | ...0_imask_rxpe (& mut self) -> INT_EVENT0_IMASK_RXPE_W < INT_EVENT0_IMASK_SPEC , 6 > { INT_EVENT0_IMASK_RXPE_W :: new (self) } # [do...
[INFO] [stdout]   |                  ^^^^^^^^^^     ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here
[INFO] [stdout]   |                  |
[INFO] [stdout]   |                  the lifetime is elided here
[INFO] [stdout]   |
[INFO] [stdout]   = help: the same lifetime is referred to in inconsistent ways, making the signature confusing
[INFO] [stdout] help: use `'_` for type paths
[INFO] [stdout]   |
[INFO] [stdout] 1 | # [doc = "Register `INT_EVENT0_IMASK` reader"] pub type R = crate :: R < INT_EVENT0_IMASK_SPEC > ; # [doc = "Register `INT_EVENT0_IMASK` writer"] pub type W = crate :: W < INT_EVENT0_IMASK_SPEC > ; # [doc = "Field `INT_EVENT0_IMASK_RTOUT` reader - Enable UARTOUT Receive Time-Out Interrupt."] pub type INT_EVENT0_IMASK_RTOUT_R = crate :: BitReader < INT_EVENT0_IMASK_RTOUT_A > ; # [doc = "Enable UARTOUT Receive Time-Out Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_RTOUT_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_RTOUT_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_RTOUT_SET = 1 , } impl From < INT_EVENT0_IMASK_RTOUT_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_RTOUT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_RTOUT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_RTOUT_A { match self . bits { false => INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_CLR , true => INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_rtout_clr (& self) -> bool { * self == INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_rtout_set (& self) -> bool { * self == INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_SET } } # [doc = "Field `INT_EVENT0_IMASK_RTOUT` writer - Enable UARTOUT Receive Time-Out Interrupt."] pub type INT_EVENT0_IMASK_RTOUT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_RTOUT_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_RTOUT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_rtout_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_rtout_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_SET) } } # [doc = "Field `INT_EVENT0_IMASK_FRMERR` reader - Enable UART Framing Error Interrupt."] pub type INT_EVENT0_IMASK_FRMERR_R = crate :: BitReader < INT_EVENT0_IMASK_FRMERR_A > ; # [doc = "Enable UART Framing Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_FRMERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_FRMERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_FRMERR_SET = 1 , } impl From < INT_EVENT0_IMASK_FRMERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_FRMERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_FRMERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_FRMERR_A { match self . bits { false => INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_CLR , true => INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_frmerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_frmerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_FRMERR` writer - Enable UART Framing Error Interrupt."] pub type INT_EVENT0_IMASK_FRMERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_FRMERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_FRMERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_frmerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_frmerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_SET) } } # [doc = "Field `INT_EVENT0_IMASK_PARERR` reader - Enable UART Parity Error Interrupt."] pub type INT_EVENT0_IMASK_PARERR_R = crate :: BitReader < INT_EVENT0_IMASK_PARERR_A > ; # [doc = "Enable UART Parity Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_PARERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_PARERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_PARERR_SET = 1 , } impl From < INT_EVENT0_IMASK_PARERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_PARERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_PARERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_PARERR_A { match self . bits { false => INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_CLR , true => INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_parerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_parerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_PARERR` writer - Enable UART Parity Error Interrupt."] pub type INT_EVENT0_IMASK_PARERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_PARERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_PARERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_parerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_parerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_SET) } } # [doc = "Field `INT_EVENT0_IMASK_BRKERR` reader - Enable UART Break Error Interrupt."] pub type INT_EVENT0_IMASK_BRKERR_R = crate :: BitReader < INT_EVENT0_IMASK_BRKERR_A > ; # [doc = "Enable UART Break Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_BRKERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_BRKERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_BRKERR_SET = 1 , } impl From < INT_EVENT0_IMASK_BRKERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_BRKERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_BRKERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_BRKERR_A { match self . bits { false => INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_CLR , true => INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_brkerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_brkerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_BRKERR` writer - Enable UART Break Error Interrupt."] pub type INT_EVENT0_IMASK_BRKERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_BRKERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_BRKERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_brkerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_brkerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_SET) } } # [doc = "Field `INT_EVENT0_IMASK_OVRERR` reader - Enable UART Receive Overrun Error Interrupt."] pub type INT_EVENT0_IMASK_OVRERR_R = crate :: BitReader < INT_EVENT0_IMASK_OVRERR_A > ; # [doc = "Enable UART Receive Overrun Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_OVRERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_OVRERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_OVRERR_SET = 1 , } impl From < INT_EVENT0_IMASK_OVRERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_OVRERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_OVRERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_OVRERR_A { match self . bits { false => INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_CLR , true => INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_ovrerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_ovrerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_OVRERR` writer - Enable UART Receive Overrun Error Interrupt."] pub type INT_EVENT0_IMASK_OVRERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_OVRERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_OVRERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_ovrerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_ovrerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_SET) } } # [doc = "Field `INT_EVENT0_IMASK_RXNE` reader - Enable Negative Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_IMASK_RXNE_R = crate :: BitReader < INT_EVENT0_IMASK_RXNE_A > ; # [doc = "Enable Negative Edge on UARTxRXD Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_RXNE_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_RXNE_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_RXNE_SET = 1 , } impl From < INT_EVENT0_IMASK_RXNE_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_RXNE_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_RXNE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_RXNE_A { match self . bits { false => INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_CLR , true => INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_rxne_clr (& self) -> bool { * self == INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_rxne_set (& self) -> bool { * self == INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_SET } } # [doc = "Field `INT_EVENT0_IMASK_RXNE` writer - Enable Negative Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_IMASK_RXNE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_RXNE_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_RXNE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_rxne_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_rxne_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_SET) } } # [doc = "Field `INT_EVENT0_IMASK_RXPE` reader - Enable Positive Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_IMASK_RXPE_R = crate :: BitReader < INT_EVENT0_IMASK_RXPE_A > ; # [doc = "Enable Positive Edge on UARTxRXD Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_RXPE_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_RXPE_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_RXPE_SET = 1 , } impl From < INT_EVENT0_IMASK_RXPE_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_RXPE_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_RXPE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_RXPE_A { match self . bits { false => INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_CLR , true => INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_rxpe_clr (& self) -> bool { * self == INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_rxpe_set (& self) -> bool { * self == INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_SET } } # [doc = "Field `INT_EVENT0_IMASK_RXPE` writer - Enable Positive Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_IMASK_RXPE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_RXPE_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_RXPE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_rxpe_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_rxpe_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_SET) } } # [doc = "Field `INT_EVENT0_IMASK_LINC0` reader - Enable LIN Capture 0 / Match Interrupt ."] pub type INT_EVENT0_IMASK_LINC0_R = crate :: BitReader < INT_EVENT0_IMASK_LINC0_A > ; # [doc = "Enable LIN Capture 0 / Match Interrupt .\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_LINC0_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_LINC0_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_LINC0_SET = 1 , } impl From < INT_EVENT0_IMASK_LINC0_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_LINC0_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_LINC0_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_LINC0_A { match self . bits { false => INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_CLR , true => INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_linc0_clr (& self) -> bool { * self == INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_linc0_set (& self) -> bool { * self == INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_SET } } # [doc = "Field `INT_EVENT0_IMASK_LINC0` writer - Enable LIN Capture 0 / Match Interrupt ."] pub type INT_EVENT0_IMASK_LINC0_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_LINC0_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_LINC0_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_linc0_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_linc0_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_SET) } } # [doc = "Field `INT_EVENT0_IMASK_LINC1` reader - Enable LIN Capture 1 Interrupt."] pub type INT_EVENT0_IMASK_LINC1_R = crate :: BitReader < INT_EVENT0_IMASK_LINC1_A > ; # [doc = "Enable LIN Capture 1 Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_LINC1_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_LINC1_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_LINC1_SET = 1 , } impl From < INT_EVENT0_IMASK_LINC1_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_LINC1_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_LINC1_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_LINC1_A { match self . bits { false => INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_CLR , true => INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_linc1_clr (& self) -> bool { * self == INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_linc1_set (& self) -> bool { * self == INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_SET } } # [doc = "Field `INT_EVENT0_IMASK_LINC1` writer - Enable LIN Capture 1 Interrupt."] pub type INT_EVENT0_IMASK_LINC1_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_LINC1_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_LINC1_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_linc1_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_linc1_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_SET) } } # [doc = "Field `INT_EVENT0_IMASK_LINOVF` reader - Enable LIN Hardware Counter Overflow Interrupt."] pub type INT_EVENT0_IMASK_LINOVF_R = crate :: BitReader < INT_EVENT0_IMASK_LINOVF_A > ; # [doc = "Enable LIN Hardware Counter Overflow Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_LINOVF_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_LINOVF_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_LINOVF_SET = 1 , } impl From < INT_EVENT0_IMASK_LINOVF_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_LINOVF_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_LINOVF_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_LINOVF_A { match self . bits { false => INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_CLR , true => INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_linovf_clr (& self) -> bool { * self == INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_linovf_set (& self) -> bool { * self == INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_SET } } # [doc = "Field `INT_EVENT0_IMASK_LINOVF` writer - Enable LIN Hardware Counter Overflow Interrupt."] pub type INT_EVENT0_IMASK_LINOVF_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_LINOVF_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_LINOVF_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_linovf_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_linovf_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_SET) } } # [doc = "Field `INT_EVENT0_IMASK_RXINT` reader - Enable UART Receive Interrupt."] pub type INT_EVENT0_IMASK_RXINT_R = crate :: BitReader < INT_EVENT0_IMASK_RXINT_A > ; # [doc = "Enable UART Receive Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_RXINT_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_RXINT_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_RXINT_SET = 1 , } impl From < INT_EVENT0_IMASK_RXINT_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_RXINT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_RXINT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_RXINT_A { match self . bits { false => INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_CLR , true => INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_rxint_clr (& self) -> bool { * self == INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_rxint_set (& self) -> bool { * self == INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_SET } } # [doc = "Field `INT_EVENT0_IMASK_RXINT` writer - Enable UART Receive Interrupt."] pub type INT_EVENT0_IMASK_RXINT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_RXINT_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_RXINT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_rxint_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_rxint_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_SET) } } # [doc = "Field `INT_EVENT0_IMASK_TXINT` reader - Enable UART Transmit Interrupt."] pub type INT_EVENT0_IMASK_TXINT_R = crate :: BitReader < INT_EVENT0_IMASK_TXINT_A > ; # [doc = "Enable UART Transmit Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_TXINT_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_TXINT_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_TXINT_SET = 1 , } impl From < INT_EVENT0_IMASK_TXINT_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_TXINT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_TXINT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_TXINT_A { match self . bits { false => INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_CLR , true => INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_txint_clr (& self) -> bool { * self == INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_txint_set (& self) -> bool { * self == INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_SET } } # [doc = "Field `INT_EVENT0_IMASK_TXINT` writer - Enable UART Transmit Interrupt."] pub type INT_EVENT0_IMASK_TXINT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_TXINT_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_TXINT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_txint_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_txint_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_SET) } } # [doc = "Field `INT_EVENT0_IMASK_EOT` reader - Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] pub type INT_EVENT0_IMASK_EOT_R = crate :: BitReader < INT_EVENT0_IMASK_EOT_A > ; # [doc = "Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_EOT_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_EOT_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_EOT_SET = 1 , } impl From < INT_EVENT0_IMASK_EOT_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_EOT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_EOT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_EOT_A { match self . bits { false => INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_CLR , true => INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_eot_clr (& self) -> bool { * self == INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_eot_set (& self) -> bool { * self == INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_SET } } # [doc = "Field `INT_EVENT0_IMASK_EOT` writer - Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] pub type INT_EVENT0_IMASK_EOT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_EOT_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_EOT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_eot_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_eot_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_SET) } } # [doc = "Field `INT_EVENT0_IMASK_ADDR_MATCH` reader - Enable Address Match Interrupt."] pub type INT_EVENT0_IMASK_ADDR_MATCH_R = crate :: BitReader < INT_EVENT0_IMASK_ADDR_MATCH_A > ; # [doc = "Enable Address Match Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_ADDR_MATCH_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_ADDR_MATCH_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_ADDR_MATCH_SET = 1 , } impl From < INT_EVENT0_IMASK_ADDR_MATCH_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_ADDR_MATCH_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_ADDR_MATCH_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_ADDR_MATCH_A { match self . bits { false => INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_CLR , true => INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_addr_match_clr (& self) -> bool { * self == INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_addr_match_set (& self) -> bool { * self == INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_SET } } # [doc = "Field `INT_EVENT0_IMASK_ADDR_MATCH` writer - Enable Address Match Interrupt."] pub type INT_EVENT0_IMASK_ADDR_MATCH_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_ADDR_MATCH_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_ADDR_MATCH_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_addr_match_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_addr_match_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_SET) } } # [doc = "Field `INT_EVENT0_IMASK_CTS` reader - Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] pub type INT_EVENT0_IMASK_CTS_R = crate :: BitReader < INT_EVENT0_IMASK_CTS_A > ; # [doc = "Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_CTS_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_CTS_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_CTS_SET = 1 , } impl From < INT_EVENT0_IMASK_CTS_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_CTS_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_CTS_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_CTS_A { match self . bits { false => INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_CLR , true => INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_cts_clr (& self) -> bool { * self == INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_cts_set (& self) -> bool { * self == INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_SET } } # [doc = "Field `INT_EVENT0_IMASK_CTS` writer - Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] pub type INT_EVENT0_IMASK_CTS_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_CTS_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_CTS_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_cts_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_cts_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DMA_DONE_RX` reader - Enable DMA Done on RX Event Channel"] pub type INT_EVENT0_IMASK_DMA_DONE_RX_R = crate :: BitReader < INT_EVENT0_IMASK_DMA_DONE_RX_A > ; # [doc = "Enable DMA Done on RX Event Channel\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DMA_DONE_RX_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DMA_DONE_RX_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DMA_DONE_RX_SET = 1 , } impl From < INT_EVENT0_IMASK_DMA_DONE_RX_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DMA_DONE_RX_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DMA_DONE_RX_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DMA_DONE_RX_A { match self . bits { false => INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_CLR , true => INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dma_done_rx_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dma_done_rx_set (& self) -> bool { * self == INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_SET } } # [doc = "Field `INT_EVENT0_IMASK_DMA_DONE_RX` writer - Enable DMA Done on RX Event Channel"] pub type INT_EVENT0_IMASK_DMA_DONE_RX_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DMA_DONE_RX_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DMA_DONE_RX_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dma_done_rx_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dma_done_rx_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DMA_DONE_TX` reader - Enable DMA Done on TX Event Channel"] pub type INT_EVENT0_IMASK_DMA_DONE_TX_R = crate :: BitReader < INT_EVENT0_IMASK_DMA_DONE_TX_A > ; # [doc = "Enable DMA Done on TX Event Channel\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DMA_DONE_TX_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DMA_DONE_TX_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DMA_DONE_TX_SET = 1 , } impl From < INT_EVENT0_IMASK_DMA_DONE_TX_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DMA_DONE_TX_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DMA_DONE_TX_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DMA_DONE_TX_A { match self . bits { false => INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_CLR , true => INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dma_done_tx_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dma_done_tx_set (& self) -> bool { * self == INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_SET } } # [doc = "Field `INT_EVENT0_IMASK_DMA_DONE_TX` writer - Enable DMA Done on TX Event Channel"] pub type INT_EVENT0_IMASK_DMA_DONE_TX_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DMA_DONE_TX_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DMA_DONE_TX_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dma_done_tx_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dma_done_tx_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_SET) } } # [doc = "Field `INT_EVENT0_IMASK_NERR` reader - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] pub type INT_EVENT0_IMASK_NERR_R = crate :: BitReader < INT_EVENT0_IMASK_NERR_A > ; # [doc = "Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_NERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_NERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_NERR_SET = 1 , } impl From < INT_EVENT0_IMASK_NERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_NERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_NERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_NERR_A { match self . bits { false => INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_CLR , true => INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_nerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_nerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_NERR` writer - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] pub type INT_EVENT0_IMASK_NERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_NERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_NERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_nerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_nerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_SET) } } impl R { # [doc = "Bit 0 - Enable UARTOUT Receive Time-Out Interrupt."] # [inline (always)] pub fn int_event0_imask_rtout (& self) -> INT_EVENT0_IMASK_RTOUT_R { INT_EVENT0_IMASK_RTOUT_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - Enable UART Framing Error Interrupt."] # [inline (always)] pub fn int_event0_imask_frmerr (& self) -> INT_EVENT0_IMASK_FRMERR_R { INT_EVENT0_IMASK_FRMERR_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - Enable UART Parity Error Interrupt."] # [inline (always)] pub fn int_event0_imask_parerr (& self) -> INT_EVENT0_IMASK_PARERR_R { INT_EVENT0_IMASK_PARERR_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - Enable UART Break Error Interrupt."] # [inline (always)] pub fn int_event0_imask_brkerr (& self) -> INT_EVENT0_IMASK_BRKERR_R { INT_EVENT0_IMASK_BRKERR_R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - Enable UART Receive Overrun Error Interrupt."] # [inline (always)] pub fn int_event0_imask_ovrerr (& self) -> INT_EVENT0_IMASK_OVRERR_R { INT_EVENT0_IMASK_OVRERR_R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - Enable Negative Edge on UARTxRXD Interrupt."] # [inline (always)] pub fn int_event0_imask_rxne (& self) -> INT_EVENT0_IMASK_RXNE_R { INT_EVENT0_IMASK_RXNE_R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - Enable Positive Edge on UARTxRXD Interrupt."] # [inline (always)] pub fn int_event0_imask_rxpe (& self) -> INT_EVENT0_IMASK_RXPE_R { INT_EVENT0_IMASK_RXPE_R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - Enable LIN Capture 0 / Match Interrupt ."] # [inline (always)] pub fn int_event0_imask_linc0 (& self) -> INT_EVENT0_IMASK_LINC0_R { INT_EVENT0_IMASK_LINC0_R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - Enable LIN Capture 1 Interrupt."] # [inline (always)] pub fn int_event0_imask_linc1 (& self) -> INT_EVENT0_IMASK_LINC1_R { INT_EVENT0_IMASK_LINC1_R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - Enable LIN Hardware Counter Overflow Interrupt."] # [inline (always)] pub fn int_event0_imask_linovf (& self) -> INT_EVENT0_IMASK_LINOVF_R { INT_EVENT0_IMASK_LINOVF_R :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - Enable UART Receive Interrupt."] # [inline (always)] pub fn int_event0_imask_rxint (& self) -> INT_EVENT0_IMASK_RXINT_R { INT_EVENT0_IMASK_RXINT_R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - Enable UART Transmit Interrupt."] # [inline (always)] pub fn int_event0_imask_txint (& self) -> INT_EVENT0_IMASK_TXINT_R { INT_EVENT0_IMASK_TXINT_R :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] # [inline (always)] pub fn int_event0_imask_eot (& self) -> INT_EVENT0_IMASK_EOT_R { INT_EVENT0_IMASK_EOT_R :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - Enable Address Match Interrupt."] # [inline (always)] pub fn int_event0_imask_addr_match (& self) -> INT_EVENT0_IMASK_ADDR_MATCH_R { INT_EVENT0_IMASK_ADDR_MATCH_R :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 14 - Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] # [inline (always)] pub fn int_event0_imask_cts (& self) -> INT_EVENT0_IMASK_CTS_R { INT_EVENT0_IMASK_CTS_R :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - Enable DMA Done on RX Event Channel"] # [inline (always)] pub fn int_event0_imask_dma_done_rx (& self) -> INT_EVENT0_IMASK_DMA_DONE_RX_R { INT_EVENT0_IMASK_DMA_DONE_RX_R :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bit 16 - Enable DMA Done on TX Event Channel"] # [inline (always)] pub fn int_event0_imask_dma_done_tx (& self) -> INT_EVENT0_IMASK_DMA_DONE_TX_R { INT_EVENT0_IMASK_DMA_DONE_TX_R :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] # [inline (always)] pub fn int_event0_imask_nerr (& self) -> INT_EVENT0_IMASK_NERR_R { INT_EVENT0_IMASK_NERR_R :: new (((self . bits >> 17) & 1) != 0) } } impl W { # [doc = "Bit 0 - Enable UARTOUT Receive Time-Out Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_rtout (& mut self) -> INT_EVENT0_IMASK_RTOUT_W < INT_EVENT0_IMASK_SPEC , 0 > { INT_EVENT0_IMASK_RTOUT_W :: new (self) } # [doc = "Bit 1 - Enable UART Framing Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_frmerr (& mut self) -> INT_EVENT0_IMASK_FRMERR_W < INT_EVENT0_IMASK_SPEC , 1 > { INT_EVENT0_IMASK_FRMERR_W :: new (self) } # [doc = "Bit 2 - Enable UART Parity Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_parerr (& mut self) -> INT_EVENT0_IMASK_PARERR_W < INT_EVENT0_IMASK_SPEC , 2 > { INT_EVENT0_IMASK_PARERR_W :: new (self) } # [doc = "Bit 3 - Enable UART Break Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_brkerr (& mut self) -> INT_EVENT0_IMASK_BRKERR_W < INT_EVENT0_IMASK_SPEC , 3 > { INT_EVENT0_IMASK_BRKERR_W :: new (self) } # [doc = "Bit 4 - Enable UART Receive Overrun Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_ovrerr (& mut self) -> INT_EVENT0_IMASK_OVRERR_W < INT_EVENT0_IMASK_SPEC , 4 > { INT_EVENT0_IMASK_OVRERR_W :: new (self) } # [doc = "Bit 5 - Enable Negative Edge on UARTxRXD Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_rxne (& mut self) -> INT_EVENT0_IMASK_RXNE_W < INT_EVENT0_IMASK_SPEC , 5 > { INT_EVENT0_IMASK_RXNE_W :: new (self) } # [doc = "Bit 6 - Enable Positive Edge on UARTxRXD Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_rxpe (& mut self) -> INT_EVENT0_IMASK_RXPE_W <'_,  INT_EVENT0_IMASK_SPEC , 6 > { INT_EVENT0_IMASK_RXPE_W :: new (self) } # [doc = "Bit 7 - Enable LIN Capture 0 / Match Interrupt ."] # [inline (always)] # [must_use] pub fn int_event0_imask_linc0 (& mut self) -> INT_EVENT0_IMASK_LINC0_W < INT_EVENT0_IMASK_SPEC , 7 > { INT_EVENT0_IMASK_LINC0_W :: new (self) } # [doc = "Bit 8 - Enable LIN Capture 1 Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_linc1 (& mut self) -> INT_EVENT0_IMASK_LINC1_W < INT_EVENT0_IMASK_SPEC , 8 > { INT_EVENT0_IMASK_LINC1_W :: new (self) } # [doc = "Bit 9 - Enable LIN Hardware Counter Overflow Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_linovf (& mut self) -> INT_EVENT0_IMASK_LINOVF_W < INT_EVENT0_IMASK_SPEC , 9 > { INT_EVENT0_IMASK_LINOVF_W :: new (self) } # [doc = "Bit 10 - Enable UART Receive Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_rxint (& mut self) -> INT_EVENT0_IMASK_RXINT_W < INT_EVENT0_IMASK_SPEC , 10 > { INT_EVENT0_IMASK_RXINT_W :: new (self) } # [doc = "Bit 11 - Enable UART Transmit Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_txint (& mut self) -> INT_EVENT0_IMASK_TXINT_W < INT_EVENT0_IMASK_SPEC , 11 > { INT_EVENT0_IMASK_TXINT_W :: new (self) } # [doc = "Bit 12 - Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] # [inline (always)] # [must_use] pub fn int_event0_imask_eot (& mut self) -> INT_EVENT0_IMASK_EOT_W < INT_EVENT0_IMASK_SPEC , 12 > { INT_EVENT0_IMASK_EOT_W :: new (self) } # [doc = "Bit 13 - Enable Address Match Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_addr_match (& mut self) -> INT_EVENT0_IMASK_ADDR_MATCH_W < INT_EVENT0_IMASK_SPEC , 13 > { INT_EVENT0_IMASK_ADDR_MATCH_W :: new (self) } # [doc = "Bit 14 - Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] # [inline (always)] # [must_use] pub fn int_event0_imask_cts (& mut self) -> INT_EVENT0_IMASK_CTS_W < INT_EVENT0_IMASK_SPEC , 14 > { INT_EVENT0_IMASK_CTS_W :: new (self) } # [doc = "Bit 15 - Enable DMA Done on RX Event Channel"] # [inline (always)] # [must_use] pub fn int_event0_imask_dma_done_rx (& mut self) -> INT_EVENT0_IMASK_DMA_DONE_RX_W < INT_EVENT0_IMASK_SPEC , 15 > { INT_EVENT0_IMASK_DMA_DONE_RX_W :: new (self) } # [doc = "Bit 16 - Enable DMA Done on TX Event Channel"] # [inline (always)] # [must_use] pub fn int_event0_imask_dma_done_tx (& mut self) -> INT_EVENT0_IMASK_DMA_DONE_TX_W < INT_EVENT0_IMASK_SPEC , 16 > { INT_EVENT0_IMASK_DMA_DONE_TX_W :: new (self) } # [doc = "Bit 17 - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] # [inline (always)] # [must_use] pub fn int_event0_imask_nerr (& mut self) -> INT_EVENT0_IMASK_NERR_W < INT_EVENT0_IMASK_SPEC , 17 > { INT_EVENT0_IMASK_NERR_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Interrupt mask\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_event0_imask::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_event0_imask::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct INT_EVENT0_IMASK_SPEC ; impl crate :: RegisterSpec for INT_EVENT0_IMASK_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`int_event0_imask::R`](R) reader structure"] impl crate :: Readable for INT_EVENT0_IMASK_SPEC { } # [doc = "`write(|w| ..)` method takes [`int_event0_imask::W`](W) writer structure"] impl crate :: Writable for INT_EVENT0_IMASK_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets INT_EVENT0_IMASK to value 0"] impl crate :: Resettable for INT_EVENT0_IMASK_SPEC { const RESET_VALUE : Self :: Ux = 0 ; }
[INFO] [stdout]   |                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                 +++
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing
[INFO] [stdout]  --> src/uart0/int_event0_imask.rs:1:42165
[INFO] [stdout]   |
[INFO] [stdout] 1 | ..._imask_linc0 (& mut self) -> INT_EVENT0_IMASK_LINC0_W < INT_EVENT0_IMASK_SPEC , 7 > { INT_EVENT0_IMASK_LINC0_W :: new (self) } # [...
[INFO] [stdout]   |                  ^^^^^^^^^^     ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here
[INFO] [stdout]   |                  |
[INFO] [stdout]   |                  the lifetime is elided here
[INFO] [stdout]   |
[INFO] [stdout]   = help: the same lifetime is referred to in inconsistent ways, making the signature confusing
[INFO] [stdout] help: use `'_` for type paths
[INFO] [stdout]   |
[INFO] [stdout] 1 | # [doc = "Register `INT_EVENT0_IMASK` reader"] pub type R = crate :: R < INT_EVENT0_IMASK_SPEC > ; # [doc = "Register `INT_EVENT0_IMASK` writer"] pub type W = crate :: W < INT_EVENT0_IMASK_SPEC > ; # [doc = "Field `INT_EVENT0_IMASK_RTOUT` reader - Enable UARTOUT Receive Time-Out Interrupt."] pub type INT_EVENT0_IMASK_RTOUT_R = crate :: BitReader < INT_EVENT0_IMASK_RTOUT_A > ; # [doc = "Enable UARTOUT Receive Time-Out Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_RTOUT_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_RTOUT_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_RTOUT_SET = 1 , } impl From < INT_EVENT0_IMASK_RTOUT_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_RTOUT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_RTOUT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_RTOUT_A { match self . bits { false => INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_CLR , true => INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_rtout_clr (& self) -> bool { * self == INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_rtout_set (& self) -> bool { * self == INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_SET } } # [doc = "Field `INT_EVENT0_IMASK_RTOUT` writer - Enable UARTOUT Receive Time-Out Interrupt."] pub type INT_EVENT0_IMASK_RTOUT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_RTOUT_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_RTOUT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_rtout_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_rtout_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_SET) } } # [doc = "Field `INT_EVENT0_IMASK_FRMERR` reader - Enable UART Framing Error Interrupt."] pub type INT_EVENT0_IMASK_FRMERR_R = crate :: BitReader < INT_EVENT0_IMASK_FRMERR_A > ; # [doc = "Enable UART Framing Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_FRMERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_FRMERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_FRMERR_SET = 1 , } impl From < INT_EVENT0_IMASK_FRMERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_FRMERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_FRMERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_FRMERR_A { match self . bits { false => INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_CLR , true => INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_frmerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_frmerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_FRMERR` writer - Enable UART Framing Error Interrupt."] pub type INT_EVENT0_IMASK_FRMERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_FRMERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_FRMERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_frmerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_frmerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_SET) } } # [doc = "Field `INT_EVENT0_IMASK_PARERR` reader - Enable UART Parity Error Interrupt."] pub type INT_EVENT0_IMASK_PARERR_R = crate :: BitReader < INT_EVENT0_IMASK_PARERR_A > ; # [doc = "Enable UART Parity Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_PARERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_PARERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_PARERR_SET = 1 , } impl From < INT_EVENT0_IMASK_PARERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_PARERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_PARERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_PARERR_A { match self . bits { false => INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_CLR , true => INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_parerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_parerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_PARERR` writer - Enable UART Parity Error Interrupt."] pub type INT_EVENT0_IMASK_PARERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_PARERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_PARERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_parerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_parerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_SET) } } # [doc = "Field `INT_EVENT0_IMASK_BRKERR` reader - Enable UART Break Error Interrupt."] pub type INT_EVENT0_IMASK_BRKERR_R = crate :: BitReader < INT_EVENT0_IMASK_BRKERR_A > ; # [doc = "Enable UART Break Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_BRKERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_BRKERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_BRKERR_SET = 1 , } impl From < INT_EVENT0_IMASK_BRKERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_BRKERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_BRKERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_BRKERR_A { match self . bits { false => INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_CLR , true => INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_brkerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_brkerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_BRKERR` writer - Enable UART Break Error Interrupt."] pub type INT_EVENT0_IMASK_BRKERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_BRKERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_BRKERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_brkerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_brkerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_SET) } } # [doc = "Field `INT_EVENT0_IMASK_OVRERR` reader - Enable UART Receive Overrun Error Interrupt."] pub type INT_EVENT0_IMASK_OVRERR_R = crate :: BitReader < INT_EVENT0_IMASK_OVRERR_A > ; # [doc = "Enable UART Receive Overrun Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_OVRERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_OVRERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_OVRERR_SET = 1 , } impl From < INT_EVENT0_IMASK_OVRERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_OVRERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_OVRERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_OVRERR_A { match self . bits { false => INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_CLR , true => INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_ovrerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_ovrerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_OVRERR` writer - Enable UART Receive Overrun Error Interrupt."] pub type INT_EVENT0_IMASK_OVRERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_OVRERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_OVRERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_ovrerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_ovrerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_SET) } } # [doc = "Field `INT_EVENT0_IMASK_RXNE` reader - Enable Negative Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_IMASK_RXNE_R = crate :: BitReader < INT_EVENT0_IMASK_RXNE_A > ; # [doc = "Enable Negative Edge on UARTxRXD Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_RXNE_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_RXNE_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_RXNE_SET = 1 , } impl From < INT_EVENT0_IMASK_RXNE_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_RXNE_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_RXNE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_RXNE_A { match self . bits { false => INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_CLR , true => INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_rxne_clr (& self) -> bool { * self == INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_rxne_set (& self) -> bool { * self == INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_SET } } # [doc = "Field `INT_EVENT0_IMASK_RXNE` writer - Enable Negative Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_IMASK_RXNE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_RXNE_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_RXNE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_rxne_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_rxne_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_SET) } } # [doc = "Field `INT_EVENT0_IMASK_RXPE` reader - Enable Positive Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_IMASK_RXPE_R = crate :: BitReader < INT_EVENT0_IMASK_RXPE_A > ; # [doc = "Enable Positive Edge on UARTxRXD Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_RXPE_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_RXPE_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_RXPE_SET = 1 , } impl From < INT_EVENT0_IMASK_RXPE_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_RXPE_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_RXPE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_RXPE_A { match self . bits { false => INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_CLR , true => INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_rxpe_clr (& self) -> bool { * self == INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_rxpe_set (& self) -> bool { * self == INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_SET } } # [doc = "Field `INT_EVENT0_IMASK_RXPE` writer - Enable Positive Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_IMASK_RXPE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_RXPE_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_RXPE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_rxpe_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_rxpe_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_SET) } } # [doc = "Field `INT_EVENT0_IMASK_LINC0` reader - Enable LIN Capture 0 / Match Interrupt ."] pub type INT_EVENT0_IMASK_LINC0_R = crate :: BitReader < INT_EVENT0_IMASK_LINC0_A > ; # [doc = "Enable LIN Capture 0 / Match Interrupt .\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_LINC0_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_LINC0_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_LINC0_SET = 1 , } impl From < INT_EVENT0_IMASK_LINC0_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_LINC0_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_LINC0_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_LINC0_A { match self . bits { false => INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_CLR , true => INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_linc0_clr (& self) -> bool { * self == INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_linc0_set (& self) -> bool { * self == INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_SET } } # [doc = "Field `INT_EVENT0_IMASK_LINC0` writer - Enable LIN Capture 0 / Match Interrupt ."] pub type INT_EVENT0_IMASK_LINC0_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_LINC0_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_LINC0_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_linc0_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_linc0_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_SET) } } # [doc = "Field `INT_EVENT0_IMASK_LINC1` reader - Enable LIN Capture 1 Interrupt."] pub type INT_EVENT0_IMASK_LINC1_R = crate :: BitReader < INT_EVENT0_IMASK_LINC1_A > ; # [doc = "Enable LIN Capture 1 Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_LINC1_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_LINC1_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_LINC1_SET = 1 , } impl From < INT_EVENT0_IMASK_LINC1_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_LINC1_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_LINC1_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_LINC1_A { match self . bits { false => INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_CLR , true => INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_linc1_clr (& self) -> bool { * self == INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_linc1_set (& self) -> bool { * self == INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_SET } } # [doc = "Field `INT_EVENT0_IMASK_LINC1` writer - Enable LIN Capture 1 Interrupt."] pub type INT_EVENT0_IMASK_LINC1_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_LINC1_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_LINC1_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_linc1_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_linc1_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_SET) } } # [doc = "Field `INT_EVENT0_IMASK_LINOVF` reader - Enable LIN Hardware Counter Overflow Interrupt."] pub type INT_EVENT0_IMASK_LINOVF_R = crate :: BitReader < INT_EVENT0_IMASK_LINOVF_A > ; # [doc = "Enable LIN Hardware Counter Overflow Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_LINOVF_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_LINOVF_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_LINOVF_SET = 1 , } impl From < INT_EVENT0_IMASK_LINOVF_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_LINOVF_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_LINOVF_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_LINOVF_A { match self . bits { false => INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_CLR , true => INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_linovf_clr (& self) -> bool { * self == INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_linovf_set (& self) -> bool { * self == INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_SET } } # [doc = "Field `INT_EVENT0_IMASK_LINOVF` writer - Enable LIN Hardware Counter Overflow Interrupt."] pub type INT_EVENT0_IMASK_LINOVF_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_LINOVF_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_LINOVF_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_linovf_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_linovf_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_SET) } } # [doc = "Field `INT_EVENT0_IMASK_RXINT` reader - Enable UART Receive Interrupt."] pub type INT_EVENT0_IMASK_RXINT_R = crate :: BitReader < INT_EVENT0_IMASK_RXINT_A > ; # [doc = "Enable UART Receive Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_RXINT_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_RXINT_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_RXINT_SET = 1 , } impl From < INT_EVENT0_IMASK_RXINT_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_RXINT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_RXINT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_RXINT_A { match self . bits { false => INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_CLR , true => INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_rxint_clr (& self) -> bool { * self == INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_rxint_set (& self) -> bool { * self == INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_SET } } # [doc = "Field `INT_EVENT0_IMASK_RXINT` writer - Enable UART Receive Interrupt."] pub type INT_EVENT0_IMASK_RXINT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_RXINT_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_RXINT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_rxint_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_rxint_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_SET) } } # [doc = "Field `INT_EVENT0_IMASK_TXINT` reader - Enable UART Transmit Interrupt."] pub type INT_EVENT0_IMASK_TXINT_R = crate :: BitReader < INT_EVENT0_IMASK_TXINT_A > ; # [doc = "Enable UART Transmit Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_TXINT_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_TXINT_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_TXINT_SET = 1 , } impl From < INT_EVENT0_IMASK_TXINT_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_TXINT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_TXINT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_TXINT_A { match self . bits { false => INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_CLR , true => INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_txint_clr (& self) -> bool { * self == INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_txint_set (& self) -> bool { * self == INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_SET } } # [doc = "Field `INT_EVENT0_IMASK_TXINT` writer - Enable UART Transmit Interrupt."] pub type INT_EVENT0_IMASK_TXINT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_TXINT_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_TXINT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_txint_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_txint_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_SET) } } # [doc = "Field `INT_EVENT0_IMASK_EOT` reader - Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] pub type INT_EVENT0_IMASK_EOT_R = crate :: BitReader < INT_EVENT0_IMASK_EOT_A > ; # [doc = "Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_EOT_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_EOT_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_EOT_SET = 1 , } impl From < INT_EVENT0_IMASK_EOT_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_EOT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_EOT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_EOT_A { match self . bits { false => INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_CLR , true => INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_eot_clr (& self) -> bool { * self == INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_eot_set (& self) -> bool { * self == INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_SET } } # [doc = "Field `INT_EVENT0_IMASK_EOT` writer - Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] pub type INT_EVENT0_IMASK_EOT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_EOT_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_EOT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_eot_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_eot_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_SET) } } # [doc = "Field `INT_EVENT0_IMASK_ADDR_MATCH` reader - Enable Address Match Interrupt."] pub type INT_EVENT0_IMASK_ADDR_MATCH_R = crate :: BitReader < INT_EVENT0_IMASK_ADDR_MATCH_A > ; # [doc = "Enable Address Match Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_ADDR_MATCH_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_ADDR_MATCH_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_ADDR_MATCH_SET = 1 , } impl From < INT_EVENT0_IMASK_ADDR_MATCH_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_ADDR_MATCH_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_ADDR_MATCH_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_ADDR_MATCH_A { match self . bits { false => INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_CLR , true => INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_addr_match_clr (& self) -> bool { * self == INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_addr_match_set (& self) -> bool { * self == INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_SET } } # [doc = "Field `INT_EVENT0_IMASK_ADDR_MATCH` writer - Enable Address Match Interrupt."] pub type INT_EVENT0_IMASK_ADDR_MATCH_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_ADDR_MATCH_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_ADDR_MATCH_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_addr_match_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_addr_match_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_SET) } } # [doc = "Field `INT_EVENT0_IMASK_CTS` reader - Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] pub type INT_EVENT0_IMASK_CTS_R = crate :: BitReader < INT_EVENT0_IMASK_CTS_A > ; # [doc = "Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_CTS_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_CTS_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_CTS_SET = 1 , } impl From < INT_EVENT0_IMASK_CTS_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_CTS_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_CTS_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_CTS_A { match self . bits { false => INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_CLR , true => INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_cts_clr (& self) -> bool { * self == INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_cts_set (& self) -> bool { * self == INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_SET } } # [doc = "Field `INT_EVENT0_IMASK_CTS` writer - Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] pub type INT_EVENT0_IMASK_CTS_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_CTS_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_CTS_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_cts_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_cts_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DMA_DONE_RX` reader - Enable DMA Done on RX Event Channel"] pub type INT_EVENT0_IMASK_DMA_DONE_RX_R = crate :: BitReader < INT_EVENT0_IMASK_DMA_DONE_RX_A > ; # [doc = "Enable DMA Done on RX Event Channel\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DMA_DONE_RX_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DMA_DONE_RX_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DMA_DONE_RX_SET = 1 , } impl From < INT_EVENT0_IMASK_DMA_DONE_RX_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DMA_DONE_RX_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DMA_DONE_RX_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DMA_DONE_RX_A { match self . bits { false => INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_CLR , true => INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dma_done_rx_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dma_done_rx_set (& self) -> bool { * self == INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_SET } } # [doc = "Field `INT_EVENT0_IMASK_DMA_DONE_RX` writer - Enable DMA Done on RX Event Channel"] pub type INT_EVENT0_IMASK_DMA_DONE_RX_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DMA_DONE_RX_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DMA_DONE_RX_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dma_done_rx_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dma_done_rx_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DMA_DONE_TX` reader - Enable DMA Done on TX Event Channel"] pub type INT_EVENT0_IMASK_DMA_DONE_TX_R = crate :: BitReader < INT_EVENT0_IMASK_DMA_DONE_TX_A > ; # [doc = "Enable DMA Done on TX Event Channel\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DMA_DONE_TX_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DMA_DONE_TX_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DMA_DONE_TX_SET = 1 , } impl From < INT_EVENT0_IMASK_DMA_DONE_TX_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DMA_DONE_TX_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DMA_DONE_TX_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DMA_DONE_TX_A { match self . bits { false => INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_CLR , true => INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dma_done_tx_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dma_done_tx_set (& self) -> bool { * self == INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_SET } } # [doc = "Field `INT_EVENT0_IMASK_DMA_DONE_TX` writer - Enable DMA Done on TX Event Channel"] pub type INT_EVENT0_IMASK_DMA_DONE_TX_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DMA_DONE_TX_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DMA_DONE_TX_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dma_done_tx_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dma_done_tx_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_SET) } } # [doc = "Field `INT_EVENT0_IMASK_NERR` reader - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] pub type INT_EVENT0_IMASK_NERR_R = crate :: BitReader < INT_EVENT0_IMASK_NERR_A > ; # [doc = "Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_NERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_NERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_NERR_SET = 1 , } impl From < INT_EVENT0_IMASK_NERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_NERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_NERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_NERR_A { match self . bits { false => INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_CLR , true => INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_nerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_nerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_NERR` writer - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] pub type INT_EVENT0_IMASK_NERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_NERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_NERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_nerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_nerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_SET) } } impl R { # [doc = "Bit 0 - Enable UARTOUT Receive Time-Out Interrupt."] # [inline (always)] pub fn int_event0_imask_rtout (& self) -> INT_EVENT0_IMASK_RTOUT_R { INT_EVENT0_IMASK_RTOUT_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - Enable UART Framing Error Interrupt."] # [inline (always)] pub fn int_event0_imask_frmerr (& self) -> INT_EVENT0_IMASK_FRMERR_R { INT_EVENT0_IMASK_FRMERR_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - Enable UART Parity Error Interrupt."] # [inline (always)] pub fn int_event0_imask_parerr (& self) -> INT_EVENT0_IMASK_PARERR_R { INT_EVENT0_IMASK_PARERR_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - Enable UART Break Error Interrupt."] # [inline (always)] pub fn int_event0_imask_brkerr (& self) -> INT_EVENT0_IMASK_BRKERR_R { INT_EVENT0_IMASK_BRKERR_R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - Enable UART Receive Overrun Error Interrupt."] # [inline (always)] pub fn int_event0_imask_ovrerr (& self) -> INT_EVENT0_IMASK_OVRERR_R { INT_EVENT0_IMASK_OVRERR_R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - Enable Negative Edge on UARTxRXD Interrupt."] # [inline (always)] pub fn int_event0_imask_rxne (& self) -> INT_EVENT0_IMASK_RXNE_R { INT_EVENT0_IMASK_RXNE_R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - Enable Positive Edge on UARTxRXD Interrupt."] # [inline (always)] pub fn int_event0_imask_rxpe (& self) -> INT_EVENT0_IMASK_RXPE_R { INT_EVENT0_IMASK_RXPE_R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - Enable LIN Capture 0 / Match Interrupt ."] # [inline (always)] pub fn int_event0_imask_linc0 (& self) -> INT_EVENT0_IMASK_LINC0_R { INT_EVENT0_IMASK_LINC0_R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - Enable LIN Capture 1 Interrupt."] # [inline (always)] pub fn int_event0_imask_linc1 (& self) -> INT_EVENT0_IMASK_LINC1_R { INT_EVENT0_IMASK_LINC1_R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - Enable LIN Hardware Counter Overflow Interrupt."] # [inline (always)] pub fn int_event0_imask_linovf (& self) -> INT_EVENT0_IMASK_LINOVF_R { INT_EVENT0_IMASK_LINOVF_R :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - Enable UART Receive Interrupt."] # [inline (always)] pub fn int_event0_imask_rxint (& self) -> INT_EVENT0_IMASK_RXINT_R { INT_EVENT0_IMASK_RXINT_R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - Enable UART Transmit Interrupt."] # [inline (always)] pub fn int_event0_imask_txint (& self) -> INT_EVENT0_IMASK_TXINT_R { INT_EVENT0_IMASK_TXINT_R :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] # [inline (always)] pub fn int_event0_imask_eot (& self) -> INT_EVENT0_IMASK_EOT_R { INT_EVENT0_IMASK_EOT_R :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - Enable Address Match Interrupt."] # [inline (always)] pub fn int_event0_imask_addr_match (& self) -> INT_EVENT0_IMASK_ADDR_MATCH_R { INT_EVENT0_IMASK_ADDR_MATCH_R :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 14 - Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] # [inline (always)] pub fn int_event0_imask_cts (& self) -> INT_EVENT0_IMASK_CTS_R { INT_EVENT0_IMASK_CTS_R :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - Enable DMA Done on RX Event Channel"] # [inline (always)] pub fn int_event0_imask_dma_done_rx (& self) -> INT_EVENT0_IMASK_DMA_DONE_RX_R { INT_EVENT0_IMASK_DMA_DONE_RX_R :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bit 16 - Enable DMA Done on TX Event Channel"] # [inline (always)] pub fn int_event0_imask_dma_done_tx (& self) -> INT_EVENT0_IMASK_DMA_DONE_TX_R { INT_EVENT0_IMASK_DMA_DONE_TX_R :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] # [inline (always)] pub fn int_event0_imask_nerr (& self) -> INT_EVENT0_IMASK_NERR_R { INT_EVENT0_IMASK_NERR_R :: new (((self . bits >> 17) & 1) != 0) } } impl W { # [doc = "Bit 0 - Enable UARTOUT Receive Time-Out Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_rtout (& mut self) -> INT_EVENT0_IMASK_RTOUT_W < INT_EVENT0_IMASK_SPEC , 0 > { INT_EVENT0_IMASK_RTOUT_W :: new (self) } # [doc = "Bit 1 - Enable UART Framing Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_frmerr (& mut self) -> INT_EVENT0_IMASK_FRMERR_W < INT_EVENT0_IMASK_SPEC , 1 > { INT_EVENT0_IMASK_FRMERR_W :: new (self) } # [doc = "Bit 2 - Enable UART Parity Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_parerr (& mut self) -> INT_EVENT0_IMASK_PARERR_W < INT_EVENT0_IMASK_SPEC , 2 > { INT_EVENT0_IMASK_PARERR_W :: new (self) } # [doc = "Bit 3 - Enable UART Break Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_brkerr (& mut self) -> INT_EVENT0_IMASK_BRKERR_W < INT_EVENT0_IMASK_SPEC , 3 > { INT_EVENT0_IMASK_BRKERR_W :: new (self) } # [doc = "Bit 4 - Enable UART Receive Overrun Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_ovrerr (& mut self) -> INT_EVENT0_IMASK_OVRERR_W < INT_EVENT0_IMASK_SPEC , 4 > { INT_EVENT0_IMASK_OVRERR_W :: new (self) } # [doc = "Bit 5 - Enable Negative Edge on UARTxRXD Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_rxne (& mut self) -> INT_EVENT0_IMASK_RXNE_W < INT_EVENT0_IMASK_SPEC , 5 > { INT_EVENT0_IMASK_RXNE_W :: new (self) } # [doc = "Bit 6 - Enable Positive Edge on UARTxRXD Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_rxpe (& mut self) -> INT_EVENT0_IMASK_RXPE_W < INT_EVENT0_IMASK_SPEC , 6 > { INT_EVENT0_IMASK_RXPE_W :: new (self) } # [doc = "Bit 7 - Enable LIN Capture 0 / Match Interrupt ."] # [inline (always)] # [must_use] pub fn int_event0_imask_linc0 (& mut self) -> INT_EVENT0_IMASK_LINC0_W <'_,  INT_EVENT0_IMASK_SPEC , 7 > { INT_EVENT0_IMASK_LINC0_W :: new (self) } # [doc = "Bit 8 - Enable LIN Capture 1 Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_linc1 (& mut self) -> INT_EVENT0_IMASK_LINC1_W < INT_EVENT0_IMASK_SPEC , 8 > { INT_EVENT0_IMASK_LINC1_W :: new (self) } # [doc = "Bit 9 - Enable LIN Hardware Counter Overflow Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_linovf (& mut self) -> INT_EVENT0_IMASK_LINOVF_W < INT_EVENT0_IMASK_SPEC , 9 > { INT_EVENT0_IMASK_LINOVF_W :: new (self) } # [doc = "Bit 10 - Enable UART Receive Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_rxint (& mut self) -> INT_EVENT0_IMASK_RXINT_W < INT_EVENT0_IMASK_SPEC , 10 > { INT_EVENT0_IMASK_RXINT_W :: new (self) } # [doc = "Bit 11 - Enable UART Transmit Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_txint (& mut self) -> INT_EVENT0_IMASK_TXINT_W < INT_EVENT0_IMASK_SPEC , 11 > { INT_EVENT0_IMASK_TXINT_W :: new (self) } # [doc = "Bit 12 - Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] # [inline (always)] # [must_use] pub fn int_event0_imask_eot (& mut self) -> INT_EVENT0_IMASK_EOT_W < INT_EVENT0_IMASK_SPEC , 12 > { INT_EVENT0_IMASK_EOT_W :: new (self) } # [doc = "Bit 13 - Enable Address Match Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_addr_match (& mut self) -> INT_EVENT0_IMASK_ADDR_MATCH_W < INT_EVENT0_IMASK_SPEC , 13 > { INT_EVENT0_IMASK_ADDR_MATCH_W :: new (self) } # [doc = "Bit 14 - Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] # [inline (always)] # [must_use] pub fn int_event0_imask_cts (& mut self) -> INT_EVENT0_IMASK_CTS_W < INT_EVENT0_IMASK_SPEC , 14 > { INT_EVENT0_IMASK_CTS_W :: new (self) } # [doc = "Bit 15 - Enable DMA Done on RX Event Channel"] # [inline (always)] # [must_use] pub fn int_event0_imask_dma_done_rx (& mut self) -> INT_EVENT0_IMASK_DMA_DONE_RX_W < INT_EVENT0_IMASK_SPEC , 15 > { INT_EVENT0_IMASK_DMA_DONE_RX_W :: new (self) } # [doc = "Bit 16 - Enable DMA Done on TX Event Channel"] # [inline (always)] # [must_use] pub fn int_event0_imask_dma_done_tx (& mut self) -> INT_EVENT0_IMASK_DMA_DONE_TX_W < INT_EVENT0_IMASK_SPEC , 16 > { INT_EVENT0_IMASK_DMA_DONE_TX_W :: new (self) } # [doc = "Bit 17 - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] # [inline (always)] # [must_use] pub fn int_event0_imask_nerr (& mut self) -> INT_EVENT0_IMASK_NERR_W < INT_EVENT0_IMASK_SPEC , 17 > { INT_EVENT0_IMASK_NERR_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Interrupt mask\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_event0_imask::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_event0_imask::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct INT_EVENT0_IMASK_SPEC ; impl crate :: RegisterSpec for INT_EVENT0_IMASK_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`int_event0_imask::R`](R) reader structure"] impl crate :: Readable for INT_EVENT0_IMASK_SPEC { } # [doc = "`write(|w| ..)` method takes [`int_event0_imask::W`](W) writer structure"] impl crate :: Writable for INT_EVENT0_IMASK_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets INT_EVENT0_IMASK to value 0"] impl crate :: Resettable for INT_EVENT0_IMASK_SPEC { const RESET_VALUE : Self :: Ux = 0 ; }
[INFO] [stdout]   |                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                              +++
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing
[INFO] [stdout]  --> src/uart0/int_event0_imask.rs:1:42394
[INFO] [stdout]   |
[INFO] [stdout] 1 | ..._imask_linc1 (& mut self) -> INT_EVENT0_IMASK_LINC1_W < INT_EVENT0_IMASK_SPEC , 8 > { INT_EVENT0_IMASK_LINC1_W :: new (self) } # [...
[INFO] [stdout]   |                  ^^^^^^^^^^     ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here
[INFO] [stdout]   |                  |
[INFO] [stdout]   |                  the lifetime is elided here
[INFO] [stdout]   |
[INFO] [stdout]   = help: the same lifetime is referred to in inconsistent ways, making the signature confusing
[INFO] [stdout] help: use `'_` for type paths
[INFO] [stdout]   |
[INFO] [stdout] 1 | # [doc = "Register `INT_EVENT0_IMASK` reader"] pub type R = crate :: R < INT_EVENT0_IMASK_SPEC > ; # [doc = "Register `INT_EVENT0_IMASK` writer"] pub type W = crate :: W < INT_EVENT0_IMASK_SPEC > ; # [doc = "Field `INT_EVENT0_IMASK_RTOUT` reader - Enable UARTOUT Receive Time-Out Interrupt."] pub type INT_EVENT0_IMASK_RTOUT_R = crate :: BitReader < INT_EVENT0_IMASK_RTOUT_A > ; # [doc = "Enable UARTOUT Receive Time-Out Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_RTOUT_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_RTOUT_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_RTOUT_SET = 1 , } impl From < INT_EVENT0_IMASK_RTOUT_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_RTOUT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_RTOUT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_RTOUT_A { match self . bits { false => INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_CLR , true => INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_rtout_clr (& self) -> bool { * self == INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_rtout_set (& self) -> bool { * self == INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_SET } } # [doc = "Field `INT_EVENT0_IMASK_RTOUT` writer - Enable UARTOUT Receive Time-Out Interrupt."] pub type INT_EVENT0_IMASK_RTOUT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_RTOUT_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_RTOUT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_rtout_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_rtout_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_SET) } } # [doc = "Field `INT_EVENT0_IMASK_FRMERR` reader - Enable UART Framing Error Interrupt."] pub type INT_EVENT0_IMASK_FRMERR_R = crate :: BitReader < INT_EVENT0_IMASK_FRMERR_A > ; # [doc = "Enable UART Framing Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_FRMERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_FRMERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_FRMERR_SET = 1 , } impl From < INT_EVENT0_IMASK_FRMERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_FRMERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_FRMERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_FRMERR_A { match self . bits { false => INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_CLR , true => INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_frmerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_frmerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_FRMERR` writer - Enable UART Framing Error Interrupt."] pub type INT_EVENT0_IMASK_FRMERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_FRMERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_FRMERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_frmerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_frmerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_SET) } } # [doc = "Field `INT_EVENT0_IMASK_PARERR` reader - Enable UART Parity Error Interrupt."] pub type INT_EVENT0_IMASK_PARERR_R = crate :: BitReader < INT_EVENT0_IMASK_PARERR_A > ; # [doc = "Enable UART Parity Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_PARERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_PARERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_PARERR_SET = 1 , } impl From < INT_EVENT0_IMASK_PARERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_PARERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_PARERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_PARERR_A { match self . bits { false => INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_CLR , true => INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_parerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_parerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_PARERR` writer - Enable UART Parity Error Interrupt."] pub type INT_EVENT0_IMASK_PARERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_PARERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_PARERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_parerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_parerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_SET) } } # [doc = "Field `INT_EVENT0_IMASK_BRKERR` reader - Enable UART Break Error Interrupt."] pub type INT_EVENT0_IMASK_BRKERR_R = crate :: BitReader < INT_EVENT0_IMASK_BRKERR_A > ; # [doc = "Enable UART Break Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_BRKERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_BRKERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_BRKERR_SET = 1 , } impl From < INT_EVENT0_IMASK_BRKERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_BRKERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_BRKERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_BRKERR_A { match self . bits { false => INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_CLR , true => INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_brkerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_brkerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_BRKERR` writer - Enable UART Break Error Interrupt."] pub type INT_EVENT0_IMASK_BRKERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_BRKERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_BRKERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_brkerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_brkerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_SET) } } # [doc = "Field `INT_EVENT0_IMASK_OVRERR` reader - Enable UART Receive Overrun Error Interrupt."] pub type INT_EVENT0_IMASK_OVRERR_R = crate :: BitReader < INT_EVENT0_IMASK_OVRERR_A > ; # [doc = "Enable UART Receive Overrun Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_OVRERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_OVRERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_OVRERR_SET = 1 , } impl From < INT_EVENT0_IMASK_OVRERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_OVRERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_OVRERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_OVRERR_A { match self . bits { false => INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_CLR , true => INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_ovrerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_ovrerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_OVRERR` writer - Enable UART Receive Overrun Error Interrupt."] pub type INT_EVENT0_IMASK_OVRERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_OVRERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_OVRERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_ovrerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_ovrerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_SET) } } # [doc = "Field `INT_EVENT0_IMASK_RXNE` reader - Enable Negative Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_IMASK_RXNE_R = crate :: BitReader < INT_EVENT0_IMASK_RXNE_A > ; # [doc = "Enable Negative Edge on UARTxRXD Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_RXNE_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_RXNE_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_RXNE_SET = 1 , } impl From < INT_EVENT0_IMASK_RXNE_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_RXNE_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_RXNE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_RXNE_A { match self . bits { false => INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_CLR , true => INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_rxne_clr (& self) -> bool { * self == INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_rxne_set (& self) -> bool { * self == INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_SET } } # [doc = "Field `INT_EVENT0_IMASK_RXNE` writer - Enable Negative Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_IMASK_RXNE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_RXNE_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_RXNE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_rxne_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_rxne_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_SET) } } # [doc = "Field `INT_EVENT0_IMASK_RXPE` reader - Enable Positive Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_IMASK_RXPE_R = crate :: BitReader < INT_EVENT0_IMASK_RXPE_A > ; # [doc = "Enable Positive Edge on UARTxRXD Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_RXPE_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_RXPE_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_RXPE_SET = 1 , } impl From < INT_EVENT0_IMASK_RXPE_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_RXPE_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_RXPE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_RXPE_A { match self . bits { false => INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_CLR , true => INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_rxpe_clr (& self) -> bool { * self == INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_rxpe_set (& self) -> bool { * self == INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_SET } } # [doc = "Field `INT_EVENT0_IMASK_RXPE` writer - Enable Positive Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_IMASK_RXPE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_RXPE_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_RXPE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_rxpe_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_rxpe_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_SET) } } # [doc = "Field `INT_EVENT0_IMASK_LINC0` reader - Enable LIN Capture 0 / Match Interrupt ."] pub type INT_EVENT0_IMASK_LINC0_R = crate :: BitReader < INT_EVENT0_IMASK_LINC0_A > ; # [doc = "Enable LIN Capture 0 / Match Interrupt .\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_LINC0_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_LINC0_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_LINC0_SET = 1 , } impl From < INT_EVENT0_IMASK_LINC0_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_LINC0_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_LINC0_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_LINC0_A { match self . bits { false => INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_CLR , true => INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_linc0_clr (& self) -> bool { * self == INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_linc0_set (& self) -> bool { * self == INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_SET } } # [doc = "Field `INT_EVENT0_IMASK_LINC0` writer - Enable LIN Capture 0 / Match Interrupt ."] pub type INT_EVENT0_IMASK_LINC0_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_LINC0_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_LINC0_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_linc0_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_linc0_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_SET) } } # [doc = "Field `INT_EVENT0_IMASK_LINC1` reader - Enable LIN Capture 1 Interrupt."] pub type INT_EVENT0_IMASK_LINC1_R = crate :: BitReader < INT_EVENT0_IMASK_LINC1_A > ; # [doc = "Enable LIN Capture 1 Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_LINC1_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_LINC1_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_LINC1_SET = 1 , } impl From < INT_EVENT0_IMASK_LINC1_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_LINC1_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_LINC1_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_LINC1_A { match self . bits { false => INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_CLR , true => INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_linc1_clr (& self) -> bool { * self == INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_linc1_set (& self) -> bool { * self == INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_SET } } # [doc = "Field `INT_EVENT0_IMASK_LINC1` writer - Enable LIN Capture 1 Interrupt."] pub type INT_EVENT0_IMASK_LINC1_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_LINC1_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_LINC1_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_linc1_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_linc1_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_SET) } } # [doc = "Field `INT_EVENT0_IMASK_LINOVF` reader - Enable LIN Hardware Counter Overflow Interrupt."] pub type INT_EVENT0_IMASK_LINOVF_R = crate :: BitReader < INT_EVENT0_IMASK_LINOVF_A > ; # [doc = "Enable LIN Hardware Counter Overflow Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_LINOVF_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_LINOVF_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_LINOVF_SET = 1 , } impl From < INT_EVENT0_IMASK_LINOVF_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_LINOVF_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_LINOVF_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_LINOVF_A { match self . bits { false => INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_CLR , true => INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_linovf_clr (& self) -> bool { * self == INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_linovf_set (& self) -> bool { * self == INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_SET } } # [doc = "Field `INT_EVENT0_IMASK_LINOVF` writer - Enable LIN Hardware Counter Overflow Interrupt."] pub type INT_EVENT0_IMASK_LINOVF_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_LINOVF_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_LINOVF_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_linovf_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_linovf_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_SET) } } # [doc = "Field `INT_EVENT0_IMASK_RXINT` reader - Enable UART Receive Interrupt."] pub type INT_EVENT0_IMASK_RXINT_R = crate :: BitReader < INT_EVENT0_IMASK_RXINT_A > ; # [doc = "Enable UART Receive Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_RXINT_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_RXINT_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_RXINT_SET = 1 , } impl From < INT_EVENT0_IMASK_RXINT_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_RXINT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_RXINT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_RXINT_A { match self . bits { false => INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_CLR , true => INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_rxint_clr (& self) -> bool { * self == INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_rxint_set (& self) -> bool { * self == INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_SET } } # [doc = "Field `INT_EVENT0_IMASK_RXINT` writer - Enable UART Receive Interrupt."] pub type INT_EVENT0_IMASK_RXINT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_RXINT_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_RXINT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_rxint_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_rxint_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_SET) } } # [doc = "Field `INT_EVENT0_IMASK_TXINT` reader - Enable UART Transmit Interrupt."] pub type INT_EVENT0_IMASK_TXINT_R = crate :: BitReader < INT_EVENT0_IMASK_TXINT_A > ; # [doc = "Enable UART Transmit Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_TXINT_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_TXINT_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_TXINT_SET = 1 , } impl From < INT_EVENT0_IMASK_TXINT_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_TXINT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_TXINT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_TXINT_A { match self . bits { false => INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_CLR , true => INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_txint_clr (& self) -> bool { * self == INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_txint_set (& self) -> bool { * self == INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_SET } } # [doc = "Field `INT_EVENT0_IMASK_TXINT` writer - Enable UART Transmit Interrupt."] pub type INT_EVENT0_IMASK_TXINT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_TXINT_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_TXINT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_txint_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_txint_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_SET) } } # [doc = "Field `INT_EVENT0_IMASK_EOT` reader - Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] pub type INT_EVENT0_IMASK_EOT_R = crate :: BitReader < INT_EVENT0_IMASK_EOT_A > ; # [doc = "Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_EOT_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_EOT_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_EOT_SET = 1 , } impl From < INT_EVENT0_IMASK_EOT_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_EOT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_EOT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_EOT_A { match self . bits { false => INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_CLR , true => INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_eot_clr (& self) -> bool { * self == INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_eot_set (& self) -> bool { * self == INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_SET } } # [doc = "Field `INT_EVENT0_IMASK_EOT` writer - Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] pub type INT_EVENT0_IMASK_EOT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_EOT_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_EOT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_eot_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_eot_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_SET) } } # [doc = "Field `INT_EVENT0_IMASK_ADDR_MATCH` reader - Enable Address Match Interrupt."] pub type INT_EVENT0_IMASK_ADDR_MATCH_R = crate :: BitReader < INT_EVENT0_IMASK_ADDR_MATCH_A > ; # [doc = "Enable Address Match Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_ADDR_MATCH_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_ADDR_MATCH_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_ADDR_MATCH_SET = 1 , } impl From < INT_EVENT0_IMASK_ADDR_MATCH_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_ADDR_MATCH_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_ADDR_MATCH_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_ADDR_MATCH_A { match self . bits { false => INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_CLR , true => INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_addr_match_clr (& self) -> bool { * self == INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_addr_match_set (& self) -> bool { * self == INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_SET } } # [doc = "Field `INT_EVENT0_IMASK_ADDR_MATCH` writer - Enable Address Match Interrupt."] pub type INT_EVENT0_IMASK_ADDR_MATCH_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_ADDR_MATCH_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_ADDR_MATCH_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_addr_match_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_addr_match_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_SET) } } # [doc = "Field `INT_EVENT0_IMASK_CTS` reader - Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] pub type INT_EVENT0_IMASK_CTS_R = crate :: BitReader < INT_EVENT0_IMASK_CTS_A > ; # [doc = "Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_CTS_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_CTS_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_CTS_SET = 1 , } impl From < INT_EVENT0_IMASK_CTS_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_CTS_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_CTS_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_CTS_A { match self . bits { false => INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_CLR , true => INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_cts_clr (& self) -> bool { * self == INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_cts_set (& self) -> bool { * self == INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_SET } } # [doc = "Field `INT_EVENT0_IMASK_CTS` writer - Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] pub type INT_EVENT0_IMASK_CTS_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_CTS_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_CTS_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_cts_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_cts_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DMA_DONE_RX` reader - Enable DMA Done on RX Event Channel"] pub type INT_EVENT0_IMASK_DMA_DONE_RX_R = crate :: BitReader < INT_EVENT0_IMASK_DMA_DONE_RX_A > ; # [doc = "Enable DMA Done on RX Event Channel\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DMA_DONE_RX_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DMA_DONE_RX_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DMA_DONE_RX_SET = 1 , } impl From < INT_EVENT0_IMASK_DMA_DONE_RX_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DMA_DONE_RX_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DMA_DONE_RX_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DMA_DONE_RX_A { match self . bits { false => INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_CLR , true => INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dma_done_rx_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dma_done_rx_set (& self) -> bool { * self == INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_SET } } # [doc = "Field `INT_EVENT0_IMASK_DMA_DONE_RX` writer - Enable DMA Done on RX Event Channel"] pub type INT_EVENT0_IMASK_DMA_DONE_RX_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DMA_DONE_RX_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DMA_DONE_RX_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dma_done_rx_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dma_done_rx_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DMA_DONE_TX` reader - Enable DMA Done on TX Event Channel"] pub type INT_EVENT0_IMASK_DMA_DONE_TX_R = crate :: BitReader < INT_EVENT0_IMASK_DMA_DONE_TX_A > ; # [doc = "Enable DMA Done on TX Event Channel\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DMA_DONE_TX_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DMA_DONE_TX_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DMA_DONE_TX_SET = 1 , } impl From < INT_EVENT0_IMASK_DMA_DONE_TX_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DMA_DONE_TX_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DMA_DONE_TX_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DMA_DONE_TX_A { match self . bits { false => INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_CLR , true => INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dma_done_tx_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dma_done_tx_set (& self) -> bool { * self == INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_SET } } # [doc = "Field `INT_EVENT0_IMASK_DMA_DONE_TX` writer - Enable DMA Done on TX Event Channel"] pub type INT_EVENT0_IMASK_DMA_DONE_TX_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DMA_DONE_TX_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DMA_DONE_TX_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dma_done_tx_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dma_done_tx_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_SET) } } # [doc = "Field `INT_EVENT0_IMASK_NERR` reader - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] pub type INT_EVENT0_IMASK_NERR_R = crate :: BitReader < INT_EVENT0_IMASK_NERR_A > ; # [doc = "Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_NERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_NERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_NERR_SET = 1 , } impl From < INT_EVENT0_IMASK_NERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_NERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_NERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_NERR_A { match self . bits { false => INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_CLR , true => INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_nerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_nerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_NERR` writer - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] pub type INT_EVENT0_IMASK_NERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_NERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_NERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_nerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_nerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_SET) } } impl R { # [doc = "Bit 0 - Enable UARTOUT Receive Time-Out Interrupt."] # [inline (always)] pub fn int_event0_imask_rtout (& self) -> INT_EVENT0_IMASK_RTOUT_R { INT_EVENT0_IMASK_RTOUT_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - Enable UART Framing Error Interrupt."] # [inline (always)] pub fn int_event0_imask_frmerr (& self) -> INT_EVENT0_IMASK_FRMERR_R { INT_EVENT0_IMASK_FRMERR_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - Enable UART Parity Error Interrupt."] # [inline (always)] pub fn int_event0_imask_parerr (& self) -> INT_EVENT0_IMASK_PARERR_R { INT_EVENT0_IMASK_PARERR_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - Enable UART Break Error Interrupt."] # [inline (always)] pub fn int_event0_imask_brkerr (& self) -> INT_EVENT0_IMASK_BRKERR_R { INT_EVENT0_IMASK_BRKERR_R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - Enable UART Receive Overrun Error Interrupt."] # [inline (always)] pub fn int_event0_imask_ovrerr (& self) -> INT_EVENT0_IMASK_OVRERR_R { INT_EVENT0_IMASK_OVRERR_R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - Enable Negative Edge on UARTxRXD Interrupt."] # [inline (always)] pub fn int_event0_imask_rxne (& self) -> INT_EVENT0_IMASK_RXNE_R { INT_EVENT0_IMASK_RXNE_R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - Enable Positive Edge on UARTxRXD Interrupt."] # [inline (always)] pub fn int_event0_imask_rxpe (& self) -> INT_EVENT0_IMASK_RXPE_R { INT_EVENT0_IMASK_RXPE_R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - Enable LIN Capture 0 / Match Interrupt ."] # [inline (always)] pub fn int_event0_imask_linc0 (& self) -> INT_EVENT0_IMASK_LINC0_R { INT_EVENT0_IMASK_LINC0_R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - Enable LIN Capture 1 Interrupt."] # [inline (always)] pub fn int_event0_imask_linc1 (& self) -> INT_EVENT0_IMASK_LINC1_R { INT_EVENT0_IMASK_LINC1_R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - Enable LIN Hardware Counter Overflow Interrupt."] # [inline (always)] pub fn int_event0_imask_linovf (& self) -> INT_EVENT0_IMASK_LINOVF_R { INT_EVENT0_IMASK_LINOVF_R :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - Enable UART Receive Interrupt."] # [inline (always)] pub fn int_event0_imask_rxint (& self) -> INT_EVENT0_IMASK_RXINT_R { INT_EVENT0_IMASK_RXINT_R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - Enable UART Transmit Interrupt."] # [inline (always)] pub fn int_event0_imask_txint (& self) -> INT_EVENT0_IMASK_TXINT_R { INT_EVENT0_IMASK_TXINT_R :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] # [inline (always)] pub fn int_event0_imask_eot (& self) -> INT_EVENT0_IMASK_EOT_R { INT_EVENT0_IMASK_EOT_R :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - Enable Address Match Interrupt."] # [inline (always)] pub fn int_event0_imask_addr_match (& self) -> INT_EVENT0_IMASK_ADDR_MATCH_R { INT_EVENT0_IMASK_ADDR_MATCH_R :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 14 - Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] # [inline (always)] pub fn int_event0_imask_cts (& self) -> INT_EVENT0_IMASK_CTS_R { INT_EVENT0_IMASK_CTS_R :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - Enable DMA Done on RX Event Channel"] # [inline (always)] pub fn int_event0_imask_dma_done_rx (& self) -> INT_EVENT0_IMASK_DMA_DONE_RX_R { INT_EVENT0_IMASK_DMA_DONE_RX_R :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bit 16 - Enable DMA Done on TX Event Channel"] # [inline (always)] pub fn int_event0_imask_dma_done_tx (& self) -> INT_EVENT0_IMASK_DMA_DONE_TX_R { INT_EVENT0_IMASK_DMA_DONE_TX_R :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] # [inline (always)] pub fn int_event0_imask_nerr (& self) -> INT_EVENT0_IMASK_NERR_R { INT_EVENT0_IMASK_NERR_R :: new (((self . bits >> 17) & 1) != 0) } } impl W { # [doc = "Bit 0 - Enable UARTOUT Receive Time-Out Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_rtout (& mut self) -> INT_EVENT0_IMASK_RTOUT_W < INT_EVENT0_IMASK_SPEC , 0 > { INT_EVENT0_IMASK_RTOUT_W :: new (self) } # [doc = "Bit 1 - Enable UART Framing Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_frmerr (& mut self) -> INT_EVENT0_IMASK_FRMERR_W < INT_EVENT0_IMASK_SPEC , 1 > { INT_EVENT0_IMASK_FRMERR_W :: new (self) } # [doc = "Bit 2 - Enable UART Parity Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_parerr (& mut self) -> INT_EVENT0_IMASK_PARERR_W < INT_EVENT0_IMASK_SPEC , 2 > { INT_EVENT0_IMASK_PARERR_W :: new (self) } # [doc = "Bit 3 - Enable UART Break Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_brkerr (& mut self) -> INT_EVENT0_IMASK_BRKERR_W < INT_EVENT0_IMASK_SPEC , 3 > { INT_EVENT0_IMASK_BRKERR_W :: new (self) } # [doc = "Bit 4 - Enable UART Receive Overrun Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_ovrerr (& mut self) -> INT_EVENT0_IMASK_OVRERR_W < INT_EVENT0_IMASK_SPEC , 4 > { INT_EVENT0_IMASK_OVRERR_W :: new (self) } # [doc = "Bit 5 - Enable Negative Edge on UARTxRXD Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_rxne (& mut self) -> INT_EVENT0_IMASK_RXNE_W < INT_EVENT0_IMASK_SPEC , 5 > { INT_EVENT0_IMASK_RXNE_W :: new (self) } # [doc = "Bit 6 - Enable Positive Edge on UARTxRXD Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_rxpe (& mut self) -> INT_EVENT0_IMASK_RXPE_W < INT_EVENT0_IMASK_SPEC , 6 > { INT_EVENT0_IMASK_RXPE_W :: new (self) } # [doc = "Bit 7 - Enable LIN Capture 0 / Match Interrupt ."] # [inline (always)] # [must_use] pub fn int_event0_imask_linc0 (& mut self) -> INT_EVENT0_IMASK_LINC0_W < INT_EVENT0_IMASK_SPEC , 7 > { INT_EVENT0_IMASK_LINC0_W :: new (self) } # [doc = "Bit 8 - Enable LIN Capture 1 Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_linc1 (& mut self) -> INT_EVENT0_IMASK_LINC1_W <'_,  INT_EVENT0_IMASK_SPEC , 8 > { INT_EVENT0_IMASK_LINC1_W :: new (self) } # [doc = "Bit 9 - Enable LIN Hardware Counter Overflow Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_linovf (& mut self) -> INT_EVENT0_IMASK_LINOVF_W < INT_EVENT0_IMASK_SPEC , 9 > { INT_EVENT0_IMASK_LINOVF_W :: new (self) } # [doc = "Bit 10 - Enable UART Receive Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_rxint (& mut self) -> INT_EVENT0_IMASK_RXINT_W < INT_EVENT0_IMASK_SPEC , 10 > { INT_EVENT0_IMASK_RXINT_W :: new (self) } # [doc = "Bit 11 - Enable UART Transmit Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_txint (& mut self) -> INT_EVENT0_IMASK_TXINT_W < INT_EVENT0_IMASK_SPEC , 11 > { INT_EVENT0_IMASK_TXINT_W :: new (self) } # [doc = "Bit 12 - Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] # [inline (always)] # [must_use] pub fn int_event0_imask_eot (& mut self) -> INT_EVENT0_IMASK_EOT_W < INT_EVENT0_IMASK_SPEC , 12 > { INT_EVENT0_IMASK_EOT_W :: new (self) } # [doc = "Bit 13 - Enable Address Match Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_addr_match (& mut self) -> INT_EVENT0_IMASK_ADDR_MATCH_W < INT_EVENT0_IMASK_SPEC , 13 > { INT_EVENT0_IMASK_ADDR_MATCH_W :: new (self) } # [doc = "Bit 14 - Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] # [inline (always)] # [must_use] pub fn int_event0_imask_cts (& mut self) -> INT_EVENT0_IMASK_CTS_W < INT_EVENT0_IMASK_SPEC , 14 > { INT_EVENT0_IMASK_CTS_W :: new (self) } # [doc = "Bit 15 - Enable DMA Done on RX Event Channel"] # [inline (always)] # [must_use] pub fn int_event0_imask_dma_done_rx (& mut self) -> INT_EVENT0_IMASK_DMA_DONE_RX_W < INT_EVENT0_IMASK_SPEC , 15 > { INT_EVENT0_IMASK_DMA_DONE_RX_W :: new (self) } # [doc = "Bit 16 - Enable DMA Done on TX Event Channel"] # [inline (always)] # [must_use] pub fn int_event0_imask_dma_done_tx (& mut self) -> INT_EVENT0_IMASK_DMA_DONE_TX_W < INT_EVENT0_IMASK_SPEC , 16 > { INT_EVENT0_IMASK_DMA_DONE_TX_W :: new (self) } # [doc = "Bit 17 - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] # [inline (always)] # [must_use] pub fn int_event0_imask_nerr (& mut self) -> INT_EVENT0_IMASK_NERR_W < INT_EVENT0_IMASK_SPEC , 17 > { INT_EVENT0_IMASK_NERR_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Interrupt mask\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_event0_imask::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_event0_imask::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct INT_EVENT0_IMASK_SPEC ; impl crate :: RegisterSpec for INT_EVENT0_IMASK_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`int_event0_imask::R`](R) reader structure"] impl crate :: Readable for INT_EVENT0_IMASK_SPEC { } # [doc = "`write(|w| ..)` method takes [`int_event0_imask::W`](W) writer structure"] impl crate :: Writable for INT_EVENT0_IMASK_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets INT_EVENT0_IMASK to value 0"] impl crate :: Resettable for INT_EVENT0_IMASK_SPEC { const RESET_VALUE : Self :: Ux = 0 ; }
[INFO] [stdout]   |                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                   +++
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing
[INFO] [stdout]  --> src/uart0/int_event0_imask.rs:1:42640
[INFO] [stdout]   |
[INFO] [stdout] 1 | ...mask_linovf (& mut self) -> INT_EVENT0_IMASK_LINOVF_W < INT_EVENT0_IMASK_SPEC , 9 > { INT_EVENT0_IMASK_LINOVF_W :: new (self) } # ...
[INFO] [stdout]   |                 ^^^^^^^^^^     ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here
[INFO] [stdout]   |                 |
[INFO] [stdout]   |                 the lifetime is elided here
[INFO] [stdout]   |
[INFO] [stdout]   = help: the same lifetime is referred to in inconsistent ways, making the signature confusing
[INFO] [stdout] help: use `'_` for type paths
[INFO] [stdout]   |
[INFO] [stdout] 1 | # [doc = "Register `INT_EVENT0_IMASK` reader"] pub type R = crate :: R < INT_EVENT0_IMASK_SPEC > ; # [doc = "Register `INT_EVENT0_IMASK` writer"] pub type W = crate :: W < INT_EVENT0_IMASK_SPEC > ; # [doc = "Field `INT_EVENT0_IMASK_RTOUT` reader - Enable UARTOUT Receive Time-Out Interrupt."] pub type INT_EVENT0_IMASK_RTOUT_R = crate :: BitReader < INT_EVENT0_IMASK_RTOUT_A > ; # [doc = "Enable UARTOUT Receive Time-Out Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_RTOUT_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_RTOUT_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_RTOUT_SET = 1 , } impl From < INT_EVENT0_IMASK_RTOUT_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_RTOUT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_RTOUT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_RTOUT_A { match self . bits { false => INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_CLR , true => INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_rtout_clr (& self) -> bool { * self == INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_rtout_set (& self) -> bool { * self == INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_SET } } # [doc = "Field `INT_EVENT0_IMASK_RTOUT` writer - Enable UARTOUT Receive Time-Out Interrupt."] pub type INT_EVENT0_IMASK_RTOUT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_RTOUT_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_RTOUT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_rtout_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_rtout_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_SET) } } # [doc = "Field `INT_EVENT0_IMASK_FRMERR` reader - Enable UART Framing Error Interrupt."] pub type INT_EVENT0_IMASK_FRMERR_R = crate :: BitReader < INT_EVENT0_IMASK_FRMERR_A > ; # [doc = "Enable UART Framing Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_FRMERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_FRMERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_FRMERR_SET = 1 , } impl From < INT_EVENT0_IMASK_FRMERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_FRMERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_FRMERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_FRMERR_A { match self . bits { false => INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_CLR , true => INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_frmerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_frmerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_FRMERR` writer - Enable UART Framing Error Interrupt."] pub type INT_EVENT0_IMASK_FRMERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_FRMERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_FRMERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_frmerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_frmerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_SET) } } # [doc = "Field `INT_EVENT0_IMASK_PARERR` reader - Enable UART Parity Error Interrupt."] pub type INT_EVENT0_IMASK_PARERR_R = crate :: BitReader < INT_EVENT0_IMASK_PARERR_A > ; # [doc = "Enable UART Parity Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_PARERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_PARERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_PARERR_SET = 1 , } impl From < INT_EVENT0_IMASK_PARERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_PARERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_PARERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_PARERR_A { match self . bits { false => INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_CLR , true => INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_parerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_parerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_PARERR` writer - Enable UART Parity Error Interrupt."] pub type INT_EVENT0_IMASK_PARERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_PARERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_PARERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_parerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_parerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_SET) } } # [doc = "Field `INT_EVENT0_IMASK_BRKERR` reader - Enable UART Break Error Interrupt."] pub type INT_EVENT0_IMASK_BRKERR_R = crate :: BitReader < INT_EVENT0_IMASK_BRKERR_A > ; # [doc = "Enable UART Break Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_BRKERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_BRKERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_BRKERR_SET = 1 , } impl From < INT_EVENT0_IMASK_BRKERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_BRKERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_BRKERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_BRKERR_A { match self . bits { false => INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_CLR , true => INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_brkerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_brkerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_BRKERR` writer - Enable UART Break Error Interrupt."] pub type INT_EVENT0_IMASK_BRKERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_BRKERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_BRKERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_brkerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_brkerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_SET) } } # [doc = "Field `INT_EVENT0_IMASK_OVRERR` reader - Enable UART Receive Overrun Error Interrupt."] pub type INT_EVENT0_IMASK_OVRERR_R = crate :: BitReader < INT_EVENT0_IMASK_OVRERR_A > ; # [doc = "Enable UART Receive Overrun Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_OVRERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_OVRERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_OVRERR_SET = 1 , } impl From < INT_EVENT0_IMASK_OVRERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_OVRERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_OVRERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_OVRERR_A { match self . bits { false => INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_CLR , true => INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_ovrerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_ovrerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_OVRERR` writer - Enable UART Receive Overrun Error Interrupt."] pub type INT_EVENT0_IMASK_OVRERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_OVRERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_OVRERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_ovrerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_ovrerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_SET) } } # [doc = "Field `INT_EVENT0_IMASK_RXNE` reader - Enable Negative Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_IMASK_RXNE_R = crate :: BitReader < INT_EVENT0_IMASK_RXNE_A > ; # [doc = "Enable Negative Edge on UARTxRXD Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_RXNE_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_RXNE_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_RXNE_SET = 1 , } impl From < INT_EVENT0_IMASK_RXNE_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_RXNE_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_RXNE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_RXNE_A { match self . bits { false => INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_CLR , true => INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_rxne_clr (& self) -> bool { * self == INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_rxne_set (& self) -> bool { * self == INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_SET } } # [doc = "Field `INT_EVENT0_IMASK_RXNE` writer - Enable Negative Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_IMASK_RXNE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_RXNE_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_RXNE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_rxne_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_rxne_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_SET) } } # [doc = "Field `INT_EVENT0_IMASK_RXPE` reader - Enable Positive Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_IMASK_RXPE_R = crate :: BitReader < INT_EVENT0_IMASK_RXPE_A > ; # [doc = "Enable Positive Edge on UARTxRXD Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_RXPE_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_RXPE_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_RXPE_SET = 1 , } impl From < INT_EVENT0_IMASK_RXPE_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_RXPE_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_RXPE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_RXPE_A { match self . bits { false => INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_CLR , true => INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_rxpe_clr (& self) -> bool { * self == INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_rxpe_set (& self) -> bool { * self == INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_SET } } # [doc = "Field `INT_EVENT0_IMASK_RXPE` writer - Enable Positive Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_IMASK_RXPE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_RXPE_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_RXPE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_rxpe_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_rxpe_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_SET) } } # [doc = "Field `INT_EVENT0_IMASK_LINC0` reader - Enable LIN Capture 0 / Match Interrupt ."] pub type INT_EVENT0_IMASK_LINC0_R = crate :: BitReader < INT_EVENT0_IMASK_LINC0_A > ; # [doc = "Enable LIN Capture 0 / Match Interrupt .\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_LINC0_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_LINC0_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_LINC0_SET = 1 , } impl From < INT_EVENT0_IMASK_LINC0_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_LINC0_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_LINC0_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_LINC0_A { match self . bits { false => INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_CLR , true => INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_linc0_clr (& self) -> bool { * self == INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_linc0_set (& self) -> bool { * self == INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_SET } } # [doc = "Field `INT_EVENT0_IMASK_LINC0` writer - Enable LIN Capture 0 / Match Interrupt ."] pub type INT_EVENT0_IMASK_LINC0_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_LINC0_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_LINC0_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_linc0_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_linc0_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_SET) } } # [doc = "Field `INT_EVENT0_IMASK_LINC1` reader - Enable LIN Capture 1 Interrupt."] pub type INT_EVENT0_IMASK_LINC1_R = crate :: BitReader < INT_EVENT0_IMASK_LINC1_A > ; # [doc = "Enable LIN Capture 1 Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_LINC1_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_LINC1_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_LINC1_SET = 1 , } impl From < INT_EVENT0_IMASK_LINC1_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_LINC1_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_LINC1_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_LINC1_A { match self . bits { false => INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_CLR , true => INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_linc1_clr (& self) -> bool { * self == INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_linc1_set (& self) -> bool { * self == INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_SET } } # [doc = "Field `INT_EVENT0_IMASK_LINC1` writer - Enable LIN Capture 1 Interrupt."] pub type INT_EVENT0_IMASK_LINC1_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_LINC1_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_LINC1_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_linc1_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_linc1_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_SET) } } # [doc = "Field `INT_EVENT0_IMASK_LINOVF` reader - Enable LIN Hardware Counter Overflow Interrupt."] pub type INT_EVENT0_IMASK_LINOVF_R = crate :: BitReader < INT_EVENT0_IMASK_LINOVF_A > ; # [doc = "Enable LIN Hardware Counter Overflow Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_LINOVF_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_LINOVF_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_LINOVF_SET = 1 , } impl From < INT_EVENT0_IMASK_LINOVF_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_LINOVF_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_LINOVF_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_LINOVF_A { match self . bits { false => INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_CLR , true => INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_linovf_clr (& self) -> bool { * self == INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_linovf_set (& self) -> bool { * self == INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_SET } } # [doc = "Field `INT_EVENT0_IMASK_LINOVF` writer - Enable LIN Hardware Counter Overflow Interrupt."] pub type INT_EVENT0_IMASK_LINOVF_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_LINOVF_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_LINOVF_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_linovf_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_linovf_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_SET) } } # [doc = "Field `INT_EVENT0_IMASK_RXINT` reader - Enable UART Receive Interrupt."] pub type INT_EVENT0_IMASK_RXINT_R = crate :: BitReader < INT_EVENT0_IMASK_RXINT_A > ; # [doc = "Enable UART Receive Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_RXINT_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_RXINT_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_RXINT_SET = 1 , } impl From < INT_EVENT0_IMASK_RXINT_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_RXINT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_RXINT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_RXINT_A { match self . bits { false => INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_CLR , true => INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_rxint_clr (& self) -> bool { * self == INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_rxint_set (& self) -> bool { * self == INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_SET } } # [doc = "Field `INT_EVENT0_IMASK_RXINT` writer - Enable UART Receive Interrupt."] pub type INT_EVENT0_IMASK_RXINT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_RXINT_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_RXINT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_rxint_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_rxint_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_SET) } } # [doc = "Field `INT_EVENT0_IMASK_TXINT` reader - Enable UART Transmit Interrupt."] pub type INT_EVENT0_IMASK_TXINT_R = crate :: BitReader < INT_EVENT0_IMASK_TXINT_A > ; # [doc = "Enable UART Transmit Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_TXINT_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_TXINT_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_TXINT_SET = 1 , } impl From < INT_EVENT0_IMASK_TXINT_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_TXINT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_TXINT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_TXINT_A { match self . bits { false => INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_CLR , true => INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_txint_clr (& self) -> bool { * self == INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_txint_set (& self) -> bool { * self == INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_SET } } # [doc = "Field `INT_EVENT0_IMASK_TXINT` writer - Enable UART Transmit Interrupt."] pub type INT_EVENT0_IMASK_TXINT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_TXINT_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_TXINT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_txint_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_txint_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_SET) } } # [doc = "Field `INT_EVENT0_IMASK_EOT` reader - Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] pub type INT_EVENT0_IMASK_EOT_R = crate :: BitReader < INT_EVENT0_IMASK_EOT_A > ; # [doc = "Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_EOT_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_EOT_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_EOT_SET = 1 , } impl From < INT_EVENT0_IMASK_EOT_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_EOT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_EOT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_EOT_A { match self . bits { false => INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_CLR , true => INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_eot_clr (& self) -> bool { * self == INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_eot_set (& self) -> bool { * self == INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_SET } } # [doc = "Field `INT_EVENT0_IMASK_EOT` writer - Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] pub type INT_EVENT0_IMASK_EOT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_EOT_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_EOT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_eot_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_eot_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_SET) } } # [doc = "Field `INT_EVENT0_IMASK_ADDR_MATCH` reader - Enable Address Match Interrupt."] pub type INT_EVENT0_IMASK_ADDR_MATCH_R = crate :: BitReader < INT_EVENT0_IMASK_ADDR_MATCH_A > ; # [doc = "Enable Address Match Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_ADDR_MATCH_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_ADDR_MATCH_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_ADDR_MATCH_SET = 1 , } impl From < INT_EVENT0_IMASK_ADDR_MATCH_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_ADDR_MATCH_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_ADDR_MATCH_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_ADDR_MATCH_A { match self . bits { false => INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_CLR , true => INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_addr_match_clr (& self) -> bool { * self == INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_addr_match_set (& self) -> bool { * self == INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_SET } } # [doc = "Field `INT_EVENT0_IMASK_ADDR_MATCH` writer - Enable Address Match Interrupt."] pub type INT_EVENT0_IMASK_ADDR_MATCH_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_ADDR_MATCH_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_ADDR_MATCH_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_addr_match_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_addr_match_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_SET) } } # [doc = "Field `INT_EVENT0_IMASK_CTS` reader - Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] pub type INT_EVENT0_IMASK_CTS_R = crate :: BitReader < INT_EVENT0_IMASK_CTS_A > ; # [doc = "Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_CTS_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_CTS_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_CTS_SET = 1 , } impl From < INT_EVENT0_IMASK_CTS_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_CTS_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_CTS_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_CTS_A { match self . bits { false => INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_CLR , true => INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_cts_clr (& self) -> bool { * self == INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_cts_set (& self) -> bool { * self == INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_SET } } # [doc = "Field `INT_EVENT0_IMASK_CTS` writer - Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] pub type INT_EVENT0_IMASK_CTS_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_CTS_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_CTS_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_cts_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_cts_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DMA_DONE_RX` reader - Enable DMA Done on RX Event Channel"] pub type INT_EVENT0_IMASK_DMA_DONE_RX_R = crate :: BitReader < INT_EVENT0_IMASK_DMA_DONE_RX_A > ; # [doc = "Enable DMA Done on RX Event Channel\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DMA_DONE_RX_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DMA_DONE_RX_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DMA_DONE_RX_SET = 1 , } impl From < INT_EVENT0_IMASK_DMA_DONE_RX_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DMA_DONE_RX_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DMA_DONE_RX_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DMA_DONE_RX_A { match self . bits { false => INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_CLR , true => INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dma_done_rx_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dma_done_rx_set (& self) -> bool { * self == INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_SET } } # [doc = "Field `INT_EVENT0_IMASK_DMA_DONE_RX` writer - Enable DMA Done on RX Event Channel"] pub type INT_EVENT0_IMASK_DMA_DONE_RX_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DMA_DONE_RX_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DMA_DONE_RX_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dma_done_rx_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dma_done_rx_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DMA_DONE_TX` reader - Enable DMA Done on TX Event Channel"] pub type INT_EVENT0_IMASK_DMA_DONE_TX_R = crate :: BitReader < INT_EVENT0_IMASK_DMA_DONE_TX_A > ; # [doc = "Enable DMA Done on TX Event Channel\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DMA_DONE_TX_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DMA_DONE_TX_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DMA_DONE_TX_SET = 1 , } impl From < INT_EVENT0_IMASK_DMA_DONE_TX_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DMA_DONE_TX_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DMA_DONE_TX_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DMA_DONE_TX_A { match self . bits { false => INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_CLR , true => INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dma_done_tx_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dma_done_tx_set (& self) -> bool { * self == INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_SET } } # [doc = "Field `INT_EVENT0_IMASK_DMA_DONE_TX` writer - Enable DMA Done on TX Event Channel"] pub type INT_EVENT0_IMASK_DMA_DONE_TX_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DMA_DONE_TX_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DMA_DONE_TX_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dma_done_tx_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dma_done_tx_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_SET) } } # [doc = "Field `INT_EVENT0_IMASK_NERR` reader - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] pub type INT_EVENT0_IMASK_NERR_R = crate :: BitReader < INT_EVENT0_IMASK_NERR_A > ; # [doc = "Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_NERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_NERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_NERR_SET = 1 , } impl From < INT_EVENT0_IMASK_NERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_NERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_NERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_NERR_A { match self . bits { false => INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_CLR , true => INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_nerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_nerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_NERR` writer - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] pub type INT_EVENT0_IMASK_NERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_NERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_NERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_nerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_nerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_SET) } } impl R { # [doc = "Bit 0 - Enable UARTOUT Receive Time-Out Interrupt."] # [inline (always)] pub fn int_event0_imask_rtout (& self) -> INT_EVENT0_IMASK_RTOUT_R { INT_EVENT0_IMASK_RTOUT_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - Enable UART Framing Error Interrupt."] # [inline (always)] pub fn int_event0_imask_frmerr (& self) -> INT_EVENT0_IMASK_FRMERR_R { INT_EVENT0_IMASK_FRMERR_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - Enable UART Parity Error Interrupt."] # [inline (always)] pub fn int_event0_imask_parerr (& self) -> INT_EVENT0_IMASK_PARERR_R { INT_EVENT0_IMASK_PARERR_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - Enable UART Break Error Interrupt."] # [inline (always)] pub fn int_event0_imask_brkerr (& self) -> INT_EVENT0_IMASK_BRKERR_R { INT_EVENT0_IMASK_BRKERR_R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - Enable UART Receive Overrun Error Interrupt."] # [inline (always)] pub fn int_event0_imask_ovrerr (& self) -> INT_EVENT0_IMASK_OVRERR_R { INT_EVENT0_IMASK_OVRERR_R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - Enable Negative Edge on UARTxRXD Interrupt."] # [inline (always)] pub fn int_event0_imask_rxne (& self) -> INT_EVENT0_IMASK_RXNE_R { INT_EVENT0_IMASK_RXNE_R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - Enable Positive Edge on UARTxRXD Interrupt."] # [inline (always)] pub fn int_event0_imask_rxpe (& self) -> INT_EVENT0_IMASK_RXPE_R { INT_EVENT0_IMASK_RXPE_R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - Enable LIN Capture 0 / Match Interrupt ."] # [inline (always)] pub fn int_event0_imask_linc0 (& self) -> INT_EVENT0_IMASK_LINC0_R { INT_EVENT0_IMASK_LINC0_R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - Enable LIN Capture 1 Interrupt."] # [inline (always)] pub fn int_event0_imask_linc1 (& self) -> INT_EVENT0_IMASK_LINC1_R { INT_EVENT0_IMASK_LINC1_R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - Enable LIN Hardware Counter Overflow Interrupt."] # [inline (always)] pub fn int_event0_imask_linovf (& self) -> INT_EVENT0_IMASK_LINOVF_R { INT_EVENT0_IMASK_LINOVF_R :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - Enable UART Receive Interrupt."] # [inline (always)] pub fn int_event0_imask_rxint (& self) -> INT_EVENT0_IMASK_RXINT_R { INT_EVENT0_IMASK_RXINT_R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - Enable UART Transmit Interrupt."] # [inline (always)] pub fn int_event0_imask_txint (& self) -> INT_EVENT0_IMASK_TXINT_R { INT_EVENT0_IMASK_TXINT_R :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] # [inline (always)] pub fn int_event0_imask_eot (& self) -> INT_EVENT0_IMASK_EOT_R { INT_EVENT0_IMASK_EOT_R :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - Enable Address Match Interrupt."] # [inline (always)] pub fn int_event0_imask_addr_match (& self) -> INT_EVENT0_IMASK_ADDR_MATCH_R { INT_EVENT0_IMASK_ADDR_MATCH_R :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 14 - Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] # [inline (always)] pub fn int_event0_imask_cts (& self) -> INT_EVENT0_IMASK_CTS_R { INT_EVENT0_IMASK_CTS_R :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - Enable DMA Done on RX Event Channel"] # [inline (always)] pub fn int_event0_imask_dma_done_rx (& self) -> INT_EVENT0_IMASK_DMA_DONE_RX_R { INT_EVENT0_IMASK_DMA_DONE_RX_R :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bit 16 - Enable DMA Done on TX Event Channel"] # [inline (always)] pub fn int_event0_imask_dma_done_tx (& self) -> INT_EVENT0_IMASK_DMA_DONE_TX_R { INT_EVENT0_IMASK_DMA_DONE_TX_R :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] # [inline (always)] pub fn int_event0_imask_nerr (& self) -> INT_EVENT0_IMASK_NERR_R { INT_EVENT0_IMASK_NERR_R :: new (((self . bits >> 17) & 1) != 0) } } impl W { # [doc = "Bit 0 - Enable UARTOUT Receive Time-Out Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_rtout (& mut self) -> INT_EVENT0_IMASK_RTOUT_W < INT_EVENT0_IMASK_SPEC , 0 > { INT_EVENT0_IMASK_RTOUT_W :: new (self) } # [doc = "Bit 1 - Enable UART Framing Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_frmerr (& mut self) -> INT_EVENT0_IMASK_FRMERR_W < INT_EVENT0_IMASK_SPEC , 1 > { INT_EVENT0_IMASK_FRMERR_W :: new (self) } # [doc = "Bit 2 - Enable UART Parity Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_parerr (& mut self) -> INT_EVENT0_IMASK_PARERR_W < INT_EVENT0_IMASK_SPEC , 2 > { INT_EVENT0_IMASK_PARERR_W :: new (self) } # [doc = "Bit 3 - Enable UART Break Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_brkerr (& mut self) -> INT_EVENT0_IMASK_BRKERR_W < INT_EVENT0_IMASK_SPEC , 3 > { INT_EVENT0_IMASK_BRKERR_W :: new (self) } # [doc = "Bit 4 - Enable UART Receive Overrun Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_ovrerr (& mut self) -> INT_EVENT0_IMASK_OVRERR_W < INT_EVENT0_IMASK_SPEC , 4 > { INT_EVENT0_IMASK_OVRERR_W :: new (self) } # [doc = "Bit 5 - Enable Negative Edge on UARTxRXD Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_rxne (& mut self) -> INT_EVENT0_IMASK_RXNE_W < INT_EVENT0_IMASK_SPEC , 5 > { INT_EVENT0_IMASK_RXNE_W :: new (self) } # [doc = "Bit 6 - Enable Positive Edge on UARTxRXD Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_rxpe (& mut self) -> INT_EVENT0_IMASK_RXPE_W < INT_EVENT0_IMASK_SPEC , 6 > { INT_EVENT0_IMASK_RXPE_W :: new (self) } # [doc = "Bit 7 - Enable LIN Capture 0 / Match Interrupt ."] # [inline (always)] # [must_use] pub fn int_event0_imask_linc0 (& mut self) -> INT_EVENT0_IMASK_LINC0_W < INT_EVENT0_IMASK_SPEC , 7 > { INT_EVENT0_IMASK_LINC0_W :: new (self) } # [doc = "Bit 8 - Enable LIN Capture 1 Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_linc1 (& mut self) -> INT_EVENT0_IMASK_LINC1_W < INT_EVENT0_IMASK_SPEC , 8 > { INT_EVENT0_IMASK_LINC1_W :: new (self) } # [doc = "Bit 9 - Enable LIN Hardware Counter Overflow Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_linovf (& mut self) -> INT_EVENT0_IMASK_LINOVF_W <'_,  INT_EVENT0_IMASK_SPEC , 9 > { INT_EVENT0_IMASK_LINOVF_W :: new (self) } # [doc = "Bit 10 - Enable UART Receive Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_rxint (& mut self) -> INT_EVENT0_IMASK_RXINT_W < INT_EVENT0_IMASK_SPEC , 10 > { INT_EVENT0_IMASK_RXINT_W :: new (self) } # [doc = "Bit 11 - Enable UART Transmit Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_txint (& mut self) -> INT_EVENT0_IMASK_TXINT_W < INT_EVENT0_IMASK_SPEC , 11 > { INT_EVENT0_IMASK_TXINT_W :: new (self) } # [doc = "Bit 12 - Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] # [inline (always)] # [must_use] pub fn int_event0_imask_eot (& mut self) -> INT_EVENT0_IMASK_EOT_W < INT_EVENT0_IMASK_SPEC , 12 > { INT_EVENT0_IMASK_EOT_W :: new (self) } # [doc = "Bit 13 - Enable Address Match Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_addr_match (& mut self) -> INT_EVENT0_IMASK_ADDR_MATCH_W < INT_EVENT0_IMASK_SPEC , 13 > { INT_EVENT0_IMASK_ADDR_MATCH_W :: new (self) } # [doc = "Bit 14 - Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] # [inline (always)] # [must_use] pub fn int_event0_imask_cts (& mut self) -> INT_EVENT0_IMASK_CTS_W < INT_EVENT0_IMASK_SPEC , 14 > { INT_EVENT0_IMASK_CTS_W :: new (self) } # [doc = "Bit 15 - Enable DMA Done on RX Event Channel"] # [inline (always)] # [must_use] pub fn int_event0_imask_dma_done_rx (& mut self) -> INT_EVENT0_IMASK_DMA_DONE_RX_W < INT_EVENT0_IMASK_SPEC , 15 > { INT_EVENT0_IMASK_DMA_DONE_RX_W :: new (self) } # [doc = "Bit 16 - Enable DMA Done on TX Event Channel"] # [inline (always)] # [must_use] pub fn int_event0_imask_dma_done_tx (& mut self) -> INT_EVENT0_IMASK_DMA_DONE_TX_W < INT_EVENT0_IMASK_SPEC , 16 > { INT_EVENT0_IMASK_DMA_DONE_TX_W :: new (self) } # [doc = "Bit 17 - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] # [inline (always)] # [must_use] pub fn int_event0_imask_nerr (& mut self) -> INT_EVENT0_IMASK_NERR_W < INT_EVENT0_IMASK_SPEC , 17 > { INT_EVENT0_IMASK_NERR_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Interrupt mask\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_event0_imask::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_event0_imask::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct INT_EVENT0_IMASK_SPEC ; impl crate :: RegisterSpec for INT_EVENT0_IMASK_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`int_event0_imask::R`](R) reader structure"] impl crate :: Readable for INT_EVENT0_IMASK_SPEC { } # [doc = "`write(|w| ..)` method takes [`int_event0_imask::W`](W) writer structure"] impl crate :: Writable for INT_EVENT0_IMASK_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets INT_EVENT0_IMASK to value 0"] impl crate :: Resettable for INT_EVENT0_IMASK_SPEC { const RESET_VALUE : Self :: Ux = 0 ; }
[INFO] [stdout]   |                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                          +++
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing
[INFO] [stdout]  --> src/uart0/int_event0_imask.rs:1:42871
[INFO] [stdout]   |
[INFO] [stdout] 1 | ...imask_rxint (& mut self) -> INT_EVENT0_IMASK_RXINT_W < INT_EVENT0_IMASK_SPEC , 10 > { INT_EVENT0_IMASK_RXINT_W :: new (self) } # [...
[INFO] [stdout]   |                 ^^^^^^^^^^     ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here
[INFO] [stdout]   |                 |
[INFO] [stdout]   |                 the lifetime is elided here
[INFO] [stdout]   |
[INFO] [stdout]   = help: the same lifetime is referred to in inconsistent ways, making the signature confusing
[INFO] [stdout] help: use `'_` for type paths
[INFO] [stdout]   |
[INFO] [stdout] 1 | # [doc = "Register `INT_EVENT0_IMASK` reader"] pub type R = crate :: R < INT_EVENT0_IMASK_SPEC > ; # [doc = "Register `INT_EVENT0_IMASK` writer"] pub type W = crate :: W < INT_EVENT0_IMASK_SPEC > ; # [doc = "Field `INT_EVENT0_IMASK_RTOUT` reader - Enable UARTOUT Receive Time-Out Interrupt."] pub type INT_EVENT0_IMASK_RTOUT_R = crate :: BitReader < INT_EVENT0_IMASK_RTOUT_A > ; # [doc = "Enable UARTOUT Receive Time-Out Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_RTOUT_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_RTOUT_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_RTOUT_SET = 1 , } impl From < INT_EVENT0_IMASK_RTOUT_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_RTOUT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_RTOUT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_RTOUT_A { match self . bits { false => INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_CLR , true => INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_rtout_clr (& self) -> bool { * self == INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_rtout_set (& self) -> bool { * self == INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_SET } } # [doc = "Field `INT_EVENT0_IMASK_RTOUT` writer - Enable UARTOUT Receive Time-Out Interrupt."] pub type INT_EVENT0_IMASK_RTOUT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_RTOUT_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_RTOUT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_rtout_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_rtout_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_SET) } } # [doc = "Field `INT_EVENT0_IMASK_FRMERR` reader - Enable UART Framing Error Interrupt."] pub type INT_EVENT0_IMASK_FRMERR_R = crate :: BitReader < INT_EVENT0_IMASK_FRMERR_A > ; # [doc = "Enable UART Framing Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_FRMERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_FRMERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_FRMERR_SET = 1 , } impl From < INT_EVENT0_IMASK_FRMERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_FRMERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_FRMERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_FRMERR_A { match self . bits { false => INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_CLR , true => INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_frmerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_frmerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_FRMERR` writer - Enable UART Framing Error Interrupt."] pub type INT_EVENT0_IMASK_FRMERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_FRMERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_FRMERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_frmerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_frmerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_SET) } } # [doc = "Field `INT_EVENT0_IMASK_PARERR` reader - Enable UART Parity Error Interrupt."] pub type INT_EVENT0_IMASK_PARERR_R = crate :: BitReader < INT_EVENT0_IMASK_PARERR_A > ; # [doc = "Enable UART Parity Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_PARERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_PARERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_PARERR_SET = 1 , } impl From < INT_EVENT0_IMASK_PARERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_PARERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_PARERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_PARERR_A { match self . bits { false => INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_CLR , true => INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_parerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_parerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_PARERR` writer - Enable UART Parity Error Interrupt."] pub type INT_EVENT0_IMASK_PARERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_PARERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_PARERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_parerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_parerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_SET) } } # [doc = "Field `INT_EVENT0_IMASK_BRKERR` reader - Enable UART Break Error Interrupt."] pub type INT_EVENT0_IMASK_BRKERR_R = crate :: BitReader < INT_EVENT0_IMASK_BRKERR_A > ; # [doc = "Enable UART Break Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_BRKERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_BRKERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_BRKERR_SET = 1 , } impl From < INT_EVENT0_IMASK_BRKERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_BRKERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_BRKERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_BRKERR_A { match self . bits { false => INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_CLR , true => INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_brkerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_brkerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_BRKERR` writer - Enable UART Break Error Interrupt."] pub type INT_EVENT0_IMASK_BRKERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_BRKERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_BRKERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_brkerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_brkerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_SET) } } # [doc = "Field `INT_EVENT0_IMASK_OVRERR` reader - Enable UART Receive Overrun Error Interrupt."] pub type INT_EVENT0_IMASK_OVRERR_R = crate :: BitReader < INT_EVENT0_IMASK_OVRERR_A > ; # [doc = "Enable UART Receive Overrun Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_OVRERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_OVRERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_OVRERR_SET = 1 , } impl From < INT_EVENT0_IMASK_OVRERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_OVRERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_OVRERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_OVRERR_A { match self . bits { false => INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_CLR , true => INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_ovrerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_ovrerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_OVRERR` writer - Enable UART Receive Overrun Error Interrupt."] pub type INT_EVENT0_IMASK_OVRERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_OVRERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_OVRERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_ovrerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_ovrerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_SET) } } # [doc = "Field `INT_EVENT0_IMASK_RXNE` reader - Enable Negative Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_IMASK_RXNE_R = crate :: BitReader < INT_EVENT0_IMASK_RXNE_A > ; # [doc = "Enable Negative Edge on UARTxRXD Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_RXNE_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_RXNE_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_RXNE_SET = 1 , } impl From < INT_EVENT0_IMASK_RXNE_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_RXNE_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_RXNE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_RXNE_A { match self . bits { false => INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_CLR , true => INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_rxne_clr (& self) -> bool { * self == INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_rxne_set (& self) -> bool { * self == INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_SET } } # [doc = "Field `INT_EVENT0_IMASK_RXNE` writer - Enable Negative Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_IMASK_RXNE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_RXNE_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_RXNE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_rxne_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_rxne_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_SET) } } # [doc = "Field `INT_EVENT0_IMASK_RXPE` reader - Enable Positive Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_IMASK_RXPE_R = crate :: BitReader < INT_EVENT0_IMASK_RXPE_A > ; # [doc = "Enable Positive Edge on UARTxRXD Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_RXPE_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_RXPE_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_RXPE_SET = 1 , } impl From < INT_EVENT0_IMASK_RXPE_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_RXPE_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_RXPE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_RXPE_A { match self . bits { false => INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_CLR , true => INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_rxpe_clr (& self) -> bool { * self == INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_rxpe_set (& self) -> bool { * self == INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_SET } } # [doc = "Field `INT_EVENT0_IMASK_RXPE` writer - Enable Positive Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_IMASK_RXPE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_RXPE_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_RXPE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_rxpe_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_rxpe_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_SET) } } # [doc = "Field `INT_EVENT0_IMASK_LINC0` reader - Enable LIN Capture 0 / Match Interrupt ."] pub type INT_EVENT0_IMASK_LINC0_R = crate :: BitReader < INT_EVENT0_IMASK_LINC0_A > ; # [doc = "Enable LIN Capture 0 / Match Interrupt .\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_LINC0_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_LINC0_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_LINC0_SET = 1 , } impl From < INT_EVENT0_IMASK_LINC0_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_LINC0_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_LINC0_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_LINC0_A { match self . bits { false => INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_CLR , true => INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_linc0_clr (& self) -> bool { * self == INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_linc0_set (& self) -> bool { * self == INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_SET } } # [doc = "Field `INT_EVENT0_IMASK_LINC0` writer - Enable LIN Capture 0 / Match Interrupt ."] pub type INT_EVENT0_IMASK_LINC0_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_LINC0_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_LINC0_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_linc0_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_linc0_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_SET) } } # [doc = "Field `INT_EVENT0_IMASK_LINC1` reader - Enable LIN Capture 1 Interrupt."] pub type INT_EVENT0_IMASK_LINC1_R = crate :: BitReader < INT_EVENT0_IMASK_LINC1_A > ; # [doc = "Enable LIN Capture 1 Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_LINC1_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_LINC1_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_LINC1_SET = 1 , } impl From < INT_EVENT0_IMASK_LINC1_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_LINC1_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_LINC1_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_LINC1_A { match self . bits { false => INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_CLR , true => INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_linc1_clr (& self) -> bool { * self == INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_linc1_set (& self) -> bool { * self == INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_SET } } # [doc = "Field `INT_EVENT0_IMASK_LINC1` writer - Enable LIN Capture 1 Interrupt."] pub type INT_EVENT0_IMASK_LINC1_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_LINC1_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_LINC1_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_linc1_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_linc1_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_SET) } } # [doc = "Field `INT_EVENT0_IMASK_LINOVF` reader - Enable LIN Hardware Counter Overflow Interrupt."] pub type INT_EVENT0_IMASK_LINOVF_R = crate :: BitReader < INT_EVENT0_IMASK_LINOVF_A > ; # [doc = "Enable LIN Hardware Counter Overflow Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_LINOVF_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_LINOVF_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_LINOVF_SET = 1 , } impl From < INT_EVENT0_IMASK_LINOVF_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_LINOVF_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_LINOVF_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_LINOVF_A { match self . bits { false => INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_CLR , true => INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_linovf_clr (& self) -> bool { * self == INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_linovf_set (& self) -> bool { * self == INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_SET } } # [doc = "Field `INT_EVENT0_IMASK_LINOVF` writer - Enable LIN Hardware Counter Overflow Interrupt."] pub type INT_EVENT0_IMASK_LINOVF_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_LINOVF_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_LINOVF_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_linovf_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_linovf_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_SET) } } # [doc = "Field `INT_EVENT0_IMASK_RXINT` reader - Enable UART Receive Interrupt."] pub type INT_EVENT0_IMASK_RXINT_R = crate :: BitReader < INT_EVENT0_IMASK_RXINT_A > ; # [doc = "Enable UART Receive Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_RXINT_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_RXINT_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_RXINT_SET = 1 , } impl From < INT_EVENT0_IMASK_RXINT_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_RXINT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_RXINT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_RXINT_A { match self . bits { false => INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_CLR , true => INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_rxint_clr (& self) -> bool { * self == INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_rxint_set (& self) -> bool { * self == INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_SET } } # [doc = "Field `INT_EVENT0_IMASK_RXINT` writer - Enable UART Receive Interrupt."] pub type INT_EVENT0_IMASK_RXINT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_RXINT_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_RXINT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_rxint_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_rxint_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_SET) } } # [doc = "Field `INT_EVENT0_IMASK_TXINT` reader - Enable UART Transmit Interrupt."] pub type INT_EVENT0_IMASK_TXINT_R = crate :: BitReader < INT_EVENT0_IMASK_TXINT_A > ; # [doc = "Enable UART Transmit Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_TXINT_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_TXINT_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_TXINT_SET = 1 , } impl From < INT_EVENT0_IMASK_TXINT_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_TXINT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_TXINT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_TXINT_A { match self . bits { false => INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_CLR , true => INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_txint_clr (& self) -> bool { * self == INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_txint_set (& self) -> bool { * self == INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_SET } } # [doc = "Field `INT_EVENT0_IMASK_TXINT` writer - Enable UART Transmit Interrupt."] pub type INT_EVENT0_IMASK_TXINT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_TXINT_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_TXINT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_txint_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_txint_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_SET) } } # [doc = "Field `INT_EVENT0_IMASK_EOT` reader - Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] pub type INT_EVENT0_IMASK_EOT_R = crate :: BitReader < INT_EVENT0_IMASK_EOT_A > ; # [doc = "Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_EOT_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_EOT_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_EOT_SET = 1 , } impl From < INT_EVENT0_IMASK_EOT_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_EOT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_EOT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_EOT_A { match self . bits { false => INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_CLR , true => INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_eot_clr (& self) -> bool { * self == INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_eot_set (& self) -> bool { * self == INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_SET } } # [doc = "Field `INT_EVENT0_IMASK_EOT` writer - Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] pub type INT_EVENT0_IMASK_EOT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_EOT_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_EOT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_eot_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_eot_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_SET) } } # [doc = "Field `INT_EVENT0_IMASK_ADDR_MATCH` reader - Enable Address Match Interrupt."] pub type INT_EVENT0_IMASK_ADDR_MATCH_R = crate :: BitReader < INT_EVENT0_IMASK_ADDR_MATCH_A > ; # [doc = "Enable Address Match Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_ADDR_MATCH_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_ADDR_MATCH_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_ADDR_MATCH_SET = 1 , } impl From < INT_EVENT0_IMASK_ADDR_MATCH_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_ADDR_MATCH_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_ADDR_MATCH_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_ADDR_MATCH_A { match self . bits { false => INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_CLR , true => INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_addr_match_clr (& self) -> bool { * self == INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_addr_match_set (& self) -> bool { * self == INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_SET } } # [doc = "Field `INT_EVENT0_IMASK_ADDR_MATCH` writer - Enable Address Match Interrupt."] pub type INT_EVENT0_IMASK_ADDR_MATCH_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_ADDR_MATCH_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_ADDR_MATCH_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_addr_match_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_addr_match_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_SET) } } # [doc = "Field `INT_EVENT0_IMASK_CTS` reader - Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] pub type INT_EVENT0_IMASK_CTS_R = crate :: BitReader < INT_EVENT0_IMASK_CTS_A > ; # [doc = "Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_CTS_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_CTS_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_CTS_SET = 1 , } impl From < INT_EVENT0_IMASK_CTS_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_CTS_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_CTS_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_CTS_A { match self . bits { false => INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_CLR , true => INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_cts_clr (& self) -> bool { * self == INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_cts_set (& self) -> bool { * self == INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_SET } } # [doc = "Field `INT_EVENT0_IMASK_CTS` writer - Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] pub type INT_EVENT0_IMASK_CTS_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_CTS_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_CTS_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_cts_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_cts_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DMA_DONE_RX` reader - Enable DMA Done on RX Event Channel"] pub type INT_EVENT0_IMASK_DMA_DONE_RX_R = crate :: BitReader < INT_EVENT0_IMASK_DMA_DONE_RX_A > ; # [doc = "Enable DMA Done on RX Event Channel\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DMA_DONE_RX_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DMA_DONE_RX_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DMA_DONE_RX_SET = 1 , } impl From < INT_EVENT0_IMASK_DMA_DONE_RX_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DMA_DONE_RX_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DMA_DONE_RX_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DMA_DONE_RX_A { match self . bits { false => INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_CLR , true => INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dma_done_rx_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dma_done_rx_set (& self) -> bool { * self == INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_SET } } # [doc = "Field `INT_EVENT0_IMASK_DMA_DONE_RX` writer - Enable DMA Done on RX Event Channel"] pub type INT_EVENT0_IMASK_DMA_DONE_RX_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DMA_DONE_RX_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DMA_DONE_RX_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dma_done_rx_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dma_done_rx_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DMA_DONE_TX` reader - Enable DMA Done on TX Event Channel"] pub type INT_EVENT0_IMASK_DMA_DONE_TX_R = crate :: BitReader < INT_EVENT0_IMASK_DMA_DONE_TX_A > ; # [doc = "Enable DMA Done on TX Event Channel\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DMA_DONE_TX_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DMA_DONE_TX_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DMA_DONE_TX_SET = 1 , } impl From < INT_EVENT0_IMASK_DMA_DONE_TX_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DMA_DONE_TX_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DMA_DONE_TX_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DMA_DONE_TX_A { match self . bits { false => INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_CLR , true => INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dma_done_tx_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dma_done_tx_set (& self) -> bool { * self == INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_SET } } # [doc = "Field `INT_EVENT0_IMASK_DMA_DONE_TX` writer - Enable DMA Done on TX Event Channel"] pub type INT_EVENT0_IMASK_DMA_DONE_TX_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DMA_DONE_TX_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DMA_DONE_TX_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dma_done_tx_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dma_done_tx_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_SET) } } # [doc = "Field `INT_EVENT0_IMASK_NERR` reader - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] pub type INT_EVENT0_IMASK_NERR_R = crate :: BitReader < INT_EVENT0_IMASK_NERR_A > ; # [doc = "Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_NERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_NERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_NERR_SET = 1 , } impl From < INT_EVENT0_IMASK_NERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_NERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_NERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_NERR_A { match self . bits { false => INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_CLR , true => INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_nerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_nerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_NERR` writer - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] pub type INT_EVENT0_IMASK_NERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_NERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_NERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_nerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_nerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_SET) } } impl R { # [doc = "Bit 0 - Enable UARTOUT Receive Time-Out Interrupt."] # [inline (always)] pub fn int_event0_imask_rtout (& self) -> INT_EVENT0_IMASK_RTOUT_R { INT_EVENT0_IMASK_RTOUT_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - Enable UART Framing Error Interrupt."] # [inline (always)] pub fn int_event0_imask_frmerr (& self) -> INT_EVENT0_IMASK_FRMERR_R { INT_EVENT0_IMASK_FRMERR_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - Enable UART Parity Error Interrupt."] # [inline (always)] pub fn int_event0_imask_parerr (& self) -> INT_EVENT0_IMASK_PARERR_R { INT_EVENT0_IMASK_PARERR_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - Enable UART Break Error Interrupt."] # [inline (always)] pub fn int_event0_imask_brkerr (& self) -> INT_EVENT0_IMASK_BRKERR_R { INT_EVENT0_IMASK_BRKERR_R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - Enable UART Receive Overrun Error Interrupt."] # [inline (always)] pub fn int_event0_imask_ovrerr (& self) -> INT_EVENT0_IMASK_OVRERR_R { INT_EVENT0_IMASK_OVRERR_R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - Enable Negative Edge on UARTxRXD Interrupt."] # [inline (always)] pub fn int_event0_imask_rxne (& self) -> INT_EVENT0_IMASK_RXNE_R { INT_EVENT0_IMASK_RXNE_R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - Enable Positive Edge on UARTxRXD Interrupt."] # [inline (always)] pub fn int_event0_imask_rxpe (& self) -> INT_EVENT0_IMASK_RXPE_R { INT_EVENT0_IMASK_RXPE_R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - Enable LIN Capture 0 / Match Interrupt ."] # [inline (always)] pub fn int_event0_imask_linc0 (& self) -> INT_EVENT0_IMASK_LINC0_R { INT_EVENT0_IMASK_LINC0_R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - Enable LIN Capture 1 Interrupt."] # [inline (always)] pub fn int_event0_imask_linc1 (& self) -> INT_EVENT0_IMASK_LINC1_R { INT_EVENT0_IMASK_LINC1_R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - Enable LIN Hardware Counter Overflow Interrupt."] # [inline (always)] pub fn int_event0_imask_linovf (& self) -> INT_EVENT0_IMASK_LINOVF_R { INT_EVENT0_IMASK_LINOVF_R :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - Enable UART Receive Interrupt."] # [inline (always)] pub fn int_event0_imask_rxint (& self) -> INT_EVENT0_IMASK_RXINT_R { INT_EVENT0_IMASK_RXINT_R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - Enable UART Transmit Interrupt."] # [inline (always)] pub fn int_event0_imask_txint (& self) -> INT_EVENT0_IMASK_TXINT_R { INT_EVENT0_IMASK_TXINT_R :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] # [inline (always)] pub fn int_event0_imask_eot (& self) -> INT_EVENT0_IMASK_EOT_R { INT_EVENT0_IMASK_EOT_R :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - Enable Address Match Interrupt."] # [inline (always)] pub fn int_event0_imask_addr_match (& self) -> INT_EVENT0_IMASK_ADDR_MATCH_R { INT_EVENT0_IMASK_ADDR_MATCH_R :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 14 - Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] # [inline (always)] pub fn int_event0_imask_cts (& self) -> INT_EVENT0_IMASK_CTS_R { INT_EVENT0_IMASK_CTS_R :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - Enable DMA Done on RX Event Channel"] # [inline (always)] pub fn int_event0_imask_dma_done_rx (& self) -> INT_EVENT0_IMASK_DMA_DONE_RX_R { INT_EVENT0_IMASK_DMA_DONE_RX_R :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bit 16 - Enable DMA Done on TX Event Channel"] # [inline (always)] pub fn int_event0_imask_dma_done_tx (& self) -> INT_EVENT0_IMASK_DMA_DONE_TX_R { INT_EVENT0_IMASK_DMA_DONE_TX_R :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] # [inline (always)] pub fn int_event0_imask_nerr (& self) -> INT_EVENT0_IMASK_NERR_R { INT_EVENT0_IMASK_NERR_R :: new (((self . bits >> 17) & 1) != 0) } } impl W { # [doc = "Bit 0 - Enable UARTOUT Receive Time-Out Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_rtout (& mut self) -> INT_EVENT0_IMASK_RTOUT_W < INT_EVENT0_IMASK_SPEC , 0 > { INT_EVENT0_IMASK_RTOUT_W :: new (self) } # [doc = "Bit 1 - Enable UART Framing Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_frmerr (& mut self) -> INT_EVENT0_IMASK_FRMERR_W < INT_EVENT0_IMASK_SPEC , 1 > { INT_EVENT0_IMASK_FRMERR_W :: new (self) } # [doc = "Bit 2 - Enable UART Parity Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_parerr (& mut self) -> INT_EVENT0_IMASK_PARERR_W < INT_EVENT0_IMASK_SPEC , 2 > { INT_EVENT0_IMASK_PARERR_W :: new (self) } # [doc = "Bit 3 - Enable UART Break Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_brkerr (& mut self) -> INT_EVENT0_IMASK_BRKERR_W < INT_EVENT0_IMASK_SPEC , 3 > { INT_EVENT0_IMASK_BRKERR_W :: new (self) } # [doc = "Bit 4 - Enable UART Receive Overrun Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_ovrerr (& mut self) -> INT_EVENT0_IMASK_OVRERR_W < INT_EVENT0_IMASK_SPEC , 4 > { INT_EVENT0_IMASK_OVRERR_W :: new (self) } # [doc = "Bit 5 - Enable Negative Edge on UARTxRXD Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_rxne (& mut self) -> INT_EVENT0_IMASK_RXNE_W < INT_EVENT0_IMASK_SPEC , 5 > { INT_EVENT0_IMASK_RXNE_W :: new (self) } # [doc = "Bit 6 - Enable Positive Edge on UARTxRXD Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_rxpe (& mut self) -> INT_EVENT0_IMASK_RXPE_W < INT_EVENT0_IMASK_SPEC , 6 > { INT_EVENT0_IMASK_RXPE_W :: new (self) } # [doc = "Bit 7 - Enable LIN Capture 0 / Match Interrupt ."] # [inline (always)] # [must_use] pub fn int_event0_imask_linc0 (& mut self) -> INT_EVENT0_IMASK_LINC0_W < INT_EVENT0_IMASK_SPEC , 7 > { INT_EVENT0_IMASK_LINC0_W :: new (self) } # [doc = "Bit 8 - Enable LIN Capture 1 Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_linc1 (& mut self) -> INT_EVENT0_IMASK_LINC1_W < INT_EVENT0_IMASK_SPEC , 8 > { INT_EVENT0_IMASK_LINC1_W :: new (self) } # [doc = "Bit 9 - Enable LIN Hardware Counter Overflow Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_linovf (& mut self) -> INT_EVENT0_IMASK_LINOVF_W < INT_EVENT0_IMASK_SPEC , 9 > { INT_EVENT0_IMASK_LINOVF_W :: new (self) } # [doc = "Bit 10 - Enable UART Receive Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_rxint (& mut self) -> INT_EVENT0_IMASK_RXINT_W <'_,  INT_EVENT0_IMASK_SPEC , 10 > { INT_EVENT0_IMASK_RXINT_W :: new (self) } # [doc = "Bit 11 - Enable UART Transmit Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_txint (& mut self) -> INT_EVENT0_IMASK_TXINT_W < INT_EVENT0_IMASK_SPEC , 11 > { INT_EVENT0_IMASK_TXINT_W :: new (self) } # [doc = "Bit 12 - Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] # [inline (always)] # [must_use] pub fn int_event0_imask_eot (& mut self) -> INT_EVENT0_IMASK_EOT_W < INT_EVENT0_IMASK_SPEC , 12 > { INT_EVENT0_IMASK_EOT_W :: new (self) } # [doc = "Bit 13 - Enable Address Match Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_addr_match (& mut self) -> INT_EVENT0_IMASK_ADDR_MATCH_W < INT_EVENT0_IMASK_SPEC , 13 > { INT_EVENT0_IMASK_ADDR_MATCH_W :: new (self) } # [doc = "Bit 14 - Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] # [inline (always)] # [must_use] pub fn int_event0_imask_cts (& mut self) -> INT_EVENT0_IMASK_CTS_W < INT_EVENT0_IMASK_SPEC , 14 > { INT_EVENT0_IMASK_CTS_W :: new (self) } # [doc = "Bit 15 - Enable DMA Done on RX Event Channel"] # [inline (always)] # [must_use] pub fn int_event0_imask_dma_done_rx (& mut self) -> INT_EVENT0_IMASK_DMA_DONE_RX_W < INT_EVENT0_IMASK_SPEC , 15 > { INT_EVENT0_IMASK_DMA_DONE_RX_W :: new (self) } # [doc = "Bit 16 - Enable DMA Done on TX Event Channel"] # [inline (always)] # [must_use] pub fn int_event0_imask_dma_done_tx (& mut self) -> INT_EVENT0_IMASK_DMA_DONE_TX_W < INT_EVENT0_IMASK_SPEC , 16 > { INT_EVENT0_IMASK_DMA_DONE_TX_W :: new (self) } # [doc = "Bit 17 - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] # [inline (always)] # [must_use] pub fn int_event0_imask_nerr (& mut self) -> INT_EVENT0_IMASK_NERR_W < INT_EVENT0_IMASK_SPEC , 17 > { INT_EVENT0_IMASK_NERR_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Interrupt mask\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_event0_imask::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_event0_imask::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct INT_EVENT0_IMASK_SPEC ; impl crate :: RegisterSpec for INT_EVENT0_IMASK_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`int_event0_imask::R`](R) reader structure"] impl crate :: Readable for INT_EVENT0_IMASK_SPEC { } # [doc = "`write(|w| ..)` method takes [`int_event0_imask::W`](W) writer structure"] impl crate :: Writable for INT_EVENT0_IMASK_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets INT_EVENT0_IMASK to value 0"] impl crate :: Resettable for INT_EVENT0_IMASK_SPEC { const RESET_VALUE : Self :: Ux = 0 ; }
[INFO] [stdout]   |                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                +++
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing
[INFO] [stdout]  --> src/uart0/int_event0_imask.rs:1:43102
[INFO] [stdout]   |
[INFO] [stdout] 1 | ...imask_txint (& mut self) -> INT_EVENT0_IMASK_TXINT_W < INT_EVENT0_IMASK_SPEC , 11 > { INT_EVENT0_IMASK_TXINT_W :: new (self) } # [...
[INFO] [stdout]   |                 ^^^^^^^^^^     ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here
[INFO] [stdout]   |                 |
[INFO] [stdout]   |                 the lifetime is elided here
[INFO] [stdout]   |
[INFO] [stdout]   = help: the same lifetime is referred to in inconsistent ways, making the signature confusing
[INFO] [stdout] help: use `'_` for type paths
[INFO] [stdout]   |
[INFO] [stdout] 1 | # [doc = "Register `INT_EVENT0_IMASK` reader"] pub type R = crate :: R < INT_EVENT0_IMASK_SPEC > ; # [doc = "Register `INT_EVENT0_IMASK` writer"] pub type W = crate :: W < INT_EVENT0_IMASK_SPEC > ; # [doc = "Field `INT_EVENT0_IMASK_RTOUT` reader - Enable UARTOUT Receive Time-Out Interrupt."] pub type INT_EVENT0_IMASK_RTOUT_R = crate :: BitReader < INT_EVENT0_IMASK_RTOUT_A > ; # [doc = "Enable UARTOUT Receive Time-Out Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_RTOUT_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_RTOUT_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_RTOUT_SET = 1 , } impl From < INT_EVENT0_IMASK_RTOUT_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_RTOUT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_RTOUT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_RTOUT_A { match self . bits { false => INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_CLR , true => INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_rtout_clr (& self) -> bool { * self == INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_rtout_set (& self) -> bool { * self == INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_SET } } # [doc = "Field `INT_EVENT0_IMASK_RTOUT` writer - Enable UARTOUT Receive Time-Out Interrupt."] pub type INT_EVENT0_IMASK_RTOUT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_RTOUT_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_RTOUT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_rtout_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_rtout_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_SET) } } # [doc = "Field `INT_EVENT0_IMASK_FRMERR` reader - Enable UART Framing Error Interrupt."] pub type INT_EVENT0_IMASK_FRMERR_R = crate :: BitReader < INT_EVENT0_IMASK_FRMERR_A > ; # [doc = "Enable UART Framing Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_FRMERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_FRMERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_FRMERR_SET = 1 , } impl From < INT_EVENT0_IMASK_FRMERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_FRMERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_FRMERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_FRMERR_A { match self . bits { false => INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_CLR , true => INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_frmerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_frmerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_FRMERR` writer - Enable UART Framing Error Interrupt."] pub type INT_EVENT0_IMASK_FRMERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_FRMERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_FRMERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_frmerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_frmerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_SET) } } # [doc = "Field `INT_EVENT0_IMASK_PARERR` reader - Enable UART Parity Error Interrupt."] pub type INT_EVENT0_IMASK_PARERR_R = crate :: BitReader < INT_EVENT0_IMASK_PARERR_A > ; # [doc = "Enable UART Parity Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_PARERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_PARERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_PARERR_SET = 1 , } impl From < INT_EVENT0_IMASK_PARERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_PARERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_PARERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_PARERR_A { match self . bits { false => INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_CLR , true => INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_parerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_parerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_PARERR` writer - Enable UART Parity Error Interrupt."] pub type INT_EVENT0_IMASK_PARERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_PARERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_PARERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_parerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_parerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_SET) } } # [doc = "Field `INT_EVENT0_IMASK_BRKERR` reader - Enable UART Break Error Interrupt."] pub type INT_EVENT0_IMASK_BRKERR_R = crate :: BitReader < INT_EVENT0_IMASK_BRKERR_A > ; # [doc = "Enable UART Break Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_BRKERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_BRKERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_BRKERR_SET = 1 , } impl From < INT_EVENT0_IMASK_BRKERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_BRKERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_BRKERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_BRKERR_A { match self . bits { false => INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_CLR , true => INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_brkerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_brkerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_BRKERR` writer - Enable UART Break Error Interrupt."] pub type INT_EVENT0_IMASK_BRKERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_BRKERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_BRKERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_brkerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_brkerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_SET) } } # [doc = "Field `INT_EVENT0_IMASK_OVRERR` reader - Enable UART Receive Overrun Error Interrupt."] pub type INT_EVENT0_IMASK_OVRERR_R = crate :: BitReader < INT_EVENT0_IMASK_OVRERR_A > ; # [doc = "Enable UART Receive Overrun Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_OVRERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_OVRERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_OVRERR_SET = 1 , } impl From < INT_EVENT0_IMASK_OVRERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_OVRERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_OVRERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_OVRERR_A { match self . bits { false => INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_CLR , true => INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_ovrerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_ovrerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_OVRERR` writer - Enable UART Receive Overrun Error Interrupt."] pub type INT_EVENT0_IMASK_OVRERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_OVRERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_OVRERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_ovrerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_ovrerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_SET) } } # [doc = "Field `INT_EVENT0_IMASK_RXNE` reader - Enable Negative Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_IMASK_RXNE_R = crate :: BitReader < INT_EVENT0_IMASK_RXNE_A > ; # [doc = "Enable Negative Edge on UARTxRXD Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_RXNE_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_RXNE_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_RXNE_SET = 1 , } impl From < INT_EVENT0_IMASK_RXNE_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_RXNE_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_RXNE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_RXNE_A { match self . bits { false => INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_CLR , true => INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_rxne_clr (& self) -> bool { * self == INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_rxne_set (& self) -> bool { * self == INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_SET } } # [doc = "Field `INT_EVENT0_IMASK_RXNE` writer - Enable Negative Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_IMASK_RXNE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_RXNE_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_RXNE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_rxne_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_rxne_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_SET) } } # [doc = "Field `INT_EVENT0_IMASK_RXPE` reader - Enable Positive Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_IMASK_RXPE_R = crate :: BitReader < INT_EVENT0_IMASK_RXPE_A > ; # [doc = "Enable Positive Edge on UARTxRXD Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_RXPE_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_RXPE_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_RXPE_SET = 1 , } impl From < INT_EVENT0_IMASK_RXPE_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_RXPE_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_RXPE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_RXPE_A { match self . bits { false => INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_CLR , true => INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_rxpe_clr (& self) -> bool { * self == INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_rxpe_set (& self) -> bool { * self == INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_SET } } # [doc = "Field `INT_EVENT0_IMASK_RXPE` writer - Enable Positive Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_IMASK_RXPE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_RXPE_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_RXPE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_rxpe_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_rxpe_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_SET) } } # [doc = "Field `INT_EVENT0_IMASK_LINC0` reader - Enable LIN Capture 0 / Match Interrupt ."] pub type INT_EVENT0_IMASK_LINC0_R = crate :: BitReader < INT_EVENT0_IMASK_LINC0_A > ; # [doc = "Enable LIN Capture 0 / Match Interrupt .\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_LINC0_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_LINC0_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_LINC0_SET = 1 , } impl From < INT_EVENT0_IMASK_LINC0_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_LINC0_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_LINC0_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_LINC0_A { match self . bits { false => INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_CLR , true => INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_linc0_clr (& self) -> bool { * self == INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_linc0_set (& self) -> bool { * self == INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_SET } } # [doc = "Field `INT_EVENT0_IMASK_LINC0` writer - Enable LIN Capture 0 / Match Interrupt ."] pub type INT_EVENT0_IMASK_LINC0_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_LINC0_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_LINC0_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_linc0_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_linc0_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_SET) } } # [doc = "Field `INT_EVENT0_IMASK_LINC1` reader - Enable LIN Capture 1 Interrupt."] pub type INT_EVENT0_IMASK_LINC1_R = crate :: BitReader < INT_EVENT0_IMASK_LINC1_A > ; # [doc = "Enable LIN Capture 1 Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_LINC1_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_LINC1_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_LINC1_SET = 1 , } impl From < INT_EVENT0_IMASK_LINC1_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_LINC1_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_LINC1_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_LINC1_A { match self . bits { false => INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_CLR , true => INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_linc1_clr (& self) -> bool { * self == INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_linc1_set (& self) -> bool { * self == INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_SET } } # [doc = "Field `INT_EVENT0_IMASK_LINC1` writer - Enable LIN Capture 1 Interrupt."] pub type INT_EVENT0_IMASK_LINC1_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_LINC1_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_LINC1_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_linc1_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_linc1_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_SET) } } # [doc = "Field `INT_EVENT0_IMASK_LINOVF` reader - Enable LIN Hardware Counter Overflow Interrupt."] pub type INT_EVENT0_IMASK_LINOVF_R = crate :: BitReader < INT_EVENT0_IMASK_LINOVF_A > ; # [doc = "Enable LIN Hardware Counter Overflow Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_LINOVF_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_LINOVF_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_LINOVF_SET = 1 , } impl From < INT_EVENT0_IMASK_LINOVF_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_LINOVF_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_LINOVF_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_LINOVF_A { match self . bits { false => INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_CLR , true => INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_linovf_clr (& self) -> bool { * self == INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_linovf_set (& self) -> bool { * self == INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_SET } } # [doc = "Field `INT_EVENT0_IMASK_LINOVF` writer - Enable LIN Hardware Counter Overflow Interrupt."] pub type INT_EVENT0_IMASK_LINOVF_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_LINOVF_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_LINOVF_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_linovf_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_linovf_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_SET) } } # [doc = "Field `INT_EVENT0_IMASK_RXINT` reader - Enable UART Receive Interrupt."] pub type INT_EVENT0_IMASK_RXINT_R = crate :: BitReader < INT_EVENT0_IMASK_RXINT_A > ; # [doc = "Enable UART Receive Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_RXINT_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_RXINT_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_RXINT_SET = 1 , } impl From < INT_EVENT0_IMASK_RXINT_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_RXINT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_RXINT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_RXINT_A { match self . bits { false => INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_CLR , true => INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_rxint_clr (& self) -> bool { * self == INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_rxint_set (& self) -> bool { * self == INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_SET } } # [doc = "Field `INT_EVENT0_IMASK_RXINT` writer - Enable UART Receive Interrupt."] pub type INT_EVENT0_IMASK_RXINT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_RXINT_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_RXINT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_rxint_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_rxint_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_SET) } } # [doc = "Field `INT_EVENT0_IMASK_TXINT` reader - Enable UART Transmit Interrupt."] pub type INT_EVENT0_IMASK_TXINT_R = crate :: BitReader < INT_EVENT0_IMASK_TXINT_A > ; # [doc = "Enable UART Transmit Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_TXINT_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_TXINT_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_TXINT_SET = 1 , } impl From < INT_EVENT0_IMASK_TXINT_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_TXINT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_TXINT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_TXINT_A { match self . bits { false => INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_CLR , true => INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_txint_clr (& self) -> bool { * self == INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_txint_set (& self) -> bool { * self == INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_SET } } # [doc = "Field `INT_EVENT0_IMASK_TXINT` writer - Enable UART Transmit Interrupt."] pub type INT_EVENT0_IMASK_TXINT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_TXINT_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_TXINT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_txint_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_txint_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_SET) } } # [doc = "Field `INT_EVENT0_IMASK_EOT` reader - Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] pub type INT_EVENT0_IMASK_EOT_R = crate :: BitReader < INT_EVENT0_IMASK_EOT_A > ; # [doc = "Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_EOT_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_EOT_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_EOT_SET = 1 , } impl From < INT_EVENT0_IMASK_EOT_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_EOT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_EOT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_EOT_A { match self . bits { false => INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_CLR , true => INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_eot_clr (& self) -> bool { * self == INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_eot_set (& self) -> bool { * self == INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_SET } } # [doc = "Field `INT_EVENT0_IMASK_EOT` writer - Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] pub type INT_EVENT0_IMASK_EOT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_EOT_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_EOT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_eot_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_eot_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_SET) } } # [doc = "Field `INT_EVENT0_IMASK_ADDR_MATCH` reader - Enable Address Match Interrupt."] pub type INT_EVENT0_IMASK_ADDR_MATCH_R = crate :: BitReader < INT_EVENT0_IMASK_ADDR_MATCH_A > ; # [doc = "Enable Address Match Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_ADDR_MATCH_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_ADDR_MATCH_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_ADDR_MATCH_SET = 1 , } impl From < INT_EVENT0_IMASK_ADDR_MATCH_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_ADDR_MATCH_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_ADDR_MATCH_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_ADDR_MATCH_A { match self . bits { false => INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_CLR , true => INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_addr_match_clr (& self) -> bool { * self == INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_addr_match_set (& self) -> bool { * self == INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_SET } } # [doc = "Field `INT_EVENT0_IMASK_ADDR_MATCH` writer - Enable Address Match Interrupt."] pub type INT_EVENT0_IMASK_ADDR_MATCH_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_ADDR_MATCH_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_ADDR_MATCH_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_addr_match_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_addr_match_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_SET) } } # [doc = "Field `INT_EVENT0_IMASK_CTS` reader - Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] pub type INT_EVENT0_IMASK_CTS_R = crate :: BitReader < INT_EVENT0_IMASK_CTS_A > ; # [doc = "Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_CTS_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_CTS_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_CTS_SET = 1 , } impl From < INT_EVENT0_IMASK_CTS_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_CTS_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_CTS_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_CTS_A { match self . bits { false => INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_CLR , true => INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_cts_clr (& self) -> bool { * self == INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_cts_set (& self) -> bool { * self == INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_SET } } # [doc = "Field `INT_EVENT0_IMASK_CTS` writer - Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] pub type INT_EVENT0_IMASK_CTS_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_CTS_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_CTS_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_cts_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_cts_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DMA_DONE_RX` reader - Enable DMA Done on RX Event Channel"] pub type INT_EVENT0_IMASK_DMA_DONE_RX_R = crate :: BitReader < INT_EVENT0_IMASK_DMA_DONE_RX_A > ; # [doc = "Enable DMA Done on RX Event Channel\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DMA_DONE_RX_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DMA_DONE_RX_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DMA_DONE_RX_SET = 1 , } impl From < INT_EVENT0_IMASK_DMA_DONE_RX_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DMA_DONE_RX_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DMA_DONE_RX_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DMA_DONE_RX_A { match self . bits { false => INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_CLR , true => INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dma_done_rx_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dma_done_rx_set (& self) -> bool { * self == INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_SET } } # [doc = "Field `INT_EVENT0_IMASK_DMA_DONE_RX` writer - Enable DMA Done on RX Event Channel"] pub type INT_EVENT0_IMASK_DMA_DONE_RX_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DMA_DONE_RX_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DMA_DONE_RX_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dma_done_rx_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dma_done_rx_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DMA_DONE_TX` reader - Enable DMA Done on TX Event Channel"] pub type INT_EVENT0_IMASK_DMA_DONE_TX_R = crate :: BitReader < INT_EVENT0_IMASK_DMA_DONE_TX_A > ; # [doc = "Enable DMA Done on TX Event Channel\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DMA_DONE_TX_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DMA_DONE_TX_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DMA_DONE_TX_SET = 1 , } impl From < INT_EVENT0_IMASK_DMA_DONE_TX_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DMA_DONE_TX_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DMA_DONE_TX_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DMA_DONE_TX_A { match self . bits { false => INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_CLR , true => INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dma_done_tx_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dma_done_tx_set (& self) -> bool { * self == INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_SET } } # [doc = "Field `INT_EVENT0_IMASK_DMA_DONE_TX` writer - Enable DMA Done on TX Event Channel"] pub type INT_EVENT0_IMASK_DMA_DONE_TX_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DMA_DONE_TX_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DMA_DONE_TX_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dma_done_tx_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dma_done_tx_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_SET) } } # [doc = "Field `INT_EVENT0_IMASK_NERR` reader - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] pub type INT_EVENT0_IMASK_NERR_R = crate :: BitReader < INT_EVENT0_IMASK_NERR_A > ; # [doc = "Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_NERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_NERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_NERR_SET = 1 , } impl From < INT_EVENT0_IMASK_NERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_NERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_NERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_NERR_A { match self . bits { false => INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_CLR , true => INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_nerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_nerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_NERR` writer - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] pub type INT_EVENT0_IMASK_NERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_NERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_NERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_nerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_nerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_SET) } } impl R { # [doc = "Bit 0 - Enable UARTOUT Receive Time-Out Interrupt."] # [inline (always)] pub fn int_event0_imask_rtout (& self) -> INT_EVENT0_IMASK_RTOUT_R { INT_EVENT0_IMASK_RTOUT_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - Enable UART Framing Error Interrupt."] # [inline (always)] pub fn int_event0_imask_frmerr (& self) -> INT_EVENT0_IMASK_FRMERR_R { INT_EVENT0_IMASK_FRMERR_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - Enable UART Parity Error Interrupt."] # [inline (always)] pub fn int_event0_imask_parerr (& self) -> INT_EVENT0_IMASK_PARERR_R { INT_EVENT0_IMASK_PARERR_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - Enable UART Break Error Interrupt."] # [inline (always)] pub fn int_event0_imask_brkerr (& self) -> INT_EVENT0_IMASK_BRKERR_R { INT_EVENT0_IMASK_BRKERR_R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - Enable UART Receive Overrun Error Interrupt."] # [inline (always)] pub fn int_event0_imask_ovrerr (& self) -> INT_EVENT0_IMASK_OVRERR_R { INT_EVENT0_IMASK_OVRERR_R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - Enable Negative Edge on UARTxRXD Interrupt."] # [inline (always)] pub fn int_event0_imask_rxne (& self) -> INT_EVENT0_IMASK_RXNE_R { INT_EVENT0_IMASK_RXNE_R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - Enable Positive Edge on UARTxRXD Interrupt."] # [inline (always)] pub fn int_event0_imask_rxpe (& self) -> INT_EVENT0_IMASK_RXPE_R { INT_EVENT0_IMASK_RXPE_R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - Enable LIN Capture 0 / Match Interrupt ."] # [inline (always)] pub fn int_event0_imask_linc0 (& self) -> INT_EVENT0_IMASK_LINC0_R { INT_EVENT0_IMASK_LINC0_R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - Enable LIN Capture 1 Interrupt."] # [inline (always)] pub fn int_event0_imask_linc1 (& self) -> INT_EVENT0_IMASK_LINC1_R { INT_EVENT0_IMASK_LINC1_R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - Enable LIN Hardware Counter Overflow Interrupt."] # [inline (always)] pub fn int_event0_imask_linovf (& self) -> INT_EVENT0_IMASK_LINOVF_R { INT_EVENT0_IMASK_LINOVF_R :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - Enable UART Receive Interrupt."] # [inline (always)] pub fn int_event0_imask_rxint (& self) -> INT_EVENT0_IMASK_RXINT_R { INT_EVENT0_IMASK_RXINT_R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - Enable UART Transmit Interrupt."] # [inline (always)] pub fn int_event0_imask_txint (& self) -> INT_EVENT0_IMASK_TXINT_R { INT_EVENT0_IMASK_TXINT_R :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] # [inline (always)] pub fn int_event0_imask_eot (& self) -> INT_EVENT0_IMASK_EOT_R { INT_EVENT0_IMASK_EOT_R :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - Enable Address Match Interrupt."] # [inline (always)] pub fn int_event0_imask_addr_match (& self) -> INT_EVENT0_IMASK_ADDR_MATCH_R { INT_EVENT0_IMASK_ADDR_MATCH_R :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 14 - Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] # [inline (always)] pub fn int_event0_imask_cts (& self) -> INT_EVENT0_IMASK_CTS_R { INT_EVENT0_IMASK_CTS_R :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - Enable DMA Done on RX Event Channel"] # [inline (always)] pub fn int_event0_imask_dma_done_rx (& self) -> INT_EVENT0_IMASK_DMA_DONE_RX_R { INT_EVENT0_IMASK_DMA_DONE_RX_R :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bit 16 - Enable DMA Done on TX Event Channel"] # [inline (always)] pub fn int_event0_imask_dma_done_tx (& self) -> INT_EVENT0_IMASK_DMA_DONE_TX_R { INT_EVENT0_IMASK_DMA_DONE_TX_R :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] # [inline (always)] pub fn int_event0_imask_nerr (& self) -> INT_EVENT0_IMASK_NERR_R { INT_EVENT0_IMASK_NERR_R :: new (((self . bits >> 17) & 1) != 0) } } impl W { # [doc = "Bit 0 - Enable UARTOUT Receive Time-Out Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_rtout (& mut self) -> INT_EVENT0_IMASK_RTOUT_W < INT_EVENT0_IMASK_SPEC , 0 > { INT_EVENT0_IMASK_RTOUT_W :: new (self) } # [doc = "Bit 1 - Enable UART Framing Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_frmerr (& mut self) -> INT_EVENT0_IMASK_FRMERR_W < INT_EVENT0_IMASK_SPEC , 1 > { INT_EVENT0_IMASK_FRMERR_W :: new (self) } # [doc = "Bit 2 - Enable UART Parity Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_parerr (& mut self) -> INT_EVENT0_IMASK_PARERR_W < INT_EVENT0_IMASK_SPEC , 2 > { INT_EVENT0_IMASK_PARERR_W :: new (self) } # [doc = "Bit 3 - Enable UART Break Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_brkerr (& mut self) -> INT_EVENT0_IMASK_BRKERR_W < INT_EVENT0_IMASK_SPEC , 3 > { INT_EVENT0_IMASK_BRKERR_W :: new (self) } # [doc = "Bit 4 - Enable UART Receive Overrun Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_ovrerr (& mut self) -> INT_EVENT0_IMASK_OVRERR_W < INT_EVENT0_IMASK_SPEC , 4 > { INT_EVENT0_IMASK_OVRERR_W :: new (self) } # [doc = "Bit 5 - Enable Negative Edge on UARTxRXD Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_rxne (& mut self) -> INT_EVENT0_IMASK_RXNE_W < INT_EVENT0_IMASK_SPEC , 5 > { INT_EVENT0_IMASK_RXNE_W :: new (self) } # [doc = "Bit 6 - Enable Positive Edge on UARTxRXD Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_rxpe (& mut self) -> INT_EVENT0_IMASK_RXPE_W < INT_EVENT0_IMASK_SPEC , 6 > { INT_EVENT0_IMASK_RXPE_W :: new (self) } # [doc = "Bit 7 - Enable LIN Capture 0 / Match Interrupt ."] # [inline (always)] # [must_use] pub fn int_event0_imask_linc0 (& mut self) -> INT_EVENT0_IMASK_LINC0_W < INT_EVENT0_IMASK_SPEC , 7 > { INT_EVENT0_IMASK_LINC0_W :: new (self) } # [doc = "Bit 8 - Enable LIN Capture 1 Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_linc1 (& mut self) -> INT_EVENT0_IMASK_LINC1_W < INT_EVENT0_IMASK_SPEC , 8 > { INT_EVENT0_IMASK_LINC1_W :: new (self) } # [doc = "Bit 9 - Enable LIN Hardware Counter Overflow Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_linovf (& mut self) -> INT_EVENT0_IMASK_LINOVF_W < INT_EVENT0_IMASK_SPEC , 9 > { INT_EVENT0_IMASK_LINOVF_W :: new (self) } # [doc = "Bit 10 - Enable UART Receive Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_rxint (& mut self) -> INT_EVENT0_IMASK_RXINT_W < INT_EVENT0_IMASK_SPEC , 10 > { INT_EVENT0_IMASK_RXINT_W :: new (self) } # [doc = "Bit 11 - Enable UART Transmit Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_txint (& mut self) -> INT_EVENT0_IMASK_TXINT_W <'_,  INT_EVENT0_IMASK_SPEC , 11 > { INT_EVENT0_IMASK_TXINT_W :: new (self) } # [doc = "Bit 12 - Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] # [inline (always)] # [must_use] pub fn int_event0_imask_eot (& mut self) -> INT_EVENT0_IMASK_EOT_W < INT_EVENT0_IMASK_SPEC , 12 > { INT_EVENT0_IMASK_EOT_W :: new (self) } # [doc = "Bit 13 - Enable Address Match Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_addr_match (& mut self) -> INT_EVENT0_IMASK_ADDR_MATCH_W < INT_EVENT0_IMASK_SPEC , 13 > { INT_EVENT0_IMASK_ADDR_MATCH_W :: new (self) } # [doc = "Bit 14 - Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] # [inline (always)] # [must_use] pub fn int_event0_imask_cts (& mut self) -> INT_EVENT0_IMASK_CTS_W < INT_EVENT0_IMASK_SPEC , 14 > { INT_EVENT0_IMASK_CTS_W :: new (self) } # [doc = "Bit 15 - Enable DMA Done on RX Event Channel"] # [inline (always)] # [must_use] pub fn int_event0_imask_dma_done_rx (& mut self) -> INT_EVENT0_IMASK_DMA_DONE_RX_W < INT_EVENT0_IMASK_SPEC , 15 > { INT_EVENT0_IMASK_DMA_DONE_RX_W :: new (self) } # [doc = "Bit 16 - Enable DMA Done on TX Event Channel"] # [inline (always)] # [must_use] pub fn int_event0_imask_dma_done_tx (& mut self) -> INT_EVENT0_IMASK_DMA_DONE_TX_W < INT_EVENT0_IMASK_SPEC , 16 > { INT_EVENT0_IMASK_DMA_DONE_TX_W :: new (self) } # [doc = "Bit 17 - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] # [inline (always)] # [must_use] pub fn int_event0_imask_nerr (& mut self) -> INT_EVENT0_IMASK_NERR_W < INT_EVENT0_IMASK_SPEC , 17 > { INT_EVENT0_IMASK_NERR_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Interrupt mask\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_event0_imask::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_event0_imask::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct INT_EVENT0_IMASK_SPEC ; impl crate :: RegisterSpec for INT_EVENT0_IMASK_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`int_event0_imask::R`](R) reader structure"] impl crate :: Readable for INT_EVENT0_IMASK_SPEC { } # [doc = "`write(|w| ..)` method takes [`int_event0_imask::W`](W) writer structure"] impl crate :: Writable for INT_EVENT0_IMASK_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets INT_EVENT0_IMASK to value 0"] impl crate :: Resettable for INT_EVENT0_IMASK_SPEC { const RESET_VALUE : Self :: Ux = 0 ; }
[INFO] [stdout]   |                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                       +++
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing
[INFO] [stdout]  --> src/uart0/int_event0_imask.rs:1:43482
[INFO] [stdout]   |
[INFO] [stdout] 1 | ...t0_imask_eot (& mut self) -> INT_EVENT0_IMASK_EOT_W < INT_EVENT0_IMASK_SPEC , 12 > { INT_EVENT0_IMASK_EOT_W :: new (self) } # [doc...
[INFO] [stdout]   |                  ^^^^^^^^^^     ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here
[INFO] [stdout]   |                  |
[INFO] [stdout]   |                  the lifetime is elided here
[INFO] [stdout]   |
[INFO] [stdout]   = help: the same lifetime is referred to in inconsistent ways, making the signature confusing
[INFO] [stdout] help: use `'_` for type paths
[INFO] [stdout]   |
[INFO] [stdout] 1 | # [doc = "Register `INT_EVENT0_IMASK` reader"] pub type R = crate :: R < INT_EVENT0_IMASK_SPEC > ; # [doc = "Register `INT_EVENT0_IMASK` writer"] pub type W = crate :: W < INT_EVENT0_IMASK_SPEC > ; # [doc = "Field `INT_EVENT0_IMASK_RTOUT` reader - Enable UARTOUT Receive Time-Out Interrupt."] pub type INT_EVENT0_IMASK_RTOUT_R = crate :: BitReader < INT_EVENT0_IMASK_RTOUT_A > ; # [doc = "Enable UARTOUT Receive Time-Out Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_RTOUT_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_RTOUT_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_RTOUT_SET = 1 , } impl From < INT_EVENT0_IMASK_RTOUT_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_RTOUT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_RTOUT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_RTOUT_A { match self . bits { false => INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_CLR , true => INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_rtout_clr (& self) -> bool { * self == INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_rtout_set (& self) -> bool { * self == INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_SET } } # [doc = "Field `INT_EVENT0_IMASK_RTOUT` writer - Enable UARTOUT Receive Time-Out Interrupt."] pub type INT_EVENT0_IMASK_RTOUT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_RTOUT_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_RTOUT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_rtout_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_rtout_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_SET) } } # [doc = "Field `INT_EVENT0_IMASK_FRMERR` reader - Enable UART Framing Error Interrupt."] pub type INT_EVENT0_IMASK_FRMERR_R = crate :: BitReader < INT_EVENT0_IMASK_FRMERR_A > ; # [doc = "Enable UART Framing Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_FRMERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_FRMERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_FRMERR_SET = 1 , } impl From < INT_EVENT0_IMASK_FRMERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_FRMERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_FRMERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_FRMERR_A { match self . bits { false => INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_CLR , true => INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_frmerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_frmerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_FRMERR` writer - Enable UART Framing Error Interrupt."] pub type INT_EVENT0_IMASK_FRMERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_FRMERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_FRMERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_frmerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_frmerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_SET) } } # [doc = "Field `INT_EVENT0_IMASK_PARERR` reader - Enable UART Parity Error Interrupt."] pub type INT_EVENT0_IMASK_PARERR_R = crate :: BitReader < INT_EVENT0_IMASK_PARERR_A > ; # [doc = "Enable UART Parity Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_PARERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_PARERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_PARERR_SET = 1 , } impl From < INT_EVENT0_IMASK_PARERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_PARERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_PARERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_PARERR_A { match self . bits { false => INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_CLR , true => INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_parerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_parerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_PARERR` writer - Enable UART Parity Error Interrupt."] pub type INT_EVENT0_IMASK_PARERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_PARERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_PARERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_parerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_parerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_SET) } } # [doc = "Field `INT_EVENT0_IMASK_BRKERR` reader - Enable UART Break Error Interrupt."] pub type INT_EVENT0_IMASK_BRKERR_R = crate :: BitReader < INT_EVENT0_IMASK_BRKERR_A > ; # [doc = "Enable UART Break Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_BRKERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_BRKERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_BRKERR_SET = 1 , } impl From < INT_EVENT0_IMASK_BRKERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_BRKERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_BRKERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_BRKERR_A { match self . bits { false => INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_CLR , true => INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_brkerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_brkerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_BRKERR` writer - Enable UART Break Error Interrupt."] pub type INT_EVENT0_IMASK_BRKERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_BRKERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_BRKERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_brkerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_brkerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_SET) } } # [doc = "Field `INT_EVENT0_IMASK_OVRERR` reader - Enable UART Receive Overrun Error Interrupt."] pub type INT_EVENT0_IMASK_OVRERR_R = crate :: BitReader < INT_EVENT0_IMASK_OVRERR_A > ; # [doc = "Enable UART Receive Overrun Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_OVRERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_OVRERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_OVRERR_SET = 1 , } impl From < INT_EVENT0_IMASK_OVRERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_OVRERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_OVRERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_OVRERR_A { match self . bits { false => INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_CLR , true => INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_ovrerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_ovrerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_OVRERR` writer - Enable UART Receive Overrun Error Interrupt."] pub type INT_EVENT0_IMASK_OVRERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_OVRERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_OVRERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_ovrerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_ovrerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_SET) } } # [doc = "Field `INT_EVENT0_IMASK_RXNE` reader - Enable Negative Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_IMASK_RXNE_R = crate :: BitReader < INT_EVENT0_IMASK_RXNE_A > ; # [doc = "Enable Negative Edge on UARTxRXD Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_RXNE_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_RXNE_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_RXNE_SET = 1 , } impl From < INT_EVENT0_IMASK_RXNE_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_RXNE_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_RXNE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_RXNE_A { match self . bits { false => INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_CLR , true => INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_rxne_clr (& self) -> bool { * self == INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_rxne_set (& self) -> bool { * self == INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_SET } } # [doc = "Field `INT_EVENT0_IMASK_RXNE` writer - Enable Negative Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_IMASK_RXNE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_RXNE_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_RXNE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_rxne_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_rxne_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_SET) } } # [doc = "Field `INT_EVENT0_IMASK_RXPE` reader - Enable Positive Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_IMASK_RXPE_R = crate :: BitReader < INT_EVENT0_IMASK_RXPE_A > ; # [doc = "Enable Positive Edge on UARTxRXD Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_RXPE_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_RXPE_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_RXPE_SET = 1 , } impl From < INT_EVENT0_IMASK_RXPE_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_RXPE_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_RXPE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_RXPE_A { match self . bits { false => INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_CLR , true => INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_rxpe_clr (& self) -> bool { * self == INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_rxpe_set (& self) -> bool { * self == INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_SET } } # [doc = "Field `INT_EVENT0_IMASK_RXPE` writer - Enable Positive Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_IMASK_RXPE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_RXPE_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_RXPE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_rxpe_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_rxpe_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_SET) } } # [doc = "Field `INT_EVENT0_IMASK_LINC0` reader - Enable LIN Capture 0 / Match Interrupt ."] pub type INT_EVENT0_IMASK_LINC0_R = crate :: BitReader < INT_EVENT0_IMASK_LINC0_A > ; # [doc = "Enable LIN Capture 0 / Match Interrupt .\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_LINC0_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_LINC0_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_LINC0_SET = 1 , } impl From < INT_EVENT0_IMASK_LINC0_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_LINC0_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_LINC0_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_LINC0_A { match self . bits { false => INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_CLR , true => INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_linc0_clr (& self) -> bool { * self == INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_linc0_set (& self) -> bool { * self == INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_SET } } # [doc = "Field `INT_EVENT0_IMASK_LINC0` writer - Enable LIN Capture 0 / Match Interrupt ."] pub type INT_EVENT0_IMASK_LINC0_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_LINC0_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_LINC0_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_linc0_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_linc0_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_SET) } } # [doc = "Field `INT_EVENT0_IMASK_LINC1` reader - Enable LIN Capture 1 Interrupt."] pub type INT_EVENT0_IMASK_LINC1_R = crate :: BitReader < INT_EVENT0_IMASK_LINC1_A > ; # [doc = "Enable LIN Capture 1 Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_LINC1_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_LINC1_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_LINC1_SET = 1 , } impl From < INT_EVENT0_IMASK_LINC1_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_LINC1_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_LINC1_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_LINC1_A { match self . bits { false => INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_CLR , true => INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_linc1_clr (& self) -> bool { * self == INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_linc1_set (& self) -> bool { * self == INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_SET } } # [doc = "Field `INT_EVENT0_IMASK_LINC1` writer - Enable LIN Capture 1 Interrupt."] pub type INT_EVENT0_IMASK_LINC1_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_LINC1_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_LINC1_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_linc1_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_linc1_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_SET) } } # [doc = "Field `INT_EVENT0_IMASK_LINOVF` reader - Enable LIN Hardware Counter Overflow Interrupt."] pub type INT_EVENT0_IMASK_LINOVF_R = crate :: BitReader < INT_EVENT0_IMASK_LINOVF_A > ; # [doc = "Enable LIN Hardware Counter Overflow Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_LINOVF_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_LINOVF_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_LINOVF_SET = 1 , } impl From < INT_EVENT0_IMASK_LINOVF_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_LINOVF_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_LINOVF_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_LINOVF_A { match self . bits { false => INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_CLR , true => INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_linovf_clr (& self) -> bool { * self == INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_linovf_set (& self) -> bool { * self == INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_SET } } # [doc = "Field `INT_EVENT0_IMASK_LINOVF` writer - Enable LIN Hardware Counter Overflow Interrupt."] pub type INT_EVENT0_IMASK_LINOVF_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_LINOVF_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_LINOVF_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_linovf_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_linovf_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_SET) } } # [doc = "Field `INT_EVENT0_IMASK_RXINT` reader - Enable UART Receive Interrupt."] pub type INT_EVENT0_IMASK_RXINT_R = crate :: BitReader < INT_EVENT0_IMASK_RXINT_A > ; # [doc = "Enable UART Receive Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_RXINT_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_RXINT_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_RXINT_SET = 1 , } impl From < INT_EVENT0_IMASK_RXINT_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_RXINT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_RXINT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_RXINT_A { match self . bits { false => INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_CLR , true => INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_rxint_clr (& self) -> bool { * self == INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_rxint_set (& self) -> bool { * self == INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_SET } } # [doc = "Field `INT_EVENT0_IMASK_RXINT` writer - Enable UART Receive Interrupt."] pub type INT_EVENT0_IMASK_RXINT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_RXINT_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_RXINT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_rxint_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_rxint_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_SET) } } # [doc = "Field `INT_EVENT0_IMASK_TXINT` reader - Enable UART Transmit Interrupt."] pub type INT_EVENT0_IMASK_TXINT_R = crate :: BitReader < INT_EVENT0_IMASK_TXINT_A > ; # [doc = "Enable UART Transmit Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_TXINT_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_TXINT_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_TXINT_SET = 1 , } impl From < INT_EVENT0_IMASK_TXINT_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_TXINT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_TXINT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_TXINT_A { match self . bits { false => INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_CLR , true => INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_txint_clr (& self) -> bool { * self == INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_txint_set (& self) -> bool { * self == INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_SET } } # [doc = "Field `INT_EVENT0_IMASK_TXINT` writer - Enable UART Transmit Interrupt."] pub type INT_EVENT0_IMASK_TXINT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_TXINT_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_TXINT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_txint_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_txint_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_SET) } } # [doc = "Field `INT_EVENT0_IMASK_EOT` reader - Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] pub type INT_EVENT0_IMASK_EOT_R = crate :: BitReader < INT_EVENT0_IMASK_EOT_A > ; # [doc = "Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_EOT_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_EOT_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_EOT_SET = 1 , } impl From < INT_EVENT0_IMASK_EOT_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_EOT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_EOT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_EOT_A { match self . bits { false => INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_CLR , true => INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_eot_clr (& self) -> bool { * self == INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_eot_set (& self) -> bool { * self == INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_SET } } # [doc = "Field `INT_EVENT0_IMASK_EOT` writer - Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] pub type INT_EVENT0_IMASK_EOT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_EOT_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_EOT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_eot_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_eot_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_SET) } } # [doc = "Field `INT_EVENT0_IMASK_ADDR_MATCH` reader - Enable Address Match Interrupt."] pub type INT_EVENT0_IMASK_ADDR_MATCH_R = crate :: BitReader < INT_EVENT0_IMASK_ADDR_MATCH_A > ; # [doc = "Enable Address Match Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_ADDR_MATCH_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_ADDR_MATCH_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_ADDR_MATCH_SET = 1 , } impl From < INT_EVENT0_IMASK_ADDR_MATCH_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_ADDR_MATCH_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_ADDR_MATCH_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_ADDR_MATCH_A { match self . bits { false => INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_CLR , true => INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_addr_match_clr (& self) -> bool { * self == INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_addr_match_set (& self) -> bool { * self == INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_SET } } # [doc = "Field `INT_EVENT0_IMASK_ADDR_MATCH` writer - Enable Address Match Interrupt."] pub type INT_EVENT0_IMASK_ADDR_MATCH_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_ADDR_MATCH_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_ADDR_MATCH_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_addr_match_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_addr_match_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_SET) } } # [doc = "Field `INT_EVENT0_IMASK_CTS` reader - Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] pub type INT_EVENT0_IMASK_CTS_R = crate :: BitReader < INT_EVENT0_IMASK_CTS_A > ; # [doc = "Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_CTS_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_CTS_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_CTS_SET = 1 , } impl From < INT_EVENT0_IMASK_CTS_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_CTS_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_CTS_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_CTS_A { match self . bits { false => INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_CLR , true => INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_cts_clr (& self) -> bool { * self == INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_cts_set (& self) -> bool { * self == INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_SET } } # [doc = "Field `INT_EVENT0_IMASK_CTS` writer - Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] pub type INT_EVENT0_IMASK_CTS_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_CTS_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_CTS_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_cts_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_cts_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DMA_DONE_RX` reader - Enable DMA Done on RX Event Channel"] pub type INT_EVENT0_IMASK_DMA_DONE_RX_R = crate :: BitReader < INT_EVENT0_IMASK_DMA_DONE_RX_A > ; # [doc = "Enable DMA Done on RX Event Channel\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DMA_DONE_RX_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DMA_DONE_RX_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DMA_DONE_RX_SET = 1 , } impl From < INT_EVENT0_IMASK_DMA_DONE_RX_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DMA_DONE_RX_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DMA_DONE_RX_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DMA_DONE_RX_A { match self . bits { false => INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_CLR , true => INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dma_done_rx_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dma_done_rx_set (& self) -> bool { * self == INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_SET } } # [doc = "Field `INT_EVENT0_IMASK_DMA_DONE_RX` writer - Enable DMA Done on RX Event Channel"] pub type INT_EVENT0_IMASK_DMA_DONE_RX_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DMA_DONE_RX_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DMA_DONE_RX_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dma_done_rx_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dma_done_rx_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DMA_DONE_TX` reader - Enable DMA Done on TX Event Channel"] pub type INT_EVENT0_IMASK_DMA_DONE_TX_R = crate :: BitReader < INT_EVENT0_IMASK_DMA_DONE_TX_A > ; # [doc = "Enable DMA Done on TX Event Channel\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DMA_DONE_TX_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DMA_DONE_TX_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DMA_DONE_TX_SET = 1 , } impl From < INT_EVENT0_IMASK_DMA_DONE_TX_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DMA_DONE_TX_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DMA_DONE_TX_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DMA_DONE_TX_A { match self . bits { false => INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_CLR , true => INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dma_done_tx_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dma_done_tx_set (& self) -> bool { * self == INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_SET } } # [doc = "Field `INT_EVENT0_IMASK_DMA_DONE_TX` writer - Enable DMA Done on TX Event Channel"] pub type INT_EVENT0_IMASK_DMA_DONE_TX_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DMA_DONE_TX_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DMA_DONE_TX_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dma_done_tx_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dma_done_tx_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_SET) } } # [doc = "Field `INT_EVENT0_IMASK_NERR` reader - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] pub type INT_EVENT0_IMASK_NERR_R = crate :: BitReader < INT_EVENT0_IMASK_NERR_A > ; # [doc = "Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_NERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_NERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_NERR_SET = 1 , } impl From < INT_EVENT0_IMASK_NERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_NERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_NERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_NERR_A { match self . bits { false => INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_CLR , true => INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_nerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_nerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_NERR` writer - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] pub type INT_EVENT0_IMASK_NERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_NERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_NERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_nerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_nerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_SET) } } impl R { # [doc = "Bit 0 - Enable UARTOUT Receive Time-Out Interrupt."] # [inline (always)] pub fn int_event0_imask_rtout (& self) -> INT_EVENT0_IMASK_RTOUT_R { INT_EVENT0_IMASK_RTOUT_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - Enable UART Framing Error Interrupt."] # [inline (always)] pub fn int_event0_imask_frmerr (& self) -> INT_EVENT0_IMASK_FRMERR_R { INT_EVENT0_IMASK_FRMERR_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - Enable UART Parity Error Interrupt."] # [inline (always)] pub fn int_event0_imask_parerr (& self) -> INT_EVENT0_IMASK_PARERR_R { INT_EVENT0_IMASK_PARERR_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - Enable UART Break Error Interrupt."] # [inline (always)] pub fn int_event0_imask_brkerr (& self) -> INT_EVENT0_IMASK_BRKERR_R { INT_EVENT0_IMASK_BRKERR_R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - Enable UART Receive Overrun Error Interrupt."] # [inline (always)] pub fn int_event0_imask_ovrerr (& self) -> INT_EVENT0_IMASK_OVRERR_R { INT_EVENT0_IMASK_OVRERR_R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - Enable Negative Edge on UARTxRXD Interrupt."] # [inline (always)] pub fn int_event0_imask_rxne (& self) -> INT_EVENT0_IMASK_RXNE_R { INT_EVENT0_IMASK_RXNE_R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - Enable Positive Edge on UARTxRXD Interrupt."] # [inline (always)] pub fn int_event0_imask_rxpe (& self) -> INT_EVENT0_IMASK_RXPE_R { INT_EVENT0_IMASK_RXPE_R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - Enable LIN Capture 0 / Match Interrupt ."] # [inline (always)] pub fn int_event0_imask_linc0 (& self) -> INT_EVENT0_IMASK_LINC0_R { INT_EVENT0_IMASK_LINC0_R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - Enable LIN Capture 1 Interrupt."] # [inline (always)] pub fn int_event0_imask_linc1 (& self) -> INT_EVENT0_IMASK_LINC1_R { INT_EVENT0_IMASK_LINC1_R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - Enable LIN Hardware Counter Overflow Interrupt."] # [inline (always)] pub fn int_event0_imask_linovf (& self) -> INT_EVENT0_IMASK_LINOVF_R { INT_EVENT0_IMASK_LINOVF_R :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - Enable UART Receive Interrupt."] # [inline (always)] pub fn int_event0_imask_rxint (& self) -> INT_EVENT0_IMASK_RXINT_R { INT_EVENT0_IMASK_RXINT_R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - Enable UART Transmit Interrupt."] # [inline (always)] pub fn int_event0_imask_txint (& self) -> INT_EVENT0_IMASK_TXINT_R { INT_EVENT0_IMASK_TXINT_R :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] # [inline (always)] pub fn int_event0_imask_eot (& self) -> INT_EVENT0_IMASK_EOT_R { INT_EVENT0_IMASK_EOT_R :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - Enable Address Match Interrupt."] # [inline (always)] pub fn int_event0_imask_addr_match (& self) -> INT_EVENT0_IMASK_ADDR_MATCH_R { INT_EVENT0_IMASK_ADDR_MATCH_R :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 14 - Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] # [inline (always)] pub fn int_event0_imask_cts (& self) -> INT_EVENT0_IMASK_CTS_R { INT_EVENT0_IMASK_CTS_R :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - Enable DMA Done on RX Event Channel"] # [inline (always)] pub fn int_event0_imask_dma_done_rx (& self) -> INT_EVENT0_IMASK_DMA_DONE_RX_R { INT_EVENT0_IMASK_DMA_DONE_RX_R :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bit 16 - Enable DMA Done on TX Event Channel"] # [inline (always)] pub fn int_event0_imask_dma_done_tx (& self) -> INT_EVENT0_IMASK_DMA_DONE_TX_R { INT_EVENT0_IMASK_DMA_DONE_TX_R :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] # [inline (always)] pub fn int_event0_imask_nerr (& self) -> INT_EVENT0_IMASK_NERR_R { INT_EVENT0_IMASK_NERR_R :: new (((self . bits >> 17) & 1) != 0) } } impl W { # [doc = "Bit 0 - Enable UARTOUT Receive Time-Out Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_rtout (& mut self) -> INT_EVENT0_IMASK_RTOUT_W < INT_EVENT0_IMASK_SPEC , 0 > { INT_EVENT0_IMASK_RTOUT_W :: new (self) } # [doc = "Bit 1 - Enable UART Framing Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_frmerr (& mut self) -> INT_EVENT0_IMASK_FRMERR_W < INT_EVENT0_IMASK_SPEC , 1 > { INT_EVENT0_IMASK_FRMERR_W :: new (self) } # [doc = "Bit 2 - Enable UART Parity Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_parerr (& mut self) -> INT_EVENT0_IMASK_PARERR_W < INT_EVENT0_IMASK_SPEC , 2 > { INT_EVENT0_IMASK_PARERR_W :: new (self) } # [doc = "Bit 3 - Enable UART Break Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_brkerr (& mut self) -> INT_EVENT0_IMASK_BRKERR_W < INT_EVENT0_IMASK_SPEC , 3 > { INT_EVENT0_IMASK_BRKERR_W :: new (self) } # [doc = "Bit 4 - Enable UART Receive Overrun Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_ovrerr (& mut self) -> INT_EVENT0_IMASK_OVRERR_W < INT_EVENT0_IMASK_SPEC , 4 > { INT_EVENT0_IMASK_OVRERR_W :: new (self) } # [doc = "Bit 5 - Enable Negative Edge on UARTxRXD Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_rxne (& mut self) -> INT_EVENT0_IMASK_RXNE_W < INT_EVENT0_IMASK_SPEC , 5 > { INT_EVENT0_IMASK_RXNE_W :: new (self) } # [doc = "Bit 6 - Enable Positive Edge on UARTxRXD Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_rxpe (& mut self) -> INT_EVENT0_IMASK_RXPE_W < INT_EVENT0_IMASK_SPEC , 6 > { INT_EVENT0_IMASK_RXPE_W :: new (self) } # [doc = "Bit 7 - Enable LIN Capture 0 / Match Interrupt ."] # [inline (always)] # [must_use] pub fn int_event0_imask_linc0 (& mut self) -> INT_EVENT0_IMASK_LINC0_W < INT_EVENT0_IMASK_SPEC , 7 > { INT_EVENT0_IMASK_LINC0_W :: new (self) } # [doc = "Bit 8 - Enable LIN Capture 1 Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_linc1 (& mut self) -> INT_EVENT0_IMASK_LINC1_W < INT_EVENT0_IMASK_SPEC , 8 > { INT_EVENT0_IMASK_LINC1_W :: new (self) } # [doc = "Bit 9 - Enable LIN Hardware Counter Overflow Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_linovf (& mut self) -> INT_EVENT0_IMASK_LINOVF_W < INT_EVENT0_IMASK_SPEC , 9 > { INT_EVENT0_IMASK_LINOVF_W :: new (self) } # [doc = "Bit 10 - Enable UART Receive Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_rxint (& mut self) -> INT_EVENT0_IMASK_RXINT_W < INT_EVENT0_IMASK_SPEC , 10 > { INT_EVENT0_IMASK_RXINT_W :: new (self) } # [doc = "Bit 11 - Enable UART Transmit Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_txint (& mut self) -> INT_EVENT0_IMASK_TXINT_W < INT_EVENT0_IMASK_SPEC , 11 > { INT_EVENT0_IMASK_TXINT_W :: new (self) } # [doc = "Bit 12 - Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] # [inline (always)] # [must_use] pub fn int_event0_imask_eot (& mut self) -> INT_EVENT0_IMASK_EOT_W <'_,  INT_EVENT0_IMASK_SPEC , 12 > { INT_EVENT0_IMASK_EOT_W :: new (self) } # [doc = "Bit 13 - Enable Address Match Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_addr_match (& mut self) -> INT_EVENT0_IMASK_ADDR_MATCH_W < INT_EVENT0_IMASK_SPEC , 13 > { INT_EVENT0_IMASK_ADDR_MATCH_W :: new (self) } # [doc = "Bit 14 - Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] # [inline (always)] # [must_use] pub fn int_event0_imask_cts (& mut self) -> INT_EVENT0_IMASK_CTS_W < INT_EVENT0_IMASK_SPEC , 14 > { INT_EVENT0_IMASK_CTS_W :: new (self) } # [doc = "Bit 15 - Enable DMA Done on RX Event Channel"] # [inline (always)] # [must_use] pub fn int_event0_imask_dma_done_rx (& mut self) -> INT_EVENT0_IMASK_DMA_DONE_RX_W < INT_EVENT0_IMASK_SPEC , 15 > { INT_EVENT0_IMASK_DMA_DONE_RX_W :: new (self) } # [doc = "Bit 16 - Enable DMA Done on TX Event Channel"] # [inline (always)] # [must_use] pub fn int_event0_imask_dma_done_tx (& mut self) -> INT_EVENT0_IMASK_DMA_DONE_TX_W < INT_EVENT0_IMASK_SPEC , 16 > { INT_EVENT0_IMASK_DMA_DONE_TX_W :: new (self) } # [doc = "Bit 17 - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] # [inline (always)] # [must_use] pub fn int_event0_imask_nerr (& mut self) -> INT_EVENT0_IMASK_NERR_W < INT_EVENT0_IMASK_SPEC , 17 > { INT_EVENT0_IMASK_NERR_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Interrupt mask\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_event0_imask::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_event0_imask::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct INT_EVENT0_IMASK_SPEC ; impl crate :: RegisterSpec for INT_EVENT0_IMASK_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`int_event0_imask::R`](R) reader structure"] impl crate :: Readable for INT_EVENT0_IMASK_SPEC { } # [doc = "`write(|w| ..)` method takes [`int_event0_imask::W`](W) writer structure"] impl crate :: Writable for INT_EVENT0_IMASK_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets INT_EVENT0_IMASK to value 0"] impl crate :: Resettable for INT_EVENT0_IMASK_SPEC { const RESET_VALUE : Self :: Ux = 0 ; }
[INFO] [stdout]   |                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                 +++
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing
[INFO] [stdout]  --> src/uart0/int_event0_imask.rs:1:43714
[INFO] [stdout]   |
[INFO] [stdout] 1 | ...ddr_match (& mut self) -> INT_EVENT0_IMASK_ADDR_MATCH_W < INT_EVENT0_IMASK_SPEC , 13 > { INT_EVENT0_IMASK_ADDR_MATCH_W :: new (sel...
[INFO] [stdout]   |               ^^^^^^^^^^     ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here
[INFO] [stdout]   |               |
[INFO] [stdout]   |               the lifetime is elided here
[INFO] [stdout]   |
[INFO] [stdout]   = help: the same lifetime is referred to in inconsistent ways, making the signature confusing
[INFO] [stdout] help: use `'_` for type paths
[INFO] [stdout]   |
[INFO] [stdout] 1 | # [doc = "Register `INT_EVENT0_IMASK` reader"] pub type R = crate :: R < INT_EVENT0_IMASK_SPEC > ; # [doc = "Register `INT_EVENT0_IMASK` writer"] pub type W = crate :: W < INT_EVENT0_IMASK_SPEC > ; # [doc = "Field `INT_EVENT0_IMASK_RTOUT` reader - Enable UARTOUT Receive Time-Out Interrupt."] pub type INT_EVENT0_IMASK_RTOUT_R = crate :: BitReader < INT_EVENT0_IMASK_RTOUT_A > ; # [doc = "Enable UARTOUT Receive Time-Out Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_RTOUT_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_RTOUT_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_RTOUT_SET = 1 , } impl From < INT_EVENT0_IMASK_RTOUT_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_RTOUT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_RTOUT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_RTOUT_A { match self . bits { false => INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_CLR , true => INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_rtout_clr (& self) -> bool { * self == INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_rtout_set (& self) -> bool { * self == INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_SET } } # [doc = "Field `INT_EVENT0_IMASK_RTOUT` writer - Enable UARTOUT Receive Time-Out Interrupt."] pub type INT_EVENT0_IMASK_RTOUT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_RTOUT_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_RTOUT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_rtout_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_rtout_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_SET) } } # [doc = "Field `INT_EVENT0_IMASK_FRMERR` reader - Enable UART Framing Error Interrupt."] pub type INT_EVENT0_IMASK_FRMERR_R = crate :: BitReader < INT_EVENT0_IMASK_FRMERR_A > ; # [doc = "Enable UART Framing Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_FRMERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_FRMERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_FRMERR_SET = 1 , } impl From < INT_EVENT0_IMASK_FRMERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_FRMERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_FRMERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_FRMERR_A { match self . bits { false => INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_CLR , true => INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_frmerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_frmerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_FRMERR` writer - Enable UART Framing Error Interrupt."] pub type INT_EVENT0_IMASK_FRMERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_FRMERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_FRMERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_frmerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_frmerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_SET) } } # [doc = "Field `INT_EVENT0_IMASK_PARERR` reader - Enable UART Parity Error Interrupt."] pub type INT_EVENT0_IMASK_PARERR_R = crate :: BitReader < INT_EVENT0_IMASK_PARERR_A > ; # [doc = "Enable UART Parity Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_PARERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_PARERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_PARERR_SET = 1 , } impl From < INT_EVENT0_IMASK_PARERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_PARERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_PARERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_PARERR_A { match self . bits { false => INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_CLR , true => INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_parerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_parerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_PARERR` writer - Enable UART Parity Error Interrupt."] pub type INT_EVENT0_IMASK_PARERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_PARERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_PARERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_parerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_parerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_SET) } } # [doc = "Field `INT_EVENT0_IMASK_BRKERR` reader - Enable UART Break Error Interrupt."] pub type INT_EVENT0_IMASK_BRKERR_R = crate :: BitReader < INT_EVENT0_IMASK_BRKERR_A > ; # [doc = "Enable UART Break Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_BRKERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_BRKERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_BRKERR_SET = 1 , } impl From < INT_EVENT0_IMASK_BRKERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_BRKERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_BRKERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_BRKERR_A { match self . bits { false => INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_CLR , true => INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_brkerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_brkerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_BRKERR` writer - Enable UART Break Error Interrupt."] pub type INT_EVENT0_IMASK_BRKERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_BRKERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_BRKERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_brkerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_brkerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_SET) } } # [doc = "Field `INT_EVENT0_IMASK_OVRERR` reader - Enable UART Receive Overrun Error Interrupt."] pub type INT_EVENT0_IMASK_OVRERR_R = crate :: BitReader < INT_EVENT0_IMASK_OVRERR_A > ; # [doc = "Enable UART Receive Overrun Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_OVRERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_OVRERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_OVRERR_SET = 1 , } impl From < INT_EVENT0_IMASK_OVRERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_OVRERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_OVRERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_OVRERR_A { match self . bits { false => INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_CLR , true => INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_ovrerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_ovrerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_OVRERR` writer - Enable UART Receive Overrun Error Interrupt."] pub type INT_EVENT0_IMASK_OVRERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_OVRERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_OVRERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_ovrerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_ovrerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_SET) } } # [doc = "Field `INT_EVENT0_IMASK_RXNE` reader - Enable Negative Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_IMASK_RXNE_R = crate :: BitReader < INT_EVENT0_IMASK_RXNE_A > ; # [doc = "Enable Negative Edge on UARTxRXD Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_RXNE_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_RXNE_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_RXNE_SET = 1 , } impl From < INT_EVENT0_IMASK_RXNE_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_RXNE_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_RXNE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_RXNE_A { match self . bits { false => INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_CLR , true => INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_rxne_clr (& self) -> bool { * self == INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_rxne_set (& self) -> bool { * self == INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_SET } } # [doc = "Field `INT_EVENT0_IMASK_RXNE` writer - Enable Negative Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_IMASK_RXNE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_RXNE_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_RXNE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_rxne_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_rxne_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_SET) } } # [doc = "Field `INT_EVENT0_IMASK_RXPE` reader - Enable Positive Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_IMASK_RXPE_R = crate :: BitReader < INT_EVENT0_IMASK_RXPE_A > ; # [doc = "Enable Positive Edge on UARTxRXD Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_RXPE_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_RXPE_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_RXPE_SET = 1 , } impl From < INT_EVENT0_IMASK_RXPE_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_RXPE_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_RXPE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_RXPE_A { match self . bits { false => INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_CLR , true => INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_rxpe_clr (& self) -> bool { * self == INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_rxpe_set (& self) -> bool { * self == INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_SET } } # [doc = "Field `INT_EVENT0_IMASK_RXPE` writer - Enable Positive Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_IMASK_RXPE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_RXPE_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_RXPE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_rxpe_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_rxpe_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_SET) } } # [doc = "Field `INT_EVENT0_IMASK_LINC0` reader - Enable LIN Capture 0 / Match Interrupt ."] pub type INT_EVENT0_IMASK_LINC0_R = crate :: BitReader < INT_EVENT0_IMASK_LINC0_A > ; # [doc = "Enable LIN Capture 0 / Match Interrupt .\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_LINC0_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_LINC0_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_LINC0_SET = 1 , } impl From < INT_EVENT0_IMASK_LINC0_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_LINC0_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_LINC0_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_LINC0_A { match self . bits { false => INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_CLR , true => INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_linc0_clr (& self) -> bool { * self == INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_linc0_set (& self) -> bool { * self == INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_SET } } # [doc = "Field `INT_EVENT0_IMASK_LINC0` writer - Enable LIN Capture 0 / Match Interrupt ."] pub type INT_EVENT0_IMASK_LINC0_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_LINC0_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_LINC0_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_linc0_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_linc0_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_SET) } } # [doc = "Field `INT_EVENT0_IMASK_LINC1` reader - Enable LIN Capture 1 Interrupt."] pub type INT_EVENT0_IMASK_LINC1_R = crate :: BitReader < INT_EVENT0_IMASK_LINC1_A > ; # [doc = "Enable LIN Capture 1 Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_LINC1_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_LINC1_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_LINC1_SET = 1 , } impl From < INT_EVENT0_IMASK_LINC1_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_LINC1_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_LINC1_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_LINC1_A { match self . bits { false => INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_CLR , true => INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_linc1_clr (& self) -> bool { * self == INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_linc1_set (& self) -> bool { * self == INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_SET } } # [doc = "Field `INT_EVENT0_IMASK_LINC1` writer - Enable LIN Capture 1 Interrupt."] pub type INT_EVENT0_IMASK_LINC1_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_LINC1_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_LINC1_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_linc1_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_linc1_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_SET) } } # [doc = "Field `INT_EVENT0_IMASK_LINOVF` reader - Enable LIN Hardware Counter Overflow Interrupt."] pub type INT_EVENT0_IMASK_LINOVF_R = crate :: BitReader < INT_EVENT0_IMASK_LINOVF_A > ; # [doc = "Enable LIN Hardware Counter Overflow Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_LINOVF_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_LINOVF_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_LINOVF_SET = 1 , } impl From < INT_EVENT0_IMASK_LINOVF_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_LINOVF_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_LINOVF_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_LINOVF_A { match self . bits { false => INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_CLR , true => INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_linovf_clr (& self) -> bool { * self == INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_linovf_set (& self) -> bool { * self == INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_SET } } # [doc = "Field `INT_EVENT0_IMASK_LINOVF` writer - Enable LIN Hardware Counter Overflow Interrupt."] pub type INT_EVENT0_IMASK_LINOVF_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_LINOVF_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_LINOVF_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_linovf_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_linovf_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_SET) } } # [doc = "Field `INT_EVENT0_IMASK_RXINT` reader - Enable UART Receive Interrupt."] pub type INT_EVENT0_IMASK_RXINT_R = crate :: BitReader < INT_EVENT0_IMASK_RXINT_A > ; # [doc = "Enable UART Receive Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_RXINT_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_RXINT_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_RXINT_SET = 1 , } impl From < INT_EVENT0_IMASK_RXINT_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_RXINT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_RXINT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_RXINT_A { match self . bits { false => INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_CLR , true => INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_rxint_clr (& self) -> bool { * self == INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_rxint_set (& self) -> bool { * self == INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_SET } } # [doc = "Field `INT_EVENT0_IMASK_RXINT` writer - Enable UART Receive Interrupt."] pub type INT_EVENT0_IMASK_RXINT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_RXINT_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_RXINT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_rxint_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_rxint_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_SET) } } # [doc = "Field `INT_EVENT0_IMASK_TXINT` reader - Enable UART Transmit Interrupt."] pub type INT_EVENT0_IMASK_TXINT_R = crate :: BitReader < INT_EVENT0_IMASK_TXINT_A > ; # [doc = "Enable UART Transmit Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_TXINT_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_TXINT_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_TXINT_SET = 1 , } impl From < INT_EVENT0_IMASK_TXINT_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_TXINT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_TXINT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_TXINT_A { match self . bits { false => INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_CLR , true => INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_txint_clr (& self) -> bool { * self == INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_txint_set (& self) -> bool { * self == INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_SET } } # [doc = "Field `INT_EVENT0_IMASK_TXINT` writer - Enable UART Transmit Interrupt."] pub type INT_EVENT0_IMASK_TXINT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_TXINT_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_TXINT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_txint_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_txint_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_SET) } } # [doc = "Field `INT_EVENT0_IMASK_EOT` reader - Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] pub type INT_EVENT0_IMASK_EOT_R = crate :: BitReader < INT_EVENT0_IMASK_EOT_A > ; # [doc = "Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_EOT_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_EOT_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_EOT_SET = 1 , } impl From < INT_EVENT0_IMASK_EOT_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_EOT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_EOT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_EOT_A { match self . bits { false => INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_CLR , true => INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_eot_clr (& self) -> bool { * self == INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_eot_set (& self) -> bool { * self == INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_SET } } # [doc = "Field `INT_EVENT0_IMASK_EOT` writer - Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] pub type INT_EVENT0_IMASK_EOT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_EOT_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_EOT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_eot_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_eot_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_SET) } } # [doc = "Field `INT_EVENT0_IMASK_ADDR_MATCH` reader - Enable Address Match Interrupt."] pub type INT_EVENT0_IMASK_ADDR_MATCH_R = crate :: BitReader < INT_EVENT0_IMASK_ADDR_MATCH_A > ; # [doc = "Enable Address Match Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_ADDR_MATCH_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_ADDR_MATCH_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_ADDR_MATCH_SET = 1 , } impl From < INT_EVENT0_IMASK_ADDR_MATCH_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_ADDR_MATCH_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_ADDR_MATCH_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_ADDR_MATCH_A { match self . bits { false => INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_CLR , true => INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_addr_match_clr (& self) -> bool { * self == INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_addr_match_set (& self) -> bool { * self == INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_SET } } # [doc = "Field `INT_EVENT0_IMASK_ADDR_MATCH` writer - Enable Address Match Interrupt."] pub type INT_EVENT0_IMASK_ADDR_MATCH_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_ADDR_MATCH_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_ADDR_MATCH_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_addr_match_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_addr_match_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_SET) } } # [doc = "Field `INT_EVENT0_IMASK_CTS` reader - Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] pub type INT_EVENT0_IMASK_CTS_R = crate :: BitReader < INT_EVENT0_IMASK_CTS_A > ; # [doc = "Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_CTS_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_CTS_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_CTS_SET = 1 , } impl From < INT_EVENT0_IMASK_CTS_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_CTS_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_CTS_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_CTS_A { match self . bits { false => INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_CLR , true => INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_cts_clr (& self) -> bool { * self == INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_cts_set (& self) -> bool { * self == INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_SET } } # [doc = "Field `INT_EVENT0_IMASK_CTS` writer - Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] pub type INT_EVENT0_IMASK_CTS_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_CTS_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_CTS_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_cts_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_cts_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DMA_DONE_RX` reader - Enable DMA Done on RX Event Channel"] pub type INT_EVENT0_IMASK_DMA_DONE_RX_R = crate :: BitReader < INT_EVENT0_IMASK_DMA_DONE_RX_A > ; # [doc = "Enable DMA Done on RX Event Channel\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DMA_DONE_RX_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DMA_DONE_RX_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DMA_DONE_RX_SET = 1 , } impl From < INT_EVENT0_IMASK_DMA_DONE_RX_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DMA_DONE_RX_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DMA_DONE_RX_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DMA_DONE_RX_A { match self . bits { false => INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_CLR , true => INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dma_done_rx_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dma_done_rx_set (& self) -> bool { * self == INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_SET } } # [doc = "Field `INT_EVENT0_IMASK_DMA_DONE_RX` writer - Enable DMA Done on RX Event Channel"] pub type INT_EVENT0_IMASK_DMA_DONE_RX_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DMA_DONE_RX_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DMA_DONE_RX_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dma_done_rx_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dma_done_rx_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DMA_DONE_TX` reader - Enable DMA Done on TX Event Channel"] pub type INT_EVENT0_IMASK_DMA_DONE_TX_R = crate :: BitReader < INT_EVENT0_IMASK_DMA_DONE_TX_A > ; # [doc = "Enable DMA Done on TX Event Channel\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DMA_DONE_TX_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DMA_DONE_TX_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DMA_DONE_TX_SET = 1 , } impl From < INT_EVENT0_IMASK_DMA_DONE_TX_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DMA_DONE_TX_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DMA_DONE_TX_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DMA_DONE_TX_A { match self . bits { false => INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_CLR , true => INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dma_done_tx_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dma_done_tx_set (& self) -> bool { * self == INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_SET } } # [doc = "Field `INT_EVENT0_IMASK_DMA_DONE_TX` writer - Enable DMA Done on TX Event Channel"] pub type INT_EVENT0_IMASK_DMA_DONE_TX_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DMA_DONE_TX_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DMA_DONE_TX_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dma_done_tx_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dma_done_tx_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_SET) } } # [doc = "Field `INT_EVENT0_IMASK_NERR` reader - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] pub type INT_EVENT0_IMASK_NERR_R = crate :: BitReader < INT_EVENT0_IMASK_NERR_A > ; # [doc = "Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_NERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_NERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_NERR_SET = 1 , } impl From < INT_EVENT0_IMASK_NERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_NERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_NERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_NERR_A { match self . bits { false => INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_CLR , true => INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_nerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_nerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_NERR` writer - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] pub type INT_EVENT0_IMASK_NERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_NERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_NERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_nerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_nerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_SET) } } impl R { # [doc = "Bit 0 - Enable UARTOUT Receive Time-Out Interrupt."] # [inline (always)] pub fn int_event0_imask_rtout (& self) -> INT_EVENT0_IMASK_RTOUT_R { INT_EVENT0_IMASK_RTOUT_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - Enable UART Framing Error Interrupt."] # [inline (always)] pub fn int_event0_imask_frmerr (& self) -> INT_EVENT0_IMASK_FRMERR_R { INT_EVENT0_IMASK_FRMERR_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - Enable UART Parity Error Interrupt."] # [inline (always)] pub fn int_event0_imask_parerr (& self) -> INT_EVENT0_IMASK_PARERR_R { INT_EVENT0_IMASK_PARERR_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - Enable UART Break Error Interrupt."] # [inline (always)] pub fn int_event0_imask_brkerr (& self) -> INT_EVENT0_IMASK_BRKERR_R { INT_EVENT0_IMASK_BRKERR_R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - Enable UART Receive Overrun Error Interrupt."] # [inline (always)] pub fn int_event0_imask_ovrerr (& self) -> INT_EVENT0_IMASK_OVRERR_R { INT_EVENT0_IMASK_OVRERR_R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - Enable Negative Edge on UARTxRXD Interrupt."] # [inline (always)] pub fn int_event0_imask_rxne (& self) -> INT_EVENT0_IMASK_RXNE_R { INT_EVENT0_IMASK_RXNE_R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - Enable Positive Edge on UARTxRXD Interrupt."] # [inline (always)] pub fn int_event0_imask_rxpe (& self) -> INT_EVENT0_IMASK_RXPE_R { INT_EVENT0_IMASK_RXPE_R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - Enable LIN Capture 0 / Match Interrupt ."] # [inline (always)] pub fn int_event0_imask_linc0 (& self) -> INT_EVENT0_IMASK_LINC0_R { INT_EVENT0_IMASK_LINC0_R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - Enable LIN Capture 1 Interrupt."] # [inline (always)] pub fn int_event0_imask_linc1 (& self) -> INT_EVENT0_IMASK_LINC1_R { INT_EVENT0_IMASK_LINC1_R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - Enable LIN Hardware Counter Overflow Interrupt."] # [inline (always)] pub fn int_event0_imask_linovf (& self) -> INT_EVENT0_IMASK_LINOVF_R { INT_EVENT0_IMASK_LINOVF_R :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - Enable UART Receive Interrupt."] # [inline (always)] pub fn int_event0_imask_rxint (& self) -> INT_EVENT0_IMASK_RXINT_R { INT_EVENT0_IMASK_RXINT_R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - Enable UART Transmit Interrupt."] # [inline (always)] pub fn int_event0_imask_txint (& self) -> INT_EVENT0_IMASK_TXINT_R { INT_EVENT0_IMASK_TXINT_R :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] # [inline (always)] pub fn int_event0_imask_eot (& self) -> INT_EVENT0_IMASK_EOT_R { INT_EVENT0_IMASK_EOT_R :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - Enable Address Match Interrupt."] # [inline (always)] pub fn int_event0_imask_addr_match (& self) -> INT_EVENT0_IMASK_ADDR_MATCH_R { INT_EVENT0_IMASK_ADDR_MATCH_R :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 14 - Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] # [inline (always)] pub fn int_event0_imask_cts (& self) -> INT_EVENT0_IMASK_CTS_R { INT_EVENT0_IMASK_CTS_R :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - Enable DMA Done on RX Event Channel"] # [inline (always)] pub fn int_event0_imask_dma_done_rx (& self) -> INT_EVENT0_IMASK_DMA_DONE_RX_R { INT_EVENT0_IMASK_DMA_DONE_RX_R :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bit 16 - Enable DMA Done on TX Event Channel"] # [inline (always)] pub fn int_event0_imask_dma_done_tx (& self) -> INT_EVENT0_IMASK_DMA_DONE_TX_R { INT_EVENT0_IMASK_DMA_DONE_TX_R :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] # [inline (always)] pub fn int_event0_imask_nerr (& self) -> INT_EVENT0_IMASK_NERR_R { INT_EVENT0_IMASK_NERR_R :: new (((self . bits >> 17) & 1) != 0) } } impl W { # [doc = "Bit 0 - Enable UARTOUT Receive Time-Out Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_rtout (& mut self) -> INT_EVENT0_IMASK_RTOUT_W < INT_EVENT0_IMASK_SPEC , 0 > { INT_EVENT0_IMASK_RTOUT_W :: new (self) } # [doc = "Bit 1 - Enable UART Framing Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_frmerr (& mut self) -> INT_EVENT0_IMASK_FRMERR_W < INT_EVENT0_IMASK_SPEC , 1 > { INT_EVENT0_IMASK_FRMERR_W :: new (self) } # [doc = "Bit 2 - Enable UART Parity Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_parerr (& mut self) -> INT_EVENT0_IMASK_PARERR_W < INT_EVENT0_IMASK_SPEC , 2 > { INT_EVENT0_IMASK_PARERR_W :: new (self) } # [doc = "Bit 3 - Enable UART Break Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_brkerr (& mut self) -> INT_EVENT0_IMASK_BRKERR_W < INT_EVENT0_IMASK_SPEC , 3 > { INT_EVENT0_IMASK_BRKERR_W :: new (self) } # [doc = "Bit 4 - Enable UART Receive Overrun Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_ovrerr (& mut self) -> INT_EVENT0_IMASK_OVRERR_W < INT_EVENT0_IMASK_SPEC , 4 > { INT_EVENT0_IMASK_OVRERR_W :: new (self) } # [doc = "Bit 5 - Enable Negative Edge on UARTxRXD Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_rxne (& mut self) -> INT_EVENT0_IMASK_RXNE_W < INT_EVENT0_IMASK_SPEC , 5 > { INT_EVENT0_IMASK_RXNE_W :: new (self) } # [doc = "Bit 6 - Enable Positive Edge on UARTxRXD Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_rxpe (& mut self) -> INT_EVENT0_IMASK_RXPE_W < INT_EVENT0_IMASK_SPEC , 6 > { INT_EVENT0_IMASK_RXPE_W :: new (self) } # [doc = "Bit 7 - Enable LIN Capture 0 / Match Interrupt ."] # [inline (always)] # [must_use] pub fn int_event0_imask_linc0 (& mut self) -> INT_EVENT0_IMASK_LINC0_W < INT_EVENT0_IMASK_SPEC , 7 > { INT_EVENT0_IMASK_LINC0_W :: new (self) } # [doc = "Bit 8 - Enable LIN Capture 1 Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_linc1 (& mut self) -> INT_EVENT0_IMASK_LINC1_W < INT_EVENT0_IMASK_SPEC , 8 > { INT_EVENT0_IMASK_LINC1_W :: new (self) } # [doc = "Bit 9 - Enable LIN Hardware Counter Overflow Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_linovf (& mut self) -> INT_EVENT0_IMASK_LINOVF_W < INT_EVENT0_IMASK_SPEC , 9 > { INT_EVENT0_IMASK_LINOVF_W :: new (self) } # [doc = "Bit 10 - Enable UART Receive Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_rxint (& mut self) -> INT_EVENT0_IMASK_RXINT_W < INT_EVENT0_IMASK_SPEC , 10 > { INT_EVENT0_IMASK_RXINT_W :: new (self) } # [doc = "Bit 11 - Enable UART Transmit Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_txint (& mut self) -> INT_EVENT0_IMASK_TXINT_W < INT_EVENT0_IMASK_SPEC , 11 > { INT_EVENT0_IMASK_TXINT_W :: new (self) } # [doc = "Bit 12 - Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] # [inline (always)] # [must_use] pub fn int_event0_imask_eot (& mut self) -> INT_EVENT0_IMASK_EOT_W < INT_EVENT0_IMASK_SPEC , 12 > { INT_EVENT0_IMASK_EOT_W :: new (self) } # [doc = "Bit 13 - Enable Address Match Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_addr_match (& mut self) -> INT_EVENT0_IMASK_ADDR_MATCH_W <'_,  INT_EVENT0_IMASK_SPEC , 13 > { INT_EVENT0_IMASK_ADDR_MATCH_W :: new (self) } # [doc = "Bit 14 - Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] # [inline (always)] # [must_use] pub fn int_event0_imask_cts (& mut self) -> INT_EVENT0_IMASK_CTS_W < INT_EVENT0_IMASK_SPEC , 14 > { INT_EVENT0_IMASK_CTS_W :: new (self) } # [doc = "Bit 15 - Enable DMA Done on RX Event Channel"] # [inline (always)] # [must_use] pub fn int_event0_imask_dma_done_rx (& mut self) -> INT_EVENT0_IMASK_DMA_DONE_RX_W < INT_EVENT0_IMASK_SPEC , 15 > { INT_EVENT0_IMASK_DMA_DONE_RX_W :: new (self) } # [doc = "Bit 16 - Enable DMA Done on TX Event Channel"] # [inline (always)] # [must_use] pub fn int_event0_imask_dma_done_tx (& mut self) -> INT_EVENT0_IMASK_DMA_DONE_TX_W < INT_EVENT0_IMASK_SPEC , 16 > { INT_EVENT0_IMASK_DMA_DONE_TX_W :: new (self) } # [doc = "Bit 17 - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] # [inline (always)] # [must_use] pub fn int_event0_imask_nerr (& mut self) -> INT_EVENT0_IMASK_NERR_W < INT_EVENT0_IMASK_SPEC , 17 > { INT_EVENT0_IMASK_NERR_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Interrupt mask\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_event0_imask::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_event0_imask::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct INT_EVENT0_IMASK_SPEC ; impl crate :: RegisterSpec for INT_EVENT0_IMASK_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`int_event0_imask::R`](R) reader structure"] impl crate :: Readable for INT_EVENT0_IMASK_SPEC { } # [doc = "`write(|w| ..)` method takes [`int_event0_imask::W`](W) writer structure"] impl crate :: Writable for INT_EVENT0_IMASK_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets INT_EVENT0_IMASK to value 0"] impl crate :: Resettable for INT_EVENT0_IMASK_SPEC { const RESET_VALUE : Self :: Ux = 0 ; }
[INFO] [stdout]   |                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                +++
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing
[INFO] [stdout]  --> src/uart0/int_event0_imask.rs:1:43987
[INFO] [stdout]   |
[INFO] [stdout] 1 | ...t0_imask_cts (& mut self) -> INT_EVENT0_IMASK_CTS_W < INT_EVENT0_IMASK_SPEC , 14 > { INT_EVENT0_IMASK_CTS_W :: new (self) } # [doc...
[INFO] [stdout]   |                  ^^^^^^^^^^     ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here
[INFO] [stdout]   |                  |
[INFO] [stdout]   |                  the lifetime is elided here
[INFO] [stdout]   |
[INFO] [stdout]   = help: the same lifetime is referred to in inconsistent ways, making the signature confusing
[INFO] [stdout] help: use `'_` for type paths
[INFO] [stdout]   |
[INFO] [stdout] 1 | # [doc = "Register `INT_EVENT0_IMASK` reader"] pub type R = crate :: R < INT_EVENT0_IMASK_SPEC > ; # [doc = "Register `INT_EVENT0_IMASK` writer"] pub type W = crate :: W < INT_EVENT0_IMASK_SPEC > ; # [doc = "Field `INT_EVENT0_IMASK_RTOUT` reader - Enable UARTOUT Receive Time-Out Interrupt."] pub type INT_EVENT0_IMASK_RTOUT_R = crate :: BitReader < INT_EVENT0_IMASK_RTOUT_A > ; # [doc = "Enable UARTOUT Receive Time-Out Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_RTOUT_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_RTOUT_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_RTOUT_SET = 1 , } impl From < INT_EVENT0_IMASK_RTOUT_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_RTOUT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_RTOUT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_RTOUT_A { match self . bits { false => INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_CLR , true => INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_rtout_clr (& self) -> bool { * self == INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_rtout_set (& self) -> bool { * self == INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_SET } } # [doc = "Field `INT_EVENT0_IMASK_RTOUT` writer - Enable UARTOUT Receive Time-Out Interrupt."] pub type INT_EVENT0_IMASK_RTOUT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_RTOUT_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_RTOUT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_rtout_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_rtout_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_SET) } } # [doc = "Field `INT_EVENT0_IMASK_FRMERR` reader - Enable UART Framing Error Interrupt."] pub type INT_EVENT0_IMASK_FRMERR_R = crate :: BitReader < INT_EVENT0_IMASK_FRMERR_A > ; # [doc = "Enable UART Framing Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_FRMERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_FRMERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_FRMERR_SET = 1 , } impl From < INT_EVENT0_IMASK_FRMERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_FRMERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_FRMERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_FRMERR_A { match self . bits { false => INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_CLR , true => INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_frmerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_frmerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_FRMERR` writer - Enable UART Framing Error Interrupt."] pub type INT_EVENT0_IMASK_FRMERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_FRMERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_FRMERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_frmerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_frmerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_SET) } } # [doc = "Field `INT_EVENT0_IMASK_PARERR` reader - Enable UART Parity Error Interrupt."] pub type INT_EVENT0_IMASK_PARERR_R = crate :: BitReader < INT_EVENT0_IMASK_PARERR_A > ; # [doc = "Enable UART Parity Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_PARERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_PARERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_PARERR_SET = 1 , } impl From < INT_EVENT0_IMASK_PARERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_PARERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_PARERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_PARERR_A { match self . bits { false => INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_CLR , true => INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_parerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_parerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_PARERR` writer - Enable UART Parity Error Interrupt."] pub type INT_EVENT0_IMASK_PARERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_PARERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_PARERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_parerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_parerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_SET) } } # [doc = "Field `INT_EVENT0_IMASK_BRKERR` reader - Enable UART Break Error Interrupt."] pub type INT_EVENT0_IMASK_BRKERR_R = crate :: BitReader < INT_EVENT0_IMASK_BRKERR_A > ; # [doc = "Enable UART Break Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_BRKERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_BRKERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_BRKERR_SET = 1 , } impl From < INT_EVENT0_IMASK_BRKERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_BRKERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_BRKERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_BRKERR_A { match self . bits { false => INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_CLR , true => INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_brkerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_brkerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_BRKERR` writer - Enable UART Break Error Interrupt."] pub type INT_EVENT0_IMASK_BRKERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_BRKERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_BRKERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_brkerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_brkerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_SET) } } # [doc = "Field `INT_EVENT0_IMASK_OVRERR` reader - Enable UART Receive Overrun Error Interrupt."] pub type INT_EVENT0_IMASK_OVRERR_R = crate :: BitReader < INT_EVENT0_IMASK_OVRERR_A > ; # [doc = "Enable UART Receive Overrun Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_OVRERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_OVRERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_OVRERR_SET = 1 , } impl From < INT_EVENT0_IMASK_OVRERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_OVRERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_OVRERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_OVRERR_A { match self . bits { false => INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_CLR , true => INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_ovrerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_ovrerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_OVRERR` writer - Enable UART Receive Overrun Error Interrupt."] pub type INT_EVENT0_IMASK_OVRERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_OVRERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_OVRERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_ovrerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_ovrerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_SET) } } # [doc = "Field `INT_EVENT0_IMASK_RXNE` reader - Enable Negative Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_IMASK_RXNE_R = crate :: BitReader < INT_EVENT0_IMASK_RXNE_A > ; # [doc = "Enable Negative Edge on UARTxRXD Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_RXNE_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_RXNE_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_RXNE_SET = 1 , } impl From < INT_EVENT0_IMASK_RXNE_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_RXNE_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_RXNE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_RXNE_A { match self . bits { false => INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_CLR , true => INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_rxne_clr (& self) -> bool { * self == INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_rxne_set (& self) -> bool { * self == INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_SET } } # [doc = "Field `INT_EVENT0_IMASK_RXNE` writer - Enable Negative Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_IMASK_RXNE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_RXNE_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_RXNE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_rxne_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_rxne_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_SET) } } # [doc = "Field `INT_EVENT0_IMASK_RXPE` reader - Enable Positive Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_IMASK_RXPE_R = crate :: BitReader < INT_EVENT0_IMASK_RXPE_A > ; # [doc = "Enable Positive Edge on UARTxRXD Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_RXPE_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_RXPE_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_RXPE_SET = 1 , } impl From < INT_EVENT0_IMASK_RXPE_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_RXPE_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_RXPE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_RXPE_A { match self . bits { false => INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_CLR , true => INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_rxpe_clr (& self) -> bool { * self == INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_rxpe_set (& self) -> bool { * self == INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_SET } } # [doc = "Field `INT_EVENT0_IMASK_RXPE` writer - Enable Positive Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_IMASK_RXPE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_RXPE_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_RXPE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_rxpe_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_rxpe_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_SET) } } # [doc = "Field `INT_EVENT0_IMASK_LINC0` reader - Enable LIN Capture 0 / Match Interrupt ."] pub type INT_EVENT0_IMASK_LINC0_R = crate :: BitReader < INT_EVENT0_IMASK_LINC0_A > ; # [doc = "Enable LIN Capture 0 / Match Interrupt .\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_LINC0_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_LINC0_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_LINC0_SET = 1 , } impl From < INT_EVENT0_IMASK_LINC0_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_LINC0_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_LINC0_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_LINC0_A { match self . bits { false => INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_CLR , true => INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_linc0_clr (& self) -> bool { * self == INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_linc0_set (& self) -> bool { * self == INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_SET } } # [doc = "Field `INT_EVENT0_IMASK_LINC0` writer - Enable LIN Capture 0 / Match Interrupt ."] pub type INT_EVENT0_IMASK_LINC0_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_LINC0_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_LINC0_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_linc0_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_linc0_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_SET) } } # [doc = "Field `INT_EVENT0_IMASK_LINC1` reader - Enable LIN Capture 1 Interrupt."] pub type INT_EVENT0_IMASK_LINC1_R = crate :: BitReader < INT_EVENT0_IMASK_LINC1_A > ; # [doc = "Enable LIN Capture 1 Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_LINC1_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_LINC1_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_LINC1_SET = 1 , } impl From < INT_EVENT0_IMASK_LINC1_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_LINC1_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_LINC1_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_LINC1_A { match self . bits { false => INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_CLR , true => INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_linc1_clr (& self) -> bool { * self == INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_linc1_set (& self) -> bool { * self == INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_SET } } # [doc = "Field `INT_EVENT0_IMASK_LINC1` writer - Enable LIN Capture 1 Interrupt."] pub type INT_EVENT0_IMASK_LINC1_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_LINC1_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_LINC1_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_linc1_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_linc1_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_SET) } } # [doc = "Field `INT_EVENT0_IMASK_LINOVF` reader - Enable LIN Hardware Counter Overflow Interrupt."] pub type INT_EVENT0_IMASK_LINOVF_R = crate :: BitReader < INT_EVENT0_IMASK_LINOVF_A > ; # [doc = "Enable LIN Hardware Counter Overflow Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_LINOVF_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_LINOVF_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_LINOVF_SET = 1 , } impl From < INT_EVENT0_IMASK_LINOVF_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_LINOVF_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_LINOVF_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_LINOVF_A { match self . bits { false => INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_CLR , true => INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_linovf_clr (& self) -> bool { * self == INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_linovf_set (& self) -> bool { * self == INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_SET } } # [doc = "Field `INT_EVENT0_IMASK_LINOVF` writer - Enable LIN Hardware Counter Overflow Interrupt."] pub type INT_EVENT0_IMASK_LINOVF_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_LINOVF_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_LINOVF_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_linovf_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_linovf_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_SET) } } # [doc = "Field `INT_EVENT0_IMASK_RXINT` reader - Enable UART Receive Interrupt."] pub type INT_EVENT0_IMASK_RXINT_R = crate :: BitReader < INT_EVENT0_IMASK_RXINT_A > ; # [doc = "Enable UART Receive Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_RXINT_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_RXINT_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_RXINT_SET = 1 , } impl From < INT_EVENT0_IMASK_RXINT_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_RXINT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_RXINT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_RXINT_A { match self . bits { false => INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_CLR , true => INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_rxint_clr (& self) -> bool { * self == INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_rxint_set (& self) -> bool { * self == INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_SET } } # [doc = "Field `INT_EVENT0_IMASK_RXINT` writer - Enable UART Receive Interrupt."] pub type INT_EVENT0_IMASK_RXINT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_RXINT_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_RXINT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_rxint_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_rxint_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_SET) } } # [doc = "Field `INT_EVENT0_IMASK_TXINT` reader - Enable UART Transmit Interrupt."] pub type INT_EVENT0_IMASK_TXINT_R = crate :: BitReader < INT_EVENT0_IMASK_TXINT_A > ; # [doc = "Enable UART Transmit Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_TXINT_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_TXINT_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_TXINT_SET = 1 , } impl From < INT_EVENT0_IMASK_TXINT_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_TXINT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_TXINT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_TXINT_A { match self . bits { false => INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_CLR , true => INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_txint_clr (& self) -> bool { * self == INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_txint_set (& self) -> bool { * self == INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_SET } } # [doc = "Field `INT_EVENT0_IMASK_TXINT` writer - Enable UART Transmit Interrupt."] pub type INT_EVENT0_IMASK_TXINT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_TXINT_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_TXINT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_txint_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_txint_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_SET) } } # [doc = "Field `INT_EVENT0_IMASK_EOT` reader - Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] pub type INT_EVENT0_IMASK_EOT_R = crate :: BitReader < INT_EVENT0_IMASK_EOT_A > ; # [doc = "Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_EOT_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_EOT_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_EOT_SET = 1 , } impl From < INT_EVENT0_IMASK_EOT_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_EOT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_EOT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_EOT_A { match self . bits { false => INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_CLR , true => INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_eot_clr (& self) -> bool { * self == INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_eot_set (& self) -> bool { * self == INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_SET } } # [doc = "Field `INT_EVENT0_IMASK_EOT` writer - Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] pub type INT_EVENT0_IMASK_EOT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_EOT_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_EOT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_eot_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_eot_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_SET) } } # [doc = "Field `INT_EVENT0_IMASK_ADDR_MATCH` reader - Enable Address Match Interrupt."] pub type INT_EVENT0_IMASK_ADDR_MATCH_R = crate :: BitReader < INT_EVENT0_IMASK_ADDR_MATCH_A > ; # [doc = "Enable Address Match Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_ADDR_MATCH_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_ADDR_MATCH_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_ADDR_MATCH_SET = 1 , } impl From < INT_EVENT0_IMASK_ADDR_MATCH_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_ADDR_MATCH_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_ADDR_MATCH_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_ADDR_MATCH_A { match self . bits { false => INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_CLR , true => INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_addr_match_clr (& self) -> bool { * self == INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_addr_match_set (& self) -> bool { * self == INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_SET } } # [doc = "Field `INT_EVENT0_IMASK_ADDR_MATCH` writer - Enable Address Match Interrupt."] pub type INT_EVENT0_IMASK_ADDR_MATCH_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_ADDR_MATCH_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_ADDR_MATCH_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_addr_match_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_addr_match_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_SET) } } # [doc = "Field `INT_EVENT0_IMASK_CTS` reader - Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] pub type INT_EVENT0_IMASK_CTS_R = crate :: BitReader < INT_EVENT0_IMASK_CTS_A > ; # [doc = "Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_CTS_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_CTS_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_CTS_SET = 1 , } impl From < INT_EVENT0_IMASK_CTS_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_CTS_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_CTS_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_CTS_A { match self . bits { false => INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_CLR , true => INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_cts_clr (& self) -> bool { * self == INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_cts_set (& self) -> bool { * self == INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_SET } } # [doc = "Field `INT_EVENT0_IMASK_CTS` writer - Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] pub type INT_EVENT0_IMASK_CTS_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_CTS_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_CTS_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_cts_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_cts_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DMA_DONE_RX` reader - Enable DMA Done on RX Event Channel"] pub type INT_EVENT0_IMASK_DMA_DONE_RX_R = crate :: BitReader < INT_EVENT0_IMASK_DMA_DONE_RX_A > ; # [doc = "Enable DMA Done on RX Event Channel\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DMA_DONE_RX_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DMA_DONE_RX_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DMA_DONE_RX_SET = 1 , } impl From < INT_EVENT0_IMASK_DMA_DONE_RX_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DMA_DONE_RX_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DMA_DONE_RX_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DMA_DONE_RX_A { match self . bits { false => INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_CLR , true => INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dma_done_rx_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dma_done_rx_set (& self) -> bool { * self == INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_SET } } # [doc = "Field `INT_EVENT0_IMASK_DMA_DONE_RX` writer - Enable DMA Done on RX Event Channel"] pub type INT_EVENT0_IMASK_DMA_DONE_RX_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DMA_DONE_RX_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DMA_DONE_RX_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dma_done_rx_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dma_done_rx_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DMA_DONE_TX` reader - Enable DMA Done on TX Event Channel"] pub type INT_EVENT0_IMASK_DMA_DONE_TX_R = crate :: BitReader < INT_EVENT0_IMASK_DMA_DONE_TX_A > ; # [doc = "Enable DMA Done on TX Event Channel\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DMA_DONE_TX_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DMA_DONE_TX_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DMA_DONE_TX_SET = 1 , } impl From < INT_EVENT0_IMASK_DMA_DONE_TX_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DMA_DONE_TX_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DMA_DONE_TX_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DMA_DONE_TX_A { match self . bits { false => INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_CLR , true => INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dma_done_tx_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dma_done_tx_set (& self) -> bool { * self == INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_SET } } # [doc = "Field `INT_EVENT0_IMASK_DMA_DONE_TX` writer - Enable DMA Done on TX Event Channel"] pub type INT_EVENT0_IMASK_DMA_DONE_TX_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DMA_DONE_TX_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DMA_DONE_TX_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dma_done_tx_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dma_done_tx_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_SET) } } # [doc = "Field `INT_EVENT0_IMASK_NERR` reader - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] pub type INT_EVENT0_IMASK_NERR_R = crate :: BitReader < INT_EVENT0_IMASK_NERR_A > ; # [doc = "Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_NERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_NERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_NERR_SET = 1 , } impl From < INT_EVENT0_IMASK_NERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_NERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_NERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_NERR_A { match self . bits { false => INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_CLR , true => INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_nerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_nerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_NERR` writer - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] pub type INT_EVENT0_IMASK_NERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_NERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_NERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_nerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_nerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_SET) } } impl R { # [doc = "Bit 0 - Enable UARTOUT Receive Time-Out Interrupt."] # [inline (always)] pub fn int_event0_imask_rtout (& self) -> INT_EVENT0_IMASK_RTOUT_R { INT_EVENT0_IMASK_RTOUT_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - Enable UART Framing Error Interrupt."] # [inline (always)] pub fn int_event0_imask_frmerr (& self) -> INT_EVENT0_IMASK_FRMERR_R { INT_EVENT0_IMASK_FRMERR_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - Enable UART Parity Error Interrupt."] # [inline (always)] pub fn int_event0_imask_parerr (& self) -> INT_EVENT0_IMASK_PARERR_R { INT_EVENT0_IMASK_PARERR_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - Enable UART Break Error Interrupt."] # [inline (always)] pub fn int_event0_imask_brkerr (& self) -> INT_EVENT0_IMASK_BRKERR_R { INT_EVENT0_IMASK_BRKERR_R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - Enable UART Receive Overrun Error Interrupt."] # [inline (always)] pub fn int_event0_imask_ovrerr (& self) -> INT_EVENT0_IMASK_OVRERR_R { INT_EVENT0_IMASK_OVRERR_R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - Enable Negative Edge on UARTxRXD Interrupt."] # [inline (always)] pub fn int_event0_imask_rxne (& self) -> INT_EVENT0_IMASK_RXNE_R { INT_EVENT0_IMASK_RXNE_R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - Enable Positive Edge on UARTxRXD Interrupt."] # [inline (always)] pub fn int_event0_imask_rxpe (& self) -> INT_EVENT0_IMASK_RXPE_R { INT_EVENT0_IMASK_RXPE_R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - Enable LIN Capture 0 / Match Interrupt ."] # [inline (always)] pub fn int_event0_imask_linc0 (& self) -> INT_EVENT0_IMASK_LINC0_R { INT_EVENT0_IMASK_LINC0_R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - Enable LIN Capture 1 Interrupt."] # [inline (always)] pub fn int_event0_imask_linc1 (& self) -> INT_EVENT0_IMASK_LINC1_R { INT_EVENT0_IMASK_LINC1_R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - Enable LIN Hardware Counter Overflow Interrupt."] # [inline (always)] pub fn int_event0_imask_linovf (& self) -> INT_EVENT0_IMASK_LINOVF_R { INT_EVENT0_IMASK_LINOVF_R :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - Enable UART Receive Interrupt."] # [inline (always)] pub fn int_event0_imask_rxint (& self) -> INT_EVENT0_IMASK_RXINT_R { INT_EVENT0_IMASK_RXINT_R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - Enable UART Transmit Interrupt."] # [inline (always)] pub fn int_event0_imask_txint (& self) -> INT_EVENT0_IMASK_TXINT_R { INT_EVENT0_IMASK_TXINT_R :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] # [inline (always)] pub fn int_event0_imask_eot (& self) -> INT_EVENT0_IMASK_EOT_R { INT_EVENT0_IMASK_EOT_R :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - Enable Address Match Interrupt."] # [inline (always)] pub fn int_event0_imask_addr_match (& self) -> INT_EVENT0_IMASK_ADDR_MATCH_R { INT_EVENT0_IMASK_ADDR_MATCH_R :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 14 - Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] # [inline (always)] pub fn int_event0_imask_cts (& self) -> INT_EVENT0_IMASK_CTS_R { INT_EVENT0_IMASK_CTS_R :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - Enable DMA Done on RX Event Channel"] # [inline (always)] pub fn int_event0_imask_dma_done_rx (& self) -> INT_EVENT0_IMASK_DMA_DONE_RX_R { INT_EVENT0_IMASK_DMA_DONE_RX_R :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bit 16 - Enable DMA Done on TX Event Channel"] # [inline (always)] pub fn int_event0_imask_dma_done_tx (& self) -> INT_EVENT0_IMASK_DMA_DONE_TX_R { INT_EVENT0_IMASK_DMA_DONE_TX_R :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] # [inline (always)] pub fn int_event0_imask_nerr (& self) -> INT_EVENT0_IMASK_NERR_R { INT_EVENT0_IMASK_NERR_R :: new (((self . bits >> 17) & 1) != 0) } } impl W { # [doc = "Bit 0 - Enable UARTOUT Receive Time-Out Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_rtout (& mut self) -> INT_EVENT0_IMASK_RTOUT_W < INT_EVENT0_IMASK_SPEC , 0 > { INT_EVENT0_IMASK_RTOUT_W :: new (self) } # [doc = "Bit 1 - Enable UART Framing Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_frmerr (& mut self) -> INT_EVENT0_IMASK_FRMERR_W < INT_EVENT0_IMASK_SPEC , 1 > { INT_EVENT0_IMASK_FRMERR_W :: new (self) } # [doc = "Bit 2 - Enable UART Parity Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_parerr (& mut self) -> INT_EVENT0_IMASK_PARERR_W < INT_EVENT0_IMASK_SPEC , 2 > { INT_EVENT0_IMASK_PARERR_W :: new (self) } # [doc = "Bit 3 - Enable UART Break Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_brkerr (& mut self) -> INT_EVENT0_IMASK_BRKERR_W < INT_EVENT0_IMASK_SPEC , 3 > { INT_EVENT0_IMASK_BRKERR_W :: new (self) } # [doc = "Bit 4 - Enable UART Receive Overrun Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_ovrerr (& mut self) -> INT_EVENT0_IMASK_OVRERR_W < INT_EVENT0_IMASK_SPEC , 4 > { INT_EVENT0_IMASK_OVRERR_W :: new (self) } # [doc = "Bit 5 - Enable Negative Edge on UARTxRXD Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_rxne (& mut self) -> INT_EVENT0_IMASK_RXNE_W < INT_EVENT0_IMASK_SPEC , 5 > { INT_EVENT0_IMASK_RXNE_W :: new (self) } # [doc = "Bit 6 - Enable Positive Edge on UARTxRXD Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_rxpe (& mut self) -> INT_EVENT0_IMASK_RXPE_W < INT_EVENT0_IMASK_SPEC , 6 > { INT_EVENT0_IMASK_RXPE_W :: new (self) } # [doc = "Bit 7 - Enable LIN Capture 0 / Match Interrupt ."] # [inline (always)] # [must_use] pub fn int_event0_imask_linc0 (& mut self) -> INT_EVENT0_IMASK_LINC0_W < INT_EVENT0_IMASK_SPEC , 7 > { INT_EVENT0_IMASK_LINC0_W :: new (self) } # [doc = "Bit 8 - Enable LIN Capture 1 Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_linc1 (& mut self) -> INT_EVENT0_IMASK_LINC1_W < INT_EVENT0_IMASK_SPEC , 8 > { INT_EVENT0_IMASK_LINC1_W :: new (self) } # [doc = "Bit 9 - Enable LIN Hardware Counter Overflow Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_linovf (& mut self) -> INT_EVENT0_IMASK_LINOVF_W < INT_EVENT0_IMASK_SPEC , 9 > { INT_EVENT0_IMASK_LINOVF_W :: new (self) } # [doc = "Bit 10 - Enable UART Receive Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_rxint (& mut self) -> INT_EVENT0_IMASK_RXINT_W < INT_EVENT0_IMASK_SPEC , 10 > { INT_EVENT0_IMASK_RXINT_W :: new (self) } # [doc = "Bit 11 - Enable UART Transmit Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_txint (& mut self) -> INT_EVENT0_IMASK_TXINT_W < INT_EVENT0_IMASK_SPEC , 11 > { INT_EVENT0_IMASK_TXINT_W :: new (self) } # [doc = "Bit 12 - Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] # [inline (always)] # [must_use] pub fn int_event0_imask_eot (& mut self) -> INT_EVENT0_IMASK_EOT_W < INT_EVENT0_IMASK_SPEC , 12 > { INT_EVENT0_IMASK_EOT_W :: new (self) } # [doc = "Bit 13 - Enable Address Match Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_addr_match (& mut self) -> INT_EVENT0_IMASK_ADDR_MATCH_W < INT_EVENT0_IMASK_SPEC , 13 > { INT_EVENT0_IMASK_ADDR_MATCH_W :: new (self) } # [doc = "Bit 14 - Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] # [inline (always)] # [must_use] pub fn int_event0_imask_cts (& mut self) -> INT_EVENT0_IMASK_CTS_W <'_,  INT_EVENT0_IMASK_SPEC , 14 > { INT_EVENT0_IMASK_CTS_W :: new (self) } # [doc = "Bit 15 - Enable DMA Done on RX Event Channel"] # [inline (always)] # [must_use] pub fn int_event0_imask_dma_done_rx (& mut self) -> INT_EVENT0_IMASK_DMA_DONE_RX_W < INT_EVENT0_IMASK_SPEC , 15 > { INT_EVENT0_IMASK_DMA_DONE_RX_W :: new (self) } # [doc = "Bit 16 - Enable DMA Done on TX Event Channel"] # [inline (always)] # [must_use] pub fn int_event0_imask_dma_done_tx (& mut self) -> INT_EVENT0_IMASK_DMA_DONE_TX_W < INT_EVENT0_IMASK_SPEC , 16 > { INT_EVENT0_IMASK_DMA_DONE_TX_W :: new (self) } # [doc = "Bit 17 - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] # [inline (always)] # [must_use] pub fn int_event0_imask_nerr (& mut self) -> INT_EVENT0_IMASK_NERR_W < INT_EVENT0_IMASK_SPEC , 17 > { INT_EVENT0_IMASK_NERR_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Interrupt mask\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_event0_imask::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_event0_imask::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct INT_EVENT0_IMASK_SPEC ; impl crate :: RegisterSpec for INT_EVENT0_IMASK_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`int_event0_imask::R`](R) reader structure"] impl crate :: Readable for INT_EVENT0_IMASK_SPEC { } # [doc = "`write(|w| ..)` method takes [`int_event0_imask::W`](W) writer structure"] impl crate :: Writable for INT_EVENT0_IMASK_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets INT_EVENT0_IMASK to value 0"] impl crate :: Resettable for INT_EVENT0_IMASK_SPEC { const RESET_VALUE : Self :: Ux = 0 ; }
[INFO] [stdout]   |                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                          +++
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing
[INFO] [stdout]  --> src/uart0/int_event0_imask.rs:1:44224
[INFO] [stdout]   |
[INFO] [stdout] 1 | ..._done_rx (& mut self) -> INT_EVENT0_IMASK_DMA_DONE_RX_W < INT_EVENT0_IMASK_SPEC , 15 > { INT_EVENT0_IMASK_DMA_DONE_RX_W :: new (se...
[INFO] [stdout]   |              ^^^^^^^^^^     ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here
[INFO] [stdout]   |              |
[INFO] [stdout]   |              the lifetime is elided here
[INFO] [stdout]   |
[INFO] [stdout]   = help: the same lifetime is referred to in inconsistent ways, making the signature confusing
[INFO] [stdout] help: use `'_` for type paths
[INFO] [stdout]   |
[INFO] [stdout] 1 | # [doc = "Register `INT_EVENT0_IMASK` reader"] pub type R = crate :: R < INT_EVENT0_IMASK_SPEC > ; # [doc = "Register `INT_EVENT0_IMASK` writer"] pub type W = crate :: W < INT_EVENT0_IMASK_SPEC > ; # [doc = "Field `INT_EVENT0_IMASK_RTOUT` reader - Enable UARTOUT Receive Time-Out Interrupt."] pub type INT_EVENT0_IMASK_RTOUT_R = crate :: BitReader < INT_EVENT0_IMASK_RTOUT_A > ; # [doc = "Enable UARTOUT Receive Time-Out Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_RTOUT_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_RTOUT_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_RTOUT_SET = 1 , } impl From < INT_EVENT0_IMASK_RTOUT_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_RTOUT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_RTOUT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_RTOUT_A { match self . bits { false => INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_CLR , true => INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_rtout_clr (& self) -> bool { * self == INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_rtout_set (& self) -> bool { * self == INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_SET } } # [doc = "Field `INT_EVENT0_IMASK_RTOUT` writer - Enable UARTOUT Receive Time-Out Interrupt."] pub type INT_EVENT0_IMASK_RTOUT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_RTOUT_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_RTOUT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_rtout_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_rtout_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_SET) } } # [doc = "Field `INT_EVENT0_IMASK_FRMERR` reader - Enable UART Framing Error Interrupt."] pub type INT_EVENT0_IMASK_FRMERR_R = crate :: BitReader < INT_EVENT0_IMASK_FRMERR_A > ; # [doc = "Enable UART Framing Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_FRMERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_FRMERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_FRMERR_SET = 1 , } impl From < INT_EVENT0_IMASK_FRMERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_FRMERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_FRMERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_FRMERR_A { match self . bits { false => INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_CLR , true => INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_frmerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_frmerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_FRMERR` writer - Enable UART Framing Error Interrupt."] pub type INT_EVENT0_IMASK_FRMERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_FRMERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_FRMERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_frmerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_frmerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_SET) } } # [doc = "Field `INT_EVENT0_IMASK_PARERR` reader - Enable UART Parity Error Interrupt."] pub type INT_EVENT0_IMASK_PARERR_R = crate :: BitReader < INT_EVENT0_IMASK_PARERR_A > ; # [doc = "Enable UART Parity Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_PARERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_PARERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_PARERR_SET = 1 , } impl From < INT_EVENT0_IMASK_PARERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_PARERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_PARERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_PARERR_A { match self . bits { false => INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_CLR , true => INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_parerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_parerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_PARERR` writer - Enable UART Parity Error Interrupt."] pub type INT_EVENT0_IMASK_PARERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_PARERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_PARERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_parerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_parerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_SET) } } # [doc = "Field `INT_EVENT0_IMASK_BRKERR` reader - Enable UART Break Error Interrupt."] pub type INT_EVENT0_IMASK_BRKERR_R = crate :: BitReader < INT_EVENT0_IMASK_BRKERR_A > ; # [doc = "Enable UART Break Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_BRKERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_BRKERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_BRKERR_SET = 1 , } impl From < INT_EVENT0_IMASK_BRKERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_BRKERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_BRKERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_BRKERR_A { match self . bits { false => INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_CLR , true => INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_brkerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_brkerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_BRKERR` writer - Enable UART Break Error Interrupt."] pub type INT_EVENT0_IMASK_BRKERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_BRKERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_BRKERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_brkerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_brkerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_SET) } } # [doc = "Field `INT_EVENT0_IMASK_OVRERR` reader - Enable UART Receive Overrun Error Interrupt."] pub type INT_EVENT0_IMASK_OVRERR_R = crate :: BitReader < INT_EVENT0_IMASK_OVRERR_A > ; # [doc = "Enable UART Receive Overrun Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_OVRERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_OVRERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_OVRERR_SET = 1 , } impl From < INT_EVENT0_IMASK_OVRERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_OVRERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_OVRERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_OVRERR_A { match self . bits { false => INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_CLR , true => INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_ovrerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_ovrerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_OVRERR` writer - Enable UART Receive Overrun Error Interrupt."] pub type INT_EVENT0_IMASK_OVRERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_OVRERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_OVRERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_ovrerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_ovrerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_SET) } } # [doc = "Field `INT_EVENT0_IMASK_RXNE` reader - Enable Negative Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_IMASK_RXNE_R = crate :: BitReader < INT_EVENT0_IMASK_RXNE_A > ; # [doc = "Enable Negative Edge on UARTxRXD Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_RXNE_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_RXNE_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_RXNE_SET = 1 , } impl From < INT_EVENT0_IMASK_RXNE_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_RXNE_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_RXNE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_RXNE_A { match self . bits { false => INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_CLR , true => INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_rxne_clr (& self) -> bool { * self == INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_rxne_set (& self) -> bool { * self == INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_SET } } # [doc = "Field `INT_EVENT0_IMASK_RXNE` writer - Enable Negative Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_IMASK_RXNE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_RXNE_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_RXNE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_rxne_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_rxne_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_SET) } } # [doc = "Field `INT_EVENT0_IMASK_RXPE` reader - Enable Positive Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_IMASK_RXPE_R = crate :: BitReader < INT_EVENT0_IMASK_RXPE_A > ; # [doc = "Enable Positive Edge on UARTxRXD Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_RXPE_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_RXPE_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_RXPE_SET = 1 , } impl From < INT_EVENT0_IMASK_RXPE_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_RXPE_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_RXPE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_RXPE_A { match self . bits { false => INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_CLR , true => INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_rxpe_clr (& self) -> bool { * self == INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_rxpe_set (& self) -> bool { * self == INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_SET } } # [doc = "Field `INT_EVENT0_IMASK_RXPE` writer - Enable Positive Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_IMASK_RXPE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_RXPE_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_RXPE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_rxpe_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_rxpe_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_SET) } } # [doc = "Field `INT_EVENT0_IMASK_LINC0` reader - Enable LIN Capture 0 / Match Interrupt ."] pub type INT_EVENT0_IMASK_LINC0_R = crate :: BitReader < INT_EVENT0_IMASK_LINC0_A > ; # [doc = "Enable LIN Capture 0 / Match Interrupt .\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_LINC0_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_LINC0_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_LINC0_SET = 1 , } impl From < INT_EVENT0_IMASK_LINC0_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_LINC0_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_LINC0_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_LINC0_A { match self . bits { false => INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_CLR , true => INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_linc0_clr (& self) -> bool { * self == INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_linc0_set (& self) -> bool { * self == INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_SET } } # [doc = "Field `INT_EVENT0_IMASK_LINC0` writer - Enable LIN Capture 0 / Match Interrupt ."] pub type INT_EVENT0_IMASK_LINC0_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_LINC0_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_LINC0_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_linc0_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_linc0_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_SET) } } # [doc = "Field `INT_EVENT0_IMASK_LINC1` reader - Enable LIN Capture 1 Interrupt."] pub type INT_EVENT0_IMASK_LINC1_R = crate :: BitReader < INT_EVENT0_IMASK_LINC1_A > ; # [doc = "Enable LIN Capture 1 Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_LINC1_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_LINC1_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_LINC1_SET = 1 , } impl From < INT_EVENT0_IMASK_LINC1_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_LINC1_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_LINC1_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_LINC1_A { match self . bits { false => INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_CLR , true => INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_linc1_clr (& self) -> bool { * self == INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_linc1_set (& self) -> bool { * self == INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_SET } } # [doc = "Field `INT_EVENT0_IMASK_LINC1` writer - Enable LIN Capture 1 Interrupt."] pub type INT_EVENT0_IMASK_LINC1_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_LINC1_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_LINC1_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_linc1_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_linc1_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_SET) } } # [doc = "Field `INT_EVENT0_IMASK_LINOVF` reader - Enable LIN Hardware Counter Overflow Interrupt."] pub type INT_EVENT0_IMASK_LINOVF_R = crate :: BitReader < INT_EVENT0_IMASK_LINOVF_A > ; # [doc = "Enable LIN Hardware Counter Overflow Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_LINOVF_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_LINOVF_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_LINOVF_SET = 1 , } impl From < INT_EVENT0_IMASK_LINOVF_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_LINOVF_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_LINOVF_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_LINOVF_A { match self . bits { false => INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_CLR , true => INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_linovf_clr (& self) -> bool { * self == INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_linovf_set (& self) -> bool { * self == INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_SET } } # [doc = "Field `INT_EVENT0_IMASK_LINOVF` writer - Enable LIN Hardware Counter Overflow Interrupt."] pub type INT_EVENT0_IMASK_LINOVF_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_LINOVF_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_LINOVF_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_linovf_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_linovf_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_SET) } } # [doc = "Field `INT_EVENT0_IMASK_RXINT` reader - Enable UART Receive Interrupt."] pub type INT_EVENT0_IMASK_RXINT_R = crate :: BitReader < INT_EVENT0_IMASK_RXINT_A > ; # [doc = "Enable UART Receive Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_RXINT_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_RXINT_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_RXINT_SET = 1 , } impl From < INT_EVENT0_IMASK_RXINT_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_RXINT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_RXINT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_RXINT_A { match self . bits { false => INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_CLR , true => INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_rxint_clr (& self) -> bool { * self == INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_rxint_set (& self) -> bool { * self == INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_SET } } # [doc = "Field `INT_EVENT0_IMASK_RXINT` writer - Enable UART Receive Interrupt."] pub type INT_EVENT0_IMASK_RXINT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_RXINT_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_RXINT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_rxint_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_rxint_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_SET) } } # [doc = "Field `INT_EVENT0_IMASK_TXINT` reader - Enable UART Transmit Interrupt."] pub type INT_EVENT0_IMASK_TXINT_R = crate :: BitReader < INT_EVENT0_IMASK_TXINT_A > ; # [doc = "Enable UART Transmit Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_TXINT_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_TXINT_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_TXINT_SET = 1 , } impl From < INT_EVENT0_IMASK_TXINT_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_TXINT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_TXINT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_TXINT_A { match self . bits { false => INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_CLR , true => INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_txint_clr (& self) -> bool { * self == INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_txint_set (& self) -> bool { * self == INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_SET } } # [doc = "Field `INT_EVENT0_IMASK_TXINT` writer - Enable UART Transmit Interrupt."] pub type INT_EVENT0_IMASK_TXINT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_TXINT_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_TXINT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_txint_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_txint_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_SET) } } # [doc = "Field `INT_EVENT0_IMASK_EOT` reader - Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] pub type INT_EVENT0_IMASK_EOT_R = crate :: BitReader < INT_EVENT0_IMASK_EOT_A > ; # [doc = "Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_EOT_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_EOT_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_EOT_SET = 1 , } impl From < INT_EVENT0_IMASK_EOT_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_EOT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_EOT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_EOT_A { match self . bits { false => INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_CLR , true => INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_eot_clr (& self) -> bool { * self == INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_eot_set (& self) -> bool { * self == INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_SET } } # [doc = "Field `INT_EVENT0_IMASK_EOT` writer - Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] pub type INT_EVENT0_IMASK_EOT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_EOT_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_EOT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_eot_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_eot_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_SET) } } # [doc = "Field `INT_EVENT0_IMASK_ADDR_MATCH` reader - Enable Address Match Interrupt."] pub type INT_EVENT0_IMASK_ADDR_MATCH_R = crate :: BitReader < INT_EVENT0_IMASK_ADDR_MATCH_A > ; # [doc = "Enable Address Match Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_ADDR_MATCH_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_ADDR_MATCH_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_ADDR_MATCH_SET = 1 , } impl From < INT_EVENT0_IMASK_ADDR_MATCH_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_ADDR_MATCH_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_ADDR_MATCH_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_ADDR_MATCH_A { match self . bits { false => INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_CLR , true => INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_addr_match_clr (& self) -> bool { * self == INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_addr_match_set (& self) -> bool { * self == INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_SET } } # [doc = "Field `INT_EVENT0_IMASK_ADDR_MATCH` writer - Enable Address Match Interrupt."] pub type INT_EVENT0_IMASK_ADDR_MATCH_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_ADDR_MATCH_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_ADDR_MATCH_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_addr_match_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_addr_match_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_SET) } } # [doc = "Field `INT_EVENT0_IMASK_CTS` reader - Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] pub type INT_EVENT0_IMASK_CTS_R = crate :: BitReader < INT_EVENT0_IMASK_CTS_A > ; # [doc = "Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_CTS_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_CTS_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_CTS_SET = 1 , } impl From < INT_EVENT0_IMASK_CTS_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_CTS_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_CTS_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_CTS_A { match self . bits { false => INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_CLR , true => INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_cts_clr (& self) -> bool { * self == INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_cts_set (& self) -> bool { * self == INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_SET } } # [doc = "Field `INT_EVENT0_IMASK_CTS` writer - Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] pub type INT_EVENT0_IMASK_CTS_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_CTS_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_CTS_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_cts_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_cts_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DMA_DONE_RX` reader - Enable DMA Done on RX Event Channel"] pub type INT_EVENT0_IMASK_DMA_DONE_RX_R = crate :: BitReader < INT_EVENT0_IMASK_DMA_DONE_RX_A > ; # [doc = "Enable DMA Done on RX Event Channel\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DMA_DONE_RX_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DMA_DONE_RX_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DMA_DONE_RX_SET = 1 , } impl From < INT_EVENT0_IMASK_DMA_DONE_RX_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DMA_DONE_RX_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DMA_DONE_RX_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DMA_DONE_RX_A { match self . bits { false => INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_CLR , true => INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dma_done_rx_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dma_done_rx_set (& self) -> bool { * self == INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_SET } } # [doc = "Field `INT_EVENT0_IMASK_DMA_DONE_RX` writer - Enable DMA Done on RX Event Channel"] pub type INT_EVENT0_IMASK_DMA_DONE_RX_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DMA_DONE_RX_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DMA_DONE_RX_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dma_done_rx_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dma_done_rx_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DMA_DONE_TX` reader - Enable DMA Done on TX Event Channel"] pub type INT_EVENT0_IMASK_DMA_DONE_TX_R = crate :: BitReader < INT_EVENT0_IMASK_DMA_DONE_TX_A > ; # [doc = "Enable DMA Done on TX Event Channel\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DMA_DONE_TX_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DMA_DONE_TX_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DMA_DONE_TX_SET = 1 , } impl From < INT_EVENT0_IMASK_DMA_DONE_TX_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DMA_DONE_TX_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DMA_DONE_TX_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DMA_DONE_TX_A { match self . bits { false => INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_CLR , true => INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dma_done_tx_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dma_done_tx_set (& self) -> bool { * self == INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_SET } } # [doc = "Field `INT_EVENT0_IMASK_DMA_DONE_TX` writer - Enable DMA Done on TX Event Channel"] pub type INT_EVENT0_IMASK_DMA_DONE_TX_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DMA_DONE_TX_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DMA_DONE_TX_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dma_done_tx_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dma_done_tx_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_SET) } } # [doc = "Field `INT_EVENT0_IMASK_NERR` reader - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] pub type INT_EVENT0_IMASK_NERR_R = crate :: BitReader < INT_EVENT0_IMASK_NERR_A > ; # [doc = "Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_NERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_NERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_NERR_SET = 1 , } impl From < INT_EVENT0_IMASK_NERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_NERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_NERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_NERR_A { match self . bits { false => INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_CLR , true => INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_nerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_nerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_NERR` writer - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] pub type INT_EVENT0_IMASK_NERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_NERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_NERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_nerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_nerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_SET) } } impl R { # [doc = "Bit 0 - Enable UARTOUT Receive Time-Out Interrupt."] # [inline (always)] pub fn int_event0_imask_rtout (& self) -> INT_EVENT0_IMASK_RTOUT_R { INT_EVENT0_IMASK_RTOUT_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - Enable UART Framing Error Interrupt."] # [inline (always)] pub fn int_event0_imask_frmerr (& self) -> INT_EVENT0_IMASK_FRMERR_R { INT_EVENT0_IMASK_FRMERR_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - Enable UART Parity Error Interrupt."] # [inline (always)] pub fn int_event0_imask_parerr (& self) -> INT_EVENT0_IMASK_PARERR_R { INT_EVENT0_IMASK_PARERR_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - Enable UART Break Error Interrupt."] # [inline (always)] pub fn int_event0_imask_brkerr (& self) -> INT_EVENT0_IMASK_BRKERR_R { INT_EVENT0_IMASK_BRKERR_R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - Enable UART Receive Overrun Error Interrupt."] # [inline (always)] pub fn int_event0_imask_ovrerr (& self) -> INT_EVENT0_IMASK_OVRERR_R { INT_EVENT0_IMASK_OVRERR_R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - Enable Negative Edge on UARTxRXD Interrupt."] # [inline (always)] pub fn int_event0_imask_rxne (& self) -> INT_EVENT0_IMASK_RXNE_R { INT_EVENT0_IMASK_RXNE_R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - Enable Positive Edge on UARTxRXD Interrupt."] # [inline (always)] pub fn int_event0_imask_rxpe (& self) -> INT_EVENT0_IMASK_RXPE_R { INT_EVENT0_IMASK_RXPE_R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - Enable LIN Capture 0 / Match Interrupt ."] # [inline (always)] pub fn int_event0_imask_linc0 (& self) -> INT_EVENT0_IMASK_LINC0_R { INT_EVENT0_IMASK_LINC0_R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - Enable LIN Capture 1 Interrupt."] # [inline (always)] pub fn int_event0_imask_linc1 (& self) -> INT_EVENT0_IMASK_LINC1_R { INT_EVENT0_IMASK_LINC1_R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - Enable LIN Hardware Counter Overflow Interrupt."] # [inline (always)] pub fn int_event0_imask_linovf (& self) -> INT_EVENT0_IMASK_LINOVF_R { INT_EVENT0_IMASK_LINOVF_R :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - Enable UART Receive Interrupt."] # [inline (always)] pub fn int_event0_imask_rxint (& self) -> INT_EVENT0_IMASK_RXINT_R { INT_EVENT0_IMASK_RXINT_R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - Enable UART Transmit Interrupt."] # [inline (always)] pub fn int_event0_imask_txint (& self) -> INT_EVENT0_IMASK_TXINT_R { INT_EVENT0_IMASK_TXINT_R :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] # [inline (always)] pub fn int_event0_imask_eot (& self) -> INT_EVENT0_IMASK_EOT_R { INT_EVENT0_IMASK_EOT_R :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - Enable Address Match Interrupt."] # [inline (always)] pub fn int_event0_imask_addr_match (& self) -> INT_EVENT0_IMASK_ADDR_MATCH_R { INT_EVENT0_IMASK_ADDR_MATCH_R :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 14 - Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] # [inline (always)] pub fn int_event0_imask_cts (& self) -> INT_EVENT0_IMASK_CTS_R { INT_EVENT0_IMASK_CTS_R :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - Enable DMA Done on RX Event Channel"] # [inline (always)] pub fn int_event0_imask_dma_done_rx (& self) -> INT_EVENT0_IMASK_DMA_DONE_RX_R { INT_EVENT0_IMASK_DMA_DONE_RX_R :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bit 16 - Enable DMA Done on TX Event Channel"] # [inline (always)] pub fn int_event0_imask_dma_done_tx (& self) -> INT_EVENT0_IMASK_DMA_DONE_TX_R { INT_EVENT0_IMASK_DMA_DONE_TX_R :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] # [inline (always)] pub fn int_event0_imask_nerr (& self) -> INT_EVENT0_IMASK_NERR_R { INT_EVENT0_IMASK_NERR_R :: new (((self . bits >> 17) & 1) != 0) } } impl W { # [doc = "Bit 0 - Enable UARTOUT Receive Time-Out Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_rtout (& mut self) -> INT_EVENT0_IMASK_RTOUT_W < INT_EVENT0_IMASK_SPEC , 0 > { INT_EVENT0_IMASK_RTOUT_W :: new (self) } # [doc = "Bit 1 - Enable UART Framing Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_frmerr (& mut self) -> INT_EVENT0_IMASK_FRMERR_W < INT_EVENT0_IMASK_SPEC , 1 > { INT_EVENT0_IMASK_FRMERR_W :: new (self) } # [doc = "Bit 2 - Enable UART Parity Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_parerr (& mut self) -> INT_EVENT0_IMASK_PARERR_W < INT_EVENT0_IMASK_SPEC , 2 > { INT_EVENT0_IMASK_PARERR_W :: new (self) } # [doc = "Bit 3 - Enable UART Break Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_brkerr (& mut self) -> INT_EVENT0_IMASK_BRKERR_W < INT_EVENT0_IMASK_SPEC , 3 > { INT_EVENT0_IMASK_BRKERR_W :: new (self) } # [doc = "Bit 4 - Enable UART Receive Overrun Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_ovrerr (& mut self) -> INT_EVENT0_IMASK_OVRERR_W < INT_EVENT0_IMASK_SPEC , 4 > { INT_EVENT0_IMASK_OVRERR_W :: new (self) } # [doc = "Bit 5 - Enable Negative Edge on UARTxRXD Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_rxne (& mut self) -> INT_EVENT0_IMASK_RXNE_W < INT_EVENT0_IMASK_SPEC , 5 > { INT_EVENT0_IMASK_RXNE_W :: new (self) } # [doc = "Bit 6 - Enable Positive Edge on UARTxRXD Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_rxpe (& mut self) -> INT_EVENT0_IMASK_RXPE_W < INT_EVENT0_IMASK_SPEC , 6 > { INT_EVENT0_IMASK_RXPE_W :: new (self) } # [doc = "Bit 7 - Enable LIN Capture 0 / Match Interrupt ."] # [inline (always)] # [must_use] pub fn int_event0_imask_linc0 (& mut self) -> INT_EVENT0_IMASK_LINC0_W < INT_EVENT0_IMASK_SPEC , 7 > { INT_EVENT0_IMASK_LINC0_W :: new (self) } # [doc = "Bit 8 - Enable LIN Capture 1 Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_linc1 (& mut self) -> INT_EVENT0_IMASK_LINC1_W < INT_EVENT0_IMASK_SPEC , 8 > { INT_EVENT0_IMASK_LINC1_W :: new (self) } # [doc = "Bit 9 - Enable LIN Hardware Counter Overflow Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_linovf (& mut self) -> INT_EVENT0_IMASK_LINOVF_W < INT_EVENT0_IMASK_SPEC , 9 > { INT_EVENT0_IMASK_LINOVF_W :: new (self) } # [doc = "Bit 10 - Enable UART Receive Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_rxint (& mut self) -> INT_EVENT0_IMASK_RXINT_W < INT_EVENT0_IMASK_SPEC , 10 > { INT_EVENT0_IMASK_RXINT_W :: new (self) } # [doc = "Bit 11 - Enable UART Transmit Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_txint (& mut self) -> INT_EVENT0_IMASK_TXINT_W < INT_EVENT0_IMASK_SPEC , 11 > { INT_EVENT0_IMASK_TXINT_W :: new (self) } # [doc = "Bit 12 - Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] # [inline (always)] # [must_use] pub fn int_event0_imask_eot (& mut self) -> INT_EVENT0_IMASK_EOT_W < INT_EVENT0_IMASK_SPEC , 12 > { INT_EVENT0_IMASK_EOT_W :: new (self) } # [doc = "Bit 13 - Enable Address Match Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_addr_match (& mut self) -> INT_EVENT0_IMASK_ADDR_MATCH_W < INT_EVENT0_IMASK_SPEC , 13 > { INT_EVENT0_IMASK_ADDR_MATCH_W :: new (self) } # [doc = "Bit 14 - Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] # [inline (always)] # [must_use] pub fn int_event0_imask_cts (& mut self) -> INT_EVENT0_IMASK_CTS_W < INT_EVENT0_IMASK_SPEC , 14 > { INT_EVENT0_IMASK_CTS_W :: new (self) } # [doc = "Bit 15 - Enable DMA Done on RX Event Channel"] # [inline (always)] # [must_use] pub fn int_event0_imask_dma_done_rx (& mut self) -> INT_EVENT0_IMASK_DMA_DONE_RX_W <'_,  INT_EVENT0_IMASK_SPEC , 15 > { INT_EVENT0_IMASK_DMA_DONE_RX_W :: new (self) } # [doc = "Bit 16 - Enable DMA Done on TX Event Channel"] # [inline (always)] # [must_use] pub fn int_event0_imask_dma_done_tx (& mut self) -> INT_EVENT0_IMASK_DMA_DONE_TX_W < INT_EVENT0_IMASK_SPEC , 16 > { INT_EVENT0_IMASK_DMA_DONE_TX_W :: new (self) } # [doc = "Bit 17 - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] # [inline (always)] # [must_use] pub fn int_event0_imask_nerr (& mut self) -> INT_EVENT0_IMASK_NERR_W < INT_EVENT0_IMASK_SPEC , 17 > { INT_EVENT0_IMASK_NERR_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Interrupt mask\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_event0_imask::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_event0_imask::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct INT_EVENT0_IMASK_SPEC ; impl crate :: RegisterSpec for INT_EVENT0_IMASK_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`int_event0_imask::R`](R) reader structure"] impl crate :: Readable for INT_EVENT0_IMASK_SPEC { } # [doc = "`write(|w| ..)` method takes [`int_event0_imask::W`](W) writer structure"] impl crate :: Writable for INT_EVENT0_IMASK_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets INT_EVENT0_IMASK to value 0"] impl crate :: Resettable for INT_EVENT0_IMASK_SPEC { const RESET_VALUE : Self :: Ux = 0 ; }
[INFO] [stdout]   |                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                               +++
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing
[INFO] [stdout]  --> src/uart0/int_event0_imask.rs:1:44477
[INFO] [stdout]   |
[INFO] [stdout] 1 | ..._done_tx (& mut self) -> INT_EVENT0_IMASK_DMA_DONE_TX_W < INT_EVENT0_IMASK_SPEC , 16 > { INT_EVENT0_IMASK_DMA_DONE_TX_W :: new (se...
[INFO] [stdout]   |              ^^^^^^^^^^     ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here
[INFO] [stdout]   |              |
[INFO] [stdout]   |              the lifetime is elided here
[INFO] [stdout]   |
[INFO] [stdout]   = help: the same lifetime is referred to in inconsistent ways, making the signature confusing
[INFO] [stdout] help: use `'_` for type paths
[INFO] [stdout]   |
[INFO] [stdout] 1 | # [doc = "Register `INT_EVENT0_IMASK` reader"] pub type R = crate :: R < INT_EVENT0_IMASK_SPEC > ; # [doc = "Register `INT_EVENT0_IMASK` writer"] pub type W = crate :: W < INT_EVENT0_IMASK_SPEC > ; # [doc = "Field `INT_EVENT0_IMASK_RTOUT` reader - Enable UARTOUT Receive Time-Out Interrupt."] pub type INT_EVENT0_IMASK_RTOUT_R = crate :: BitReader < INT_EVENT0_IMASK_RTOUT_A > ; # [doc = "Enable UARTOUT Receive Time-Out Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_RTOUT_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_RTOUT_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_RTOUT_SET = 1 , } impl From < INT_EVENT0_IMASK_RTOUT_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_RTOUT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_RTOUT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_RTOUT_A { match self . bits { false => INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_CLR , true => INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_rtout_clr (& self) -> bool { * self == INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_rtout_set (& self) -> bool { * self == INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_SET } } # [doc = "Field `INT_EVENT0_IMASK_RTOUT` writer - Enable UARTOUT Receive Time-Out Interrupt."] pub type INT_EVENT0_IMASK_RTOUT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_RTOUT_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_RTOUT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_rtout_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_rtout_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_SET) } } # [doc = "Field `INT_EVENT0_IMASK_FRMERR` reader - Enable UART Framing Error Interrupt."] pub type INT_EVENT0_IMASK_FRMERR_R = crate :: BitReader < INT_EVENT0_IMASK_FRMERR_A > ; # [doc = "Enable UART Framing Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_FRMERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_FRMERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_FRMERR_SET = 1 , } impl From < INT_EVENT0_IMASK_FRMERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_FRMERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_FRMERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_FRMERR_A { match self . bits { false => INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_CLR , true => INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_frmerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_frmerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_FRMERR` writer - Enable UART Framing Error Interrupt."] pub type INT_EVENT0_IMASK_FRMERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_FRMERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_FRMERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_frmerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_frmerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_SET) } } # [doc = "Field `INT_EVENT0_IMASK_PARERR` reader - Enable UART Parity Error Interrupt."] pub type INT_EVENT0_IMASK_PARERR_R = crate :: BitReader < INT_EVENT0_IMASK_PARERR_A > ; # [doc = "Enable UART Parity Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_PARERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_PARERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_PARERR_SET = 1 , } impl From < INT_EVENT0_IMASK_PARERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_PARERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_PARERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_PARERR_A { match self . bits { false => INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_CLR , true => INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_parerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_parerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_PARERR` writer - Enable UART Parity Error Interrupt."] pub type INT_EVENT0_IMASK_PARERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_PARERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_PARERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_parerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_parerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_SET) } } # [doc = "Field `INT_EVENT0_IMASK_BRKERR` reader - Enable UART Break Error Interrupt."] pub type INT_EVENT0_IMASK_BRKERR_R = crate :: BitReader < INT_EVENT0_IMASK_BRKERR_A > ; # [doc = "Enable UART Break Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_BRKERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_BRKERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_BRKERR_SET = 1 , } impl From < INT_EVENT0_IMASK_BRKERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_BRKERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_BRKERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_BRKERR_A { match self . bits { false => INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_CLR , true => INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_brkerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_brkerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_BRKERR` writer - Enable UART Break Error Interrupt."] pub type INT_EVENT0_IMASK_BRKERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_BRKERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_BRKERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_brkerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_brkerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_SET) } } # [doc = "Field `INT_EVENT0_IMASK_OVRERR` reader - Enable UART Receive Overrun Error Interrupt."] pub type INT_EVENT0_IMASK_OVRERR_R = crate :: BitReader < INT_EVENT0_IMASK_OVRERR_A > ; # [doc = "Enable UART Receive Overrun Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_OVRERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_OVRERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_OVRERR_SET = 1 , } impl From < INT_EVENT0_IMASK_OVRERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_OVRERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_OVRERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_OVRERR_A { match self . bits { false => INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_CLR , true => INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_ovrerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_ovrerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_OVRERR` writer - Enable UART Receive Overrun Error Interrupt."] pub type INT_EVENT0_IMASK_OVRERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_OVRERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_OVRERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_ovrerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_ovrerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_SET) } } # [doc = "Field `INT_EVENT0_IMASK_RXNE` reader - Enable Negative Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_IMASK_RXNE_R = crate :: BitReader < INT_EVENT0_IMASK_RXNE_A > ; # [doc = "Enable Negative Edge on UARTxRXD Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_RXNE_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_RXNE_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_RXNE_SET = 1 , } impl From < INT_EVENT0_IMASK_RXNE_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_RXNE_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_RXNE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_RXNE_A { match self . bits { false => INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_CLR , true => INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_rxne_clr (& self) -> bool { * self == INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_rxne_set (& self) -> bool { * self == INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_SET } } # [doc = "Field `INT_EVENT0_IMASK_RXNE` writer - Enable Negative Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_IMASK_RXNE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_RXNE_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_RXNE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_rxne_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_rxne_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_SET) } } # [doc = "Field `INT_EVENT0_IMASK_RXPE` reader - Enable Positive Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_IMASK_RXPE_R = crate :: BitReader < INT_EVENT0_IMASK_RXPE_A > ; # [doc = "Enable Positive Edge on UARTxRXD Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_RXPE_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_RXPE_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_RXPE_SET = 1 , } impl From < INT_EVENT0_IMASK_RXPE_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_RXPE_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_RXPE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_RXPE_A { match self . bits { false => INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_CLR , true => INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_rxpe_clr (& self) -> bool { * self == INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_rxpe_set (& self) -> bool { * self == INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_SET } } # [doc = "Field `INT_EVENT0_IMASK_RXPE` writer - Enable Positive Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_IMASK_RXPE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_RXPE_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_RXPE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_rxpe_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_rxpe_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_SET) } } # [doc = "Field `INT_EVENT0_IMASK_LINC0` reader - Enable LIN Capture 0 / Match Interrupt ."] pub type INT_EVENT0_IMASK_LINC0_R = crate :: BitReader < INT_EVENT0_IMASK_LINC0_A > ; # [doc = "Enable LIN Capture 0 / Match Interrupt .\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_LINC0_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_LINC0_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_LINC0_SET = 1 , } impl From < INT_EVENT0_IMASK_LINC0_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_LINC0_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_LINC0_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_LINC0_A { match self . bits { false => INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_CLR , true => INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_linc0_clr (& self) -> bool { * self == INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_linc0_set (& self) -> bool { * self == INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_SET } } # [doc = "Field `INT_EVENT0_IMASK_LINC0` writer - Enable LIN Capture 0 / Match Interrupt ."] pub type INT_EVENT0_IMASK_LINC0_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_LINC0_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_LINC0_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_linc0_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_linc0_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_SET) } } # [doc = "Field `INT_EVENT0_IMASK_LINC1` reader - Enable LIN Capture 1 Interrupt."] pub type INT_EVENT0_IMASK_LINC1_R = crate :: BitReader < INT_EVENT0_IMASK_LINC1_A > ; # [doc = "Enable LIN Capture 1 Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_LINC1_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_LINC1_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_LINC1_SET = 1 , } impl From < INT_EVENT0_IMASK_LINC1_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_LINC1_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_LINC1_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_LINC1_A { match self . bits { false => INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_CLR , true => INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_linc1_clr (& self) -> bool { * self == INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_linc1_set (& self) -> bool { * self == INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_SET } } # [doc = "Field `INT_EVENT0_IMASK_LINC1` writer - Enable LIN Capture 1 Interrupt."] pub type INT_EVENT0_IMASK_LINC1_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_LINC1_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_LINC1_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_linc1_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_linc1_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_SET) } } # [doc = "Field `INT_EVENT0_IMASK_LINOVF` reader - Enable LIN Hardware Counter Overflow Interrupt."] pub type INT_EVENT0_IMASK_LINOVF_R = crate :: BitReader < INT_EVENT0_IMASK_LINOVF_A > ; # [doc = "Enable LIN Hardware Counter Overflow Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_LINOVF_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_LINOVF_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_LINOVF_SET = 1 , } impl From < INT_EVENT0_IMASK_LINOVF_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_LINOVF_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_LINOVF_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_LINOVF_A { match self . bits { false => INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_CLR , true => INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_linovf_clr (& self) -> bool { * self == INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_linovf_set (& self) -> bool { * self == INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_SET } } # [doc = "Field `INT_EVENT0_IMASK_LINOVF` writer - Enable LIN Hardware Counter Overflow Interrupt."] pub type INT_EVENT0_IMASK_LINOVF_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_LINOVF_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_LINOVF_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_linovf_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_linovf_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_SET) } } # [doc = "Field `INT_EVENT0_IMASK_RXINT` reader - Enable UART Receive Interrupt."] pub type INT_EVENT0_IMASK_RXINT_R = crate :: BitReader < INT_EVENT0_IMASK_RXINT_A > ; # [doc = "Enable UART Receive Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_RXINT_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_RXINT_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_RXINT_SET = 1 , } impl From < INT_EVENT0_IMASK_RXINT_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_RXINT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_RXINT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_RXINT_A { match self . bits { false => INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_CLR , true => INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_rxint_clr (& self) -> bool { * self == INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_rxint_set (& self) -> bool { * self == INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_SET } } # [doc = "Field `INT_EVENT0_IMASK_RXINT` writer - Enable UART Receive Interrupt."] pub type INT_EVENT0_IMASK_RXINT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_RXINT_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_RXINT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_rxint_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_rxint_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_SET) } } # [doc = "Field `INT_EVENT0_IMASK_TXINT` reader - Enable UART Transmit Interrupt."] pub type INT_EVENT0_IMASK_TXINT_R = crate :: BitReader < INT_EVENT0_IMASK_TXINT_A > ; # [doc = "Enable UART Transmit Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_TXINT_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_TXINT_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_TXINT_SET = 1 , } impl From < INT_EVENT0_IMASK_TXINT_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_TXINT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_TXINT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_TXINT_A { match self . bits { false => INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_CLR , true => INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_txint_clr (& self) -> bool { * self == INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_txint_set (& self) -> bool { * self == INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_SET } } # [doc = "Field `INT_EVENT0_IMASK_TXINT` writer - Enable UART Transmit Interrupt."] pub type INT_EVENT0_IMASK_TXINT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_TXINT_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_TXINT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_txint_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_txint_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_SET) } } # [doc = "Field `INT_EVENT0_IMASK_EOT` reader - Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] pub type INT_EVENT0_IMASK_EOT_R = crate :: BitReader < INT_EVENT0_IMASK_EOT_A > ; # [doc = "Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_EOT_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_EOT_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_EOT_SET = 1 , } impl From < INT_EVENT0_IMASK_EOT_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_EOT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_EOT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_EOT_A { match self . bits { false => INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_CLR , true => INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_eot_clr (& self) -> bool { * self == INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_eot_set (& self) -> bool { * self == INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_SET } } # [doc = "Field `INT_EVENT0_IMASK_EOT` writer - Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] pub type INT_EVENT0_IMASK_EOT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_EOT_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_EOT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_eot_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_eot_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_SET) } } # [doc = "Field `INT_EVENT0_IMASK_ADDR_MATCH` reader - Enable Address Match Interrupt."] pub type INT_EVENT0_IMASK_ADDR_MATCH_R = crate :: BitReader < INT_EVENT0_IMASK_ADDR_MATCH_A > ; # [doc = "Enable Address Match Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_ADDR_MATCH_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_ADDR_MATCH_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_ADDR_MATCH_SET = 1 , } impl From < INT_EVENT0_IMASK_ADDR_MATCH_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_ADDR_MATCH_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_ADDR_MATCH_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_ADDR_MATCH_A { match self . bits { false => INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_CLR , true => INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_addr_match_clr (& self) -> bool { * self == INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_addr_match_set (& self) -> bool { * self == INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_SET } } # [doc = "Field `INT_EVENT0_IMASK_ADDR_MATCH` writer - Enable Address Match Interrupt."] pub type INT_EVENT0_IMASK_ADDR_MATCH_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_ADDR_MATCH_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_ADDR_MATCH_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_addr_match_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_addr_match_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_SET) } } # [doc = "Field `INT_EVENT0_IMASK_CTS` reader - Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] pub type INT_EVENT0_IMASK_CTS_R = crate :: BitReader < INT_EVENT0_IMASK_CTS_A > ; # [doc = "Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_CTS_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_CTS_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_CTS_SET = 1 , } impl From < INT_EVENT0_IMASK_CTS_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_CTS_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_CTS_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_CTS_A { match self . bits { false => INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_CLR , true => INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_cts_clr (& self) -> bool { * self == INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_cts_set (& self) -> bool { * self == INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_SET } } # [doc = "Field `INT_EVENT0_IMASK_CTS` writer - Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] pub type INT_EVENT0_IMASK_CTS_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_CTS_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_CTS_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_cts_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_cts_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DMA_DONE_RX` reader - Enable DMA Done on RX Event Channel"] pub type INT_EVENT0_IMASK_DMA_DONE_RX_R = crate :: BitReader < INT_EVENT0_IMASK_DMA_DONE_RX_A > ; # [doc = "Enable DMA Done on RX Event Channel\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DMA_DONE_RX_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DMA_DONE_RX_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DMA_DONE_RX_SET = 1 , } impl From < INT_EVENT0_IMASK_DMA_DONE_RX_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DMA_DONE_RX_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DMA_DONE_RX_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DMA_DONE_RX_A { match self . bits { false => INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_CLR , true => INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dma_done_rx_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dma_done_rx_set (& self) -> bool { * self == INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_SET } } # [doc = "Field `INT_EVENT0_IMASK_DMA_DONE_RX` writer - Enable DMA Done on RX Event Channel"] pub type INT_EVENT0_IMASK_DMA_DONE_RX_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DMA_DONE_RX_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DMA_DONE_RX_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dma_done_rx_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dma_done_rx_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DMA_DONE_TX` reader - Enable DMA Done on TX Event Channel"] pub type INT_EVENT0_IMASK_DMA_DONE_TX_R = crate :: BitReader < INT_EVENT0_IMASK_DMA_DONE_TX_A > ; # [doc = "Enable DMA Done on TX Event Channel\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DMA_DONE_TX_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DMA_DONE_TX_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DMA_DONE_TX_SET = 1 , } impl From < INT_EVENT0_IMASK_DMA_DONE_TX_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DMA_DONE_TX_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DMA_DONE_TX_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DMA_DONE_TX_A { match self . bits { false => INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_CLR , true => INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dma_done_tx_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dma_done_tx_set (& self) -> bool { * self == INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_SET } } # [doc = "Field `INT_EVENT0_IMASK_DMA_DONE_TX` writer - Enable DMA Done on TX Event Channel"] pub type INT_EVENT0_IMASK_DMA_DONE_TX_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DMA_DONE_TX_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DMA_DONE_TX_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dma_done_tx_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dma_done_tx_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_SET) } } # [doc = "Field `INT_EVENT0_IMASK_NERR` reader - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] pub type INT_EVENT0_IMASK_NERR_R = crate :: BitReader < INT_EVENT0_IMASK_NERR_A > ; # [doc = "Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_NERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_NERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_NERR_SET = 1 , } impl From < INT_EVENT0_IMASK_NERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_NERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_NERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_NERR_A { match self . bits { false => INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_CLR , true => INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_nerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_nerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_NERR` writer - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] pub type INT_EVENT0_IMASK_NERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_NERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_NERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_nerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_nerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_SET) } } impl R { # [doc = "Bit 0 - Enable UARTOUT Receive Time-Out Interrupt."] # [inline (always)] pub fn int_event0_imask_rtout (& self) -> INT_EVENT0_IMASK_RTOUT_R { INT_EVENT0_IMASK_RTOUT_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - Enable UART Framing Error Interrupt."] # [inline (always)] pub fn int_event0_imask_frmerr (& self) -> INT_EVENT0_IMASK_FRMERR_R { INT_EVENT0_IMASK_FRMERR_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - Enable UART Parity Error Interrupt."] # [inline (always)] pub fn int_event0_imask_parerr (& self) -> INT_EVENT0_IMASK_PARERR_R { INT_EVENT0_IMASK_PARERR_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - Enable UART Break Error Interrupt."] # [inline (always)] pub fn int_event0_imask_brkerr (& self) -> INT_EVENT0_IMASK_BRKERR_R { INT_EVENT0_IMASK_BRKERR_R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - Enable UART Receive Overrun Error Interrupt."] # [inline (always)] pub fn int_event0_imask_ovrerr (& self) -> INT_EVENT0_IMASK_OVRERR_R { INT_EVENT0_IMASK_OVRERR_R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - Enable Negative Edge on UARTxRXD Interrupt."] # [inline (always)] pub fn int_event0_imask_rxne (& self) -> INT_EVENT0_IMASK_RXNE_R { INT_EVENT0_IMASK_RXNE_R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - Enable Positive Edge on UARTxRXD Interrupt."] # [inline (always)] pub fn int_event0_imask_rxpe (& self) -> INT_EVENT0_IMASK_RXPE_R { INT_EVENT0_IMASK_RXPE_R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - Enable LIN Capture 0 / Match Interrupt ."] # [inline (always)] pub fn int_event0_imask_linc0 (& self) -> INT_EVENT0_IMASK_LINC0_R { INT_EVENT0_IMASK_LINC0_R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - Enable LIN Capture 1 Interrupt."] # [inline (always)] pub fn int_event0_imask_linc1 (& self) -> INT_EVENT0_IMASK_LINC1_R { INT_EVENT0_IMASK_LINC1_R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - Enable LIN Hardware Counter Overflow Interrupt."] # [inline (always)] pub fn int_event0_imask_linovf (& self) -> INT_EVENT0_IMASK_LINOVF_R { INT_EVENT0_IMASK_LINOVF_R :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - Enable UART Receive Interrupt."] # [inline (always)] pub fn int_event0_imask_rxint (& self) -> INT_EVENT0_IMASK_RXINT_R { INT_EVENT0_IMASK_RXINT_R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - Enable UART Transmit Interrupt."] # [inline (always)] pub fn int_event0_imask_txint (& self) -> INT_EVENT0_IMASK_TXINT_R { INT_EVENT0_IMASK_TXINT_R :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] # [inline (always)] pub fn int_event0_imask_eot (& self) -> INT_EVENT0_IMASK_EOT_R { INT_EVENT0_IMASK_EOT_R :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - Enable Address Match Interrupt."] # [inline (always)] pub fn int_event0_imask_addr_match (& self) -> INT_EVENT0_IMASK_ADDR_MATCH_R { INT_EVENT0_IMASK_ADDR_MATCH_R :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 14 - Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] # [inline (always)] pub fn int_event0_imask_cts (& self) -> INT_EVENT0_IMASK_CTS_R { INT_EVENT0_IMASK_CTS_R :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - Enable DMA Done on RX Event Channel"] # [inline (always)] pub fn int_event0_imask_dma_done_rx (& self) -> INT_EVENT0_IMASK_DMA_DONE_RX_R { INT_EVENT0_IMASK_DMA_DONE_RX_R :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bit 16 - Enable DMA Done on TX Event Channel"] # [inline (always)] pub fn int_event0_imask_dma_done_tx (& self) -> INT_EVENT0_IMASK_DMA_DONE_TX_R { INT_EVENT0_IMASK_DMA_DONE_TX_R :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] # [inline (always)] pub fn int_event0_imask_nerr (& self) -> INT_EVENT0_IMASK_NERR_R { INT_EVENT0_IMASK_NERR_R :: new (((self . bits >> 17) & 1) != 0) } } impl W { # [doc = "Bit 0 - Enable UARTOUT Receive Time-Out Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_rtout (& mut self) -> INT_EVENT0_IMASK_RTOUT_W < INT_EVENT0_IMASK_SPEC , 0 > { INT_EVENT0_IMASK_RTOUT_W :: new (self) } # [doc = "Bit 1 - Enable UART Framing Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_frmerr (& mut self) -> INT_EVENT0_IMASK_FRMERR_W < INT_EVENT0_IMASK_SPEC , 1 > { INT_EVENT0_IMASK_FRMERR_W :: new (self) } # [doc = "Bit 2 - Enable UART Parity Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_parerr (& mut self) -> INT_EVENT0_IMASK_PARERR_W < INT_EVENT0_IMASK_SPEC , 2 > { INT_EVENT0_IMASK_PARERR_W :: new (self) } # [doc = "Bit 3 - Enable UART Break Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_brkerr (& mut self) -> INT_EVENT0_IMASK_BRKERR_W < INT_EVENT0_IMASK_SPEC , 3 > { INT_EVENT0_IMASK_BRKERR_W :: new (self) } # [doc = "Bit 4 - Enable UART Receive Overrun Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_ovrerr (& mut self) -> INT_EVENT0_IMASK_OVRERR_W < INT_EVENT0_IMASK_SPEC , 4 > { INT_EVENT0_IMASK_OVRERR_W :: new (self) } # [doc = "Bit 5 - Enable Negative Edge on UARTxRXD Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_rxne (& mut self) -> INT_EVENT0_IMASK_RXNE_W < INT_EVENT0_IMASK_SPEC , 5 > { INT_EVENT0_IMASK_RXNE_W :: new (self) } # [doc = "Bit 6 - Enable Positive Edge on UARTxRXD Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_rxpe (& mut self) -> INT_EVENT0_IMASK_RXPE_W < INT_EVENT0_IMASK_SPEC , 6 > { INT_EVENT0_IMASK_RXPE_W :: new (self) } # [doc = "Bit 7 - Enable LIN Capture 0 / Match Interrupt ."] # [inline (always)] # [must_use] pub fn int_event0_imask_linc0 (& mut self) -> INT_EVENT0_IMASK_LINC0_W < INT_EVENT0_IMASK_SPEC , 7 > { INT_EVENT0_IMASK_LINC0_W :: new (self) } # [doc = "Bit 8 - Enable LIN Capture 1 Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_linc1 (& mut self) -> INT_EVENT0_IMASK_LINC1_W < INT_EVENT0_IMASK_SPEC , 8 > { INT_EVENT0_IMASK_LINC1_W :: new (self) } # [doc = "Bit 9 - Enable LIN Hardware Counter Overflow Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_linovf (& mut self) -> INT_EVENT0_IMASK_LINOVF_W < INT_EVENT0_IMASK_SPEC , 9 > { INT_EVENT0_IMASK_LINOVF_W :: new (self) } # [doc = "Bit 10 - Enable UART Receive Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_rxint (& mut self) -> INT_EVENT0_IMASK_RXINT_W < INT_EVENT0_IMASK_SPEC , 10 > { INT_EVENT0_IMASK_RXINT_W :: new (self) } # [doc = "Bit 11 - Enable UART Transmit Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_txint (& mut self) -> INT_EVENT0_IMASK_TXINT_W < INT_EVENT0_IMASK_SPEC , 11 > { INT_EVENT0_IMASK_TXINT_W :: new (self) } # [doc = "Bit 12 - Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] # [inline (always)] # [must_use] pub fn int_event0_imask_eot (& mut self) -> INT_EVENT0_IMASK_EOT_W < INT_EVENT0_IMASK_SPEC , 12 > { INT_EVENT0_IMASK_EOT_W :: new (self) } # [doc = "Bit 13 - Enable Address Match Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_addr_match (& mut self) -> INT_EVENT0_IMASK_ADDR_MATCH_W < INT_EVENT0_IMASK_SPEC , 13 > { INT_EVENT0_IMASK_ADDR_MATCH_W :: new (self) } # [doc = "Bit 14 - Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] # [inline (always)] # [must_use] pub fn int_event0_imask_cts (& mut self) -> INT_EVENT0_IMASK_CTS_W < INT_EVENT0_IMASK_SPEC , 14 > { INT_EVENT0_IMASK_CTS_W :: new (self) } # [doc = "Bit 15 - Enable DMA Done on RX Event Channel"] # [inline (always)] # [must_use] pub fn int_event0_imask_dma_done_rx (& mut self) -> INT_EVENT0_IMASK_DMA_DONE_RX_W < INT_EVENT0_IMASK_SPEC , 15 > { INT_EVENT0_IMASK_DMA_DONE_RX_W :: new (self) } # [doc = "Bit 16 - Enable DMA Done on TX Event Channel"] # [inline (always)] # [must_use] pub fn int_event0_imask_dma_done_tx (& mut self) -> INT_EVENT0_IMASK_DMA_DONE_TX_W <'_,  INT_EVENT0_IMASK_SPEC , 16 > { INT_EVENT0_IMASK_DMA_DONE_TX_W :: new (self) } # [doc = "Bit 17 - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] # [inline (always)] # [must_use] pub fn int_event0_imask_nerr (& mut self) -> INT_EVENT0_IMASK_NERR_W < INT_EVENT0_IMASK_SPEC , 17 > { INT_EVENT0_IMASK_NERR_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Interrupt mask\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_event0_imask::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_event0_imask::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct INT_EVENT0_IMASK_SPEC ; impl crate :: RegisterSpec for INT_EVENT0_IMASK_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`int_event0_imask::R`](R) reader structure"] impl crate :: Readable for INT_EVENT0_IMASK_SPEC { } # [doc = "`write(|w| ..)` method takes [`int_event0_imask::W`](W) writer structure"] impl crate :: Writable for INT_EVENT0_IMASK_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets INT_EVENT0_IMASK to value 0"] impl crate :: Resettable for INT_EVENT0_IMASK_SPEC { const RESET_VALUE : Self :: Ux = 0 ; }
[INFO] [stdout]   |                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                            +++
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing
[INFO] [stdout]  --> src/uart0/int_event0_imask.rs:1:44778
[INFO] [stdout]   |
[INFO] [stdout] 1 | ...0_imask_nerr (& mut self) -> INT_EVENT0_IMASK_NERR_W < INT_EVENT0_IMASK_SPEC , 17 > { INT_EVENT0_IMASK_NERR_W :: new (self) } # [d...
[INFO] [stdout]   |                  ^^^^^^^^^^     ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here
[INFO] [stdout]   |                  |
[INFO] [stdout]   |                  the lifetime is elided here
[INFO] [stdout]   |
[INFO] [stdout]   = help: the same lifetime is referred to in inconsistent ways, making the signature confusing
[INFO] [stdout] help: use `'_` for type paths
[INFO] [stdout]   |
[INFO] [stdout] 1 | # [doc = "Register `INT_EVENT0_IMASK` reader"] pub type R = crate :: R < INT_EVENT0_IMASK_SPEC > ; # [doc = "Register `INT_EVENT0_IMASK` writer"] pub type W = crate :: W < INT_EVENT0_IMASK_SPEC > ; # [doc = "Field `INT_EVENT0_IMASK_RTOUT` reader - Enable UARTOUT Receive Time-Out Interrupt."] pub type INT_EVENT0_IMASK_RTOUT_R = crate :: BitReader < INT_EVENT0_IMASK_RTOUT_A > ; # [doc = "Enable UARTOUT Receive Time-Out Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_RTOUT_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_RTOUT_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_RTOUT_SET = 1 , } impl From < INT_EVENT0_IMASK_RTOUT_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_RTOUT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_RTOUT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_RTOUT_A { match self . bits { false => INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_CLR , true => INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_rtout_clr (& self) -> bool { * self == INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_rtout_set (& self) -> bool { * self == INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_SET } } # [doc = "Field `INT_EVENT0_IMASK_RTOUT` writer - Enable UARTOUT Receive Time-Out Interrupt."] pub type INT_EVENT0_IMASK_RTOUT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_RTOUT_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_RTOUT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_rtout_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_rtout_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_SET) } } # [doc = "Field `INT_EVENT0_IMASK_FRMERR` reader - Enable UART Framing Error Interrupt."] pub type INT_EVENT0_IMASK_FRMERR_R = crate :: BitReader < INT_EVENT0_IMASK_FRMERR_A > ; # [doc = "Enable UART Framing Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_FRMERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_FRMERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_FRMERR_SET = 1 , } impl From < INT_EVENT0_IMASK_FRMERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_FRMERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_FRMERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_FRMERR_A { match self . bits { false => INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_CLR , true => INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_frmerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_frmerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_FRMERR` writer - Enable UART Framing Error Interrupt."] pub type INT_EVENT0_IMASK_FRMERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_FRMERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_FRMERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_frmerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_frmerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_SET) } } # [doc = "Field `INT_EVENT0_IMASK_PARERR` reader - Enable UART Parity Error Interrupt."] pub type INT_EVENT0_IMASK_PARERR_R = crate :: BitReader < INT_EVENT0_IMASK_PARERR_A > ; # [doc = "Enable UART Parity Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_PARERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_PARERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_PARERR_SET = 1 , } impl From < INT_EVENT0_IMASK_PARERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_PARERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_PARERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_PARERR_A { match self . bits { false => INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_CLR , true => INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_parerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_parerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_PARERR` writer - Enable UART Parity Error Interrupt."] pub type INT_EVENT0_IMASK_PARERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_PARERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_PARERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_parerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_parerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_SET) } } # [doc = "Field `INT_EVENT0_IMASK_BRKERR` reader - Enable UART Break Error Interrupt."] pub type INT_EVENT0_IMASK_BRKERR_R = crate :: BitReader < INT_EVENT0_IMASK_BRKERR_A > ; # [doc = "Enable UART Break Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_BRKERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_BRKERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_BRKERR_SET = 1 , } impl From < INT_EVENT0_IMASK_BRKERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_BRKERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_BRKERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_BRKERR_A { match self . bits { false => INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_CLR , true => INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_brkerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_brkerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_BRKERR` writer - Enable UART Break Error Interrupt."] pub type INT_EVENT0_IMASK_BRKERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_BRKERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_BRKERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_brkerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_brkerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_SET) } } # [doc = "Field `INT_EVENT0_IMASK_OVRERR` reader - Enable UART Receive Overrun Error Interrupt."] pub type INT_EVENT0_IMASK_OVRERR_R = crate :: BitReader < INT_EVENT0_IMASK_OVRERR_A > ; # [doc = "Enable UART Receive Overrun Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_OVRERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_OVRERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_OVRERR_SET = 1 , } impl From < INT_EVENT0_IMASK_OVRERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_OVRERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_OVRERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_OVRERR_A { match self . bits { false => INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_CLR , true => INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_ovrerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_ovrerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_OVRERR` writer - Enable UART Receive Overrun Error Interrupt."] pub type INT_EVENT0_IMASK_OVRERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_OVRERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_OVRERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_ovrerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_ovrerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_SET) } } # [doc = "Field `INT_EVENT0_IMASK_RXNE` reader - Enable Negative Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_IMASK_RXNE_R = crate :: BitReader < INT_EVENT0_IMASK_RXNE_A > ; # [doc = "Enable Negative Edge on UARTxRXD Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_RXNE_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_RXNE_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_RXNE_SET = 1 , } impl From < INT_EVENT0_IMASK_RXNE_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_RXNE_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_RXNE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_RXNE_A { match self . bits { false => INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_CLR , true => INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_rxne_clr (& self) -> bool { * self == INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_rxne_set (& self) -> bool { * self == INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_SET } } # [doc = "Field `INT_EVENT0_IMASK_RXNE` writer - Enable Negative Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_IMASK_RXNE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_RXNE_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_RXNE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_rxne_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_rxne_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_SET) } } # [doc = "Field `INT_EVENT0_IMASK_RXPE` reader - Enable Positive Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_IMASK_RXPE_R = crate :: BitReader < INT_EVENT0_IMASK_RXPE_A > ; # [doc = "Enable Positive Edge on UARTxRXD Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_RXPE_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_RXPE_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_RXPE_SET = 1 , } impl From < INT_EVENT0_IMASK_RXPE_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_RXPE_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_RXPE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_RXPE_A { match self . bits { false => INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_CLR , true => INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_rxpe_clr (& self) -> bool { * self == INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_rxpe_set (& self) -> bool { * self == INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_SET } } # [doc = "Field `INT_EVENT0_IMASK_RXPE` writer - Enable Positive Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_IMASK_RXPE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_RXPE_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_RXPE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_rxpe_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_rxpe_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_SET) } } # [doc = "Field `INT_EVENT0_IMASK_LINC0` reader - Enable LIN Capture 0 / Match Interrupt ."] pub type INT_EVENT0_IMASK_LINC0_R = crate :: BitReader < INT_EVENT0_IMASK_LINC0_A > ; # [doc = "Enable LIN Capture 0 / Match Interrupt .\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_LINC0_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_LINC0_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_LINC0_SET = 1 , } impl From < INT_EVENT0_IMASK_LINC0_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_LINC0_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_LINC0_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_LINC0_A { match self . bits { false => INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_CLR , true => INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_linc0_clr (& self) -> bool { * self == INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_linc0_set (& self) -> bool { * self == INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_SET } } # [doc = "Field `INT_EVENT0_IMASK_LINC0` writer - Enable LIN Capture 0 / Match Interrupt ."] pub type INT_EVENT0_IMASK_LINC0_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_LINC0_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_LINC0_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_linc0_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_linc0_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_SET) } } # [doc = "Field `INT_EVENT0_IMASK_LINC1` reader - Enable LIN Capture 1 Interrupt."] pub type INT_EVENT0_IMASK_LINC1_R = crate :: BitReader < INT_EVENT0_IMASK_LINC1_A > ; # [doc = "Enable LIN Capture 1 Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_LINC1_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_LINC1_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_LINC1_SET = 1 , } impl From < INT_EVENT0_IMASK_LINC1_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_LINC1_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_LINC1_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_LINC1_A { match self . bits { false => INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_CLR , true => INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_linc1_clr (& self) -> bool { * self == INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_linc1_set (& self) -> bool { * self == INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_SET } } # [doc = "Field `INT_EVENT0_IMASK_LINC1` writer - Enable LIN Capture 1 Interrupt."] pub type INT_EVENT0_IMASK_LINC1_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_LINC1_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_LINC1_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_linc1_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_linc1_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_SET) } } # [doc = "Field `INT_EVENT0_IMASK_LINOVF` reader - Enable LIN Hardware Counter Overflow Interrupt."] pub type INT_EVENT0_IMASK_LINOVF_R = crate :: BitReader < INT_EVENT0_IMASK_LINOVF_A > ; # [doc = "Enable LIN Hardware Counter Overflow Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_LINOVF_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_LINOVF_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_LINOVF_SET = 1 , } impl From < INT_EVENT0_IMASK_LINOVF_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_LINOVF_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_LINOVF_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_LINOVF_A { match self . bits { false => INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_CLR , true => INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_linovf_clr (& self) -> bool { * self == INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_linovf_set (& self) -> bool { * self == INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_SET } } # [doc = "Field `INT_EVENT0_IMASK_LINOVF` writer - Enable LIN Hardware Counter Overflow Interrupt."] pub type INT_EVENT0_IMASK_LINOVF_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_LINOVF_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_LINOVF_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_linovf_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_linovf_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_SET) } } # [doc = "Field `INT_EVENT0_IMASK_RXINT` reader - Enable UART Receive Interrupt."] pub type INT_EVENT0_IMASK_RXINT_R = crate :: BitReader < INT_EVENT0_IMASK_RXINT_A > ; # [doc = "Enable UART Receive Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_RXINT_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_RXINT_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_RXINT_SET = 1 , } impl From < INT_EVENT0_IMASK_RXINT_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_RXINT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_RXINT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_RXINT_A { match self . bits { false => INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_CLR , true => INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_rxint_clr (& self) -> bool { * self == INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_rxint_set (& self) -> bool { * self == INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_SET } } # [doc = "Field `INT_EVENT0_IMASK_RXINT` writer - Enable UART Receive Interrupt."] pub type INT_EVENT0_IMASK_RXINT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_RXINT_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_RXINT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_rxint_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_rxint_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_SET) } } # [doc = "Field `INT_EVENT0_IMASK_TXINT` reader - Enable UART Transmit Interrupt."] pub type INT_EVENT0_IMASK_TXINT_R = crate :: BitReader < INT_EVENT0_IMASK_TXINT_A > ; # [doc = "Enable UART Transmit Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_TXINT_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_TXINT_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_TXINT_SET = 1 , } impl From < INT_EVENT0_IMASK_TXINT_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_TXINT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_TXINT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_TXINT_A { match self . bits { false => INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_CLR , true => INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_txint_clr (& self) -> bool { * self == INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_txint_set (& self) -> bool { * self == INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_SET } } # [doc = "Field `INT_EVENT0_IMASK_TXINT` writer - Enable UART Transmit Interrupt."] pub type INT_EVENT0_IMASK_TXINT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_TXINT_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_TXINT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_txint_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_txint_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_SET) } } # [doc = "Field `INT_EVENT0_IMASK_EOT` reader - Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] pub type INT_EVENT0_IMASK_EOT_R = crate :: BitReader < INT_EVENT0_IMASK_EOT_A > ; # [doc = "Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_EOT_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_EOT_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_EOT_SET = 1 , } impl From < INT_EVENT0_IMASK_EOT_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_EOT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_EOT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_EOT_A { match self . bits { false => INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_CLR , true => INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_eot_clr (& self) -> bool { * self == INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_eot_set (& self) -> bool { * self == INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_SET } } # [doc = "Field `INT_EVENT0_IMASK_EOT` writer - Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] pub type INT_EVENT0_IMASK_EOT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_EOT_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_EOT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_eot_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_eot_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_SET) } } # [doc = "Field `INT_EVENT0_IMASK_ADDR_MATCH` reader - Enable Address Match Interrupt."] pub type INT_EVENT0_IMASK_ADDR_MATCH_R = crate :: BitReader < INT_EVENT0_IMASK_ADDR_MATCH_A > ; # [doc = "Enable Address Match Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_ADDR_MATCH_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_ADDR_MATCH_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_ADDR_MATCH_SET = 1 , } impl From < INT_EVENT0_IMASK_ADDR_MATCH_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_ADDR_MATCH_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_ADDR_MATCH_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_ADDR_MATCH_A { match self . bits { false => INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_CLR , true => INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_addr_match_clr (& self) -> bool { * self == INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_addr_match_set (& self) -> bool { * self == INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_SET } } # [doc = "Field `INT_EVENT0_IMASK_ADDR_MATCH` writer - Enable Address Match Interrupt."] pub type INT_EVENT0_IMASK_ADDR_MATCH_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_ADDR_MATCH_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_ADDR_MATCH_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_addr_match_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_addr_match_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_SET) } } # [doc = "Field `INT_EVENT0_IMASK_CTS` reader - Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] pub type INT_EVENT0_IMASK_CTS_R = crate :: BitReader < INT_EVENT0_IMASK_CTS_A > ; # [doc = "Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_CTS_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_CTS_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_CTS_SET = 1 , } impl From < INT_EVENT0_IMASK_CTS_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_CTS_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_CTS_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_CTS_A { match self . bits { false => INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_CLR , true => INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_cts_clr (& self) -> bool { * self == INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_cts_set (& self) -> bool { * self == INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_SET } } # [doc = "Field `INT_EVENT0_IMASK_CTS` writer - Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] pub type INT_EVENT0_IMASK_CTS_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_CTS_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_CTS_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_cts_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_cts_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DMA_DONE_RX` reader - Enable DMA Done on RX Event Channel"] pub type INT_EVENT0_IMASK_DMA_DONE_RX_R = crate :: BitReader < INT_EVENT0_IMASK_DMA_DONE_RX_A > ; # [doc = "Enable DMA Done on RX Event Channel\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DMA_DONE_RX_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DMA_DONE_RX_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DMA_DONE_RX_SET = 1 , } impl From < INT_EVENT0_IMASK_DMA_DONE_RX_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DMA_DONE_RX_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DMA_DONE_RX_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DMA_DONE_RX_A { match self . bits { false => INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_CLR , true => INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dma_done_rx_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dma_done_rx_set (& self) -> bool { * self == INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_SET } } # [doc = "Field `INT_EVENT0_IMASK_DMA_DONE_RX` writer - Enable DMA Done on RX Event Channel"] pub type INT_EVENT0_IMASK_DMA_DONE_RX_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DMA_DONE_RX_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DMA_DONE_RX_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dma_done_rx_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dma_done_rx_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DMA_DONE_TX` reader - Enable DMA Done on TX Event Channel"] pub type INT_EVENT0_IMASK_DMA_DONE_TX_R = crate :: BitReader < INT_EVENT0_IMASK_DMA_DONE_TX_A > ; # [doc = "Enable DMA Done on TX Event Channel\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DMA_DONE_TX_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DMA_DONE_TX_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DMA_DONE_TX_SET = 1 , } impl From < INT_EVENT0_IMASK_DMA_DONE_TX_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DMA_DONE_TX_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DMA_DONE_TX_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DMA_DONE_TX_A { match self . bits { false => INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_CLR , true => INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dma_done_tx_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dma_done_tx_set (& self) -> bool { * self == INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_SET } } # [doc = "Field `INT_EVENT0_IMASK_DMA_DONE_TX` writer - Enable DMA Done on TX Event Channel"] pub type INT_EVENT0_IMASK_DMA_DONE_TX_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DMA_DONE_TX_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DMA_DONE_TX_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dma_done_tx_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dma_done_tx_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_SET) } } # [doc = "Field `INT_EVENT0_IMASK_NERR` reader - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] pub type INT_EVENT0_IMASK_NERR_R = crate :: BitReader < INT_EVENT0_IMASK_NERR_A > ; # [doc = "Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_NERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_NERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_NERR_SET = 1 , } impl From < INT_EVENT0_IMASK_NERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_NERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_NERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_NERR_A { match self . bits { false => INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_CLR , true => INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_nerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_nerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_NERR` writer - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] pub type INT_EVENT0_IMASK_NERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_NERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_NERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_nerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_nerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_SET) } } impl R { # [doc = "Bit 0 - Enable UARTOUT Receive Time-Out Interrupt."] # [inline (always)] pub fn int_event0_imask_rtout (& self) -> INT_EVENT0_IMASK_RTOUT_R { INT_EVENT0_IMASK_RTOUT_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - Enable UART Framing Error Interrupt."] # [inline (always)] pub fn int_event0_imask_frmerr (& self) -> INT_EVENT0_IMASK_FRMERR_R { INT_EVENT0_IMASK_FRMERR_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - Enable UART Parity Error Interrupt."] # [inline (always)] pub fn int_event0_imask_parerr (& self) -> INT_EVENT0_IMASK_PARERR_R { INT_EVENT0_IMASK_PARERR_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - Enable UART Break Error Interrupt."] # [inline (always)] pub fn int_event0_imask_brkerr (& self) -> INT_EVENT0_IMASK_BRKERR_R { INT_EVENT0_IMASK_BRKERR_R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - Enable UART Receive Overrun Error Interrupt."] # [inline (always)] pub fn int_event0_imask_ovrerr (& self) -> INT_EVENT0_IMASK_OVRERR_R { INT_EVENT0_IMASK_OVRERR_R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - Enable Negative Edge on UARTxRXD Interrupt."] # [inline (always)] pub fn int_event0_imask_rxne (& self) -> INT_EVENT0_IMASK_RXNE_R { INT_EVENT0_IMASK_RXNE_R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - Enable Positive Edge on UARTxRXD Interrupt."] # [inline (always)] pub fn int_event0_imask_rxpe (& self) -> INT_EVENT0_IMASK_RXPE_R { INT_EVENT0_IMASK_RXPE_R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - Enable LIN Capture 0 / Match Interrupt ."] # [inline (always)] pub fn int_event0_imask_linc0 (& self) -> INT_EVENT0_IMASK_LINC0_R { INT_EVENT0_IMASK_LINC0_R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - Enable LIN Capture 1 Interrupt."] # [inline (always)] pub fn int_event0_imask_linc1 (& self) -> INT_EVENT0_IMASK_LINC1_R { INT_EVENT0_IMASK_LINC1_R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - Enable LIN Hardware Counter Overflow Interrupt."] # [inline (always)] pub fn int_event0_imask_linovf (& self) -> INT_EVENT0_IMASK_LINOVF_R { INT_EVENT0_IMASK_LINOVF_R :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - Enable UART Receive Interrupt."] # [inline (always)] pub fn int_event0_imask_rxint (& self) -> INT_EVENT0_IMASK_RXINT_R { INT_EVENT0_IMASK_RXINT_R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - Enable UART Transmit Interrupt."] # [inline (always)] pub fn int_event0_imask_txint (& self) -> INT_EVENT0_IMASK_TXINT_R { INT_EVENT0_IMASK_TXINT_R :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] # [inline (always)] pub fn int_event0_imask_eot (& self) -> INT_EVENT0_IMASK_EOT_R { INT_EVENT0_IMASK_EOT_R :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - Enable Address Match Interrupt."] # [inline (always)] pub fn int_event0_imask_addr_match (& self) -> INT_EVENT0_IMASK_ADDR_MATCH_R { INT_EVENT0_IMASK_ADDR_MATCH_R :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 14 - Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] # [inline (always)] pub fn int_event0_imask_cts (& self) -> INT_EVENT0_IMASK_CTS_R { INT_EVENT0_IMASK_CTS_R :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - Enable DMA Done on RX Event Channel"] # [inline (always)] pub fn int_event0_imask_dma_done_rx (& self) -> INT_EVENT0_IMASK_DMA_DONE_RX_R { INT_EVENT0_IMASK_DMA_DONE_RX_R :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bit 16 - Enable DMA Done on TX Event Channel"] # [inline (always)] pub fn int_event0_imask_dma_done_tx (& self) -> INT_EVENT0_IMASK_DMA_DONE_TX_R { INT_EVENT0_IMASK_DMA_DONE_TX_R :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] # [inline (always)] pub fn int_event0_imask_nerr (& self) -> INT_EVENT0_IMASK_NERR_R { INT_EVENT0_IMASK_NERR_R :: new (((self . bits >> 17) & 1) != 0) } } impl W { # [doc = "Bit 0 - Enable UARTOUT Receive Time-Out Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_rtout (& mut self) -> INT_EVENT0_IMASK_RTOUT_W < INT_EVENT0_IMASK_SPEC , 0 > { INT_EVENT0_IMASK_RTOUT_W :: new (self) } # [doc = "Bit 1 - Enable UART Framing Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_frmerr (& mut self) -> INT_EVENT0_IMASK_FRMERR_W < INT_EVENT0_IMASK_SPEC , 1 > { INT_EVENT0_IMASK_FRMERR_W :: new (self) } # [doc = "Bit 2 - Enable UART Parity Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_parerr (& mut self) -> INT_EVENT0_IMASK_PARERR_W < INT_EVENT0_IMASK_SPEC , 2 > { INT_EVENT0_IMASK_PARERR_W :: new (self) } # [doc = "Bit 3 - Enable UART Break Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_brkerr (& mut self) -> INT_EVENT0_IMASK_BRKERR_W < INT_EVENT0_IMASK_SPEC , 3 > { INT_EVENT0_IMASK_BRKERR_W :: new (self) } # [doc = "Bit 4 - Enable UART Receive Overrun Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_ovrerr (& mut self) -> INT_EVENT0_IMASK_OVRERR_W < INT_EVENT0_IMASK_SPEC , 4 > { INT_EVENT0_IMASK_OVRERR_W :: new (self) } # [doc = "Bit 5 - Enable Negative Edge on UARTxRXD Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_rxne (& mut self) -> INT_EVENT0_IMASK_RXNE_W < INT_EVENT0_IMASK_SPEC , 5 > { INT_EVENT0_IMASK_RXNE_W :: new (self) } # [doc = "Bit 6 - Enable Positive Edge on UARTxRXD Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_rxpe (& mut self) -> INT_EVENT0_IMASK_RXPE_W < INT_EVENT0_IMASK_SPEC , 6 > { INT_EVENT0_IMASK_RXPE_W :: new (self) } # [doc = "Bit 7 - Enable LIN Capture 0 / Match Interrupt ."] # [inline (always)] # [must_use] pub fn int_event0_imask_linc0 (& mut self) -> INT_EVENT0_IMASK_LINC0_W < INT_EVENT0_IMASK_SPEC , 7 > { INT_EVENT0_IMASK_LINC0_W :: new (self) } # [doc = "Bit 8 - Enable LIN Capture 1 Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_linc1 (& mut self) -> INT_EVENT0_IMASK_LINC1_W < INT_EVENT0_IMASK_SPEC , 8 > { INT_EVENT0_IMASK_LINC1_W :: new (self) } # [doc = "Bit 9 - Enable LIN Hardware Counter Overflow Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_linovf (& mut self) -> INT_EVENT0_IMASK_LINOVF_W < INT_EVENT0_IMASK_SPEC , 9 > { INT_EVENT0_IMASK_LINOVF_W :: new (self) } # [doc = "Bit 10 - Enable UART Receive Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_rxint (& mut self) -> INT_EVENT0_IMASK_RXINT_W < INT_EVENT0_IMASK_SPEC , 10 > { INT_EVENT0_IMASK_RXINT_W :: new (self) } # [doc = "Bit 11 - Enable UART Transmit Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_txint (& mut self) -> INT_EVENT0_IMASK_TXINT_W < INT_EVENT0_IMASK_SPEC , 11 > { INT_EVENT0_IMASK_TXINT_W :: new (self) } # [doc = "Bit 12 - Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] # [inline (always)] # [must_use] pub fn int_event0_imask_eot (& mut self) -> INT_EVENT0_IMASK_EOT_W < INT_EVENT0_IMASK_SPEC , 12 > { INT_EVENT0_IMASK_EOT_W :: new (self) } # [doc = "Bit 13 - Enable Address Match Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_addr_match (& mut self) -> INT_EVENT0_IMASK_ADDR_MATCH_W < INT_EVENT0_IMASK_SPEC , 13 > { INT_EVENT0_IMASK_ADDR_MATCH_W :: new (self) } # [doc = "Bit 14 - Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] # [inline (always)] # [must_use] pub fn int_event0_imask_cts (& mut self) -> INT_EVENT0_IMASK_CTS_W < INT_EVENT0_IMASK_SPEC , 14 > { INT_EVENT0_IMASK_CTS_W :: new (self) } # [doc = "Bit 15 - Enable DMA Done on RX Event Channel"] # [inline (always)] # [must_use] pub fn int_event0_imask_dma_done_rx (& mut self) -> INT_EVENT0_IMASK_DMA_DONE_RX_W < INT_EVENT0_IMASK_SPEC , 15 > { INT_EVENT0_IMASK_DMA_DONE_RX_W :: new (self) } # [doc = "Bit 16 - Enable DMA Done on TX Event Channel"] # [inline (always)] # [must_use] pub fn int_event0_imask_dma_done_tx (& mut self) -> INT_EVENT0_IMASK_DMA_DONE_TX_W < INT_EVENT0_IMASK_SPEC , 16 > { INT_EVENT0_IMASK_DMA_DONE_TX_W :: new (self) } # [doc = "Bit 17 - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] # [inline (always)] # [must_use] pub fn int_event0_imask_nerr (& mut self) -> INT_EVENT0_IMASK_NERR_W <'_,  INT_EVENT0_IMASK_SPEC , 17 > { INT_EVENT0_IMASK_NERR_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Interrupt mask\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_event0_imask::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_event0_imask::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct INT_EVENT0_IMASK_SPEC ; impl crate :: RegisterSpec for INT_EVENT0_IMASK_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`int_event0_imask::R`](R) reader structure"] impl crate :: Readable for INT_EVENT0_IMASK_SPEC { } # [doc = "`write(|w| ..)` method takes [`int_event0_imask::W`](W) writer structure"] impl crate :: Writable for INT_EVENT0_IMASK_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets INT_EVENT0_IMASK to value 0"] impl crate :: Resettable for INT_EVENT0_IMASK_SPEC { const RESET_VALUE : Self :: Ux = 0 ; }
[INFO] [stdout]   |                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                  +++
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing
[INFO] [stdout]  --> src/uart0/int_event0_iset.rs:1:21599
[INFO] [stdout]   |
[INFO] [stdout] 1 | ...t0_iset_rtout (& mut self) -> INT_EVENT0_ISET_RTOUT_W < INT_EVENT0_ISET_SPEC , 0 > { INT_EVENT0_ISET_RTOUT_W :: new (self) } # [do...
[INFO] [stdout]   |                   ^^^^^^^^^^     ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here
[INFO] [stdout]   |                   |
[INFO] [stdout]   |                   the lifetime is elided here
[INFO] [stdout]   |
[INFO] [stdout]   = help: the same lifetime is referred to in inconsistent ways, making the signature confusing
[INFO] [stdout] help: use `'_` for type paths
[INFO] [stdout]   |
[INFO] [stdout] 1 | # [doc = "Register `INT_EVENT0_ISET` writer"] pub type W = crate :: W < INT_EVENT0_ISET_SPEC > ; # [doc = "Set UARTOUT Receive Time-Out Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_RTOUT_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_RTOUT_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_RTOUT_SET = 1 , } impl From < INT_EVENT0_ISET_RTOUT_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_RTOUT_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_RTOUT` writer - Set UARTOUT Receive Time-Out Interrupt."] pub type INT_EVENT0_ISET_RTOUT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_RTOUT_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_RTOUT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_rtout_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_RTOUT_AW :: INT_EVENT0_ISET_RTOUT_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_rtout_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_RTOUT_AW :: INT_EVENT0_ISET_RTOUT_SET) } } # [doc = "Set UART Framing Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_FRMERR_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_FRMERR_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_FRMERR_SET = 1 , } impl From < INT_EVENT0_ISET_FRMERR_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_FRMERR_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_FRMERR` writer - Set UART Framing Error Interrupt."] pub type INT_EVENT0_ISET_FRMERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_FRMERR_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_FRMERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_frmerr_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_FRMERR_AW :: INT_EVENT0_ISET_FRMERR_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_frmerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_FRMERR_AW :: INT_EVENT0_ISET_FRMERR_SET) } } # [doc = "Set UART Parity Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_PARERR_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_PARERR_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_PARERR_SET = 1 , } impl From < INT_EVENT0_ISET_PARERR_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_PARERR_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_PARERR` writer - Set UART Parity Error Interrupt."] pub type INT_EVENT0_ISET_PARERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_PARERR_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_PARERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_parerr_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_PARERR_AW :: INT_EVENT0_ISET_PARERR_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_parerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_PARERR_AW :: INT_EVENT0_ISET_PARERR_SET) } } # [doc = "Set UART Break Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_BRKERR_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_BRKERR_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_BRKERR_SET = 1 , } impl From < INT_EVENT0_ISET_BRKERR_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_BRKERR_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_BRKERR` writer - Set UART Break Error Interrupt."] pub type INT_EVENT0_ISET_BRKERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_BRKERR_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_BRKERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_brkerr_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_BRKERR_AW :: INT_EVENT0_ISET_BRKERR_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_brkerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_BRKERR_AW :: INT_EVENT0_ISET_BRKERR_SET) } } # [doc = "Set UART Receive Overrun Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_OVRERR_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_OVRERR_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_OVRERR_SET = 1 , } impl From < INT_EVENT0_ISET_OVRERR_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_OVRERR_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_OVRERR` writer - Set UART Receive Overrun Error Interrupt."] pub type INT_EVENT0_ISET_OVRERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_OVRERR_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_OVRERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_ovrerr_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_OVRERR_AW :: INT_EVENT0_ISET_OVRERR_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_ovrerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_OVRERR_AW :: INT_EVENT0_ISET_OVRERR_SET) } } # [doc = "Set Negative Edge on UARTxRXD Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_RXNE_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_RXNE_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_RXNE_SET = 1 , } impl From < INT_EVENT0_ISET_RXNE_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_RXNE_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_RXNE` writer - Set Negative Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_ISET_RXNE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_RXNE_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_RXNE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_rxne_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_RXNE_AW :: INT_EVENT0_ISET_RXNE_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_rxne_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_RXNE_AW :: INT_EVENT0_ISET_RXNE_SET) } } # [doc = "Set Positive Edge on UARTxRXD Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_RXPE_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_RXPE_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_RXPE_SET = 1 , } impl From < INT_EVENT0_ISET_RXPE_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_RXPE_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_RXPE` writer - Set Positive Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_ISET_RXPE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_RXPE_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_RXPE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_rxpe_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_RXPE_AW :: INT_EVENT0_ISET_RXPE_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_rxpe_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_RXPE_AW :: INT_EVENT0_ISET_RXPE_SET) } } # [doc = "Set LIN Capture 0 / Match Interrupt .\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_LINC0_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_LINC0_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_LINC0_SET = 1 , } impl From < INT_EVENT0_ISET_LINC0_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_LINC0_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_LINC0` writer - Set LIN Capture 0 / Match Interrupt ."] pub type INT_EVENT0_ISET_LINC0_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_LINC0_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_LINC0_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_linc0_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_LINC0_AW :: INT_EVENT0_ISET_LINC0_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_linc0_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_LINC0_AW :: INT_EVENT0_ISET_LINC0_SET) } } # [doc = "Set LIN Capture 1 Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_LINC1_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_LINC1_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_LINC1_SET = 1 , } impl From < INT_EVENT0_ISET_LINC1_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_LINC1_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_LINC1` writer - Set LIN Capture 1 Interrupt."] pub type INT_EVENT0_ISET_LINC1_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_LINC1_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_LINC1_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_linc1_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_LINC1_AW :: INT_EVENT0_ISET_LINC1_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_linc1_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_LINC1_AW :: INT_EVENT0_ISET_LINC1_SET) } } # [doc = "Set LIN Hardware Counter Overflow Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_LINOVF_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_LINOVF_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_LINOVF_SET = 1 , } impl From < INT_EVENT0_ISET_LINOVF_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_LINOVF_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_LINOVF` writer - Set LIN Hardware Counter Overflow Interrupt."] pub type INT_EVENT0_ISET_LINOVF_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_LINOVF_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_LINOVF_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_linovf_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_LINOVF_AW :: INT_EVENT0_ISET_LINOVF_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_linovf_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_LINOVF_AW :: INT_EVENT0_ISET_LINOVF_SET) } } # [doc = "Set UART Receive Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_RXINT_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_RXINT_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_RXINT_SET = 1 , } impl From < INT_EVENT0_ISET_RXINT_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_RXINT_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_RXINT` writer - Set UART Receive Interrupt."] pub type INT_EVENT0_ISET_RXINT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_RXINT_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_RXINT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_rxint_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_RXINT_AW :: INT_EVENT0_ISET_RXINT_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_rxint_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_RXINT_AW :: INT_EVENT0_ISET_RXINT_SET) } } # [doc = "Set UART Transmit Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_TXINT_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_TXINT_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_TXINT_SET = 1 , } impl From < INT_EVENT0_ISET_TXINT_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_TXINT_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_TXINT` writer - Set UART Transmit Interrupt."] pub type INT_EVENT0_ISET_TXINT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_TXINT_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_TXINT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_txint_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_TXINT_AW :: INT_EVENT0_ISET_TXINT_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_txint_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_TXINT_AW :: INT_EVENT0_ISET_TXINT_SET) } } # [doc = "Set UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_EOT_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_EOT_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_EOT_SET = 1 , } impl From < INT_EVENT0_ISET_EOT_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_EOT_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_EOT` writer - Set UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] pub type INT_EVENT0_ISET_EOT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_EOT_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_EOT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_eot_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_EOT_AW :: INT_EVENT0_ISET_EOT_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_eot_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_EOT_AW :: INT_EVENT0_ISET_EOT_SET) } } # [doc = "Set Address Match Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_ADDR_MATCH_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_ADDR_MATCH_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_ADDR_MATCH_SET = 1 , } impl From < INT_EVENT0_ISET_ADDR_MATCH_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_ADDR_MATCH_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_ADDR_MATCH` writer - Set Address Match Interrupt."] pub type INT_EVENT0_ISET_ADDR_MATCH_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_ADDR_MATCH_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_ADDR_MATCH_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_addr_match_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_ADDR_MATCH_AW :: INT_EVENT0_ISET_ADDR_MATCH_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_addr_match_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_ADDR_MATCH_AW :: INT_EVENT0_ISET_ADDR_MATCH_SET) } } # [doc = "Set UART Clear to Send Modem Interrupt. 0 = Interrupt disabled\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_CTS_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_CTS_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_CTS_SET = 1 , } impl From < INT_EVENT0_ISET_CTS_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_CTS_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_CTS` writer - Set UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] pub type INT_EVENT0_ISET_CTS_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_CTS_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_CTS_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_cts_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_CTS_AW :: INT_EVENT0_ISET_CTS_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_cts_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_CTS_AW :: INT_EVENT0_ISET_CTS_SET) } } # [doc = "Set DMA Done on RX Event Channel\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_DMA_DONE_RX_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_DMA_DONE_RX_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_DMA_DONE_RX_SET = 1 , } impl From < INT_EVENT0_ISET_DMA_DONE_RX_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_DMA_DONE_RX_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_DMA_DONE_RX` writer - Set DMA Done on RX Event Channel"] pub type INT_EVENT0_ISET_DMA_DONE_RX_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_DMA_DONE_RX_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_DMA_DONE_RX_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_dma_done_rx_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_DMA_DONE_RX_AW :: INT_EVENT0_ISET_DMA_DONE_RX_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_dma_done_rx_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_DMA_DONE_RX_AW :: INT_EVENT0_ISET_DMA_DONE_RX_SET) } } # [doc = "Set DMA Done on TX Event Channel\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_DMA_DONE_TX_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_DMA_DONE_TX_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_DMA_DONE_TX_SET = 1 , } impl From < INT_EVENT0_ISET_DMA_DONE_TX_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_DMA_DONE_TX_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_DMA_DONE_TX` writer - Set DMA Done on TX Event Channel"] pub type INT_EVENT0_ISET_DMA_DONE_TX_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_DMA_DONE_TX_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_DMA_DONE_TX_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_dma_done_tx_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_DMA_DONE_TX_AW :: INT_EVENT0_ISET_DMA_DONE_TX_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_dma_done_tx_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_DMA_DONE_TX_AW :: INT_EVENT0_ISET_DMA_DONE_TX_SET) } } # [doc = "Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_NERR_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_NERR_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_NERR_SET = 1 , } impl From < INT_EVENT0_ISET_NERR_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_NERR_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_NERR` writer - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] pub type INT_EVENT0_ISET_NERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_NERR_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_NERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_nerr_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_NERR_AW :: INT_EVENT0_ISET_NERR_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_nerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_NERR_AW :: INT_EVENT0_ISET_NERR_SET) } } impl W { # [doc = "Bit 0 - Set UARTOUT Receive Time-Out Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iset_rtout (& mut self) -> INT_EVENT0_ISET_RTOUT_W <'_,  INT_EVENT0_ISET_SPEC , 0 > { INT_EVENT0_ISET_RTOUT_W :: new (self) } # [doc = "Bit 1 - Set UART Framing Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iset_frmerr (& mut self) -> INT_EVENT0_ISET_FRMERR_W < INT_EVENT0_ISET_SPEC , 1 > { INT_EVENT0_ISET_FRMERR_W :: new (self) } # [doc = "Bit 2 - Set UART Parity Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iset_parerr (& mut self) -> INT_EVENT0_ISET_PARERR_W < INT_EVENT0_ISET_SPEC , 2 > { INT_EVENT0_ISET_PARERR_W :: new (self) } # [doc = "Bit 3 - Set UART Break Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iset_brkerr (& mut self) -> INT_EVENT0_ISET_BRKERR_W < INT_EVENT0_ISET_SPEC , 3 > { INT_EVENT0_ISET_BRKERR_W :: new (self) } # [doc = "Bit 4 - Set UART Receive Overrun Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iset_ovrerr (& mut self) -> INT_EVENT0_ISET_OVRERR_W < INT_EVENT0_ISET_SPEC , 4 > { INT_EVENT0_ISET_OVRERR_W :: new (self) } # [doc = "Bit 5 - Set Negative Edge on UARTxRXD Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iset_rxne (& mut self) -> INT_EVENT0_ISET_RXNE_W < INT_EVENT0_ISET_SPEC , 5 > { INT_EVENT0_ISET_RXNE_W :: new (self) } # [doc = "Bit 6 - Set Positive Edge on UARTxRXD Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iset_rxpe (& mut self) -> INT_EVENT0_ISET_RXPE_W < INT_EVENT0_ISET_SPEC , 6 > { INT_EVENT0_ISET_RXPE_W :: new (self) } # [doc = "Bit 7 - Set LIN Capture 0 / Match Interrupt ."] # [inline (always)] # [must_use] pub fn int_event0_iset_linc0 (& mut self) -> INT_EVENT0_ISET_LINC0_W < INT_EVENT0_ISET_SPEC , 7 > { INT_EVENT0_ISET_LINC0_W :: new (self) } # [doc = "Bit 8 - Set LIN Capture 1 Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iset_linc1 (& mut self) -> INT_EVENT0_ISET_LINC1_W < INT_EVENT0_ISET_SPEC , 8 > { INT_EVENT0_ISET_LINC1_W :: new (self) } # [doc = "Bit 9 - Set LIN Hardware Counter Overflow Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iset_linovf (& mut self) -> INT_EVENT0_ISET_LINOVF_W < INT_EVENT0_ISET_SPEC , 9 > { INT_EVENT0_ISET_LINOVF_W :: new (self) } # [doc = "Bit 10 - Set UART Receive Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iset_rxint (& mut self) -> INT_EVENT0_ISET_RXINT_W < INT_EVENT0_ISET_SPEC , 10 > { INT_EVENT0_ISET_RXINT_W :: new (self) } # [doc = "Bit 11 - Set UART Transmit Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iset_txint (& mut self) -> INT_EVENT0_ISET_TXINT_W < INT_EVENT0_ISET_SPEC , 11 > { INT_EVENT0_ISET_TXINT_W :: new (self) } # [doc = "Bit 12 - Set UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] # [inline (always)] # [must_use] pub fn int_event0_iset_eot (& mut self) -> INT_EVENT0_ISET_EOT_W < INT_EVENT0_ISET_SPEC , 12 > { INT_EVENT0_ISET_EOT_W :: new (self) } # [doc = "Bit 13 - Set Address Match Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iset_addr_match (& mut self) -> INT_EVENT0_ISET_ADDR_MATCH_W < INT_EVENT0_ISET_SPEC , 13 > { INT_EVENT0_ISET_ADDR_MATCH_W :: new (self) } # [doc = "Bit 14 - Set UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] # [inline (always)] # [must_use] pub fn int_event0_iset_cts (& mut self) -> INT_EVENT0_ISET_CTS_W < INT_EVENT0_ISET_SPEC , 14 > { INT_EVENT0_ISET_CTS_W :: new (self) } # [doc = "Bit 15 - Set DMA Done on RX Event Channel"] # [inline (always)] # [must_use] pub fn int_event0_iset_dma_done_rx (& mut self) -> INT_EVENT0_ISET_DMA_DONE_RX_W < INT_EVENT0_ISET_SPEC , 15 > { INT_EVENT0_ISET_DMA_DONE_RX_W :: new (self) } # [doc = "Bit 16 - Set DMA Done on TX Event Channel"] # [inline (always)] # [must_use] pub fn int_event0_iset_dma_done_tx (& mut self) -> INT_EVENT0_ISET_DMA_DONE_TX_W < INT_EVENT0_ISET_SPEC , 16 > { INT_EVENT0_ISET_DMA_DONE_TX_W :: new (self) } # [doc = "Bit 17 - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] # [inline (always)] # [must_use] pub fn int_event0_iset_nerr (& mut self) -> INT_EVENT0_ISET_NERR_W < INT_EVENT0_ISET_SPEC , 17 > { INT_EVENT0_ISET_NERR_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Interrupt set\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_event0_iset::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct INT_EVENT0_ISET_SPEC ; impl crate :: RegisterSpec for INT_EVENT0_ISET_SPEC { type Ux = u32 ; } # [doc = "`write(|w| ..)` method takes [`int_event0_iset::W`](W) writer structure"] impl crate :: Writable for INT_EVENT0_ISET_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets INT_EVENT0_ISET to value 0"] impl crate :: Resettable for INT_EVENT0_ISET_SPEC { const RESET_VALUE : Self :: Ux = 0 ; }
[INFO] [stdout]   |                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                       +++
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing
[INFO] [stdout]  --> src/uart0/int_event0_iset.rs:1:21827
[INFO] [stdout]   |
[INFO] [stdout] 1 | ..._iset_frmerr (& mut self) -> INT_EVENT0_ISET_FRMERR_W < INT_EVENT0_ISET_SPEC , 1 > { INT_EVENT0_ISET_FRMERR_W :: new (self) } # [d...
[INFO] [stdout]   |                  ^^^^^^^^^^     ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here
[INFO] [stdout]   |                  |
[INFO] [stdout]   |                  the lifetime is elided here
[INFO] [stdout]   |
[INFO] [stdout]   = help: the same lifetime is referred to in inconsistent ways, making the signature confusing
[INFO] [stdout] help: use `'_` for type paths
[INFO] [stdout]   |
[INFO] [stdout] 1 | # [doc = "Register `INT_EVENT0_ISET` writer"] pub type W = crate :: W < INT_EVENT0_ISET_SPEC > ; # [doc = "Set UARTOUT Receive Time-Out Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_RTOUT_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_RTOUT_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_RTOUT_SET = 1 , } impl From < INT_EVENT0_ISET_RTOUT_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_RTOUT_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_RTOUT` writer - Set UARTOUT Receive Time-Out Interrupt."] pub type INT_EVENT0_ISET_RTOUT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_RTOUT_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_RTOUT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_rtout_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_RTOUT_AW :: INT_EVENT0_ISET_RTOUT_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_rtout_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_RTOUT_AW :: INT_EVENT0_ISET_RTOUT_SET) } } # [doc = "Set UART Framing Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_FRMERR_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_FRMERR_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_FRMERR_SET = 1 , } impl From < INT_EVENT0_ISET_FRMERR_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_FRMERR_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_FRMERR` writer - Set UART Framing Error Interrupt."] pub type INT_EVENT0_ISET_FRMERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_FRMERR_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_FRMERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_frmerr_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_FRMERR_AW :: INT_EVENT0_ISET_FRMERR_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_frmerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_FRMERR_AW :: INT_EVENT0_ISET_FRMERR_SET) } } # [doc = "Set UART Parity Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_PARERR_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_PARERR_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_PARERR_SET = 1 , } impl From < INT_EVENT0_ISET_PARERR_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_PARERR_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_PARERR` writer - Set UART Parity Error Interrupt."] pub type INT_EVENT0_ISET_PARERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_PARERR_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_PARERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_parerr_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_PARERR_AW :: INT_EVENT0_ISET_PARERR_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_parerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_PARERR_AW :: INT_EVENT0_ISET_PARERR_SET) } } # [doc = "Set UART Break Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_BRKERR_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_BRKERR_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_BRKERR_SET = 1 , } impl From < INT_EVENT0_ISET_BRKERR_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_BRKERR_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_BRKERR` writer - Set UART Break Error Interrupt."] pub type INT_EVENT0_ISET_BRKERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_BRKERR_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_BRKERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_brkerr_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_BRKERR_AW :: INT_EVENT0_ISET_BRKERR_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_brkerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_BRKERR_AW :: INT_EVENT0_ISET_BRKERR_SET) } } # [doc = "Set UART Receive Overrun Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_OVRERR_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_OVRERR_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_OVRERR_SET = 1 , } impl From < INT_EVENT0_ISET_OVRERR_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_OVRERR_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_OVRERR` writer - Set UART Receive Overrun Error Interrupt."] pub type INT_EVENT0_ISET_OVRERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_OVRERR_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_OVRERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_ovrerr_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_OVRERR_AW :: INT_EVENT0_ISET_OVRERR_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_ovrerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_OVRERR_AW :: INT_EVENT0_ISET_OVRERR_SET) } } # [doc = "Set Negative Edge on UARTxRXD Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_RXNE_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_RXNE_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_RXNE_SET = 1 , } impl From < INT_EVENT0_ISET_RXNE_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_RXNE_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_RXNE` writer - Set Negative Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_ISET_RXNE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_RXNE_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_RXNE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_rxne_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_RXNE_AW :: INT_EVENT0_ISET_RXNE_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_rxne_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_RXNE_AW :: INT_EVENT0_ISET_RXNE_SET) } } # [doc = "Set Positive Edge on UARTxRXD Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_RXPE_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_RXPE_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_RXPE_SET = 1 , } impl From < INT_EVENT0_ISET_RXPE_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_RXPE_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_RXPE` writer - Set Positive Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_ISET_RXPE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_RXPE_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_RXPE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_rxpe_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_RXPE_AW :: INT_EVENT0_ISET_RXPE_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_rxpe_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_RXPE_AW :: INT_EVENT0_ISET_RXPE_SET) } } # [doc = "Set LIN Capture 0 / Match Interrupt .\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_LINC0_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_LINC0_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_LINC0_SET = 1 , } impl From < INT_EVENT0_ISET_LINC0_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_LINC0_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_LINC0` writer - Set LIN Capture 0 / Match Interrupt ."] pub type INT_EVENT0_ISET_LINC0_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_LINC0_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_LINC0_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_linc0_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_LINC0_AW :: INT_EVENT0_ISET_LINC0_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_linc0_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_LINC0_AW :: INT_EVENT0_ISET_LINC0_SET) } } # [doc = "Set LIN Capture 1 Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_LINC1_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_LINC1_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_LINC1_SET = 1 , } impl From < INT_EVENT0_ISET_LINC1_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_LINC1_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_LINC1` writer - Set LIN Capture 1 Interrupt."] pub type INT_EVENT0_ISET_LINC1_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_LINC1_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_LINC1_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_linc1_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_LINC1_AW :: INT_EVENT0_ISET_LINC1_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_linc1_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_LINC1_AW :: INT_EVENT0_ISET_LINC1_SET) } } # [doc = "Set LIN Hardware Counter Overflow Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_LINOVF_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_LINOVF_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_LINOVF_SET = 1 , } impl From < INT_EVENT0_ISET_LINOVF_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_LINOVF_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_LINOVF` writer - Set LIN Hardware Counter Overflow Interrupt."] pub type INT_EVENT0_ISET_LINOVF_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_LINOVF_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_LINOVF_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_linovf_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_LINOVF_AW :: INT_EVENT0_ISET_LINOVF_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_linovf_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_LINOVF_AW :: INT_EVENT0_ISET_LINOVF_SET) } } # [doc = "Set UART Receive Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_RXINT_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_RXINT_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_RXINT_SET = 1 , } impl From < INT_EVENT0_ISET_RXINT_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_RXINT_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_RXINT` writer - Set UART Receive Interrupt."] pub type INT_EVENT0_ISET_RXINT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_RXINT_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_RXINT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_rxint_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_RXINT_AW :: INT_EVENT0_ISET_RXINT_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_rxint_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_RXINT_AW :: INT_EVENT0_ISET_RXINT_SET) } } # [doc = "Set UART Transmit Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_TXINT_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_TXINT_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_TXINT_SET = 1 , } impl From < INT_EVENT0_ISET_TXINT_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_TXINT_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_TXINT` writer - Set UART Transmit Interrupt."] pub type INT_EVENT0_ISET_TXINT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_TXINT_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_TXINT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_txint_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_TXINT_AW :: INT_EVENT0_ISET_TXINT_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_txint_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_TXINT_AW :: INT_EVENT0_ISET_TXINT_SET) } } # [doc = "Set UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_EOT_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_EOT_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_EOT_SET = 1 , } impl From < INT_EVENT0_ISET_EOT_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_EOT_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_EOT` writer - Set UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] pub type INT_EVENT0_ISET_EOT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_EOT_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_EOT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_eot_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_EOT_AW :: INT_EVENT0_ISET_EOT_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_eot_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_EOT_AW :: INT_EVENT0_ISET_EOT_SET) } } # [doc = "Set Address Match Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_ADDR_MATCH_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_ADDR_MATCH_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_ADDR_MATCH_SET = 1 , } impl From < INT_EVENT0_ISET_ADDR_MATCH_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_ADDR_MATCH_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_ADDR_MATCH` writer - Set Address Match Interrupt."] pub type INT_EVENT0_ISET_ADDR_MATCH_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_ADDR_MATCH_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_ADDR_MATCH_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_addr_match_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_ADDR_MATCH_AW :: INT_EVENT0_ISET_ADDR_MATCH_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_addr_match_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_ADDR_MATCH_AW :: INT_EVENT0_ISET_ADDR_MATCH_SET) } } # [doc = "Set UART Clear to Send Modem Interrupt. 0 = Interrupt disabled\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_CTS_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_CTS_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_CTS_SET = 1 , } impl From < INT_EVENT0_ISET_CTS_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_CTS_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_CTS` writer - Set UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] pub type INT_EVENT0_ISET_CTS_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_CTS_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_CTS_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_cts_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_CTS_AW :: INT_EVENT0_ISET_CTS_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_cts_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_CTS_AW :: INT_EVENT0_ISET_CTS_SET) } } # [doc = "Set DMA Done on RX Event Channel\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_DMA_DONE_RX_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_DMA_DONE_RX_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_DMA_DONE_RX_SET = 1 , } impl From < INT_EVENT0_ISET_DMA_DONE_RX_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_DMA_DONE_RX_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_DMA_DONE_RX` writer - Set DMA Done on RX Event Channel"] pub type INT_EVENT0_ISET_DMA_DONE_RX_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_DMA_DONE_RX_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_DMA_DONE_RX_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_dma_done_rx_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_DMA_DONE_RX_AW :: INT_EVENT0_ISET_DMA_DONE_RX_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_dma_done_rx_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_DMA_DONE_RX_AW :: INT_EVENT0_ISET_DMA_DONE_RX_SET) } } # [doc = "Set DMA Done on TX Event Channel\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_DMA_DONE_TX_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_DMA_DONE_TX_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_DMA_DONE_TX_SET = 1 , } impl From < INT_EVENT0_ISET_DMA_DONE_TX_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_DMA_DONE_TX_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_DMA_DONE_TX` writer - Set DMA Done on TX Event Channel"] pub type INT_EVENT0_ISET_DMA_DONE_TX_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_DMA_DONE_TX_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_DMA_DONE_TX_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_dma_done_tx_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_DMA_DONE_TX_AW :: INT_EVENT0_ISET_DMA_DONE_TX_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_dma_done_tx_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_DMA_DONE_TX_AW :: INT_EVENT0_ISET_DMA_DONE_TX_SET) } } # [doc = "Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_NERR_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_NERR_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_NERR_SET = 1 , } impl From < INT_EVENT0_ISET_NERR_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_NERR_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_NERR` writer - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] pub type INT_EVENT0_ISET_NERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_NERR_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_NERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_nerr_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_NERR_AW :: INT_EVENT0_ISET_NERR_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_nerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_NERR_AW :: INT_EVENT0_ISET_NERR_SET) } } impl W { # [doc = "Bit 0 - Set UARTOUT Receive Time-Out Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iset_rtout (& mut self) -> INT_EVENT0_ISET_RTOUT_W < INT_EVENT0_ISET_SPEC , 0 > { INT_EVENT0_ISET_RTOUT_W :: new (self) } # [doc = "Bit 1 - Set UART Framing Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iset_frmerr (& mut self) -> INT_EVENT0_ISET_FRMERR_W <'_,  INT_EVENT0_ISET_SPEC , 1 > { INT_EVENT0_ISET_FRMERR_W :: new (self) } # [doc = "Bit 2 - Set UART Parity Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iset_parerr (& mut self) -> INT_EVENT0_ISET_PARERR_W < INT_EVENT0_ISET_SPEC , 2 > { INT_EVENT0_ISET_PARERR_W :: new (self) } # [doc = "Bit 3 - Set UART Break Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iset_brkerr (& mut self) -> INT_EVENT0_ISET_BRKERR_W < INT_EVENT0_ISET_SPEC , 3 > { INT_EVENT0_ISET_BRKERR_W :: new (self) } # [doc = "Bit 4 - Set UART Receive Overrun Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iset_ovrerr (& mut self) -> INT_EVENT0_ISET_OVRERR_W < INT_EVENT0_ISET_SPEC , 4 > { INT_EVENT0_ISET_OVRERR_W :: new (self) } # [doc = "Bit 5 - Set Negative Edge on UARTxRXD Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iset_rxne (& mut self) -> INT_EVENT0_ISET_RXNE_W < INT_EVENT0_ISET_SPEC , 5 > { INT_EVENT0_ISET_RXNE_W :: new (self) } # [doc = "Bit 6 - Set Positive Edge on UARTxRXD Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iset_rxpe (& mut self) -> INT_EVENT0_ISET_RXPE_W < INT_EVENT0_ISET_SPEC , 6 > { INT_EVENT0_ISET_RXPE_W :: new (self) } # [doc = "Bit 7 - Set LIN Capture 0 / Match Interrupt ."] # [inline (always)] # [must_use] pub fn int_event0_iset_linc0 (& mut self) -> INT_EVENT0_ISET_LINC0_W < INT_EVENT0_ISET_SPEC , 7 > { INT_EVENT0_ISET_LINC0_W :: new (self) } # [doc = "Bit 8 - Set LIN Capture 1 Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iset_linc1 (& mut self) -> INT_EVENT0_ISET_LINC1_W < INT_EVENT0_ISET_SPEC , 8 > { INT_EVENT0_ISET_LINC1_W :: new (self) } # [doc = "Bit 9 - Set LIN Hardware Counter Overflow Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iset_linovf (& mut self) -> INT_EVENT0_ISET_LINOVF_W < INT_EVENT0_ISET_SPEC , 9 > { INT_EVENT0_ISET_LINOVF_W :: new (self) } # [doc = "Bit 10 - Set UART Receive Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iset_rxint (& mut self) -> INT_EVENT0_ISET_RXINT_W < INT_EVENT0_ISET_SPEC , 10 > { INT_EVENT0_ISET_RXINT_W :: new (self) } # [doc = "Bit 11 - Set UART Transmit Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iset_txint (& mut self) -> INT_EVENT0_ISET_TXINT_W < INT_EVENT0_ISET_SPEC , 11 > { INT_EVENT0_ISET_TXINT_W :: new (self) } # [doc = "Bit 12 - Set UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] # [inline (always)] # [must_use] pub fn int_event0_iset_eot (& mut self) -> INT_EVENT0_ISET_EOT_W < INT_EVENT0_ISET_SPEC , 12 > { INT_EVENT0_ISET_EOT_W :: new (self) } # [doc = "Bit 13 - Set Address Match Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iset_addr_match (& mut self) -> INT_EVENT0_ISET_ADDR_MATCH_W < INT_EVENT0_ISET_SPEC , 13 > { INT_EVENT0_ISET_ADDR_MATCH_W :: new (self) } # [doc = "Bit 14 - Set UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] # [inline (always)] # [must_use] pub fn int_event0_iset_cts (& mut self) -> INT_EVENT0_ISET_CTS_W < INT_EVENT0_ISET_SPEC , 14 > { INT_EVENT0_ISET_CTS_W :: new (self) } # [doc = "Bit 15 - Set DMA Done on RX Event Channel"] # [inline (always)] # [must_use] pub fn int_event0_iset_dma_done_rx (& mut self) -> INT_EVENT0_ISET_DMA_DONE_RX_W < INT_EVENT0_ISET_SPEC , 15 > { INT_EVENT0_ISET_DMA_DONE_RX_W :: new (self) } # [doc = "Bit 16 - Set DMA Done on TX Event Channel"] # [inline (always)] # [must_use] pub fn int_event0_iset_dma_done_tx (& mut self) -> INT_EVENT0_ISET_DMA_DONE_TX_W < INT_EVENT0_ISET_SPEC , 16 > { INT_EVENT0_ISET_DMA_DONE_TX_W :: new (self) } # [doc = "Bit 17 - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] # [inline (always)] # [must_use] pub fn int_event0_iset_nerr (& mut self) -> INT_EVENT0_ISET_NERR_W < INT_EVENT0_ISET_SPEC , 17 > { INT_EVENT0_ISET_NERR_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Interrupt set\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_event0_iset::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct INT_EVENT0_ISET_SPEC ; impl crate :: RegisterSpec for INT_EVENT0_ISET_SPEC { type Ux = u32 ; } # [doc = "`write(|w| ..)` method takes [`int_event0_iset::W`](W) writer structure"] impl crate :: Writable for INT_EVENT0_ISET_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets INT_EVENT0_ISET to value 0"] impl crate :: Resettable for INT_EVENT0_ISET_SPEC { const RESET_VALUE : Self :: Ux = 0 ; }
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                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                             +++
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing
[INFO] [stdout]  --> src/uart0/int_event0_iset.rs:1:22056
[INFO] [stdout]   |
[INFO] [stdout] 1 | ..._iset_parerr (& mut self) -> INT_EVENT0_ISET_PARERR_W < INT_EVENT0_ISET_SPEC , 2 > { INT_EVENT0_ISET_PARERR_W :: new (self) } # [d...
[INFO] [stdout]   |                  ^^^^^^^^^^     ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here
[INFO] [stdout]   |                  |
[INFO] [stdout]   |                  the lifetime is elided here
[INFO] [stdout]   |
[INFO] [stdout]   = help: the same lifetime is referred to in inconsistent ways, making the signature confusing
[INFO] [stdout] help: use `'_` for type paths
[INFO] [stdout]   |
[INFO] [stdout] 1 | # [doc = "Register `INT_EVENT0_ISET` writer"] pub type W = crate :: W < INT_EVENT0_ISET_SPEC > ; # [doc = "Set UARTOUT Receive Time-Out Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_RTOUT_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_RTOUT_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_RTOUT_SET = 1 , } impl From < INT_EVENT0_ISET_RTOUT_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_RTOUT_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_RTOUT` writer - Set UARTOUT Receive Time-Out Interrupt."] pub type INT_EVENT0_ISET_RTOUT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_RTOUT_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_RTOUT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_rtout_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_RTOUT_AW :: INT_EVENT0_ISET_RTOUT_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_rtout_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_RTOUT_AW :: INT_EVENT0_ISET_RTOUT_SET) } } # [doc = "Set UART Framing Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_FRMERR_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_FRMERR_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_FRMERR_SET = 1 , } impl From < INT_EVENT0_ISET_FRMERR_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_FRMERR_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_FRMERR` writer - Set UART Framing Error Interrupt."] pub type INT_EVENT0_ISET_FRMERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_FRMERR_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_FRMERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_frmerr_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_FRMERR_AW :: INT_EVENT0_ISET_FRMERR_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_frmerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_FRMERR_AW :: INT_EVENT0_ISET_FRMERR_SET) } } # [doc = "Set UART Parity Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_PARERR_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_PARERR_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_PARERR_SET = 1 , } impl From < INT_EVENT0_ISET_PARERR_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_PARERR_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_PARERR` writer - Set UART Parity Error Interrupt."] pub type INT_EVENT0_ISET_PARERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_PARERR_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_PARERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_parerr_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_PARERR_AW :: INT_EVENT0_ISET_PARERR_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_parerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_PARERR_AW :: INT_EVENT0_ISET_PARERR_SET) } } # [doc = "Set UART Break Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_BRKERR_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_BRKERR_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_BRKERR_SET = 1 , } impl From < INT_EVENT0_ISET_BRKERR_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_BRKERR_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_BRKERR` writer - Set UART Break Error Interrupt."] pub type INT_EVENT0_ISET_BRKERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_BRKERR_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_BRKERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_brkerr_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_BRKERR_AW :: INT_EVENT0_ISET_BRKERR_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_brkerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_BRKERR_AW :: INT_EVENT0_ISET_BRKERR_SET) } } # [doc = "Set UART Receive Overrun Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_OVRERR_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_OVRERR_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_OVRERR_SET = 1 , } impl From < INT_EVENT0_ISET_OVRERR_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_OVRERR_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_OVRERR` writer - Set UART Receive Overrun Error Interrupt."] pub type INT_EVENT0_ISET_OVRERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_OVRERR_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_OVRERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_ovrerr_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_OVRERR_AW :: INT_EVENT0_ISET_OVRERR_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_ovrerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_OVRERR_AW :: INT_EVENT0_ISET_OVRERR_SET) } } # [doc = "Set Negative Edge on UARTxRXD Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_RXNE_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_RXNE_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_RXNE_SET = 1 , } impl From < INT_EVENT0_ISET_RXNE_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_RXNE_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_RXNE` writer - Set Negative Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_ISET_RXNE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_RXNE_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_RXNE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_rxne_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_RXNE_AW :: INT_EVENT0_ISET_RXNE_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_rxne_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_RXNE_AW :: INT_EVENT0_ISET_RXNE_SET) } } # [doc = "Set Positive Edge on UARTxRXD Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_RXPE_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_RXPE_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_RXPE_SET = 1 , } impl From < INT_EVENT0_ISET_RXPE_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_RXPE_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_RXPE` writer - Set Positive Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_ISET_RXPE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_RXPE_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_RXPE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_rxpe_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_RXPE_AW :: INT_EVENT0_ISET_RXPE_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_rxpe_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_RXPE_AW :: INT_EVENT0_ISET_RXPE_SET) } } # [doc = "Set LIN Capture 0 / Match Interrupt .\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_LINC0_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_LINC0_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_LINC0_SET = 1 , } impl From < INT_EVENT0_ISET_LINC0_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_LINC0_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_LINC0` writer - Set LIN Capture 0 / Match Interrupt ."] pub type INT_EVENT0_ISET_LINC0_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_LINC0_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_LINC0_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_linc0_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_LINC0_AW :: INT_EVENT0_ISET_LINC0_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_linc0_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_LINC0_AW :: INT_EVENT0_ISET_LINC0_SET) } } # [doc = "Set LIN Capture 1 Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_LINC1_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_LINC1_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_LINC1_SET = 1 , } impl From < INT_EVENT0_ISET_LINC1_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_LINC1_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_LINC1` writer - Set LIN Capture 1 Interrupt."] pub type INT_EVENT0_ISET_LINC1_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_LINC1_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_LINC1_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_linc1_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_LINC1_AW :: INT_EVENT0_ISET_LINC1_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_linc1_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_LINC1_AW :: INT_EVENT0_ISET_LINC1_SET) } } # [doc = "Set LIN Hardware Counter Overflow Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_LINOVF_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_LINOVF_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_LINOVF_SET = 1 , } impl From < INT_EVENT0_ISET_LINOVF_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_LINOVF_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_LINOVF` writer - Set LIN Hardware Counter Overflow Interrupt."] pub type INT_EVENT0_ISET_LINOVF_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_LINOVF_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_LINOVF_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_linovf_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_LINOVF_AW :: INT_EVENT0_ISET_LINOVF_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_linovf_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_LINOVF_AW :: INT_EVENT0_ISET_LINOVF_SET) } } # [doc = "Set UART Receive Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_RXINT_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_RXINT_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_RXINT_SET = 1 , } impl From < INT_EVENT0_ISET_RXINT_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_RXINT_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_RXINT` writer - Set UART Receive Interrupt."] pub type INT_EVENT0_ISET_RXINT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_RXINT_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_RXINT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_rxint_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_RXINT_AW :: INT_EVENT0_ISET_RXINT_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_rxint_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_RXINT_AW :: INT_EVENT0_ISET_RXINT_SET) } } # [doc = "Set UART Transmit Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_TXINT_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_TXINT_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_TXINT_SET = 1 , } impl From < INT_EVENT0_ISET_TXINT_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_TXINT_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_TXINT` writer - Set UART Transmit Interrupt."] pub type INT_EVENT0_ISET_TXINT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_TXINT_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_TXINT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_txint_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_TXINT_AW :: INT_EVENT0_ISET_TXINT_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_txint_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_TXINT_AW :: INT_EVENT0_ISET_TXINT_SET) } } # [doc = "Set UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_EOT_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_EOT_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_EOT_SET = 1 , } impl From < INT_EVENT0_ISET_EOT_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_EOT_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_EOT` writer - Set UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] pub type INT_EVENT0_ISET_EOT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_EOT_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_EOT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_eot_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_EOT_AW :: INT_EVENT0_ISET_EOT_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_eot_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_EOT_AW :: INT_EVENT0_ISET_EOT_SET) } } # [doc = "Set Address Match Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_ADDR_MATCH_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_ADDR_MATCH_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_ADDR_MATCH_SET = 1 , } impl From < INT_EVENT0_ISET_ADDR_MATCH_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_ADDR_MATCH_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_ADDR_MATCH` writer - Set Address Match Interrupt."] pub type INT_EVENT0_ISET_ADDR_MATCH_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_ADDR_MATCH_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_ADDR_MATCH_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_addr_match_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_ADDR_MATCH_AW :: INT_EVENT0_ISET_ADDR_MATCH_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_addr_match_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_ADDR_MATCH_AW :: INT_EVENT0_ISET_ADDR_MATCH_SET) } } # [doc = "Set UART Clear to Send Modem Interrupt. 0 = Interrupt disabled\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_CTS_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_CTS_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_CTS_SET = 1 , } impl From < INT_EVENT0_ISET_CTS_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_CTS_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_CTS` writer - Set UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] pub type INT_EVENT0_ISET_CTS_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_CTS_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_CTS_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_cts_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_CTS_AW :: INT_EVENT0_ISET_CTS_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_cts_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_CTS_AW :: INT_EVENT0_ISET_CTS_SET) } } # [doc = "Set DMA Done on RX Event Channel\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_DMA_DONE_RX_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_DMA_DONE_RX_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_DMA_DONE_RX_SET = 1 , } impl From < INT_EVENT0_ISET_DMA_DONE_RX_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_DMA_DONE_RX_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_DMA_DONE_RX` writer - Set DMA Done on RX Event Channel"] pub type INT_EVENT0_ISET_DMA_DONE_RX_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_DMA_DONE_RX_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_DMA_DONE_RX_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_dma_done_rx_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_DMA_DONE_RX_AW :: INT_EVENT0_ISET_DMA_DONE_RX_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_dma_done_rx_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_DMA_DONE_RX_AW :: INT_EVENT0_ISET_DMA_DONE_RX_SET) } } # [doc = "Set DMA Done on TX Event Channel\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_DMA_DONE_TX_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_DMA_DONE_TX_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_DMA_DONE_TX_SET = 1 , } impl From < INT_EVENT0_ISET_DMA_DONE_TX_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_DMA_DONE_TX_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_DMA_DONE_TX` writer - Set DMA Done on TX Event Channel"] pub type INT_EVENT0_ISET_DMA_DONE_TX_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_DMA_DONE_TX_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_DMA_DONE_TX_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_dma_done_tx_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_DMA_DONE_TX_AW :: INT_EVENT0_ISET_DMA_DONE_TX_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_dma_done_tx_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_DMA_DONE_TX_AW :: INT_EVENT0_ISET_DMA_DONE_TX_SET) } } # [doc = "Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_NERR_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_NERR_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_NERR_SET = 1 , } impl From < INT_EVENT0_ISET_NERR_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_NERR_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_NERR` writer - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] pub type INT_EVENT0_ISET_NERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_NERR_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_NERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_nerr_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_NERR_AW :: INT_EVENT0_ISET_NERR_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_nerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_NERR_AW :: INT_EVENT0_ISET_NERR_SET) } } impl W { # [doc = "Bit 0 - Set UARTOUT Receive Time-Out Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iset_rtout (& mut self) -> INT_EVENT0_ISET_RTOUT_W < INT_EVENT0_ISET_SPEC , 0 > { INT_EVENT0_ISET_RTOUT_W :: new (self) } # [doc = "Bit 1 - Set UART Framing Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iset_frmerr (& mut self) -> INT_EVENT0_ISET_FRMERR_W < INT_EVENT0_ISET_SPEC , 1 > { INT_EVENT0_ISET_FRMERR_W :: new (self) } # [doc = "Bit 2 - Set UART Parity Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iset_parerr (& mut self) -> INT_EVENT0_ISET_PARERR_W <'_,  INT_EVENT0_ISET_SPEC , 2 > { INT_EVENT0_ISET_PARERR_W :: new (self) } # [doc = "Bit 3 - Set UART Break Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iset_brkerr (& mut self) -> INT_EVENT0_ISET_BRKERR_W < INT_EVENT0_ISET_SPEC , 3 > { INT_EVENT0_ISET_BRKERR_W :: new (self) } # [doc = "Bit 4 - Set UART Receive Overrun Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iset_ovrerr (& mut self) -> INT_EVENT0_ISET_OVRERR_W < INT_EVENT0_ISET_SPEC , 4 > { INT_EVENT0_ISET_OVRERR_W :: new (self) } # [doc = "Bit 5 - Set Negative Edge on UARTxRXD Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iset_rxne (& mut self) -> INT_EVENT0_ISET_RXNE_W < INT_EVENT0_ISET_SPEC , 5 > { INT_EVENT0_ISET_RXNE_W :: new (self) } # [doc = "Bit 6 - Set Positive Edge on UARTxRXD Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iset_rxpe (& mut self) -> INT_EVENT0_ISET_RXPE_W < INT_EVENT0_ISET_SPEC , 6 > { INT_EVENT0_ISET_RXPE_W :: new (self) } # [doc = "Bit 7 - Set LIN Capture 0 / Match Interrupt ."] # [inline (always)] # [must_use] pub fn int_event0_iset_linc0 (& mut self) -> INT_EVENT0_ISET_LINC0_W < INT_EVENT0_ISET_SPEC , 7 > { INT_EVENT0_ISET_LINC0_W :: new (self) } # [doc = "Bit 8 - Set LIN Capture 1 Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iset_linc1 (& mut self) -> INT_EVENT0_ISET_LINC1_W < INT_EVENT0_ISET_SPEC , 8 > { INT_EVENT0_ISET_LINC1_W :: new (self) } # [doc = "Bit 9 - Set LIN Hardware Counter Overflow Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iset_linovf (& mut self) -> INT_EVENT0_ISET_LINOVF_W < INT_EVENT0_ISET_SPEC , 9 > { INT_EVENT0_ISET_LINOVF_W :: new (self) } # [doc = "Bit 10 - Set UART Receive Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iset_rxint (& mut self) -> INT_EVENT0_ISET_RXINT_W < INT_EVENT0_ISET_SPEC , 10 > { INT_EVENT0_ISET_RXINT_W :: new (self) } # [doc = "Bit 11 - Set UART Transmit Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iset_txint (& mut self) -> INT_EVENT0_ISET_TXINT_W < INT_EVENT0_ISET_SPEC , 11 > { INT_EVENT0_ISET_TXINT_W :: new (self) } # [doc = "Bit 12 - Set UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] # [inline (always)] # [must_use] pub fn int_event0_iset_eot (& mut self) -> INT_EVENT0_ISET_EOT_W < INT_EVENT0_ISET_SPEC , 12 > { INT_EVENT0_ISET_EOT_W :: new (self) } # [doc = "Bit 13 - Set Address Match Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iset_addr_match (& mut self) -> INT_EVENT0_ISET_ADDR_MATCH_W < INT_EVENT0_ISET_SPEC , 13 > { INT_EVENT0_ISET_ADDR_MATCH_W :: new (self) } # [doc = "Bit 14 - Set UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] # [inline (always)] # [must_use] pub fn int_event0_iset_cts (& mut self) -> INT_EVENT0_ISET_CTS_W < INT_EVENT0_ISET_SPEC , 14 > { INT_EVENT0_ISET_CTS_W :: new (self) } # [doc = "Bit 15 - Set DMA Done on RX Event Channel"] # [inline (always)] # [must_use] pub fn int_event0_iset_dma_done_rx (& mut self) -> INT_EVENT0_ISET_DMA_DONE_RX_W < INT_EVENT0_ISET_SPEC , 15 > { INT_EVENT0_ISET_DMA_DONE_RX_W :: new (self) } # [doc = "Bit 16 - Set DMA Done on TX Event Channel"] # [inline (always)] # [must_use] pub fn int_event0_iset_dma_done_tx (& mut self) -> INT_EVENT0_ISET_DMA_DONE_TX_W < INT_EVENT0_ISET_SPEC , 16 > { INT_EVENT0_ISET_DMA_DONE_TX_W :: new (self) } # [doc = "Bit 17 - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] # [inline (always)] # [must_use] pub fn int_event0_iset_nerr (& mut self) -> INT_EVENT0_ISET_NERR_W < INT_EVENT0_ISET_SPEC , 17 > { INT_EVENT0_ISET_NERR_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Interrupt set\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_event0_iset::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct INT_EVENT0_ISET_SPEC ; impl crate :: RegisterSpec for INT_EVENT0_ISET_SPEC { type Ux = u32 ; } # [doc = "`write(|w| ..)` method takes [`int_event0_iset::W`](W) writer structure"] impl crate :: Writable for INT_EVENT0_ISET_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets INT_EVENT0_ISET to value 0"] impl crate :: Resettable for INT_EVENT0_ISET_SPEC { const RESET_VALUE : Self :: Ux = 0 ; }
[INFO] [stdout]   |                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                 +++
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing
[INFO] [stdout]  --> src/uart0/int_event0_iset.rs:1:22284
[INFO] [stdout]   |
[INFO] [stdout] 1 | ..._iset_brkerr (& mut self) -> INT_EVENT0_ISET_BRKERR_W < INT_EVENT0_ISET_SPEC , 3 > { INT_EVENT0_ISET_BRKERR_W :: new (self) } # [d...
[INFO] [stdout]   |                  ^^^^^^^^^^     ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here
[INFO] [stdout]   |                  |
[INFO] [stdout]   |                  the lifetime is elided here
[INFO] [stdout]   |
[INFO] [stdout]   = help: the same lifetime is referred to in inconsistent ways, making the signature confusing
[INFO] [stdout] help: use `'_` for type paths
[INFO] [stdout]   |
[INFO] [stdout] 1 | # [doc = "Register `INT_EVENT0_ISET` writer"] pub type W = crate :: W < INT_EVENT0_ISET_SPEC > ; # [doc = "Set UARTOUT Receive Time-Out Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_RTOUT_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_RTOUT_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_RTOUT_SET = 1 , } impl From < INT_EVENT0_ISET_RTOUT_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_RTOUT_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_RTOUT` writer - Set UARTOUT Receive Time-Out Interrupt."] pub type INT_EVENT0_ISET_RTOUT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_RTOUT_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_RTOUT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_rtout_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_RTOUT_AW :: INT_EVENT0_ISET_RTOUT_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_rtout_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_RTOUT_AW :: INT_EVENT0_ISET_RTOUT_SET) } } # [doc = "Set UART Framing Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_FRMERR_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_FRMERR_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_FRMERR_SET = 1 , } impl From < INT_EVENT0_ISET_FRMERR_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_FRMERR_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_FRMERR` writer - Set UART Framing Error Interrupt."] pub type INT_EVENT0_ISET_FRMERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_FRMERR_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_FRMERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_frmerr_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_FRMERR_AW :: INT_EVENT0_ISET_FRMERR_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_frmerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_FRMERR_AW :: INT_EVENT0_ISET_FRMERR_SET) } } # [doc = "Set UART Parity Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_PARERR_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_PARERR_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_PARERR_SET = 1 , } impl From < INT_EVENT0_ISET_PARERR_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_PARERR_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_PARERR` writer - Set UART Parity Error Interrupt."] pub type INT_EVENT0_ISET_PARERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_PARERR_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_PARERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_parerr_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_PARERR_AW :: INT_EVENT0_ISET_PARERR_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_parerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_PARERR_AW :: INT_EVENT0_ISET_PARERR_SET) } } # [doc = "Set UART Break Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_BRKERR_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_BRKERR_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_BRKERR_SET = 1 , } impl From < INT_EVENT0_ISET_BRKERR_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_BRKERR_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_BRKERR` writer - Set UART Break Error Interrupt."] pub type INT_EVENT0_ISET_BRKERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_BRKERR_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_BRKERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_brkerr_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_BRKERR_AW :: INT_EVENT0_ISET_BRKERR_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_brkerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_BRKERR_AW :: INT_EVENT0_ISET_BRKERR_SET) } } # [doc = "Set UART Receive Overrun Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_OVRERR_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_OVRERR_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_OVRERR_SET = 1 , } impl From < INT_EVENT0_ISET_OVRERR_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_OVRERR_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_OVRERR` writer - Set UART Receive Overrun Error Interrupt."] pub type INT_EVENT0_ISET_OVRERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_OVRERR_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_OVRERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_ovrerr_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_OVRERR_AW :: INT_EVENT0_ISET_OVRERR_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_ovrerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_OVRERR_AW :: INT_EVENT0_ISET_OVRERR_SET) } } # [doc = "Set Negative Edge on UARTxRXD Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_RXNE_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_RXNE_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_RXNE_SET = 1 , } impl From < INT_EVENT0_ISET_RXNE_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_RXNE_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_RXNE` writer - Set Negative Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_ISET_RXNE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_RXNE_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_RXNE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_rxne_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_RXNE_AW :: INT_EVENT0_ISET_RXNE_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_rxne_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_RXNE_AW :: INT_EVENT0_ISET_RXNE_SET) } } # [doc = "Set Positive Edge on UARTxRXD Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_RXPE_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_RXPE_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_RXPE_SET = 1 , } impl From < INT_EVENT0_ISET_RXPE_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_RXPE_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_RXPE` writer - Set Positive Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_ISET_RXPE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_RXPE_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_RXPE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_rxpe_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_RXPE_AW :: INT_EVENT0_ISET_RXPE_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_rxpe_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_RXPE_AW :: INT_EVENT0_ISET_RXPE_SET) } } # [doc = "Set LIN Capture 0 / Match Interrupt .\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_LINC0_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_LINC0_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_LINC0_SET = 1 , } impl From < INT_EVENT0_ISET_LINC0_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_LINC0_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_LINC0` writer - Set LIN Capture 0 / Match Interrupt ."] pub type INT_EVENT0_ISET_LINC0_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_LINC0_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_LINC0_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_linc0_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_LINC0_AW :: INT_EVENT0_ISET_LINC0_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_linc0_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_LINC0_AW :: INT_EVENT0_ISET_LINC0_SET) } } # [doc = "Set LIN Capture 1 Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_LINC1_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_LINC1_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_LINC1_SET = 1 , } impl From < INT_EVENT0_ISET_LINC1_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_LINC1_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_LINC1` writer - Set LIN Capture 1 Interrupt."] pub type INT_EVENT0_ISET_LINC1_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_LINC1_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_LINC1_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_linc1_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_LINC1_AW :: INT_EVENT0_ISET_LINC1_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_linc1_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_LINC1_AW :: INT_EVENT0_ISET_LINC1_SET) } } # [doc = "Set LIN Hardware Counter Overflow Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_LINOVF_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_LINOVF_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_LINOVF_SET = 1 , } impl From < INT_EVENT0_ISET_LINOVF_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_LINOVF_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_LINOVF` writer - Set LIN Hardware Counter Overflow Interrupt."] pub type INT_EVENT0_ISET_LINOVF_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_LINOVF_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_LINOVF_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_linovf_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_LINOVF_AW :: INT_EVENT0_ISET_LINOVF_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_linovf_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_LINOVF_AW :: INT_EVENT0_ISET_LINOVF_SET) } } # [doc = "Set UART Receive Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_RXINT_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_RXINT_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_RXINT_SET = 1 , } impl From < INT_EVENT0_ISET_RXINT_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_RXINT_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_RXINT` writer - Set UART Receive Interrupt."] pub type INT_EVENT0_ISET_RXINT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_RXINT_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_RXINT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_rxint_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_RXINT_AW :: INT_EVENT0_ISET_RXINT_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_rxint_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_RXINT_AW :: INT_EVENT0_ISET_RXINT_SET) } } # [doc = "Set UART Transmit Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_TXINT_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_TXINT_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_TXINT_SET = 1 , } impl From < INT_EVENT0_ISET_TXINT_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_TXINT_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_TXINT` writer - Set UART Transmit Interrupt."] pub type INT_EVENT0_ISET_TXINT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_TXINT_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_TXINT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_txint_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_TXINT_AW :: INT_EVENT0_ISET_TXINT_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_txint_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_TXINT_AW :: INT_EVENT0_ISET_TXINT_SET) } } # [doc = "Set UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_EOT_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_EOT_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_EOT_SET = 1 , } impl From < INT_EVENT0_ISET_EOT_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_EOT_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_EOT` writer - Set UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] pub type INT_EVENT0_ISET_EOT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_EOT_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_EOT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_eot_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_EOT_AW :: INT_EVENT0_ISET_EOT_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_eot_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_EOT_AW :: INT_EVENT0_ISET_EOT_SET) } } # [doc = "Set Address Match Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_ADDR_MATCH_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_ADDR_MATCH_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_ADDR_MATCH_SET = 1 , } impl From < INT_EVENT0_ISET_ADDR_MATCH_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_ADDR_MATCH_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_ADDR_MATCH` writer - Set Address Match Interrupt."] pub type INT_EVENT0_ISET_ADDR_MATCH_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_ADDR_MATCH_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_ADDR_MATCH_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_addr_match_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_ADDR_MATCH_AW :: INT_EVENT0_ISET_ADDR_MATCH_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_addr_match_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_ADDR_MATCH_AW :: INT_EVENT0_ISET_ADDR_MATCH_SET) } } # [doc = "Set UART Clear to Send Modem Interrupt. 0 = Interrupt disabled\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_CTS_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_CTS_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_CTS_SET = 1 , } impl From < INT_EVENT0_ISET_CTS_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_CTS_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_CTS` writer - Set UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] pub type INT_EVENT0_ISET_CTS_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_CTS_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_CTS_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_cts_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_CTS_AW :: INT_EVENT0_ISET_CTS_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_cts_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_CTS_AW :: INT_EVENT0_ISET_CTS_SET) } } # [doc = "Set DMA Done on RX Event Channel\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_DMA_DONE_RX_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_DMA_DONE_RX_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_DMA_DONE_RX_SET = 1 , } impl From < INT_EVENT0_ISET_DMA_DONE_RX_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_DMA_DONE_RX_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_DMA_DONE_RX` writer - Set DMA Done on RX Event Channel"] pub type INT_EVENT0_ISET_DMA_DONE_RX_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_DMA_DONE_RX_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_DMA_DONE_RX_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_dma_done_rx_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_DMA_DONE_RX_AW :: INT_EVENT0_ISET_DMA_DONE_RX_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_dma_done_rx_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_DMA_DONE_RX_AW :: INT_EVENT0_ISET_DMA_DONE_RX_SET) } } # [doc = "Set DMA Done on TX Event Channel\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_DMA_DONE_TX_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_DMA_DONE_TX_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_DMA_DONE_TX_SET = 1 , } impl From < INT_EVENT0_ISET_DMA_DONE_TX_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_DMA_DONE_TX_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_DMA_DONE_TX` writer - Set DMA Done on TX Event Channel"] pub type INT_EVENT0_ISET_DMA_DONE_TX_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_DMA_DONE_TX_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_DMA_DONE_TX_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_dma_done_tx_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_DMA_DONE_TX_AW :: INT_EVENT0_ISET_DMA_DONE_TX_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_dma_done_tx_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_DMA_DONE_TX_AW :: INT_EVENT0_ISET_DMA_DONE_TX_SET) } } # [doc = "Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_NERR_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_NERR_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_NERR_SET = 1 , } impl From < INT_EVENT0_ISET_NERR_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_NERR_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_NERR` writer - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] pub type INT_EVENT0_ISET_NERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_NERR_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_NERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_nerr_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_NERR_AW :: INT_EVENT0_ISET_NERR_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_nerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_NERR_AW :: INT_EVENT0_ISET_NERR_SET) } } impl W { # [doc = "Bit 0 - Set UARTOUT Receive Time-Out Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iset_rtout (& mut self) -> INT_EVENT0_ISET_RTOUT_W < INT_EVENT0_ISET_SPEC , 0 > { INT_EVENT0_ISET_RTOUT_W :: new (self) } # [doc = "Bit 1 - Set UART Framing Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iset_frmerr (& mut self) -> INT_EVENT0_ISET_FRMERR_W < INT_EVENT0_ISET_SPEC , 1 > { INT_EVENT0_ISET_FRMERR_W :: new (self) } # [doc = "Bit 2 - Set UART Parity Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iset_parerr (& mut self) -> INT_EVENT0_ISET_PARERR_W < INT_EVENT0_ISET_SPEC , 2 > { INT_EVENT0_ISET_PARERR_W :: new (self) } # [doc = "Bit 3 - Set UART Break Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iset_brkerr (& mut self) -> INT_EVENT0_ISET_BRKERR_W <'_,  INT_EVENT0_ISET_SPEC , 3 > { INT_EVENT0_ISET_BRKERR_W :: new (self) } # [doc = "Bit 4 - Set UART Receive Overrun Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iset_ovrerr (& mut self) -> INT_EVENT0_ISET_OVRERR_W < INT_EVENT0_ISET_SPEC , 4 > { INT_EVENT0_ISET_OVRERR_W :: new (self) } # [doc = "Bit 5 - Set Negative Edge on UARTxRXD Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iset_rxne (& mut self) -> INT_EVENT0_ISET_RXNE_W < INT_EVENT0_ISET_SPEC , 5 > { INT_EVENT0_ISET_RXNE_W :: new (self) } # [doc = "Bit 6 - Set Positive Edge on UARTxRXD Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iset_rxpe (& mut self) -> INT_EVENT0_ISET_RXPE_W < INT_EVENT0_ISET_SPEC , 6 > { INT_EVENT0_ISET_RXPE_W :: new (self) } # [doc = "Bit 7 - Set LIN Capture 0 / Match Interrupt ."] # [inline (always)] # [must_use] pub fn int_event0_iset_linc0 (& mut self) -> INT_EVENT0_ISET_LINC0_W < INT_EVENT0_ISET_SPEC , 7 > { INT_EVENT0_ISET_LINC0_W :: new (self) } # [doc = "Bit 8 - Set LIN Capture 1 Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iset_linc1 (& mut self) -> INT_EVENT0_ISET_LINC1_W < INT_EVENT0_ISET_SPEC , 8 > { INT_EVENT0_ISET_LINC1_W :: new (self) } # [doc = "Bit 9 - Set LIN Hardware Counter Overflow Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iset_linovf (& mut self) -> INT_EVENT0_ISET_LINOVF_W < INT_EVENT0_ISET_SPEC , 9 > { INT_EVENT0_ISET_LINOVF_W :: new (self) } # [doc = "Bit 10 - Set UART Receive Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iset_rxint (& mut self) -> INT_EVENT0_ISET_RXINT_W < INT_EVENT0_ISET_SPEC , 10 > { INT_EVENT0_ISET_RXINT_W :: new (self) } # [doc = "Bit 11 - Set UART Transmit Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iset_txint (& mut self) -> INT_EVENT0_ISET_TXINT_W < INT_EVENT0_ISET_SPEC , 11 > { INT_EVENT0_ISET_TXINT_W :: new (self) } # [doc = "Bit 12 - Set UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] # [inline (always)] # [must_use] pub fn int_event0_iset_eot (& mut self) -> INT_EVENT0_ISET_EOT_W < INT_EVENT0_ISET_SPEC , 12 > { INT_EVENT0_ISET_EOT_W :: new (self) } # [doc = "Bit 13 - Set Address Match Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iset_addr_match (& mut self) -> INT_EVENT0_ISET_ADDR_MATCH_W < INT_EVENT0_ISET_SPEC , 13 > { INT_EVENT0_ISET_ADDR_MATCH_W :: new (self) } # [doc = "Bit 14 - Set UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] # [inline (always)] # [must_use] pub fn int_event0_iset_cts (& mut self) -> INT_EVENT0_ISET_CTS_W < INT_EVENT0_ISET_SPEC , 14 > { INT_EVENT0_ISET_CTS_W :: new (self) } # [doc = "Bit 15 - Set DMA Done on RX Event Channel"] # [inline (always)] # [must_use] pub fn int_event0_iset_dma_done_rx (& mut self) -> INT_EVENT0_ISET_DMA_DONE_RX_W < INT_EVENT0_ISET_SPEC , 15 > { INT_EVENT0_ISET_DMA_DONE_RX_W :: new (self) } # [doc = "Bit 16 - Set DMA Done on TX Event Channel"] # [inline (always)] # [must_use] pub fn int_event0_iset_dma_done_tx (& mut self) -> INT_EVENT0_ISET_DMA_DONE_TX_W < INT_EVENT0_ISET_SPEC , 16 > { INT_EVENT0_ISET_DMA_DONE_TX_W :: new (self) } # [doc = "Bit 17 - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] # [inline (always)] # [must_use] pub fn int_event0_iset_nerr (& mut self) -> INT_EVENT0_ISET_NERR_W < INT_EVENT0_ISET_SPEC , 17 > { INT_EVENT0_ISET_NERR_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Interrupt set\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_event0_iset::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct INT_EVENT0_ISET_SPEC ; impl crate :: RegisterSpec for INT_EVENT0_ISET_SPEC { type Ux = u32 ; } # [doc = "`write(|w| ..)` method takes [`int_event0_iset::W`](W) writer structure"] impl crate :: Writable for INT_EVENT0_ISET_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets INT_EVENT0_ISET to value 0"] impl crate :: Resettable for INT_EVENT0_ISET_SPEC { const RESET_VALUE : Self :: Ux = 0 ; }
[INFO] [stdout]   |                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                     +++
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing
[INFO] [stdout]  --> src/uart0/int_event0_iset.rs:1:22522
[INFO] [stdout]   |
[INFO] [stdout] 1 | ..._iset_ovrerr (& mut self) -> INT_EVENT0_ISET_OVRERR_W < INT_EVENT0_ISET_SPEC , 4 > { INT_EVENT0_ISET_OVRERR_W :: new (self) } # [d...
[INFO] [stdout]   |                  ^^^^^^^^^^     ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here
[INFO] [stdout]   |                  |
[INFO] [stdout]   |                  the lifetime is elided here
[INFO] [stdout]   |
[INFO] [stdout]   = help: the same lifetime is referred to in inconsistent ways, making the signature confusing
[INFO] [stdout] help: use `'_` for type paths
[INFO] [stdout]   |
[INFO] [stdout] 1 | # [doc = "Register `INT_EVENT0_ISET` writer"] pub type W = crate :: W < INT_EVENT0_ISET_SPEC > ; # [doc = "Set UARTOUT Receive Time-Out Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_RTOUT_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_RTOUT_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_RTOUT_SET = 1 , } impl From < INT_EVENT0_ISET_RTOUT_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_RTOUT_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_RTOUT` writer - Set UARTOUT Receive Time-Out Interrupt."] pub type INT_EVENT0_ISET_RTOUT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_RTOUT_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_RTOUT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_rtout_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_RTOUT_AW :: INT_EVENT0_ISET_RTOUT_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_rtout_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_RTOUT_AW :: INT_EVENT0_ISET_RTOUT_SET) } } # [doc = "Set UART Framing Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_FRMERR_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_FRMERR_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_FRMERR_SET = 1 , } impl From < INT_EVENT0_ISET_FRMERR_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_FRMERR_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_FRMERR` writer - Set UART Framing Error Interrupt."] pub type INT_EVENT0_ISET_FRMERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_FRMERR_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_FRMERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_frmerr_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_FRMERR_AW :: INT_EVENT0_ISET_FRMERR_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_frmerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_FRMERR_AW :: INT_EVENT0_ISET_FRMERR_SET) } } # [doc = "Set UART Parity Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_PARERR_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_PARERR_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_PARERR_SET = 1 , } impl From < INT_EVENT0_ISET_PARERR_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_PARERR_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_PARERR` writer - Set UART Parity Error Interrupt."] pub type INT_EVENT0_ISET_PARERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_PARERR_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_PARERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_parerr_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_PARERR_AW :: INT_EVENT0_ISET_PARERR_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_parerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_PARERR_AW :: INT_EVENT0_ISET_PARERR_SET) } } # [doc = "Set UART Break Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_BRKERR_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_BRKERR_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_BRKERR_SET = 1 , } impl From < INT_EVENT0_ISET_BRKERR_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_BRKERR_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_BRKERR` writer - Set UART Break Error Interrupt."] pub type INT_EVENT0_ISET_BRKERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_BRKERR_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_BRKERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_brkerr_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_BRKERR_AW :: INT_EVENT0_ISET_BRKERR_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_brkerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_BRKERR_AW :: INT_EVENT0_ISET_BRKERR_SET) } } # [doc = "Set UART Receive Overrun Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_OVRERR_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_OVRERR_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_OVRERR_SET = 1 , } impl From < INT_EVENT0_ISET_OVRERR_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_OVRERR_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_OVRERR` writer - Set UART Receive Overrun Error Interrupt."] pub type INT_EVENT0_ISET_OVRERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_OVRERR_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_OVRERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_ovrerr_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_OVRERR_AW :: INT_EVENT0_ISET_OVRERR_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_ovrerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_OVRERR_AW :: INT_EVENT0_ISET_OVRERR_SET) } } # [doc = "Set Negative Edge on UARTxRXD Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_RXNE_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_RXNE_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_RXNE_SET = 1 , } impl From < INT_EVENT0_ISET_RXNE_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_RXNE_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_RXNE` writer - Set Negative Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_ISET_RXNE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_RXNE_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_RXNE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_rxne_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_RXNE_AW :: INT_EVENT0_ISET_RXNE_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_rxne_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_RXNE_AW :: INT_EVENT0_ISET_RXNE_SET) } } # [doc = "Set Positive Edge on UARTxRXD Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_RXPE_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_RXPE_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_RXPE_SET = 1 , } impl From < INT_EVENT0_ISET_RXPE_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_RXPE_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_RXPE` writer - Set Positive Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_ISET_RXPE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_RXPE_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_RXPE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_rxpe_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_RXPE_AW :: INT_EVENT0_ISET_RXPE_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_rxpe_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_RXPE_AW :: INT_EVENT0_ISET_RXPE_SET) } } # [doc = "Set LIN Capture 0 / Match Interrupt .\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_LINC0_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_LINC0_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_LINC0_SET = 1 , } impl From < INT_EVENT0_ISET_LINC0_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_LINC0_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_LINC0` writer - Set LIN Capture 0 / Match Interrupt ."] pub type INT_EVENT0_ISET_LINC0_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_LINC0_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_LINC0_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_linc0_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_LINC0_AW :: INT_EVENT0_ISET_LINC0_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_linc0_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_LINC0_AW :: INT_EVENT0_ISET_LINC0_SET) } } # [doc = "Set LIN Capture 1 Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_LINC1_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_LINC1_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_LINC1_SET = 1 , } impl From < INT_EVENT0_ISET_LINC1_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_LINC1_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_LINC1` writer - Set LIN Capture 1 Interrupt."] pub type INT_EVENT0_ISET_LINC1_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_LINC1_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_LINC1_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_linc1_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_LINC1_AW :: INT_EVENT0_ISET_LINC1_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_linc1_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_LINC1_AW :: INT_EVENT0_ISET_LINC1_SET) } } # [doc = "Set LIN Hardware Counter Overflow Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_LINOVF_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_LINOVF_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_LINOVF_SET = 1 , } impl From < INT_EVENT0_ISET_LINOVF_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_LINOVF_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_LINOVF` writer - Set LIN Hardware Counter Overflow Interrupt."] pub type INT_EVENT0_ISET_LINOVF_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_LINOVF_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_LINOVF_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_linovf_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_LINOVF_AW :: INT_EVENT0_ISET_LINOVF_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_linovf_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_LINOVF_AW :: INT_EVENT0_ISET_LINOVF_SET) } } # [doc = "Set UART Receive Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_RXINT_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_RXINT_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_RXINT_SET = 1 , } impl From < INT_EVENT0_ISET_RXINT_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_RXINT_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_RXINT` writer - Set UART Receive Interrupt."] pub type INT_EVENT0_ISET_RXINT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_RXINT_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_RXINT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_rxint_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_RXINT_AW :: INT_EVENT0_ISET_RXINT_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_rxint_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_RXINT_AW :: INT_EVENT0_ISET_RXINT_SET) } } # [doc = "Set UART Transmit Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_TXINT_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_TXINT_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_TXINT_SET = 1 , } impl From < INT_EVENT0_ISET_TXINT_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_TXINT_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_TXINT` writer - Set UART Transmit Interrupt."] pub type INT_EVENT0_ISET_TXINT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_TXINT_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_TXINT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_txint_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_TXINT_AW :: INT_EVENT0_ISET_TXINT_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_txint_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_TXINT_AW :: INT_EVENT0_ISET_TXINT_SET) } } # [doc = "Set UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_EOT_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_EOT_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_EOT_SET = 1 , } impl From < INT_EVENT0_ISET_EOT_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_EOT_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_EOT` writer - Set UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] pub type INT_EVENT0_ISET_EOT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_EOT_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_EOT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_eot_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_EOT_AW :: INT_EVENT0_ISET_EOT_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_eot_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_EOT_AW :: INT_EVENT0_ISET_EOT_SET) } } # [doc = "Set Address Match Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_ADDR_MATCH_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_ADDR_MATCH_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_ADDR_MATCH_SET = 1 , } impl From < INT_EVENT0_ISET_ADDR_MATCH_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_ADDR_MATCH_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_ADDR_MATCH` writer - Set Address Match Interrupt."] pub type INT_EVENT0_ISET_ADDR_MATCH_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_ADDR_MATCH_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_ADDR_MATCH_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_addr_match_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_ADDR_MATCH_AW :: INT_EVENT0_ISET_ADDR_MATCH_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_addr_match_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_ADDR_MATCH_AW :: INT_EVENT0_ISET_ADDR_MATCH_SET) } } # [doc = "Set UART Clear to Send Modem Interrupt. 0 = Interrupt disabled\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_CTS_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_CTS_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_CTS_SET = 1 , } impl From < INT_EVENT0_ISET_CTS_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_CTS_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_CTS` writer - Set UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] pub type INT_EVENT0_ISET_CTS_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_CTS_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_CTS_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_cts_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_CTS_AW :: INT_EVENT0_ISET_CTS_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_cts_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_CTS_AW :: INT_EVENT0_ISET_CTS_SET) } } # [doc = "Set DMA Done on RX Event Channel\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_DMA_DONE_RX_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_DMA_DONE_RX_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_DMA_DONE_RX_SET = 1 , } impl From < INT_EVENT0_ISET_DMA_DONE_RX_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_DMA_DONE_RX_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_DMA_DONE_RX` writer - Set DMA Done on RX Event Channel"] pub type INT_EVENT0_ISET_DMA_DONE_RX_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_DMA_DONE_RX_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_DMA_DONE_RX_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_dma_done_rx_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_DMA_DONE_RX_AW :: INT_EVENT0_ISET_DMA_DONE_RX_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_dma_done_rx_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_DMA_DONE_RX_AW :: INT_EVENT0_ISET_DMA_DONE_RX_SET) } } # [doc = "Set DMA Done on TX Event Channel\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_DMA_DONE_TX_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_DMA_DONE_TX_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_DMA_DONE_TX_SET = 1 , } impl From < INT_EVENT0_ISET_DMA_DONE_TX_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_DMA_DONE_TX_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_DMA_DONE_TX` writer - Set DMA Done on TX Event Channel"] pub type INT_EVENT0_ISET_DMA_DONE_TX_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_DMA_DONE_TX_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_DMA_DONE_TX_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_dma_done_tx_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_DMA_DONE_TX_AW :: INT_EVENT0_ISET_DMA_DONE_TX_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_dma_done_tx_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_DMA_DONE_TX_AW :: INT_EVENT0_ISET_DMA_DONE_TX_SET) } } # [doc = "Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_NERR_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_NERR_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_NERR_SET = 1 , } impl From < INT_EVENT0_ISET_NERR_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_NERR_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_NERR` writer - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] pub type INT_EVENT0_ISET_NERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_NERR_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_NERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_nerr_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_NERR_AW :: INT_EVENT0_ISET_NERR_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_nerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_NERR_AW :: INT_EVENT0_ISET_NERR_SET) } } impl W { # [doc = "Bit 0 - Set UARTOUT Receive Time-Out Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iset_rtout (& mut self) -> INT_EVENT0_ISET_RTOUT_W < INT_EVENT0_ISET_SPEC , 0 > { INT_EVENT0_ISET_RTOUT_W :: new (self) } # [doc = "Bit 1 - Set UART Framing Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iset_frmerr (& mut self) -> INT_EVENT0_ISET_FRMERR_W < INT_EVENT0_ISET_SPEC , 1 > { INT_EVENT0_ISET_FRMERR_W :: new (self) } # [doc = "Bit 2 - Set UART Parity Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iset_parerr (& mut self) -> INT_EVENT0_ISET_PARERR_W < INT_EVENT0_ISET_SPEC , 2 > { INT_EVENT0_ISET_PARERR_W :: new (self) } # [doc = "Bit 3 - Set UART Break Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iset_brkerr (& mut self) -> INT_EVENT0_ISET_BRKERR_W < INT_EVENT0_ISET_SPEC , 3 > { INT_EVENT0_ISET_BRKERR_W :: new (self) } # [doc = "Bit 4 - Set UART Receive Overrun Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iset_ovrerr (& mut self) -> INT_EVENT0_ISET_OVRERR_W <'_,  INT_EVENT0_ISET_SPEC , 4 > { INT_EVENT0_ISET_OVRERR_W :: new (self) } # [doc = "Bit 5 - Set Negative Edge on UARTxRXD Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iset_rxne (& mut self) -> INT_EVENT0_ISET_RXNE_W < INT_EVENT0_ISET_SPEC , 5 > { INT_EVENT0_ISET_RXNE_W :: new (self) } # [doc = "Bit 6 - Set Positive Edge on UARTxRXD Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iset_rxpe (& mut self) -> INT_EVENT0_ISET_RXPE_W < INT_EVENT0_ISET_SPEC , 6 > { INT_EVENT0_ISET_RXPE_W :: new (self) } # [doc = "Bit 7 - Set LIN Capture 0 / Match Interrupt ."] # [inline (always)] # [must_use] pub fn int_event0_iset_linc0 (& mut self) -> INT_EVENT0_ISET_LINC0_W < INT_EVENT0_ISET_SPEC , 7 > { INT_EVENT0_ISET_LINC0_W :: new (self) } # [doc = "Bit 8 - Set LIN Capture 1 Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iset_linc1 (& mut self) -> INT_EVENT0_ISET_LINC1_W < INT_EVENT0_ISET_SPEC , 8 > { INT_EVENT0_ISET_LINC1_W :: new (self) } # [doc = "Bit 9 - Set LIN Hardware Counter Overflow Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iset_linovf (& mut self) -> INT_EVENT0_ISET_LINOVF_W < INT_EVENT0_ISET_SPEC , 9 > { INT_EVENT0_ISET_LINOVF_W :: new (self) } # [doc = "Bit 10 - Set UART Receive Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iset_rxint (& mut self) -> INT_EVENT0_ISET_RXINT_W < INT_EVENT0_ISET_SPEC , 10 > { INT_EVENT0_ISET_RXINT_W :: new (self) } # [doc = "Bit 11 - Set UART Transmit Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iset_txint (& mut self) -> INT_EVENT0_ISET_TXINT_W < INT_EVENT0_ISET_SPEC , 11 > { INT_EVENT0_ISET_TXINT_W :: new (self) } # [doc = "Bit 12 - Set UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] # [inline (always)] # [must_use] pub fn int_event0_iset_eot (& mut self) -> INT_EVENT0_ISET_EOT_W < INT_EVENT0_ISET_SPEC , 12 > { INT_EVENT0_ISET_EOT_W :: new (self) } # [doc = "Bit 13 - Set Address Match Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iset_addr_match (& mut self) -> INT_EVENT0_ISET_ADDR_MATCH_W < INT_EVENT0_ISET_SPEC , 13 > { INT_EVENT0_ISET_ADDR_MATCH_W :: new (self) } # [doc = "Bit 14 - Set UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] # [inline (always)] # [must_use] pub fn int_event0_iset_cts (& mut self) -> INT_EVENT0_ISET_CTS_W < INT_EVENT0_ISET_SPEC , 14 > { INT_EVENT0_ISET_CTS_W :: new (self) } # [doc = "Bit 15 - Set DMA Done on RX Event Channel"] # [inline (always)] # [must_use] pub fn int_event0_iset_dma_done_rx (& mut self) -> INT_EVENT0_ISET_DMA_DONE_RX_W < INT_EVENT0_ISET_SPEC , 15 > { INT_EVENT0_ISET_DMA_DONE_RX_W :: new (self) } # [doc = "Bit 16 - Set DMA Done on TX Event Channel"] # [inline (always)] # [must_use] pub fn int_event0_iset_dma_done_tx (& mut self) -> INT_EVENT0_ISET_DMA_DONE_TX_W < INT_EVENT0_ISET_SPEC , 16 > { INT_EVENT0_ISET_DMA_DONE_TX_W :: new (self) } # [doc = "Bit 17 - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] # [inline (always)] # [must_use] pub fn int_event0_iset_nerr (& mut self) -> INT_EVENT0_ISET_NERR_W < INT_EVENT0_ISET_SPEC , 17 > { INT_EVENT0_ISET_NERR_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Interrupt set\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_event0_iset::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct INT_EVENT0_ISET_SPEC ; impl crate :: RegisterSpec for INT_EVENT0_ISET_SPEC { type Ux = u32 ; } # [doc = "`write(|w| ..)` method takes [`int_event0_iset::W`](W) writer structure"] impl crate :: Writable for INT_EVENT0_ISET_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets INT_EVENT0_ISET to value 0"] impl crate :: Resettable for INT_EVENT0_ISET_SPEC { const RESET_VALUE : Self :: Ux = 0 ; }
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                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                    +++
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing
[INFO] [stdout]  --> src/uart0/int_event0_iset.rs:1:22757
[INFO] [stdout]   |
[INFO] [stdout] 1 | ...nt0_iset_rxne (& mut self) -> INT_EVENT0_ISET_RXNE_W < INT_EVENT0_ISET_SPEC , 5 > { INT_EVENT0_ISET_RXNE_W :: new (self) } # [doc ...
[INFO] [stdout]   |                   ^^^^^^^^^^     ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here
[INFO] [stdout]   |                   |
[INFO] [stdout]   |                   the lifetime is elided here
[INFO] [stdout]   |
[INFO] [stdout]   = help: the same lifetime is referred to in inconsistent ways, making the signature confusing
[INFO] [stdout] help: use `'_` for type paths
[INFO] [stdout]   |
[INFO] [stdout] 1 | # [doc = "Register `INT_EVENT0_ISET` writer"] pub type W = crate :: W < INT_EVENT0_ISET_SPEC > ; # [doc = "Set UARTOUT Receive Time-Out Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_RTOUT_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_RTOUT_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_RTOUT_SET = 1 , } impl From < INT_EVENT0_ISET_RTOUT_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_RTOUT_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_RTOUT` writer - Set UARTOUT Receive Time-Out Interrupt."] pub type INT_EVENT0_ISET_RTOUT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_RTOUT_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_RTOUT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_rtout_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_RTOUT_AW :: INT_EVENT0_ISET_RTOUT_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_rtout_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_RTOUT_AW :: INT_EVENT0_ISET_RTOUT_SET) } } # [doc = "Set UART Framing Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_FRMERR_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_FRMERR_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_FRMERR_SET = 1 , } impl From < INT_EVENT0_ISET_FRMERR_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_FRMERR_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_FRMERR` writer - Set UART Framing Error Interrupt."] pub type INT_EVENT0_ISET_FRMERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_FRMERR_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_FRMERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_frmerr_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_FRMERR_AW :: INT_EVENT0_ISET_FRMERR_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_frmerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_FRMERR_AW :: INT_EVENT0_ISET_FRMERR_SET) } } # [doc = "Set UART Parity Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_PARERR_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_PARERR_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_PARERR_SET = 1 , } impl From < INT_EVENT0_ISET_PARERR_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_PARERR_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_PARERR` writer - Set UART Parity Error Interrupt."] pub type INT_EVENT0_ISET_PARERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_PARERR_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_PARERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_parerr_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_PARERR_AW :: INT_EVENT0_ISET_PARERR_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_parerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_PARERR_AW :: INT_EVENT0_ISET_PARERR_SET) } } # [doc = "Set UART Break Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_BRKERR_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_BRKERR_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_BRKERR_SET = 1 , } impl From < INT_EVENT0_ISET_BRKERR_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_BRKERR_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_BRKERR` writer - Set UART Break Error Interrupt."] pub type INT_EVENT0_ISET_BRKERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_BRKERR_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_BRKERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_brkerr_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_BRKERR_AW :: INT_EVENT0_ISET_BRKERR_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_brkerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_BRKERR_AW :: INT_EVENT0_ISET_BRKERR_SET) } } # [doc = "Set UART Receive Overrun Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_OVRERR_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_OVRERR_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_OVRERR_SET = 1 , } impl From < INT_EVENT0_ISET_OVRERR_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_OVRERR_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_OVRERR` writer - Set UART Receive Overrun Error Interrupt."] pub type INT_EVENT0_ISET_OVRERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_OVRERR_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_OVRERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_ovrerr_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_OVRERR_AW :: INT_EVENT0_ISET_OVRERR_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_ovrerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_OVRERR_AW :: INT_EVENT0_ISET_OVRERR_SET) } } # [doc = "Set Negative Edge on UARTxRXD Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_RXNE_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_RXNE_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_RXNE_SET = 1 , } impl From < INT_EVENT0_ISET_RXNE_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_RXNE_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_RXNE` writer - Set Negative Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_ISET_RXNE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_RXNE_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_RXNE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_rxne_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_RXNE_AW :: INT_EVENT0_ISET_RXNE_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_rxne_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_RXNE_AW :: INT_EVENT0_ISET_RXNE_SET) } } # [doc = "Set Positive Edge on UARTxRXD Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_RXPE_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_RXPE_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_RXPE_SET = 1 , } impl From < INT_EVENT0_ISET_RXPE_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_RXPE_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_RXPE` writer - Set Positive Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_ISET_RXPE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_RXPE_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_RXPE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_rxpe_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_RXPE_AW :: INT_EVENT0_ISET_RXPE_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_rxpe_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_RXPE_AW :: INT_EVENT0_ISET_RXPE_SET) } } # [doc = "Set LIN Capture 0 / Match Interrupt .\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_LINC0_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_LINC0_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_LINC0_SET = 1 , } impl From < INT_EVENT0_ISET_LINC0_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_LINC0_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_LINC0` writer - Set LIN Capture 0 / Match Interrupt ."] pub type INT_EVENT0_ISET_LINC0_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_LINC0_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_LINC0_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_linc0_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_LINC0_AW :: INT_EVENT0_ISET_LINC0_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_linc0_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_LINC0_AW :: INT_EVENT0_ISET_LINC0_SET) } } # [doc = "Set LIN Capture 1 Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_LINC1_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_LINC1_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_LINC1_SET = 1 , } impl From < INT_EVENT0_ISET_LINC1_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_LINC1_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_LINC1` writer - Set LIN Capture 1 Interrupt."] pub type INT_EVENT0_ISET_LINC1_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_LINC1_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_LINC1_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_linc1_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_LINC1_AW :: INT_EVENT0_ISET_LINC1_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_linc1_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_LINC1_AW :: INT_EVENT0_ISET_LINC1_SET) } } # [doc = "Set LIN Hardware Counter Overflow Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_LINOVF_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_LINOVF_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_LINOVF_SET = 1 , } impl From < INT_EVENT0_ISET_LINOVF_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_LINOVF_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_LINOVF` writer - Set LIN Hardware Counter Overflow Interrupt."] pub type INT_EVENT0_ISET_LINOVF_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_LINOVF_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_LINOVF_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_linovf_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_LINOVF_AW :: INT_EVENT0_ISET_LINOVF_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_linovf_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_LINOVF_AW :: INT_EVENT0_ISET_LINOVF_SET) } } # [doc = "Set UART Receive Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_RXINT_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_RXINT_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_RXINT_SET = 1 , } impl From < INT_EVENT0_ISET_RXINT_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_RXINT_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_RXINT` writer - Set UART Receive Interrupt."] pub type INT_EVENT0_ISET_RXINT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_RXINT_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_RXINT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_rxint_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_RXINT_AW :: INT_EVENT0_ISET_RXINT_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_rxint_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_RXINT_AW :: INT_EVENT0_ISET_RXINT_SET) } } # [doc = "Set UART Transmit Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_TXINT_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_TXINT_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_TXINT_SET = 1 , } impl From < INT_EVENT0_ISET_TXINT_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_TXINT_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_TXINT` writer - Set UART Transmit Interrupt."] pub type INT_EVENT0_ISET_TXINT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_TXINT_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_TXINT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_txint_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_TXINT_AW :: INT_EVENT0_ISET_TXINT_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_txint_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_TXINT_AW :: INT_EVENT0_ISET_TXINT_SET) } } # [doc = "Set UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_EOT_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_EOT_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_EOT_SET = 1 , } impl From < INT_EVENT0_ISET_EOT_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_EOT_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_EOT` writer - Set UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] pub type INT_EVENT0_ISET_EOT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_EOT_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_EOT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_eot_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_EOT_AW :: INT_EVENT0_ISET_EOT_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_eot_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_EOT_AW :: INT_EVENT0_ISET_EOT_SET) } } # [doc = "Set Address Match Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_ADDR_MATCH_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_ADDR_MATCH_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_ADDR_MATCH_SET = 1 , } impl From < INT_EVENT0_ISET_ADDR_MATCH_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_ADDR_MATCH_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_ADDR_MATCH` writer - Set Address Match Interrupt."] pub type INT_EVENT0_ISET_ADDR_MATCH_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_ADDR_MATCH_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_ADDR_MATCH_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_addr_match_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_ADDR_MATCH_AW :: INT_EVENT0_ISET_ADDR_MATCH_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_addr_match_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_ADDR_MATCH_AW :: INT_EVENT0_ISET_ADDR_MATCH_SET) } } # [doc = "Set UART Clear to Send Modem Interrupt. 0 = Interrupt disabled\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_CTS_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_CTS_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_CTS_SET = 1 , } impl From < INT_EVENT0_ISET_CTS_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_CTS_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_CTS` writer - Set UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] pub type INT_EVENT0_ISET_CTS_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_CTS_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_CTS_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_cts_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_CTS_AW :: INT_EVENT0_ISET_CTS_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_cts_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_CTS_AW :: INT_EVENT0_ISET_CTS_SET) } } # [doc = "Set DMA Done on RX Event Channel\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_DMA_DONE_RX_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_DMA_DONE_RX_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_DMA_DONE_RX_SET = 1 , } impl From < INT_EVENT0_ISET_DMA_DONE_RX_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_DMA_DONE_RX_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_DMA_DONE_RX` writer - Set DMA Done on RX Event Channel"] pub type INT_EVENT0_ISET_DMA_DONE_RX_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_DMA_DONE_RX_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_DMA_DONE_RX_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_dma_done_rx_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_DMA_DONE_RX_AW :: INT_EVENT0_ISET_DMA_DONE_RX_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_dma_done_rx_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_DMA_DONE_RX_AW :: INT_EVENT0_ISET_DMA_DONE_RX_SET) } } # [doc = "Set DMA Done on TX Event Channel\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_DMA_DONE_TX_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_DMA_DONE_TX_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_DMA_DONE_TX_SET = 1 , } impl From < INT_EVENT0_ISET_DMA_DONE_TX_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_DMA_DONE_TX_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_DMA_DONE_TX` writer - Set DMA Done on TX Event Channel"] pub type INT_EVENT0_ISET_DMA_DONE_TX_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_DMA_DONE_TX_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_DMA_DONE_TX_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_dma_done_tx_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_DMA_DONE_TX_AW :: INT_EVENT0_ISET_DMA_DONE_TX_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_dma_done_tx_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_DMA_DONE_TX_AW :: INT_EVENT0_ISET_DMA_DONE_TX_SET) } } # [doc = "Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_NERR_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_NERR_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_NERR_SET = 1 , } impl From < INT_EVENT0_ISET_NERR_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_NERR_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_NERR` writer - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] pub type INT_EVENT0_ISET_NERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_NERR_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_NERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_nerr_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_NERR_AW :: INT_EVENT0_ISET_NERR_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_nerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_NERR_AW :: INT_EVENT0_ISET_NERR_SET) } } impl W { # [doc = "Bit 0 - Set UARTOUT Receive Time-Out Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iset_rtout (& mut self) -> INT_EVENT0_ISET_RTOUT_W < INT_EVENT0_ISET_SPEC , 0 > { INT_EVENT0_ISET_RTOUT_W :: new (self) } # [doc = "Bit 1 - Set UART Framing Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iset_frmerr (& mut self) -> INT_EVENT0_ISET_FRMERR_W < INT_EVENT0_ISET_SPEC , 1 > { INT_EVENT0_ISET_FRMERR_W :: new (self) } # [doc = "Bit 2 - Set UART Parity Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iset_parerr (& mut self) -> INT_EVENT0_ISET_PARERR_W < INT_EVENT0_ISET_SPEC , 2 > { INT_EVENT0_ISET_PARERR_W :: new (self) } # [doc = "Bit 3 - Set UART Break Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iset_brkerr (& mut self) -> INT_EVENT0_ISET_BRKERR_W < INT_EVENT0_ISET_SPEC , 3 > { INT_EVENT0_ISET_BRKERR_W :: new (self) } # [doc = "Bit 4 - Set UART Receive Overrun Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iset_ovrerr (& mut self) -> INT_EVENT0_ISET_OVRERR_W < INT_EVENT0_ISET_SPEC , 4 > { INT_EVENT0_ISET_OVRERR_W :: new (self) } # [doc = "Bit 5 - Set Negative Edge on UARTxRXD Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iset_rxne (& mut self) -> INT_EVENT0_ISET_RXNE_W <'_,  INT_EVENT0_ISET_SPEC , 5 > { INT_EVENT0_ISET_RXNE_W :: new (self) } # [doc = "Bit 6 - Set Positive Edge on UARTxRXD Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iset_rxpe (& mut self) -> INT_EVENT0_ISET_RXPE_W < INT_EVENT0_ISET_SPEC , 6 > { INT_EVENT0_ISET_RXPE_W :: new (self) } # [doc = "Bit 7 - Set LIN Capture 0 / Match Interrupt ."] # [inline (always)] # [must_use] pub fn int_event0_iset_linc0 (& mut self) -> INT_EVENT0_ISET_LINC0_W < INT_EVENT0_ISET_SPEC , 7 > { INT_EVENT0_ISET_LINC0_W :: new (self) } # [doc = "Bit 8 - Set LIN Capture 1 Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iset_linc1 (& mut self) -> INT_EVENT0_ISET_LINC1_W < INT_EVENT0_ISET_SPEC , 8 > { INT_EVENT0_ISET_LINC1_W :: new (self) } # [doc = "Bit 9 - Set LIN Hardware Counter Overflow Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iset_linovf (& mut self) -> INT_EVENT0_ISET_LINOVF_W < INT_EVENT0_ISET_SPEC , 9 > { INT_EVENT0_ISET_LINOVF_W :: new (self) } # [doc = "Bit 10 - Set UART Receive Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iset_rxint (& mut self) -> INT_EVENT0_ISET_RXINT_W < INT_EVENT0_ISET_SPEC , 10 > { INT_EVENT0_ISET_RXINT_W :: new (self) } # [doc = "Bit 11 - Set UART Transmit Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iset_txint (& mut self) -> INT_EVENT0_ISET_TXINT_W < INT_EVENT0_ISET_SPEC , 11 > { INT_EVENT0_ISET_TXINT_W :: new (self) } # [doc = "Bit 12 - Set UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] # [inline (always)] # [must_use] pub fn int_event0_iset_eot (& mut self) -> INT_EVENT0_ISET_EOT_W < INT_EVENT0_ISET_SPEC , 12 > { INT_EVENT0_ISET_EOT_W :: new (self) } # [doc = "Bit 13 - Set Address Match Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iset_addr_match (& mut self) -> INT_EVENT0_ISET_ADDR_MATCH_W < INT_EVENT0_ISET_SPEC , 13 > { INT_EVENT0_ISET_ADDR_MATCH_W :: new (self) } # [doc = "Bit 14 - Set UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] # [inline (always)] # [must_use] pub fn int_event0_iset_cts (& mut self) -> INT_EVENT0_ISET_CTS_W < INT_EVENT0_ISET_SPEC , 14 > { INT_EVENT0_ISET_CTS_W :: new (self) } # [doc = "Bit 15 - Set DMA Done on RX Event Channel"] # [inline (always)] # [must_use] pub fn int_event0_iset_dma_done_rx (& mut self) -> INT_EVENT0_ISET_DMA_DONE_RX_W < INT_EVENT0_ISET_SPEC , 15 > { INT_EVENT0_ISET_DMA_DONE_RX_W :: new (self) } # [doc = "Bit 16 - Set DMA Done on TX Event Channel"] # [inline (always)] # [must_use] pub fn int_event0_iset_dma_done_tx (& mut self) -> INT_EVENT0_ISET_DMA_DONE_TX_W < INT_EVENT0_ISET_SPEC , 16 > { INT_EVENT0_ISET_DMA_DONE_TX_W :: new (self) } # [doc = "Bit 17 - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] # [inline (always)] # [must_use] pub fn int_event0_iset_nerr (& mut self) -> INT_EVENT0_ISET_NERR_W < INT_EVENT0_ISET_SPEC , 17 > { INT_EVENT0_ISET_NERR_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Interrupt set\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_event0_iset::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct INT_EVENT0_ISET_SPEC ; impl crate :: RegisterSpec for INT_EVENT0_ISET_SPEC { type Ux = u32 ; } # [doc = "`write(|w| ..)` method takes [`int_event0_iset::W`](W) writer structure"] impl crate :: Writable for INT_EVENT0_ISET_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets INT_EVENT0_ISET to value 0"] impl crate :: Resettable for INT_EVENT0_ISET_SPEC { const RESET_VALUE : Self :: Ux = 0 ; }
[INFO] [stdout]   |                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                            +++
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing
[INFO] [stdout]  --> src/uart0/int_event0_iset.rs:1:22988
[INFO] [stdout]   |
[INFO] [stdout] 1 | ...nt0_iset_rxpe (& mut self) -> INT_EVENT0_ISET_RXPE_W < INT_EVENT0_ISET_SPEC , 6 > { INT_EVENT0_ISET_RXPE_W :: new (self) } # [doc ...
[INFO] [stdout]   |                   ^^^^^^^^^^     ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here
[INFO] [stdout]   |                   |
[INFO] [stdout]   |                   the lifetime is elided here
[INFO] [stdout]   |
[INFO] [stdout]   = help: the same lifetime is referred to in inconsistent ways, making the signature confusing
[INFO] [stdout] help: use `'_` for type paths
[INFO] [stdout]   |
[INFO] [stdout] 1 | # [doc = "Register `INT_EVENT0_ISET` writer"] pub type W = crate :: W < INT_EVENT0_ISET_SPEC > ; # [doc = "Set UARTOUT Receive Time-Out Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_RTOUT_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_RTOUT_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_RTOUT_SET = 1 , } impl From < INT_EVENT0_ISET_RTOUT_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_RTOUT_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_RTOUT` writer - Set UARTOUT Receive Time-Out Interrupt."] pub type INT_EVENT0_ISET_RTOUT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_RTOUT_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_RTOUT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_rtout_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_RTOUT_AW :: INT_EVENT0_ISET_RTOUT_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_rtout_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_RTOUT_AW :: INT_EVENT0_ISET_RTOUT_SET) } } # [doc = "Set UART Framing Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_FRMERR_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_FRMERR_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_FRMERR_SET = 1 , } impl From < INT_EVENT0_ISET_FRMERR_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_FRMERR_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_FRMERR` writer - Set UART Framing Error Interrupt."] pub type INT_EVENT0_ISET_FRMERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_FRMERR_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_FRMERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_frmerr_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_FRMERR_AW :: INT_EVENT0_ISET_FRMERR_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_frmerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_FRMERR_AW :: INT_EVENT0_ISET_FRMERR_SET) } } # [doc = "Set UART Parity Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_PARERR_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_PARERR_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_PARERR_SET = 1 , } impl From < INT_EVENT0_ISET_PARERR_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_PARERR_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_PARERR` writer - Set UART Parity Error Interrupt."] pub type INT_EVENT0_ISET_PARERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_PARERR_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_PARERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_parerr_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_PARERR_AW :: INT_EVENT0_ISET_PARERR_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_parerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_PARERR_AW :: INT_EVENT0_ISET_PARERR_SET) } } # [doc = "Set UART Break Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_BRKERR_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_BRKERR_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_BRKERR_SET = 1 , } impl From < INT_EVENT0_ISET_BRKERR_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_BRKERR_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_BRKERR` writer - Set UART Break Error Interrupt."] pub type INT_EVENT0_ISET_BRKERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_BRKERR_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_BRKERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_brkerr_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_BRKERR_AW :: INT_EVENT0_ISET_BRKERR_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_brkerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_BRKERR_AW :: INT_EVENT0_ISET_BRKERR_SET) } } # [doc = "Set UART Receive Overrun Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_OVRERR_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_OVRERR_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_OVRERR_SET = 1 , } impl From < INT_EVENT0_ISET_OVRERR_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_OVRERR_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_OVRERR` writer - Set UART Receive Overrun Error Interrupt."] pub type INT_EVENT0_ISET_OVRERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_OVRERR_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_OVRERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_ovrerr_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_OVRERR_AW :: INT_EVENT0_ISET_OVRERR_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_ovrerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_OVRERR_AW :: INT_EVENT0_ISET_OVRERR_SET) } } # [doc = "Set Negative Edge on UARTxRXD Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_RXNE_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_RXNE_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_RXNE_SET = 1 , } impl From < INT_EVENT0_ISET_RXNE_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_RXNE_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_RXNE` writer - Set Negative Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_ISET_RXNE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_RXNE_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_RXNE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_rxne_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_RXNE_AW :: INT_EVENT0_ISET_RXNE_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_rxne_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_RXNE_AW :: INT_EVENT0_ISET_RXNE_SET) } } # [doc = "Set Positive Edge on UARTxRXD Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_RXPE_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_RXPE_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_RXPE_SET = 1 , } impl From < INT_EVENT0_ISET_RXPE_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_RXPE_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_RXPE` writer - Set Positive Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_ISET_RXPE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_RXPE_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_RXPE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_rxpe_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_RXPE_AW :: INT_EVENT0_ISET_RXPE_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_rxpe_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_RXPE_AW :: INT_EVENT0_ISET_RXPE_SET) } } # [doc = "Set LIN Capture 0 / Match Interrupt .\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_LINC0_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_LINC0_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_LINC0_SET = 1 , } impl From < INT_EVENT0_ISET_LINC0_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_LINC0_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_LINC0` writer - Set LIN Capture 0 / Match Interrupt ."] pub type INT_EVENT0_ISET_LINC0_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_LINC0_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_LINC0_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_linc0_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_LINC0_AW :: INT_EVENT0_ISET_LINC0_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_linc0_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_LINC0_AW :: INT_EVENT0_ISET_LINC0_SET) } } # [doc = "Set LIN Capture 1 Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_LINC1_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_LINC1_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_LINC1_SET = 1 , } impl From < INT_EVENT0_ISET_LINC1_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_LINC1_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_LINC1` writer - Set LIN Capture 1 Interrupt."] pub type INT_EVENT0_ISET_LINC1_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_LINC1_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_LINC1_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_linc1_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_LINC1_AW :: INT_EVENT0_ISET_LINC1_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_linc1_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_LINC1_AW :: INT_EVENT0_ISET_LINC1_SET) } } # [doc = "Set LIN Hardware Counter Overflow Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_LINOVF_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_LINOVF_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_LINOVF_SET = 1 , } impl From < INT_EVENT0_ISET_LINOVF_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_LINOVF_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_LINOVF` writer - Set LIN Hardware Counter Overflow Interrupt."] pub type INT_EVENT0_ISET_LINOVF_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_LINOVF_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_LINOVF_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_linovf_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_LINOVF_AW :: INT_EVENT0_ISET_LINOVF_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_linovf_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_LINOVF_AW :: INT_EVENT0_ISET_LINOVF_SET) } } # [doc = "Set UART Receive Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_RXINT_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_RXINT_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_RXINT_SET = 1 , } impl From < INT_EVENT0_ISET_RXINT_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_RXINT_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_RXINT` writer - Set UART Receive Interrupt."] pub type INT_EVENT0_ISET_RXINT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_RXINT_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_RXINT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_rxint_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_RXINT_AW :: INT_EVENT0_ISET_RXINT_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_rxint_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_RXINT_AW :: INT_EVENT0_ISET_RXINT_SET) } } # [doc = "Set UART Transmit Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_TXINT_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_TXINT_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_TXINT_SET = 1 , } impl From < INT_EVENT0_ISET_TXINT_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_TXINT_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_TXINT` writer - Set UART Transmit Interrupt."] pub type INT_EVENT0_ISET_TXINT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_TXINT_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_TXINT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_txint_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_TXINT_AW :: INT_EVENT0_ISET_TXINT_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_txint_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_TXINT_AW :: INT_EVENT0_ISET_TXINT_SET) } } # [doc = "Set UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_EOT_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_EOT_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_EOT_SET = 1 , } impl From < INT_EVENT0_ISET_EOT_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_EOT_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_EOT` writer - Set UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] pub type INT_EVENT0_ISET_EOT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_EOT_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_EOT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_eot_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_EOT_AW :: INT_EVENT0_ISET_EOT_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_eot_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_EOT_AW :: INT_EVENT0_ISET_EOT_SET) } } # [doc = "Set Address Match Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_ADDR_MATCH_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_ADDR_MATCH_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_ADDR_MATCH_SET = 1 , } impl From < INT_EVENT0_ISET_ADDR_MATCH_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_ADDR_MATCH_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_ADDR_MATCH` writer - Set Address Match Interrupt."] pub type INT_EVENT0_ISET_ADDR_MATCH_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_ADDR_MATCH_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_ADDR_MATCH_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_addr_match_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_ADDR_MATCH_AW :: INT_EVENT0_ISET_ADDR_MATCH_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_addr_match_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_ADDR_MATCH_AW :: INT_EVENT0_ISET_ADDR_MATCH_SET) } } # [doc = "Set UART Clear to Send Modem Interrupt. 0 = Interrupt disabled\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_CTS_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_CTS_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_CTS_SET = 1 , } impl From < INT_EVENT0_ISET_CTS_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_CTS_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_CTS` writer - Set UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] pub type INT_EVENT0_ISET_CTS_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_CTS_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_CTS_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_cts_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_CTS_AW :: INT_EVENT0_ISET_CTS_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_cts_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_CTS_AW :: INT_EVENT0_ISET_CTS_SET) } } # [doc = "Set DMA Done on RX Event Channel\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_DMA_DONE_RX_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_DMA_DONE_RX_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_DMA_DONE_RX_SET = 1 , } impl From < INT_EVENT0_ISET_DMA_DONE_RX_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_DMA_DONE_RX_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_DMA_DONE_RX` writer - Set DMA Done on RX Event Channel"] pub type INT_EVENT0_ISET_DMA_DONE_RX_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_DMA_DONE_RX_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_DMA_DONE_RX_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_dma_done_rx_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_DMA_DONE_RX_AW :: INT_EVENT0_ISET_DMA_DONE_RX_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_dma_done_rx_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_DMA_DONE_RX_AW :: INT_EVENT0_ISET_DMA_DONE_RX_SET) } } # [doc = "Set DMA Done on TX Event Channel\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_DMA_DONE_TX_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_DMA_DONE_TX_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_DMA_DONE_TX_SET = 1 , } impl From < INT_EVENT0_ISET_DMA_DONE_TX_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_DMA_DONE_TX_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_DMA_DONE_TX` writer - Set DMA Done on TX Event Channel"] pub type INT_EVENT0_ISET_DMA_DONE_TX_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_DMA_DONE_TX_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_DMA_DONE_TX_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_dma_done_tx_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_DMA_DONE_TX_AW :: INT_EVENT0_ISET_DMA_DONE_TX_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_dma_done_tx_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_DMA_DONE_TX_AW :: INT_EVENT0_ISET_DMA_DONE_TX_SET) } } # [doc = "Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_NERR_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_NERR_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_NERR_SET = 1 , } impl From < INT_EVENT0_ISET_NERR_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_NERR_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_NERR` writer - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] pub type INT_EVENT0_ISET_NERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_NERR_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_NERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_nerr_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_NERR_AW :: INT_EVENT0_ISET_NERR_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_nerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_NERR_AW :: INT_EVENT0_ISET_NERR_SET) } } impl W { # [doc = "Bit 0 - Set UARTOUT Receive Time-Out Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iset_rtout (& mut self) -> INT_EVENT0_ISET_RTOUT_W < INT_EVENT0_ISET_SPEC , 0 > { INT_EVENT0_ISET_RTOUT_W :: new (self) } # [doc = "Bit 1 - Set UART Framing Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iset_frmerr (& mut self) -> INT_EVENT0_ISET_FRMERR_W < INT_EVENT0_ISET_SPEC , 1 > { INT_EVENT0_ISET_FRMERR_W :: new (self) } # [doc = "Bit 2 - Set UART Parity Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iset_parerr (& mut self) -> INT_EVENT0_ISET_PARERR_W < INT_EVENT0_ISET_SPEC , 2 > { INT_EVENT0_ISET_PARERR_W :: new (self) } # [doc = "Bit 3 - Set UART Break Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iset_brkerr (& mut self) -> INT_EVENT0_ISET_BRKERR_W < INT_EVENT0_ISET_SPEC , 3 > { INT_EVENT0_ISET_BRKERR_W :: new (self) } # [doc = "Bit 4 - Set UART Receive Overrun Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iset_ovrerr (& mut self) -> INT_EVENT0_ISET_OVRERR_W < INT_EVENT0_ISET_SPEC , 4 > { INT_EVENT0_ISET_OVRERR_W :: new (self) } # [doc = "Bit 5 - Set Negative Edge on UARTxRXD Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iset_rxne (& mut self) -> INT_EVENT0_ISET_RXNE_W < INT_EVENT0_ISET_SPEC , 5 > { INT_EVENT0_ISET_RXNE_W :: new (self) } # [doc = "Bit 6 - Set Positive Edge on UARTxRXD Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iset_rxpe (& mut self) -> INT_EVENT0_ISET_RXPE_W <'_,  INT_EVENT0_ISET_SPEC , 6 > { INT_EVENT0_ISET_RXPE_W :: new (self) } # [doc = "Bit 7 - Set LIN Capture 0 / Match Interrupt ."] # [inline (always)] # [must_use] pub fn int_event0_iset_linc0 (& mut self) -> INT_EVENT0_ISET_LINC0_W < INT_EVENT0_ISET_SPEC , 7 > { INT_EVENT0_ISET_LINC0_W :: new (self) } # [doc = "Bit 8 - Set LIN Capture 1 Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iset_linc1 (& mut self) -> INT_EVENT0_ISET_LINC1_W < INT_EVENT0_ISET_SPEC , 8 > { INT_EVENT0_ISET_LINC1_W :: new (self) } # [doc = "Bit 9 - Set LIN Hardware Counter Overflow Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iset_linovf (& mut self) -> INT_EVENT0_ISET_LINOVF_W < INT_EVENT0_ISET_SPEC , 9 > { INT_EVENT0_ISET_LINOVF_W :: new (self) } # [doc = "Bit 10 - Set UART Receive Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iset_rxint (& mut self) -> INT_EVENT0_ISET_RXINT_W < INT_EVENT0_ISET_SPEC , 10 > { INT_EVENT0_ISET_RXINT_W :: new (self) } # [doc = "Bit 11 - Set UART Transmit Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iset_txint (& mut self) -> INT_EVENT0_ISET_TXINT_W < INT_EVENT0_ISET_SPEC , 11 > { INT_EVENT0_ISET_TXINT_W :: new (self) } # [doc = "Bit 12 - Set UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] # [inline (always)] # [must_use] pub fn int_event0_iset_eot (& mut self) -> INT_EVENT0_ISET_EOT_W < INT_EVENT0_ISET_SPEC , 12 > { INT_EVENT0_ISET_EOT_W :: new (self) } # [doc = "Bit 13 - Set Address Match Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iset_addr_match (& mut self) -> INT_EVENT0_ISET_ADDR_MATCH_W < INT_EVENT0_ISET_SPEC , 13 > { INT_EVENT0_ISET_ADDR_MATCH_W :: new (self) } # [doc = "Bit 14 - Set UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] # [inline (always)] # [must_use] pub fn int_event0_iset_cts (& mut self) -> INT_EVENT0_ISET_CTS_W < INT_EVENT0_ISET_SPEC , 14 > { INT_EVENT0_ISET_CTS_W :: new (self) } # [doc = "Bit 15 - Set DMA Done on RX Event Channel"] # [inline (always)] # [must_use] pub fn int_event0_iset_dma_done_rx (& mut self) -> INT_EVENT0_ISET_DMA_DONE_RX_W < INT_EVENT0_ISET_SPEC , 15 > { INT_EVENT0_ISET_DMA_DONE_RX_W :: new (self) } # [doc = "Bit 16 - Set DMA Done on TX Event Channel"] # [inline (always)] # [must_use] pub fn int_event0_iset_dma_done_tx (& mut self) -> INT_EVENT0_ISET_DMA_DONE_TX_W < INT_EVENT0_ISET_SPEC , 16 > { INT_EVENT0_ISET_DMA_DONE_TX_W :: new (self) } # [doc = "Bit 17 - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] # [inline (always)] # [must_use] pub fn int_event0_iset_nerr (& mut self) -> INT_EVENT0_ISET_NERR_W < INT_EVENT0_ISET_SPEC , 17 > { INT_EVENT0_ISET_NERR_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Interrupt set\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_event0_iset::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct INT_EVENT0_ISET_SPEC ; impl crate :: RegisterSpec for INT_EVENT0_ISET_SPEC { type Ux = u32 ; } # [doc = "`write(|w| ..)` method takes [`int_event0_iset::W`](W) writer structure"] impl crate :: Writable for INT_EVENT0_ISET_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets INT_EVENT0_ISET to value 0"] impl crate :: Resettable for INT_EVENT0_ISET_SPEC { const RESET_VALUE : Self :: Ux = 0 ; }
[INFO] [stdout]   |                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                   +++
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing
[INFO] [stdout]  --> src/uart0/int_event0_iset.rs:1:23217
[INFO] [stdout]   |
[INFO] [stdout] 1 | ...t0_iset_linc0 (& mut self) -> INT_EVENT0_ISET_LINC0_W < INT_EVENT0_ISET_SPEC , 7 > { INT_EVENT0_ISET_LINC0_W :: new (self) } # [do...
[INFO] [stdout]   |                   ^^^^^^^^^^     ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here
[INFO] [stdout]   |                   |
[INFO] [stdout]   |                   the lifetime is elided here
[INFO] [stdout]   |
[INFO] [stdout]   = help: the same lifetime is referred to in inconsistent ways, making the signature confusing
[INFO] [stdout] help: use `'_` for type paths
[INFO] [stdout]   |
[INFO] [stdout] 1 | # [doc = "Register `INT_EVENT0_ISET` writer"] pub type W = crate :: W < INT_EVENT0_ISET_SPEC > ; # [doc = "Set UARTOUT Receive Time-Out Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_RTOUT_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_RTOUT_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_RTOUT_SET = 1 , } impl From < INT_EVENT0_ISET_RTOUT_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_RTOUT_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_RTOUT` writer - Set UARTOUT Receive Time-Out Interrupt."] pub type INT_EVENT0_ISET_RTOUT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_RTOUT_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_RTOUT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_rtout_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_RTOUT_AW :: INT_EVENT0_ISET_RTOUT_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_rtout_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_RTOUT_AW :: INT_EVENT0_ISET_RTOUT_SET) } } # [doc = "Set UART Framing Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_FRMERR_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_FRMERR_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_FRMERR_SET = 1 , } impl From < INT_EVENT0_ISET_FRMERR_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_FRMERR_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_FRMERR` writer - Set UART Framing Error Interrupt."] pub type INT_EVENT0_ISET_FRMERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_FRMERR_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_FRMERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_frmerr_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_FRMERR_AW :: INT_EVENT0_ISET_FRMERR_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_frmerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_FRMERR_AW :: INT_EVENT0_ISET_FRMERR_SET) } } # [doc = "Set UART Parity Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_PARERR_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_PARERR_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_PARERR_SET = 1 , } impl From < INT_EVENT0_ISET_PARERR_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_PARERR_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_PARERR` writer - Set UART Parity Error Interrupt."] pub type INT_EVENT0_ISET_PARERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_PARERR_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_PARERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_parerr_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_PARERR_AW :: INT_EVENT0_ISET_PARERR_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_parerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_PARERR_AW :: INT_EVENT0_ISET_PARERR_SET) } } # [doc = "Set UART Break Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_BRKERR_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_BRKERR_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_BRKERR_SET = 1 , } impl From < INT_EVENT0_ISET_BRKERR_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_BRKERR_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_BRKERR` writer - Set UART Break Error Interrupt."] pub type INT_EVENT0_ISET_BRKERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_BRKERR_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_BRKERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_brkerr_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_BRKERR_AW :: INT_EVENT0_ISET_BRKERR_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_brkerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_BRKERR_AW :: INT_EVENT0_ISET_BRKERR_SET) } } # [doc = "Set UART Receive Overrun Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_OVRERR_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_OVRERR_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_OVRERR_SET = 1 , } impl From < INT_EVENT0_ISET_OVRERR_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_OVRERR_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_OVRERR` writer - Set UART Receive Overrun Error Interrupt."] pub type INT_EVENT0_ISET_OVRERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_OVRERR_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_OVRERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_ovrerr_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_OVRERR_AW :: INT_EVENT0_ISET_OVRERR_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_ovrerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_OVRERR_AW :: INT_EVENT0_ISET_OVRERR_SET) } } # [doc = "Set Negative Edge on UARTxRXD Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_RXNE_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_RXNE_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_RXNE_SET = 1 , } impl From < INT_EVENT0_ISET_RXNE_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_RXNE_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_RXNE` writer - Set Negative Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_ISET_RXNE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_RXNE_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_RXNE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_rxne_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_RXNE_AW :: INT_EVENT0_ISET_RXNE_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_rxne_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_RXNE_AW :: INT_EVENT0_ISET_RXNE_SET) } } # [doc = "Set Positive Edge on UARTxRXD Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_RXPE_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_RXPE_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_RXPE_SET = 1 , } impl From < INT_EVENT0_ISET_RXPE_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_RXPE_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_RXPE` writer - Set Positive Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_ISET_RXPE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_RXPE_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_RXPE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_rxpe_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_RXPE_AW :: INT_EVENT0_ISET_RXPE_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_rxpe_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_RXPE_AW :: INT_EVENT0_ISET_RXPE_SET) } } # [doc = "Set LIN Capture 0 / Match Interrupt .\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_LINC0_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_LINC0_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_LINC0_SET = 1 , } impl From < INT_EVENT0_ISET_LINC0_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_LINC0_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_LINC0` writer - Set LIN Capture 0 / Match Interrupt ."] pub type INT_EVENT0_ISET_LINC0_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_LINC0_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_LINC0_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_linc0_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_LINC0_AW :: INT_EVENT0_ISET_LINC0_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_linc0_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_LINC0_AW :: INT_EVENT0_ISET_LINC0_SET) } } # [doc = "Set LIN Capture 1 Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_LINC1_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_LINC1_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_LINC1_SET = 1 , } impl From < INT_EVENT0_ISET_LINC1_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_LINC1_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_LINC1` writer - Set LIN Capture 1 Interrupt."] pub type INT_EVENT0_ISET_LINC1_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_LINC1_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_LINC1_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_linc1_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_LINC1_AW :: INT_EVENT0_ISET_LINC1_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_linc1_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_LINC1_AW :: INT_EVENT0_ISET_LINC1_SET) } } # [doc = "Set LIN Hardware Counter Overflow Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_LINOVF_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_LINOVF_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_LINOVF_SET = 1 , } impl From < INT_EVENT0_ISET_LINOVF_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_LINOVF_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_LINOVF` writer - Set LIN Hardware Counter Overflow Interrupt."] pub type INT_EVENT0_ISET_LINOVF_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_LINOVF_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_LINOVF_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_linovf_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_LINOVF_AW :: INT_EVENT0_ISET_LINOVF_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_linovf_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_LINOVF_AW :: INT_EVENT0_ISET_LINOVF_SET) } } # [doc = "Set UART Receive Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_RXINT_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_RXINT_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_RXINT_SET = 1 , } impl From < INT_EVENT0_ISET_RXINT_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_RXINT_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_RXINT` writer - Set UART Receive Interrupt."] pub type INT_EVENT0_ISET_RXINT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_RXINT_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_RXINT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_rxint_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_RXINT_AW :: INT_EVENT0_ISET_RXINT_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_rxint_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_RXINT_AW :: INT_EVENT0_ISET_RXINT_SET) } } # [doc = "Set UART Transmit Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_TXINT_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_TXINT_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_TXINT_SET = 1 , } impl From < INT_EVENT0_ISET_TXINT_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_TXINT_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_TXINT` writer - Set UART Transmit Interrupt."] pub type INT_EVENT0_ISET_TXINT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_TXINT_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_TXINT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_txint_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_TXINT_AW :: INT_EVENT0_ISET_TXINT_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_txint_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_TXINT_AW :: INT_EVENT0_ISET_TXINT_SET) } } # [doc = "Set UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_EOT_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_EOT_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_EOT_SET = 1 , } impl From < INT_EVENT0_ISET_EOT_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_EOT_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_EOT` writer - Set UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] pub type INT_EVENT0_ISET_EOT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_EOT_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_EOT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_eot_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_EOT_AW :: INT_EVENT0_ISET_EOT_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_eot_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_EOT_AW :: INT_EVENT0_ISET_EOT_SET) } } # [doc = "Set Address Match Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_ADDR_MATCH_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_ADDR_MATCH_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_ADDR_MATCH_SET = 1 , } impl From < INT_EVENT0_ISET_ADDR_MATCH_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_ADDR_MATCH_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_ADDR_MATCH` writer - Set Address Match Interrupt."] pub type INT_EVENT0_ISET_ADDR_MATCH_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_ADDR_MATCH_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_ADDR_MATCH_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_addr_match_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_ADDR_MATCH_AW :: INT_EVENT0_ISET_ADDR_MATCH_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_addr_match_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_ADDR_MATCH_AW :: INT_EVENT0_ISET_ADDR_MATCH_SET) } } # [doc = "Set UART Clear to Send Modem Interrupt. 0 = Interrupt disabled\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_CTS_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_CTS_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_CTS_SET = 1 , } impl From < INT_EVENT0_ISET_CTS_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_CTS_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_CTS` writer - Set UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] pub type INT_EVENT0_ISET_CTS_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_CTS_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_CTS_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_cts_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_CTS_AW :: INT_EVENT0_ISET_CTS_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_cts_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_CTS_AW :: INT_EVENT0_ISET_CTS_SET) } } # [doc = "Set DMA Done on RX Event Channel\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_DMA_DONE_RX_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_DMA_DONE_RX_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_DMA_DONE_RX_SET = 1 , } impl From < INT_EVENT0_ISET_DMA_DONE_RX_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_DMA_DONE_RX_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_DMA_DONE_RX` writer - Set DMA Done on RX Event Channel"] pub type INT_EVENT0_ISET_DMA_DONE_RX_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_DMA_DONE_RX_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_DMA_DONE_RX_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_dma_done_rx_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_DMA_DONE_RX_AW :: INT_EVENT0_ISET_DMA_DONE_RX_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_dma_done_rx_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_DMA_DONE_RX_AW :: INT_EVENT0_ISET_DMA_DONE_RX_SET) } } # [doc = "Set DMA Done on TX Event Channel\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_DMA_DONE_TX_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_DMA_DONE_TX_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_DMA_DONE_TX_SET = 1 , } impl From < INT_EVENT0_ISET_DMA_DONE_TX_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_DMA_DONE_TX_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_DMA_DONE_TX` writer - Set DMA Done on TX Event Channel"] pub type INT_EVENT0_ISET_DMA_DONE_TX_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_DMA_DONE_TX_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_DMA_DONE_TX_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_dma_done_tx_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_DMA_DONE_TX_AW :: INT_EVENT0_ISET_DMA_DONE_TX_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_dma_done_tx_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_DMA_DONE_TX_AW :: INT_EVENT0_ISET_DMA_DONE_TX_SET) } } # [doc = "Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_NERR_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_NERR_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_NERR_SET = 1 , } impl From < INT_EVENT0_ISET_NERR_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_NERR_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_NERR` writer - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] pub type INT_EVENT0_ISET_NERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_NERR_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_NERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_nerr_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_NERR_AW :: INT_EVENT0_ISET_NERR_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_nerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_NERR_AW :: INT_EVENT0_ISET_NERR_SET) } } impl W { # [doc = "Bit 0 - Set UARTOUT Receive Time-Out Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iset_rtout (& mut self) -> INT_EVENT0_ISET_RTOUT_W < INT_EVENT0_ISET_SPEC , 0 > { INT_EVENT0_ISET_RTOUT_W :: new (self) } # [doc = "Bit 1 - Set UART Framing Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iset_frmerr (& mut self) -> INT_EVENT0_ISET_FRMERR_W < INT_EVENT0_ISET_SPEC , 1 > { INT_EVENT0_ISET_FRMERR_W :: new (self) } # [doc = "Bit 2 - Set UART Parity Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iset_parerr (& mut self) -> INT_EVENT0_ISET_PARERR_W < INT_EVENT0_ISET_SPEC , 2 > { INT_EVENT0_ISET_PARERR_W :: new (self) } # [doc = "Bit 3 - Set UART Break Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iset_brkerr (& mut self) -> INT_EVENT0_ISET_BRKERR_W < INT_EVENT0_ISET_SPEC , 3 > { INT_EVENT0_ISET_BRKERR_W :: new (self) } # [doc = "Bit 4 - Set UART Receive Overrun Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iset_ovrerr (& mut self) -> INT_EVENT0_ISET_OVRERR_W < INT_EVENT0_ISET_SPEC , 4 > { INT_EVENT0_ISET_OVRERR_W :: new (self) } # [doc = "Bit 5 - Set Negative Edge on UARTxRXD Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iset_rxne (& mut self) -> INT_EVENT0_ISET_RXNE_W < INT_EVENT0_ISET_SPEC , 5 > { INT_EVENT0_ISET_RXNE_W :: new (self) } # [doc = "Bit 6 - Set Positive Edge on UARTxRXD Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iset_rxpe (& mut self) -> INT_EVENT0_ISET_RXPE_W < INT_EVENT0_ISET_SPEC , 6 > { INT_EVENT0_ISET_RXPE_W :: new (self) } # [doc = "Bit 7 - Set LIN Capture 0 / Match Interrupt ."] # [inline (always)] # [must_use] pub fn int_event0_iset_linc0 (& mut self) -> INT_EVENT0_ISET_LINC0_W <'_,  INT_EVENT0_ISET_SPEC , 7 > { INT_EVENT0_ISET_LINC0_W :: new (self) } # [doc = "Bit 8 - Set LIN Capture 1 Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iset_linc1 (& mut self) -> INT_EVENT0_ISET_LINC1_W < INT_EVENT0_ISET_SPEC , 8 > { INT_EVENT0_ISET_LINC1_W :: new (self) } # [doc = "Bit 9 - Set LIN Hardware Counter Overflow Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iset_linovf (& mut self) -> INT_EVENT0_ISET_LINOVF_W < INT_EVENT0_ISET_SPEC , 9 > { INT_EVENT0_ISET_LINOVF_W :: new (self) } # [doc = "Bit 10 - Set UART Receive Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iset_rxint (& mut self) -> INT_EVENT0_ISET_RXINT_W < INT_EVENT0_ISET_SPEC , 10 > { INT_EVENT0_ISET_RXINT_W :: new (self) } # [doc = "Bit 11 - Set UART Transmit Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iset_txint (& mut self) -> INT_EVENT0_ISET_TXINT_W < INT_EVENT0_ISET_SPEC , 11 > { INT_EVENT0_ISET_TXINT_W :: new (self) } # [doc = "Bit 12 - Set UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] # [inline (always)] # [must_use] pub fn int_event0_iset_eot (& mut self) -> INT_EVENT0_ISET_EOT_W < INT_EVENT0_ISET_SPEC , 12 > { INT_EVENT0_ISET_EOT_W :: new (self) } # [doc = "Bit 13 - Set Address Match Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iset_addr_match (& mut self) -> INT_EVENT0_ISET_ADDR_MATCH_W < INT_EVENT0_ISET_SPEC , 13 > { INT_EVENT0_ISET_ADDR_MATCH_W :: new (self) } # [doc = "Bit 14 - Set UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] # [inline (always)] # [must_use] pub fn int_event0_iset_cts (& mut self) -> INT_EVENT0_ISET_CTS_W < INT_EVENT0_ISET_SPEC , 14 > { INT_EVENT0_ISET_CTS_W :: new (self) } # [doc = "Bit 15 - Set DMA Done on RX Event Channel"] # [inline (always)] # [must_use] pub fn int_event0_iset_dma_done_rx (& mut self) -> INT_EVENT0_ISET_DMA_DONE_RX_W < INT_EVENT0_ISET_SPEC , 15 > { INT_EVENT0_ISET_DMA_DONE_RX_W :: new (self) } # [doc = "Bit 16 - Set DMA Done on TX Event Channel"] # [inline (always)] # [must_use] pub fn int_event0_iset_dma_done_tx (& mut self) -> INT_EVENT0_ISET_DMA_DONE_TX_W < INT_EVENT0_ISET_SPEC , 16 > { INT_EVENT0_ISET_DMA_DONE_TX_W :: new (self) } # [doc = "Bit 17 - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] # [inline (always)] # [must_use] pub fn int_event0_iset_nerr (& mut self) -> INT_EVENT0_ISET_NERR_W < INT_EVENT0_ISET_SPEC , 17 > { INT_EVENT0_ISET_NERR_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Interrupt set\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_event0_iset::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct INT_EVENT0_ISET_SPEC ; impl crate :: RegisterSpec for INT_EVENT0_ISET_SPEC { type Ux = u32 ; } # [doc = "`write(|w| ..)` method takes [`int_event0_iset::W`](W) writer structure"] impl crate :: Writable for INT_EVENT0_ISET_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets INT_EVENT0_ISET to value 0"] impl crate :: Resettable for INT_EVENT0_ISET_SPEC { const RESET_VALUE : Self :: Ux = 0 ; }
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                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                          +++
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing
[INFO] [stdout]  --> src/uart0/int_event0_iset.rs:1:23439
[INFO] [stdout]   |
[INFO] [stdout] 1 | ...t0_iset_linc1 (& mut self) -> INT_EVENT0_ISET_LINC1_W < INT_EVENT0_ISET_SPEC , 8 > { INT_EVENT0_ISET_LINC1_W :: new (self) } # [do...
[INFO] [stdout]   |                   ^^^^^^^^^^     ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here
[INFO] [stdout]   |                   |
[INFO] [stdout]   |                   the lifetime is elided here
[INFO] [stdout]   |
[INFO] [stdout]   = help: the same lifetime is referred to in inconsistent ways, making the signature confusing
[INFO] [stdout] help: use `'_` for type paths
[INFO] [stdout]   |
[INFO] [stdout] 1 | # [doc = "Register `INT_EVENT0_ISET` writer"] pub type W = crate :: W < INT_EVENT0_ISET_SPEC > ; # [doc = "Set UARTOUT Receive Time-Out Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_RTOUT_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_RTOUT_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_RTOUT_SET = 1 , } impl From < INT_EVENT0_ISET_RTOUT_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_RTOUT_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_RTOUT` writer - Set UARTOUT Receive Time-Out Interrupt."] pub type INT_EVENT0_ISET_RTOUT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_RTOUT_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_RTOUT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_rtout_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_RTOUT_AW :: INT_EVENT0_ISET_RTOUT_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_rtout_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_RTOUT_AW :: INT_EVENT0_ISET_RTOUT_SET) } } # [doc = "Set UART Framing Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_FRMERR_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_FRMERR_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_FRMERR_SET = 1 , } impl From < INT_EVENT0_ISET_FRMERR_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_FRMERR_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_FRMERR` writer - Set UART Framing Error Interrupt."] pub type INT_EVENT0_ISET_FRMERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_FRMERR_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_FRMERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_frmerr_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_FRMERR_AW :: INT_EVENT0_ISET_FRMERR_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_frmerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_FRMERR_AW :: INT_EVENT0_ISET_FRMERR_SET) } } # [doc = "Set UART Parity Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_PARERR_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_PARERR_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_PARERR_SET = 1 , } impl From < INT_EVENT0_ISET_PARERR_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_PARERR_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_PARERR` writer - Set UART Parity Error Interrupt."] pub type INT_EVENT0_ISET_PARERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_PARERR_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_PARERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_parerr_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_PARERR_AW :: INT_EVENT0_ISET_PARERR_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_parerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_PARERR_AW :: INT_EVENT0_ISET_PARERR_SET) } } # [doc = "Set UART Break Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_BRKERR_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_BRKERR_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_BRKERR_SET = 1 , } impl From < INT_EVENT0_ISET_BRKERR_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_BRKERR_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_BRKERR` writer - Set UART Break Error Interrupt."] pub type INT_EVENT0_ISET_BRKERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_BRKERR_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_BRKERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_brkerr_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_BRKERR_AW :: INT_EVENT0_ISET_BRKERR_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_brkerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_BRKERR_AW :: INT_EVENT0_ISET_BRKERR_SET) } } # [doc = "Set UART Receive Overrun Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_OVRERR_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_OVRERR_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_OVRERR_SET = 1 , } impl From < INT_EVENT0_ISET_OVRERR_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_OVRERR_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_OVRERR` writer - Set UART Receive Overrun Error Interrupt."] pub type INT_EVENT0_ISET_OVRERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_OVRERR_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_OVRERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_ovrerr_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_OVRERR_AW :: INT_EVENT0_ISET_OVRERR_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_ovrerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_OVRERR_AW :: INT_EVENT0_ISET_OVRERR_SET) } } # [doc = "Set Negative Edge on UARTxRXD Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_RXNE_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_RXNE_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_RXNE_SET = 1 , } impl From < INT_EVENT0_ISET_RXNE_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_RXNE_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_RXNE` writer - Set Negative Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_ISET_RXNE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_RXNE_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_RXNE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_rxne_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_RXNE_AW :: INT_EVENT0_ISET_RXNE_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_rxne_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_RXNE_AW :: INT_EVENT0_ISET_RXNE_SET) } } # [doc = "Set Positive Edge on UARTxRXD Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_RXPE_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_RXPE_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_RXPE_SET = 1 , } impl From < INT_EVENT0_ISET_RXPE_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_RXPE_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_RXPE` writer - Set Positive Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_ISET_RXPE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_RXPE_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_RXPE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_rxpe_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_RXPE_AW :: INT_EVENT0_ISET_RXPE_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_rxpe_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_RXPE_AW :: INT_EVENT0_ISET_RXPE_SET) } } # [doc = "Set LIN Capture 0 / Match Interrupt .\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_LINC0_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_LINC0_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_LINC0_SET = 1 , } impl From < INT_EVENT0_ISET_LINC0_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_LINC0_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_LINC0` writer - Set LIN Capture 0 / Match Interrupt ."] pub type INT_EVENT0_ISET_LINC0_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_LINC0_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_LINC0_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_linc0_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_LINC0_AW :: INT_EVENT0_ISET_LINC0_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_linc0_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_LINC0_AW :: INT_EVENT0_ISET_LINC0_SET) } } # [doc = "Set LIN Capture 1 Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_LINC1_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_LINC1_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_LINC1_SET = 1 , } impl From < INT_EVENT0_ISET_LINC1_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_LINC1_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_LINC1` writer - Set LIN Capture 1 Interrupt."] pub type INT_EVENT0_ISET_LINC1_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_LINC1_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_LINC1_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_linc1_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_LINC1_AW :: INT_EVENT0_ISET_LINC1_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_linc1_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_LINC1_AW :: INT_EVENT0_ISET_LINC1_SET) } } # [doc = "Set LIN Hardware Counter Overflow Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_LINOVF_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_LINOVF_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_LINOVF_SET = 1 , } impl From < INT_EVENT0_ISET_LINOVF_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_LINOVF_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_LINOVF` writer - Set LIN Hardware Counter Overflow Interrupt."] pub type INT_EVENT0_ISET_LINOVF_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_LINOVF_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_LINOVF_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_linovf_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_LINOVF_AW :: INT_EVENT0_ISET_LINOVF_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_linovf_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_LINOVF_AW :: INT_EVENT0_ISET_LINOVF_SET) } } # [doc = "Set UART Receive Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_RXINT_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_RXINT_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_RXINT_SET = 1 , } impl From < INT_EVENT0_ISET_RXINT_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_RXINT_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_RXINT` writer - Set UART Receive Interrupt."] pub type INT_EVENT0_ISET_RXINT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_RXINT_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_RXINT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_rxint_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_RXINT_AW :: INT_EVENT0_ISET_RXINT_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_rxint_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_RXINT_AW :: INT_EVENT0_ISET_RXINT_SET) } } # [doc = "Set UART Transmit Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_TXINT_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_TXINT_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_TXINT_SET = 1 , } impl From < INT_EVENT0_ISET_TXINT_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_TXINT_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_TXINT` writer - Set UART Transmit Interrupt."] pub type INT_EVENT0_ISET_TXINT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_TXINT_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_TXINT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_txint_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_TXINT_AW :: INT_EVENT0_ISET_TXINT_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_txint_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_TXINT_AW :: INT_EVENT0_ISET_TXINT_SET) } } # [doc = "Set UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_EOT_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_EOT_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_EOT_SET = 1 , } impl From < INT_EVENT0_ISET_EOT_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_EOT_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_EOT` writer - Set UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] pub type INT_EVENT0_ISET_EOT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_EOT_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_EOT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_eot_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_EOT_AW :: INT_EVENT0_ISET_EOT_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_eot_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_EOT_AW :: INT_EVENT0_ISET_EOT_SET) } } # [doc = "Set Address Match Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_ADDR_MATCH_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_ADDR_MATCH_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_ADDR_MATCH_SET = 1 , } impl From < INT_EVENT0_ISET_ADDR_MATCH_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_ADDR_MATCH_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_ADDR_MATCH` writer - Set Address Match Interrupt."] pub type INT_EVENT0_ISET_ADDR_MATCH_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_ADDR_MATCH_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_ADDR_MATCH_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_addr_match_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_ADDR_MATCH_AW :: INT_EVENT0_ISET_ADDR_MATCH_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_addr_match_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_ADDR_MATCH_AW :: INT_EVENT0_ISET_ADDR_MATCH_SET) } } # [doc = "Set UART Clear to Send Modem Interrupt. 0 = Interrupt disabled\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_CTS_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_CTS_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_CTS_SET = 1 , } impl From < INT_EVENT0_ISET_CTS_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_CTS_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_CTS` writer - Set UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] pub type INT_EVENT0_ISET_CTS_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_CTS_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_CTS_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_cts_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_CTS_AW :: INT_EVENT0_ISET_CTS_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_cts_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_CTS_AW :: INT_EVENT0_ISET_CTS_SET) } } # [doc = "Set DMA Done on RX Event Channel\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_DMA_DONE_RX_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_DMA_DONE_RX_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_DMA_DONE_RX_SET = 1 , } impl From < INT_EVENT0_ISET_DMA_DONE_RX_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_DMA_DONE_RX_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_DMA_DONE_RX` writer - Set DMA Done on RX Event Channel"] pub type INT_EVENT0_ISET_DMA_DONE_RX_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_DMA_DONE_RX_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_DMA_DONE_RX_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_dma_done_rx_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_DMA_DONE_RX_AW :: INT_EVENT0_ISET_DMA_DONE_RX_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_dma_done_rx_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_DMA_DONE_RX_AW :: INT_EVENT0_ISET_DMA_DONE_RX_SET) } } # [doc = "Set DMA Done on TX Event Channel\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_DMA_DONE_TX_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_DMA_DONE_TX_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_DMA_DONE_TX_SET = 1 , } impl From < INT_EVENT0_ISET_DMA_DONE_TX_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_DMA_DONE_TX_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_DMA_DONE_TX` writer - Set DMA Done on TX Event Channel"] pub type INT_EVENT0_ISET_DMA_DONE_TX_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_DMA_DONE_TX_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_DMA_DONE_TX_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_dma_done_tx_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_DMA_DONE_TX_AW :: INT_EVENT0_ISET_DMA_DONE_TX_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_dma_done_tx_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_DMA_DONE_TX_AW :: INT_EVENT0_ISET_DMA_DONE_TX_SET) } } # [doc = "Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_NERR_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_NERR_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_NERR_SET = 1 , } impl From < INT_EVENT0_ISET_NERR_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_NERR_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_NERR` writer - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] pub type INT_EVENT0_ISET_NERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_NERR_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_NERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_nerr_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_NERR_AW :: INT_EVENT0_ISET_NERR_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_nerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_NERR_AW :: INT_EVENT0_ISET_NERR_SET) } } impl W { # [doc = "Bit 0 - Set UARTOUT Receive Time-Out Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iset_rtout (& mut self) -> INT_EVENT0_ISET_RTOUT_W < INT_EVENT0_ISET_SPEC , 0 > { INT_EVENT0_ISET_RTOUT_W :: new (self) } # [doc = "Bit 1 - Set UART Framing Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iset_frmerr (& mut self) -> INT_EVENT0_ISET_FRMERR_W < INT_EVENT0_ISET_SPEC , 1 > { INT_EVENT0_ISET_FRMERR_W :: new (self) } # [doc = "Bit 2 - Set UART Parity Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iset_parerr (& mut self) -> INT_EVENT0_ISET_PARERR_W < INT_EVENT0_ISET_SPEC , 2 > { INT_EVENT0_ISET_PARERR_W :: new (self) } # [doc = "Bit 3 - Set UART Break Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iset_brkerr (& mut self) -> INT_EVENT0_ISET_BRKERR_W < INT_EVENT0_ISET_SPEC , 3 > { INT_EVENT0_ISET_BRKERR_W :: new (self) } # [doc = "Bit 4 - Set UART Receive Overrun Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iset_ovrerr (& mut self) -> INT_EVENT0_ISET_OVRERR_W < INT_EVENT0_ISET_SPEC , 4 > { INT_EVENT0_ISET_OVRERR_W :: new (self) } # [doc = "Bit 5 - Set Negative Edge on UARTxRXD Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iset_rxne (& mut self) -> INT_EVENT0_ISET_RXNE_W < INT_EVENT0_ISET_SPEC , 5 > { INT_EVENT0_ISET_RXNE_W :: new (self) } # [doc = "Bit 6 - Set Positive Edge on UARTxRXD Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iset_rxpe (& mut self) -> INT_EVENT0_ISET_RXPE_W < INT_EVENT0_ISET_SPEC , 6 > { INT_EVENT0_ISET_RXPE_W :: new (self) } # [doc = "Bit 7 - Set LIN Capture 0 / Match Interrupt ."] # [inline (always)] # [must_use] pub fn int_event0_iset_linc0 (& mut self) -> INT_EVENT0_ISET_LINC0_W < INT_EVENT0_ISET_SPEC , 7 > { INT_EVENT0_ISET_LINC0_W :: new (self) } # [doc = "Bit 8 - Set LIN Capture 1 Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iset_linc1 (& mut self) -> INT_EVENT0_ISET_LINC1_W <'_,  INT_EVENT0_ISET_SPEC , 8 > { INT_EVENT0_ISET_LINC1_W :: new (self) } # [doc = "Bit 9 - Set LIN Hardware Counter Overflow Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iset_linovf (& mut self) -> INT_EVENT0_ISET_LINOVF_W < INT_EVENT0_ISET_SPEC , 9 > { INT_EVENT0_ISET_LINOVF_W :: new (self) } # [doc = "Bit 10 - Set UART Receive Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iset_rxint (& mut self) -> INT_EVENT0_ISET_RXINT_W < INT_EVENT0_ISET_SPEC , 10 > { INT_EVENT0_ISET_RXINT_W :: new (self) } # [doc = "Bit 11 - Set UART Transmit Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iset_txint (& mut self) -> INT_EVENT0_ISET_TXINT_W < INT_EVENT0_ISET_SPEC , 11 > { INT_EVENT0_ISET_TXINT_W :: new (self) } # [doc = "Bit 12 - Set UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] # [inline (always)] # [must_use] pub fn int_event0_iset_eot (& mut self) -> INT_EVENT0_ISET_EOT_W < INT_EVENT0_ISET_SPEC , 12 > { INT_EVENT0_ISET_EOT_W :: new (self) } # [doc = "Bit 13 - Set Address Match Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iset_addr_match (& mut self) -> INT_EVENT0_ISET_ADDR_MATCH_W < INT_EVENT0_ISET_SPEC , 13 > { INT_EVENT0_ISET_ADDR_MATCH_W :: new (self) } # [doc = "Bit 14 - Set UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] # [inline (always)] # [must_use] pub fn int_event0_iset_cts (& mut self) -> INT_EVENT0_ISET_CTS_W < INT_EVENT0_ISET_SPEC , 14 > { INT_EVENT0_ISET_CTS_W :: new (self) } # [doc = "Bit 15 - Set DMA Done on RX Event Channel"] # [inline (always)] # [must_use] pub fn int_event0_iset_dma_done_rx (& mut self) -> INT_EVENT0_ISET_DMA_DONE_RX_W < INT_EVENT0_ISET_SPEC , 15 > { INT_EVENT0_ISET_DMA_DONE_RX_W :: new (self) } # [doc = "Bit 16 - Set DMA Done on TX Event Channel"] # [inline (always)] # [must_use] pub fn int_event0_iset_dma_done_tx (& mut self) -> INT_EVENT0_ISET_DMA_DONE_TX_W < INT_EVENT0_ISET_SPEC , 16 > { INT_EVENT0_ISET_DMA_DONE_TX_W :: new (self) } # [doc = "Bit 17 - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] # [inline (always)] # [must_use] pub fn int_event0_iset_nerr (& mut self) -> INT_EVENT0_ISET_NERR_W < INT_EVENT0_ISET_SPEC , 17 > { INT_EVENT0_ISET_NERR_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Interrupt set\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_event0_iset::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct INT_EVENT0_ISET_SPEC ; impl crate :: RegisterSpec for INT_EVENT0_ISET_SPEC { type Ux = u32 ; } # [doc = "`write(|w| ..)` method takes [`int_event0_iset::W`](W) writer structure"] impl crate :: Writable for INT_EVENT0_ISET_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets INT_EVENT0_ISET to value 0"] impl crate :: Resettable for INT_EVENT0_ISET_SPEC { const RESET_VALUE : Self :: Ux = 0 ; }
[INFO] [stdout]   |                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                       +++
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing
[INFO] [stdout]  --> src/uart0/int_event0_iset.rs:1:23678
[INFO] [stdout]   |
[INFO] [stdout] 1 | ..._iset_linovf (& mut self) -> INT_EVENT0_ISET_LINOVF_W < INT_EVENT0_ISET_SPEC , 9 > { INT_EVENT0_ISET_LINOVF_W :: new (self) } # [d...
[INFO] [stdout]   |                  ^^^^^^^^^^     ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here
[INFO] [stdout]   |                  |
[INFO] [stdout]   |                  the lifetime is elided here
[INFO] [stdout]   |
[INFO] [stdout]   = help: the same lifetime is referred to in inconsistent ways, making the signature confusing
[INFO] [stdout] help: use `'_` for type paths
[INFO] [stdout]   |
[INFO] [stdout] 1 | # [doc = "Register `INT_EVENT0_ISET` writer"] pub type W = crate :: W < INT_EVENT0_ISET_SPEC > ; # [doc = "Set UARTOUT Receive Time-Out Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_RTOUT_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_RTOUT_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_RTOUT_SET = 1 , } impl From < INT_EVENT0_ISET_RTOUT_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_RTOUT_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_RTOUT` writer - Set UARTOUT Receive Time-Out Interrupt."] pub type INT_EVENT0_ISET_RTOUT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_RTOUT_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_RTOUT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_rtout_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_RTOUT_AW :: INT_EVENT0_ISET_RTOUT_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_rtout_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_RTOUT_AW :: INT_EVENT0_ISET_RTOUT_SET) } } # [doc = "Set UART Framing Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_FRMERR_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_FRMERR_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_FRMERR_SET = 1 , } impl From < INT_EVENT0_ISET_FRMERR_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_FRMERR_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_FRMERR` writer - Set UART Framing Error Interrupt."] pub type INT_EVENT0_ISET_FRMERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_FRMERR_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_FRMERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_frmerr_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_FRMERR_AW :: INT_EVENT0_ISET_FRMERR_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_frmerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_FRMERR_AW :: INT_EVENT0_ISET_FRMERR_SET) } } # [doc = "Set UART Parity Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_PARERR_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_PARERR_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_PARERR_SET = 1 , } impl From < INT_EVENT0_ISET_PARERR_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_PARERR_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_PARERR` writer - Set UART Parity Error Interrupt."] pub type INT_EVENT0_ISET_PARERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_PARERR_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_PARERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_parerr_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_PARERR_AW :: INT_EVENT0_ISET_PARERR_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_parerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_PARERR_AW :: INT_EVENT0_ISET_PARERR_SET) } } # [doc = "Set UART Break Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_BRKERR_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_BRKERR_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_BRKERR_SET = 1 , } impl From < INT_EVENT0_ISET_BRKERR_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_BRKERR_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_BRKERR` writer - Set UART Break Error Interrupt."] pub type INT_EVENT0_ISET_BRKERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_BRKERR_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_BRKERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_brkerr_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_BRKERR_AW :: INT_EVENT0_ISET_BRKERR_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_brkerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_BRKERR_AW :: INT_EVENT0_ISET_BRKERR_SET) } } # [doc = "Set UART Receive Overrun Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_OVRERR_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_OVRERR_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_OVRERR_SET = 1 , } impl From < INT_EVENT0_ISET_OVRERR_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_OVRERR_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_OVRERR` writer - Set UART Receive Overrun Error Interrupt."] pub type INT_EVENT0_ISET_OVRERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_OVRERR_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_OVRERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_ovrerr_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_OVRERR_AW :: INT_EVENT0_ISET_OVRERR_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_ovrerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_OVRERR_AW :: INT_EVENT0_ISET_OVRERR_SET) } } # [doc = "Set Negative Edge on UARTxRXD Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_RXNE_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_RXNE_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_RXNE_SET = 1 , } impl From < INT_EVENT0_ISET_RXNE_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_RXNE_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_RXNE` writer - Set Negative Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_ISET_RXNE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_RXNE_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_RXNE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_rxne_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_RXNE_AW :: INT_EVENT0_ISET_RXNE_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_rxne_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_RXNE_AW :: INT_EVENT0_ISET_RXNE_SET) } } # [doc = "Set Positive Edge on UARTxRXD Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_RXPE_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_RXPE_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_RXPE_SET = 1 , } impl From < INT_EVENT0_ISET_RXPE_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_RXPE_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_RXPE` writer - Set Positive Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_ISET_RXPE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_RXPE_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_RXPE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_rxpe_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_RXPE_AW :: INT_EVENT0_ISET_RXPE_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_rxpe_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_RXPE_AW :: INT_EVENT0_ISET_RXPE_SET) } } # [doc = "Set LIN Capture 0 / Match Interrupt .\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_LINC0_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_LINC0_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_LINC0_SET = 1 , } impl From < INT_EVENT0_ISET_LINC0_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_LINC0_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_LINC0` writer - Set LIN Capture 0 / Match Interrupt ."] pub type INT_EVENT0_ISET_LINC0_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_LINC0_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_LINC0_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_linc0_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_LINC0_AW :: INT_EVENT0_ISET_LINC0_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_linc0_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_LINC0_AW :: INT_EVENT0_ISET_LINC0_SET) } } # [doc = "Set LIN Capture 1 Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_LINC1_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_LINC1_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_LINC1_SET = 1 , } impl From < INT_EVENT0_ISET_LINC1_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_LINC1_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_LINC1` writer - Set LIN Capture 1 Interrupt."] pub type INT_EVENT0_ISET_LINC1_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_LINC1_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_LINC1_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_linc1_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_LINC1_AW :: INT_EVENT0_ISET_LINC1_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_linc1_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_LINC1_AW :: INT_EVENT0_ISET_LINC1_SET) } } # [doc = "Set LIN Hardware Counter Overflow Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_LINOVF_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_LINOVF_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_LINOVF_SET = 1 , } impl From < INT_EVENT0_ISET_LINOVF_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_LINOVF_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_LINOVF` writer - Set LIN Hardware Counter Overflow Interrupt."] pub type INT_EVENT0_ISET_LINOVF_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_LINOVF_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_LINOVF_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_linovf_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_LINOVF_AW :: INT_EVENT0_ISET_LINOVF_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_linovf_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_LINOVF_AW :: INT_EVENT0_ISET_LINOVF_SET) } } # [doc = "Set UART Receive Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_RXINT_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_RXINT_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_RXINT_SET = 1 , } impl From < INT_EVENT0_ISET_RXINT_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_RXINT_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_RXINT` writer - Set UART Receive Interrupt."] pub type INT_EVENT0_ISET_RXINT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_RXINT_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_RXINT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_rxint_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_RXINT_AW :: INT_EVENT0_ISET_RXINT_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_rxint_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_RXINT_AW :: INT_EVENT0_ISET_RXINT_SET) } } # [doc = "Set UART Transmit Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_TXINT_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_TXINT_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_TXINT_SET = 1 , } impl From < INT_EVENT0_ISET_TXINT_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_TXINT_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_TXINT` writer - Set UART Transmit Interrupt."] pub type INT_EVENT0_ISET_TXINT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_TXINT_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_TXINT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_txint_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_TXINT_AW :: INT_EVENT0_ISET_TXINT_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_txint_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_TXINT_AW :: INT_EVENT0_ISET_TXINT_SET) } } # [doc = "Set UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_EOT_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_EOT_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_EOT_SET = 1 , } impl From < INT_EVENT0_ISET_EOT_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_EOT_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_EOT` writer - Set UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] pub type INT_EVENT0_ISET_EOT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_EOT_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_EOT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_eot_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_EOT_AW :: INT_EVENT0_ISET_EOT_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_eot_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_EOT_AW :: INT_EVENT0_ISET_EOT_SET) } } # [doc = "Set Address Match Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_ADDR_MATCH_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_ADDR_MATCH_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_ADDR_MATCH_SET = 1 , } impl From < INT_EVENT0_ISET_ADDR_MATCH_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_ADDR_MATCH_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_ADDR_MATCH` writer - Set Address Match Interrupt."] pub type INT_EVENT0_ISET_ADDR_MATCH_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_ADDR_MATCH_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_ADDR_MATCH_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_addr_match_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_ADDR_MATCH_AW :: INT_EVENT0_ISET_ADDR_MATCH_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_addr_match_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_ADDR_MATCH_AW :: INT_EVENT0_ISET_ADDR_MATCH_SET) } } # [doc = "Set UART Clear to Send Modem Interrupt. 0 = Interrupt disabled\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_CTS_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_CTS_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_CTS_SET = 1 , } impl From < INT_EVENT0_ISET_CTS_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_CTS_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_CTS` writer - Set UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] pub type INT_EVENT0_ISET_CTS_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_CTS_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_CTS_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_cts_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_CTS_AW :: INT_EVENT0_ISET_CTS_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_cts_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_CTS_AW :: INT_EVENT0_ISET_CTS_SET) } } # [doc = "Set DMA Done on RX Event Channel\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_DMA_DONE_RX_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_DMA_DONE_RX_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_DMA_DONE_RX_SET = 1 , } impl From < INT_EVENT0_ISET_DMA_DONE_RX_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_DMA_DONE_RX_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_DMA_DONE_RX` writer - Set DMA Done on RX Event Channel"] pub type INT_EVENT0_ISET_DMA_DONE_RX_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_DMA_DONE_RX_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_DMA_DONE_RX_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_dma_done_rx_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_DMA_DONE_RX_AW :: INT_EVENT0_ISET_DMA_DONE_RX_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_dma_done_rx_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_DMA_DONE_RX_AW :: INT_EVENT0_ISET_DMA_DONE_RX_SET) } } # [doc = "Set DMA Done on TX Event Channel\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_DMA_DONE_TX_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_DMA_DONE_TX_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_DMA_DONE_TX_SET = 1 , } impl From < INT_EVENT0_ISET_DMA_DONE_TX_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_DMA_DONE_TX_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_DMA_DONE_TX` writer - Set DMA Done on TX Event Channel"] pub type INT_EVENT0_ISET_DMA_DONE_TX_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_DMA_DONE_TX_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_DMA_DONE_TX_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_dma_done_tx_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_DMA_DONE_TX_AW :: INT_EVENT0_ISET_DMA_DONE_TX_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_dma_done_tx_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_DMA_DONE_TX_AW :: INT_EVENT0_ISET_DMA_DONE_TX_SET) } } # [doc = "Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_NERR_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_NERR_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_NERR_SET = 1 , } impl From < INT_EVENT0_ISET_NERR_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_NERR_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_NERR` writer - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] pub type INT_EVENT0_ISET_NERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_NERR_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_NERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_nerr_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_NERR_AW :: INT_EVENT0_ISET_NERR_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_nerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_NERR_AW :: INT_EVENT0_ISET_NERR_SET) } } impl W { # [doc = "Bit 0 - Set UARTOUT Receive Time-Out Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iset_rtout (& mut self) -> INT_EVENT0_ISET_RTOUT_W < INT_EVENT0_ISET_SPEC , 0 > { INT_EVENT0_ISET_RTOUT_W :: new (self) } # [doc = "Bit 1 - Set UART Framing Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iset_frmerr (& mut self) -> INT_EVENT0_ISET_FRMERR_W < INT_EVENT0_ISET_SPEC , 1 > { INT_EVENT0_ISET_FRMERR_W :: new (self) } # [doc = "Bit 2 - Set UART Parity Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iset_parerr (& mut self) -> INT_EVENT0_ISET_PARERR_W < INT_EVENT0_ISET_SPEC , 2 > { INT_EVENT0_ISET_PARERR_W :: new (self) } # [doc = "Bit 3 - Set UART Break Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iset_brkerr (& mut self) -> INT_EVENT0_ISET_BRKERR_W < INT_EVENT0_ISET_SPEC , 3 > { INT_EVENT0_ISET_BRKERR_W :: new (self) } # [doc = "Bit 4 - Set UART Receive Overrun Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iset_ovrerr (& mut self) -> INT_EVENT0_ISET_OVRERR_W < INT_EVENT0_ISET_SPEC , 4 > { INT_EVENT0_ISET_OVRERR_W :: new (self) } # [doc = "Bit 5 - Set Negative Edge on UARTxRXD Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iset_rxne (& mut self) -> INT_EVENT0_ISET_RXNE_W < INT_EVENT0_ISET_SPEC , 5 > { INT_EVENT0_ISET_RXNE_W :: new (self) } # [doc = "Bit 6 - Set Positive Edge on UARTxRXD Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iset_rxpe (& mut self) -> INT_EVENT0_ISET_RXPE_W < INT_EVENT0_ISET_SPEC , 6 > { INT_EVENT0_ISET_RXPE_W :: new (self) } # [doc = "Bit 7 - Set LIN Capture 0 / Match Interrupt ."] # [inline (always)] # [must_use] pub fn int_event0_iset_linc0 (& mut self) -> INT_EVENT0_ISET_LINC0_W < INT_EVENT0_ISET_SPEC , 7 > { INT_EVENT0_ISET_LINC0_W :: new (self) } # [doc = "Bit 8 - Set LIN Capture 1 Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iset_linc1 (& mut self) -> INT_EVENT0_ISET_LINC1_W < INT_EVENT0_ISET_SPEC , 8 > { INT_EVENT0_ISET_LINC1_W :: new (self) } # [doc = "Bit 9 - Set LIN Hardware Counter Overflow Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iset_linovf (& mut self) -> INT_EVENT0_ISET_LINOVF_W <'_,  INT_EVENT0_ISET_SPEC , 9 > { INT_EVENT0_ISET_LINOVF_W :: new (self) } # [doc = "Bit 10 - Set UART Receive Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iset_rxint (& mut self) -> INT_EVENT0_ISET_RXINT_W < INT_EVENT0_ISET_SPEC , 10 > { INT_EVENT0_ISET_RXINT_W :: new (self) } # [doc = "Bit 11 - Set UART Transmit Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iset_txint (& mut self) -> INT_EVENT0_ISET_TXINT_W < INT_EVENT0_ISET_SPEC , 11 > { INT_EVENT0_ISET_TXINT_W :: new (self) } # [doc = "Bit 12 - Set UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] # [inline (always)] # [must_use] pub fn int_event0_iset_eot (& mut self) -> INT_EVENT0_ISET_EOT_W < INT_EVENT0_ISET_SPEC , 12 > { INT_EVENT0_ISET_EOT_W :: new (self) } # [doc = "Bit 13 - Set Address Match Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iset_addr_match (& mut self) -> INT_EVENT0_ISET_ADDR_MATCH_W < INT_EVENT0_ISET_SPEC , 13 > { INT_EVENT0_ISET_ADDR_MATCH_W :: new (self) } # [doc = "Bit 14 - Set UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] # [inline (always)] # [must_use] pub fn int_event0_iset_cts (& mut self) -> INT_EVENT0_ISET_CTS_W < INT_EVENT0_ISET_SPEC , 14 > { INT_EVENT0_ISET_CTS_W :: new (self) } # [doc = "Bit 15 - Set DMA Done on RX Event Channel"] # [inline (always)] # [must_use] pub fn int_event0_iset_dma_done_rx (& mut self) -> INT_EVENT0_ISET_DMA_DONE_RX_W < INT_EVENT0_ISET_SPEC , 15 > { INT_EVENT0_ISET_DMA_DONE_RX_W :: new (self) } # [doc = "Bit 16 - Set DMA Done on TX Event Channel"] # [inline (always)] # [must_use] pub fn int_event0_iset_dma_done_tx (& mut self) -> INT_EVENT0_ISET_DMA_DONE_TX_W < INT_EVENT0_ISET_SPEC , 16 > { INT_EVENT0_ISET_DMA_DONE_TX_W :: new (self) } # [doc = "Bit 17 - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] # [inline (always)] # [must_use] pub fn int_event0_iset_nerr (& mut self) -> INT_EVENT0_ISET_NERR_W < INT_EVENT0_ISET_SPEC , 17 > { INT_EVENT0_ISET_NERR_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Interrupt set\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_event0_iset::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct INT_EVENT0_ISET_SPEC ; impl crate :: RegisterSpec for INT_EVENT0_ISET_SPEC { type Ux = u32 ; } # [doc = "`write(|w| ..)` method takes [`int_event0_iset::W`](W) writer structure"] impl crate :: Writable for INT_EVENT0_ISET_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets INT_EVENT0_ISET to value 0"] impl crate :: Resettable for INT_EVENT0_ISET_SPEC { const RESET_VALUE : Self :: Ux = 0 ; }
[INFO] [stdout]   |                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                       +++
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing
[INFO] [stdout]  --> src/uart0/int_event0_iset.rs:1:23902
[INFO] [stdout]   |
[INFO] [stdout] 1 | ...0_iset_rxint (& mut self) -> INT_EVENT0_ISET_RXINT_W < INT_EVENT0_ISET_SPEC , 10 > { INT_EVENT0_ISET_RXINT_W :: new (self) } # [do...
[INFO] [stdout]   |                  ^^^^^^^^^^     ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here
[INFO] [stdout]   |                  |
[INFO] [stdout]   |                  the lifetime is elided here
[INFO] [stdout]   |
[INFO] [stdout]   = help: the same lifetime is referred to in inconsistent ways, making the signature confusing
[INFO] [stdout] help: use `'_` for type paths
[INFO] [stdout]   |
[INFO] [stdout] 1 | # [doc = "Register `INT_EVENT0_ISET` writer"] pub type W = crate :: W < INT_EVENT0_ISET_SPEC > ; # [doc = "Set UARTOUT Receive Time-Out Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_RTOUT_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_RTOUT_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_RTOUT_SET = 1 , } impl From < INT_EVENT0_ISET_RTOUT_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_RTOUT_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_RTOUT` writer - Set UARTOUT Receive Time-Out Interrupt."] pub type INT_EVENT0_ISET_RTOUT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_RTOUT_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_RTOUT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_rtout_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_RTOUT_AW :: INT_EVENT0_ISET_RTOUT_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_rtout_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_RTOUT_AW :: INT_EVENT0_ISET_RTOUT_SET) } } # [doc = "Set UART Framing Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_FRMERR_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_FRMERR_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_FRMERR_SET = 1 , } impl From < INT_EVENT0_ISET_FRMERR_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_FRMERR_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_FRMERR` writer - Set UART Framing Error Interrupt."] pub type INT_EVENT0_ISET_FRMERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_FRMERR_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_FRMERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_frmerr_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_FRMERR_AW :: INT_EVENT0_ISET_FRMERR_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_frmerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_FRMERR_AW :: INT_EVENT0_ISET_FRMERR_SET) } } # [doc = "Set UART Parity Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_PARERR_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_PARERR_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_PARERR_SET = 1 , } impl From < INT_EVENT0_ISET_PARERR_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_PARERR_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_PARERR` writer - Set UART Parity Error Interrupt."] pub type INT_EVENT0_ISET_PARERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_PARERR_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_PARERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_parerr_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_PARERR_AW :: INT_EVENT0_ISET_PARERR_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_parerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_PARERR_AW :: INT_EVENT0_ISET_PARERR_SET) } } # [doc = "Set UART Break Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_BRKERR_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_BRKERR_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_BRKERR_SET = 1 , } impl From < INT_EVENT0_ISET_BRKERR_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_BRKERR_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_BRKERR` writer - Set UART Break Error Interrupt."] pub type INT_EVENT0_ISET_BRKERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_BRKERR_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_BRKERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_brkerr_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_BRKERR_AW :: INT_EVENT0_ISET_BRKERR_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_brkerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_BRKERR_AW :: INT_EVENT0_ISET_BRKERR_SET) } } # [doc = "Set UART Receive Overrun Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_OVRERR_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_OVRERR_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_OVRERR_SET = 1 , } impl From < INT_EVENT0_ISET_OVRERR_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_OVRERR_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_OVRERR` writer - Set UART Receive Overrun Error Interrupt."] pub type INT_EVENT0_ISET_OVRERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_OVRERR_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_OVRERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_ovrerr_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_OVRERR_AW :: INT_EVENT0_ISET_OVRERR_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_ovrerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_OVRERR_AW :: INT_EVENT0_ISET_OVRERR_SET) } } # [doc = "Set Negative Edge on UARTxRXD Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_RXNE_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_RXNE_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_RXNE_SET = 1 , } impl From < INT_EVENT0_ISET_RXNE_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_RXNE_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_RXNE` writer - Set Negative Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_ISET_RXNE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_RXNE_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_RXNE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_rxne_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_RXNE_AW :: INT_EVENT0_ISET_RXNE_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_rxne_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_RXNE_AW :: INT_EVENT0_ISET_RXNE_SET) } } # [doc = "Set Positive Edge on UARTxRXD Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_RXPE_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_RXPE_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_RXPE_SET = 1 , } impl From < INT_EVENT0_ISET_RXPE_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_RXPE_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_RXPE` writer - Set Positive Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_ISET_RXPE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_RXPE_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_RXPE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_rxpe_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_RXPE_AW :: INT_EVENT0_ISET_RXPE_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_rxpe_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_RXPE_AW :: INT_EVENT0_ISET_RXPE_SET) } } # [doc = "Set LIN Capture 0 / Match Interrupt .\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_LINC0_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_LINC0_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_LINC0_SET = 1 , } impl From < INT_EVENT0_ISET_LINC0_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_LINC0_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_LINC0` writer - Set LIN Capture 0 / Match Interrupt ."] pub type INT_EVENT0_ISET_LINC0_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_LINC0_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_LINC0_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_linc0_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_LINC0_AW :: INT_EVENT0_ISET_LINC0_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_linc0_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_LINC0_AW :: INT_EVENT0_ISET_LINC0_SET) } } # [doc = "Set LIN Capture 1 Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_LINC1_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_LINC1_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_LINC1_SET = 1 , } impl From < INT_EVENT0_ISET_LINC1_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_LINC1_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_LINC1` writer - Set LIN Capture 1 Interrupt."] pub type INT_EVENT0_ISET_LINC1_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_LINC1_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_LINC1_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_linc1_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_LINC1_AW :: INT_EVENT0_ISET_LINC1_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_linc1_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_LINC1_AW :: INT_EVENT0_ISET_LINC1_SET) } } # [doc = "Set LIN Hardware Counter Overflow Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_LINOVF_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_LINOVF_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_LINOVF_SET = 1 , } impl From < INT_EVENT0_ISET_LINOVF_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_LINOVF_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_LINOVF` writer - Set LIN Hardware Counter Overflow Interrupt."] pub type INT_EVENT0_ISET_LINOVF_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_LINOVF_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_LINOVF_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_linovf_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_LINOVF_AW :: INT_EVENT0_ISET_LINOVF_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_linovf_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_LINOVF_AW :: INT_EVENT0_ISET_LINOVF_SET) } } # [doc = "Set UART Receive Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_RXINT_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_RXINT_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_RXINT_SET = 1 , } impl From < INT_EVENT0_ISET_RXINT_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_RXINT_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_RXINT` writer - Set UART Receive Interrupt."] pub type INT_EVENT0_ISET_RXINT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_RXINT_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_RXINT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_rxint_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_RXINT_AW :: INT_EVENT0_ISET_RXINT_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_rxint_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_RXINT_AW :: INT_EVENT0_ISET_RXINT_SET) } } # [doc = "Set UART Transmit Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_TXINT_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_TXINT_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_TXINT_SET = 1 , } impl From < INT_EVENT0_ISET_TXINT_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_TXINT_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_TXINT` writer - Set UART Transmit Interrupt."] pub type INT_EVENT0_ISET_TXINT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_TXINT_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_TXINT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_txint_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_TXINT_AW :: INT_EVENT0_ISET_TXINT_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_txint_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_TXINT_AW :: INT_EVENT0_ISET_TXINT_SET) } } # [doc = "Set UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_EOT_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_EOT_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_EOT_SET = 1 , } impl From < INT_EVENT0_ISET_EOT_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_EOT_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_EOT` writer - Set UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] pub type INT_EVENT0_ISET_EOT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_EOT_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_EOT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_eot_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_EOT_AW :: INT_EVENT0_ISET_EOT_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_eot_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_EOT_AW :: INT_EVENT0_ISET_EOT_SET) } } # [doc = "Set Address Match Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_ADDR_MATCH_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_ADDR_MATCH_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_ADDR_MATCH_SET = 1 , } impl From < INT_EVENT0_ISET_ADDR_MATCH_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_ADDR_MATCH_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_ADDR_MATCH` writer - Set Address Match Interrupt."] pub type INT_EVENT0_ISET_ADDR_MATCH_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_ADDR_MATCH_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_ADDR_MATCH_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_addr_match_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_ADDR_MATCH_AW :: INT_EVENT0_ISET_ADDR_MATCH_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_addr_match_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_ADDR_MATCH_AW :: INT_EVENT0_ISET_ADDR_MATCH_SET) } } # [doc = "Set UART Clear to Send Modem Interrupt. 0 = Interrupt disabled\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_CTS_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_CTS_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_CTS_SET = 1 , } impl From < INT_EVENT0_ISET_CTS_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_CTS_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_CTS` writer - Set UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] pub type INT_EVENT0_ISET_CTS_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_CTS_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_CTS_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_cts_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_CTS_AW :: INT_EVENT0_ISET_CTS_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_cts_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_CTS_AW :: INT_EVENT0_ISET_CTS_SET) } } # [doc = "Set DMA Done on RX Event Channel\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_DMA_DONE_RX_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_DMA_DONE_RX_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_DMA_DONE_RX_SET = 1 , } impl From < INT_EVENT0_ISET_DMA_DONE_RX_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_DMA_DONE_RX_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_DMA_DONE_RX` writer - Set DMA Done on RX Event Channel"] pub type INT_EVENT0_ISET_DMA_DONE_RX_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_DMA_DONE_RX_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_DMA_DONE_RX_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_dma_done_rx_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_DMA_DONE_RX_AW :: INT_EVENT0_ISET_DMA_DONE_RX_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_dma_done_rx_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_DMA_DONE_RX_AW :: INT_EVENT0_ISET_DMA_DONE_RX_SET) } } # [doc = "Set DMA Done on TX Event Channel\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_DMA_DONE_TX_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_DMA_DONE_TX_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_DMA_DONE_TX_SET = 1 , } impl From < INT_EVENT0_ISET_DMA_DONE_TX_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_DMA_DONE_TX_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_DMA_DONE_TX` writer - Set DMA Done on TX Event Channel"] pub type INT_EVENT0_ISET_DMA_DONE_TX_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_DMA_DONE_TX_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_DMA_DONE_TX_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_dma_done_tx_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_DMA_DONE_TX_AW :: INT_EVENT0_ISET_DMA_DONE_TX_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_dma_done_tx_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_DMA_DONE_TX_AW :: INT_EVENT0_ISET_DMA_DONE_TX_SET) } } # [doc = "Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_NERR_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_NERR_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_NERR_SET = 1 , } impl From < INT_EVENT0_ISET_NERR_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_NERR_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_NERR` writer - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] pub type INT_EVENT0_ISET_NERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_NERR_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_NERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_nerr_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_NERR_AW :: INT_EVENT0_ISET_NERR_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_nerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_NERR_AW :: INT_EVENT0_ISET_NERR_SET) } } impl W { # [doc = "Bit 0 - Set UARTOUT Receive Time-Out Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iset_rtout (& mut self) -> INT_EVENT0_ISET_RTOUT_W < INT_EVENT0_ISET_SPEC , 0 > { INT_EVENT0_ISET_RTOUT_W :: new (self) } # [doc = "Bit 1 - Set UART Framing Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iset_frmerr (& mut self) -> INT_EVENT0_ISET_FRMERR_W < INT_EVENT0_ISET_SPEC , 1 > { INT_EVENT0_ISET_FRMERR_W :: new (self) } # [doc = "Bit 2 - Set UART Parity Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iset_parerr (& mut self) -> INT_EVENT0_ISET_PARERR_W < INT_EVENT0_ISET_SPEC , 2 > { INT_EVENT0_ISET_PARERR_W :: new (self) } # [doc = "Bit 3 - Set UART Break Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iset_brkerr (& mut self) -> INT_EVENT0_ISET_BRKERR_W < INT_EVENT0_ISET_SPEC , 3 > { INT_EVENT0_ISET_BRKERR_W :: new (self) } # [doc = "Bit 4 - Set UART Receive Overrun Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iset_ovrerr (& mut self) -> INT_EVENT0_ISET_OVRERR_W < INT_EVENT0_ISET_SPEC , 4 > { INT_EVENT0_ISET_OVRERR_W :: new (self) } # [doc = "Bit 5 - Set Negative Edge on UARTxRXD Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iset_rxne (& mut self) -> INT_EVENT0_ISET_RXNE_W < INT_EVENT0_ISET_SPEC , 5 > { INT_EVENT0_ISET_RXNE_W :: new (self) } # [doc = "Bit 6 - Set Positive Edge on UARTxRXD Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iset_rxpe (& mut self) -> INT_EVENT0_ISET_RXPE_W < INT_EVENT0_ISET_SPEC , 6 > { INT_EVENT0_ISET_RXPE_W :: new (self) } # [doc = "Bit 7 - Set LIN Capture 0 / Match Interrupt ."] # [inline (always)] # [must_use] pub fn int_event0_iset_linc0 (& mut self) -> INT_EVENT0_ISET_LINC0_W < INT_EVENT0_ISET_SPEC , 7 > { INT_EVENT0_ISET_LINC0_W :: new (self) } # [doc = "Bit 8 - Set LIN Capture 1 Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iset_linc1 (& mut self) -> INT_EVENT0_ISET_LINC1_W < INT_EVENT0_ISET_SPEC , 8 > { INT_EVENT0_ISET_LINC1_W :: new (self) } # [doc = "Bit 9 - Set LIN Hardware Counter Overflow Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iset_linovf (& mut self) -> INT_EVENT0_ISET_LINOVF_W < INT_EVENT0_ISET_SPEC , 9 > { INT_EVENT0_ISET_LINOVF_W :: new (self) } # [doc = "Bit 10 - Set UART Receive Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iset_rxint (& mut self) -> INT_EVENT0_ISET_RXINT_W <'_,  INT_EVENT0_ISET_SPEC , 10 > { INT_EVENT0_ISET_RXINT_W :: new (self) } # [doc = "Bit 11 - Set UART Transmit Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iset_txint (& mut self) -> INT_EVENT0_ISET_TXINT_W < INT_EVENT0_ISET_SPEC , 11 > { INT_EVENT0_ISET_TXINT_W :: new (self) } # [doc = "Bit 12 - Set UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] # [inline (always)] # [must_use] pub fn int_event0_iset_eot (& mut self) -> INT_EVENT0_ISET_EOT_W < INT_EVENT0_ISET_SPEC , 12 > { INT_EVENT0_ISET_EOT_W :: new (self) } # [doc = "Bit 13 - Set Address Match Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iset_addr_match (& mut self) -> INT_EVENT0_ISET_ADDR_MATCH_W < INT_EVENT0_ISET_SPEC , 13 > { INT_EVENT0_ISET_ADDR_MATCH_W :: new (self) } # [doc = "Bit 14 - Set UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] # [inline (always)] # [must_use] pub fn int_event0_iset_cts (& mut self) -> INT_EVENT0_ISET_CTS_W < INT_EVENT0_ISET_SPEC , 14 > { INT_EVENT0_ISET_CTS_W :: new (self) } # [doc = "Bit 15 - Set DMA Done on RX Event Channel"] # [inline (always)] # [must_use] pub fn int_event0_iset_dma_done_rx (& mut self) -> INT_EVENT0_ISET_DMA_DONE_RX_W < INT_EVENT0_ISET_SPEC , 15 > { INT_EVENT0_ISET_DMA_DONE_RX_W :: new (self) } # [doc = "Bit 16 - Set DMA Done on TX Event Channel"] # [inline (always)] # [must_use] pub fn int_event0_iset_dma_done_tx (& mut self) -> INT_EVENT0_ISET_DMA_DONE_TX_W < INT_EVENT0_ISET_SPEC , 16 > { INT_EVENT0_ISET_DMA_DONE_TX_W :: new (self) } # [doc = "Bit 17 - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] # [inline (always)] # [must_use] pub fn int_event0_iset_nerr (& mut self) -> INT_EVENT0_ISET_NERR_W < INT_EVENT0_ISET_SPEC , 17 > { INT_EVENT0_ISET_NERR_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Interrupt set\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_event0_iset::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct INT_EVENT0_ISET_SPEC ; impl crate :: RegisterSpec for INT_EVENT0_ISET_SPEC { type Ux = u32 ; } # [doc = "`write(|w| ..)` method takes [`int_event0_iset::W`](W) writer structure"] impl crate :: Writable for INT_EVENT0_ISET_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets INT_EVENT0_ISET to value 0"] impl crate :: Resettable for INT_EVENT0_ISET_SPEC { const RESET_VALUE : Self :: Ux = 0 ; }
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                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                       +++
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing
[INFO] [stdout]  --> src/uart0/int_event0_iset.rs:1:24126
[INFO] [stdout]   |
[INFO] [stdout] 1 | ...0_iset_txint (& mut self) -> INT_EVENT0_ISET_TXINT_W < INT_EVENT0_ISET_SPEC , 11 > { INT_EVENT0_ISET_TXINT_W :: new (self) } # [do...
[INFO] [stdout]   |                  ^^^^^^^^^^     ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here
[INFO] [stdout]   |                  |
[INFO] [stdout]   |                  the lifetime is elided here
[INFO] [stdout]   |
[INFO] [stdout]   = help: the same lifetime is referred to in inconsistent ways, making the signature confusing
[INFO] [stdout] help: use `'_` for type paths
[INFO] [stdout]   |
[INFO] [stdout] 1 | # [doc = "Register `INT_EVENT0_ISET` writer"] pub type W = crate :: W < INT_EVENT0_ISET_SPEC > ; # [doc = "Set UARTOUT Receive Time-Out Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_RTOUT_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_RTOUT_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_RTOUT_SET = 1 , } impl From < INT_EVENT0_ISET_RTOUT_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_RTOUT_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_RTOUT` writer - Set UARTOUT Receive Time-Out Interrupt."] pub type INT_EVENT0_ISET_RTOUT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_RTOUT_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_RTOUT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_rtout_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_RTOUT_AW :: INT_EVENT0_ISET_RTOUT_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_rtout_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_RTOUT_AW :: INT_EVENT0_ISET_RTOUT_SET) } } # [doc = "Set UART Framing Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_FRMERR_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_FRMERR_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_FRMERR_SET = 1 , } impl From < INT_EVENT0_ISET_FRMERR_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_FRMERR_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_FRMERR` writer - Set UART Framing Error Interrupt."] pub type INT_EVENT0_ISET_FRMERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_FRMERR_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_FRMERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_frmerr_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_FRMERR_AW :: INT_EVENT0_ISET_FRMERR_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_frmerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_FRMERR_AW :: INT_EVENT0_ISET_FRMERR_SET) } } # [doc = "Set UART Parity Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_PARERR_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_PARERR_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_PARERR_SET = 1 , } impl From < INT_EVENT0_ISET_PARERR_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_PARERR_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_PARERR` writer - Set UART Parity Error Interrupt."] pub type INT_EVENT0_ISET_PARERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_PARERR_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_PARERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_parerr_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_PARERR_AW :: INT_EVENT0_ISET_PARERR_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_parerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_PARERR_AW :: INT_EVENT0_ISET_PARERR_SET) } } # [doc = "Set UART Break Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_BRKERR_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_BRKERR_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_BRKERR_SET = 1 , } impl From < INT_EVENT0_ISET_BRKERR_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_BRKERR_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_BRKERR` writer - Set UART Break Error Interrupt."] pub type INT_EVENT0_ISET_BRKERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_BRKERR_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_BRKERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_brkerr_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_BRKERR_AW :: INT_EVENT0_ISET_BRKERR_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_brkerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_BRKERR_AW :: INT_EVENT0_ISET_BRKERR_SET) } } # [doc = "Set UART Receive Overrun Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_OVRERR_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_OVRERR_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_OVRERR_SET = 1 , } impl From < INT_EVENT0_ISET_OVRERR_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_OVRERR_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_OVRERR` writer - Set UART Receive Overrun Error Interrupt."] pub type INT_EVENT0_ISET_OVRERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_OVRERR_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_OVRERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_ovrerr_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_OVRERR_AW :: INT_EVENT0_ISET_OVRERR_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_ovrerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_OVRERR_AW :: INT_EVENT0_ISET_OVRERR_SET) } } # [doc = "Set Negative Edge on UARTxRXD Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_RXNE_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_RXNE_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_RXNE_SET = 1 , } impl From < INT_EVENT0_ISET_RXNE_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_RXNE_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_RXNE` writer - Set Negative Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_ISET_RXNE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_RXNE_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_RXNE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_rxne_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_RXNE_AW :: INT_EVENT0_ISET_RXNE_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_rxne_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_RXNE_AW :: INT_EVENT0_ISET_RXNE_SET) } } # [doc = "Set Positive Edge on UARTxRXD Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_RXPE_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_RXPE_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_RXPE_SET = 1 , } impl From < INT_EVENT0_ISET_RXPE_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_RXPE_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_RXPE` writer - Set Positive Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_ISET_RXPE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_RXPE_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_RXPE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_rxpe_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_RXPE_AW :: INT_EVENT0_ISET_RXPE_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_rxpe_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_RXPE_AW :: INT_EVENT0_ISET_RXPE_SET) } } # [doc = "Set LIN Capture 0 / Match Interrupt .\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_LINC0_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_LINC0_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_LINC0_SET = 1 , } impl From < INT_EVENT0_ISET_LINC0_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_LINC0_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_LINC0` writer - Set LIN Capture 0 / Match Interrupt ."] pub type INT_EVENT0_ISET_LINC0_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_LINC0_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_LINC0_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_linc0_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_LINC0_AW :: INT_EVENT0_ISET_LINC0_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_linc0_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_LINC0_AW :: INT_EVENT0_ISET_LINC0_SET) } } # [doc = "Set LIN Capture 1 Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_LINC1_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_LINC1_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_LINC1_SET = 1 , } impl From < INT_EVENT0_ISET_LINC1_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_LINC1_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_LINC1` writer - Set LIN Capture 1 Interrupt."] pub type INT_EVENT0_ISET_LINC1_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_LINC1_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_LINC1_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_linc1_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_LINC1_AW :: INT_EVENT0_ISET_LINC1_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_linc1_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_LINC1_AW :: INT_EVENT0_ISET_LINC1_SET) } } # [doc = "Set LIN Hardware Counter Overflow Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_LINOVF_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_LINOVF_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_LINOVF_SET = 1 , } impl From < INT_EVENT0_ISET_LINOVF_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_LINOVF_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_LINOVF` writer - Set LIN Hardware Counter Overflow Interrupt."] pub type INT_EVENT0_ISET_LINOVF_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_LINOVF_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_LINOVF_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_linovf_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_LINOVF_AW :: INT_EVENT0_ISET_LINOVF_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_linovf_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_LINOVF_AW :: INT_EVENT0_ISET_LINOVF_SET) } } # [doc = "Set UART Receive Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_RXINT_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_RXINT_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_RXINT_SET = 1 , } impl From < INT_EVENT0_ISET_RXINT_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_RXINT_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_RXINT` writer - Set UART Receive Interrupt."] pub type INT_EVENT0_ISET_RXINT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_RXINT_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_RXINT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_rxint_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_RXINT_AW :: INT_EVENT0_ISET_RXINT_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_rxint_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_RXINT_AW :: INT_EVENT0_ISET_RXINT_SET) } } # [doc = "Set UART Transmit Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_TXINT_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_TXINT_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_TXINT_SET = 1 , } impl From < INT_EVENT0_ISET_TXINT_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_TXINT_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_TXINT` writer - Set UART Transmit Interrupt."] pub type INT_EVENT0_ISET_TXINT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_TXINT_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_TXINT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_txint_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_TXINT_AW :: INT_EVENT0_ISET_TXINT_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_txint_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_TXINT_AW :: INT_EVENT0_ISET_TXINT_SET) } } # [doc = "Set UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_EOT_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_EOT_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_EOT_SET = 1 , } impl From < INT_EVENT0_ISET_EOT_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_EOT_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_EOT` writer - Set UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] pub type INT_EVENT0_ISET_EOT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_EOT_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_EOT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_eot_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_EOT_AW :: INT_EVENT0_ISET_EOT_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_eot_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_EOT_AW :: INT_EVENT0_ISET_EOT_SET) } } # [doc = "Set Address Match Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_ADDR_MATCH_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_ADDR_MATCH_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_ADDR_MATCH_SET = 1 , } impl From < INT_EVENT0_ISET_ADDR_MATCH_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_ADDR_MATCH_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_ADDR_MATCH` writer - Set Address Match Interrupt."] pub type INT_EVENT0_ISET_ADDR_MATCH_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_ADDR_MATCH_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_ADDR_MATCH_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_addr_match_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_ADDR_MATCH_AW :: INT_EVENT0_ISET_ADDR_MATCH_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_addr_match_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_ADDR_MATCH_AW :: INT_EVENT0_ISET_ADDR_MATCH_SET) } } # [doc = "Set UART Clear to Send Modem Interrupt. 0 = Interrupt disabled\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_CTS_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_CTS_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_CTS_SET = 1 , } impl From < INT_EVENT0_ISET_CTS_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_CTS_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_CTS` writer - Set UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] pub type INT_EVENT0_ISET_CTS_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_CTS_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_CTS_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_cts_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_CTS_AW :: INT_EVENT0_ISET_CTS_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_cts_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_CTS_AW :: INT_EVENT0_ISET_CTS_SET) } } # [doc = "Set DMA Done on RX Event Channel\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_DMA_DONE_RX_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_DMA_DONE_RX_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_DMA_DONE_RX_SET = 1 , } impl From < INT_EVENT0_ISET_DMA_DONE_RX_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_DMA_DONE_RX_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_DMA_DONE_RX` writer - Set DMA Done on RX Event Channel"] pub type INT_EVENT0_ISET_DMA_DONE_RX_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_DMA_DONE_RX_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_DMA_DONE_RX_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_dma_done_rx_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_DMA_DONE_RX_AW :: INT_EVENT0_ISET_DMA_DONE_RX_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_dma_done_rx_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_DMA_DONE_RX_AW :: INT_EVENT0_ISET_DMA_DONE_RX_SET) } } # [doc = "Set DMA Done on TX Event Channel\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_DMA_DONE_TX_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_DMA_DONE_TX_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_DMA_DONE_TX_SET = 1 , } impl From < INT_EVENT0_ISET_DMA_DONE_TX_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_DMA_DONE_TX_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_DMA_DONE_TX` writer - Set DMA Done on TX Event Channel"] pub type INT_EVENT0_ISET_DMA_DONE_TX_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_DMA_DONE_TX_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_DMA_DONE_TX_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_dma_done_tx_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_DMA_DONE_TX_AW :: INT_EVENT0_ISET_DMA_DONE_TX_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_dma_done_tx_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_DMA_DONE_TX_AW :: INT_EVENT0_ISET_DMA_DONE_TX_SET) } } # [doc = "Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_NERR_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_NERR_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_NERR_SET = 1 , } impl From < INT_EVENT0_ISET_NERR_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_NERR_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_NERR` writer - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] pub type INT_EVENT0_ISET_NERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_NERR_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_NERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_nerr_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_NERR_AW :: INT_EVENT0_ISET_NERR_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_nerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_NERR_AW :: INT_EVENT0_ISET_NERR_SET) } } impl W { # [doc = "Bit 0 - Set UARTOUT Receive Time-Out Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iset_rtout (& mut self) -> INT_EVENT0_ISET_RTOUT_W < INT_EVENT0_ISET_SPEC , 0 > { INT_EVENT0_ISET_RTOUT_W :: new (self) } # [doc = "Bit 1 - Set UART Framing Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iset_frmerr (& mut self) -> INT_EVENT0_ISET_FRMERR_W < INT_EVENT0_ISET_SPEC , 1 > { INT_EVENT0_ISET_FRMERR_W :: new (self) } # [doc = "Bit 2 - Set UART Parity Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iset_parerr (& mut self) -> INT_EVENT0_ISET_PARERR_W < INT_EVENT0_ISET_SPEC , 2 > { INT_EVENT0_ISET_PARERR_W :: new (self) } # [doc = "Bit 3 - Set UART Break Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iset_brkerr (& mut self) -> INT_EVENT0_ISET_BRKERR_W < INT_EVENT0_ISET_SPEC , 3 > { INT_EVENT0_ISET_BRKERR_W :: new (self) } # [doc = "Bit 4 - Set UART Receive Overrun Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iset_ovrerr (& mut self) -> INT_EVENT0_ISET_OVRERR_W < INT_EVENT0_ISET_SPEC , 4 > { INT_EVENT0_ISET_OVRERR_W :: new (self) } # [doc = "Bit 5 - Set Negative Edge on UARTxRXD Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iset_rxne (& mut self) -> INT_EVENT0_ISET_RXNE_W < INT_EVENT0_ISET_SPEC , 5 > { INT_EVENT0_ISET_RXNE_W :: new (self) } # [doc = "Bit 6 - Set Positive Edge on UARTxRXD Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iset_rxpe (& mut self) -> INT_EVENT0_ISET_RXPE_W < INT_EVENT0_ISET_SPEC , 6 > { INT_EVENT0_ISET_RXPE_W :: new (self) } # [doc = "Bit 7 - Set LIN Capture 0 / Match Interrupt ."] # [inline (always)] # [must_use] pub fn int_event0_iset_linc0 (& mut self) -> INT_EVENT0_ISET_LINC0_W < INT_EVENT0_ISET_SPEC , 7 > { INT_EVENT0_ISET_LINC0_W :: new (self) } # [doc = "Bit 8 - Set LIN Capture 1 Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iset_linc1 (& mut self) -> INT_EVENT0_ISET_LINC1_W < INT_EVENT0_ISET_SPEC , 8 > { INT_EVENT0_ISET_LINC1_W :: new (self) } # [doc = "Bit 9 - Set LIN Hardware Counter Overflow Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iset_linovf (& mut self) -> INT_EVENT0_ISET_LINOVF_W < INT_EVENT0_ISET_SPEC , 9 > { INT_EVENT0_ISET_LINOVF_W :: new (self) } # [doc = "Bit 10 - Set UART Receive Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iset_rxint (& mut self) -> INT_EVENT0_ISET_RXINT_W < INT_EVENT0_ISET_SPEC , 10 > { INT_EVENT0_ISET_RXINT_W :: new (self) } # [doc = "Bit 11 - Set UART Transmit Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iset_txint (& mut self) -> INT_EVENT0_ISET_TXINT_W <'_,  INT_EVENT0_ISET_SPEC , 11 > { INT_EVENT0_ISET_TXINT_W :: new (self) } # [doc = "Bit 12 - Set UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] # [inline (always)] # [must_use] pub fn int_event0_iset_eot (& mut self) -> INT_EVENT0_ISET_EOT_W < INT_EVENT0_ISET_SPEC , 12 > { INT_EVENT0_ISET_EOT_W :: new (self) } # [doc = "Bit 13 - Set Address Match Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iset_addr_match (& mut self) -> INT_EVENT0_ISET_ADDR_MATCH_W < INT_EVENT0_ISET_SPEC , 13 > { INT_EVENT0_ISET_ADDR_MATCH_W :: new (self) } # [doc = "Bit 14 - Set UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] # [inline (always)] # [must_use] pub fn int_event0_iset_cts (& mut self) -> INT_EVENT0_ISET_CTS_W < INT_EVENT0_ISET_SPEC , 14 > { INT_EVENT0_ISET_CTS_W :: new (self) } # [doc = "Bit 15 - Set DMA Done on RX Event Channel"] # [inline (always)] # [must_use] pub fn int_event0_iset_dma_done_rx (& mut self) -> INT_EVENT0_ISET_DMA_DONE_RX_W < INT_EVENT0_ISET_SPEC , 15 > { INT_EVENT0_ISET_DMA_DONE_RX_W :: new (self) } # [doc = "Bit 16 - Set DMA Done on TX Event Channel"] # [inline (always)] # [must_use] pub fn int_event0_iset_dma_done_tx (& mut self) -> INT_EVENT0_ISET_DMA_DONE_TX_W < INT_EVENT0_ISET_SPEC , 16 > { INT_EVENT0_ISET_DMA_DONE_TX_W :: new (self) } # [doc = "Bit 17 - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] # [inline (always)] # [must_use] pub fn int_event0_iset_nerr (& mut self) -> INT_EVENT0_ISET_NERR_W < INT_EVENT0_ISET_SPEC , 17 > { INT_EVENT0_ISET_NERR_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Interrupt set\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_event0_iset::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct INT_EVENT0_ISET_SPEC ; impl crate :: RegisterSpec for INT_EVENT0_ISET_SPEC { type Ux = u32 ; } # [doc = "`write(|w| ..)` method takes [`int_event0_iset::W`](W) writer structure"] impl crate :: Writable for INT_EVENT0_ISET_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets INT_EVENT0_ISET to value 0"] impl crate :: Resettable for INT_EVENT0_ISET_SPEC { const RESET_VALUE : Self :: Ux = 0 ; }
[INFO] [stdout]   |                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                      +++
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing
[INFO] [stdout]  --> src/uart0/int_event0_iset.rs:1:24499
[INFO] [stdout]   |
[INFO] [stdout] 1 | ...ent0_iset_eot (& mut self) -> INT_EVENT0_ISET_EOT_W < INT_EVENT0_ISET_SPEC , 12 > { INT_EVENT0_ISET_EOT_W :: new (self) } # [doc =...
[INFO] [stdout]   |                   ^^^^^^^^^^     ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here
[INFO] [stdout]   |                   |
[INFO] [stdout]   |                   the lifetime is elided here
[INFO] [stdout]   |
[INFO] [stdout]   = help: the same lifetime is referred to in inconsistent ways, making the signature confusing
[INFO] [stdout] help: use `'_` for type paths
[INFO] [stdout]   |
[INFO] [stdout] 1 | # [doc = "Register `INT_EVENT0_ISET` writer"] pub type W = crate :: W < INT_EVENT0_ISET_SPEC > ; # [doc = "Set UARTOUT Receive Time-Out Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_RTOUT_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_RTOUT_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_RTOUT_SET = 1 , } impl From < INT_EVENT0_ISET_RTOUT_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_RTOUT_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_RTOUT` writer - Set UARTOUT Receive Time-Out Interrupt."] pub type INT_EVENT0_ISET_RTOUT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_RTOUT_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_RTOUT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_rtout_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_RTOUT_AW :: INT_EVENT0_ISET_RTOUT_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_rtout_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_RTOUT_AW :: INT_EVENT0_ISET_RTOUT_SET) } } # [doc = "Set UART Framing Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_FRMERR_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_FRMERR_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_FRMERR_SET = 1 , } impl From < INT_EVENT0_ISET_FRMERR_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_FRMERR_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_FRMERR` writer - Set UART Framing Error Interrupt."] pub type INT_EVENT0_ISET_FRMERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_FRMERR_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_FRMERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_frmerr_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_FRMERR_AW :: INT_EVENT0_ISET_FRMERR_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_frmerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_FRMERR_AW :: INT_EVENT0_ISET_FRMERR_SET) } } # [doc = "Set UART Parity Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_PARERR_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_PARERR_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_PARERR_SET = 1 , } impl From < INT_EVENT0_ISET_PARERR_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_PARERR_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_PARERR` writer - Set UART Parity Error Interrupt."] pub type INT_EVENT0_ISET_PARERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_PARERR_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_PARERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_parerr_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_PARERR_AW :: INT_EVENT0_ISET_PARERR_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_parerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_PARERR_AW :: INT_EVENT0_ISET_PARERR_SET) } } # [doc = "Set UART Break Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_BRKERR_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_BRKERR_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_BRKERR_SET = 1 , } impl From < INT_EVENT0_ISET_BRKERR_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_BRKERR_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_BRKERR` writer - Set UART Break Error Interrupt."] pub type INT_EVENT0_ISET_BRKERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_BRKERR_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_BRKERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_brkerr_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_BRKERR_AW :: INT_EVENT0_ISET_BRKERR_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_brkerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_BRKERR_AW :: INT_EVENT0_ISET_BRKERR_SET) } } # [doc = "Set UART Receive Overrun Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_OVRERR_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_OVRERR_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_OVRERR_SET = 1 , } impl From < INT_EVENT0_ISET_OVRERR_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_OVRERR_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_OVRERR` writer - Set UART Receive Overrun Error Interrupt."] pub type INT_EVENT0_ISET_OVRERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_OVRERR_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_OVRERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_ovrerr_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_OVRERR_AW :: INT_EVENT0_ISET_OVRERR_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_ovrerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_OVRERR_AW :: INT_EVENT0_ISET_OVRERR_SET) } } # [doc = "Set Negative Edge on UARTxRXD Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_RXNE_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_RXNE_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_RXNE_SET = 1 , } impl From < INT_EVENT0_ISET_RXNE_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_RXNE_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_RXNE` writer - Set Negative Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_ISET_RXNE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_RXNE_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_RXNE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_rxne_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_RXNE_AW :: INT_EVENT0_ISET_RXNE_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_rxne_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_RXNE_AW :: INT_EVENT0_ISET_RXNE_SET) } } # [doc = "Set Positive Edge on UARTxRXD Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_RXPE_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_RXPE_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_RXPE_SET = 1 , } impl From < INT_EVENT0_ISET_RXPE_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_RXPE_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_RXPE` writer - Set Positive Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_ISET_RXPE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_RXPE_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_RXPE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_rxpe_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_RXPE_AW :: INT_EVENT0_ISET_RXPE_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_rxpe_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_RXPE_AW :: INT_EVENT0_ISET_RXPE_SET) } } # [doc = "Set LIN Capture 0 / Match Interrupt .\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_LINC0_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_LINC0_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_LINC0_SET = 1 , } impl From < INT_EVENT0_ISET_LINC0_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_LINC0_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_LINC0` writer - Set LIN Capture 0 / Match Interrupt ."] pub type INT_EVENT0_ISET_LINC0_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_LINC0_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_LINC0_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_linc0_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_LINC0_AW :: INT_EVENT0_ISET_LINC0_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_linc0_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_LINC0_AW :: INT_EVENT0_ISET_LINC0_SET) } } # [doc = "Set LIN Capture 1 Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_LINC1_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_LINC1_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_LINC1_SET = 1 , } impl From < INT_EVENT0_ISET_LINC1_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_LINC1_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_LINC1` writer - Set LIN Capture 1 Interrupt."] pub type INT_EVENT0_ISET_LINC1_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_LINC1_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_LINC1_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_linc1_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_LINC1_AW :: INT_EVENT0_ISET_LINC1_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_linc1_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_LINC1_AW :: INT_EVENT0_ISET_LINC1_SET) } } # [doc = "Set LIN Hardware Counter Overflow Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_LINOVF_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_LINOVF_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_LINOVF_SET = 1 , } impl From < INT_EVENT0_ISET_LINOVF_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_LINOVF_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_LINOVF` writer - Set LIN Hardware Counter Overflow Interrupt."] pub type INT_EVENT0_ISET_LINOVF_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_LINOVF_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_LINOVF_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_linovf_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_LINOVF_AW :: INT_EVENT0_ISET_LINOVF_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_linovf_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_LINOVF_AW :: INT_EVENT0_ISET_LINOVF_SET) } } # [doc = "Set UART Receive Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_RXINT_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_RXINT_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_RXINT_SET = 1 , } impl From < INT_EVENT0_ISET_RXINT_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_RXINT_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_RXINT` writer - Set UART Receive Interrupt."] pub type INT_EVENT0_ISET_RXINT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_RXINT_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_RXINT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_rxint_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_RXINT_AW :: INT_EVENT0_ISET_RXINT_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_rxint_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_RXINT_AW :: INT_EVENT0_ISET_RXINT_SET) } } # [doc = "Set UART Transmit Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_TXINT_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_TXINT_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_TXINT_SET = 1 , } impl From < INT_EVENT0_ISET_TXINT_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_TXINT_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_TXINT` writer - Set UART Transmit Interrupt."] pub type INT_EVENT0_ISET_TXINT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_TXINT_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_TXINT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_txint_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_TXINT_AW :: INT_EVENT0_ISET_TXINT_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_txint_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_TXINT_AW :: INT_EVENT0_ISET_TXINT_SET) } } # [doc = "Set UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_EOT_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_EOT_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_EOT_SET = 1 , } impl From < INT_EVENT0_ISET_EOT_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_EOT_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_EOT` writer - Set UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] pub type INT_EVENT0_ISET_EOT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_EOT_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_EOT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_eot_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_EOT_AW :: INT_EVENT0_ISET_EOT_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_eot_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_EOT_AW :: INT_EVENT0_ISET_EOT_SET) } } # [doc = "Set Address Match Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_ADDR_MATCH_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_ADDR_MATCH_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_ADDR_MATCH_SET = 1 , } impl From < INT_EVENT0_ISET_ADDR_MATCH_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_ADDR_MATCH_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_ADDR_MATCH` writer - Set Address Match Interrupt."] pub type INT_EVENT0_ISET_ADDR_MATCH_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_ADDR_MATCH_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_ADDR_MATCH_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_addr_match_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_ADDR_MATCH_AW :: INT_EVENT0_ISET_ADDR_MATCH_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_addr_match_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_ADDR_MATCH_AW :: INT_EVENT0_ISET_ADDR_MATCH_SET) } } # [doc = "Set UART Clear to Send Modem Interrupt. 0 = Interrupt disabled\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_CTS_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_CTS_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_CTS_SET = 1 , } impl From < INT_EVENT0_ISET_CTS_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_CTS_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_CTS` writer - Set UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] pub type INT_EVENT0_ISET_CTS_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_CTS_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_CTS_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_cts_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_CTS_AW :: INT_EVENT0_ISET_CTS_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_cts_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_CTS_AW :: INT_EVENT0_ISET_CTS_SET) } } # [doc = "Set DMA Done on RX Event Channel\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_DMA_DONE_RX_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_DMA_DONE_RX_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_DMA_DONE_RX_SET = 1 , } impl From < INT_EVENT0_ISET_DMA_DONE_RX_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_DMA_DONE_RX_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_DMA_DONE_RX` writer - Set DMA Done on RX Event Channel"] pub type INT_EVENT0_ISET_DMA_DONE_RX_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_DMA_DONE_RX_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_DMA_DONE_RX_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_dma_done_rx_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_DMA_DONE_RX_AW :: INT_EVENT0_ISET_DMA_DONE_RX_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_dma_done_rx_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_DMA_DONE_RX_AW :: INT_EVENT0_ISET_DMA_DONE_RX_SET) } } # [doc = "Set DMA Done on TX Event Channel\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_DMA_DONE_TX_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_DMA_DONE_TX_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_DMA_DONE_TX_SET = 1 , } impl From < INT_EVENT0_ISET_DMA_DONE_TX_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_DMA_DONE_TX_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_DMA_DONE_TX` writer - Set DMA Done on TX Event Channel"] pub type INT_EVENT0_ISET_DMA_DONE_TX_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_DMA_DONE_TX_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_DMA_DONE_TX_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_dma_done_tx_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_DMA_DONE_TX_AW :: INT_EVENT0_ISET_DMA_DONE_TX_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_dma_done_tx_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_DMA_DONE_TX_AW :: INT_EVENT0_ISET_DMA_DONE_TX_SET) } } # [doc = "Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_NERR_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_NERR_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_NERR_SET = 1 , } impl From < INT_EVENT0_ISET_NERR_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_NERR_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_NERR` writer - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] pub type INT_EVENT0_ISET_NERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_NERR_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_NERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_nerr_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_NERR_AW :: INT_EVENT0_ISET_NERR_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_nerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_NERR_AW :: INT_EVENT0_ISET_NERR_SET) } } impl W { # [doc = "Bit 0 - Set UARTOUT Receive Time-Out Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iset_rtout (& mut self) -> INT_EVENT0_ISET_RTOUT_W < INT_EVENT0_ISET_SPEC , 0 > { INT_EVENT0_ISET_RTOUT_W :: new (self) } # [doc = "Bit 1 - Set UART Framing Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iset_frmerr (& mut self) -> INT_EVENT0_ISET_FRMERR_W < INT_EVENT0_ISET_SPEC , 1 > { INT_EVENT0_ISET_FRMERR_W :: new (self) } # [doc = "Bit 2 - Set UART Parity Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iset_parerr (& mut self) -> INT_EVENT0_ISET_PARERR_W < INT_EVENT0_ISET_SPEC , 2 > { INT_EVENT0_ISET_PARERR_W :: new (self) } # [doc = "Bit 3 - Set UART Break Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iset_brkerr (& mut self) -> INT_EVENT0_ISET_BRKERR_W < INT_EVENT0_ISET_SPEC , 3 > { INT_EVENT0_ISET_BRKERR_W :: new (self) } # [doc = "Bit 4 - Set UART Receive Overrun Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iset_ovrerr (& mut self) -> INT_EVENT0_ISET_OVRERR_W < INT_EVENT0_ISET_SPEC , 4 > { INT_EVENT0_ISET_OVRERR_W :: new (self) } # [doc = "Bit 5 - Set Negative Edge on UARTxRXD Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iset_rxne (& mut self) -> INT_EVENT0_ISET_RXNE_W < INT_EVENT0_ISET_SPEC , 5 > { INT_EVENT0_ISET_RXNE_W :: new (self) } # [doc = "Bit 6 - Set Positive Edge on UARTxRXD Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iset_rxpe (& mut self) -> INT_EVENT0_ISET_RXPE_W < INT_EVENT0_ISET_SPEC , 6 > { INT_EVENT0_ISET_RXPE_W :: new (self) } # [doc = "Bit 7 - Set LIN Capture 0 / Match Interrupt ."] # [inline (always)] # [must_use] pub fn int_event0_iset_linc0 (& mut self) -> INT_EVENT0_ISET_LINC0_W < INT_EVENT0_ISET_SPEC , 7 > { INT_EVENT0_ISET_LINC0_W :: new (self) } # [doc = "Bit 8 - Set LIN Capture 1 Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iset_linc1 (& mut self) -> INT_EVENT0_ISET_LINC1_W < INT_EVENT0_ISET_SPEC , 8 > { INT_EVENT0_ISET_LINC1_W :: new (self) } # [doc = "Bit 9 - Set LIN Hardware Counter Overflow Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iset_linovf (& mut self) -> INT_EVENT0_ISET_LINOVF_W < INT_EVENT0_ISET_SPEC , 9 > { INT_EVENT0_ISET_LINOVF_W :: new (self) } # [doc = "Bit 10 - Set UART Receive Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iset_rxint (& mut self) -> INT_EVENT0_ISET_RXINT_W < INT_EVENT0_ISET_SPEC , 10 > { INT_EVENT0_ISET_RXINT_W :: new (self) } # [doc = "Bit 11 - Set UART Transmit Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iset_txint (& mut self) -> INT_EVENT0_ISET_TXINT_W < INT_EVENT0_ISET_SPEC , 11 > { INT_EVENT0_ISET_TXINT_W :: new (self) } # [doc = "Bit 12 - Set UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] # [inline (always)] # [must_use] pub fn int_event0_iset_eot (& mut self) -> INT_EVENT0_ISET_EOT_W <'_,  INT_EVENT0_ISET_SPEC , 12 > { INT_EVENT0_ISET_EOT_W :: new (self) } # [doc = "Bit 13 - Set Address Match Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iset_addr_match (& mut self) -> INT_EVENT0_ISET_ADDR_MATCH_W < INT_EVENT0_ISET_SPEC , 13 > { INT_EVENT0_ISET_ADDR_MATCH_W :: new (self) } # [doc = "Bit 14 - Set UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] # [inline (always)] # [must_use] pub fn int_event0_iset_cts (& mut self) -> INT_EVENT0_ISET_CTS_W < INT_EVENT0_ISET_SPEC , 14 > { INT_EVENT0_ISET_CTS_W :: new (self) } # [doc = "Bit 15 - Set DMA Done on RX Event Channel"] # [inline (always)] # [must_use] pub fn int_event0_iset_dma_done_rx (& mut self) -> INT_EVENT0_ISET_DMA_DONE_RX_W < INT_EVENT0_ISET_SPEC , 15 > { INT_EVENT0_ISET_DMA_DONE_RX_W :: new (self) } # [doc = "Bit 16 - Set DMA Done on TX Event Channel"] # [inline (always)] # [must_use] pub fn int_event0_iset_dma_done_tx (& mut self) -> INT_EVENT0_ISET_DMA_DONE_TX_W < INT_EVENT0_ISET_SPEC , 16 > { INT_EVENT0_ISET_DMA_DONE_TX_W :: new (self) } # [doc = "Bit 17 - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] # [inline (always)] # [must_use] pub fn int_event0_iset_nerr (& mut self) -> INT_EVENT0_ISET_NERR_W < INT_EVENT0_ISET_SPEC , 17 > { INT_EVENT0_ISET_NERR_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Interrupt set\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_event0_iset::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct INT_EVENT0_ISET_SPEC ; impl crate :: RegisterSpec for INT_EVENT0_ISET_SPEC { type Ux = u32 ; } # [doc = "`write(|w| ..)` method takes [`int_event0_iset::W`](W) writer structure"] impl crate :: Writable for INT_EVENT0_ISET_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets INT_EVENT0_ISET to value 0"] impl crate :: Resettable for INT_EVENT0_ISET_SPEC { const RESET_VALUE : Self :: Ux = 0 ; }
[INFO] [stdout]   |                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                         +++
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing
[INFO] [stdout]  --> src/uart0/int_event0_iset.rs:1:24724
[INFO] [stdout]   |
[INFO] [stdout] 1 | ...addr_match (& mut self) -> INT_EVENT0_ISET_ADDR_MATCH_W < INT_EVENT0_ISET_SPEC , 13 > { INT_EVENT0_ISET_ADDR_MATCH_W :: new (self)...
[INFO] [stdout]   |                ^^^^^^^^^^     ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here
[INFO] [stdout]   |                |
[INFO] [stdout]   |                the lifetime is elided here
[INFO] [stdout]   |
[INFO] [stdout]   = help: the same lifetime is referred to in inconsistent ways, making the signature confusing
[INFO] [stdout] help: use `'_` for type paths
[INFO] [stdout]   |
[INFO] [stdout] 1 | # [doc = "Register `INT_EVENT0_ISET` writer"] pub type W = crate :: W < INT_EVENT0_ISET_SPEC > ; # [doc = "Set UARTOUT Receive Time-Out Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_RTOUT_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_RTOUT_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_RTOUT_SET = 1 , } impl From < INT_EVENT0_ISET_RTOUT_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_RTOUT_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_RTOUT` writer - Set UARTOUT Receive Time-Out Interrupt."] pub type INT_EVENT0_ISET_RTOUT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_RTOUT_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_RTOUT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_rtout_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_RTOUT_AW :: INT_EVENT0_ISET_RTOUT_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_rtout_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_RTOUT_AW :: INT_EVENT0_ISET_RTOUT_SET) } } # [doc = "Set UART Framing Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_FRMERR_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_FRMERR_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_FRMERR_SET = 1 , } impl From < INT_EVENT0_ISET_FRMERR_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_FRMERR_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_FRMERR` writer - Set UART Framing Error Interrupt."] pub type INT_EVENT0_ISET_FRMERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_FRMERR_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_FRMERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_frmerr_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_FRMERR_AW :: INT_EVENT0_ISET_FRMERR_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_frmerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_FRMERR_AW :: INT_EVENT0_ISET_FRMERR_SET) } } # [doc = "Set UART Parity Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_PARERR_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_PARERR_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_PARERR_SET = 1 , } impl From < INT_EVENT0_ISET_PARERR_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_PARERR_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_PARERR` writer - Set UART Parity Error Interrupt."] pub type INT_EVENT0_ISET_PARERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_PARERR_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_PARERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_parerr_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_PARERR_AW :: INT_EVENT0_ISET_PARERR_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_parerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_PARERR_AW :: INT_EVENT0_ISET_PARERR_SET) } } # [doc = "Set UART Break Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_BRKERR_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_BRKERR_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_BRKERR_SET = 1 , } impl From < INT_EVENT0_ISET_BRKERR_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_BRKERR_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_BRKERR` writer - Set UART Break Error Interrupt."] pub type INT_EVENT0_ISET_BRKERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_BRKERR_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_BRKERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_brkerr_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_BRKERR_AW :: INT_EVENT0_ISET_BRKERR_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_brkerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_BRKERR_AW :: INT_EVENT0_ISET_BRKERR_SET) } } # [doc = "Set UART Receive Overrun Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_OVRERR_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_OVRERR_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_OVRERR_SET = 1 , } impl From < INT_EVENT0_ISET_OVRERR_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_OVRERR_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_OVRERR` writer - Set UART Receive Overrun Error Interrupt."] pub type INT_EVENT0_ISET_OVRERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_OVRERR_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_OVRERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_ovrerr_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_OVRERR_AW :: INT_EVENT0_ISET_OVRERR_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_ovrerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_OVRERR_AW :: INT_EVENT0_ISET_OVRERR_SET) } } # [doc = "Set Negative Edge on UARTxRXD Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_RXNE_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_RXNE_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_RXNE_SET = 1 , } impl From < INT_EVENT0_ISET_RXNE_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_RXNE_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_RXNE` writer - Set Negative Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_ISET_RXNE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_RXNE_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_RXNE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_rxne_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_RXNE_AW :: INT_EVENT0_ISET_RXNE_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_rxne_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_RXNE_AW :: INT_EVENT0_ISET_RXNE_SET) } } # [doc = "Set Positive Edge on UARTxRXD Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_RXPE_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_RXPE_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_RXPE_SET = 1 , } impl From < INT_EVENT0_ISET_RXPE_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_RXPE_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_RXPE` writer - Set Positive Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_ISET_RXPE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_RXPE_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_RXPE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_rxpe_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_RXPE_AW :: INT_EVENT0_ISET_RXPE_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_rxpe_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_RXPE_AW :: INT_EVENT0_ISET_RXPE_SET) } } # [doc = "Set LIN Capture 0 / Match Interrupt .\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_LINC0_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_LINC0_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_LINC0_SET = 1 , } impl From < INT_EVENT0_ISET_LINC0_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_LINC0_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_LINC0` writer - Set LIN Capture 0 / Match Interrupt ."] pub type INT_EVENT0_ISET_LINC0_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_LINC0_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_LINC0_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_linc0_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_LINC0_AW :: INT_EVENT0_ISET_LINC0_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_linc0_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_LINC0_AW :: INT_EVENT0_ISET_LINC0_SET) } } # [doc = "Set LIN Capture 1 Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_LINC1_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_LINC1_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_LINC1_SET = 1 , } impl From < INT_EVENT0_ISET_LINC1_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_LINC1_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_LINC1` writer - Set LIN Capture 1 Interrupt."] pub type INT_EVENT0_ISET_LINC1_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_LINC1_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_LINC1_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_linc1_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_LINC1_AW :: INT_EVENT0_ISET_LINC1_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_linc1_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_LINC1_AW :: INT_EVENT0_ISET_LINC1_SET) } } # [doc = "Set LIN Hardware Counter Overflow Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_LINOVF_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_LINOVF_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_LINOVF_SET = 1 , } impl From < INT_EVENT0_ISET_LINOVF_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_LINOVF_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_LINOVF` writer - Set LIN Hardware Counter Overflow Interrupt."] pub type INT_EVENT0_ISET_LINOVF_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_LINOVF_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_LINOVF_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_linovf_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_LINOVF_AW :: INT_EVENT0_ISET_LINOVF_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_linovf_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_LINOVF_AW :: INT_EVENT0_ISET_LINOVF_SET) } } # [doc = "Set UART Receive Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_RXINT_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_RXINT_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_RXINT_SET = 1 , } impl From < INT_EVENT0_ISET_RXINT_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_RXINT_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_RXINT` writer - Set UART Receive Interrupt."] pub type INT_EVENT0_ISET_RXINT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_RXINT_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_RXINT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_rxint_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_RXINT_AW :: INT_EVENT0_ISET_RXINT_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_rxint_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_RXINT_AW :: INT_EVENT0_ISET_RXINT_SET) } } # [doc = "Set UART Transmit Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_TXINT_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_TXINT_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_TXINT_SET = 1 , } impl From < INT_EVENT0_ISET_TXINT_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_TXINT_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_TXINT` writer - Set UART Transmit Interrupt."] pub type INT_EVENT0_ISET_TXINT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_TXINT_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_TXINT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_txint_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_TXINT_AW :: INT_EVENT0_ISET_TXINT_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_txint_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_TXINT_AW :: INT_EVENT0_ISET_TXINT_SET) } } # [doc = "Set UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_EOT_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_EOT_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_EOT_SET = 1 , } impl From < INT_EVENT0_ISET_EOT_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_EOT_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_EOT` writer - Set UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] pub type INT_EVENT0_ISET_EOT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_EOT_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_EOT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_eot_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_EOT_AW :: INT_EVENT0_ISET_EOT_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_eot_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_EOT_AW :: INT_EVENT0_ISET_EOT_SET) } } # [doc = "Set Address Match Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_ADDR_MATCH_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_ADDR_MATCH_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_ADDR_MATCH_SET = 1 , } impl From < INT_EVENT0_ISET_ADDR_MATCH_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_ADDR_MATCH_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_ADDR_MATCH` writer - Set Address Match Interrupt."] pub type INT_EVENT0_ISET_ADDR_MATCH_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_ADDR_MATCH_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_ADDR_MATCH_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_addr_match_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_ADDR_MATCH_AW :: INT_EVENT0_ISET_ADDR_MATCH_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_addr_match_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_ADDR_MATCH_AW :: INT_EVENT0_ISET_ADDR_MATCH_SET) } } # [doc = "Set UART Clear to Send Modem Interrupt. 0 = Interrupt disabled\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_CTS_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_CTS_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_CTS_SET = 1 , } impl From < INT_EVENT0_ISET_CTS_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_CTS_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_CTS` writer - Set UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] pub type INT_EVENT0_ISET_CTS_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_CTS_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_CTS_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_cts_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_CTS_AW :: INT_EVENT0_ISET_CTS_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_cts_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_CTS_AW :: INT_EVENT0_ISET_CTS_SET) } } # [doc = "Set DMA Done on RX Event Channel\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_DMA_DONE_RX_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_DMA_DONE_RX_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_DMA_DONE_RX_SET = 1 , } impl From < INT_EVENT0_ISET_DMA_DONE_RX_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_DMA_DONE_RX_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_DMA_DONE_RX` writer - Set DMA Done on RX Event Channel"] pub type INT_EVENT0_ISET_DMA_DONE_RX_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_DMA_DONE_RX_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_DMA_DONE_RX_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_dma_done_rx_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_DMA_DONE_RX_AW :: INT_EVENT0_ISET_DMA_DONE_RX_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_dma_done_rx_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_DMA_DONE_RX_AW :: INT_EVENT0_ISET_DMA_DONE_RX_SET) } } # [doc = "Set DMA Done on TX Event Channel\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_DMA_DONE_TX_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_DMA_DONE_TX_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_DMA_DONE_TX_SET = 1 , } impl From < INT_EVENT0_ISET_DMA_DONE_TX_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_DMA_DONE_TX_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_DMA_DONE_TX` writer - Set DMA Done on TX Event Channel"] pub type INT_EVENT0_ISET_DMA_DONE_TX_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_DMA_DONE_TX_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_DMA_DONE_TX_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_dma_done_tx_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_DMA_DONE_TX_AW :: INT_EVENT0_ISET_DMA_DONE_TX_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_dma_done_tx_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_DMA_DONE_TX_AW :: INT_EVENT0_ISET_DMA_DONE_TX_SET) } } # [doc = "Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_NERR_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_NERR_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_NERR_SET = 1 , } impl From < INT_EVENT0_ISET_NERR_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_NERR_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_NERR` writer - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] pub type INT_EVENT0_ISET_NERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_NERR_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_NERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_nerr_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_NERR_AW :: INT_EVENT0_ISET_NERR_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_nerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_NERR_AW :: INT_EVENT0_ISET_NERR_SET) } } impl W { # [doc = "Bit 0 - Set UARTOUT Receive Time-Out Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iset_rtout (& mut self) -> INT_EVENT0_ISET_RTOUT_W < INT_EVENT0_ISET_SPEC , 0 > { INT_EVENT0_ISET_RTOUT_W :: new (self) } # [doc = "Bit 1 - Set UART Framing Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iset_frmerr (& mut self) -> INT_EVENT0_ISET_FRMERR_W < INT_EVENT0_ISET_SPEC , 1 > { INT_EVENT0_ISET_FRMERR_W :: new (self) } # [doc = "Bit 2 - Set UART Parity Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iset_parerr (& mut self) -> INT_EVENT0_ISET_PARERR_W < INT_EVENT0_ISET_SPEC , 2 > { INT_EVENT0_ISET_PARERR_W :: new (self) } # [doc = "Bit 3 - Set UART Break Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iset_brkerr (& mut self) -> INT_EVENT0_ISET_BRKERR_W < INT_EVENT0_ISET_SPEC , 3 > { INT_EVENT0_ISET_BRKERR_W :: new (self) } # [doc = "Bit 4 - Set UART Receive Overrun Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iset_ovrerr (& mut self) -> INT_EVENT0_ISET_OVRERR_W < INT_EVENT0_ISET_SPEC , 4 > { INT_EVENT0_ISET_OVRERR_W :: new (self) } # [doc = "Bit 5 - Set Negative Edge on UARTxRXD Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iset_rxne (& mut self) -> INT_EVENT0_ISET_RXNE_W < INT_EVENT0_ISET_SPEC , 5 > { INT_EVENT0_ISET_RXNE_W :: new (self) } # [doc = "Bit 6 - Set Positive Edge on UARTxRXD Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iset_rxpe (& mut self) -> INT_EVENT0_ISET_RXPE_W < INT_EVENT0_ISET_SPEC , 6 > { INT_EVENT0_ISET_RXPE_W :: new (self) } # [doc = "Bit 7 - Set LIN Capture 0 / Match Interrupt ."] # [inline (always)] # [must_use] pub fn int_event0_iset_linc0 (& mut self) -> INT_EVENT0_ISET_LINC0_W < INT_EVENT0_ISET_SPEC , 7 > { INT_EVENT0_ISET_LINC0_W :: new (self) } # [doc = "Bit 8 - Set LIN Capture 1 Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iset_linc1 (& mut self) -> INT_EVENT0_ISET_LINC1_W < INT_EVENT0_ISET_SPEC , 8 > { INT_EVENT0_ISET_LINC1_W :: new (self) } # [doc = "Bit 9 - Set LIN Hardware Counter Overflow Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iset_linovf (& mut self) -> INT_EVENT0_ISET_LINOVF_W < INT_EVENT0_ISET_SPEC , 9 > { INT_EVENT0_ISET_LINOVF_W :: new (self) } # [doc = "Bit 10 - Set UART Receive Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iset_rxint (& mut self) -> INT_EVENT0_ISET_RXINT_W < INT_EVENT0_ISET_SPEC , 10 > { INT_EVENT0_ISET_RXINT_W :: new (self) } # [doc = "Bit 11 - Set UART Transmit Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iset_txint (& mut self) -> INT_EVENT0_ISET_TXINT_W < INT_EVENT0_ISET_SPEC , 11 > { INT_EVENT0_ISET_TXINT_W :: new (self) } # [doc = "Bit 12 - Set UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] # [inline (always)] # [must_use] pub fn int_event0_iset_eot (& mut self) -> INT_EVENT0_ISET_EOT_W < INT_EVENT0_ISET_SPEC , 12 > { INT_EVENT0_ISET_EOT_W :: new (self) } # [doc = "Bit 13 - Set Address Match Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iset_addr_match (& mut self) -> INT_EVENT0_ISET_ADDR_MATCH_W <'_,  INT_EVENT0_ISET_SPEC , 13 > { INT_EVENT0_ISET_ADDR_MATCH_W :: new (self) } # [doc = "Bit 14 - Set UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] # [inline (always)] # [must_use] pub fn int_event0_iset_cts (& mut self) -> INT_EVENT0_ISET_CTS_W < INT_EVENT0_ISET_SPEC , 14 > { INT_EVENT0_ISET_CTS_W :: new (self) } # [doc = "Bit 15 - Set DMA Done on RX Event Channel"] # [inline (always)] # [must_use] pub fn int_event0_iset_dma_done_rx (& mut self) -> INT_EVENT0_ISET_DMA_DONE_RX_W < INT_EVENT0_ISET_SPEC , 15 > { INT_EVENT0_ISET_DMA_DONE_RX_W :: new (self) } # [doc = "Bit 16 - Set DMA Done on TX Event Channel"] # [inline (always)] # [must_use] pub fn int_event0_iset_dma_done_tx (& mut self) -> INT_EVENT0_ISET_DMA_DONE_TX_W < INT_EVENT0_ISET_SPEC , 16 > { INT_EVENT0_ISET_DMA_DONE_TX_W :: new (self) } # [doc = "Bit 17 - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] # [inline (always)] # [must_use] pub fn int_event0_iset_nerr (& mut self) -> INT_EVENT0_ISET_NERR_W < INT_EVENT0_ISET_SPEC , 17 > { INT_EVENT0_ISET_NERR_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Interrupt set\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_event0_iset::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct INT_EVENT0_ISET_SPEC ; impl crate :: RegisterSpec for INT_EVENT0_ISET_SPEC { type Ux = u32 ; } # [doc = "`write(|w| ..)` method takes [`int_event0_iset::W`](W) writer structure"] impl crate :: Writable for INT_EVENT0_ISET_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets INT_EVENT0_ISET to value 0"] impl crate :: Resettable for INT_EVENT0_ISET_SPEC { const RESET_VALUE : Self :: Ux = 0 ; }
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                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                  +++
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing
[INFO] [stdout]  --> src/uart0/int_event0_iset.rs:1:24990
[INFO] [stdout]   |
[INFO] [stdout] 1 | ...ent0_iset_cts (& mut self) -> INT_EVENT0_ISET_CTS_W < INT_EVENT0_ISET_SPEC , 14 > { INT_EVENT0_ISET_CTS_W :: new (self) } # [doc =...
[INFO] [stdout]   |                   ^^^^^^^^^^     ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here
[INFO] [stdout]   |                   |
[INFO] [stdout]   |                   the lifetime is elided here
[INFO] [stdout]   |
[INFO] [stdout]   = help: the same lifetime is referred to in inconsistent ways, making the signature confusing
[INFO] [stdout] help: use `'_` for type paths
[INFO] [stdout]   |
[INFO] [stdout] 1 | # [doc = "Register `INT_EVENT0_ISET` writer"] pub type W = crate :: W < INT_EVENT0_ISET_SPEC > ; # [doc = "Set UARTOUT Receive Time-Out Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_RTOUT_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_RTOUT_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_RTOUT_SET = 1 , } impl From < INT_EVENT0_ISET_RTOUT_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_RTOUT_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_RTOUT` writer - Set UARTOUT Receive Time-Out Interrupt."] pub type INT_EVENT0_ISET_RTOUT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_RTOUT_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_RTOUT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_rtout_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_RTOUT_AW :: INT_EVENT0_ISET_RTOUT_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_rtout_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_RTOUT_AW :: INT_EVENT0_ISET_RTOUT_SET) } } # [doc = "Set UART Framing Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_FRMERR_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_FRMERR_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_FRMERR_SET = 1 , } impl From < INT_EVENT0_ISET_FRMERR_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_FRMERR_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_FRMERR` writer - Set UART Framing Error Interrupt."] pub type INT_EVENT0_ISET_FRMERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_FRMERR_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_FRMERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_frmerr_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_FRMERR_AW :: INT_EVENT0_ISET_FRMERR_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_frmerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_FRMERR_AW :: INT_EVENT0_ISET_FRMERR_SET) } } # [doc = "Set UART Parity Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_PARERR_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_PARERR_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_PARERR_SET = 1 , } impl From < INT_EVENT0_ISET_PARERR_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_PARERR_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_PARERR` writer - Set UART Parity Error Interrupt."] pub type INT_EVENT0_ISET_PARERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_PARERR_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_PARERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_parerr_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_PARERR_AW :: INT_EVENT0_ISET_PARERR_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_parerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_PARERR_AW :: INT_EVENT0_ISET_PARERR_SET) } } # [doc = "Set UART Break Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_BRKERR_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_BRKERR_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_BRKERR_SET = 1 , } impl From < INT_EVENT0_ISET_BRKERR_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_BRKERR_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_BRKERR` writer - Set UART Break Error Interrupt."] pub type INT_EVENT0_ISET_BRKERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_BRKERR_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_BRKERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_brkerr_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_BRKERR_AW :: INT_EVENT0_ISET_BRKERR_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_brkerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_BRKERR_AW :: INT_EVENT0_ISET_BRKERR_SET) } } # [doc = "Set UART Receive Overrun Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_OVRERR_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_OVRERR_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_OVRERR_SET = 1 , } impl From < INT_EVENT0_ISET_OVRERR_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_OVRERR_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_OVRERR` writer - Set UART Receive Overrun Error Interrupt."] pub type INT_EVENT0_ISET_OVRERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_OVRERR_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_OVRERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_ovrerr_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_OVRERR_AW :: INT_EVENT0_ISET_OVRERR_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_ovrerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_OVRERR_AW :: INT_EVENT0_ISET_OVRERR_SET) } } # [doc = "Set Negative Edge on UARTxRXD Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_RXNE_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_RXNE_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_RXNE_SET = 1 , } impl From < INT_EVENT0_ISET_RXNE_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_RXNE_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_RXNE` writer - Set Negative Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_ISET_RXNE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_RXNE_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_RXNE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_rxne_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_RXNE_AW :: INT_EVENT0_ISET_RXNE_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_rxne_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_RXNE_AW :: INT_EVENT0_ISET_RXNE_SET) } } # [doc = "Set Positive Edge on UARTxRXD Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_RXPE_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_RXPE_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_RXPE_SET = 1 , } impl From < INT_EVENT0_ISET_RXPE_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_RXPE_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_RXPE` writer - Set Positive Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_ISET_RXPE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_RXPE_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_RXPE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_rxpe_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_RXPE_AW :: INT_EVENT0_ISET_RXPE_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_rxpe_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_RXPE_AW :: INT_EVENT0_ISET_RXPE_SET) } } # [doc = "Set LIN Capture 0 / Match Interrupt .\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_LINC0_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_LINC0_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_LINC0_SET = 1 , } impl From < INT_EVENT0_ISET_LINC0_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_LINC0_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_LINC0` writer - Set LIN Capture 0 / Match Interrupt ."] pub type INT_EVENT0_ISET_LINC0_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_LINC0_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_LINC0_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_linc0_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_LINC0_AW :: INT_EVENT0_ISET_LINC0_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_linc0_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_LINC0_AW :: INT_EVENT0_ISET_LINC0_SET) } } # [doc = "Set LIN Capture 1 Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_LINC1_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_LINC1_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_LINC1_SET = 1 , } impl From < INT_EVENT0_ISET_LINC1_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_LINC1_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_LINC1` writer - Set LIN Capture 1 Interrupt."] pub type INT_EVENT0_ISET_LINC1_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_LINC1_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_LINC1_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_linc1_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_LINC1_AW :: INT_EVENT0_ISET_LINC1_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_linc1_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_LINC1_AW :: INT_EVENT0_ISET_LINC1_SET) } } # [doc = "Set LIN Hardware Counter Overflow Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_LINOVF_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_LINOVF_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_LINOVF_SET = 1 , } impl From < INT_EVENT0_ISET_LINOVF_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_LINOVF_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_LINOVF` writer - Set LIN Hardware Counter Overflow Interrupt."] pub type INT_EVENT0_ISET_LINOVF_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_LINOVF_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_LINOVF_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_linovf_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_LINOVF_AW :: INT_EVENT0_ISET_LINOVF_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_linovf_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_LINOVF_AW :: INT_EVENT0_ISET_LINOVF_SET) } } # [doc = "Set UART Receive Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_RXINT_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_RXINT_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_RXINT_SET = 1 , } impl From < INT_EVENT0_ISET_RXINT_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_RXINT_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_RXINT` writer - Set UART Receive Interrupt."] pub type INT_EVENT0_ISET_RXINT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_RXINT_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_RXINT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_rxint_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_RXINT_AW :: INT_EVENT0_ISET_RXINT_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_rxint_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_RXINT_AW :: INT_EVENT0_ISET_RXINT_SET) } } # [doc = "Set UART Transmit Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_TXINT_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_TXINT_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_TXINT_SET = 1 , } impl From < INT_EVENT0_ISET_TXINT_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_TXINT_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_TXINT` writer - Set UART Transmit Interrupt."] pub type INT_EVENT0_ISET_TXINT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_TXINT_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_TXINT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_txint_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_TXINT_AW :: INT_EVENT0_ISET_TXINT_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_txint_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_TXINT_AW :: INT_EVENT0_ISET_TXINT_SET) } } # [doc = "Set UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_EOT_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_EOT_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_EOT_SET = 1 , } impl From < INT_EVENT0_ISET_EOT_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_EOT_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_EOT` writer - Set UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] pub type INT_EVENT0_ISET_EOT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_EOT_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_EOT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_eot_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_EOT_AW :: INT_EVENT0_ISET_EOT_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_eot_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_EOT_AW :: INT_EVENT0_ISET_EOT_SET) } } # [doc = "Set Address Match Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_ADDR_MATCH_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_ADDR_MATCH_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_ADDR_MATCH_SET = 1 , } impl From < INT_EVENT0_ISET_ADDR_MATCH_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_ADDR_MATCH_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_ADDR_MATCH` writer - Set Address Match Interrupt."] pub type INT_EVENT0_ISET_ADDR_MATCH_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_ADDR_MATCH_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_ADDR_MATCH_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_addr_match_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_ADDR_MATCH_AW :: INT_EVENT0_ISET_ADDR_MATCH_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_addr_match_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_ADDR_MATCH_AW :: INT_EVENT0_ISET_ADDR_MATCH_SET) } } # [doc = "Set UART Clear to Send Modem Interrupt. 0 = Interrupt disabled\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_CTS_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_CTS_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_CTS_SET = 1 , } impl From < INT_EVENT0_ISET_CTS_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_CTS_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_CTS` writer - Set UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] pub type INT_EVENT0_ISET_CTS_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_CTS_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_CTS_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_cts_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_CTS_AW :: INT_EVENT0_ISET_CTS_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_cts_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_CTS_AW :: INT_EVENT0_ISET_CTS_SET) } } # [doc = "Set DMA Done on RX Event Channel\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_DMA_DONE_RX_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_DMA_DONE_RX_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_DMA_DONE_RX_SET = 1 , } impl From < INT_EVENT0_ISET_DMA_DONE_RX_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_DMA_DONE_RX_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_DMA_DONE_RX` writer - Set DMA Done on RX Event Channel"] pub type INT_EVENT0_ISET_DMA_DONE_RX_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_DMA_DONE_RX_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_DMA_DONE_RX_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_dma_done_rx_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_DMA_DONE_RX_AW :: INT_EVENT0_ISET_DMA_DONE_RX_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_dma_done_rx_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_DMA_DONE_RX_AW :: INT_EVENT0_ISET_DMA_DONE_RX_SET) } } # [doc = "Set DMA Done on TX Event Channel\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_DMA_DONE_TX_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_DMA_DONE_TX_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_DMA_DONE_TX_SET = 1 , } impl From < INT_EVENT0_ISET_DMA_DONE_TX_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_DMA_DONE_TX_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_DMA_DONE_TX` writer - Set DMA Done on TX Event Channel"] pub type INT_EVENT0_ISET_DMA_DONE_TX_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_DMA_DONE_TX_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_DMA_DONE_TX_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_dma_done_tx_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_DMA_DONE_TX_AW :: INT_EVENT0_ISET_DMA_DONE_TX_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_dma_done_tx_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_DMA_DONE_TX_AW :: INT_EVENT0_ISET_DMA_DONE_TX_SET) } } # [doc = "Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_NERR_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_NERR_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_NERR_SET = 1 , } impl From < INT_EVENT0_ISET_NERR_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_NERR_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_NERR` writer - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] pub type INT_EVENT0_ISET_NERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_NERR_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_NERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_nerr_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_NERR_AW :: INT_EVENT0_ISET_NERR_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_nerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_NERR_AW :: INT_EVENT0_ISET_NERR_SET) } } impl W { # [doc = "Bit 0 - Set UARTOUT Receive Time-Out Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iset_rtout (& mut self) -> INT_EVENT0_ISET_RTOUT_W < INT_EVENT0_ISET_SPEC , 0 > { INT_EVENT0_ISET_RTOUT_W :: new (self) } # [doc = "Bit 1 - Set UART Framing Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iset_frmerr (& mut self) -> INT_EVENT0_ISET_FRMERR_W < INT_EVENT0_ISET_SPEC , 1 > { INT_EVENT0_ISET_FRMERR_W :: new (self) } # [doc = "Bit 2 - Set UART Parity Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iset_parerr (& mut self) -> INT_EVENT0_ISET_PARERR_W < INT_EVENT0_ISET_SPEC , 2 > { INT_EVENT0_ISET_PARERR_W :: new (self) } # [doc = "Bit 3 - Set UART Break Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iset_brkerr (& mut self) -> INT_EVENT0_ISET_BRKERR_W < INT_EVENT0_ISET_SPEC , 3 > { INT_EVENT0_ISET_BRKERR_W :: new (self) } # [doc = "Bit 4 - Set UART Receive Overrun Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iset_ovrerr (& mut self) -> INT_EVENT0_ISET_OVRERR_W < INT_EVENT0_ISET_SPEC , 4 > { INT_EVENT0_ISET_OVRERR_W :: new (self) } # [doc = "Bit 5 - Set Negative Edge on UARTxRXD Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iset_rxne (& mut self) -> INT_EVENT0_ISET_RXNE_W < INT_EVENT0_ISET_SPEC , 5 > { INT_EVENT0_ISET_RXNE_W :: new (self) } # [doc = "Bit 6 - Set Positive Edge on UARTxRXD Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iset_rxpe (& mut self) -> INT_EVENT0_ISET_RXPE_W < INT_EVENT0_ISET_SPEC , 6 > { INT_EVENT0_ISET_RXPE_W :: new (self) } # [doc = "Bit 7 - Set LIN Capture 0 / Match Interrupt ."] # [inline (always)] # [must_use] pub fn int_event0_iset_linc0 (& mut self) -> INT_EVENT0_ISET_LINC0_W < INT_EVENT0_ISET_SPEC , 7 > { INT_EVENT0_ISET_LINC0_W :: new (self) } # [doc = "Bit 8 - Set LIN Capture 1 Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iset_linc1 (& mut self) -> INT_EVENT0_ISET_LINC1_W < INT_EVENT0_ISET_SPEC , 8 > { INT_EVENT0_ISET_LINC1_W :: new (self) } # [doc = "Bit 9 - Set LIN Hardware Counter Overflow Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iset_linovf (& mut self) -> INT_EVENT0_ISET_LINOVF_W < INT_EVENT0_ISET_SPEC , 9 > { INT_EVENT0_ISET_LINOVF_W :: new (self) } # [doc = "Bit 10 - Set UART Receive Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iset_rxint (& mut self) -> INT_EVENT0_ISET_RXINT_W < INT_EVENT0_ISET_SPEC , 10 > { INT_EVENT0_ISET_RXINT_W :: new (self) } # [doc = "Bit 11 - Set UART Transmit Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iset_txint (& mut self) -> INT_EVENT0_ISET_TXINT_W < INT_EVENT0_ISET_SPEC , 11 > { INT_EVENT0_ISET_TXINT_W :: new (self) } # [doc = "Bit 12 - Set UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] # [inline (always)] # [must_use] pub fn int_event0_iset_eot (& mut self) -> INT_EVENT0_ISET_EOT_W < INT_EVENT0_ISET_SPEC , 12 > { INT_EVENT0_ISET_EOT_W :: new (self) } # [doc = "Bit 13 - Set Address Match Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iset_addr_match (& mut self) -> INT_EVENT0_ISET_ADDR_MATCH_W < INT_EVENT0_ISET_SPEC , 13 > { INT_EVENT0_ISET_ADDR_MATCH_W :: new (self) } # [doc = "Bit 14 - Set UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] # [inline (always)] # [must_use] pub fn int_event0_iset_cts (& mut self) -> INT_EVENT0_ISET_CTS_W <'_,  INT_EVENT0_ISET_SPEC , 14 > { INT_EVENT0_ISET_CTS_W :: new (self) } # [doc = "Bit 15 - Set DMA Done on RX Event Channel"] # [inline (always)] # [must_use] pub fn int_event0_iset_dma_done_rx (& mut self) -> INT_EVENT0_ISET_DMA_DONE_RX_W < INT_EVENT0_ISET_SPEC , 15 > { INT_EVENT0_ISET_DMA_DONE_RX_W :: new (self) } # [doc = "Bit 16 - Set DMA Done on TX Event Channel"] # [inline (always)] # [must_use] pub fn int_event0_iset_dma_done_tx (& mut self) -> INT_EVENT0_ISET_DMA_DONE_TX_W < INT_EVENT0_ISET_SPEC , 16 > { INT_EVENT0_ISET_DMA_DONE_TX_W :: new (self) } # [doc = "Bit 17 - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] # [inline (always)] # [must_use] pub fn int_event0_iset_nerr (& mut self) -> INT_EVENT0_ISET_NERR_W < INT_EVENT0_ISET_SPEC , 17 > { INT_EVENT0_ISET_NERR_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Interrupt set\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_event0_iset::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct INT_EVENT0_ISET_SPEC ; impl crate :: RegisterSpec for INT_EVENT0_ISET_SPEC { type Ux = u32 ; } # [doc = "`write(|w| ..)` method takes [`int_event0_iset::W`](W) writer structure"] impl crate :: Writable for INT_EVENT0_ISET_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets INT_EVENT0_ISET to value 0"] impl crate :: Resettable for INT_EVENT0_ISET_SPEC { const RESET_VALUE : Self :: Ux = 0 ; }
[INFO] [stdout]   |                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                    +++
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing
[INFO] [stdout]  --> src/uart0/int_event0_iset.rs:1:25220
[INFO] [stdout]   |
[INFO] [stdout] 1 | ...a_done_rx (& mut self) -> INT_EVENT0_ISET_DMA_DONE_RX_W < INT_EVENT0_ISET_SPEC , 15 > { INT_EVENT0_ISET_DMA_DONE_RX_W :: new (self...
[INFO] [stdout]   |               ^^^^^^^^^^     ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here
[INFO] [stdout]   |               |
[INFO] [stdout]   |               the lifetime is elided here
[INFO] [stdout]   |
[INFO] [stdout]   = help: the same lifetime is referred to in inconsistent ways, making the signature confusing
[INFO] [stdout] help: use `'_` for type paths
[INFO] [stdout]   |
[INFO] [stdout] 1 | # [doc = "Register `INT_EVENT0_ISET` writer"] pub type W = crate :: W < INT_EVENT0_ISET_SPEC > ; # [doc = "Set UARTOUT Receive Time-Out Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_RTOUT_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_RTOUT_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_RTOUT_SET = 1 , } impl From < INT_EVENT0_ISET_RTOUT_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_RTOUT_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_RTOUT` writer - Set UARTOUT Receive Time-Out Interrupt."] pub type INT_EVENT0_ISET_RTOUT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_RTOUT_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_RTOUT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_rtout_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_RTOUT_AW :: INT_EVENT0_ISET_RTOUT_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_rtout_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_RTOUT_AW :: INT_EVENT0_ISET_RTOUT_SET) } } # [doc = "Set UART Framing Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_FRMERR_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_FRMERR_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_FRMERR_SET = 1 , } impl From < INT_EVENT0_ISET_FRMERR_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_FRMERR_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_FRMERR` writer - Set UART Framing Error Interrupt."] pub type INT_EVENT0_ISET_FRMERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_FRMERR_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_FRMERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_frmerr_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_FRMERR_AW :: INT_EVENT0_ISET_FRMERR_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_frmerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_FRMERR_AW :: INT_EVENT0_ISET_FRMERR_SET) } } # [doc = "Set UART Parity Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_PARERR_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_PARERR_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_PARERR_SET = 1 , } impl From < INT_EVENT0_ISET_PARERR_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_PARERR_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_PARERR` writer - Set UART Parity Error Interrupt."] pub type INT_EVENT0_ISET_PARERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_PARERR_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_PARERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_parerr_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_PARERR_AW :: INT_EVENT0_ISET_PARERR_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_parerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_PARERR_AW :: INT_EVENT0_ISET_PARERR_SET) } } # [doc = "Set UART Break Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_BRKERR_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_BRKERR_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_BRKERR_SET = 1 , } impl From < INT_EVENT0_ISET_BRKERR_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_BRKERR_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_BRKERR` writer - Set UART Break Error Interrupt."] pub type INT_EVENT0_ISET_BRKERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_BRKERR_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_BRKERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_brkerr_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_BRKERR_AW :: INT_EVENT0_ISET_BRKERR_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_brkerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_BRKERR_AW :: INT_EVENT0_ISET_BRKERR_SET) } } # [doc = "Set UART Receive Overrun Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_OVRERR_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_OVRERR_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_OVRERR_SET = 1 , } impl From < INT_EVENT0_ISET_OVRERR_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_OVRERR_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_OVRERR` writer - Set UART Receive Overrun Error Interrupt."] pub type INT_EVENT0_ISET_OVRERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_OVRERR_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_OVRERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_ovrerr_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_OVRERR_AW :: INT_EVENT0_ISET_OVRERR_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_ovrerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_OVRERR_AW :: INT_EVENT0_ISET_OVRERR_SET) } } # [doc = "Set Negative Edge on UARTxRXD Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_RXNE_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_RXNE_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_RXNE_SET = 1 , } impl From < INT_EVENT0_ISET_RXNE_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_RXNE_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_RXNE` writer - Set Negative Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_ISET_RXNE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_RXNE_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_RXNE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_rxne_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_RXNE_AW :: INT_EVENT0_ISET_RXNE_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_rxne_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_RXNE_AW :: INT_EVENT0_ISET_RXNE_SET) } } # [doc = "Set Positive Edge on UARTxRXD Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_RXPE_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_RXPE_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_RXPE_SET = 1 , } impl From < INT_EVENT0_ISET_RXPE_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_RXPE_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_RXPE` writer - Set Positive Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_ISET_RXPE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_RXPE_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_RXPE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_rxpe_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_RXPE_AW :: INT_EVENT0_ISET_RXPE_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_rxpe_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_RXPE_AW :: INT_EVENT0_ISET_RXPE_SET) } } # [doc = "Set LIN Capture 0 / Match Interrupt .\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_LINC0_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_LINC0_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_LINC0_SET = 1 , } impl From < INT_EVENT0_ISET_LINC0_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_LINC0_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_LINC0` writer - Set LIN Capture 0 / Match Interrupt ."] pub type INT_EVENT0_ISET_LINC0_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_LINC0_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_LINC0_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_linc0_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_LINC0_AW :: INT_EVENT0_ISET_LINC0_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_linc0_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_LINC0_AW :: INT_EVENT0_ISET_LINC0_SET) } } # [doc = "Set LIN Capture 1 Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_LINC1_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_LINC1_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_LINC1_SET = 1 , } impl From < INT_EVENT0_ISET_LINC1_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_LINC1_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_LINC1` writer - Set LIN Capture 1 Interrupt."] pub type INT_EVENT0_ISET_LINC1_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_LINC1_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_LINC1_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_linc1_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_LINC1_AW :: INT_EVENT0_ISET_LINC1_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_linc1_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_LINC1_AW :: INT_EVENT0_ISET_LINC1_SET) } } # [doc = "Set LIN Hardware Counter Overflow Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_LINOVF_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_LINOVF_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_LINOVF_SET = 1 , } impl From < INT_EVENT0_ISET_LINOVF_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_LINOVF_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_LINOVF` writer - Set LIN Hardware Counter Overflow Interrupt."] pub type INT_EVENT0_ISET_LINOVF_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_LINOVF_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_LINOVF_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_linovf_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_LINOVF_AW :: INT_EVENT0_ISET_LINOVF_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_linovf_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_LINOVF_AW :: INT_EVENT0_ISET_LINOVF_SET) } } # [doc = "Set UART Receive Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_RXINT_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_RXINT_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_RXINT_SET = 1 , } impl From < INT_EVENT0_ISET_RXINT_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_RXINT_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_RXINT` writer - Set UART Receive Interrupt."] pub type INT_EVENT0_ISET_RXINT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_RXINT_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_RXINT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_rxint_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_RXINT_AW :: INT_EVENT0_ISET_RXINT_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_rxint_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_RXINT_AW :: INT_EVENT0_ISET_RXINT_SET) } } # [doc = "Set UART Transmit Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_TXINT_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_TXINT_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_TXINT_SET = 1 , } impl From < INT_EVENT0_ISET_TXINT_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_TXINT_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_TXINT` writer - Set UART Transmit Interrupt."] pub type INT_EVENT0_ISET_TXINT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_TXINT_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_TXINT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_txint_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_TXINT_AW :: INT_EVENT0_ISET_TXINT_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_txint_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_TXINT_AW :: INT_EVENT0_ISET_TXINT_SET) } } # [doc = "Set UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_EOT_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_EOT_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_EOT_SET = 1 , } impl From < INT_EVENT0_ISET_EOT_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_EOT_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_EOT` writer - Set UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] pub type INT_EVENT0_ISET_EOT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_EOT_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_EOT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_eot_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_EOT_AW :: INT_EVENT0_ISET_EOT_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_eot_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_EOT_AW :: INT_EVENT0_ISET_EOT_SET) } } # [doc = "Set Address Match Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_ADDR_MATCH_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_ADDR_MATCH_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_ADDR_MATCH_SET = 1 , } impl From < INT_EVENT0_ISET_ADDR_MATCH_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_ADDR_MATCH_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_ADDR_MATCH` writer - Set Address Match Interrupt."] pub type INT_EVENT0_ISET_ADDR_MATCH_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_ADDR_MATCH_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_ADDR_MATCH_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_addr_match_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_ADDR_MATCH_AW :: INT_EVENT0_ISET_ADDR_MATCH_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_addr_match_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_ADDR_MATCH_AW :: INT_EVENT0_ISET_ADDR_MATCH_SET) } } # [doc = "Set UART Clear to Send Modem Interrupt. 0 = Interrupt disabled\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_CTS_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_CTS_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_CTS_SET = 1 , } impl From < INT_EVENT0_ISET_CTS_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_CTS_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_CTS` writer - Set UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] pub type INT_EVENT0_ISET_CTS_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_CTS_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_CTS_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_cts_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_CTS_AW :: INT_EVENT0_ISET_CTS_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_cts_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_CTS_AW :: INT_EVENT0_ISET_CTS_SET) } } # [doc = "Set DMA Done on RX Event Channel\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_DMA_DONE_RX_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_DMA_DONE_RX_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_DMA_DONE_RX_SET = 1 , } impl From < INT_EVENT0_ISET_DMA_DONE_RX_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_DMA_DONE_RX_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_DMA_DONE_RX` writer - Set DMA Done on RX Event Channel"] pub type INT_EVENT0_ISET_DMA_DONE_RX_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_DMA_DONE_RX_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_DMA_DONE_RX_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_dma_done_rx_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_DMA_DONE_RX_AW :: INT_EVENT0_ISET_DMA_DONE_RX_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_dma_done_rx_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_DMA_DONE_RX_AW :: INT_EVENT0_ISET_DMA_DONE_RX_SET) } } # [doc = "Set DMA Done on TX Event Channel\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_DMA_DONE_TX_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_DMA_DONE_TX_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_DMA_DONE_TX_SET = 1 , } impl From < INT_EVENT0_ISET_DMA_DONE_TX_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_DMA_DONE_TX_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_DMA_DONE_TX` writer - Set DMA Done on TX Event Channel"] pub type INT_EVENT0_ISET_DMA_DONE_TX_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_DMA_DONE_TX_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_DMA_DONE_TX_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_dma_done_tx_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_DMA_DONE_TX_AW :: INT_EVENT0_ISET_DMA_DONE_TX_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_dma_done_tx_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_DMA_DONE_TX_AW :: INT_EVENT0_ISET_DMA_DONE_TX_SET) } } # [doc = "Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_NERR_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_NERR_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_NERR_SET = 1 , } impl From < INT_EVENT0_ISET_NERR_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_NERR_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_NERR` writer - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] pub type INT_EVENT0_ISET_NERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_NERR_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_NERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_nerr_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_NERR_AW :: INT_EVENT0_ISET_NERR_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_nerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_NERR_AW :: INT_EVENT0_ISET_NERR_SET) } } impl W { # [doc = "Bit 0 - Set UARTOUT Receive Time-Out Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iset_rtout (& mut self) -> INT_EVENT0_ISET_RTOUT_W < INT_EVENT0_ISET_SPEC , 0 > { INT_EVENT0_ISET_RTOUT_W :: new (self) } # [doc = "Bit 1 - Set UART Framing Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iset_frmerr (& mut self) -> INT_EVENT0_ISET_FRMERR_W < INT_EVENT0_ISET_SPEC , 1 > { INT_EVENT0_ISET_FRMERR_W :: new (self) } # [doc = "Bit 2 - Set UART Parity Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iset_parerr (& mut self) -> INT_EVENT0_ISET_PARERR_W < INT_EVENT0_ISET_SPEC , 2 > { INT_EVENT0_ISET_PARERR_W :: new (self) } # [doc = "Bit 3 - Set UART Break Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iset_brkerr (& mut self) -> INT_EVENT0_ISET_BRKERR_W < INT_EVENT0_ISET_SPEC , 3 > { INT_EVENT0_ISET_BRKERR_W :: new (self) } # [doc = "Bit 4 - Set UART Receive Overrun Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iset_ovrerr (& mut self) -> INT_EVENT0_ISET_OVRERR_W < INT_EVENT0_ISET_SPEC , 4 > { INT_EVENT0_ISET_OVRERR_W :: new (self) } # [doc = "Bit 5 - Set Negative Edge on UARTxRXD Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iset_rxne (& mut self) -> INT_EVENT0_ISET_RXNE_W < INT_EVENT0_ISET_SPEC , 5 > { INT_EVENT0_ISET_RXNE_W :: new (self) } # [doc = "Bit 6 - Set Positive Edge on UARTxRXD Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iset_rxpe (& mut self) -> INT_EVENT0_ISET_RXPE_W < INT_EVENT0_ISET_SPEC , 6 > { INT_EVENT0_ISET_RXPE_W :: new (self) } # [doc = "Bit 7 - Set LIN Capture 0 / Match Interrupt ."] # [inline (always)] # [must_use] pub fn int_event0_iset_linc0 (& mut self) -> INT_EVENT0_ISET_LINC0_W < INT_EVENT0_ISET_SPEC , 7 > { INT_EVENT0_ISET_LINC0_W :: new (self) } # [doc = "Bit 8 - Set LIN Capture 1 Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iset_linc1 (& mut self) -> INT_EVENT0_ISET_LINC1_W < INT_EVENT0_ISET_SPEC , 8 > { INT_EVENT0_ISET_LINC1_W :: new (self) } # [doc = "Bit 9 - Set LIN Hardware Counter Overflow Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iset_linovf (& mut self) -> INT_EVENT0_ISET_LINOVF_W < INT_EVENT0_ISET_SPEC , 9 > { INT_EVENT0_ISET_LINOVF_W :: new (self) } # [doc = "Bit 10 - Set UART Receive Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iset_rxint (& mut self) -> INT_EVENT0_ISET_RXINT_W < INT_EVENT0_ISET_SPEC , 10 > { INT_EVENT0_ISET_RXINT_W :: new (self) } # [doc = "Bit 11 - Set UART Transmit Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iset_txint (& mut self) -> INT_EVENT0_ISET_TXINT_W < INT_EVENT0_ISET_SPEC , 11 > { INT_EVENT0_ISET_TXINT_W :: new (self) } # [doc = "Bit 12 - Set UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] # [inline (always)] # [must_use] pub fn int_event0_iset_eot (& mut self) -> INT_EVENT0_ISET_EOT_W < INT_EVENT0_ISET_SPEC , 12 > { INT_EVENT0_ISET_EOT_W :: new (self) } # [doc = "Bit 13 - Set Address Match Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iset_addr_match (& mut self) -> INT_EVENT0_ISET_ADDR_MATCH_W < INT_EVENT0_ISET_SPEC , 13 > { INT_EVENT0_ISET_ADDR_MATCH_W :: new (self) } # [doc = "Bit 14 - Set UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] # [inline (always)] # [must_use] pub fn int_event0_iset_cts (& mut self) -> INT_EVENT0_ISET_CTS_W < INT_EVENT0_ISET_SPEC , 14 > { INT_EVENT0_ISET_CTS_W :: new (self) } # [doc = "Bit 15 - Set DMA Done on RX Event Channel"] # [inline (always)] # [must_use] pub fn int_event0_iset_dma_done_rx (& mut self) -> INT_EVENT0_ISET_DMA_DONE_RX_W <'_,  INT_EVENT0_ISET_SPEC , 15 > { INT_EVENT0_ISET_DMA_DONE_RX_W :: new (self) } # [doc = "Bit 16 - Set DMA Done on TX Event Channel"] # [inline (always)] # [must_use] pub fn int_event0_iset_dma_done_tx (& mut self) -> INT_EVENT0_ISET_DMA_DONE_TX_W < INT_EVENT0_ISET_SPEC , 16 > { INT_EVENT0_ISET_DMA_DONE_TX_W :: new (self) } # [doc = "Bit 17 - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] # [inline (always)] # [must_use] pub fn int_event0_iset_nerr (& mut self) -> INT_EVENT0_ISET_NERR_W < INT_EVENT0_ISET_SPEC , 17 > { INT_EVENT0_ISET_NERR_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Interrupt set\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_event0_iset::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct INT_EVENT0_ISET_SPEC ; impl crate :: RegisterSpec for INT_EVENT0_ISET_SPEC { type Ux = u32 ; } # [doc = "`write(|w| ..)` method takes [`int_event0_iset::W`](W) writer structure"] impl crate :: Writable for INT_EVENT0_ISET_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets INT_EVENT0_ISET to value 0"] impl crate :: Resettable for INT_EVENT0_ISET_SPEC { const RESET_VALUE : Self :: Ux = 0 ; }
[INFO] [stdout]   |                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                  +++
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing
[INFO] [stdout]  --> src/uart0/int_event0_iset.rs:1:25466
[INFO] [stdout]   |
[INFO] [stdout] 1 | ...a_done_tx (& mut self) -> INT_EVENT0_ISET_DMA_DONE_TX_W < INT_EVENT0_ISET_SPEC , 16 > { INT_EVENT0_ISET_DMA_DONE_TX_W :: new (self...
[INFO] [stdout]   |               ^^^^^^^^^^     ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here
[INFO] [stdout]   |               |
[INFO] [stdout]   |               the lifetime is elided here
[INFO] [stdout]   |
[INFO] [stdout]   = help: the same lifetime is referred to in inconsistent ways, making the signature confusing
[INFO] [stdout] help: use `'_` for type paths
[INFO] [stdout]   |
[INFO] [stdout] 1 | # [doc = "Register `INT_EVENT0_ISET` writer"] pub type W = crate :: W < INT_EVENT0_ISET_SPEC > ; # [doc = "Set UARTOUT Receive Time-Out Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_RTOUT_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_RTOUT_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_RTOUT_SET = 1 , } impl From < INT_EVENT0_ISET_RTOUT_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_RTOUT_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_RTOUT` writer - Set UARTOUT Receive Time-Out Interrupt."] pub type INT_EVENT0_ISET_RTOUT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_RTOUT_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_RTOUT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_rtout_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_RTOUT_AW :: INT_EVENT0_ISET_RTOUT_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_rtout_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_RTOUT_AW :: INT_EVENT0_ISET_RTOUT_SET) } } # [doc = "Set UART Framing Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_FRMERR_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_FRMERR_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_FRMERR_SET = 1 , } impl From < INT_EVENT0_ISET_FRMERR_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_FRMERR_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_FRMERR` writer - Set UART Framing Error Interrupt."] pub type INT_EVENT0_ISET_FRMERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_FRMERR_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_FRMERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_frmerr_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_FRMERR_AW :: INT_EVENT0_ISET_FRMERR_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_frmerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_FRMERR_AW :: INT_EVENT0_ISET_FRMERR_SET) } } # [doc = "Set UART Parity Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_PARERR_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_PARERR_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_PARERR_SET = 1 , } impl From < INT_EVENT0_ISET_PARERR_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_PARERR_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_PARERR` writer - Set UART Parity Error Interrupt."] pub type INT_EVENT0_ISET_PARERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_PARERR_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_PARERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_parerr_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_PARERR_AW :: INT_EVENT0_ISET_PARERR_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_parerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_PARERR_AW :: INT_EVENT0_ISET_PARERR_SET) } } # [doc = "Set UART Break Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_BRKERR_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_BRKERR_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_BRKERR_SET = 1 , } impl From < INT_EVENT0_ISET_BRKERR_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_BRKERR_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_BRKERR` writer - Set UART Break Error Interrupt."] pub type INT_EVENT0_ISET_BRKERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_BRKERR_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_BRKERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_brkerr_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_BRKERR_AW :: INT_EVENT0_ISET_BRKERR_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_brkerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_BRKERR_AW :: INT_EVENT0_ISET_BRKERR_SET) } } # [doc = "Set UART Receive Overrun Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_OVRERR_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_OVRERR_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_OVRERR_SET = 1 , } impl From < INT_EVENT0_ISET_OVRERR_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_OVRERR_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_OVRERR` writer - Set UART Receive Overrun Error Interrupt."] pub type INT_EVENT0_ISET_OVRERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_OVRERR_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_OVRERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_ovrerr_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_OVRERR_AW :: INT_EVENT0_ISET_OVRERR_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_ovrerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_OVRERR_AW :: INT_EVENT0_ISET_OVRERR_SET) } } # [doc = "Set Negative Edge on UARTxRXD Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_RXNE_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_RXNE_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_RXNE_SET = 1 , } impl From < INT_EVENT0_ISET_RXNE_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_RXNE_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_RXNE` writer - Set Negative Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_ISET_RXNE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_RXNE_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_RXNE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_rxne_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_RXNE_AW :: INT_EVENT0_ISET_RXNE_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_rxne_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_RXNE_AW :: INT_EVENT0_ISET_RXNE_SET) } } # [doc = "Set Positive Edge on UARTxRXD Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_RXPE_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_RXPE_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_RXPE_SET = 1 , } impl From < INT_EVENT0_ISET_RXPE_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_RXPE_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_RXPE` writer - Set Positive Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_ISET_RXPE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_RXPE_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_RXPE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_rxpe_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_RXPE_AW :: INT_EVENT0_ISET_RXPE_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_rxpe_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_RXPE_AW :: INT_EVENT0_ISET_RXPE_SET) } } # [doc = "Set LIN Capture 0 / Match Interrupt .\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_LINC0_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_LINC0_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_LINC0_SET = 1 , } impl From < INT_EVENT0_ISET_LINC0_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_LINC0_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_LINC0` writer - Set LIN Capture 0 / Match Interrupt ."] pub type INT_EVENT0_ISET_LINC0_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_LINC0_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_LINC0_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_linc0_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_LINC0_AW :: INT_EVENT0_ISET_LINC0_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_linc0_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_LINC0_AW :: INT_EVENT0_ISET_LINC0_SET) } } # [doc = "Set LIN Capture 1 Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_LINC1_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_LINC1_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_LINC1_SET = 1 , } impl From < INT_EVENT0_ISET_LINC1_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_LINC1_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_LINC1` writer - Set LIN Capture 1 Interrupt."] pub type INT_EVENT0_ISET_LINC1_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_LINC1_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_LINC1_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_linc1_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_LINC1_AW :: INT_EVENT0_ISET_LINC1_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_linc1_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_LINC1_AW :: INT_EVENT0_ISET_LINC1_SET) } } # [doc = "Set LIN Hardware Counter Overflow Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_LINOVF_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_LINOVF_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_LINOVF_SET = 1 , } impl From < INT_EVENT0_ISET_LINOVF_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_LINOVF_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_LINOVF` writer - Set LIN Hardware Counter Overflow Interrupt."] pub type INT_EVENT0_ISET_LINOVF_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_LINOVF_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_LINOVF_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_linovf_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_LINOVF_AW :: INT_EVENT0_ISET_LINOVF_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_linovf_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_LINOVF_AW :: INT_EVENT0_ISET_LINOVF_SET) } } # [doc = "Set UART Receive Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_RXINT_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_RXINT_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_RXINT_SET = 1 , } impl From < INT_EVENT0_ISET_RXINT_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_RXINT_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_RXINT` writer - Set UART Receive Interrupt."] pub type INT_EVENT0_ISET_RXINT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_RXINT_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_RXINT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_rxint_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_RXINT_AW :: INT_EVENT0_ISET_RXINT_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_rxint_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_RXINT_AW :: INT_EVENT0_ISET_RXINT_SET) } } # [doc = "Set UART Transmit Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_TXINT_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_TXINT_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_TXINT_SET = 1 , } impl From < INT_EVENT0_ISET_TXINT_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_TXINT_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_TXINT` writer - Set UART Transmit Interrupt."] pub type INT_EVENT0_ISET_TXINT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_TXINT_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_TXINT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_txint_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_TXINT_AW :: INT_EVENT0_ISET_TXINT_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_txint_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_TXINT_AW :: INT_EVENT0_ISET_TXINT_SET) } } # [doc = "Set UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_EOT_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_EOT_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_EOT_SET = 1 , } impl From < INT_EVENT0_ISET_EOT_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_EOT_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_EOT` writer - Set UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] pub type INT_EVENT0_ISET_EOT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_EOT_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_EOT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_eot_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_EOT_AW :: INT_EVENT0_ISET_EOT_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_eot_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_EOT_AW :: INT_EVENT0_ISET_EOT_SET) } } # [doc = "Set Address Match Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_ADDR_MATCH_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_ADDR_MATCH_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_ADDR_MATCH_SET = 1 , } impl From < INT_EVENT0_ISET_ADDR_MATCH_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_ADDR_MATCH_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_ADDR_MATCH` writer - Set Address Match Interrupt."] pub type INT_EVENT0_ISET_ADDR_MATCH_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_ADDR_MATCH_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_ADDR_MATCH_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_addr_match_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_ADDR_MATCH_AW :: INT_EVENT0_ISET_ADDR_MATCH_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_addr_match_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_ADDR_MATCH_AW :: INT_EVENT0_ISET_ADDR_MATCH_SET) } } # [doc = "Set UART Clear to Send Modem Interrupt. 0 = Interrupt disabled\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_CTS_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_CTS_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_CTS_SET = 1 , } impl From < INT_EVENT0_ISET_CTS_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_CTS_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_CTS` writer - Set UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] pub type INT_EVENT0_ISET_CTS_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_CTS_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_CTS_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_cts_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_CTS_AW :: INT_EVENT0_ISET_CTS_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_cts_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_CTS_AW :: INT_EVENT0_ISET_CTS_SET) } } # [doc = "Set DMA Done on RX Event Channel\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_DMA_DONE_RX_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_DMA_DONE_RX_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_DMA_DONE_RX_SET = 1 , } impl From < INT_EVENT0_ISET_DMA_DONE_RX_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_DMA_DONE_RX_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_DMA_DONE_RX` writer - Set DMA Done on RX Event Channel"] pub type INT_EVENT0_ISET_DMA_DONE_RX_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_DMA_DONE_RX_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_DMA_DONE_RX_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_dma_done_rx_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_DMA_DONE_RX_AW :: INT_EVENT0_ISET_DMA_DONE_RX_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_dma_done_rx_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_DMA_DONE_RX_AW :: INT_EVENT0_ISET_DMA_DONE_RX_SET) } } # [doc = "Set DMA Done on TX Event Channel\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_DMA_DONE_TX_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_DMA_DONE_TX_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_DMA_DONE_TX_SET = 1 , } impl From < INT_EVENT0_ISET_DMA_DONE_TX_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_DMA_DONE_TX_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_DMA_DONE_TX` writer - Set DMA Done on TX Event Channel"] pub type INT_EVENT0_ISET_DMA_DONE_TX_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_DMA_DONE_TX_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_DMA_DONE_TX_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_dma_done_tx_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_DMA_DONE_TX_AW :: INT_EVENT0_ISET_DMA_DONE_TX_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_dma_done_tx_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_DMA_DONE_TX_AW :: INT_EVENT0_ISET_DMA_DONE_TX_SET) } } # [doc = "Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_NERR_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_NERR_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_NERR_SET = 1 , } impl From < INT_EVENT0_ISET_NERR_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_NERR_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_NERR` writer - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] pub type INT_EVENT0_ISET_NERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_NERR_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_NERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_nerr_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_NERR_AW :: INT_EVENT0_ISET_NERR_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_nerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_NERR_AW :: INT_EVENT0_ISET_NERR_SET) } } impl W { # [doc = "Bit 0 - Set UARTOUT Receive Time-Out Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iset_rtout (& mut self) -> INT_EVENT0_ISET_RTOUT_W < INT_EVENT0_ISET_SPEC , 0 > { INT_EVENT0_ISET_RTOUT_W :: new (self) } # [doc = "Bit 1 - Set UART Framing Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iset_frmerr (& mut self) -> INT_EVENT0_ISET_FRMERR_W < INT_EVENT0_ISET_SPEC , 1 > { INT_EVENT0_ISET_FRMERR_W :: new (self) } # [doc = "Bit 2 - Set UART Parity Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iset_parerr (& mut self) -> INT_EVENT0_ISET_PARERR_W < INT_EVENT0_ISET_SPEC , 2 > { INT_EVENT0_ISET_PARERR_W :: new (self) } # [doc = "Bit 3 - Set UART Break Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iset_brkerr (& mut self) -> INT_EVENT0_ISET_BRKERR_W < INT_EVENT0_ISET_SPEC , 3 > { INT_EVENT0_ISET_BRKERR_W :: new (self) } # [doc = "Bit 4 - Set UART Receive Overrun Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iset_ovrerr (& mut self) -> INT_EVENT0_ISET_OVRERR_W < INT_EVENT0_ISET_SPEC , 4 > { INT_EVENT0_ISET_OVRERR_W :: new (self) } # [doc = "Bit 5 - Set Negative Edge on UARTxRXD Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iset_rxne (& mut self) -> INT_EVENT0_ISET_RXNE_W < INT_EVENT0_ISET_SPEC , 5 > { INT_EVENT0_ISET_RXNE_W :: new (self) } # [doc = "Bit 6 - Set Positive Edge on UARTxRXD Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iset_rxpe (& mut self) -> INT_EVENT0_ISET_RXPE_W < INT_EVENT0_ISET_SPEC , 6 > { INT_EVENT0_ISET_RXPE_W :: new (self) } # [doc = "Bit 7 - Set LIN Capture 0 / Match Interrupt ."] # [inline (always)] # [must_use] pub fn int_event0_iset_linc0 (& mut self) -> INT_EVENT0_ISET_LINC0_W < INT_EVENT0_ISET_SPEC , 7 > { INT_EVENT0_ISET_LINC0_W :: new (self) } # [doc = "Bit 8 - Set LIN Capture 1 Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iset_linc1 (& mut self) -> INT_EVENT0_ISET_LINC1_W < INT_EVENT0_ISET_SPEC , 8 > { INT_EVENT0_ISET_LINC1_W :: new (self) } # [doc = "Bit 9 - Set LIN Hardware Counter Overflow Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iset_linovf (& mut self) -> INT_EVENT0_ISET_LINOVF_W < INT_EVENT0_ISET_SPEC , 9 > { INT_EVENT0_ISET_LINOVF_W :: new (self) } # [doc = "Bit 10 - Set UART Receive Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iset_rxint (& mut self) -> INT_EVENT0_ISET_RXINT_W < INT_EVENT0_ISET_SPEC , 10 > { INT_EVENT0_ISET_RXINT_W :: new (self) } # [doc = "Bit 11 - Set UART Transmit Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iset_txint (& mut self) -> INT_EVENT0_ISET_TXINT_W < INT_EVENT0_ISET_SPEC , 11 > { INT_EVENT0_ISET_TXINT_W :: new (self) } # [doc = "Bit 12 - Set UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] # [inline (always)] # [must_use] pub fn int_event0_iset_eot (& mut self) -> INT_EVENT0_ISET_EOT_W < INT_EVENT0_ISET_SPEC , 12 > { INT_EVENT0_ISET_EOT_W :: new (self) } # [doc = "Bit 13 - Set Address Match Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iset_addr_match (& mut self) -> INT_EVENT0_ISET_ADDR_MATCH_W < INT_EVENT0_ISET_SPEC , 13 > { INT_EVENT0_ISET_ADDR_MATCH_W :: new (self) } # [doc = "Bit 14 - Set UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] # [inline (always)] # [must_use] pub fn int_event0_iset_cts (& mut self) -> INT_EVENT0_ISET_CTS_W < INT_EVENT0_ISET_SPEC , 14 > { INT_EVENT0_ISET_CTS_W :: new (self) } # [doc = "Bit 15 - Set DMA Done on RX Event Channel"] # [inline (always)] # [must_use] pub fn int_event0_iset_dma_done_rx (& mut self) -> INT_EVENT0_ISET_DMA_DONE_RX_W < INT_EVENT0_ISET_SPEC , 15 > { INT_EVENT0_ISET_DMA_DONE_RX_W :: new (self) } # [doc = "Bit 16 - Set DMA Done on TX Event Channel"] # [inline (always)] # [must_use] pub fn int_event0_iset_dma_done_tx (& mut self) -> INT_EVENT0_ISET_DMA_DONE_TX_W <'_,  INT_EVENT0_ISET_SPEC , 16 > { INT_EVENT0_ISET_DMA_DONE_TX_W :: new (self) } # [doc = "Bit 17 - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] # [inline (always)] # [must_use] pub fn int_event0_iset_nerr (& mut self) -> INT_EVENT0_ISET_NERR_W < INT_EVENT0_ISET_SPEC , 17 > { INT_EVENT0_ISET_NERR_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Interrupt set\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_event0_iset::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct INT_EVENT0_ISET_SPEC ; impl crate :: RegisterSpec for INT_EVENT0_ISET_SPEC { type Ux = u32 ; } # [doc = "`write(|w| ..)` method takes [`int_event0_iset::W`](W) writer structure"] impl crate :: Writable for INT_EVENT0_ISET_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets INT_EVENT0_ISET to value 0"] impl crate :: Resettable for INT_EVENT0_ISET_SPEC { const RESET_VALUE : Self :: Ux = 0 ; }
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                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                         +++
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing
[INFO] [stdout]  --> src/uart0/int_event0_iset.rs:1:25763
[INFO] [stdout]   |
[INFO] [stdout] 1 | ...nt0_iset_nerr (& mut self) -> INT_EVENT0_ISET_NERR_W < INT_EVENT0_ISET_SPEC , 17 > { INT_EVENT0_ISET_NERR_W :: new (self) } # [doc...
[INFO] [stdout]   |                   ^^^^^^^^^^     ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here
[INFO] [stdout]   |                   |
[INFO] [stdout]   |                   the lifetime is elided here
[INFO] [stdout]   |
[INFO] [stdout]   = help: the same lifetime is referred to in inconsistent ways, making the signature confusing
[INFO] [stdout] help: use `'_` for type paths
[INFO] [stdout]   |
[INFO] [stdout] 1 | # [doc = "Register `INT_EVENT0_ISET` writer"] pub type W = crate :: W < INT_EVENT0_ISET_SPEC > ; # [doc = "Set UARTOUT Receive Time-Out Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_RTOUT_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_RTOUT_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_RTOUT_SET = 1 , } impl From < INT_EVENT0_ISET_RTOUT_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_RTOUT_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_RTOUT` writer - Set UARTOUT Receive Time-Out Interrupt."] pub type INT_EVENT0_ISET_RTOUT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_RTOUT_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_RTOUT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_rtout_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_RTOUT_AW :: INT_EVENT0_ISET_RTOUT_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_rtout_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_RTOUT_AW :: INT_EVENT0_ISET_RTOUT_SET) } } # [doc = "Set UART Framing Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_FRMERR_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_FRMERR_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_FRMERR_SET = 1 , } impl From < INT_EVENT0_ISET_FRMERR_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_FRMERR_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_FRMERR` writer - Set UART Framing Error Interrupt."] pub type INT_EVENT0_ISET_FRMERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_FRMERR_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_FRMERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_frmerr_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_FRMERR_AW :: INT_EVENT0_ISET_FRMERR_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_frmerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_FRMERR_AW :: INT_EVENT0_ISET_FRMERR_SET) } } # [doc = "Set UART Parity Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_PARERR_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_PARERR_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_PARERR_SET = 1 , } impl From < INT_EVENT0_ISET_PARERR_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_PARERR_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_PARERR` writer - Set UART Parity Error Interrupt."] pub type INT_EVENT0_ISET_PARERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_PARERR_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_PARERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_parerr_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_PARERR_AW :: INT_EVENT0_ISET_PARERR_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_parerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_PARERR_AW :: INT_EVENT0_ISET_PARERR_SET) } } # [doc = "Set UART Break Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_BRKERR_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_BRKERR_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_BRKERR_SET = 1 , } impl From < INT_EVENT0_ISET_BRKERR_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_BRKERR_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_BRKERR` writer - Set UART Break Error Interrupt."] pub type INT_EVENT0_ISET_BRKERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_BRKERR_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_BRKERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_brkerr_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_BRKERR_AW :: INT_EVENT0_ISET_BRKERR_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_brkerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_BRKERR_AW :: INT_EVENT0_ISET_BRKERR_SET) } } # [doc = "Set UART Receive Overrun Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_OVRERR_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_OVRERR_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_OVRERR_SET = 1 , } impl From < INT_EVENT0_ISET_OVRERR_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_OVRERR_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_OVRERR` writer - Set UART Receive Overrun Error Interrupt."] pub type INT_EVENT0_ISET_OVRERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_OVRERR_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_OVRERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_ovrerr_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_OVRERR_AW :: INT_EVENT0_ISET_OVRERR_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_ovrerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_OVRERR_AW :: INT_EVENT0_ISET_OVRERR_SET) } } # [doc = "Set Negative Edge on UARTxRXD Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_RXNE_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_RXNE_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_RXNE_SET = 1 , } impl From < INT_EVENT0_ISET_RXNE_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_RXNE_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_RXNE` writer - Set Negative Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_ISET_RXNE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_RXNE_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_RXNE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_rxne_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_RXNE_AW :: INT_EVENT0_ISET_RXNE_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_rxne_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_RXNE_AW :: INT_EVENT0_ISET_RXNE_SET) } } # [doc = "Set Positive Edge on UARTxRXD Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_RXPE_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_RXPE_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_RXPE_SET = 1 , } impl From < INT_EVENT0_ISET_RXPE_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_RXPE_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_RXPE` writer - Set Positive Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_ISET_RXPE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_RXPE_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_RXPE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_rxpe_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_RXPE_AW :: INT_EVENT0_ISET_RXPE_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_rxpe_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_RXPE_AW :: INT_EVENT0_ISET_RXPE_SET) } } # [doc = "Set LIN Capture 0 / Match Interrupt .\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_LINC0_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_LINC0_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_LINC0_SET = 1 , } impl From < INT_EVENT0_ISET_LINC0_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_LINC0_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_LINC0` writer - Set LIN Capture 0 / Match Interrupt ."] pub type INT_EVENT0_ISET_LINC0_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_LINC0_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_LINC0_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_linc0_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_LINC0_AW :: INT_EVENT0_ISET_LINC0_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_linc0_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_LINC0_AW :: INT_EVENT0_ISET_LINC0_SET) } } # [doc = "Set LIN Capture 1 Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_LINC1_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_LINC1_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_LINC1_SET = 1 , } impl From < INT_EVENT0_ISET_LINC1_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_LINC1_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_LINC1` writer - Set LIN Capture 1 Interrupt."] pub type INT_EVENT0_ISET_LINC1_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_LINC1_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_LINC1_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_linc1_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_LINC1_AW :: INT_EVENT0_ISET_LINC1_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_linc1_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_LINC1_AW :: INT_EVENT0_ISET_LINC1_SET) } } # [doc = "Set LIN Hardware Counter Overflow Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_LINOVF_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_LINOVF_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_LINOVF_SET = 1 , } impl From < INT_EVENT0_ISET_LINOVF_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_LINOVF_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_LINOVF` writer - Set LIN Hardware Counter Overflow Interrupt."] pub type INT_EVENT0_ISET_LINOVF_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_LINOVF_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_LINOVF_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_linovf_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_LINOVF_AW :: INT_EVENT0_ISET_LINOVF_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_linovf_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_LINOVF_AW :: INT_EVENT0_ISET_LINOVF_SET) } } # [doc = "Set UART Receive Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_RXINT_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_RXINT_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_RXINT_SET = 1 , } impl From < INT_EVENT0_ISET_RXINT_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_RXINT_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_RXINT` writer - Set UART Receive Interrupt."] pub type INT_EVENT0_ISET_RXINT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_RXINT_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_RXINT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_rxint_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_RXINT_AW :: INT_EVENT0_ISET_RXINT_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_rxint_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_RXINT_AW :: INT_EVENT0_ISET_RXINT_SET) } } # [doc = "Set UART Transmit Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_TXINT_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_TXINT_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_TXINT_SET = 1 , } impl From < INT_EVENT0_ISET_TXINT_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_TXINT_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_TXINT` writer - Set UART Transmit Interrupt."] pub type INT_EVENT0_ISET_TXINT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_TXINT_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_TXINT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_txint_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_TXINT_AW :: INT_EVENT0_ISET_TXINT_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_txint_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_TXINT_AW :: INT_EVENT0_ISET_TXINT_SET) } } # [doc = "Set UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_EOT_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_EOT_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_EOT_SET = 1 , } impl From < INT_EVENT0_ISET_EOT_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_EOT_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_EOT` writer - Set UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] pub type INT_EVENT0_ISET_EOT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_EOT_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_EOT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_eot_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_EOT_AW :: INT_EVENT0_ISET_EOT_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_eot_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_EOT_AW :: INT_EVENT0_ISET_EOT_SET) } } # [doc = "Set Address Match Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_ADDR_MATCH_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_ADDR_MATCH_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_ADDR_MATCH_SET = 1 , } impl From < INT_EVENT0_ISET_ADDR_MATCH_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_ADDR_MATCH_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_ADDR_MATCH` writer - Set Address Match Interrupt."] pub type INT_EVENT0_ISET_ADDR_MATCH_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_ADDR_MATCH_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_ADDR_MATCH_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_addr_match_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_ADDR_MATCH_AW :: INT_EVENT0_ISET_ADDR_MATCH_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_addr_match_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_ADDR_MATCH_AW :: INT_EVENT0_ISET_ADDR_MATCH_SET) } } # [doc = "Set UART Clear to Send Modem Interrupt. 0 = Interrupt disabled\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_CTS_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_CTS_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_CTS_SET = 1 , } impl From < INT_EVENT0_ISET_CTS_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_CTS_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_CTS` writer - Set UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] pub type INT_EVENT0_ISET_CTS_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_CTS_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_CTS_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_cts_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_CTS_AW :: INT_EVENT0_ISET_CTS_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_cts_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_CTS_AW :: INT_EVENT0_ISET_CTS_SET) } } # [doc = "Set DMA Done on RX Event Channel\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_DMA_DONE_RX_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_DMA_DONE_RX_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_DMA_DONE_RX_SET = 1 , } impl From < INT_EVENT0_ISET_DMA_DONE_RX_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_DMA_DONE_RX_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_DMA_DONE_RX` writer - Set DMA Done on RX Event Channel"] pub type INT_EVENT0_ISET_DMA_DONE_RX_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_DMA_DONE_RX_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_DMA_DONE_RX_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_dma_done_rx_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_DMA_DONE_RX_AW :: INT_EVENT0_ISET_DMA_DONE_RX_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_dma_done_rx_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_DMA_DONE_RX_AW :: INT_EVENT0_ISET_DMA_DONE_RX_SET) } } # [doc = "Set DMA Done on TX Event Channel\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_DMA_DONE_TX_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_DMA_DONE_TX_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_DMA_DONE_TX_SET = 1 , } impl From < INT_EVENT0_ISET_DMA_DONE_TX_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_DMA_DONE_TX_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_DMA_DONE_TX` writer - Set DMA Done on TX Event Channel"] pub type INT_EVENT0_ISET_DMA_DONE_TX_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_DMA_DONE_TX_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_DMA_DONE_TX_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_dma_done_tx_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_DMA_DONE_TX_AW :: INT_EVENT0_ISET_DMA_DONE_TX_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_dma_done_tx_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_DMA_DONE_TX_AW :: INT_EVENT0_ISET_DMA_DONE_TX_SET) } } # [doc = "Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_NERR_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_NERR_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_NERR_SET = 1 , } impl From < INT_EVENT0_ISET_NERR_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_NERR_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_NERR` writer - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] pub type INT_EVENT0_ISET_NERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_NERR_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_NERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_nerr_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_NERR_AW :: INT_EVENT0_ISET_NERR_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_nerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_NERR_AW :: INT_EVENT0_ISET_NERR_SET) } } impl W { # [doc = "Bit 0 - Set UARTOUT Receive Time-Out Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iset_rtout (& mut self) -> INT_EVENT0_ISET_RTOUT_W < INT_EVENT0_ISET_SPEC , 0 > { INT_EVENT0_ISET_RTOUT_W :: new (self) } # [doc = "Bit 1 - Set UART Framing Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iset_frmerr (& mut self) -> INT_EVENT0_ISET_FRMERR_W < INT_EVENT0_ISET_SPEC , 1 > { INT_EVENT0_ISET_FRMERR_W :: new (self) } # [doc = "Bit 2 - Set UART Parity Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iset_parerr (& mut self) -> INT_EVENT0_ISET_PARERR_W < INT_EVENT0_ISET_SPEC , 2 > { INT_EVENT0_ISET_PARERR_W :: new (self) } # [doc = "Bit 3 - Set UART Break Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iset_brkerr (& mut self) -> INT_EVENT0_ISET_BRKERR_W < INT_EVENT0_ISET_SPEC , 3 > { INT_EVENT0_ISET_BRKERR_W :: new (self) } # [doc = "Bit 4 - Set UART Receive Overrun Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iset_ovrerr (& mut self) -> INT_EVENT0_ISET_OVRERR_W < INT_EVENT0_ISET_SPEC , 4 > { INT_EVENT0_ISET_OVRERR_W :: new (self) } # [doc = "Bit 5 - Set Negative Edge on UARTxRXD Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iset_rxne (& mut self) -> INT_EVENT0_ISET_RXNE_W < INT_EVENT0_ISET_SPEC , 5 > { INT_EVENT0_ISET_RXNE_W :: new (self) } # [doc = "Bit 6 - Set Positive Edge on UARTxRXD Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iset_rxpe (& mut self) -> INT_EVENT0_ISET_RXPE_W < INT_EVENT0_ISET_SPEC , 6 > { INT_EVENT0_ISET_RXPE_W :: new (self) } # [doc = "Bit 7 - Set LIN Capture 0 / Match Interrupt ."] # [inline (always)] # [must_use] pub fn int_event0_iset_linc0 (& mut self) -> INT_EVENT0_ISET_LINC0_W < INT_EVENT0_ISET_SPEC , 7 > { INT_EVENT0_ISET_LINC0_W :: new (self) } # [doc = "Bit 8 - Set LIN Capture 1 Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iset_linc1 (& mut self) -> INT_EVENT0_ISET_LINC1_W < INT_EVENT0_ISET_SPEC , 8 > { INT_EVENT0_ISET_LINC1_W :: new (self) } # [doc = "Bit 9 - Set LIN Hardware Counter Overflow Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iset_linovf (& mut self) -> INT_EVENT0_ISET_LINOVF_W < INT_EVENT0_ISET_SPEC , 9 > { INT_EVENT0_ISET_LINOVF_W :: new (self) } # [doc = "Bit 10 - Set UART Receive Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iset_rxint (& mut self) -> INT_EVENT0_ISET_RXINT_W < INT_EVENT0_ISET_SPEC , 10 > { INT_EVENT0_ISET_RXINT_W :: new (self) } # [doc = "Bit 11 - Set UART Transmit Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iset_txint (& mut self) -> INT_EVENT0_ISET_TXINT_W < INT_EVENT0_ISET_SPEC , 11 > { INT_EVENT0_ISET_TXINT_W :: new (self) } # [doc = "Bit 12 - Set UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] # [inline (always)] # [must_use] pub fn int_event0_iset_eot (& mut self) -> INT_EVENT0_ISET_EOT_W < INT_EVENT0_ISET_SPEC , 12 > { INT_EVENT0_ISET_EOT_W :: new (self) } # [doc = "Bit 13 - Set Address Match Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iset_addr_match (& mut self) -> INT_EVENT0_ISET_ADDR_MATCH_W < INT_EVENT0_ISET_SPEC , 13 > { INT_EVENT0_ISET_ADDR_MATCH_W :: new (self) } # [doc = "Bit 14 - Set UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] # [inline (always)] # [must_use] pub fn int_event0_iset_cts (& mut self) -> INT_EVENT0_ISET_CTS_W < INT_EVENT0_ISET_SPEC , 14 > { INT_EVENT0_ISET_CTS_W :: new (self) } # [doc = "Bit 15 - Set DMA Done on RX Event Channel"] # [inline (always)] # [must_use] pub fn int_event0_iset_dma_done_rx (& mut self) -> INT_EVENT0_ISET_DMA_DONE_RX_W < INT_EVENT0_ISET_SPEC , 15 > { INT_EVENT0_ISET_DMA_DONE_RX_W :: new (self) } # [doc = "Bit 16 - Set DMA Done on TX Event Channel"] # [inline (always)] # [must_use] pub fn int_event0_iset_dma_done_tx (& mut self) -> INT_EVENT0_ISET_DMA_DONE_TX_W < INT_EVENT0_ISET_SPEC , 16 > { INT_EVENT0_ISET_DMA_DONE_TX_W :: new (self) } # [doc = "Bit 17 - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] # [inline (always)] # [must_use] pub fn int_event0_iset_nerr (& mut self) -> INT_EVENT0_ISET_NERR_W <'_,  INT_EVENT0_ISET_SPEC , 17 > { INT_EVENT0_ISET_NERR_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Interrupt set\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_event0_iset::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct INT_EVENT0_ISET_SPEC ; impl crate :: RegisterSpec for INT_EVENT0_ISET_SPEC { type Ux = u32 ; } # [doc = "`write(|w| ..)` method takes [`int_event0_iset::W`](W) writer structure"] impl crate :: Writable for INT_EVENT0_ISET_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets INT_EVENT0_ISET to value 0"] impl crate :: Resettable for INT_EVENT0_ISET_SPEC { const RESET_VALUE : Self :: Ux = 0 ; }
[INFO] [stdout]   |                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                          +++
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing
[INFO] [stdout]  --> src/uart0/int_event0_iclr.rs:1:21669
[INFO] [stdout]   |
[INFO] [stdout] 1 | ...t0_iclr_rtout (& mut self) -> INT_EVENT0_ICLR_RTOUT_W < INT_EVENT0_ICLR_SPEC , 0 > { INT_EVENT0_ICLR_RTOUT_W :: new (self) } # [do...
[INFO] [stdout]   |                   ^^^^^^^^^^     ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here
[INFO] [stdout]   |                   |
[INFO] [stdout]   |                   the lifetime is elided here
[INFO] [stdout]   |
[INFO] [stdout]   = help: the same lifetime is referred to in inconsistent ways, making the signature confusing
[INFO] [stdout] help: use `'_` for type paths
[INFO] [stdout]   |
[INFO] [stdout] 1 | # [doc = "Register `INT_EVENT0_ICLR` writer"] pub type W = crate :: W < INT_EVENT0_ICLR_SPEC > ; # [doc = "Clear UARTOUT Receive Time-Out Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_RTOUT_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_RTOUT_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_RTOUT_CLR = 1 , } impl From < INT_EVENT0_ICLR_RTOUT_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_RTOUT_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_RTOUT` writer - Clear UARTOUT Receive Time-Out Interrupt."] pub type INT_EVENT0_ICLR_RTOUT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_RTOUT_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_RTOUT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_rtout_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_RTOUT_AW :: INT_EVENT0_ICLR_RTOUT_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_rtout_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_RTOUT_AW :: INT_EVENT0_ICLR_RTOUT_CLR) } } # [doc = "Clear UART Framing Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_FRMERR_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_FRMERR_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_FRMERR_CLR = 1 , } impl From < INT_EVENT0_ICLR_FRMERR_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_FRMERR_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_FRMERR` writer - Clear UART Framing Error Interrupt."] pub type INT_EVENT0_ICLR_FRMERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_FRMERR_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_FRMERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_frmerr_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_FRMERR_AW :: INT_EVENT0_ICLR_FRMERR_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_frmerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_FRMERR_AW :: INT_EVENT0_ICLR_FRMERR_CLR) } } # [doc = "Clear UART Parity Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_PARERR_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_PARERR_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_PARERR_CLR = 1 , } impl From < INT_EVENT0_ICLR_PARERR_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_PARERR_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_PARERR` writer - Clear UART Parity Error Interrupt."] pub type INT_EVENT0_ICLR_PARERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_PARERR_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_PARERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_parerr_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_PARERR_AW :: INT_EVENT0_ICLR_PARERR_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_parerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_PARERR_AW :: INT_EVENT0_ICLR_PARERR_CLR) } } # [doc = "Clear UART Break Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_BRKERR_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_BRKERR_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_BRKERR_CLR = 1 , } impl From < INT_EVENT0_ICLR_BRKERR_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_BRKERR_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_BRKERR` writer - Clear UART Break Error Interrupt."] pub type INT_EVENT0_ICLR_BRKERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_BRKERR_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_BRKERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_brkerr_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_BRKERR_AW :: INT_EVENT0_ICLR_BRKERR_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_brkerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_BRKERR_AW :: INT_EVENT0_ICLR_BRKERR_CLR) } } # [doc = "Clear UART Receive Overrun Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_OVRERR_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_OVRERR_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_OVRERR_CLR = 1 , } impl From < INT_EVENT0_ICLR_OVRERR_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_OVRERR_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_OVRERR` writer - Clear UART Receive Overrun Error Interrupt."] pub type INT_EVENT0_ICLR_OVRERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_OVRERR_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_OVRERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_ovrerr_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_OVRERR_AW :: INT_EVENT0_ICLR_OVRERR_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_ovrerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_OVRERR_AW :: INT_EVENT0_ICLR_OVRERR_CLR) } } # [doc = "Clear Negative Edge on UARTxRXD Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_RXNE_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_RXNE_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_RXNE_CLR = 1 , } impl From < INT_EVENT0_ICLR_RXNE_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_RXNE_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_RXNE` writer - Clear Negative Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_ICLR_RXNE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_RXNE_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_RXNE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_rxne_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_RXNE_AW :: INT_EVENT0_ICLR_RXNE_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_rxne_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_RXNE_AW :: INT_EVENT0_ICLR_RXNE_CLR) } } # [doc = "Clear Positive Edge on UARTxRXD Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_RXPE_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_RXPE_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_RXPE_CLR = 1 , } impl From < INT_EVENT0_ICLR_RXPE_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_RXPE_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_RXPE` writer - Clear Positive Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_ICLR_RXPE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_RXPE_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_RXPE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_rxpe_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_RXPE_AW :: INT_EVENT0_ICLR_RXPE_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_rxpe_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_RXPE_AW :: INT_EVENT0_ICLR_RXPE_CLR) } } # [doc = "Clear LIN Capture 0 / Match Interrupt .\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_LINC0_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_LINC0_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_LINC0_CLR = 1 , } impl From < INT_EVENT0_ICLR_LINC0_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_LINC0_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_LINC0` writer - Clear LIN Capture 0 / Match Interrupt ."] pub type INT_EVENT0_ICLR_LINC0_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_LINC0_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_LINC0_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_linc0_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_LINC0_AW :: INT_EVENT0_ICLR_LINC0_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_linc0_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_LINC0_AW :: INT_EVENT0_ICLR_LINC0_CLR) } } # [doc = "Clear LIN Capture 1 Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_LINC1_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_LINC1_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_LINC1_CLR = 1 , } impl From < INT_EVENT0_ICLR_LINC1_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_LINC1_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_LINC1` writer - Clear LIN Capture 1 Interrupt."] pub type INT_EVENT0_ICLR_LINC1_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_LINC1_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_LINC1_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_linc1_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_LINC1_AW :: INT_EVENT0_ICLR_LINC1_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_linc1_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_LINC1_AW :: INT_EVENT0_ICLR_LINC1_CLR) } } # [doc = "Clear LIN Hardware Counter Overflow Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_LINOVF_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_LINOVF_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_LINOVF_CLR = 1 , } impl From < INT_EVENT0_ICLR_LINOVF_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_LINOVF_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_LINOVF` writer - Clear LIN Hardware Counter Overflow Interrupt."] pub type INT_EVENT0_ICLR_LINOVF_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_LINOVF_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_LINOVF_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_linovf_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_LINOVF_AW :: INT_EVENT0_ICLR_LINOVF_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_linovf_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_LINOVF_AW :: INT_EVENT0_ICLR_LINOVF_CLR) } } # [doc = "Clear UART Receive Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_RXINT_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_RXINT_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_RXINT_CLR = 1 , } impl From < INT_EVENT0_ICLR_RXINT_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_RXINT_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_RXINT` writer - Clear UART Receive Interrupt."] pub type INT_EVENT0_ICLR_RXINT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_RXINT_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_RXINT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_rxint_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_RXINT_AW :: INT_EVENT0_ICLR_RXINT_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_rxint_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_RXINT_AW :: INT_EVENT0_ICLR_RXINT_CLR) } } # [doc = "Clear UART Transmit Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_TXINT_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_TXINT_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_TXINT_CLR = 1 , } impl From < INT_EVENT0_ICLR_TXINT_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_TXINT_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_TXINT` writer - Clear UART Transmit Interrupt."] pub type INT_EVENT0_ICLR_TXINT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_TXINT_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_TXINT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_txint_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_TXINT_AW :: INT_EVENT0_ICLR_TXINT_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_txint_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_TXINT_AW :: INT_EVENT0_ICLR_TXINT_CLR) } } # [doc = "Clear UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_EOT_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_EOT_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_EOT_CLR = 1 , } impl From < INT_EVENT0_ICLR_EOT_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_EOT_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_EOT` writer - Clear UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] pub type INT_EVENT0_ICLR_EOT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_EOT_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_EOT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_eot_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_EOT_AW :: INT_EVENT0_ICLR_EOT_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_eot_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_EOT_AW :: INT_EVENT0_ICLR_EOT_CLR) } } # [doc = "Clear Address Match Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_ADDR_MATCH_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_ADDR_MATCH_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_ADDR_MATCH_CLR = 1 , } impl From < INT_EVENT0_ICLR_ADDR_MATCH_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_ADDR_MATCH_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_ADDR_MATCH` writer - Clear Address Match Interrupt."] pub type INT_EVENT0_ICLR_ADDR_MATCH_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_ADDR_MATCH_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_ADDR_MATCH_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_addr_match_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_ADDR_MATCH_AW :: INT_EVENT0_ICLR_ADDR_MATCH_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_addr_match_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_ADDR_MATCH_AW :: INT_EVENT0_ICLR_ADDR_MATCH_CLR) } } # [doc = "Clear UART Clear to Send Modem Interrupt. 0 = Interrupt disabled\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_CTS_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_CTS_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_CTS_CLR = 1 , } impl From < INT_EVENT0_ICLR_CTS_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_CTS_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_CTS` writer - Clear UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] pub type INT_EVENT0_ICLR_CTS_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_CTS_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_CTS_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_cts_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_CTS_AW :: INT_EVENT0_ICLR_CTS_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_cts_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_CTS_AW :: INT_EVENT0_ICLR_CTS_CLR) } } # [doc = "Clear DMA Done on RX Event Channel\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_DMA_DONE_RX_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_DMA_DONE_RX_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_DMA_DONE_RX_CLR = 1 , } impl From < INT_EVENT0_ICLR_DMA_DONE_RX_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_DMA_DONE_RX_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_DMA_DONE_RX` writer - Clear DMA Done on RX Event Channel"] pub type INT_EVENT0_ICLR_DMA_DONE_RX_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_DMA_DONE_RX_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_DMA_DONE_RX_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_dma_done_rx_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_DMA_DONE_RX_AW :: INT_EVENT0_ICLR_DMA_DONE_RX_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_dma_done_rx_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_DMA_DONE_RX_AW :: INT_EVENT0_ICLR_DMA_DONE_RX_CLR) } } # [doc = "Clear DMA Done on TX Event Channel\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_DMA_DONE_TX_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_DMA_DONE_TX_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_DMA_DONE_TX_CLR = 1 , } impl From < INT_EVENT0_ICLR_DMA_DONE_TX_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_DMA_DONE_TX_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_DMA_DONE_TX` writer - Clear DMA Done on TX Event Channel"] pub type INT_EVENT0_ICLR_DMA_DONE_TX_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_DMA_DONE_TX_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_DMA_DONE_TX_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_dma_done_tx_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_DMA_DONE_TX_AW :: INT_EVENT0_ICLR_DMA_DONE_TX_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_dma_done_tx_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_DMA_DONE_TX_AW :: INT_EVENT0_ICLR_DMA_DONE_TX_CLR) } } # [doc = "Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_NERR_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_NERR_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_NERR_CLR = 1 , } impl From < INT_EVENT0_ICLR_NERR_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_NERR_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_NERR` writer - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] pub type INT_EVENT0_ICLR_NERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_NERR_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_NERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_nerr_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_NERR_AW :: INT_EVENT0_ICLR_NERR_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_nerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_NERR_AW :: INT_EVENT0_ICLR_NERR_CLR) } } impl W { # [doc = "Bit 0 - Clear UARTOUT Receive Time-Out Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iclr_rtout (& mut self) -> INT_EVENT0_ICLR_RTOUT_W <'_,  INT_EVENT0_ICLR_SPEC , 0 > { INT_EVENT0_ICLR_RTOUT_W :: new (self) } # [doc = "Bit 1 - Clear UART Framing Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iclr_frmerr (& mut self) -> INT_EVENT0_ICLR_FRMERR_W < INT_EVENT0_ICLR_SPEC , 1 > { INT_EVENT0_ICLR_FRMERR_W :: new (self) } # [doc = "Bit 2 - Clear UART Parity Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iclr_parerr (& mut self) -> INT_EVENT0_ICLR_PARERR_W < INT_EVENT0_ICLR_SPEC , 2 > { INT_EVENT0_ICLR_PARERR_W :: new (self) } # [doc = "Bit 3 - Clear UART Break Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iclr_brkerr (& mut self) -> INT_EVENT0_ICLR_BRKERR_W < INT_EVENT0_ICLR_SPEC , 3 > { INT_EVENT0_ICLR_BRKERR_W :: new (self) } # [doc = "Bit 4 - Clear UART Receive Overrun Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iclr_ovrerr (& mut self) -> INT_EVENT0_ICLR_OVRERR_W < INT_EVENT0_ICLR_SPEC , 4 > { INT_EVENT0_ICLR_OVRERR_W :: new (self) } # [doc = "Bit 5 - Clear Negative Edge on UARTxRXD Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iclr_rxne (& mut self) -> INT_EVENT0_ICLR_RXNE_W < INT_EVENT0_ICLR_SPEC , 5 > { INT_EVENT0_ICLR_RXNE_W :: new (self) } # [doc = "Bit 6 - Clear Positive Edge on UARTxRXD Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iclr_rxpe (& mut self) -> INT_EVENT0_ICLR_RXPE_W < INT_EVENT0_ICLR_SPEC , 6 > { INT_EVENT0_ICLR_RXPE_W :: new (self) } # [doc = "Bit 7 - Clear LIN Capture 0 / Match Interrupt ."] # [inline (always)] # [must_use] pub fn int_event0_iclr_linc0 (& mut self) -> INT_EVENT0_ICLR_LINC0_W < INT_EVENT0_ICLR_SPEC , 7 > { INT_EVENT0_ICLR_LINC0_W :: new (self) } # [doc = "Bit 8 - Clear LIN Capture 1 Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iclr_linc1 (& mut self) -> INT_EVENT0_ICLR_LINC1_W < INT_EVENT0_ICLR_SPEC , 8 > { INT_EVENT0_ICLR_LINC1_W :: new (self) } # [doc = "Bit 9 - Clear LIN Hardware Counter Overflow Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iclr_linovf (& mut self) -> INT_EVENT0_ICLR_LINOVF_W < INT_EVENT0_ICLR_SPEC , 9 > { INT_EVENT0_ICLR_LINOVF_W :: new (self) } # [doc = "Bit 10 - Clear UART Receive Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iclr_rxint (& mut self) -> INT_EVENT0_ICLR_RXINT_W < INT_EVENT0_ICLR_SPEC , 10 > { INT_EVENT0_ICLR_RXINT_W :: new (self) } # [doc = "Bit 11 - Clear UART Transmit Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iclr_txint (& mut self) -> INT_EVENT0_ICLR_TXINT_W < INT_EVENT0_ICLR_SPEC , 11 > { INT_EVENT0_ICLR_TXINT_W :: new (self) } # [doc = "Bit 12 - Clear UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] # [inline (always)] # [must_use] pub fn int_event0_iclr_eot (& mut self) -> INT_EVENT0_ICLR_EOT_W < INT_EVENT0_ICLR_SPEC , 12 > { INT_EVENT0_ICLR_EOT_W :: new (self) } # [doc = "Bit 13 - Clear Address Match Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iclr_addr_match (& mut self) -> INT_EVENT0_ICLR_ADDR_MATCH_W < INT_EVENT0_ICLR_SPEC , 13 > { INT_EVENT0_ICLR_ADDR_MATCH_W :: new (self) } # [doc = "Bit 14 - Clear UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] # [inline (always)] # [must_use] pub fn int_event0_iclr_cts (& mut self) -> INT_EVENT0_ICLR_CTS_W < INT_EVENT0_ICLR_SPEC , 14 > { INT_EVENT0_ICLR_CTS_W :: new (self) } # [doc = "Bit 15 - Clear DMA Done on RX Event Channel"] # [inline (always)] # [must_use] pub fn int_event0_iclr_dma_done_rx (& mut self) -> INT_EVENT0_ICLR_DMA_DONE_RX_W < INT_EVENT0_ICLR_SPEC , 15 > { INT_EVENT0_ICLR_DMA_DONE_RX_W :: new (self) } # [doc = "Bit 16 - Clear DMA Done on TX Event Channel"] # [inline (always)] # [must_use] pub fn int_event0_iclr_dma_done_tx (& mut self) -> INT_EVENT0_ICLR_DMA_DONE_TX_W < INT_EVENT0_ICLR_SPEC , 16 > { INT_EVENT0_ICLR_DMA_DONE_TX_W :: new (self) } # [doc = "Bit 17 - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] # [inline (always)] # [must_use] pub fn int_event0_iclr_nerr (& mut self) -> INT_EVENT0_ICLR_NERR_W < INT_EVENT0_ICLR_SPEC , 17 > { INT_EVENT0_ICLR_NERR_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Interrupt clear\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_event0_iclr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct INT_EVENT0_ICLR_SPEC ; impl crate :: RegisterSpec for INT_EVENT0_ICLR_SPEC { type Ux = u32 ; } # [doc = "`write(|w| ..)` method takes [`int_event0_iclr::W`](W) writer structure"] impl crate :: Writable for INT_EVENT0_ICLR_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets INT_EVENT0_ICLR to value 0"] impl crate :: Resettable for INT_EVENT0_ICLR_SPEC { const RESET_VALUE : Self :: Ux = 0 ; }
[INFO] [stdout]   |                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                             +++
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing
[INFO] [stdout]  --> src/uart0/int_event0_iclr.rs:1:21899
[INFO] [stdout]   |
[INFO] [stdout] 1 | ..._iclr_frmerr (& mut self) -> INT_EVENT0_ICLR_FRMERR_W < INT_EVENT0_ICLR_SPEC , 1 > { INT_EVENT0_ICLR_FRMERR_W :: new (self) } # [d...
[INFO] [stdout]   |                  ^^^^^^^^^^     ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here
[INFO] [stdout]   |                  |
[INFO] [stdout]   |                  the lifetime is elided here
[INFO] [stdout]   |
[INFO] [stdout]   = help: the same lifetime is referred to in inconsistent ways, making the signature confusing
[INFO] [stdout] help: use `'_` for type paths
[INFO] [stdout]   |
[INFO] [stdout] 1 | # [doc = "Register `INT_EVENT0_ICLR` writer"] pub type W = crate :: W < INT_EVENT0_ICLR_SPEC > ; # [doc = "Clear UARTOUT Receive Time-Out Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_RTOUT_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_RTOUT_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_RTOUT_CLR = 1 , } impl From < INT_EVENT0_ICLR_RTOUT_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_RTOUT_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_RTOUT` writer - Clear UARTOUT Receive Time-Out Interrupt."] pub type INT_EVENT0_ICLR_RTOUT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_RTOUT_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_RTOUT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_rtout_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_RTOUT_AW :: INT_EVENT0_ICLR_RTOUT_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_rtout_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_RTOUT_AW :: INT_EVENT0_ICLR_RTOUT_CLR) } } # [doc = "Clear UART Framing Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_FRMERR_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_FRMERR_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_FRMERR_CLR = 1 , } impl From < INT_EVENT0_ICLR_FRMERR_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_FRMERR_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_FRMERR` writer - Clear UART Framing Error Interrupt."] pub type INT_EVENT0_ICLR_FRMERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_FRMERR_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_FRMERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_frmerr_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_FRMERR_AW :: INT_EVENT0_ICLR_FRMERR_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_frmerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_FRMERR_AW :: INT_EVENT0_ICLR_FRMERR_CLR) } } # [doc = "Clear UART Parity Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_PARERR_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_PARERR_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_PARERR_CLR = 1 , } impl From < INT_EVENT0_ICLR_PARERR_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_PARERR_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_PARERR` writer - Clear UART Parity Error Interrupt."] pub type INT_EVENT0_ICLR_PARERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_PARERR_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_PARERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_parerr_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_PARERR_AW :: INT_EVENT0_ICLR_PARERR_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_parerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_PARERR_AW :: INT_EVENT0_ICLR_PARERR_CLR) } } # [doc = "Clear UART Break Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_BRKERR_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_BRKERR_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_BRKERR_CLR = 1 , } impl From < INT_EVENT0_ICLR_BRKERR_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_BRKERR_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_BRKERR` writer - Clear UART Break Error Interrupt."] pub type INT_EVENT0_ICLR_BRKERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_BRKERR_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_BRKERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_brkerr_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_BRKERR_AW :: INT_EVENT0_ICLR_BRKERR_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_brkerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_BRKERR_AW :: INT_EVENT0_ICLR_BRKERR_CLR) } } # [doc = "Clear UART Receive Overrun Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_OVRERR_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_OVRERR_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_OVRERR_CLR = 1 , } impl From < INT_EVENT0_ICLR_OVRERR_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_OVRERR_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_OVRERR` writer - Clear UART Receive Overrun Error Interrupt."] pub type INT_EVENT0_ICLR_OVRERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_OVRERR_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_OVRERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_ovrerr_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_OVRERR_AW :: INT_EVENT0_ICLR_OVRERR_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_ovrerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_OVRERR_AW :: INT_EVENT0_ICLR_OVRERR_CLR) } } # [doc = "Clear Negative Edge on UARTxRXD Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_RXNE_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_RXNE_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_RXNE_CLR = 1 , } impl From < INT_EVENT0_ICLR_RXNE_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_RXNE_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_RXNE` writer - Clear Negative Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_ICLR_RXNE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_RXNE_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_RXNE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_rxne_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_RXNE_AW :: INT_EVENT0_ICLR_RXNE_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_rxne_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_RXNE_AW :: INT_EVENT0_ICLR_RXNE_CLR) } } # [doc = "Clear Positive Edge on UARTxRXD Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_RXPE_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_RXPE_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_RXPE_CLR = 1 , } impl From < INT_EVENT0_ICLR_RXPE_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_RXPE_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_RXPE` writer - Clear Positive Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_ICLR_RXPE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_RXPE_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_RXPE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_rxpe_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_RXPE_AW :: INT_EVENT0_ICLR_RXPE_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_rxpe_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_RXPE_AW :: INT_EVENT0_ICLR_RXPE_CLR) } } # [doc = "Clear LIN Capture 0 / Match Interrupt .\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_LINC0_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_LINC0_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_LINC0_CLR = 1 , } impl From < INT_EVENT0_ICLR_LINC0_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_LINC0_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_LINC0` writer - Clear LIN Capture 0 / Match Interrupt ."] pub type INT_EVENT0_ICLR_LINC0_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_LINC0_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_LINC0_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_linc0_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_LINC0_AW :: INT_EVENT0_ICLR_LINC0_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_linc0_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_LINC0_AW :: INT_EVENT0_ICLR_LINC0_CLR) } } # [doc = "Clear LIN Capture 1 Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_LINC1_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_LINC1_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_LINC1_CLR = 1 , } impl From < INT_EVENT0_ICLR_LINC1_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_LINC1_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_LINC1` writer - Clear LIN Capture 1 Interrupt."] pub type INT_EVENT0_ICLR_LINC1_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_LINC1_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_LINC1_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_linc1_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_LINC1_AW :: INT_EVENT0_ICLR_LINC1_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_linc1_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_LINC1_AW :: INT_EVENT0_ICLR_LINC1_CLR) } } # [doc = "Clear LIN Hardware Counter Overflow Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_LINOVF_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_LINOVF_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_LINOVF_CLR = 1 , } impl From < INT_EVENT0_ICLR_LINOVF_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_LINOVF_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_LINOVF` writer - Clear LIN Hardware Counter Overflow Interrupt."] pub type INT_EVENT0_ICLR_LINOVF_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_LINOVF_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_LINOVF_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_linovf_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_LINOVF_AW :: INT_EVENT0_ICLR_LINOVF_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_linovf_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_LINOVF_AW :: INT_EVENT0_ICLR_LINOVF_CLR) } } # [doc = "Clear UART Receive Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_RXINT_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_RXINT_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_RXINT_CLR = 1 , } impl From < INT_EVENT0_ICLR_RXINT_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_RXINT_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_RXINT` writer - Clear UART Receive Interrupt."] pub type INT_EVENT0_ICLR_RXINT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_RXINT_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_RXINT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_rxint_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_RXINT_AW :: INT_EVENT0_ICLR_RXINT_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_rxint_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_RXINT_AW :: INT_EVENT0_ICLR_RXINT_CLR) } } # [doc = "Clear UART Transmit Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_TXINT_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_TXINT_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_TXINT_CLR = 1 , } impl From < INT_EVENT0_ICLR_TXINT_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_TXINT_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_TXINT` writer - Clear UART Transmit Interrupt."] pub type INT_EVENT0_ICLR_TXINT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_TXINT_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_TXINT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_txint_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_TXINT_AW :: INT_EVENT0_ICLR_TXINT_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_txint_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_TXINT_AW :: INT_EVENT0_ICLR_TXINT_CLR) } } # [doc = "Clear UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_EOT_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_EOT_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_EOT_CLR = 1 , } impl From < INT_EVENT0_ICLR_EOT_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_EOT_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_EOT` writer - Clear UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] pub type INT_EVENT0_ICLR_EOT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_EOT_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_EOT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_eot_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_EOT_AW :: INT_EVENT0_ICLR_EOT_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_eot_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_EOT_AW :: INT_EVENT0_ICLR_EOT_CLR) } } # [doc = "Clear Address Match Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_ADDR_MATCH_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_ADDR_MATCH_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_ADDR_MATCH_CLR = 1 , } impl From < INT_EVENT0_ICLR_ADDR_MATCH_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_ADDR_MATCH_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_ADDR_MATCH` writer - Clear Address Match Interrupt."] pub type INT_EVENT0_ICLR_ADDR_MATCH_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_ADDR_MATCH_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_ADDR_MATCH_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_addr_match_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_ADDR_MATCH_AW :: INT_EVENT0_ICLR_ADDR_MATCH_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_addr_match_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_ADDR_MATCH_AW :: INT_EVENT0_ICLR_ADDR_MATCH_CLR) } } # [doc = "Clear UART Clear to Send Modem Interrupt. 0 = Interrupt disabled\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_CTS_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_CTS_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_CTS_CLR = 1 , } impl From < INT_EVENT0_ICLR_CTS_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_CTS_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_CTS` writer - Clear UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] pub type INT_EVENT0_ICLR_CTS_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_CTS_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_CTS_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_cts_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_CTS_AW :: INT_EVENT0_ICLR_CTS_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_cts_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_CTS_AW :: INT_EVENT0_ICLR_CTS_CLR) } } # [doc = "Clear DMA Done on RX Event Channel\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_DMA_DONE_RX_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_DMA_DONE_RX_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_DMA_DONE_RX_CLR = 1 , } impl From < INT_EVENT0_ICLR_DMA_DONE_RX_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_DMA_DONE_RX_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_DMA_DONE_RX` writer - Clear DMA Done on RX Event Channel"] pub type INT_EVENT0_ICLR_DMA_DONE_RX_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_DMA_DONE_RX_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_DMA_DONE_RX_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_dma_done_rx_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_DMA_DONE_RX_AW :: INT_EVENT0_ICLR_DMA_DONE_RX_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_dma_done_rx_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_DMA_DONE_RX_AW :: INT_EVENT0_ICLR_DMA_DONE_RX_CLR) } } # [doc = "Clear DMA Done on TX Event Channel\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_DMA_DONE_TX_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_DMA_DONE_TX_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_DMA_DONE_TX_CLR = 1 , } impl From < INT_EVENT0_ICLR_DMA_DONE_TX_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_DMA_DONE_TX_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_DMA_DONE_TX` writer - Clear DMA Done on TX Event Channel"] pub type INT_EVENT0_ICLR_DMA_DONE_TX_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_DMA_DONE_TX_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_DMA_DONE_TX_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_dma_done_tx_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_DMA_DONE_TX_AW :: INT_EVENT0_ICLR_DMA_DONE_TX_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_dma_done_tx_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_DMA_DONE_TX_AW :: INT_EVENT0_ICLR_DMA_DONE_TX_CLR) } } # [doc = "Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_NERR_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_NERR_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_NERR_CLR = 1 , } impl From < INT_EVENT0_ICLR_NERR_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_NERR_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_NERR` writer - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] pub type INT_EVENT0_ICLR_NERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_NERR_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_NERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_nerr_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_NERR_AW :: INT_EVENT0_ICLR_NERR_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_nerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_NERR_AW :: INT_EVENT0_ICLR_NERR_CLR) } } impl W { # [doc = "Bit 0 - Clear UARTOUT Receive Time-Out Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iclr_rtout (& mut self) -> INT_EVENT0_ICLR_RTOUT_W < INT_EVENT0_ICLR_SPEC , 0 > { INT_EVENT0_ICLR_RTOUT_W :: new (self) } # [doc = "Bit 1 - Clear UART Framing Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iclr_frmerr (& mut self) -> INT_EVENT0_ICLR_FRMERR_W <'_,  INT_EVENT0_ICLR_SPEC , 1 > { INT_EVENT0_ICLR_FRMERR_W :: new (self) } # [doc = "Bit 2 - Clear UART Parity Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iclr_parerr (& mut self) -> INT_EVENT0_ICLR_PARERR_W < INT_EVENT0_ICLR_SPEC , 2 > { INT_EVENT0_ICLR_PARERR_W :: new (self) } # [doc = "Bit 3 - Clear UART Break Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iclr_brkerr (& mut self) -> INT_EVENT0_ICLR_BRKERR_W < INT_EVENT0_ICLR_SPEC , 3 > { INT_EVENT0_ICLR_BRKERR_W :: new (self) } # [doc = "Bit 4 - Clear UART Receive Overrun Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iclr_ovrerr (& mut self) -> INT_EVENT0_ICLR_OVRERR_W < INT_EVENT0_ICLR_SPEC , 4 > { INT_EVENT0_ICLR_OVRERR_W :: new (self) } # [doc = "Bit 5 - Clear Negative Edge on UARTxRXD Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iclr_rxne (& mut self) -> INT_EVENT0_ICLR_RXNE_W < INT_EVENT0_ICLR_SPEC , 5 > { INT_EVENT0_ICLR_RXNE_W :: new (self) } # [doc = "Bit 6 - Clear Positive Edge on UARTxRXD Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iclr_rxpe (& mut self) -> INT_EVENT0_ICLR_RXPE_W < INT_EVENT0_ICLR_SPEC , 6 > { INT_EVENT0_ICLR_RXPE_W :: new (self) } # [doc = "Bit 7 - Clear LIN Capture 0 / Match Interrupt ."] # [inline (always)] # [must_use] pub fn int_event0_iclr_linc0 (& mut self) -> INT_EVENT0_ICLR_LINC0_W < INT_EVENT0_ICLR_SPEC , 7 > { INT_EVENT0_ICLR_LINC0_W :: new (self) } # [doc = "Bit 8 - Clear LIN Capture 1 Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iclr_linc1 (& mut self) -> INT_EVENT0_ICLR_LINC1_W < INT_EVENT0_ICLR_SPEC , 8 > { INT_EVENT0_ICLR_LINC1_W :: new (self) } # [doc = "Bit 9 - Clear LIN Hardware Counter Overflow Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iclr_linovf (& mut self) -> INT_EVENT0_ICLR_LINOVF_W < INT_EVENT0_ICLR_SPEC , 9 > { INT_EVENT0_ICLR_LINOVF_W :: new (self) } # [doc = "Bit 10 - Clear UART Receive Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iclr_rxint (& mut self) -> INT_EVENT0_ICLR_RXINT_W < INT_EVENT0_ICLR_SPEC , 10 > { INT_EVENT0_ICLR_RXINT_W :: new (self) } # [doc = "Bit 11 - Clear UART Transmit Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iclr_txint (& mut self) -> INT_EVENT0_ICLR_TXINT_W < INT_EVENT0_ICLR_SPEC , 11 > { INT_EVENT0_ICLR_TXINT_W :: new (self) } # [doc = "Bit 12 - Clear UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] # [inline (always)] # [must_use] pub fn int_event0_iclr_eot (& mut self) -> INT_EVENT0_ICLR_EOT_W < INT_EVENT0_ICLR_SPEC , 12 > { INT_EVENT0_ICLR_EOT_W :: new (self) } # [doc = "Bit 13 - Clear Address Match Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iclr_addr_match (& mut self) -> INT_EVENT0_ICLR_ADDR_MATCH_W < INT_EVENT0_ICLR_SPEC , 13 > { INT_EVENT0_ICLR_ADDR_MATCH_W :: new (self) } # [doc = "Bit 14 - Clear UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] # [inline (always)] # [must_use] pub fn int_event0_iclr_cts (& mut self) -> INT_EVENT0_ICLR_CTS_W < INT_EVENT0_ICLR_SPEC , 14 > { INT_EVENT0_ICLR_CTS_W :: new (self) } # [doc = "Bit 15 - Clear DMA Done on RX Event Channel"] # [inline (always)] # [must_use] pub fn int_event0_iclr_dma_done_rx (& mut self) -> INT_EVENT0_ICLR_DMA_DONE_RX_W < INT_EVENT0_ICLR_SPEC , 15 > { INT_EVENT0_ICLR_DMA_DONE_RX_W :: new (self) } # [doc = "Bit 16 - Clear DMA Done on TX Event Channel"] # [inline (always)] # [must_use] pub fn int_event0_iclr_dma_done_tx (& mut self) -> INT_EVENT0_ICLR_DMA_DONE_TX_W < INT_EVENT0_ICLR_SPEC , 16 > { INT_EVENT0_ICLR_DMA_DONE_TX_W :: new (self) } # [doc = "Bit 17 - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] # [inline (always)] # [must_use] pub fn int_event0_iclr_nerr (& mut self) -> INT_EVENT0_ICLR_NERR_W < INT_EVENT0_ICLR_SPEC , 17 > { INT_EVENT0_ICLR_NERR_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Interrupt clear\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_event0_iclr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct INT_EVENT0_ICLR_SPEC ; impl crate :: RegisterSpec for INT_EVENT0_ICLR_SPEC { type Ux = u32 ; } # [doc = "`write(|w| ..)` method takes [`int_event0_iclr::W`](W) writer structure"] impl crate :: Writable for INT_EVENT0_ICLR_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets INT_EVENT0_ICLR to value 0"] impl crate :: Resettable for INT_EVENT0_ICLR_SPEC { const RESET_VALUE : Self :: Ux = 0 ; }
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                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                     +++
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing
[INFO] [stdout]  --> src/uart0/pwren.rs:1:2941
[INFO] [stdout]   |
[INFO] [stdout] 1 | ...e] pub fn pwren_enable (& mut self) -> PWREN_ENABLE_W < PWREN_SPEC , 0 > { PWREN_ENABLE_W :: new (self) } # [doc = "Bits 24:31 - K...
[INFO] [stdout]   |                            ^^^^^^^^^^     ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here
[INFO] [stdout]   |                            |
[INFO] [stdout]   |                            the lifetime is elided here
[INFO] [stdout]   |
[INFO] [stdout]   = help: the same lifetime is referred to in inconsistent ways, making the signature confusing
[INFO] [stdout]   = note: `#[warn(mismatched_lifetime_syntaxes)]` on by default
[INFO] [stdout] help: use `'_` for type paths
[INFO] [stdout]   |
[INFO] [stdout] 1 | # [doc = "Register `PWREN` reader"] pub type R = crate :: R < PWREN_SPEC > ; # [doc = "Register `PWREN` writer"] pub type W = crate :: W < PWREN_SPEC > ; # [doc = "Field `PWREN_ENABLE` reader - Enable the power"] pub type PWREN_ENABLE_R = crate :: BitReader < PWREN_ENABLE_A > ; # [doc = "Enable the power\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum PWREN_ENABLE_A { # [doc = "0: DISABLE"] PWREN_ENABLE_DISABLE = 0 , # [doc = "1: ENABLE"] PWREN_ENABLE_ENABLE = 1 , } impl From < PWREN_ENABLE_A > for bool { # [inline (always)] fn from (variant : PWREN_ENABLE_A) -> Self { variant as u8 != 0 } } impl PWREN_ENABLE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> PWREN_ENABLE_A { match self . bits { false => PWREN_ENABLE_A :: PWREN_ENABLE_DISABLE , true => PWREN_ENABLE_A :: PWREN_ENABLE_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_pwren_enable_disable (& self) -> bool { * self == PWREN_ENABLE_A :: PWREN_ENABLE_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_pwren_enable_enable (& self) -> bool { * self == PWREN_ENABLE_A :: PWREN_ENABLE_ENABLE } } # [doc = "Field `PWREN_ENABLE` writer - Enable the power"] pub type PWREN_ENABLE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , PWREN_ENABLE_A > ; impl < 'a , REG , const O : u8 > PWREN_ENABLE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn pwren_enable_disable (self) -> & 'a mut crate :: W < REG > { self . variant (PWREN_ENABLE_A :: PWREN_ENABLE_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn pwren_enable_enable (self) -> & 'a mut crate :: W < REG > { self . variant (PWREN_ENABLE_A :: PWREN_ENABLE_ENABLE) } } # [doc = "KEY to allow Power State Change\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum PWREN_KEY_AW { # [doc = "38: _TO_UNLOCK_W_"] PWREN_KEY_UNLOCK_W = 38 , } impl From < PWREN_KEY_AW > for u8 { # [inline (always)] fn from (variant : PWREN_KEY_AW) -> Self { variant as _ } } impl crate :: FieldSpec for PWREN_KEY_AW { type Ux = u8 ; } # [doc = "Field `PWREN_KEY` writer - KEY to allow Power State Change"] pub type PWREN_KEY_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 8 , O , PWREN_KEY_AW > ; impl < 'a , REG , const O : u8 > PWREN_KEY_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "_TO_UNLOCK_W_"] # [inline (always)] pub fn pwren_key_unlock_w (self) -> & 'a mut crate :: W < REG > { self . variant (PWREN_KEY_AW :: PWREN_KEY_UNLOCK_W) } } impl R { # [doc = "Bit 0 - Enable the power"] # [inline (always)] pub fn pwren_enable (& self) -> PWREN_ENABLE_R { PWREN_ENABLE_R :: new ((self . bits & 1) != 0) } } impl W { # [doc = "Bit 0 - Enable the power"] # [inline (always)] # [must_use] pub fn pwren_enable (& mut self) -> PWREN_ENABLE_W <'_,  PWREN_SPEC , 0 > { PWREN_ENABLE_W :: new (self) } # [doc = "Bits 24:31 - KEY to allow Power State Change"] # [inline (always)] # [must_use] pub fn pwren_key (& mut self) -> PWREN_KEY_W < PWREN_SPEC , 24 > { PWREN_KEY_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Power enable\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pwren::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pwren::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PWREN_SPEC ; impl crate :: RegisterSpec for PWREN_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`pwren::R`](R) reader structure"] impl crate :: Readable for PWREN_SPEC { } # [doc = "`write(|w| ..)` method takes [`pwren::W`](W) writer structure"] impl crate :: Writable for PWREN_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets PWREN to value 0"] impl crate :: Resettable for PWREN_SPEC { const RESET_VALUE : Self :: Ux = 0 ; }
[INFO] [stdout]   |                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                            +++
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing
[INFO] [stdout]  --> src/uart0/pwren.rs:1:3131
[INFO] [stdout]   |
[INFO] [stdout] 1 | ...t_use] pub fn pwren_key (& mut self) -> PWREN_KEY_W < PWREN_SPEC , 24 > { PWREN_KEY_W :: new (self) } # [doc = r" Writes raw bits ...
[INFO] [stdout]   |                             ^^^^^^^^^^     ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here
[INFO] [stdout]   |                             |
[INFO] [stdout]   |                             the lifetime is elided here
[INFO] [stdout]   |
[INFO] [stdout]   = help: the same lifetime is referred to in inconsistent ways, making the signature confusing
[INFO] [stdout] help: use `'_` for type paths
[INFO] [stdout]   |
[INFO] [stdout] 1 | # [doc = "Register `PWREN` reader"] pub type R = crate :: R < PWREN_SPEC > ; # [doc = "Register `PWREN` writer"] pub type W = crate :: W < PWREN_SPEC > ; # [doc = "Field `PWREN_ENABLE` reader - Enable the power"] pub type PWREN_ENABLE_R = crate :: BitReader < PWREN_ENABLE_A > ; # [doc = "Enable the power\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum PWREN_ENABLE_A { # [doc = "0: DISABLE"] PWREN_ENABLE_DISABLE = 0 , # [doc = "1: ENABLE"] PWREN_ENABLE_ENABLE = 1 , } impl From < PWREN_ENABLE_A > for bool { # [inline (always)] fn from (variant : PWREN_ENABLE_A) -> Self { variant as u8 != 0 } } impl PWREN_ENABLE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> PWREN_ENABLE_A { match self . bits { false => PWREN_ENABLE_A :: PWREN_ENABLE_DISABLE , true => PWREN_ENABLE_A :: PWREN_ENABLE_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_pwren_enable_disable (& self) -> bool { * self == PWREN_ENABLE_A :: PWREN_ENABLE_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_pwren_enable_enable (& self) -> bool { * self == PWREN_ENABLE_A :: PWREN_ENABLE_ENABLE } } # [doc = "Field `PWREN_ENABLE` writer - Enable the power"] pub type PWREN_ENABLE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , PWREN_ENABLE_A > ; impl < 'a , REG , const O : u8 > PWREN_ENABLE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn pwren_enable_disable (self) -> & 'a mut crate :: W < REG > { self . variant (PWREN_ENABLE_A :: PWREN_ENABLE_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn pwren_enable_enable (self) -> & 'a mut crate :: W < REG > { self . variant (PWREN_ENABLE_A :: PWREN_ENABLE_ENABLE) } } # [doc = "KEY to allow Power State Change\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum PWREN_KEY_AW { # [doc = "38: _TO_UNLOCK_W_"] PWREN_KEY_UNLOCK_W = 38 , } impl From < PWREN_KEY_AW > for u8 { # [inline (always)] fn from (variant : PWREN_KEY_AW) -> Self { variant as _ } } impl crate :: FieldSpec for PWREN_KEY_AW { type Ux = u8 ; } # [doc = "Field `PWREN_KEY` writer - KEY to allow Power State Change"] pub type PWREN_KEY_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 8 , O , PWREN_KEY_AW > ; impl < 'a , REG , const O : u8 > PWREN_KEY_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "_TO_UNLOCK_W_"] # [inline (always)] pub fn pwren_key_unlock_w (self) -> & 'a mut crate :: W < REG > { self . variant (PWREN_KEY_AW :: PWREN_KEY_UNLOCK_W) } } impl R { # [doc = "Bit 0 - Enable the power"] # [inline (always)] pub fn pwren_enable (& self) -> PWREN_ENABLE_R { PWREN_ENABLE_R :: new ((self . bits & 1) != 0) } } impl W { # [doc = "Bit 0 - Enable the power"] # [inline (always)] # [must_use] pub fn pwren_enable (& mut self) -> PWREN_ENABLE_W < PWREN_SPEC , 0 > { PWREN_ENABLE_W :: new (self) } # [doc = "Bits 24:31 - KEY to allow Power State Change"] # [inline (always)] # [must_use] pub fn pwren_key (& mut self) -> PWREN_KEY_W <'_,  PWREN_SPEC , 24 > { PWREN_KEY_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Power enable\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pwren::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pwren::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PWREN_SPEC ; impl crate :: RegisterSpec for PWREN_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`pwren::R`](R) reader structure"] impl crate :: Readable for PWREN_SPEC { } # [doc = "`write(|w| ..)` method takes [`pwren::W`](W) writer structure"] impl crate :: Writable for PWREN_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets PWREN to value 0"] impl crate :: Resettable for PWREN_SPEC { const RESET_VALUE : Self :: Ux = 0 ; }
[INFO] [stdout]   |                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                       +++
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing
[INFO] [stdout]  --> src/uart0/int_event0_iclr.rs:1:22130
[INFO] [stdout]   |
[INFO] [stdout] 1 | ..._iclr_parerr (& mut self) -> INT_EVENT0_ICLR_PARERR_W < INT_EVENT0_ICLR_SPEC , 2 > { INT_EVENT0_ICLR_PARERR_W :: new (self) } # [d...
[INFO] [stdout]   |                  ^^^^^^^^^^     ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here
[INFO] [stdout]   |                  |
[INFO] [stdout]   |                  the lifetime is elided here
[INFO] [stdout]   |
[INFO] [stdout]   = help: the same lifetime is referred to in inconsistent ways, making the signature confusing
[INFO] [stdout] help: use `'_` for type paths
[INFO] [stdout]   |
[INFO] [stdout] 1 | # [doc = "Register `INT_EVENT0_ICLR` writer"] pub type W = crate :: W < INT_EVENT0_ICLR_SPEC > ; # [doc = "Clear UARTOUT Receive Time-Out Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_RTOUT_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_RTOUT_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_RTOUT_CLR = 1 , } impl From < INT_EVENT0_ICLR_RTOUT_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_RTOUT_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_RTOUT` writer - Clear UARTOUT Receive Time-Out Interrupt."] pub type INT_EVENT0_ICLR_RTOUT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_RTOUT_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_RTOUT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_rtout_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_RTOUT_AW :: INT_EVENT0_ICLR_RTOUT_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_rtout_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_RTOUT_AW :: INT_EVENT0_ICLR_RTOUT_CLR) } } # [doc = "Clear UART Framing Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_FRMERR_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_FRMERR_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_FRMERR_CLR = 1 , } impl From < INT_EVENT0_ICLR_FRMERR_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_FRMERR_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_FRMERR` writer - Clear UART Framing Error Interrupt."] pub type INT_EVENT0_ICLR_FRMERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_FRMERR_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_FRMERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_frmerr_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_FRMERR_AW :: INT_EVENT0_ICLR_FRMERR_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_frmerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_FRMERR_AW :: INT_EVENT0_ICLR_FRMERR_CLR) } } # [doc = "Clear UART Parity Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_PARERR_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_PARERR_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_PARERR_CLR = 1 , } impl From < INT_EVENT0_ICLR_PARERR_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_PARERR_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_PARERR` writer - Clear UART Parity Error Interrupt."] pub type INT_EVENT0_ICLR_PARERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_PARERR_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_PARERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_parerr_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_PARERR_AW :: INT_EVENT0_ICLR_PARERR_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_parerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_PARERR_AW :: INT_EVENT0_ICLR_PARERR_CLR) } } # [doc = "Clear UART Break Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_BRKERR_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_BRKERR_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_BRKERR_CLR = 1 , } impl From < INT_EVENT0_ICLR_BRKERR_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_BRKERR_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_BRKERR` writer - Clear UART Break Error Interrupt."] pub type INT_EVENT0_ICLR_BRKERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_BRKERR_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_BRKERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_brkerr_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_BRKERR_AW :: INT_EVENT0_ICLR_BRKERR_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_brkerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_BRKERR_AW :: INT_EVENT0_ICLR_BRKERR_CLR) } } # [doc = "Clear UART Receive Overrun Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_OVRERR_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_OVRERR_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_OVRERR_CLR = 1 , } impl From < INT_EVENT0_ICLR_OVRERR_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_OVRERR_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_OVRERR` writer - Clear UART Receive Overrun Error Interrupt."] pub type INT_EVENT0_ICLR_OVRERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_OVRERR_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_OVRERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_ovrerr_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_OVRERR_AW :: INT_EVENT0_ICLR_OVRERR_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_ovrerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_OVRERR_AW :: INT_EVENT0_ICLR_OVRERR_CLR) } } # [doc = "Clear Negative Edge on UARTxRXD Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_RXNE_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_RXNE_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_RXNE_CLR = 1 , } impl From < INT_EVENT0_ICLR_RXNE_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_RXNE_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_RXNE` writer - Clear Negative Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_ICLR_RXNE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_RXNE_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_RXNE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_rxne_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_RXNE_AW :: INT_EVENT0_ICLR_RXNE_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_rxne_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_RXNE_AW :: INT_EVENT0_ICLR_RXNE_CLR) } } # [doc = "Clear Positive Edge on UARTxRXD Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_RXPE_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_RXPE_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_RXPE_CLR = 1 , } impl From < INT_EVENT0_ICLR_RXPE_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_RXPE_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_RXPE` writer - Clear Positive Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_ICLR_RXPE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_RXPE_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_RXPE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_rxpe_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_RXPE_AW :: INT_EVENT0_ICLR_RXPE_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_rxpe_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_RXPE_AW :: INT_EVENT0_ICLR_RXPE_CLR) } } # [doc = "Clear LIN Capture 0 / Match Interrupt .\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_LINC0_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_LINC0_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_LINC0_CLR = 1 , } impl From < INT_EVENT0_ICLR_LINC0_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_LINC0_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_LINC0` writer - Clear LIN Capture 0 / Match Interrupt ."] pub type INT_EVENT0_ICLR_LINC0_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_LINC0_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_LINC0_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_linc0_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_LINC0_AW :: INT_EVENT0_ICLR_LINC0_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_linc0_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_LINC0_AW :: INT_EVENT0_ICLR_LINC0_CLR) } } # [doc = "Clear LIN Capture 1 Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_LINC1_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_LINC1_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_LINC1_CLR = 1 , } impl From < INT_EVENT0_ICLR_LINC1_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_LINC1_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_LINC1` writer - Clear LIN Capture 1 Interrupt."] pub type INT_EVENT0_ICLR_LINC1_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_LINC1_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_LINC1_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_linc1_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_LINC1_AW :: INT_EVENT0_ICLR_LINC1_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_linc1_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_LINC1_AW :: INT_EVENT0_ICLR_LINC1_CLR) } } # [doc = "Clear LIN Hardware Counter Overflow Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_LINOVF_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_LINOVF_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_LINOVF_CLR = 1 , } impl From < INT_EVENT0_ICLR_LINOVF_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_LINOVF_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_LINOVF` writer - Clear LIN Hardware Counter Overflow Interrupt."] pub type INT_EVENT0_ICLR_LINOVF_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_LINOVF_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_LINOVF_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_linovf_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_LINOVF_AW :: INT_EVENT0_ICLR_LINOVF_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_linovf_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_LINOVF_AW :: INT_EVENT0_ICLR_LINOVF_CLR) } } # [doc = "Clear UART Receive Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_RXINT_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_RXINT_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_RXINT_CLR = 1 , } impl From < INT_EVENT0_ICLR_RXINT_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_RXINT_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_RXINT` writer - Clear UART Receive Interrupt."] pub type INT_EVENT0_ICLR_RXINT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_RXINT_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_RXINT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_rxint_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_RXINT_AW :: INT_EVENT0_ICLR_RXINT_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_rxint_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_RXINT_AW :: INT_EVENT0_ICLR_RXINT_CLR) } } # [doc = "Clear UART Transmit Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_TXINT_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_TXINT_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_TXINT_CLR = 1 , } impl From < INT_EVENT0_ICLR_TXINT_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_TXINT_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_TXINT` writer - Clear UART Transmit Interrupt."] pub type INT_EVENT0_ICLR_TXINT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_TXINT_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_TXINT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_txint_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_TXINT_AW :: INT_EVENT0_ICLR_TXINT_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_txint_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_TXINT_AW :: INT_EVENT0_ICLR_TXINT_CLR) } } # [doc = "Clear UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_EOT_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_EOT_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_EOT_CLR = 1 , } impl From < INT_EVENT0_ICLR_EOT_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_EOT_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_EOT` writer - Clear UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] pub type INT_EVENT0_ICLR_EOT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_EOT_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_EOT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_eot_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_EOT_AW :: INT_EVENT0_ICLR_EOT_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_eot_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_EOT_AW :: INT_EVENT0_ICLR_EOT_CLR) } } # [doc = "Clear Address Match Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_ADDR_MATCH_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_ADDR_MATCH_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_ADDR_MATCH_CLR = 1 , } impl From < INT_EVENT0_ICLR_ADDR_MATCH_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_ADDR_MATCH_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_ADDR_MATCH` writer - Clear Address Match Interrupt."] pub type INT_EVENT0_ICLR_ADDR_MATCH_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_ADDR_MATCH_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_ADDR_MATCH_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_addr_match_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_ADDR_MATCH_AW :: INT_EVENT0_ICLR_ADDR_MATCH_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_addr_match_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_ADDR_MATCH_AW :: INT_EVENT0_ICLR_ADDR_MATCH_CLR) } } # [doc = "Clear UART Clear to Send Modem Interrupt. 0 = Interrupt disabled\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_CTS_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_CTS_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_CTS_CLR = 1 , } impl From < INT_EVENT0_ICLR_CTS_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_CTS_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_CTS` writer - Clear UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] pub type INT_EVENT0_ICLR_CTS_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_CTS_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_CTS_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_cts_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_CTS_AW :: INT_EVENT0_ICLR_CTS_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_cts_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_CTS_AW :: INT_EVENT0_ICLR_CTS_CLR) } } # [doc = "Clear DMA Done on RX Event Channel\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_DMA_DONE_RX_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_DMA_DONE_RX_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_DMA_DONE_RX_CLR = 1 , } impl From < INT_EVENT0_ICLR_DMA_DONE_RX_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_DMA_DONE_RX_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_DMA_DONE_RX` writer - Clear DMA Done on RX Event Channel"] pub type INT_EVENT0_ICLR_DMA_DONE_RX_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_DMA_DONE_RX_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_DMA_DONE_RX_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_dma_done_rx_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_DMA_DONE_RX_AW :: INT_EVENT0_ICLR_DMA_DONE_RX_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_dma_done_rx_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_DMA_DONE_RX_AW :: INT_EVENT0_ICLR_DMA_DONE_RX_CLR) } } # [doc = "Clear DMA Done on TX Event Channel\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_DMA_DONE_TX_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_DMA_DONE_TX_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_DMA_DONE_TX_CLR = 1 , } impl From < INT_EVENT0_ICLR_DMA_DONE_TX_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_DMA_DONE_TX_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_DMA_DONE_TX` writer - Clear DMA Done on TX Event Channel"] pub type INT_EVENT0_ICLR_DMA_DONE_TX_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_DMA_DONE_TX_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_DMA_DONE_TX_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_dma_done_tx_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_DMA_DONE_TX_AW :: INT_EVENT0_ICLR_DMA_DONE_TX_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_dma_done_tx_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_DMA_DONE_TX_AW :: INT_EVENT0_ICLR_DMA_DONE_TX_CLR) } } # [doc = "Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_NERR_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_NERR_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_NERR_CLR = 1 , } impl From < INT_EVENT0_ICLR_NERR_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_NERR_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_NERR` writer - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] pub type INT_EVENT0_ICLR_NERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_NERR_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_NERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_nerr_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_NERR_AW :: INT_EVENT0_ICLR_NERR_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_nerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_NERR_AW :: INT_EVENT0_ICLR_NERR_CLR) } } impl W { # [doc = "Bit 0 - Clear UARTOUT Receive Time-Out Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iclr_rtout (& mut self) -> INT_EVENT0_ICLR_RTOUT_W < INT_EVENT0_ICLR_SPEC , 0 > { INT_EVENT0_ICLR_RTOUT_W :: new (self) } # [doc = "Bit 1 - Clear UART Framing Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iclr_frmerr (& mut self) -> INT_EVENT0_ICLR_FRMERR_W < INT_EVENT0_ICLR_SPEC , 1 > { INT_EVENT0_ICLR_FRMERR_W :: new (self) } # [doc = "Bit 2 - Clear UART Parity Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iclr_parerr (& mut self) -> INT_EVENT0_ICLR_PARERR_W <'_,  INT_EVENT0_ICLR_SPEC , 2 > { INT_EVENT0_ICLR_PARERR_W :: new (self) } # [doc = "Bit 3 - Clear UART Break Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iclr_brkerr (& mut self) -> INT_EVENT0_ICLR_BRKERR_W < INT_EVENT0_ICLR_SPEC , 3 > { INT_EVENT0_ICLR_BRKERR_W :: new (self) } # [doc = "Bit 4 - Clear UART Receive Overrun Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iclr_ovrerr (& mut self) -> INT_EVENT0_ICLR_OVRERR_W < INT_EVENT0_ICLR_SPEC , 4 > { INT_EVENT0_ICLR_OVRERR_W :: new (self) } # [doc = "Bit 5 - Clear Negative Edge on UARTxRXD Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iclr_rxne (& mut self) -> INT_EVENT0_ICLR_RXNE_W < INT_EVENT0_ICLR_SPEC , 5 > { INT_EVENT0_ICLR_RXNE_W :: new (self) } # [doc = "Bit 6 - Clear Positive Edge on UARTxRXD Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iclr_rxpe (& mut self) -> INT_EVENT0_ICLR_RXPE_W < INT_EVENT0_ICLR_SPEC , 6 > { INT_EVENT0_ICLR_RXPE_W :: new (self) } # [doc = "Bit 7 - Clear LIN Capture 0 / Match Interrupt ."] # [inline (always)] # [must_use] pub fn int_event0_iclr_linc0 (& mut self) -> INT_EVENT0_ICLR_LINC0_W < INT_EVENT0_ICLR_SPEC , 7 > { INT_EVENT0_ICLR_LINC0_W :: new (self) } # [doc = "Bit 8 - Clear LIN Capture 1 Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iclr_linc1 (& mut self) -> INT_EVENT0_ICLR_LINC1_W < INT_EVENT0_ICLR_SPEC , 8 > { INT_EVENT0_ICLR_LINC1_W :: new (self) } # [doc = "Bit 9 - Clear LIN Hardware Counter Overflow Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iclr_linovf (& mut self) -> INT_EVENT0_ICLR_LINOVF_W < INT_EVENT0_ICLR_SPEC , 9 > { INT_EVENT0_ICLR_LINOVF_W :: new (self) } # [doc = "Bit 10 - Clear UART Receive Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iclr_rxint (& mut self) -> INT_EVENT0_ICLR_RXINT_W < INT_EVENT0_ICLR_SPEC , 10 > { INT_EVENT0_ICLR_RXINT_W :: new (self) } # [doc = "Bit 11 - Clear UART Transmit Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iclr_txint (& mut self) -> INT_EVENT0_ICLR_TXINT_W < INT_EVENT0_ICLR_SPEC , 11 > { INT_EVENT0_ICLR_TXINT_W :: new (self) } # [doc = "Bit 12 - Clear UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] # [inline (always)] # [must_use] pub fn int_event0_iclr_eot (& mut self) -> INT_EVENT0_ICLR_EOT_W < INT_EVENT0_ICLR_SPEC , 12 > { INT_EVENT0_ICLR_EOT_W :: new (self) } # [doc = "Bit 13 - Clear Address Match Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iclr_addr_match (& mut self) -> INT_EVENT0_ICLR_ADDR_MATCH_W < INT_EVENT0_ICLR_SPEC , 13 > { INT_EVENT0_ICLR_ADDR_MATCH_W :: new (self) } # [doc = "Bit 14 - Clear UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] # [inline (always)] # [must_use] pub fn int_event0_iclr_cts (& mut self) -> INT_EVENT0_ICLR_CTS_W < INT_EVENT0_ICLR_SPEC , 14 > { INT_EVENT0_ICLR_CTS_W :: new (self) } # [doc = "Bit 15 - Clear DMA Done on RX Event Channel"] # [inline (always)] # [must_use] pub fn int_event0_iclr_dma_done_rx (& mut self) -> INT_EVENT0_ICLR_DMA_DONE_RX_W < INT_EVENT0_ICLR_SPEC , 15 > { INT_EVENT0_ICLR_DMA_DONE_RX_W :: new (self) } # [doc = "Bit 16 - Clear DMA Done on TX Event Channel"] # [inline (always)] # [must_use] pub fn int_event0_iclr_dma_done_tx (& mut self) -> INT_EVENT0_ICLR_DMA_DONE_TX_W < INT_EVENT0_ICLR_SPEC , 16 > { INT_EVENT0_ICLR_DMA_DONE_TX_W :: new (self) } # [doc = "Bit 17 - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] # [inline (always)] # [must_use] pub fn int_event0_iclr_nerr (& mut self) -> INT_EVENT0_ICLR_NERR_W < INT_EVENT0_ICLR_SPEC , 17 > { INT_EVENT0_ICLR_NERR_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Interrupt clear\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_event0_iclr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct INT_EVENT0_ICLR_SPEC ; impl crate :: RegisterSpec for INT_EVENT0_ICLR_SPEC { type Ux = u32 ; } # [doc = "`write(|w| ..)` method takes [`int_event0_iclr::W`](W) writer structure"] impl crate :: Writable for INT_EVENT0_ICLR_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets INT_EVENT0_ICLR to value 0"] impl crate :: Resettable for INT_EVENT0_ICLR_SPEC { const RESET_VALUE : Self :: Ux = 0 ; }
[INFO] [stdout]   |                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                           +++
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing
[INFO] [stdout]  --> src/uart0/rstctl.rs:1:3243
[INFO] [stdout]   |
[INFO] [stdout] 1 | ... rstctl_resetassert (& mut self) -> RSTCTL_RESETASSERT_W < RSTCTL_SPEC , 0 > { RSTCTL_RESETASSERT_W :: new (self) } # [doc = "Bit ...
[INFO] [stdout]   |                         ^^^^^^^^^^     ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here
[INFO] [stdout]   |                         |
[INFO] [stdout]   |                         the lifetime is elided here
[INFO] [stdout]   |
[INFO] [stdout]   = help: the same lifetime is referred to in inconsistent ways, making the signature confusing
[INFO] [stdout] help: use `'_` for type paths
[INFO] [stdout]   |
[INFO] [stdout] 1 | # [doc = "Register `RSTCTL` writer"] pub type W = crate :: W < RSTCTL_SPEC > ; # [doc = "Assert reset to the peripheral\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum RSTCTL_RESETASSERT_AW { # [doc = "0: NOP"] RSTCTL_RESETASSERT_NOP = 0 , # [doc = "1: ASSERT"] RSTCTL_RESETASSERT_ASSERT = 1 , } impl From < RSTCTL_RESETASSERT_AW > for bool { # [inline (always)] fn from (variant : RSTCTL_RESETASSERT_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `RSTCTL_RESETASSERT` writer - Assert reset to the peripheral"] pub type RSTCTL_RESETASSERT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , RSTCTL_RESETASSERT_AW > ; impl < 'a , REG , const O : u8 > RSTCTL_RESETASSERT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NOP"] # [inline (always)] pub fn rstctl_resetassert_nop (self) -> & 'a mut crate :: W < REG > { self . variant (RSTCTL_RESETASSERT_AW :: RSTCTL_RESETASSERT_NOP) } # [doc = "ASSERT"] # [inline (always)] pub fn rstctl_resetassert_assert (self) -> & 'a mut crate :: W < REG > { self . variant (RSTCTL_RESETASSERT_AW :: RSTCTL_RESETASSERT_ASSERT) } } # [doc = "Clear the RESETSTKY bit in the STAT register\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum RSTCTL_RESETSTKYCLR_AW { # [doc = "0: NOP"] RSTCTL_RESETSTKYCLR_NOP = 0 , # [doc = "1: CLR"] RSTCTL_RESETSTKYCLR_CLR = 1 , } impl From < RSTCTL_RESETSTKYCLR_AW > for bool { # [inline (always)] fn from (variant : RSTCTL_RESETSTKYCLR_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `RSTCTL_RESETSTKYCLR` writer - Clear the RESETSTKY bit in the STAT register"] pub type RSTCTL_RESETSTKYCLR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , RSTCTL_RESETSTKYCLR_AW > ; impl < 'a , REG , const O : u8 > RSTCTL_RESETSTKYCLR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NOP"] # [inline (always)] pub fn rstctl_resetstkyclr_nop (self) -> & 'a mut crate :: W < REG > { self . variant (RSTCTL_RESETSTKYCLR_AW :: RSTCTL_RESETSTKYCLR_NOP) } # [doc = "CLR"] # [inline (always)] pub fn rstctl_resetstkyclr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (RSTCTL_RESETSTKYCLR_AW :: RSTCTL_RESETSTKYCLR_CLR) } } # [doc = "Unlock key\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum RSTCTL_KEY_AW { # [doc = "177: _TO_UNLOCK_W_"] RSTCTL_KEY_UNLOCK_W = 177 , } impl From < RSTCTL_KEY_AW > for u8 { # [inline (always)] fn from (variant : RSTCTL_KEY_AW) -> Self { variant as _ } } impl crate :: FieldSpec for RSTCTL_KEY_AW { type Ux = u8 ; } # [doc = "Field `RSTCTL_KEY` writer - Unlock key"] pub type RSTCTL_KEY_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 8 , O , RSTCTL_KEY_AW > ; impl < 'a , REG , const O : u8 > RSTCTL_KEY_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "_TO_UNLOCK_W_"] # [inline (always)] pub fn rstctl_key_unlock_w (self) -> & 'a mut crate :: W < REG > { self . variant (RSTCTL_KEY_AW :: RSTCTL_KEY_UNLOCK_W) } } impl W { # [doc = "Bit 0 - Assert reset to the peripheral"] # [inline (always)] # [must_use] pub fn rstctl_resetassert (& mut self) -> RSTCTL_RESETASSERT_W <'_,  RSTCTL_SPEC , 0 > { RSTCTL_RESETASSERT_W :: new (self) } # [doc = "Bit 1 - Clear the RESETSTKY bit in the STAT register"] # [inline (always)] # [must_use] pub fn rstctl_resetstkyclr (& mut self) -> RSTCTL_RESETSTKYCLR_W < RSTCTL_SPEC , 1 > { RSTCTL_RESETSTKYCLR_W :: new (self) } # [doc = "Bits 24:31 - Unlock key"] # [inline (always)] # [must_use] pub fn rstctl_key (& mut self) -> RSTCTL_KEY_W < RSTCTL_SPEC , 24 > { RSTCTL_KEY_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Reset Control\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rstctl::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct RSTCTL_SPEC ; impl crate :: RegisterSpec for RSTCTL_SPEC { type Ux = u32 ; } # [doc = "`write(|w| ..)` method takes [`rstctl::W`](W) writer structure"] impl crate :: Writable for RSTCTL_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets RSTCTL to value 0"] impl crate :: Resettable for RSTCTL_SPEC { const RESET_VALUE : Self :: Ux = 0 ; }
[INFO] [stdout]   |                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                +++
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing
[INFO] [stdout]  --> src/uart0/rstctl.rs:1:3464
[INFO] [stdout]   |
[INFO] [stdout] 1 | ...stctl_resetstkyclr (& mut self) -> RSTCTL_RESETSTKYCLR_W < RSTCTL_SPEC , 1 > { RSTCTL_RESETSTKYCLR_W :: new (self) } # [doc = "Bit...
[INFO] [stdout]   |                        ^^^^^^^^^^     ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here
[INFO] [stdout]   |                        |
[INFO] [stdout]   |                        the lifetime is elided here
[INFO] [stdout]   |
[INFO] [stdout]   = help: the same lifetime is referred to in inconsistent ways, making the signature confusing
[INFO] [stdout] help: use `'_` for type paths
[INFO] [stdout]   |
[INFO] [stdout] 1 | # [doc = "Register `RSTCTL` writer"] pub type W = crate :: W < RSTCTL_SPEC > ; # [doc = "Assert reset to the peripheral\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum RSTCTL_RESETASSERT_AW { # [doc = "0: NOP"] RSTCTL_RESETASSERT_NOP = 0 , # [doc = "1: ASSERT"] RSTCTL_RESETASSERT_ASSERT = 1 , } impl From < RSTCTL_RESETASSERT_AW > for bool { # [inline (always)] fn from (variant : RSTCTL_RESETASSERT_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `RSTCTL_RESETASSERT` writer - Assert reset to the peripheral"] pub type RSTCTL_RESETASSERT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , RSTCTL_RESETASSERT_AW > ; impl < 'a , REG , const O : u8 > RSTCTL_RESETASSERT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NOP"] # [inline (always)] pub fn rstctl_resetassert_nop (self) -> & 'a mut crate :: W < REG > { self . variant (RSTCTL_RESETASSERT_AW :: RSTCTL_RESETASSERT_NOP) } # [doc = "ASSERT"] # [inline (always)] pub fn rstctl_resetassert_assert (self) -> & 'a mut crate :: W < REG > { self . variant (RSTCTL_RESETASSERT_AW :: RSTCTL_RESETASSERT_ASSERT) } } # [doc = "Clear the RESETSTKY bit in the STAT register\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum RSTCTL_RESETSTKYCLR_AW { # [doc = "0: NOP"] RSTCTL_RESETSTKYCLR_NOP = 0 , # [doc = "1: CLR"] RSTCTL_RESETSTKYCLR_CLR = 1 , } impl From < RSTCTL_RESETSTKYCLR_AW > for bool { # [inline (always)] fn from (variant : RSTCTL_RESETSTKYCLR_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `RSTCTL_RESETSTKYCLR` writer - Clear the RESETSTKY bit in the STAT register"] pub type RSTCTL_RESETSTKYCLR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , RSTCTL_RESETSTKYCLR_AW > ; impl < 'a , REG , const O : u8 > RSTCTL_RESETSTKYCLR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NOP"] # [inline (always)] pub fn rstctl_resetstkyclr_nop (self) -> & 'a mut crate :: W < REG > { self . variant (RSTCTL_RESETSTKYCLR_AW :: RSTCTL_RESETSTKYCLR_NOP) } # [doc = "CLR"] # [inline (always)] pub fn rstctl_resetstkyclr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (RSTCTL_RESETSTKYCLR_AW :: RSTCTL_RESETSTKYCLR_CLR) } } # [doc = "Unlock key\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum RSTCTL_KEY_AW { # [doc = "177: _TO_UNLOCK_W_"] RSTCTL_KEY_UNLOCK_W = 177 , } impl From < RSTCTL_KEY_AW > for u8 { # [inline (always)] fn from (variant : RSTCTL_KEY_AW) -> Self { variant as _ } } impl crate :: FieldSpec for RSTCTL_KEY_AW { type Ux = u8 ; } # [doc = "Field `RSTCTL_KEY` writer - Unlock key"] pub type RSTCTL_KEY_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 8 , O , RSTCTL_KEY_AW > ; impl < 'a , REG , const O : u8 > RSTCTL_KEY_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "_TO_UNLOCK_W_"] # [inline (always)] pub fn rstctl_key_unlock_w (self) -> & 'a mut crate :: W < REG > { self . variant (RSTCTL_KEY_AW :: RSTCTL_KEY_UNLOCK_W) } } impl W { # [doc = "Bit 0 - Assert reset to the peripheral"] # [inline (always)] # [must_use] pub fn rstctl_resetassert (& mut self) -> RSTCTL_RESETASSERT_W < RSTCTL_SPEC , 0 > { RSTCTL_RESETASSERT_W :: new (self) } # [doc = "Bit 1 - Clear the RESETSTKY bit in the STAT register"] # [inline (always)] # [must_use] pub fn rstctl_resetstkyclr (& mut self) -> RSTCTL_RESETSTKYCLR_W <'_,  RSTCTL_SPEC , 1 > { RSTCTL_RESETSTKYCLR_W :: new (self) } # [doc = "Bits 24:31 - Unlock key"] # [inline (always)] # [must_use] pub fn rstctl_key (& mut self) -> RSTCTL_KEY_W < RSTCTL_SPEC , 24 > { RSTCTL_KEY_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Reset Control\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rstctl::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct RSTCTL_SPEC ; impl crate :: RegisterSpec for RSTCTL_SPEC { type Ux = u32 ; } # [doc = "`write(|w| ..)` method takes [`rstctl::W`](W) writer structure"] impl crate :: Writable for RSTCTL_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets RSTCTL to value 0"] impl crate :: Resettable for RSTCTL_SPEC { const RESET_VALUE : Self :: Ux = 0 ; }
[INFO] [stdout]   |                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                              +++
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing
[INFO] [stdout]  --> src/uart0/rstctl.rs:1:3649
[INFO] [stdout]   |
[INFO] [stdout] 1 | ...use] pub fn rstctl_key (& mut self) -> RSTCTL_KEY_W < RSTCTL_SPEC , 24 > { RSTCTL_KEY_W :: new (self) } # [doc = r" Writes raw bit...
[INFO] [stdout]   |                            ^^^^^^^^^^     ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here
[INFO] [stdout]   |                            |
[INFO] [stdout]   |                            the lifetime is elided here
[INFO] [stdout]   |
[INFO] [stdout]   = help: the same lifetime is referred to in inconsistent ways, making the signature confusing
[INFO] [stdout] help: use `'_` for type paths
[INFO] [stdout]   |
[INFO] [stdout] 1 | # [doc = "Register `RSTCTL` writer"] pub type W = crate :: W < RSTCTL_SPEC > ; # [doc = "Assert reset to the peripheral\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum RSTCTL_RESETASSERT_AW { # [doc = "0: NOP"] RSTCTL_RESETASSERT_NOP = 0 , # [doc = "1: ASSERT"] RSTCTL_RESETASSERT_ASSERT = 1 , } impl From < RSTCTL_RESETASSERT_AW > for bool { # [inline (always)] fn from (variant : RSTCTL_RESETASSERT_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `RSTCTL_RESETASSERT` writer - Assert reset to the peripheral"] pub type RSTCTL_RESETASSERT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , RSTCTL_RESETASSERT_AW > ; impl < 'a , REG , const O : u8 > RSTCTL_RESETASSERT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NOP"] # [inline (always)] pub fn rstctl_resetassert_nop (self) -> & 'a mut crate :: W < REG > { self . variant (RSTCTL_RESETASSERT_AW :: RSTCTL_RESETASSERT_NOP) } # [doc = "ASSERT"] # [inline (always)] pub fn rstctl_resetassert_assert (self) -> & 'a mut crate :: W < REG > { self . variant (RSTCTL_RESETASSERT_AW :: RSTCTL_RESETASSERT_ASSERT) } } # [doc = "Clear the RESETSTKY bit in the STAT register\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum RSTCTL_RESETSTKYCLR_AW { # [doc = "0: NOP"] RSTCTL_RESETSTKYCLR_NOP = 0 , # [doc = "1: CLR"] RSTCTL_RESETSTKYCLR_CLR = 1 , } impl From < RSTCTL_RESETSTKYCLR_AW > for bool { # [inline (always)] fn from (variant : RSTCTL_RESETSTKYCLR_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `RSTCTL_RESETSTKYCLR` writer - Clear the RESETSTKY bit in the STAT register"] pub type RSTCTL_RESETSTKYCLR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , RSTCTL_RESETSTKYCLR_AW > ; impl < 'a , REG , const O : u8 > RSTCTL_RESETSTKYCLR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NOP"] # [inline (always)] pub fn rstctl_resetstkyclr_nop (self) -> & 'a mut crate :: W < REG > { self . variant (RSTCTL_RESETSTKYCLR_AW :: RSTCTL_RESETSTKYCLR_NOP) } # [doc = "CLR"] # [inline (always)] pub fn rstctl_resetstkyclr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (RSTCTL_RESETSTKYCLR_AW :: RSTCTL_RESETSTKYCLR_CLR) } } # [doc = "Unlock key\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum RSTCTL_KEY_AW { # [doc = "177: _TO_UNLOCK_W_"] RSTCTL_KEY_UNLOCK_W = 177 , } impl From < RSTCTL_KEY_AW > for u8 { # [inline (always)] fn from (variant : RSTCTL_KEY_AW) -> Self { variant as _ } } impl crate :: FieldSpec for RSTCTL_KEY_AW { type Ux = u8 ; } # [doc = "Field `RSTCTL_KEY` writer - Unlock key"] pub type RSTCTL_KEY_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 8 , O , RSTCTL_KEY_AW > ; impl < 'a , REG , const O : u8 > RSTCTL_KEY_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "_TO_UNLOCK_W_"] # [inline (always)] pub fn rstctl_key_unlock_w (self) -> & 'a mut crate :: W < REG > { self . variant (RSTCTL_KEY_AW :: RSTCTL_KEY_UNLOCK_W) } } impl W { # [doc = "Bit 0 - Assert reset to the peripheral"] # [inline (always)] # [must_use] pub fn rstctl_resetassert (& mut self) -> RSTCTL_RESETASSERT_W < RSTCTL_SPEC , 0 > { RSTCTL_RESETASSERT_W :: new (self) } # [doc = "Bit 1 - Clear the RESETSTKY bit in the STAT register"] # [inline (always)] # [must_use] pub fn rstctl_resetstkyclr (& mut self) -> RSTCTL_RESETSTKYCLR_W < RSTCTL_SPEC , 1 > { RSTCTL_RESETSTKYCLR_W :: new (self) } # [doc = "Bits 24:31 - Unlock key"] # [inline (always)] # [must_use] pub fn rstctl_key (& mut self) -> RSTCTL_KEY_W <'_,  RSTCTL_SPEC , 24 > { RSTCTL_KEY_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Reset Control\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rstctl::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct RSTCTL_SPEC ; impl crate :: RegisterSpec for RSTCTL_SPEC { type Ux = u32 ; } # [doc = "`write(|w| ..)` method takes [`rstctl::W`](W) writer structure"] impl crate :: Writable for RSTCTL_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets RSTCTL to value 0"] impl crate :: Resettable for RSTCTL_SPEC { const RESET_VALUE : Self :: Ux = 0 ; }
[INFO] [stdout]   |                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                              +++
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing
[INFO] [stdout]  --> src/uart0/clkcfg.rs:1:3453
[INFO] [stdout]   |
[INFO] [stdout] 1 | ...n clkcfg_blockasync (& mut self) -> CLKCFG_BLOCKASYNC_W < CLKCFG_SPEC , 8 > { CLKCFG_BLOCKASYNC_W :: new (self) } # [doc = "Bits 2...
[INFO] [stdout]   |                         ^^^^^^^^^^     ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here
[INFO] [stdout]   |                         |
[INFO] [stdout]   |                         the lifetime is elided here
[INFO] [stdout]   |
[INFO] [stdout]   = help: the same lifetime is referred to in inconsistent ways, making the signature confusing
[INFO] [stdout] help: use `'_` for type paths
[INFO] [stdout]   |
[INFO] [stdout] 1 | # [doc = "Register `CLKCFG` reader"] pub type R = crate :: R < CLKCFG_SPEC > ; # [doc = "Register `CLKCFG` writer"] pub type W = crate :: W < CLKCFG_SPEC > ; # [doc = "Field `CLKCFG_BLOCKASYNC` reader - Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz"] pub type CLKCFG_BLOCKASYNC_R = crate :: BitReader < CLKCFG_BLOCKASYNC_A > ; # [doc = "Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CLKCFG_BLOCKASYNC_A { # [doc = "0: DISABLE"] CLKCFG_BLOCKASYNC_DISABLE = 0 , # [doc = "1: ENABLE"] CLKCFG_BLOCKASYNC_ENABLE = 1 , } impl From < CLKCFG_BLOCKASYNC_A > for bool { # [inline (always)] fn from (variant : CLKCFG_BLOCKASYNC_A) -> Self { variant as u8 != 0 } } impl CLKCFG_BLOCKASYNC_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CLKCFG_BLOCKASYNC_A { match self . bits { false => CLKCFG_BLOCKASYNC_A :: CLKCFG_BLOCKASYNC_DISABLE , true => CLKCFG_BLOCKASYNC_A :: CLKCFG_BLOCKASYNC_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_clkcfg_blockasync_disable (& self) -> bool { * self == CLKCFG_BLOCKASYNC_A :: CLKCFG_BLOCKASYNC_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_clkcfg_blockasync_enable (& self) -> bool { * self == CLKCFG_BLOCKASYNC_A :: CLKCFG_BLOCKASYNC_ENABLE } } # [doc = "Field `CLKCFG_BLOCKASYNC` writer - Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz"] pub type CLKCFG_BLOCKASYNC_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CLKCFG_BLOCKASYNC_A > ; impl < 'a , REG , const O : u8 > CLKCFG_BLOCKASYNC_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn clkcfg_blockasync_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CLKCFG_BLOCKASYNC_A :: CLKCFG_BLOCKASYNC_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn clkcfg_blockasync_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CLKCFG_BLOCKASYNC_A :: CLKCFG_BLOCKASYNC_ENABLE) } } # [doc = "KEY to Allow State Change -- 0xA9\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum CLKCFG_KEY_AW { # [doc = "169: _UNLOCK_W_"] CLKCFG_KEY_UNLOCK = 169 , } impl From < CLKCFG_KEY_AW > for u8 { # [inline (always)] fn from (variant : CLKCFG_KEY_AW) -> Self { variant as _ } } impl crate :: FieldSpec for CLKCFG_KEY_AW { type Ux = u8 ; } # [doc = "Field `CLKCFG_KEY` writer - KEY to Allow State Change -- 0xA9"] pub type CLKCFG_KEY_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 8 , O , CLKCFG_KEY_AW > ; impl < 'a , REG , const O : u8 > CLKCFG_KEY_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "_UNLOCK_W_"] # [inline (always)] pub fn clkcfg_key_unlock (self) -> & 'a mut crate :: W < REG > { self . variant (CLKCFG_KEY_AW :: CLKCFG_KEY_UNLOCK) } } impl R { # [doc = "Bit 8 - Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz"] # [inline (always)] pub fn clkcfg_blockasync (& self) -> CLKCFG_BLOCKASYNC_R { CLKCFG_BLOCKASYNC_R :: new (((self . bits >> 8) & 1) != 0) } } impl W { # [doc = "Bit 8 - Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz"] # [inline (always)] # [must_use] pub fn clkcfg_blockasync (& mut self) -> CLKCFG_BLOCKASYNC_W <'_,  CLKCFG_SPEC , 8 > { CLKCFG_BLOCKASYNC_W :: new (self) } # [doc = "Bits 24:31 - KEY to Allow State Change -- 0xA9"] # [inline (always)] # [must_use] pub fn clkcfg_key (& mut self) -> CLKCFG_KEY_W < CLKCFG_SPEC , 24 > { CLKCFG_KEY_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Peripheral Clock Configuration Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clkcfg::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clkcfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CLKCFG_SPEC ; impl crate :: RegisterSpec for CLKCFG_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`clkcfg::R`](R) reader structure"] impl crate :: Readable for CLKCFG_SPEC { } # [doc = "`write(|w| ..)` method takes [`clkcfg::W`](W) writer structure"] impl crate :: Writable for CLKCFG_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets CLKCFG to value 0"] impl crate :: Resettable for CLKCFG_SPEC { const RESET_VALUE : Self :: Ux = 0 ; }
[INFO] [stdout]   |                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                 +++
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing
[INFO] [stdout]  --> src/uart0/clkcfg.rs:1:3657
[INFO] [stdout]   |
[INFO] [stdout] 1 | ...use] pub fn clkcfg_key (& mut self) -> CLKCFG_KEY_W < CLKCFG_SPEC , 24 > { CLKCFG_KEY_W :: new (self) } # [doc = r" Writes raw bit...
[INFO] [stdout]   |                            ^^^^^^^^^^     ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here
[INFO] [stdout]   |                            |
[INFO] [stdout]   |                            the lifetime is elided here
[INFO] [stdout]   |
[INFO] [stdout]   = help: the same lifetime is referred to in inconsistent ways, making the signature confusing
[INFO] [stdout] help: use `'_` for type paths
[INFO] [stdout]   |
[INFO] [stdout] 1 | # [doc = "Register `CLKCFG` reader"] pub type R = crate :: R < CLKCFG_SPEC > ; # [doc = "Register `CLKCFG` writer"] pub type W = crate :: W < CLKCFG_SPEC > ; # [doc = "Field `CLKCFG_BLOCKASYNC` reader - Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz"] pub type CLKCFG_BLOCKASYNC_R = crate :: BitReader < CLKCFG_BLOCKASYNC_A > ; # [doc = "Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CLKCFG_BLOCKASYNC_A { # [doc = "0: DISABLE"] CLKCFG_BLOCKASYNC_DISABLE = 0 , # [doc = "1: ENABLE"] CLKCFG_BLOCKASYNC_ENABLE = 1 , } impl From < CLKCFG_BLOCKASYNC_A > for bool { # [inline (always)] fn from (variant : CLKCFG_BLOCKASYNC_A) -> Self { variant as u8 != 0 } } impl CLKCFG_BLOCKASYNC_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CLKCFG_BLOCKASYNC_A { match self . bits { false => CLKCFG_BLOCKASYNC_A :: CLKCFG_BLOCKASYNC_DISABLE , true => CLKCFG_BLOCKASYNC_A :: CLKCFG_BLOCKASYNC_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_clkcfg_blockasync_disable (& self) -> bool { * self == CLKCFG_BLOCKASYNC_A :: CLKCFG_BLOCKASYNC_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_clkcfg_blockasync_enable (& self) -> bool { * self == CLKCFG_BLOCKASYNC_A :: CLKCFG_BLOCKASYNC_ENABLE } } # [doc = "Field `CLKCFG_BLOCKASYNC` writer - Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz"] pub type CLKCFG_BLOCKASYNC_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CLKCFG_BLOCKASYNC_A > ; impl < 'a , REG , const O : u8 > CLKCFG_BLOCKASYNC_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn clkcfg_blockasync_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CLKCFG_BLOCKASYNC_A :: CLKCFG_BLOCKASYNC_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn clkcfg_blockasync_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CLKCFG_BLOCKASYNC_A :: CLKCFG_BLOCKASYNC_ENABLE) } } # [doc = "KEY to Allow State Change -- 0xA9\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum CLKCFG_KEY_AW { # [doc = "169: _UNLOCK_W_"] CLKCFG_KEY_UNLOCK = 169 , } impl From < CLKCFG_KEY_AW > for u8 { # [inline (always)] fn from (variant : CLKCFG_KEY_AW) -> Self { variant as _ } } impl crate :: FieldSpec for CLKCFG_KEY_AW { type Ux = u8 ; } # [doc = "Field `CLKCFG_KEY` writer - KEY to Allow State Change -- 0xA9"] pub type CLKCFG_KEY_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 8 , O , CLKCFG_KEY_AW > ; impl < 'a , REG , const O : u8 > CLKCFG_KEY_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "_UNLOCK_W_"] # [inline (always)] pub fn clkcfg_key_unlock (self) -> & 'a mut crate :: W < REG > { self . variant (CLKCFG_KEY_AW :: CLKCFG_KEY_UNLOCK) } } impl R { # [doc = "Bit 8 - Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz"] # [inline (always)] pub fn clkcfg_blockasync (& self) -> CLKCFG_BLOCKASYNC_R { CLKCFG_BLOCKASYNC_R :: new (((self . bits >> 8) & 1) != 0) } } impl W { # [doc = "Bit 8 - Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz"] # [inline (always)] # [must_use] pub fn clkcfg_blockasync (& mut self) -> CLKCFG_BLOCKASYNC_W < CLKCFG_SPEC , 8 > { CLKCFG_BLOCKASYNC_W :: new (self) } # [doc = "Bits 24:31 - KEY to Allow State Change -- 0xA9"] # [inline (always)] # [must_use] pub fn clkcfg_key (& mut self) -> CLKCFG_KEY_W <'_,  CLKCFG_SPEC , 24 > { CLKCFG_KEY_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Peripheral Clock Configuration Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clkcfg::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clkcfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CLKCFG_SPEC ; impl crate :: RegisterSpec for CLKCFG_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`clkcfg::R`](R) reader structure"] impl crate :: Readable for CLKCFG_SPEC { } # [doc = "`write(|w| ..)` method takes [`clkcfg::W`](W) writer structure"] impl crate :: Writable for CLKCFG_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets CLKCFG to value 0"] impl crate :: Resettable for CLKCFG_SPEC { const RESET_VALUE : Self :: Ux = 0 ; }
[INFO] [stdout]   |                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                      +++
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing
[INFO] [stdout]  --> src/uart0/int_event0_iclr.rs:1:22360
[INFO] [stdout]   |
[INFO] [stdout] 1 | ..._iclr_brkerr (& mut self) -> INT_EVENT0_ICLR_BRKERR_W < INT_EVENT0_ICLR_SPEC , 3 > { INT_EVENT0_ICLR_BRKERR_W :: new (self) } # [d...
[INFO] [stdout]   |                  ^^^^^^^^^^     ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here
[INFO] [stdout]   |                  |
[INFO] [stdout]   |                  the lifetime is elided here
[INFO] [stdout]   |
[INFO] [stdout]   = help: the same lifetime is referred to in inconsistent ways, making the signature confusing
[INFO] [stdout] help: use `'_` for type paths
[INFO] [stdout]   |
[INFO] [stdout] 1 | # [doc = "Register `INT_EVENT0_ICLR` writer"] pub type W = crate :: W < INT_EVENT0_ICLR_SPEC > ; # [doc = "Clear UARTOUT Receive Time-Out Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_RTOUT_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_RTOUT_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_RTOUT_CLR = 1 , } impl From < INT_EVENT0_ICLR_RTOUT_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_RTOUT_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_RTOUT` writer - Clear UARTOUT Receive Time-Out Interrupt."] pub type INT_EVENT0_ICLR_RTOUT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_RTOUT_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_RTOUT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_rtout_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_RTOUT_AW :: INT_EVENT0_ICLR_RTOUT_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_rtout_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_RTOUT_AW :: INT_EVENT0_ICLR_RTOUT_CLR) } } # [doc = "Clear UART Framing Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_FRMERR_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_FRMERR_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_FRMERR_CLR = 1 , } impl From < INT_EVENT0_ICLR_FRMERR_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_FRMERR_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_FRMERR` writer - Clear UART Framing Error Interrupt."] pub type INT_EVENT0_ICLR_FRMERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_FRMERR_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_FRMERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_frmerr_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_FRMERR_AW :: INT_EVENT0_ICLR_FRMERR_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_frmerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_FRMERR_AW :: INT_EVENT0_ICLR_FRMERR_CLR) } } # [doc = "Clear UART Parity Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_PARERR_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_PARERR_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_PARERR_CLR = 1 , } impl From < INT_EVENT0_ICLR_PARERR_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_PARERR_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_PARERR` writer - Clear UART Parity Error Interrupt."] pub type INT_EVENT0_ICLR_PARERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_PARERR_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_PARERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_parerr_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_PARERR_AW :: INT_EVENT0_ICLR_PARERR_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_parerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_PARERR_AW :: INT_EVENT0_ICLR_PARERR_CLR) } } # [doc = "Clear UART Break Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_BRKERR_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_BRKERR_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_BRKERR_CLR = 1 , } impl From < INT_EVENT0_ICLR_BRKERR_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_BRKERR_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_BRKERR` writer - Clear UART Break Error Interrupt."] pub type INT_EVENT0_ICLR_BRKERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_BRKERR_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_BRKERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_brkerr_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_BRKERR_AW :: INT_EVENT0_ICLR_BRKERR_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_brkerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_BRKERR_AW :: INT_EVENT0_ICLR_BRKERR_CLR) } } # [doc = "Clear UART Receive Overrun Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_OVRERR_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_OVRERR_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_OVRERR_CLR = 1 , } impl From < INT_EVENT0_ICLR_OVRERR_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_OVRERR_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_OVRERR` writer - Clear UART Receive Overrun Error Interrupt."] pub type INT_EVENT0_ICLR_OVRERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_OVRERR_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_OVRERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_ovrerr_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_OVRERR_AW :: INT_EVENT0_ICLR_OVRERR_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_ovrerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_OVRERR_AW :: INT_EVENT0_ICLR_OVRERR_CLR) } } # [doc = "Clear Negative Edge on UARTxRXD Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_RXNE_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_RXNE_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_RXNE_CLR = 1 , } impl From < INT_EVENT0_ICLR_RXNE_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_RXNE_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_RXNE` writer - Clear Negative Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_ICLR_RXNE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_RXNE_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_RXNE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_rxne_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_RXNE_AW :: INT_EVENT0_ICLR_RXNE_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_rxne_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_RXNE_AW :: INT_EVENT0_ICLR_RXNE_CLR) } } # [doc = "Clear Positive Edge on UARTxRXD Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_RXPE_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_RXPE_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_RXPE_CLR = 1 , } impl From < INT_EVENT0_ICLR_RXPE_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_RXPE_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_RXPE` writer - Clear Positive Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_ICLR_RXPE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_RXPE_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_RXPE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_rxpe_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_RXPE_AW :: INT_EVENT0_ICLR_RXPE_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_rxpe_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_RXPE_AW :: INT_EVENT0_ICLR_RXPE_CLR) } } # [doc = "Clear LIN Capture 0 / Match Interrupt .\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_LINC0_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_LINC0_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_LINC0_CLR = 1 , } impl From < INT_EVENT0_ICLR_LINC0_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_LINC0_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_LINC0` writer - Clear LIN Capture 0 / Match Interrupt ."] pub type INT_EVENT0_ICLR_LINC0_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_LINC0_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_LINC0_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_linc0_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_LINC0_AW :: INT_EVENT0_ICLR_LINC0_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_linc0_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_LINC0_AW :: INT_EVENT0_ICLR_LINC0_CLR) } } # [doc = "Clear LIN Capture 1 Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_LINC1_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_LINC1_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_LINC1_CLR = 1 , } impl From < INT_EVENT0_ICLR_LINC1_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_LINC1_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_LINC1` writer - Clear LIN Capture 1 Interrupt."] pub type INT_EVENT0_ICLR_LINC1_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_LINC1_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_LINC1_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_linc1_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_LINC1_AW :: INT_EVENT0_ICLR_LINC1_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_linc1_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_LINC1_AW :: INT_EVENT0_ICLR_LINC1_CLR) } } # [doc = "Clear LIN Hardware Counter Overflow Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_LINOVF_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_LINOVF_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_LINOVF_CLR = 1 , } impl From < INT_EVENT0_ICLR_LINOVF_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_LINOVF_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_LINOVF` writer - Clear LIN Hardware Counter Overflow Interrupt."] pub type INT_EVENT0_ICLR_LINOVF_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_LINOVF_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_LINOVF_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_linovf_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_LINOVF_AW :: INT_EVENT0_ICLR_LINOVF_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_linovf_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_LINOVF_AW :: INT_EVENT0_ICLR_LINOVF_CLR) } } # [doc = "Clear UART Receive Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_RXINT_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_RXINT_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_RXINT_CLR = 1 , } impl From < INT_EVENT0_ICLR_RXINT_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_RXINT_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_RXINT` writer - Clear UART Receive Interrupt."] pub type INT_EVENT0_ICLR_RXINT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_RXINT_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_RXINT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_rxint_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_RXINT_AW :: INT_EVENT0_ICLR_RXINT_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_rxint_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_RXINT_AW :: INT_EVENT0_ICLR_RXINT_CLR) } } # [doc = "Clear UART Transmit Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_TXINT_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_TXINT_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_TXINT_CLR = 1 , } impl From < INT_EVENT0_ICLR_TXINT_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_TXINT_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_TXINT` writer - Clear UART Transmit Interrupt."] pub type INT_EVENT0_ICLR_TXINT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_TXINT_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_TXINT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_txint_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_TXINT_AW :: INT_EVENT0_ICLR_TXINT_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_txint_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_TXINT_AW :: INT_EVENT0_ICLR_TXINT_CLR) } } # [doc = "Clear UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_EOT_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_EOT_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_EOT_CLR = 1 , } impl From < INT_EVENT0_ICLR_EOT_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_EOT_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_EOT` writer - Clear UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] pub type INT_EVENT0_ICLR_EOT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_EOT_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_EOT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_eot_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_EOT_AW :: INT_EVENT0_ICLR_EOT_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_eot_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_EOT_AW :: INT_EVENT0_ICLR_EOT_CLR) } } # [doc = "Clear Address Match Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_ADDR_MATCH_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_ADDR_MATCH_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_ADDR_MATCH_CLR = 1 , } impl From < INT_EVENT0_ICLR_ADDR_MATCH_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_ADDR_MATCH_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_ADDR_MATCH` writer - Clear Address Match Interrupt."] pub type INT_EVENT0_ICLR_ADDR_MATCH_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_ADDR_MATCH_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_ADDR_MATCH_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_addr_match_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_ADDR_MATCH_AW :: INT_EVENT0_ICLR_ADDR_MATCH_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_addr_match_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_ADDR_MATCH_AW :: INT_EVENT0_ICLR_ADDR_MATCH_CLR) } } # [doc = "Clear UART Clear to Send Modem Interrupt. 0 = Interrupt disabled\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_CTS_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_CTS_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_CTS_CLR = 1 , } impl From < INT_EVENT0_ICLR_CTS_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_CTS_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_CTS` writer - Clear UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] pub type INT_EVENT0_ICLR_CTS_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_CTS_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_CTS_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_cts_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_CTS_AW :: INT_EVENT0_ICLR_CTS_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_cts_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_CTS_AW :: INT_EVENT0_ICLR_CTS_CLR) } } # [doc = "Clear DMA Done on RX Event Channel\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_DMA_DONE_RX_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_DMA_DONE_RX_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_DMA_DONE_RX_CLR = 1 , } impl From < INT_EVENT0_ICLR_DMA_DONE_RX_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_DMA_DONE_RX_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_DMA_DONE_RX` writer - Clear DMA Done on RX Event Channel"] pub type INT_EVENT0_ICLR_DMA_DONE_RX_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_DMA_DONE_RX_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_DMA_DONE_RX_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_dma_done_rx_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_DMA_DONE_RX_AW :: INT_EVENT0_ICLR_DMA_DONE_RX_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_dma_done_rx_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_DMA_DONE_RX_AW :: INT_EVENT0_ICLR_DMA_DONE_RX_CLR) } } # [doc = "Clear DMA Done on TX Event Channel\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_DMA_DONE_TX_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_DMA_DONE_TX_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_DMA_DONE_TX_CLR = 1 , } impl From < INT_EVENT0_ICLR_DMA_DONE_TX_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_DMA_DONE_TX_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_DMA_DONE_TX` writer - Clear DMA Done on TX Event Channel"] pub type INT_EVENT0_ICLR_DMA_DONE_TX_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_DMA_DONE_TX_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_DMA_DONE_TX_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_dma_done_tx_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_DMA_DONE_TX_AW :: INT_EVENT0_ICLR_DMA_DONE_TX_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_dma_done_tx_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_DMA_DONE_TX_AW :: INT_EVENT0_ICLR_DMA_DONE_TX_CLR) } } # [doc = "Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_NERR_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_NERR_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_NERR_CLR = 1 , } impl From < INT_EVENT0_ICLR_NERR_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_NERR_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_NERR` writer - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] pub type INT_EVENT0_ICLR_NERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_NERR_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_NERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_nerr_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_NERR_AW :: INT_EVENT0_ICLR_NERR_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_nerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_NERR_AW :: INT_EVENT0_ICLR_NERR_CLR) } } impl W { # [doc = "Bit 0 - Clear UARTOUT Receive Time-Out Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iclr_rtout (& mut self) -> INT_EVENT0_ICLR_RTOUT_W < INT_EVENT0_ICLR_SPEC , 0 > { INT_EVENT0_ICLR_RTOUT_W :: new (self) } # [doc = "Bit 1 - Clear UART Framing Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iclr_frmerr (& mut self) -> INT_EVENT0_ICLR_FRMERR_W < INT_EVENT0_ICLR_SPEC , 1 > { INT_EVENT0_ICLR_FRMERR_W :: new (self) } # [doc = "Bit 2 - Clear UART Parity Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iclr_parerr (& mut self) -> INT_EVENT0_ICLR_PARERR_W < INT_EVENT0_ICLR_SPEC , 2 > { INT_EVENT0_ICLR_PARERR_W :: new (self) } # [doc = "Bit 3 - Clear UART Break Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iclr_brkerr (& mut self) -> INT_EVENT0_ICLR_BRKERR_W <'_,  INT_EVENT0_ICLR_SPEC , 3 > { INT_EVENT0_ICLR_BRKERR_W :: new (self) } # [doc = "Bit 4 - Clear UART Receive Overrun Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iclr_ovrerr (& mut self) -> INT_EVENT0_ICLR_OVRERR_W < INT_EVENT0_ICLR_SPEC , 4 > { INT_EVENT0_ICLR_OVRERR_W :: new (self) } # [doc = "Bit 5 - Clear Negative Edge on UARTxRXD Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iclr_rxne (& mut self) -> INT_EVENT0_ICLR_RXNE_W < INT_EVENT0_ICLR_SPEC , 5 > { INT_EVENT0_ICLR_RXNE_W :: new (self) } # [doc = "Bit 6 - Clear Positive Edge on UARTxRXD Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iclr_rxpe (& mut self) -> INT_EVENT0_ICLR_RXPE_W < INT_EVENT0_ICLR_SPEC , 6 > { INT_EVENT0_ICLR_RXPE_W :: new (self) } # [doc = "Bit 7 - Clear LIN Capture 0 / Match Interrupt ."] # [inline (always)] # [must_use] pub fn int_event0_iclr_linc0 (& mut self) -> INT_EVENT0_ICLR_LINC0_W < INT_EVENT0_ICLR_SPEC , 7 > { INT_EVENT0_ICLR_LINC0_W :: new (self) } # [doc = "Bit 8 - Clear LIN Capture 1 Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iclr_linc1 (& mut self) -> INT_EVENT0_ICLR_LINC1_W < INT_EVENT0_ICLR_SPEC , 8 > { INT_EVENT0_ICLR_LINC1_W :: new (self) } # [doc = "Bit 9 - Clear LIN Hardware Counter Overflow Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iclr_linovf (& mut self) -> INT_EVENT0_ICLR_LINOVF_W < INT_EVENT0_ICLR_SPEC , 9 > { INT_EVENT0_ICLR_LINOVF_W :: new (self) } # [doc = "Bit 10 - Clear UART Receive Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iclr_rxint (& mut self) -> INT_EVENT0_ICLR_RXINT_W < INT_EVENT0_ICLR_SPEC , 10 > { INT_EVENT0_ICLR_RXINT_W :: new (self) } # [doc = "Bit 11 - Clear UART Transmit Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iclr_txint (& mut self) -> INT_EVENT0_ICLR_TXINT_W < INT_EVENT0_ICLR_SPEC , 11 > { INT_EVENT0_ICLR_TXINT_W :: new (self) } # [doc = "Bit 12 - Clear UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] # [inline (always)] # [must_use] pub fn int_event0_iclr_eot (& mut self) -> INT_EVENT0_ICLR_EOT_W < INT_EVENT0_ICLR_SPEC , 12 > { INT_EVENT0_ICLR_EOT_W :: new (self) } # [doc = "Bit 13 - Clear Address Match Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iclr_addr_match (& mut self) -> INT_EVENT0_ICLR_ADDR_MATCH_W < INT_EVENT0_ICLR_SPEC , 13 > { INT_EVENT0_ICLR_ADDR_MATCH_W :: new (self) } # [doc = "Bit 14 - Clear UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] # [inline (always)] # [must_use] pub fn int_event0_iclr_cts (& mut self) -> INT_EVENT0_ICLR_CTS_W < INT_EVENT0_ICLR_SPEC , 14 > { INT_EVENT0_ICLR_CTS_W :: new (self) } # [doc = "Bit 15 - Clear DMA Done on RX Event Channel"] # [inline (always)] # [must_use] pub fn int_event0_iclr_dma_done_rx (& mut self) -> INT_EVENT0_ICLR_DMA_DONE_RX_W < INT_EVENT0_ICLR_SPEC , 15 > { INT_EVENT0_ICLR_DMA_DONE_RX_W :: new (self) } # [doc = "Bit 16 - Clear DMA Done on TX Event Channel"] # [inline (always)] # [must_use] pub fn int_event0_iclr_dma_done_tx (& mut self) -> INT_EVENT0_ICLR_DMA_DONE_TX_W < INT_EVENT0_ICLR_SPEC , 16 > { INT_EVENT0_ICLR_DMA_DONE_TX_W :: new (self) } # [doc = "Bit 17 - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] # [inline (always)] # [must_use] pub fn int_event0_iclr_nerr (& mut self) -> INT_EVENT0_ICLR_NERR_W < INT_EVENT0_ICLR_SPEC , 17 > { INT_EVENT0_ICLR_NERR_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Interrupt clear\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_event0_iclr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct INT_EVENT0_ICLR_SPEC ; impl crate :: RegisterSpec for INT_EVENT0_ICLR_SPEC { type Ux = u32 ; } # [doc = "`write(|w| ..)` method takes [`int_event0_iclr::W`](W) writer structure"] impl crate :: Writable for INT_EVENT0_ICLR_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets INT_EVENT0_ICLR to value 0"] impl crate :: Resettable for INT_EVENT0_ICLR_SPEC { const RESET_VALUE : Self :: Ux = 0 ; }
[INFO] [stdout]   |                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                 +++
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing
[INFO] [stdout]  --> src/uart0/clkdiv.rs:1:4791
[INFO] [stdout]   |
[INFO] [stdout] 1 | ...e] pub fn clkdiv_ratio (& mut self) -> CLKDIV_RATIO_W < CLKDIV_SPEC , 0 > { CLKDIV_RATIO_W :: new (self) } # [doc = r" Writes raw ...
[INFO] [stdout]   |                            ^^^^^^^^^^     ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here
[INFO] [stdout]   |                            |
[INFO] [stdout]   |                            the lifetime is elided here
[INFO] [stdout]   |
[INFO] [stdout]   = help: the same lifetime is referred to in inconsistent ways, making the signature confusing
[INFO] [stdout] help: use `'_` for type paths
[INFO] [stdout]   |
[INFO] [stdout] 1 | # [doc = "Register `CLKDIV` reader"] pub type R = crate :: R < CLKDIV_SPEC > ; # [doc = "Register `CLKDIV` writer"] pub type W = crate :: W < CLKDIV_SPEC > ; # [doc = "Field `CLKDIV_RATIO` reader - Selects divide ratio of module clock"] pub type CLKDIV_RATIO_R = crate :: FieldReader < CLKDIV_RATIO_A > ; # [doc = "Selects divide ratio of module clock\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum CLKDIV_RATIO_A { # [doc = "0: DIV_BY_1"] CLKDIV_RATIO_DIV_BY_1 = 0 , # [doc = "1: DIV_BY_2"] CLKDIV_RATIO_DIV_BY_2 = 1 , # [doc = "2: DIV_BY_3"] CLKDIV_RATIO_DIV_BY_3 = 2 , # [doc = "3: DIV_BY_4"] CLKDIV_RATIO_DIV_BY_4 = 3 , # [doc = "4: DIV_BY_5"] CLKDIV_RATIO_DIV_BY_5 = 4 , # [doc = "5: DIV_BY_6"] CLKDIV_RATIO_DIV_BY_6 = 5 , # [doc = "6: DIV_BY_7"] CLKDIV_RATIO_DIV_BY_7 = 6 , # [doc = "7: DIV_BY_8"] CLKDIV_RATIO_DIV_BY_8 = 7 , } impl From < CLKDIV_RATIO_A > for u8 { # [inline (always)] fn from (variant : CLKDIV_RATIO_A) -> Self { variant as _ } } impl crate :: FieldSpec for CLKDIV_RATIO_A { type Ux = u8 ; } impl CLKDIV_RATIO_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CLKDIV_RATIO_A { match self . bits { 0 => CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_1 , 1 => CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_2 , 2 => CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_3 , 3 => CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_4 , 4 => CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_5 , 5 => CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_6 , 6 => CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_7 , 7 => CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_8 , _ => unreachable ! () , } } # [doc = "DIV_BY_1"] # [inline (always)] pub fn is_clkdiv_ratio_div_by_1 (& self) -> bool { * self == CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_1 } # [doc = "DIV_BY_2"] # [inline (always)] pub fn is_clkdiv_ratio_div_by_2 (& self) -> bool { * self == CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_2 } # [doc = "DIV_BY_3"] # [inline (always)] pub fn is_clkdiv_ratio_div_by_3 (& self) -> bool { * self == CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_3 } # [doc = "DIV_BY_4"] # [inline (always)] pub fn is_clkdiv_ratio_div_by_4 (& self) -> bool { * self == CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_4 } # [doc = "DIV_BY_5"] # [inline (always)] pub fn is_clkdiv_ratio_div_by_5 (& self) -> bool { * self == CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_5 } # [doc = "DIV_BY_6"] # [inline (always)] pub fn is_clkdiv_ratio_div_by_6 (& self) -> bool { * self == CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_6 } # [doc = "DIV_BY_7"] # [inline (always)] pub fn is_clkdiv_ratio_div_by_7 (& self) -> bool { * self == CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_7 } # [doc = "DIV_BY_8"] # [inline (always)] pub fn is_clkdiv_ratio_div_by_8 (& self) -> bool { * self == CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_8 } } # [doc = "Field `CLKDIV_RATIO` writer - Selects divide ratio of module clock"] pub type CLKDIV_RATIO_W < 'a , REG , const O : u8 > = crate :: FieldWriterSafe < 'a , REG , 3 , O , CLKDIV_RATIO_A > ; impl < 'a , REG , const O : u8 > CLKDIV_RATIO_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "DIV_BY_1"] # [inline (always)] pub fn clkdiv_ratio_div_by_1 (self) -> & 'a mut crate :: W < REG > { self . variant (CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_1) } # [doc = "DIV_BY_2"] # [inline (always)] pub fn clkdiv_ratio_div_by_2 (self) -> & 'a mut crate :: W < REG > { self . variant (CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_2) } # [doc = "DIV_BY_3"] # [inline (always)] pub fn clkdiv_ratio_div_by_3 (self) -> & 'a mut crate :: W < REG > { self . variant (CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_3) } # [doc = "DIV_BY_4"] # [inline (always)] pub fn clkdiv_ratio_div_by_4 (self) -> & 'a mut crate :: W < REG > { self . variant (CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_4) } # [doc = "DIV_BY_5"] # [inline (always)] pub fn clkdiv_ratio_div_by_5 (self) -> & 'a mut crate :: W < REG > { self . variant (CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_5) } # [doc = "DIV_BY_6"] # [inline (always)] pub fn clkdiv_ratio_div_by_6 (self) -> & 'a mut crate :: W < REG > { self . variant (CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_6) } # [doc = "DIV_BY_7"] # [inline (always)] pub fn clkdiv_ratio_div_by_7 (self) -> & 'a mut crate :: W < REG > { self . variant (CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_7) } # [doc = "DIV_BY_8"] # [inline (always)] pub fn clkdiv_ratio_div_by_8 (self) -> & 'a mut crate :: W < REG > { self . variant (CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_8) } } impl R { # [doc = "Bits 0:2 - Selects divide ratio of module clock"] # [inline (always)] pub fn clkdiv_ratio (& self) -> CLKDIV_RATIO_R { CLKDIV_RATIO_R :: new ((self . bits & 7) as u8) } } impl W { # [doc = "Bits 0:2 - Selects divide ratio of module clock"] # [inline (always)] # [must_use] pub fn clkdiv_ratio (& mut self) -> CLKDIV_RATIO_W <'_,  CLKDIV_SPEC , 0 > { CLKDIV_RATIO_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Clock Divider\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clkdiv::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clkdiv::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CLKDIV_SPEC ; impl crate :: RegisterSpec for CLKDIV_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`clkdiv::R`](R) reader structure"] impl crate :: Readable for CLKDIV_SPEC { } # [doc = "`write(|w| ..)` method takes [`clkdiv::W`](W) writer structure"] impl crate :: Writable for CLKDIV_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets CLKDIV to value 0"] impl crate :: Resettable for CLKDIV_SPEC { const RESET_VALUE : Self :: Ux = 0 ; }
[INFO] [stdout]   |                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                      +++
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing
[INFO] [stdout]  --> src/uart0/clksel.rs:1:6426
[INFO] [stdout]   |
[INFO] [stdout] 1 | ... fn clksel_lfclk_sel (& mut self) -> CLKSEL_LFCLK_SEL_W < CLKSEL_SPEC , 1 > { CLKSEL_LFCLK_SEL_W :: new (self) } # [doc = "Bit 2 -...
[INFO] [stdout]   |                          ^^^^^^^^^^     ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here
[INFO] [stdout]   |                          |
[INFO] [stdout]   |                          the lifetime is elided here
[INFO] [stdout]   |
[INFO] [stdout]   = help: the same lifetime is referred to in inconsistent ways, making the signature confusing
[INFO] [stdout] help: use `'_` for type paths
[INFO] [stdout]   |
[INFO] [stdout] 1 | # [doc = "Register `CLKSEL` reader"] pub type R = crate :: R < CLKSEL_SPEC > ; # [doc = "Register `CLKSEL` writer"] pub type W = crate :: W < CLKSEL_SPEC > ; # [doc = "Field `CLKSEL_LFCLK_SEL` reader - Selects LFCLK as clock source if enabled"] pub type CLKSEL_LFCLK_SEL_R = crate :: BitReader < CLKSEL_LFCLK_SEL_A > ; # [doc = "Selects LFCLK as clock source if enabled\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CLKSEL_LFCLK_SEL_A { # [doc = "0: DISABLE"] CLKSEL_LFCLK_SEL_DISABLE = 0 , # [doc = "1: ENABLE"] CLKSEL_LFCLK_SEL_ENABLE = 1 , } impl From < CLKSEL_LFCLK_SEL_A > for bool { # [inline (always)] fn from (variant : CLKSEL_LFCLK_SEL_A) -> Self { variant as u8 != 0 } } impl CLKSEL_LFCLK_SEL_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CLKSEL_LFCLK_SEL_A { match self . bits { false => CLKSEL_LFCLK_SEL_A :: CLKSEL_LFCLK_SEL_DISABLE , true => CLKSEL_LFCLK_SEL_A :: CLKSEL_LFCLK_SEL_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_clksel_lfclk_sel_disable (& self) -> bool { * self == CLKSEL_LFCLK_SEL_A :: CLKSEL_LFCLK_SEL_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_clksel_lfclk_sel_enable (& self) -> bool { * self == CLKSEL_LFCLK_SEL_A :: CLKSEL_LFCLK_SEL_ENABLE } } # [doc = "Field `CLKSEL_LFCLK_SEL` writer - Selects LFCLK as clock source if enabled"] pub type CLKSEL_LFCLK_SEL_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CLKSEL_LFCLK_SEL_A > ; impl < 'a , REG , const O : u8 > CLKSEL_LFCLK_SEL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn clksel_lfclk_sel_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CLKSEL_LFCLK_SEL_A :: CLKSEL_LFCLK_SEL_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn clksel_lfclk_sel_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CLKSEL_LFCLK_SEL_A :: CLKSEL_LFCLK_SEL_ENABLE) } } # [doc = "Field `CLKSEL_MFCLK_SEL` reader - Selects MFCLK as clock source if enabled"] pub type CLKSEL_MFCLK_SEL_R = crate :: BitReader < CLKSEL_MFCLK_SEL_A > ; # [doc = "Selects MFCLK as clock source if enabled\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CLKSEL_MFCLK_SEL_A { # [doc = "0: DISABLE"] CLKSEL_MFCLK_SEL_DISABLE = 0 , # [doc = "1: ENABLE"] CLKSEL_MFCLK_SEL_ENABLE = 1 , } impl From < CLKSEL_MFCLK_SEL_A > for bool { # [inline (always)] fn from (variant : CLKSEL_MFCLK_SEL_A) -> Self { variant as u8 != 0 } } impl CLKSEL_MFCLK_SEL_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CLKSEL_MFCLK_SEL_A { match self . bits { false => CLKSEL_MFCLK_SEL_A :: CLKSEL_MFCLK_SEL_DISABLE , true => CLKSEL_MFCLK_SEL_A :: CLKSEL_MFCLK_SEL_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_clksel_mfclk_sel_disable (& self) -> bool { * self == CLKSEL_MFCLK_SEL_A :: CLKSEL_MFCLK_SEL_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_clksel_mfclk_sel_enable (& self) -> bool { * self == CLKSEL_MFCLK_SEL_A :: CLKSEL_MFCLK_SEL_ENABLE } } # [doc = "Field `CLKSEL_MFCLK_SEL` writer - Selects MFCLK as clock source if enabled"] pub type CLKSEL_MFCLK_SEL_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CLKSEL_MFCLK_SEL_A > ; impl < 'a , REG , const O : u8 > CLKSEL_MFCLK_SEL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn clksel_mfclk_sel_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CLKSEL_MFCLK_SEL_A :: CLKSEL_MFCLK_SEL_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn clksel_mfclk_sel_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CLKSEL_MFCLK_SEL_A :: CLKSEL_MFCLK_SEL_ENABLE) } } # [doc = "Field `CLKSEL_BUSCLK_SEL` reader - Selects BUS CLK as clock source if enabled"] pub type CLKSEL_BUSCLK_SEL_R = crate :: BitReader < CLKSEL_BUSCLK_SEL_A > ; # [doc = "Selects BUS CLK as clock source if enabled\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CLKSEL_BUSCLK_SEL_A { # [doc = "0: DISABLE"] CLKSEL_BUSCLK_SEL_DISABLE = 0 , # [doc = "1: ENABLE"] CLKSEL_BUSCLK_SEL_ENABLE = 1 , } impl From < CLKSEL_BUSCLK_SEL_A > for bool { # [inline (always)] fn from (variant : CLKSEL_BUSCLK_SEL_A) -> Self { variant as u8 != 0 } } impl CLKSEL_BUSCLK_SEL_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CLKSEL_BUSCLK_SEL_A { match self . bits { false => CLKSEL_BUSCLK_SEL_A :: CLKSEL_BUSCLK_SEL_DISABLE , true => CLKSEL_BUSCLK_SEL_A :: CLKSEL_BUSCLK_SEL_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_clksel_busclk_sel_disable (& self) -> bool { * self == CLKSEL_BUSCLK_SEL_A :: CLKSEL_BUSCLK_SEL_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_clksel_busclk_sel_enable (& self) -> bool { * self == CLKSEL_BUSCLK_SEL_A :: CLKSEL_BUSCLK_SEL_ENABLE } } # [doc = "Field `CLKSEL_BUSCLK_SEL` writer - Selects BUS CLK as clock source if enabled"] pub type CLKSEL_BUSCLK_SEL_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CLKSEL_BUSCLK_SEL_A > ; impl < 'a , REG , const O : u8 > CLKSEL_BUSCLK_SEL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn clksel_busclk_sel_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CLKSEL_BUSCLK_SEL_A :: CLKSEL_BUSCLK_SEL_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn clksel_busclk_sel_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CLKSEL_BUSCLK_SEL_A :: CLKSEL_BUSCLK_SEL_ENABLE) } } impl R { # [doc = "Bit 1 - Selects LFCLK as clock source if enabled"] # [inline (always)] pub fn clksel_lfclk_sel (& self) -> CLKSEL_LFCLK_SEL_R { CLKSEL_LFCLK_SEL_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - Selects MFCLK as clock source if enabled"] # [inline (always)] pub fn clksel_mfclk_sel (& self) -> CLKSEL_MFCLK_SEL_R { CLKSEL_MFCLK_SEL_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - Selects BUS CLK as clock source if enabled"] # [inline (always)] pub fn clksel_busclk_sel (& self) -> CLKSEL_BUSCLK_SEL_R { CLKSEL_BUSCLK_SEL_R :: new (((self . bits >> 3) & 1) != 0) } } impl W { # [doc = "Bit 1 - Selects LFCLK as clock source if enabled"] # [inline (always)] # [must_use] pub fn clksel_lfclk_sel (& mut self) -> CLKSEL_LFCLK_SEL_W <'_,  CLKSEL_SPEC , 1 > { CLKSEL_LFCLK_SEL_W :: new (self) } # [doc = "Bit 2 - Selects MFCLK as clock source if enabled"] # [inline (always)] # [must_use] pub fn clksel_mfclk_sel (& mut self) -> CLKSEL_MFCLK_SEL_W < CLKSEL_SPEC , 2 > { CLKSEL_MFCLK_SEL_W :: new (self) } # [doc = "Bit 3 - Selects BUS CLK as clock source if enabled"] # [inline (always)] # [must_use] pub fn clksel_busclk_sel (& mut self) -> CLKSEL_BUSCLK_SEL_W < CLKSEL_SPEC , 3 > { CLKSEL_BUSCLK_SEL_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Clock Select for Ultra Low Power peripherals\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clksel::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clksel::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CLKSEL_SPEC ; impl crate :: RegisterSpec for CLKSEL_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`clksel::R`](R) reader structure"] impl crate :: Readable for CLKSEL_SPEC { } # [doc = "`write(|w| ..)` method takes [`clksel::W`](W) writer structure"] impl crate :: Writable for CLKSEL_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets CLKSEL to value 0"] impl crate :: Resettable for CLKSEL_SPEC { const RESET_VALUE : Self :: Ux = 0 ; }
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                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                           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[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing
[INFO] [stdout]  --> src/uart0/int_event0_iclr.rs:1:22600
[INFO] [stdout]   |
[INFO] [stdout] 1 | ..._iclr_ovrerr (& mut self) -> INT_EVENT0_ICLR_OVRERR_W < INT_EVENT0_ICLR_SPEC , 4 > { INT_EVENT0_ICLR_OVRERR_W :: new (self) } # [d...
[INFO] [stdout]   |                  ^^^^^^^^^^     ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here
[INFO] [stdout]   |                  |
[INFO] [stdout]   |                  the lifetime is elided here
[INFO] [stdout]   |
[INFO] [stdout]   = help: the same lifetime is referred to in inconsistent ways, making the signature confusing
[INFO] [stdout] help: use `'_` for type paths
[INFO] [stdout]   |
[INFO] [stdout] 1 | # [doc = "Register `INT_EVENT0_ICLR` writer"] pub type W = crate :: W < INT_EVENT0_ICLR_SPEC > ; # [doc = "Clear UARTOUT Receive Time-Out Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_RTOUT_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_RTOUT_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_RTOUT_CLR = 1 , } impl From < INT_EVENT0_ICLR_RTOUT_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_RTOUT_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_RTOUT` writer - Clear UARTOUT Receive Time-Out Interrupt."] pub type INT_EVENT0_ICLR_RTOUT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_RTOUT_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_RTOUT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_rtout_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_RTOUT_AW :: INT_EVENT0_ICLR_RTOUT_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_rtout_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_RTOUT_AW :: INT_EVENT0_ICLR_RTOUT_CLR) } } # [doc = "Clear UART Framing Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_FRMERR_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_FRMERR_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_FRMERR_CLR = 1 , } impl From < INT_EVENT0_ICLR_FRMERR_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_FRMERR_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_FRMERR` writer - Clear UART Framing Error Interrupt."] pub type INT_EVENT0_ICLR_FRMERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_FRMERR_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_FRMERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_frmerr_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_FRMERR_AW :: INT_EVENT0_ICLR_FRMERR_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_frmerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_FRMERR_AW :: INT_EVENT0_ICLR_FRMERR_CLR) } } # [doc = "Clear UART Parity Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_PARERR_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_PARERR_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_PARERR_CLR = 1 , } impl From < INT_EVENT0_ICLR_PARERR_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_PARERR_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_PARERR` writer - Clear UART Parity Error Interrupt."] pub type INT_EVENT0_ICLR_PARERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_PARERR_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_PARERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_parerr_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_PARERR_AW :: INT_EVENT0_ICLR_PARERR_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_parerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_PARERR_AW :: INT_EVENT0_ICLR_PARERR_CLR) } } # [doc = "Clear UART Break Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_BRKERR_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_BRKERR_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_BRKERR_CLR = 1 , } impl From < INT_EVENT0_ICLR_BRKERR_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_BRKERR_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_BRKERR` writer - Clear UART Break Error Interrupt."] pub type INT_EVENT0_ICLR_BRKERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_BRKERR_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_BRKERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_brkerr_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_BRKERR_AW :: INT_EVENT0_ICLR_BRKERR_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_brkerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_BRKERR_AW :: INT_EVENT0_ICLR_BRKERR_CLR) } } # [doc = "Clear UART Receive Overrun Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_OVRERR_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_OVRERR_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_OVRERR_CLR = 1 , } impl From < INT_EVENT0_ICLR_OVRERR_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_OVRERR_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_OVRERR` writer - Clear UART Receive Overrun Error Interrupt."] pub type INT_EVENT0_ICLR_OVRERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_OVRERR_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_OVRERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_ovrerr_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_OVRERR_AW :: INT_EVENT0_ICLR_OVRERR_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_ovrerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_OVRERR_AW :: INT_EVENT0_ICLR_OVRERR_CLR) } } # [doc = "Clear Negative Edge on UARTxRXD Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_RXNE_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_RXNE_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_RXNE_CLR = 1 , } impl From < INT_EVENT0_ICLR_RXNE_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_RXNE_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_RXNE` writer - Clear Negative Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_ICLR_RXNE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_RXNE_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_RXNE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_rxne_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_RXNE_AW :: INT_EVENT0_ICLR_RXNE_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_rxne_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_RXNE_AW :: INT_EVENT0_ICLR_RXNE_CLR) } } # [doc = "Clear Positive Edge on UARTxRXD Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_RXPE_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_RXPE_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_RXPE_CLR = 1 , } impl From < INT_EVENT0_ICLR_RXPE_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_RXPE_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_RXPE` writer - Clear Positive Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_ICLR_RXPE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_RXPE_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_RXPE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_rxpe_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_RXPE_AW :: INT_EVENT0_ICLR_RXPE_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_rxpe_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_RXPE_AW :: INT_EVENT0_ICLR_RXPE_CLR) } } # [doc = "Clear LIN Capture 0 / Match Interrupt .\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_LINC0_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_LINC0_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_LINC0_CLR = 1 , } impl From < INT_EVENT0_ICLR_LINC0_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_LINC0_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_LINC0` writer - Clear LIN Capture 0 / Match Interrupt ."] pub type INT_EVENT0_ICLR_LINC0_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_LINC0_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_LINC0_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_linc0_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_LINC0_AW :: INT_EVENT0_ICLR_LINC0_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_linc0_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_LINC0_AW :: INT_EVENT0_ICLR_LINC0_CLR) } } # [doc = "Clear LIN Capture 1 Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_LINC1_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_LINC1_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_LINC1_CLR = 1 , } impl From < INT_EVENT0_ICLR_LINC1_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_LINC1_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_LINC1` writer - Clear LIN Capture 1 Interrupt."] pub type INT_EVENT0_ICLR_LINC1_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_LINC1_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_LINC1_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_linc1_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_LINC1_AW :: INT_EVENT0_ICLR_LINC1_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_linc1_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_LINC1_AW :: INT_EVENT0_ICLR_LINC1_CLR) } } # [doc = "Clear LIN Hardware Counter Overflow Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_LINOVF_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_LINOVF_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_LINOVF_CLR = 1 , } impl From < INT_EVENT0_ICLR_LINOVF_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_LINOVF_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_LINOVF` writer - Clear LIN Hardware Counter Overflow Interrupt."] pub type INT_EVENT0_ICLR_LINOVF_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_LINOVF_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_LINOVF_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_linovf_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_LINOVF_AW :: INT_EVENT0_ICLR_LINOVF_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_linovf_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_LINOVF_AW :: INT_EVENT0_ICLR_LINOVF_CLR) } } # [doc = "Clear UART Receive Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_RXINT_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_RXINT_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_RXINT_CLR = 1 , } impl From < INT_EVENT0_ICLR_RXINT_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_RXINT_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_RXINT` writer - Clear UART Receive Interrupt."] pub type INT_EVENT0_ICLR_RXINT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_RXINT_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_RXINT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_rxint_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_RXINT_AW :: INT_EVENT0_ICLR_RXINT_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_rxint_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_RXINT_AW :: INT_EVENT0_ICLR_RXINT_CLR) } } # [doc = "Clear UART Transmit Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_TXINT_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_TXINT_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_TXINT_CLR = 1 , } impl From < INT_EVENT0_ICLR_TXINT_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_TXINT_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_TXINT` writer - Clear UART Transmit Interrupt."] pub type INT_EVENT0_ICLR_TXINT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_TXINT_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_TXINT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_txint_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_TXINT_AW :: INT_EVENT0_ICLR_TXINT_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_txint_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_TXINT_AW :: INT_EVENT0_ICLR_TXINT_CLR) } } # [doc = "Clear UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_EOT_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_EOT_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_EOT_CLR = 1 , } impl From < INT_EVENT0_ICLR_EOT_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_EOT_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_EOT` writer - Clear UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] pub type INT_EVENT0_ICLR_EOT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_EOT_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_EOT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_eot_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_EOT_AW :: INT_EVENT0_ICLR_EOT_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_eot_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_EOT_AW :: INT_EVENT0_ICLR_EOT_CLR) } } # [doc = "Clear Address Match Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_ADDR_MATCH_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_ADDR_MATCH_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_ADDR_MATCH_CLR = 1 , } impl From < INT_EVENT0_ICLR_ADDR_MATCH_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_ADDR_MATCH_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_ADDR_MATCH` writer - Clear Address Match Interrupt."] pub type INT_EVENT0_ICLR_ADDR_MATCH_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_ADDR_MATCH_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_ADDR_MATCH_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_addr_match_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_ADDR_MATCH_AW :: INT_EVENT0_ICLR_ADDR_MATCH_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_addr_match_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_ADDR_MATCH_AW :: INT_EVENT0_ICLR_ADDR_MATCH_CLR) } } # [doc = "Clear UART Clear to Send Modem Interrupt. 0 = Interrupt disabled\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_CTS_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_CTS_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_CTS_CLR = 1 , } impl From < INT_EVENT0_ICLR_CTS_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_CTS_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_CTS` writer - Clear UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] pub type INT_EVENT0_ICLR_CTS_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_CTS_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_CTS_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_cts_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_CTS_AW :: INT_EVENT0_ICLR_CTS_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_cts_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_CTS_AW :: INT_EVENT0_ICLR_CTS_CLR) } } # [doc = "Clear DMA Done on RX Event Channel\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_DMA_DONE_RX_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_DMA_DONE_RX_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_DMA_DONE_RX_CLR = 1 , } impl From < INT_EVENT0_ICLR_DMA_DONE_RX_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_DMA_DONE_RX_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_DMA_DONE_RX` writer - Clear DMA Done on RX Event Channel"] pub type INT_EVENT0_ICLR_DMA_DONE_RX_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_DMA_DONE_RX_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_DMA_DONE_RX_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_dma_done_rx_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_DMA_DONE_RX_AW :: INT_EVENT0_ICLR_DMA_DONE_RX_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_dma_done_rx_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_DMA_DONE_RX_AW :: INT_EVENT0_ICLR_DMA_DONE_RX_CLR) } } # [doc = "Clear DMA Done on TX Event Channel\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_DMA_DONE_TX_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_DMA_DONE_TX_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_DMA_DONE_TX_CLR = 1 , } impl From < INT_EVENT0_ICLR_DMA_DONE_TX_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_DMA_DONE_TX_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_DMA_DONE_TX` writer - Clear DMA Done on TX Event Channel"] pub type INT_EVENT0_ICLR_DMA_DONE_TX_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_DMA_DONE_TX_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_DMA_DONE_TX_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_dma_done_tx_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_DMA_DONE_TX_AW :: INT_EVENT0_ICLR_DMA_DONE_TX_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_dma_done_tx_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_DMA_DONE_TX_AW :: INT_EVENT0_ICLR_DMA_DONE_TX_CLR) } } # [doc = "Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_NERR_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_NERR_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_NERR_CLR = 1 , } impl From < INT_EVENT0_ICLR_NERR_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_NERR_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_NERR` writer - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] pub type INT_EVENT0_ICLR_NERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_NERR_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_NERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_nerr_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_NERR_AW :: INT_EVENT0_ICLR_NERR_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_nerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_NERR_AW :: INT_EVENT0_ICLR_NERR_CLR) } } impl W { # [doc = "Bit 0 - Clear UARTOUT Receive Time-Out Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iclr_rtout (& mut self) -> INT_EVENT0_ICLR_RTOUT_W < INT_EVENT0_ICLR_SPEC , 0 > { INT_EVENT0_ICLR_RTOUT_W :: new (self) } # [doc = "Bit 1 - Clear UART Framing Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iclr_frmerr (& mut self) -> INT_EVENT0_ICLR_FRMERR_W < INT_EVENT0_ICLR_SPEC , 1 > { INT_EVENT0_ICLR_FRMERR_W :: new (self) } # [doc = "Bit 2 - Clear UART Parity Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iclr_parerr (& mut self) -> INT_EVENT0_ICLR_PARERR_W < INT_EVENT0_ICLR_SPEC , 2 > { INT_EVENT0_ICLR_PARERR_W :: new (self) } # [doc = "Bit 3 - Clear UART Break Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iclr_brkerr (& mut self) -> INT_EVENT0_ICLR_BRKERR_W < INT_EVENT0_ICLR_SPEC , 3 > { INT_EVENT0_ICLR_BRKERR_W :: new (self) } # [doc = "Bit 4 - Clear UART Receive Overrun Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iclr_ovrerr (& mut self) -> INT_EVENT0_ICLR_OVRERR_W <'_,  INT_EVENT0_ICLR_SPEC , 4 > { INT_EVENT0_ICLR_OVRERR_W :: new (self) } # [doc = "Bit 5 - Clear Negative Edge on UARTxRXD Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iclr_rxne (& mut self) -> INT_EVENT0_ICLR_RXNE_W < INT_EVENT0_ICLR_SPEC , 5 > { INT_EVENT0_ICLR_RXNE_W :: new (self) } # [doc = "Bit 6 - Clear Positive Edge on UARTxRXD Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iclr_rxpe (& mut self) -> INT_EVENT0_ICLR_RXPE_W < INT_EVENT0_ICLR_SPEC , 6 > { INT_EVENT0_ICLR_RXPE_W :: new (self) } # [doc = "Bit 7 - Clear LIN Capture 0 / Match Interrupt ."] # [inline (always)] # [must_use] pub fn int_event0_iclr_linc0 (& mut self) -> INT_EVENT0_ICLR_LINC0_W < INT_EVENT0_ICLR_SPEC , 7 > { INT_EVENT0_ICLR_LINC0_W :: new (self) } # [doc = "Bit 8 - Clear LIN Capture 1 Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iclr_linc1 (& mut self) -> INT_EVENT0_ICLR_LINC1_W < INT_EVENT0_ICLR_SPEC , 8 > { INT_EVENT0_ICLR_LINC1_W :: new (self) } # [doc = "Bit 9 - Clear LIN Hardware Counter Overflow Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iclr_linovf (& mut self) -> INT_EVENT0_ICLR_LINOVF_W < INT_EVENT0_ICLR_SPEC , 9 > { INT_EVENT0_ICLR_LINOVF_W :: new (self) } # [doc = "Bit 10 - Clear UART Receive Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iclr_rxint (& mut self) -> INT_EVENT0_ICLR_RXINT_W < INT_EVENT0_ICLR_SPEC , 10 > { INT_EVENT0_ICLR_RXINT_W :: new (self) } # [doc = "Bit 11 - Clear UART Transmit Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iclr_txint (& mut self) -> INT_EVENT0_ICLR_TXINT_W < INT_EVENT0_ICLR_SPEC , 11 > { INT_EVENT0_ICLR_TXINT_W :: new (self) } # [doc = "Bit 12 - Clear UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] # [inline (always)] # [must_use] pub fn int_event0_iclr_eot (& mut self) -> INT_EVENT0_ICLR_EOT_W < INT_EVENT0_ICLR_SPEC , 12 > { INT_EVENT0_ICLR_EOT_W :: new (self) } # [doc = "Bit 13 - Clear Address Match Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iclr_addr_match (& mut self) -> INT_EVENT0_ICLR_ADDR_MATCH_W < INT_EVENT0_ICLR_SPEC , 13 > { INT_EVENT0_ICLR_ADDR_MATCH_W :: new (self) } # [doc = "Bit 14 - Clear UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] # [inline (always)] # [must_use] pub fn int_event0_iclr_cts (& mut self) -> INT_EVENT0_ICLR_CTS_W < INT_EVENT0_ICLR_SPEC , 14 > { INT_EVENT0_ICLR_CTS_W :: new (self) } # [doc = "Bit 15 - Clear DMA Done on RX Event Channel"] # [inline (always)] # [must_use] pub fn int_event0_iclr_dma_done_rx (& mut self) -> INT_EVENT0_ICLR_DMA_DONE_RX_W < INT_EVENT0_ICLR_SPEC , 15 > { INT_EVENT0_ICLR_DMA_DONE_RX_W :: new (self) } # [doc = "Bit 16 - Clear DMA Done on TX Event Channel"] # [inline (always)] # [must_use] pub fn int_event0_iclr_dma_done_tx (& mut self) -> INT_EVENT0_ICLR_DMA_DONE_TX_W < INT_EVENT0_ICLR_SPEC , 16 > { INT_EVENT0_ICLR_DMA_DONE_TX_W :: new (self) } # [doc = "Bit 17 - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] # [inline (always)] # [must_use] pub fn int_event0_iclr_nerr (& mut self) -> INT_EVENT0_ICLR_NERR_W < INT_EVENT0_ICLR_SPEC , 17 > { INT_EVENT0_ICLR_NERR_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Interrupt clear\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_event0_iclr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct INT_EVENT0_ICLR_SPEC ; impl crate :: RegisterSpec for INT_EVENT0_ICLR_SPEC { type Ux = u32 ; } # [doc = "`write(|w| ..)` method takes [`int_event0_iclr::W`](W) writer structure"] impl crate :: Writable for INT_EVENT0_ICLR_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets INT_EVENT0_ICLR to value 0"] impl crate :: Resettable for INT_EVENT0_ICLR_SPEC { const RESET_VALUE : Self :: Ux = 0 ; }
[INFO] [stdout]   |                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                 +++
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing
[INFO] [stdout]  --> src/uart0/clksel.rs:1:6636
[INFO] [stdout]   |
[INFO] [stdout] 1 | ... fn clksel_mfclk_sel (& mut self) -> CLKSEL_MFCLK_SEL_W < CLKSEL_SPEC , 2 > { CLKSEL_MFCLK_SEL_W :: new (self) } # [doc = "Bit 3 -...
[INFO] [stdout]   |                          ^^^^^^^^^^     ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here
[INFO] [stdout]   |                          |
[INFO] [stdout]   |                          the lifetime is elided here
[INFO] [stdout]   |
[INFO] [stdout]   = help: the same lifetime is referred to in inconsistent ways, making the signature confusing
[INFO] [stdout] help: use `'_` for type paths
[INFO] [stdout]   |
[INFO] [stdout] 1 | # [doc = "Register `CLKSEL` reader"] pub type R = crate :: R < CLKSEL_SPEC > ; # [doc = "Register `CLKSEL` writer"] pub type W = crate :: W < CLKSEL_SPEC > ; # [doc = "Field `CLKSEL_LFCLK_SEL` reader - Selects LFCLK as clock source if enabled"] pub type CLKSEL_LFCLK_SEL_R = crate :: BitReader < CLKSEL_LFCLK_SEL_A > ; # [doc = "Selects LFCLK as clock source if enabled\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CLKSEL_LFCLK_SEL_A { # [doc = "0: DISABLE"] CLKSEL_LFCLK_SEL_DISABLE = 0 , # [doc = "1: ENABLE"] CLKSEL_LFCLK_SEL_ENABLE = 1 , } impl From < CLKSEL_LFCLK_SEL_A > for bool { # [inline (always)] fn from (variant : CLKSEL_LFCLK_SEL_A) -> Self { variant as u8 != 0 } } impl CLKSEL_LFCLK_SEL_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CLKSEL_LFCLK_SEL_A { match self . bits { false => CLKSEL_LFCLK_SEL_A :: CLKSEL_LFCLK_SEL_DISABLE , true => CLKSEL_LFCLK_SEL_A :: CLKSEL_LFCLK_SEL_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_clksel_lfclk_sel_disable (& self) -> bool { * self == CLKSEL_LFCLK_SEL_A :: CLKSEL_LFCLK_SEL_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_clksel_lfclk_sel_enable (& self) -> bool { * self == CLKSEL_LFCLK_SEL_A :: CLKSEL_LFCLK_SEL_ENABLE } } # [doc = "Field `CLKSEL_LFCLK_SEL` writer - Selects LFCLK as clock source if enabled"] pub type CLKSEL_LFCLK_SEL_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CLKSEL_LFCLK_SEL_A > ; impl < 'a , REG , const O : u8 > CLKSEL_LFCLK_SEL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn clksel_lfclk_sel_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CLKSEL_LFCLK_SEL_A :: CLKSEL_LFCLK_SEL_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn clksel_lfclk_sel_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CLKSEL_LFCLK_SEL_A :: CLKSEL_LFCLK_SEL_ENABLE) } } # [doc = "Field `CLKSEL_MFCLK_SEL` reader - Selects MFCLK as clock source if enabled"] pub type CLKSEL_MFCLK_SEL_R = crate :: BitReader < CLKSEL_MFCLK_SEL_A > ; # [doc = "Selects MFCLK as clock source if enabled\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CLKSEL_MFCLK_SEL_A { # [doc = "0: DISABLE"] CLKSEL_MFCLK_SEL_DISABLE = 0 , # [doc = "1: ENABLE"] CLKSEL_MFCLK_SEL_ENABLE = 1 , } impl From < CLKSEL_MFCLK_SEL_A > for bool { # [inline (always)] fn from (variant : CLKSEL_MFCLK_SEL_A) -> Self { variant as u8 != 0 } } impl CLKSEL_MFCLK_SEL_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CLKSEL_MFCLK_SEL_A { match self . bits { false => CLKSEL_MFCLK_SEL_A :: CLKSEL_MFCLK_SEL_DISABLE , true => CLKSEL_MFCLK_SEL_A :: CLKSEL_MFCLK_SEL_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_clksel_mfclk_sel_disable (& self) -> bool { * self == CLKSEL_MFCLK_SEL_A :: CLKSEL_MFCLK_SEL_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_clksel_mfclk_sel_enable (& self) -> bool { * self == CLKSEL_MFCLK_SEL_A :: CLKSEL_MFCLK_SEL_ENABLE } } # [doc = "Field `CLKSEL_MFCLK_SEL` writer - Selects MFCLK as clock source if enabled"] pub type CLKSEL_MFCLK_SEL_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CLKSEL_MFCLK_SEL_A > ; impl < 'a , REG , const O : u8 > CLKSEL_MFCLK_SEL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn clksel_mfclk_sel_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CLKSEL_MFCLK_SEL_A :: CLKSEL_MFCLK_SEL_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn clksel_mfclk_sel_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CLKSEL_MFCLK_SEL_A :: CLKSEL_MFCLK_SEL_ENABLE) } } # [doc = "Field `CLKSEL_BUSCLK_SEL` reader - Selects BUS CLK as clock source if enabled"] pub type CLKSEL_BUSCLK_SEL_R = crate :: BitReader < CLKSEL_BUSCLK_SEL_A > ; # [doc = "Selects BUS CLK as clock source if enabled\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CLKSEL_BUSCLK_SEL_A { # [doc = "0: DISABLE"] CLKSEL_BUSCLK_SEL_DISABLE = 0 , # [doc = "1: ENABLE"] CLKSEL_BUSCLK_SEL_ENABLE = 1 , } impl From < CLKSEL_BUSCLK_SEL_A > for bool { # [inline (always)] fn from (variant : CLKSEL_BUSCLK_SEL_A) -> Self { variant as u8 != 0 } } impl CLKSEL_BUSCLK_SEL_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CLKSEL_BUSCLK_SEL_A { match self . bits { false => CLKSEL_BUSCLK_SEL_A :: CLKSEL_BUSCLK_SEL_DISABLE , true => CLKSEL_BUSCLK_SEL_A :: CLKSEL_BUSCLK_SEL_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_clksel_busclk_sel_disable (& self) -> bool { * self == CLKSEL_BUSCLK_SEL_A :: CLKSEL_BUSCLK_SEL_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_clksel_busclk_sel_enable (& self) -> bool { * self == CLKSEL_BUSCLK_SEL_A :: CLKSEL_BUSCLK_SEL_ENABLE } } # [doc = "Field `CLKSEL_BUSCLK_SEL` writer - Selects BUS CLK as clock source if enabled"] pub type CLKSEL_BUSCLK_SEL_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CLKSEL_BUSCLK_SEL_A > ; impl < 'a , REG , const O : u8 > CLKSEL_BUSCLK_SEL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn clksel_busclk_sel_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CLKSEL_BUSCLK_SEL_A :: CLKSEL_BUSCLK_SEL_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn clksel_busclk_sel_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CLKSEL_BUSCLK_SEL_A :: CLKSEL_BUSCLK_SEL_ENABLE) } } impl R { # [doc = "Bit 1 - Selects LFCLK as clock source if enabled"] # [inline (always)] pub fn clksel_lfclk_sel (& self) -> CLKSEL_LFCLK_SEL_R { CLKSEL_LFCLK_SEL_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - Selects MFCLK as clock source if enabled"] # [inline (always)] pub fn clksel_mfclk_sel (& self) -> CLKSEL_MFCLK_SEL_R { CLKSEL_MFCLK_SEL_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - Selects BUS CLK as clock source if enabled"] # [inline (always)] pub fn clksel_busclk_sel (& self) -> CLKSEL_BUSCLK_SEL_R { CLKSEL_BUSCLK_SEL_R :: new (((self . bits >> 3) & 1) != 0) } } impl W { # [doc = "Bit 1 - Selects LFCLK as clock source if enabled"] # [inline (always)] # [must_use] pub fn clksel_lfclk_sel (& mut self) -> CLKSEL_LFCLK_SEL_W < CLKSEL_SPEC , 1 > { CLKSEL_LFCLK_SEL_W :: new (self) } # [doc = "Bit 2 - Selects MFCLK as clock source if enabled"] # [inline (always)] # [must_use] pub fn clksel_mfclk_sel (& mut self) -> CLKSEL_MFCLK_SEL_W <'_,  CLKSEL_SPEC , 2 > { CLKSEL_MFCLK_SEL_W :: new (self) } # [doc = "Bit 3 - Selects BUS CLK as clock source if enabled"] # [inline (always)] # [must_use] pub fn clksel_busclk_sel (& mut self) -> CLKSEL_BUSCLK_SEL_W < CLKSEL_SPEC , 3 > { CLKSEL_BUSCLK_SEL_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Clock Select for Ultra Low Power peripherals\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clksel::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clksel::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CLKSEL_SPEC ; impl crate :: RegisterSpec for CLKSEL_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`clksel::R`](R) reader structure"] impl crate :: Readable for CLKSEL_SPEC { } # [doc = "`write(|w| ..)` method takes [`clksel::W`](W) writer structure"] impl crate :: Writable for CLKSEL_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets CLKSEL to value 0"] impl crate :: Resettable for CLKSEL_SPEC { const RESET_VALUE : Self :: Ux = 0 ; }
[INFO] [stdout]   |                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                               +++
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing
[INFO] [stdout]  --> src/uart0/clksel.rs:1:6849
[INFO] [stdout]   |
[INFO] [stdout] 1 | ...n clksel_busclk_sel (& mut self) -> CLKSEL_BUSCLK_SEL_W < CLKSEL_SPEC , 3 > { CLKSEL_BUSCLK_SEL_W :: new (self) } # [doc = r" Writ...
[INFO] [stdout]   |                         ^^^^^^^^^^     ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here
[INFO] [stdout]   |                         |
[INFO] [stdout]   |                         the lifetime is elided here
[INFO] [stdout]   |
[INFO] [stdout]   = help: the same lifetime is referred to in inconsistent ways, making the signature confusing
[INFO] [stdout] help: use `'_` for type paths
[INFO] [stdout]   |
[INFO] [stdout] 1 | # [doc = "Register `CLKSEL` reader"] pub type R = crate :: R < CLKSEL_SPEC > ; # [doc = "Register `CLKSEL` writer"] pub type W = crate :: W < CLKSEL_SPEC > ; # [doc = "Field `CLKSEL_LFCLK_SEL` reader - Selects LFCLK as clock source if enabled"] pub type CLKSEL_LFCLK_SEL_R = crate :: BitReader < CLKSEL_LFCLK_SEL_A > ; # [doc = "Selects LFCLK as clock source if enabled\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CLKSEL_LFCLK_SEL_A { # [doc = "0: DISABLE"] CLKSEL_LFCLK_SEL_DISABLE = 0 , # [doc = "1: ENABLE"] CLKSEL_LFCLK_SEL_ENABLE = 1 , } impl From < CLKSEL_LFCLK_SEL_A > for bool { # [inline (always)] fn from (variant : CLKSEL_LFCLK_SEL_A) -> Self { variant as u8 != 0 } } impl CLKSEL_LFCLK_SEL_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CLKSEL_LFCLK_SEL_A { match self . bits { false => CLKSEL_LFCLK_SEL_A :: CLKSEL_LFCLK_SEL_DISABLE , true => CLKSEL_LFCLK_SEL_A :: CLKSEL_LFCLK_SEL_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_clksel_lfclk_sel_disable (& self) -> bool { * self == CLKSEL_LFCLK_SEL_A :: CLKSEL_LFCLK_SEL_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_clksel_lfclk_sel_enable (& self) -> bool { * self == CLKSEL_LFCLK_SEL_A :: CLKSEL_LFCLK_SEL_ENABLE } } # [doc = "Field `CLKSEL_LFCLK_SEL` writer - Selects LFCLK as clock source if enabled"] pub type CLKSEL_LFCLK_SEL_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CLKSEL_LFCLK_SEL_A > ; impl < 'a , REG , const O : u8 > CLKSEL_LFCLK_SEL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn clksel_lfclk_sel_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CLKSEL_LFCLK_SEL_A :: CLKSEL_LFCLK_SEL_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn clksel_lfclk_sel_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CLKSEL_LFCLK_SEL_A :: CLKSEL_LFCLK_SEL_ENABLE) } } # [doc = "Field `CLKSEL_MFCLK_SEL` reader - Selects MFCLK as clock source if enabled"] pub type CLKSEL_MFCLK_SEL_R = crate :: BitReader < CLKSEL_MFCLK_SEL_A > ; # [doc = "Selects MFCLK as clock source if enabled\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CLKSEL_MFCLK_SEL_A { # [doc = "0: DISABLE"] CLKSEL_MFCLK_SEL_DISABLE = 0 , # [doc = "1: ENABLE"] CLKSEL_MFCLK_SEL_ENABLE = 1 , } impl From < CLKSEL_MFCLK_SEL_A > for bool { # [inline (always)] fn from (variant : CLKSEL_MFCLK_SEL_A) -> Self { variant as u8 != 0 } } impl CLKSEL_MFCLK_SEL_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CLKSEL_MFCLK_SEL_A { match self . bits { false => CLKSEL_MFCLK_SEL_A :: CLKSEL_MFCLK_SEL_DISABLE , true => CLKSEL_MFCLK_SEL_A :: CLKSEL_MFCLK_SEL_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_clksel_mfclk_sel_disable (& self) -> bool { * self == CLKSEL_MFCLK_SEL_A :: CLKSEL_MFCLK_SEL_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_clksel_mfclk_sel_enable (& self) -> bool { * self == CLKSEL_MFCLK_SEL_A :: CLKSEL_MFCLK_SEL_ENABLE } } # [doc = "Field `CLKSEL_MFCLK_SEL` writer - Selects MFCLK as clock source if enabled"] pub type CLKSEL_MFCLK_SEL_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CLKSEL_MFCLK_SEL_A > ; impl < 'a , REG , const O : u8 > CLKSEL_MFCLK_SEL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn clksel_mfclk_sel_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CLKSEL_MFCLK_SEL_A :: CLKSEL_MFCLK_SEL_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn clksel_mfclk_sel_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CLKSEL_MFCLK_SEL_A :: CLKSEL_MFCLK_SEL_ENABLE) } } # [doc = "Field `CLKSEL_BUSCLK_SEL` reader - Selects BUS CLK as clock source if enabled"] pub type CLKSEL_BUSCLK_SEL_R = crate :: BitReader < CLKSEL_BUSCLK_SEL_A > ; # [doc = "Selects BUS CLK as clock source if enabled\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CLKSEL_BUSCLK_SEL_A { # [doc = "0: DISABLE"] CLKSEL_BUSCLK_SEL_DISABLE = 0 , # [doc = "1: ENABLE"] CLKSEL_BUSCLK_SEL_ENABLE = 1 , } impl From < CLKSEL_BUSCLK_SEL_A > for bool { # [inline (always)] fn from (variant : CLKSEL_BUSCLK_SEL_A) -> Self { variant as u8 != 0 } } impl CLKSEL_BUSCLK_SEL_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CLKSEL_BUSCLK_SEL_A { match self . bits { false => CLKSEL_BUSCLK_SEL_A :: CLKSEL_BUSCLK_SEL_DISABLE , true => CLKSEL_BUSCLK_SEL_A :: CLKSEL_BUSCLK_SEL_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_clksel_busclk_sel_disable (& self) -> bool { * self == CLKSEL_BUSCLK_SEL_A :: CLKSEL_BUSCLK_SEL_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_clksel_busclk_sel_enable (& self) -> bool { * self == CLKSEL_BUSCLK_SEL_A :: CLKSEL_BUSCLK_SEL_ENABLE } } # [doc = "Field `CLKSEL_BUSCLK_SEL` writer - Selects BUS CLK as clock source if enabled"] pub type CLKSEL_BUSCLK_SEL_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CLKSEL_BUSCLK_SEL_A > ; impl < 'a , REG , const O : u8 > CLKSEL_BUSCLK_SEL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn clksel_busclk_sel_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CLKSEL_BUSCLK_SEL_A :: CLKSEL_BUSCLK_SEL_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn clksel_busclk_sel_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CLKSEL_BUSCLK_SEL_A :: CLKSEL_BUSCLK_SEL_ENABLE) } } impl R { # [doc = "Bit 1 - Selects LFCLK as clock source if enabled"] # [inline (always)] pub fn clksel_lfclk_sel (& self) -> CLKSEL_LFCLK_SEL_R { CLKSEL_LFCLK_SEL_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - Selects MFCLK as clock source if enabled"] # [inline (always)] pub fn clksel_mfclk_sel (& self) -> CLKSEL_MFCLK_SEL_R { CLKSEL_MFCLK_SEL_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - Selects BUS CLK as clock source if enabled"] # [inline (always)] pub fn clksel_busclk_sel (& self) -> CLKSEL_BUSCLK_SEL_R { CLKSEL_BUSCLK_SEL_R :: new (((self . bits >> 3) & 1) != 0) } } impl W { # [doc = "Bit 1 - Selects LFCLK as clock source if enabled"] # [inline (always)] # [must_use] pub fn clksel_lfclk_sel (& mut self) -> CLKSEL_LFCLK_SEL_W < CLKSEL_SPEC , 1 > { CLKSEL_LFCLK_SEL_W :: new (self) } # [doc = "Bit 2 - Selects MFCLK as clock source if enabled"] # [inline (always)] # [must_use] pub fn clksel_mfclk_sel (& mut self) -> CLKSEL_MFCLK_SEL_W < CLKSEL_SPEC , 2 > { CLKSEL_MFCLK_SEL_W :: new (self) } # [doc = "Bit 3 - Selects BUS CLK as clock source if enabled"] # [inline (always)] # [must_use] pub fn clksel_busclk_sel (& mut self) -> CLKSEL_BUSCLK_SEL_W <'_,  CLKSEL_SPEC , 3 > { CLKSEL_BUSCLK_SEL_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Clock Select for Ultra Low Power peripherals\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clksel::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clksel::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CLKSEL_SPEC ; impl crate :: RegisterSpec for CLKSEL_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`clksel::R`](R) reader structure"] impl crate :: Readable for CLKSEL_SPEC { } # [doc = "`write(|w| ..)` method takes [`clksel::W`](W) writer structure"] impl crate :: Writable for CLKSEL_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets CLKSEL to value 0"] impl crate :: Resettable for CLKSEL_SPEC { const RESET_VALUE : Self :: Ux = 0 ; }
[INFO] [stdout]   |                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                     +++
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing
[INFO] [stdout]  --> src/uart0/pdbgctl.rs:5:247
[INFO] [stdout]   |
[INFO] [stdout] 5 | ...] pub fn pdbgctl_free (& mut self) -> PDBGCTL_FREE_W < PDBGCTL_SPEC , 0 > { PDBGCTL_FREE_W :: new (self) } # [doc = "Bit 1 - Soft ...
[INFO] [stdout]   |                           ^^^^^^^^^^     ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here
[INFO] [stdout]   |                           |
[INFO] [stdout]   |                           the lifetime is elided here
[INFO] [stdout]   |
[INFO] [stdout]   = help: the same lifetime is referred to in inconsistent ways, making the signature confusing
[INFO] [stdout] help: use `'_` for type paths
[INFO] [stdout]   |
[INFO] [stdout] 5 | is set to 'STOP'"] # [inline (always)] pub fn pdbgctl_soft (& self) -> PDBGCTL_SOFT_R { PDBGCTL_SOFT_R :: new (((self . bits >> 1) & 1) != 0) } } impl W { # [doc = "Bit 0 - Free run control"] # [inline (always)] # [must_use] pub fn pdbgctl_free (& mut self) -> PDBGCTL_FREE_W <'_,  PDBGCTL_SPEC , 0 > { PDBGCTL_FREE_W :: new (self) } # [doc = "Bit 1 - Soft halt boundary control. This function is only available, if \\[FREE\\]
[INFO] [stdout]   |                                                                                                                                                                                                                                                                                      +++
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing
[INFO] [stdout]  --> src/uart0/pdbgctl.rs:6:74
[INFO] [stdout]   |
[INFO] [stdout] 6 | ...] pub fn pdbgctl_soft (& mut self) -> PDBGCTL_SOFT_W < PDBGCTL_SPEC , 1 > { PDBGCTL_SOFT_W :: new (self) } # [doc = r" Writes raw ...
[INFO] [stdout]   |                           ^^^^^^^^^^     ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here
[INFO] [stdout]   |                           |
[INFO] [stdout]   |                           the lifetime is elided here
[INFO] [stdout]   |
[INFO] [stdout]   = help: the same lifetime is referred to in inconsistent ways, making the signature confusing
[INFO] [stdout] help: use `'_` for type paths
[INFO] [stdout]   |
[INFO] [stdout] 6 | is set to 'STOP'"] # [inline (always)] # [must_use] pub fn pdbgctl_soft (& mut self) -> PDBGCTL_SOFT_W <'_,  PDBGCTL_SPEC , 1 > { PDBGCTL_SOFT_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Peripheral Debug Control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pdbgctl::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pdbgctl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PDBGCTL_SPEC ; impl crate :: RegisterSpec for PDBGCTL_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`pdbgctl::R`](R) reader structure"] impl crate :: Readable for PDBGCTL_SPEC { } # [doc = "`write(|w| ..)` method takes [`pdbgctl::W`](W) writer structure"] impl crate :: Writable for PDBGCTL_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets PDBGCTL to value 0"] impl crate :: Resettable for PDBGCTL_SPEC { const RESET_VALUE : Self :: Ux = 0 ; }
[INFO] [stdout]   |                                                                                                         +++
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing
[INFO] [stdout]  --> src/uart0/int_event0_iclr.rs:1:22837
[INFO] [stdout]   |
[INFO] [stdout] 1 | ...nt0_iclr_rxne (& mut self) -> INT_EVENT0_ICLR_RXNE_W < INT_EVENT0_ICLR_SPEC , 5 > { INT_EVENT0_ICLR_RXNE_W :: new (self) } # [doc ...
[INFO] [stdout]   |                   ^^^^^^^^^^     ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here
[INFO] [stdout]   |                   |
[INFO] [stdout]   |                   the lifetime is elided here
[INFO] [stdout]   |
[INFO] [stdout]   = help: the same lifetime is referred to in inconsistent ways, making the signature confusing
[INFO] [stdout] help: use `'_` for type paths
[INFO] [stdout]   |
[INFO] [stdout] 1 | # [doc = "Register `INT_EVENT0_ICLR` writer"] pub type W = crate :: W < INT_EVENT0_ICLR_SPEC > ; # [doc = "Clear UARTOUT Receive Time-Out Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_RTOUT_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_RTOUT_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_RTOUT_CLR = 1 , } impl From < INT_EVENT0_ICLR_RTOUT_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_RTOUT_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_RTOUT` writer - Clear UARTOUT Receive Time-Out Interrupt."] pub type INT_EVENT0_ICLR_RTOUT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_RTOUT_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_RTOUT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_rtout_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_RTOUT_AW :: INT_EVENT0_ICLR_RTOUT_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_rtout_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_RTOUT_AW :: INT_EVENT0_ICLR_RTOUT_CLR) } } # [doc = "Clear UART Framing Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_FRMERR_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_FRMERR_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_FRMERR_CLR = 1 , } impl From < INT_EVENT0_ICLR_FRMERR_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_FRMERR_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_FRMERR` writer - Clear UART Framing Error Interrupt."] pub type INT_EVENT0_ICLR_FRMERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_FRMERR_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_FRMERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_frmerr_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_FRMERR_AW :: INT_EVENT0_ICLR_FRMERR_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_frmerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_FRMERR_AW :: INT_EVENT0_ICLR_FRMERR_CLR) } } # [doc = "Clear UART Parity Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_PARERR_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_PARERR_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_PARERR_CLR = 1 , } impl From < INT_EVENT0_ICLR_PARERR_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_PARERR_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_PARERR` writer - Clear UART Parity Error Interrupt."] pub type INT_EVENT0_ICLR_PARERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_PARERR_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_PARERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_parerr_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_PARERR_AW :: INT_EVENT0_ICLR_PARERR_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_parerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_PARERR_AW :: INT_EVENT0_ICLR_PARERR_CLR) } } # [doc = "Clear UART Break Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_BRKERR_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_BRKERR_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_BRKERR_CLR = 1 , } impl From < INT_EVENT0_ICLR_BRKERR_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_BRKERR_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_BRKERR` writer - Clear UART Break Error Interrupt."] pub type INT_EVENT0_ICLR_BRKERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_BRKERR_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_BRKERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_brkerr_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_BRKERR_AW :: INT_EVENT0_ICLR_BRKERR_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_brkerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_BRKERR_AW :: INT_EVENT0_ICLR_BRKERR_CLR) } } # [doc = "Clear UART Receive Overrun Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_OVRERR_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_OVRERR_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_OVRERR_CLR = 1 , } impl From < INT_EVENT0_ICLR_OVRERR_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_OVRERR_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_OVRERR` writer - Clear UART Receive Overrun Error Interrupt."] pub type INT_EVENT0_ICLR_OVRERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_OVRERR_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_OVRERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_ovrerr_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_OVRERR_AW :: INT_EVENT0_ICLR_OVRERR_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_ovrerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_OVRERR_AW :: INT_EVENT0_ICLR_OVRERR_CLR) } } # [doc = "Clear Negative Edge on UARTxRXD Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_RXNE_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_RXNE_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_RXNE_CLR = 1 , } impl From < INT_EVENT0_ICLR_RXNE_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_RXNE_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_RXNE` writer - Clear Negative Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_ICLR_RXNE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_RXNE_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_RXNE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_rxne_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_RXNE_AW :: INT_EVENT0_ICLR_RXNE_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_rxne_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_RXNE_AW :: INT_EVENT0_ICLR_RXNE_CLR) } } # [doc = "Clear Positive Edge on UARTxRXD Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_RXPE_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_RXPE_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_RXPE_CLR = 1 , } impl From < INT_EVENT0_ICLR_RXPE_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_RXPE_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_RXPE` writer - Clear Positive Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_ICLR_RXPE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_RXPE_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_RXPE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_rxpe_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_RXPE_AW :: INT_EVENT0_ICLR_RXPE_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_rxpe_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_RXPE_AW :: INT_EVENT0_ICLR_RXPE_CLR) } } # [doc = "Clear LIN Capture 0 / Match Interrupt .\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_LINC0_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_LINC0_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_LINC0_CLR = 1 , } impl From < INT_EVENT0_ICLR_LINC0_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_LINC0_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_LINC0` writer - Clear LIN Capture 0 / Match Interrupt ."] pub type INT_EVENT0_ICLR_LINC0_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_LINC0_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_LINC0_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_linc0_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_LINC0_AW :: INT_EVENT0_ICLR_LINC0_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_linc0_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_LINC0_AW :: INT_EVENT0_ICLR_LINC0_CLR) } } # [doc = "Clear LIN Capture 1 Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_LINC1_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_LINC1_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_LINC1_CLR = 1 , } impl From < INT_EVENT0_ICLR_LINC1_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_LINC1_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_LINC1` writer - Clear LIN Capture 1 Interrupt."] pub type INT_EVENT0_ICLR_LINC1_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_LINC1_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_LINC1_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_linc1_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_LINC1_AW :: INT_EVENT0_ICLR_LINC1_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_linc1_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_LINC1_AW :: INT_EVENT0_ICLR_LINC1_CLR) } } # [doc = "Clear LIN Hardware Counter Overflow Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_LINOVF_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_LINOVF_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_LINOVF_CLR = 1 , } impl From < INT_EVENT0_ICLR_LINOVF_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_LINOVF_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_LINOVF` writer - Clear LIN Hardware Counter Overflow Interrupt."] pub type INT_EVENT0_ICLR_LINOVF_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_LINOVF_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_LINOVF_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_linovf_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_LINOVF_AW :: INT_EVENT0_ICLR_LINOVF_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_linovf_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_LINOVF_AW :: INT_EVENT0_ICLR_LINOVF_CLR) } } # [doc = "Clear UART Receive Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_RXINT_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_RXINT_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_RXINT_CLR = 1 , } impl From < INT_EVENT0_ICLR_RXINT_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_RXINT_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_RXINT` writer - Clear UART Receive Interrupt."] pub type INT_EVENT0_ICLR_RXINT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_RXINT_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_RXINT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_rxint_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_RXINT_AW :: INT_EVENT0_ICLR_RXINT_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_rxint_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_RXINT_AW :: INT_EVENT0_ICLR_RXINT_CLR) } } # [doc = "Clear UART Transmit Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_TXINT_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_TXINT_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_TXINT_CLR = 1 , } impl From < INT_EVENT0_ICLR_TXINT_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_TXINT_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_TXINT` writer - Clear UART Transmit Interrupt."] pub type INT_EVENT0_ICLR_TXINT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_TXINT_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_TXINT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_txint_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_TXINT_AW :: INT_EVENT0_ICLR_TXINT_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_txint_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_TXINT_AW :: INT_EVENT0_ICLR_TXINT_CLR) } } # [doc = "Clear UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_EOT_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_EOT_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_EOT_CLR = 1 , } impl From < INT_EVENT0_ICLR_EOT_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_EOT_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_EOT` writer - Clear UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] pub type INT_EVENT0_ICLR_EOT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_EOT_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_EOT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_eot_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_EOT_AW :: INT_EVENT0_ICLR_EOT_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_eot_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_EOT_AW :: INT_EVENT0_ICLR_EOT_CLR) } } # [doc = "Clear Address Match Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_ADDR_MATCH_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_ADDR_MATCH_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_ADDR_MATCH_CLR = 1 , } impl From < INT_EVENT0_ICLR_ADDR_MATCH_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_ADDR_MATCH_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_ADDR_MATCH` writer - Clear Address Match Interrupt."] pub type INT_EVENT0_ICLR_ADDR_MATCH_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_ADDR_MATCH_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_ADDR_MATCH_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_addr_match_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_ADDR_MATCH_AW :: INT_EVENT0_ICLR_ADDR_MATCH_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_addr_match_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_ADDR_MATCH_AW :: INT_EVENT0_ICLR_ADDR_MATCH_CLR) } } # [doc = "Clear UART Clear to Send Modem Interrupt. 0 = Interrupt disabled\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_CTS_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_CTS_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_CTS_CLR = 1 , } impl From < INT_EVENT0_ICLR_CTS_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_CTS_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_CTS` writer - Clear UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] pub type INT_EVENT0_ICLR_CTS_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_CTS_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_CTS_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_cts_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_CTS_AW :: INT_EVENT0_ICLR_CTS_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_cts_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_CTS_AW :: INT_EVENT0_ICLR_CTS_CLR) } } # [doc = "Clear DMA Done on RX Event Channel\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_DMA_DONE_RX_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_DMA_DONE_RX_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_DMA_DONE_RX_CLR = 1 , } impl From < INT_EVENT0_ICLR_DMA_DONE_RX_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_DMA_DONE_RX_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_DMA_DONE_RX` writer - Clear DMA Done on RX Event Channel"] pub type INT_EVENT0_ICLR_DMA_DONE_RX_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_DMA_DONE_RX_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_DMA_DONE_RX_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_dma_done_rx_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_DMA_DONE_RX_AW :: INT_EVENT0_ICLR_DMA_DONE_RX_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_dma_done_rx_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_DMA_DONE_RX_AW :: INT_EVENT0_ICLR_DMA_DONE_RX_CLR) } } # [doc = "Clear DMA Done on TX Event Channel\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_DMA_DONE_TX_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_DMA_DONE_TX_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_DMA_DONE_TX_CLR = 1 , } impl From < INT_EVENT0_ICLR_DMA_DONE_TX_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_DMA_DONE_TX_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_DMA_DONE_TX` writer - Clear DMA Done on TX Event Channel"] pub type INT_EVENT0_ICLR_DMA_DONE_TX_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_DMA_DONE_TX_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_DMA_DONE_TX_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_dma_done_tx_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_DMA_DONE_TX_AW :: INT_EVENT0_ICLR_DMA_DONE_TX_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_dma_done_tx_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_DMA_DONE_TX_AW :: INT_EVENT0_ICLR_DMA_DONE_TX_CLR) } } # [doc = "Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_NERR_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_NERR_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_NERR_CLR = 1 , } impl From < INT_EVENT0_ICLR_NERR_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_NERR_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_NERR` writer - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] pub type INT_EVENT0_ICLR_NERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_NERR_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_NERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_nerr_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_NERR_AW :: INT_EVENT0_ICLR_NERR_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_nerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_NERR_AW :: INT_EVENT0_ICLR_NERR_CLR) } } impl W { # [doc = "Bit 0 - Clear UARTOUT Receive Time-Out Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iclr_rtout (& mut self) -> INT_EVENT0_ICLR_RTOUT_W < INT_EVENT0_ICLR_SPEC , 0 > { INT_EVENT0_ICLR_RTOUT_W :: new (self) } # [doc = "Bit 1 - Clear UART Framing Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iclr_frmerr (& mut self) -> INT_EVENT0_ICLR_FRMERR_W < INT_EVENT0_ICLR_SPEC , 1 > { INT_EVENT0_ICLR_FRMERR_W :: new (self) } # [doc = "Bit 2 - Clear UART Parity Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iclr_parerr (& mut self) -> INT_EVENT0_ICLR_PARERR_W < INT_EVENT0_ICLR_SPEC , 2 > { INT_EVENT0_ICLR_PARERR_W :: new (self) } # [doc = "Bit 3 - Clear UART Break Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iclr_brkerr (& mut self) -> INT_EVENT0_ICLR_BRKERR_W < INT_EVENT0_ICLR_SPEC , 3 > { INT_EVENT0_ICLR_BRKERR_W :: new (self) } # [doc = "Bit 4 - Clear UART Receive Overrun Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iclr_ovrerr (& mut self) -> INT_EVENT0_ICLR_OVRERR_W < INT_EVENT0_ICLR_SPEC , 4 > { INT_EVENT0_ICLR_OVRERR_W :: new (self) } # [doc = "Bit 5 - Clear Negative Edge on UARTxRXD Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iclr_rxne (& mut self) -> INT_EVENT0_ICLR_RXNE_W <'_,  INT_EVENT0_ICLR_SPEC , 5 > { INT_EVENT0_ICLR_RXNE_W :: new (self) } # [doc = "Bit 6 - Clear Positive Edge on UARTxRXD Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iclr_rxpe (& mut self) -> INT_EVENT0_ICLR_RXPE_W < INT_EVENT0_ICLR_SPEC , 6 > { INT_EVENT0_ICLR_RXPE_W :: new (self) } # [doc = "Bit 7 - Clear LIN Capture 0 / Match Interrupt ."] # [inline (always)] # [must_use] pub fn int_event0_iclr_linc0 (& mut self) -> INT_EVENT0_ICLR_LINC0_W < INT_EVENT0_ICLR_SPEC , 7 > { INT_EVENT0_ICLR_LINC0_W :: new (self) } # [doc = "Bit 8 - Clear LIN Capture 1 Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iclr_linc1 (& mut self) -> INT_EVENT0_ICLR_LINC1_W < INT_EVENT0_ICLR_SPEC , 8 > { INT_EVENT0_ICLR_LINC1_W :: new (self) } # [doc = "Bit 9 - Clear LIN Hardware Counter Overflow Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iclr_linovf (& mut self) -> INT_EVENT0_ICLR_LINOVF_W < INT_EVENT0_ICLR_SPEC , 9 > { INT_EVENT0_ICLR_LINOVF_W :: new (self) } # [doc = "Bit 10 - Clear UART Receive Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iclr_rxint (& mut self) -> INT_EVENT0_ICLR_RXINT_W < INT_EVENT0_ICLR_SPEC , 10 > { INT_EVENT0_ICLR_RXINT_W :: new (self) } # [doc = "Bit 11 - Clear UART Transmit Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iclr_txint (& mut self) -> INT_EVENT0_ICLR_TXINT_W < INT_EVENT0_ICLR_SPEC , 11 > { INT_EVENT0_ICLR_TXINT_W :: new (self) } # [doc = "Bit 12 - Clear UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] # [inline (always)] # [must_use] pub fn int_event0_iclr_eot (& mut self) -> INT_EVENT0_ICLR_EOT_W < INT_EVENT0_ICLR_SPEC , 12 > { INT_EVENT0_ICLR_EOT_W :: new (self) } # [doc = "Bit 13 - Clear Address Match Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iclr_addr_match (& mut self) -> INT_EVENT0_ICLR_ADDR_MATCH_W < INT_EVENT0_ICLR_SPEC , 13 > { INT_EVENT0_ICLR_ADDR_MATCH_W :: new (self) } # [doc = "Bit 14 - Clear UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] # [inline (always)] # [must_use] pub fn int_event0_iclr_cts (& mut self) -> INT_EVENT0_ICLR_CTS_W < INT_EVENT0_ICLR_SPEC , 14 > { INT_EVENT0_ICLR_CTS_W :: new (self) } # [doc = "Bit 15 - Clear DMA Done on RX Event Channel"] # [inline (always)] # [must_use] pub fn int_event0_iclr_dma_done_rx (& mut self) -> INT_EVENT0_ICLR_DMA_DONE_RX_W < INT_EVENT0_ICLR_SPEC , 15 > { INT_EVENT0_ICLR_DMA_DONE_RX_W :: new (self) } # [doc = "Bit 16 - Clear DMA Done on TX Event Channel"] # [inline (always)] # [must_use] pub fn int_event0_iclr_dma_done_tx (& mut self) -> INT_EVENT0_ICLR_DMA_DONE_TX_W < INT_EVENT0_ICLR_SPEC , 16 > { INT_EVENT0_ICLR_DMA_DONE_TX_W :: new (self) } # [doc = "Bit 17 - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] # [inline (always)] # [must_use] pub fn int_event0_iclr_nerr (& mut self) -> INT_EVENT0_ICLR_NERR_W < INT_EVENT0_ICLR_SPEC , 17 > { INT_EVENT0_ICLR_NERR_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Interrupt clear\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_event0_iclr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct INT_EVENT0_ICLR_SPEC ; impl crate :: RegisterSpec for INT_EVENT0_ICLR_SPEC { type Ux = u32 ; } # [doc = "`write(|w| ..)` method takes [`int_event0_iclr::W`](W) writer structure"] impl crate :: Writable for INT_EVENT0_ICLR_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets INT_EVENT0_ICLR to value 0"] impl crate :: Resettable for INT_EVENT0_ICLR_SPEC { const RESET_VALUE : Self :: Ux = 0 ; }
[INFO] [stdout]   |                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                            +++
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing
[INFO] [stdout]  --> src/uart0/int_event0_iclr.rs:1:23070
[INFO] [stdout]   |
[INFO] [stdout] 1 | ...nt0_iclr_rxpe (& mut self) -> INT_EVENT0_ICLR_RXPE_W < INT_EVENT0_ICLR_SPEC , 6 > { INT_EVENT0_ICLR_RXPE_W :: new (self) } # [doc ...
[INFO] [stdout]   |                   ^^^^^^^^^^     ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here
[INFO] [stdout]   |                   |
[INFO] [stdout]   |                   the lifetime is elided here
[INFO] [stdout]   |
[INFO] [stdout]   = help: the same lifetime is referred to in inconsistent ways, making the signature confusing
[INFO] [stdout] help: use `'_` for type paths
[INFO] [stdout]   |
[INFO] [stdout] 1 | # [doc = "Register `INT_EVENT0_ICLR` writer"] pub type W = crate :: W < INT_EVENT0_ICLR_SPEC > ; # [doc = "Clear UARTOUT Receive Time-Out Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_RTOUT_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_RTOUT_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_RTOUT_CLR = 1 , } impl From < INT_EVENT0_ICLR_RTOUT_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_RTOUT_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_RTOUT` writer - Clear UARTOUT Receive Time-Out Interrupt."] pub type INT_EVENT0_ICLR_RTOUT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_RTOUT_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_RTOUT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_rtout_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_RTOUT_AW :: INT_EVENT0_ICLR_RTOUT_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_rtout_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_RTOUT_AW :: INT_EVENT0_ICLR_RTOUT_CLR) } } # [doc = "Clear UART Framing Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_FRMERR_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_FRMERR_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_FRMERR_CLR = 1 , } impl From < INT_EVENT0_ICLR_FRMERR_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_FRMERR_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_FRMERR` writer - Clear UART Framing Error Interrupt."] pub type INT_EVENT0_ICLR_FRMERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_FRMERR_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_FRMERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_frmerr_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_FRMERR_AW :: INT_EVENT0_ICLR_FRMERR_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_frmerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_FRMERR_AW :: INT_EVENT0_ICLR_FRMERR_CLR) } } # [doc = "Clear UART Parity Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_PARERR_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_PARERR_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_PARERR_CLR = 1 , } impl From < INT_EVENT0_ICLR_PARERR_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_PARERR_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_PARERR` writer - Clear UART Parity Error Interrupt."] pub type INT_EVENT0_ICLR_PARERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_PARERR_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_PARERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_parerr_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_PARERR_AW :: INT_EVENT0_ICLR_PARERR_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_parerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_PARERR_AW :: INT_EVENT0_ICLR_PARERR_CLR) } } # [doc = "Clear UART Break Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_BRKERR_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_BRKERR_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_BRKERR_CLR = 1 , } impl From < INT_EVENT0_ICLR_BRKERR_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_BRKERR_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_BRKERR` writer - Clear UART Break Error Interrupt."] pub type INT_EVENT0_ICLR_BRKERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_BRKERR_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_BRKERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_brkerr_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_BRKERR_AW :: INT_EVENT0_ICLR_BRKERR_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_brkerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_BRKERR_AW :: INT_EVENT0_ICLR_BRKERR_CLR) } } # [doc = "Clear UART Receive Overrun Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_OVRERR_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_OVRERR_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_OVRERR_CLR = 1 , } impl From < INT_EVENT0_ICLR_OVRERR_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_OVRERR_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_OVRERR` writer - Clear UART Receive Overrun Error Interrupt."] pub type INT_EVENT0_ICLR_OVRERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_OVRERR_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_OVRERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_ovrerr_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_OVRERR_AW :: INT_EVENT0_ICLR_OVRERR_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_ovrerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_OVRERR_AW :: INT_EVENT0_ICLR_OVRERR_CLR) } } # [doc = "Clear Negative Edge on UARTxRXD Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_RXNE_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_RXNE_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_RXNE_CLR = 1 , } impl From < INT_EVENT0_ICLR_RXNE_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_RXNE_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_RXNE` writer - Clear Negative Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_ICLR_RXNE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_RXNE_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_RXNE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_rxne_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_RXNE_AW :: INT_EVENT0_ICLR_RXNE_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_rxne_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_RXNE_AW :: INT_EVENT0_ICLR_RXNE_CLR) } } # [doc = "Clear Positive Edge on UARTxRXD Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_RXPE_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_RXPE_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_RXPE_CLR = 1 , } impl From < INT_EVENT0_ICLR_RXPE_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_RXPE_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_RXPE` writer - Clear Positive Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_ICLR_RXPE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_RXPE_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_RXPE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_rxpe_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_RXPE_AW :: INT_EVENT0_ICLR_RXPE_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_rxpe_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_RXPE_AW :: INT_EVENT0_ICLR_RXPE_CLR) } } # [doc = "Clear LIN Capture 0 / Match Interrupt .\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_LINC0_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_LINC0_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_LINC0_CLR = 1 , } impl From < INT_EVENT0_ICLR_LINC0_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_LINC0_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_LINC0` writer - Clear LIN Capture 0 / Match Interrupt ."] pub type INT_EVENT0_ICLR_LINC0_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_LINC0_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_LINC0_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_linc0_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_LINC0_AW :: INT_EVENT0_ICLR_LINC0_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_linc0_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_LINC0_AW :: INT_EVENT0_ICLR_LINC0_CLR) } } # [doc = "Clear LIN Capture 1 Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_LINC1_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_LINC1_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_LINC1_CLR = 1 , } impl From < INT_EVENT0_ICLR_LINC1_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_LINC1_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_LINC1` writer - Clear LIN Capture 1 Interrupt."] pub type INT_EVENT0_ICLR_LINC1_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_LINC1_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_LINC1_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_linc1_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_LINC1_AW :: INT_EVENT0_ICLR_LINC1_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_linc1_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_LINC1_AW :: INT_EVENT0_ICLR_LINC1_CLR) } } # [doc = "Clear LIN Hardware Counter Overflow Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_LINOVF_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_LINOVF_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_LINOVF_CLR = 1 , } impl From < INT_EVENT0_ICLR_LINOVF_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_LINOVF_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_LINOVF` writer - Clear LIN Hardware Counter Overflow Interrupt."] pub type INT_EVENT0_ICLR_LINOVF_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_LINOVF_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_LINOVF_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_linovf_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_LINOVF_AW :: INT_EVENT0_ICLR_LINOVF_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_linovf_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_LINOVF_AW :: INT_EVENT0_ICLR_LINOVF_CLR) } } # [doc = "Clear UART Receive Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_RXINT_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_RXINT_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_RXINT_CLR = 1 , } impl From < INT_EVENT0_ICLR_RXINT_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_RXINT_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_RXINT` writer - Clear UART Receive Interrupt."] pub type INT_EVENT0_ICLR_RXINT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_RXINT_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_RXINT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_rxint_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_RXINT_AW :: INT_EVENT0_ICLR_RXINT_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_rxint_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_RXINT_AW :: INT_EVENT0_ICLR_RXINT_CLR) } } # [doc = "Clear UART Transmit Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_TXINT_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_TXINT_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_TXINT_CLR = 1 , } impl From < INT_EVENT0_ICLR_TXINT_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_TXINT_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_TXINT` writer - Clear UART Transmit Interrupt."] pub type INT_EVENT0_ICLR_TXINT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_TXINT_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_TXINT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_txint_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_TXINT_AW :: INT_EVENT0_ICLR_TXINT_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_txint_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_TXINT_AW :: INT_EVENT0_ICLR_TXINT_CLR) } } # [doc = "Clear UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_EOT_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_EOT_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_EOT_CLR = 1 , } impl From < INT_EVENT0_ICLR_EOT_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_EOT_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_EOT` writer - Clear UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] pub type INT_EVENT0_ICLR_EOT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_EOT_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_EOT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_eot_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_EOT_AW :: INT_EVENT0_ICLR_EOT_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_eot_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_EOT_AW :: INT_EVENT0_ICLR_EOT_CLR) } } # [doc = "Clear Address Match Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_ADDR_MATCH_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_ADDR_MATCH_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_ADDR_MATCH_CLR = 1 , } impl From < INT_EVENT0_ICLR_ADDR_MATCH_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_ADDR_MATCH_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_ADDR_MATCH` writer - Clear Address Match Interrupt."] pub type INT_EVENT0_ICLR_ADDR_MATCH_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_ADDR_MATCH_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_ADDR_MATCH_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_addr_match_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_ADDR_MATCH_AW :: INT_EVENT0_ICLR_ADDR_MATCH_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_addr_match_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_ADDR_MATCH_AW :: INT_EVENT0_ICLR_ADDR_MATCH_CLR) } } # [doc = "Clear UART Clear to Send Modem Interrupt. 0 = Interrupt disabled\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_CTS_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_CTS_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_CTS_CLR = 1 , } impl From < INT_EVENT0_ICLR_CTS_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_CTS_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_CTS` writer - Clear UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] pub type INT_EVENT0_ICLR_CTS_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_CTS_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_CTS_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_cts_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_CTS_AW :: INT_EVENT0_ICLR_CTS_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_cts_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_CTS_AW :: INT_EVENT0_ICLR_CTS_CLR) } } # [doc = "Clear DMA Done on RX Event Channel\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_DMA_DONE_RX_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_DMA_DONE_RX_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_DMA_DONE_RX_CLR = 1 , } impl From < INT_EVENT0_ICLR_DMA_DONE_RX_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_DMA_DONE_RX_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_DMA_DONE_RX` writer - Clear DMA Done on RX Event Channel"] pub type INT_EVENT0_ICLR_DMA_DONE_RX_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_DMA_DONE_RX_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_DMA_DONE_RX_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_dma_done_rx_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_DMA_DONE_RX_AW :: INT_EVENT0_ICLR_DMA_DONE_RX_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_dma_done_rx_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_DMA_DONE_RX_AW :: INT_EVENT0_ICLR_DMA_DONE_RX_CLR) } } # [doc = "Clear DMA Done on TX Event Channel\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_DMA_DONE_TX_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_DMA_DONE_TX_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_DMA_DONE_TX_CLR = 1 , } impl From < INT_EVENT0_ICLR_DMA_DONE_TX_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_DMA_DONE_TX_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_DMA_DONE_TX` writer - Clear DMA Done on TX Event Channel"] pub type INT_EVENT0_ICLR_DMA_DONE_TX_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_DMA_DONE_TX_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_DMA_DONE_TX_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_dma_done_tx_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_DMA_DONE_TX_AW :: INT_EVENT0_ICLR_DMA_DONE_TX_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_dma_done_tx_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_DMA_DONE_TX_AW :: INT_EVENT0_ICLR_DMA_DONE_TX_CLR) } } # [doc = "Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_NERR_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_NERR_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_NERR_CLR = 1 , } impl From < INT_EVENT0_ICLR_NERR_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_NERR_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_NERR` writer - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] pub type INT_EVENT0_ICLR_NERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_NERR_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_NERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_nerr_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_NERR_AW :: INT_EVENT0_ICLR_NERR_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_nerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_NERR_AW :: INT_EVENT0_ICLR_NERR_CLR) } } impl W { # [doc = "Bit 0 - Clear UARTOUT Receive Time-Out Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iclr_rtout (& mut self) -> INT_EVENT0_ICLR_RTOUT_W < INT_EVENT0_ICLR_SPEC , 0 > { INT_EVENT0_ICLR_RTOUT_W :: new (self) } # [doc = "Bit 1 - Clear UART Framing Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iclr_frmerr (& mut self) -> INT_EVENT0_ICLR_FRMERR_W < INT_EVENT0_ICLR_SPEC , 1 > { INT_EVENT0_ICLR_FRMERR_W :: new (self) } # [doc = "Bit 2 - Clear UART Parity Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iclr_parerr (& mut self) -> INT_EVENT0_ICLR_PARERR_W < INT_EVENT0_ICLR_SPEC , 2 > { INT_EVENT0_ICLR_PARERR_W :: new (self) } # [doc = "Bit 3 - Clear UART Break Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iclr_brkerr (& mut self) -> INT_EVENT0_ICLR_BRKERR_W < INT_EVENT0_ICLR_SPEC , 3 > { INT_EVENT0_ICLR_BRKERR_W :: new (self) } # [doc = "Bit 4 - Clear UART Receive Overrun Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iclr_ovrerr (& mut self) -> INT_EVENT0_ICLR_OVRERR_W < INT_EVENT0_ICLR_SPEC , 4 > { INT_EVENT0_ICLR_OVRERR_W :: new (self) } # [doc = "Bit 5 - Clear Negative Edge on UARTxRXD Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iclr_rxne (& mut self) -> INT_EVENT0_ICLR_RXNE_W < INT_EVENT0_ICLR_SPEC , 5 > { INT_EVENT0_ICLR_RXNE_W :: new (self) } # [doc = "Bit 6 - Clear Positive Edge on UARTxRXD Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iclr_rxpe (& mut self) -> INT_EVENT0_ICLR_RXPE_W <'_,  INT_EVENT0_ICLR_SPEC , 6 > { INT_EVENT0_ICLR_RXPE_W :: new (self) } # [doc = "Bit 7 - Clear LIN Capture 0 / Match Interrupt ."] # [inline (always)] # [must_use] pub fn int_event0_iclr_linc0 (& mut self) -> INT_EVENT0_ICLR_LINC0_W < INT_EVENT0_ICLR_SPEC , 7 > { INT_EVENT0_ICLR_LINC0_W :: new (self) } # [doc = "Bit 8 - Clear LIN Capture 1 Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iclr_linc1 (& mut self) -> INT_EVENT0_ICLR_LINC1_W < INT_EVENT0_ICLR_SPEC , 8 > { INT_EVENT0_ICLR_LINC1_W :: new (self) } # [doc = "Bit 9 - Clear LIN Hardware Counter Overflow Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iclr_linovf (& mut self) -> INT_EVENT0_ICLR_LINOVF_W < INT_EVENT0_ICLR_SPEC , 9 > { INT_EVENT0_ICLR_LINOVF_W :: new (self) } # [doc = "Bit 10 - Clear UART Receive Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iclr_rxint (& mut self) -> INT_EVENT0_ICLR_RXINT_W < INT_EVENT0_ICLR_SPEC , 10 > { INT_EVENT0_ICLR_RXINT_W :: new (self) } # [doc = "Bit 11 - Clear UART Transmit Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iclr_txint (& mut self) -> INT_EVENT0_ICLR_TXINT_W < INT_EVENT0_ICLR_SPEC , 11 > { INT_EVENT0_ICLR_TXINT_W :: new (self) } # [doc = "Bit 12 - Clear UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] # [inline (always)] # [must_use] pub fn int_event0_iclr_eot (& mut self) -> INT_EVENT0_ICLR_EOT_W < INT_EVENT0_ICLR_SPEC , 12 > { INT_EVENT0_ICLR_EOT_W :: new (self) } # [doc = "Bit 13 - Clear Address Match Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iclr_addr_match (& mut self) -> INT_EVENT0_ICLR_ADDR_MATCH_W < INT_EVENT0_ICLR_SPEC , 13 > { INT_EVENT0_ICLR_ADDR_MATCH_W :: new (self) } # [doc = "Bit 14 - Clear UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] # [inline (always)] # [must_use] pub fn int_event0_iclr_cts (& mut self) -> INT_EVENT0_ICLR_CTS_W < INT_EVENT0_ICLR_SPEC , 14 > { INT_EVENT0_ICLR_CTS_W :: new (self) } # [doc = "Bit 15 - Clear DMA Done on RX Event Channel"] # [inline (always)] # [must_use] pub fn int_event0_iclr_dma_done_rx (& mut self) -> INT_EVENT0_ICLR_DMA_DONE_RX_W < INT_EVENT0_ICLR_SPEC , 15 > { INT_EVENT0_ICLR_DMA_DONE_RX_W :: new (self) } # [doc = "Bit 16 - Clear DMA Done on TX Event Channel"] # [inline (always)] # [must_use] pub fn int_event0_iclr_dma_done_tx (& mut self) -> INT_EVENT0_ICLR_DMA_DONE_TX_W < INT_EVENT0_ICLR_SPEC , 16 > { INT_EVENT0_ICLR_DMA_DONE_TX_W :: new (self) } # [doc = "Bit 17 - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] # [inline (always)] # [must_use] pub fn int_event0_iclr_nerr (& mut self) -> INT_EVENT0_ICLR_NERR_W < INT_EVENT0_ICLR_SPEC , 17 > { INT_EVENT0_ICLR_NERR_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Interrupt clear\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_event0_iclr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct INT_EVENT0_ICLR_SPEC ; impl crate :: RegisterSpec for INT_EVENT0_ICLR_SPEC { type Ux = u32 ; } # [doc = "`write(|w| ..)` method takes [`int_event0_iclr::W`](W) writer structure"] impl crate :: Writable for INT_EVENT0_ICLR_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets INT_EVENT0_ICLR to value 0"] impl crate :: Resettable for INT_EVENT0_ICLR_SPEC { const RESET_VALUE : Self :: Ux = 0 ; }
[INFO] [stdout]   |                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                     +++
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing
[INFO] [stdout]  --> src/uart0/int_event0_imask.rs:1:40498
[INFO] [stdout]   |
[INFO] [stdout] 1 | ..._imask_rtout (& mut self) -> INT_EVENT0_IMASK_RTOUT_W < INT_EVENT0_IMASK_SPEC , 0 > { INT_EVENT0_IMASK_RTOUT_W :: new (self) } # [...
[INFO] [stdout]   |                  ^^^^^^^^^^     ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here
[INFO] [stdout]   |                  |
[INFO] [stdout]   |                  the lifetime is elided here
[INFO] [stdout]   |
[INFO] [stdout]   = help: the same lifetime is referred to in inconsistent ways, making the signature confusing
[INFO] [stdout] help: use `'_` for type paths
[INFO] [stdout]   |
[INFO] [stdout] 1 | # [doc = "Register `INT_EVENT0_IMASK` reader"] pub type R = crate :: R < INT_EVENT0_IMASK_SPEC > ; # [doc = "Register `INT_EVENT0_IMASK` writer"] pub type W = crate :: W < INT_EVENT0_IMASK_SPEC > ; # [doc = "Field `INT_EVENT0_IMASK_RTOUT` reader - Enable UARTOUT Receive Time-Out Interrupt."] pub type INT_EVENT0_IMASK_RTOUT_R = crate :: BitReader < INT_EVENT0_IMASK_RTOUT_A > ; # [doc = "Enable UARTOUT Receive Time-Out Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_RTOUT_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_RTOUT_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_RTOUT_SET = 1 , } impl From < INT_EVENT0_IMASK_RTOUT_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_RTOUT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_RTOUT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_RTOUT_A { match self . bits { false => INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_CLR , true => INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_rtout_clr (& self) -> bool { * self == INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_rtout_set (& self) -> bool { * self == INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_SET } } # [doc = "Field `INT_EVENT0_IMASK_RTOUT` writer - Enable UARTOUT Receive Time-Out Interrupt."] pub type INT_EVENT0_IMASK_RTOUT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_RTOUT_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_RTOUT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_rtout_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_rtout_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_SET) } } # [doc = "Field `INT_EVENT0_IMASK_FRMERR` reader - Enable UART Framing Error Interrupt."] pub type INT_EVENT0_IMASK_FRMERR_R = crate :: BitReader < INT_EVENT0_IMASK_FRMERR_A > ; # [doc = "Enable UART Framing Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_FRMERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_FRMERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_FRMERR_SET = 1 , } impl From < INT_EVENT0_IMASK_FRMERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_FRMERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_FRMERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_FRMERR_A { match self . bits { false => INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_CLR , true => INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_frmerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_frmerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_FRMERR` writer - Enable UART Framing Error Interrupt."] pub type INT_EVENT0_IMASK_FRMERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_FRMERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_FRMERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_frmerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_frmerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_SET) } } # [doc = "Field `INT_EVENT0_IMASK_PARERR` reader - Enable UART Parity Error Interrupt."] pub type INT_EVENT0_IMASK_PARERR_R = crate :: BitReader < INT_EVENT0_IMASK_PARERR_A > ; # [doc = "Enable UART Parity Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_PARERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_PARERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_PARERR_SET = 1 , } impl From < INT_EVENT0_IMASK_PARERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_PARERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_PARERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_PARERR_A { match self . bits { false => INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_CLR , true => INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_parerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_parerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_PARERR` writer - Enable UART Parity Error Interrupt."] pub type INT_EVENT0_IMASK_PARERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_PARERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_PARERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_parerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_parerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_SET) } } # [doc = "Field `INT_EVENT0_IMASK_BRKERR` reader - Enable UART Break Error Interrupt."] pub type INT_EVENT0_IMASK_BRKERR_R = crate :: BitReader < INT_EVENT0_IMASK_BRKERR_A > ; # [doc = "Enable UART Break Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_BRKERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_BRKERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_BRKERR_SET = 1 , } impl From < INT_EVENT0_IMASK_BRKERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_BRKERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_BRKERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_BRKERR_A { match self . bits { false => INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_CLR , true => INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_brkerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_brkerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_BRKERR` writer - Enable UART Break Error Interrupt."] pub type INT_EVENT0_IMASK_BRKERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_BRKERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_BRKERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_brkerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_brkerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_SET) } } # [doc = "Field `INT_EVENT0_IMASK_OVRERR` reader - Enable UART Receive Overrun Error Interrupt."] pub type INT_EVENT0_IMASK_OVRERR_R = crate :: BitReader < INT_EVENT0_IMASK_OVRERR_A > ; # [doc = "Enable UART Receive Overrun Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_OVRERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_OVRERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_OVRERR_SET = 1 , } impl From < INT_EVENT0_IMASK_OVRERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_OVRERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_OVRERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_OVRERR_A { match self . bits { false => INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_CLR , true => INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_ovrerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_ovrerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_OVRERR` writer - Enable UART Receive Overrun Error Interrupt."] pub type INT_EVENT0_IMASK_OVRERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_OVRERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_OVRERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_ovrerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_ovrerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_SET) } } # [doc = "Field `INT_EVENT0_IMASK_RXNE` reader - Enable Negative Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_IMASK_RXNE_R = crate :: BitReader < INT_EVENT0_IMASK_RXNE_A > ; # [doc = "Enable Negative Edge on UARTxRXD Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_RXNE_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_RXNE_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_RXNE_SET = 1 , } impl From < INT_EVENT0_IMASK_RXNE_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_RXNE_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_RXNE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_RXNE_A { match self . bits { false => INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_CLR , true => INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_rxne_clr (& self) -> bool { * self == INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_rxne_set (& self) -> bool { * self == INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_SET } } # [doc = "Field `INT_EVENT0_IMASK_RXNE` writer - Enable Negative Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_IMASK_RXNE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_RXNE_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_RXNE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_rxne_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_rxne_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_SET) } } # [doc = "Field `INT_EVENT0_IMASK_RXPE` reader - Enable Positive Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_IMASK_RXPE_R = crate :: BitReader < INT_EVENT0_IMASK_RXPE_A > ; # [doc = "Enable Positive Edge on UARTxRXD Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_RXPE_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_RXPE_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_RXPE_SET = 1 , } impl From < INT_EVENT0_IMASK_RXPE_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_RXPE_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_RXPE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_RXPE_A { match self . bits { false => INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_CLR , true => INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_rxpe_clr (& self) -> bool { * self == INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_rxpe_set (& self) -> bool { * self == INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_SET } } # [doc = "Field `INT_EVENT0_IMASK_RXPE` writer - Enable Positive Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_IMASK_RXPE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_RXPE_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_RXPE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_rxpe_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_rxpe_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_SET) } } # [doc = "Field `INT_EVENT0_IMASK_LINC0` reader - Enable LIN Capture 0 / Match Interrupt ."] pub type INT_EVENT0_IMASK_LINC0_R = crate :: BitReader < INT_EVENT0_IMASK_LINC0_A > ; # [doc = "Enable LIN Capture 0 / Match Interrupt .\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_LINC0_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_LINC0_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_LINC0_SET = 1 , } impl From < INT_EVENT0_IMASK_LINC0_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_LINC0_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_LINC0_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_LINC0_A { match self . bits { false => INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_CLR , true => INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_linc0_clr (& self) -> bool { * self == INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_linc0_set (& self) -> bool { * self == INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_SET } } # [doc = "Field `INT_EVENT0_IMASK_LINC0` writer - Enable LIN Capture 0 / Match Interrupt ."] pub type INT_EVENT0_IMASK_LINC0_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_LINC0_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_LINC0_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_linc0_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_linc0_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_SET) } } # [doc = "Field `INT_EVENT0_IMASK_LINC1` reader - Enable LIN Capture 1 Interrupt."] pub type INT_EVENT0_IMASK_LINC1_R = crate :: BitReader < INT_EVENT0_IMASK_LINC1_A > ; # [doc = "Enable LIN Capture 1 Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_LINC1_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_LINC1_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_LINC1_SET = 1 , } impl From < INT_EVENT0_IMASK_LINC1_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_LINC1_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_LINC1_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_LINC1_A { match self . bits { false => INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_CLR , true => INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_linc1_clr (& self) -> bool { * self == INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_linc1_set (& self) -> bool { * self == INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_SET } } # [doc = "Field `INT_EVENT0_IMASK_LINC1` writer - Enable LIN Capture 1 Interrupt."] pub type INT_EVENT0_IMASK_LINC1_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_LINC1_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_LINC1_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_linc1_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_linc1_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_SET) } } # [doc = "Field `INT_EVENT0_IMASK_LINOVF` reader - Enable LIN Hardware Counter Overflow Interrupt."] pub type INT_EVENT0_IMASK_LINOVF_R = crate :: BitReader < INT_EVENT0_IMASK_LINOVF_A > ; # [doc = "Enable LIN Hardware Counter Overflow Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_LINOVF_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_LINOVF_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_LINOVF_SET = 1 , } impl From < INT_EVENT0_IMASK_LINOVF_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_LINOVF_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_LINOVF_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_LINOVF_A { match self . bits { false => INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_CLR , true => INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_linovf_clr (& self) -> bool { * self == INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_linovf_set (& self) -> bool { * self == INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_SET } } # [doc = "Field `INT_EVENT0_IMASK_LINOVF` writer - Enable LIN Hardware Counter Overflow Interrupt."] pub type INT_EVENT0_IMASK_LINOVF_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_LINOVF_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_LINOVF_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_linovf_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_linovf_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_SET) } } # [doc = "Field `INT_EVENT0_IMASK_RXINT` reader - Enable UART Receive Interrupt."] pub type INT_EVENT0_IMASK_RXINT_R = crate :: BitReader < INT_EVENT0_IMASK_RXINT_A > ; # [doc = "Enable UART Receive Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_RXINT_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_RXINT_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_RXINT_SET = 1 , } impl From < INT_EVENT0_IMASK_RXINT_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_RXINT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_RXINT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_RXINT_A { match self . bits { false => INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_CLR , true => INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_rxint_clr (& self) -> bool { * self == INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_rxint_set (& self) -> bool { * self == INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_SET } } # [doc = "Field `INT_EVENT0_IMASK_RXINT` writer - Enable UART Receive Interrupt."] pub type INT_EVENT0_IMASK_RXINT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_RXINT_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_RXINT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_rxint_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_rxint_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_SET) } } # [doc = "Field `INT_EVENT0_IMASK_TXINT` reader - Enable UART Transmit Interrupt."] pub type INT_EVENT0_IMASK_TXINT_R = crate :: BitReader < INT_EVENT0_IMASK_TXINT_A > ; # [doc = "Enable UART Transmit Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_TXINT_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_TXINT_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_TXINT_SET = 1 , } impl From < INT_EVENT0_IMASK_TXINT_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_TXINT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_TXINT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_TXINT_A { match self . bits { false => INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_CLR , true => INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_txint_clr (& self) -> bool { * self == INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_txint_set (& self) -> bool { * self == INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_SET } } # [doc = "Field `INT_EVENT0_IMASK_TXINT` writer - Enable UART Transmit Interrupt."] pub type INT_EVENT0_IMASK_TXINT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_TXINT_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_TXINT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_txint_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_txint_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_SET) } } # [doc = "Field `INT_EVENT0_IMASK_EOT` reader - Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] pub type INT_EVENT0_IMASK_EOT_R = crate :: BitReader < INT_EVENT0_IMASK_EOT_A > ; # [doc = "Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_EOT_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_EOT_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_EOT_SET = 1 , } impl From < INT_EVENT0_IMASK_EOT_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_EOT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_EOT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_EOT_A { match self . bits { false => INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_CLR , true => INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_eot_clr (& self) -> bool { * self == INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_eot_set (& self) -> bool { * self == INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_SET } } # [doc = "Field `INT_EVENT0_IMASK_EOT` writer - Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] pub type INT_EVENT0_IMASK_EOT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_EOT_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_EOT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_eot_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_eot_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_SET) } } # [doc = "Field `INT_EVENT0_IMASK_ADDR_MATCH` reader - Enable Address Match Interrupt."] pub type INT_EVENT0_IMASK_ADDR_MATCH_R = crate :: BitReader < INT_EVENT0_IMASK_ADDR_MATCH_A > ; # [doc = "Enable Address Match Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_ADDR_MATCH_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_ADDR_MATCH_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_ADDR_MATCH_SET = 1 , } impl From < INT_EVENT0_IMASK_ADDR_MATCH_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_ADDR_MATCH_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_ADDR_MATCH_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_ADDR_MATCH_A { match self . bits { false => INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_CLR , true => INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_addr_match_clr (& self) -> bool { * self == INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_addr_match_set (& self) -> bool { * self == INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_SET } } # [doc = "Field `INT_EVENT0_IMASK_ADDR_MATCH` writer - Enable Address Match Interrupt."] pub type INT_EVENT0_IMASK_ADDR_MATCH_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_ADDR_MATCH_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_ADDR_MATCH_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_addr_match_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_addr_match_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_SET) } } # [doc = "Field `INT_EVENT0_IMASK_CTS` reader - Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] pub type INT_EVENT0_IMASK_CTS_R = crate :: BitReader < INT_EVENT0_IMASK_CTS_A > ; # [doc = "Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_CTS_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_CTS_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_CTS_SET = 1 , } impl From < INT_EVENT0_IMASK_CTS_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_CTS_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_CTS_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_CTS_A { match self . bits { false => INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_CLR , true => INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_cts_clr (& self) -> bool { * self == INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_cts_set (& self) -> bool { * self == INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_SET } } # [doc = "Field `INT_EVENT0_IMASK_CTS` writer - Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] pub type INT_EVENT0_IMASK_CTS_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_CTS_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_CTS_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_cts_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_cts_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DMA_DONE_RX` reader - Enable DMA Done on RX Event Channel"] pub type INT_EVENT0_IMASK_DMA_DONE_RX_R = crate :: BitReader < INT_EVENT0_IMASK_DMA_DONE_RX_A > ; # [doc = "Enable DMA Done on RX Event Channel\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DMA_DONE_RX_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DMA_DONE_RX_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DMA_DONE_RX_SET = 1 , } impl From < INT_EVENT0_IMASK_DMA_DONE_RX_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DMA_DONE_RX_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DMA_DONE_RX_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DMA_DONE_RX_A { match self . bits { false => INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_CLR , true => INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dma_done_rx_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dma_done_rx_set (& self) -> bool { * self == INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_SET } } # [doc = "Field `INT_EVENT0_IMASK_DMA_DONE_RX` writer - Enable DMA Done on RX Event Channel"] pub type INT_EVENT0_IMASK_DMA_DONE_RX_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DMA_DONE_RX_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DMA_DONE_RX_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dma_done_rx_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dma_done_rx_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DMA_DONE_TX` reader - Enable DMA Done on TX Event Channel"] pub type INT_EVENT0_IMASK_DMA_DONE_TX_R = crate :: BitReader < INT_EVENT0_IMASK_DMA_DONE_TX_A > ; # [doc = "Enable DMA Done on TX Event Channel\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DMA_DONE_TX_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DMA_DONE_TX_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DMA_DONE_TX_SET = 1 , } impl From < INT_EVENT0_IMASK_DMA_DONE_TX_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DMA_DONE_TX_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DMA_DONE_TX_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DMA_DONE_TX_A { match self . bits { false => INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_CLR , true => INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dma_done_tx_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dma_done_tx_set (& self) -> bool { * self == INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_SET } } # [doc = "Field `INT_EVENT0_IMASK_DMA_DONE_TX` writer - Enable DMA Done on TX Event Channel"] pub type INT_EVENT0_IMASK_DMA_DONE_TX_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DMA_DONE_TX_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DMA_DONE_TX_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dma_done_tx_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dma_done_tx_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_SET) } } # [doc = "Field `INT_EVENT0_IMASK_NERR` reader - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] pub type INT_EVENT0_IMASK_NERR_R = crate :: BitReader < INT_EVENT0_IMASK_NERR_A > ; # [doc = "Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_NERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_NERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_NERR_SET = 1 , } impl From < INT_EVENT0_IMASK_NERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_NERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_NERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_NERR_A { match self . bits { false => INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_CLR , true => INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_nerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_nerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_NERR` writer - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] pub type INT_EVENT0_IMASK_NERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_NERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_NERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_nerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_nerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_SET) } } impl R { # [doc = "Bit 0 - Enable UARTOUT Receive Time-Out Interrupt."] # [inline (always)] pub fn int_event0_imask_rtout (& self) -> INT_EVENT0_IMASK_RTOUT_R { INT_EVENT0_IMASK_RTOUT_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - Enable UART Framing Error Interrupt."] # [inline (always)] pub fn int_event0_imask_frmerr (& self) -> INT_EVENT0_IMASK_FRMERR_R { INT_EVENT0_IMASK_FRMERR_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - Enable UART Parity Error Interrupt."] # [inline (always)] pub fn int_event0_imask_parerr (& self) -> INT_EVENT0_IMASK_PARERR_R { INT_EVENT0_IMASK_PARERR_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - Enable UART Break Error Interrupt."] # [inline (always)] pub fn int_event0_imask_brkerr (& self) -> INT_EVENT0_IMASK_BRKERR_R { INT_EVENT0_IMASK_BRKERR_R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - Enable UART Receive Overrun Error Interrupt."] # [inline (always)] pub fn int_event0_imask_ovrerr (& self) -> INT_EVENT0_IMASK_OVRERR_R { INT_EVENT0_IMASK_OVRERR_R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - Enable Negative Edge on UARTxRXD Interrupt."] # [inline (always)] pub fn int_event0_imask_rxne (& self) -> INT_EVENT0_IMASK_RXNE_R { INT_EVENT0_IMASK_RXNE_R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - Enable Positive Edge on UARTxRXD Interrupt."] # [inline (always)] pub fn int_event0_imask_rxpe (& self) -> INT_EVENT0_IMASK_RXPE_R { INT_EVENT0_IMASK_RXPE_R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - Enable LIN Capture 0 / Match Interrupt ."] # [inline (always)] pub fn int_event0_imask_linc0 (& self) -> INT_EVENT0_IMASK_LINC0_R { INT_EVENT0_IMASK_LINC0_R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - Enable LIN Capture 1 Interrupt."] # [inline (always)] pub fn int_event0_imask_linc1 (& self) -> INT_EVENT0_IMASK_LINC1_R { INT_EVENT0_IMASK_LINC1_R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - Enable LIN Hardware Counter Overflow Interrupt."] # [inline (always)] pub fn int_event0_imask_linovf (& self) -> INT_EVENT0_IMASK_LINOVF_R { INT_EVENT0_IMASK_LINOVF_R :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - Enable UART Receive Interrupt."] # [inline (always)] pub fn int_event0_imask_rxint (& self) -> INT_EVENT0_IMASK_RXINT_R { INT_EVENT0_IMASK_RXINT_R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - Enable UART Transmit Interrupt."] # [inline (always)] pub fn int_event0_imask_txint (& self) -> INT_EVENT0_IMASK_TXINT_R { INT_EVENT0_IMASK_TXINT_R :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] # [inline (always)] pub fn int_event0_imask_eot (& self) -> INT_EVENT0_IMASK_EOT_R { INT_EVENT0_IMASK_EOT_R :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - Enable Address Match Interrupt."] # [inline (always)] pub fn int_event0_imask_addr_match (& self) -> INT_EVENT0_IMASK_ADDR_MATCH_R { INT_EVENT0_IMASK_ADDR_MATCH_R :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 14 - Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] # [inline (always)] pub fn int_event0_imask_cts (& self) -> INT_EVENT0_IMASK_CTS_R { INT_EVENT0_IMASK_CTS_R :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - Enable DMA Done on RX Event Channel"] # [inline (always)] pub fn int_event0_imask_dma_done_rx (& self) -> INT_EVENT0_IMASK_DMA_DONE_RX_R { INT_EVENT0_IMASK_DMA_DONE_RX_R :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bit 16 - Enable DMA Done on TX Event Channel"] # [inline (always)] pub fn int_event0_imask_dma_done_tx (& self) -> INT_EVENT0_IMASK_DMA_DONE_TX_R { INT_EVENT0_IMASK_DMA_DONE_TX_R :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] # [inline (always)] pub fn int_event0_imask_nerr (& self) -> INT_EVENT0_IMASK_NERR_R { INT_EVENT0_IMASK_NERR_R :: new (((self . bits >> 17) & 1) != 0) } } impl W { # [doc = "Bit 0 - Enable UARTOUT Receive Time-Out Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_rtout (& mut self) -> INT_EVENT0_IMASK_RTOUT_W <'_,  INT_EVENT0_IMASK_SPEC , 0 > { INT_EVENT0_IMASK_RTOUT_W :: new (self) } # [doc = "Bit 1 - Enable UART Framing Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_frmerr (& mut self) -> INT_EVENT0_IMASK_FRMERR_W < INT_EVENT0_IMASK_SPEC , 1 > { INT_EVENT0_IMASK_FRMERR_W :: new (self) } # [doc = "Bit 2 - Enable UART Parity Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_parerr (& mut self) -> INT_EVENT0_IMASK_PARERR_W < INT_EVENT0_IMASK_SPEC , 2 > { INT_EVENT0_IMASK_PARERR_W :: new (self) } # [doc = "Bit 3 - Enable UART Break Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_brkerr (& mut self) -> INT_EVENT0_IMASK_BRKERR_W < INT_EVENT0_IMASK_SPEC , 3 > { INT_EVENT0_IMASK_BRKERR_W :: new (self) } # [doc = "Bit 4 - Enable UART Receive Overrun Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_ovrerr (& mut self) -> INT_EVENT0_IMASK_OVRERR_W < INT_EVENT0_IMASK_SPEC , 4 > { INT_EVENT0_IMASK_OVRERR_W :: new (self) } # [doc = "Bit 5 - Enable Negative Edge on UARTxRXD Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_rxne (& mut self) -> INT_EVENT0_IMASK_RXNE_W < INT_EVENT0_IMASK_SPEC , 5 > { INT_EVENT0_IMASK_RXNE_W :: new (self) } # [doc = "Bit 6 - Enable Positive Edge on UARTxRXD Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_rxpe (& mut self) -> INT_EVENT0_IMASK_RXPE_W < INT_EVENT0_IMASK_SPEC , 6 > { INT_EVENT0_IMASK_RXPE_W :: new (self) } # [doc = "Bit 7 - Enable LIN Capture 0 / Match Interrupt ."] # [inline (always)] # [must_use] pub fn int_event0_imask_linc0 (& mut self) -> INT_EVENT0_IMASK_LINC0_W < INT_EVENT0_IMASK_SPEC , 7 > { INT_EVENT0_IMASK_LINC0_W :: new (self) } # [doc = "Bit 8 - Enable LIN Capture 1 Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_linc1 (& mut self) -> INT_EVENT0_IMASK_LINC1_W < INT_EVENT0_IMASK_SPEC , 8 > { INT_EVENT0_IMASK_LINC1_W :: new (self) } # [doc = "Bit 9 - Enable LIN Hardware Counter Overflow Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_linovf (& mut self) -> INT_EVENT0_IMASK_LINOVF_W < INT_EVENT0_IMASK_SPEC , 9 > { INT_EVENT0_IMASK_LINOVF_W :: new (self) } # [doc = "Bit 10 - Enable UART Receive Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_rxint (& mut self) -> INT_EVENT0_IMASK_RXINT_W < INT_EVENT0_IMASK_SPEC , 10 > { INT_EVENT0_IMASK_RXINT_W :: new (self) } # [doc = "Bit 11 - Enable UART Transmit Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_txint (& mut self) -> INT_EVENT0_IMASK_TXINT_W < INT_EVENT0_IMASK_SPEC , 11 > { INT_EVENT0_IMASK_TXINT_W :: new (self) } # [doc = "Bit 12 - Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] # [inline (always)] # [must_use] pub fn int_event0_imask_eot (& mut self) -> INT_EVENT0_IMASK_EOT_W < INT_EVENT0_IMASK_SPEC , 12 > { INT_EVENT0_IMASK_EOT_W :: new (self) } # [doc = "Bit 13 - Enable Address Match Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_addr_match (& mut self) -> INT_EVENT0_IMASK_ADDR_MATCH_W < INT_EVENT0_IMASK_SPEC , 13 > { INT_EVENT0_IMASK_ADDR_MATCH_W :: new (self) } # [doc = "Bit 14 - Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] # [inline (always)] # [must_use] pub fn int_event0_imask_cts (& mut self) -> INT_EVENT0_IMASK_CTS_W < INT_EVENT0_IMASK_SPEC , 14 > { INT_EVENT0_IMASK_CTS_W :: new (self) } # [doc = "Bit 15 - Enable DMA Done on RX Event Channel"] # [inline (always)] # [must_use] pub fn int_event0_imask_dma_done_rx (& mut self) -> INT_EVENT0_IMASK_DMA_DONE_RX_W < INT_EVENT0_IMASK_SPEC , 15 > { INT_EVENT0_IMASK_DMA_DONE_RX_W :: new (self) } # [doc = "Bit 16 - Enable DMA Done on TX Event Channel"] # [inline (always)] # [must_use] pub fn int_event0_imask_dma_done_tx (& mut self) -> INT_EVENT0_IMASK_DMA_DONE_TX_W < INT_EVENT0_IMASK_SPEC , 16 > { INT_EVENT0_IMASK_DMA_DONE_TX_W :: new (self) } # [doc = "Bit 17 - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] # [inline (always)] # [must_use] pub fn int_event0_imask_nerr (& mut self) -> INT_EVENT0_IMASK_NERR_W < INT_EVENT0_IMASK_SPEC , 17 > { INT_EVENT0_IMASK_NERR_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Interrupt mask\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_event0_imask::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_event0_imask::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct INT_EVENT0_IMASK_SPEC ; impl crate :: RegisterSpec for INT_EVENT0_IMASK_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`int_event0_imask::R`](R) reader structure"] impl crate :: Readable for INT_EVENT0_IMASK_SPEC { } # [doc = "`write(|w| ..)` method takes [`int_event0_imask::W`](W) writer structure"] impl crate :: Writable for INT_EVENT0_IMASK_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets INT_EVENT0_IMASK to value 0"] impl crate :: Resettable for INT_EVENT0_IMASK_SPEC { const RESET_VALUE : Self :: Ux = 0 ; }
[INFO] [stdout]   |                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                           +++
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing
[INFO] [stdout]  --> src/uart0/int_event0_iclr.rs:1:23301
[INFO] [stdout]   |
[INFO] [stdout] 1 | ...t0_iclr_linc0 (& mut self) -> INT_EVENT0_ICLR_LINC0_W < INT_EVENT0_ICLR_SPEC , 7 > { INT_EVENT0_ICLR_LINC0_W :: new (self) } # [do...
[INFO] [stdout]   |                   ^^^^^^^^^^     ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here
[INFO] [stdout]   |                   |
[INFO] [stdout]   |                   the lifetime is elided here
[INFO] [stdout]   |
[INFO] [stdout]   = help: the same lifetime is referred to in inconsistent ways, making the signature confusing
[INFO] [stdout] help: use `'_` for type paths
[INFO] [stdout]   |
[INFO] [stdout] 1 | # [doc = "Register `INT_EVENT0_ICLR` writer"] pub type W = crate :: W < INT_EVENT0_ICLR_SPEC > ; # [doc = "Clear UARTOUT Receive Time-Out Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_RTOUT_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_RTOUT_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_RTOUT_CLR = 1 , } impl From < INT_EVENT0_ICLR_RTOUT_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_RTOUT_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_RTOUT` writer - Clear UARTOUT Receive Time-Out Interrupt."] pub type INT_EVENT0_ICLR_RTOUT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_RTOUT_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_RTOUT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_rtout_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_RTOUT_AW :: INT_EVENT0_ICLR_RTOUT_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_rtout_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_RTOUT_AW :: INT_EVENT0_ICLR_RTOUT_CLR) } } # [doc = "Clear UART Framing Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_FRMERR_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_FRMERR_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_FRMERR_CLR = 1 , } impl From < INT_EVENT0_ICLR_FRMERR_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_FRMERR_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_FRMERR` writer - Clear UART Framing Error Interrupt."] pub type INT_EVENT0_ICLR_FRMERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_FRMERR_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_FRMERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_frmerr_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_FRMERR_AW :: INT_EVENT0_ICLR_FRMERR_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_frmerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_FRMERR_AW :: INT_EVENT0_ICLR_FRMERR_CLR) } } # [doc = "Clear UART Parity Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_PARERR_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_PARERR_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_PARERR_CLR = 1 , } impl From < INT_EVENT0_ICLR_PARERR_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_PARERR_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_PARERR` writer - Clear UART Parity Error Interrupt."] pub type INT_EVENT0_ICLR_PARERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_PARERR_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_PARERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_parerr_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_PARERR_AW :: INT_EVENT0_ICLR_PARERR_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_parerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_PARERR_AW :: INT_EVENT0_ICLR_PARERR_CLR) } } # [doc = "Clear UART Break Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_BRKERR_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_BRKERR_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_BRKERR_CLR = 1 , } impl From < INT_EVENT0_ICLR_BRKERR_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_BRKERR_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_BRKERR` writer - Clear UART Break Error Interrupt."] pub type INT_EVENT0_ICLR_BRKERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_BRKERR_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_BRKERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_brkerr_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_BRKERR_AW :: INT_EVENT0_ICLR_BRKERR_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_brkerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_BRKERR_AW :: INT_EVENT0_ICLR_BRKERR_CLR) } } # [doc = "Clear UART Receive Overrun Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_OVRERR_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_OVRERR_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_OVRERR_CLR = 1 , } impl From < INT_EVENT0_ICLR_OVRERR_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_OVRERR_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_OVRERR` writer - Clear UART Receive Overrun Error Interrupt."] pub type INT_EVENT0_ICLR_OVRERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_OVRERR_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_OVRERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_ovrerr_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_OVRERR_AW :: INT_EVENT0_ICLR_OVRERR_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_ovrerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_OVRERR_AW :: INT_EVENT0_ICLR_OVRERR_CLR) } } # [doc = "Clear Negative Edge on UARTxRXD Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_RXNE_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_RXNE_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_RXNE_CLR = 1 , } impl From < INT_EVENT0_ICLR_RXNE_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_RXNE_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_RXNE` writer - Clear Negative Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_ICLR_RXNE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_RXNE_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_RXNE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_rxne_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_RXNE_AW :: INT_EVENT0_ICLR_RXNE_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_rxne_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_RXNE_AW :: INT_EVENT0_ICLR_RXNE_CLR) } } # [doc = "Clear Positive Edge on UARTxRXD Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_RXPE_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_RXPE_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_RXPE_CLR = 1 , } impl From < INT_EVENT0_ICLR_RXPE_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_RXPE_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_RXPE` writer - Clear Positive Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_ICLR_RXPE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_RXPE_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_RXPE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_rxpe_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_RXPE_AW :: INT_EVENT0_ICLR_RXPE_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_rxpe_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_RXPE_AW :: INT_EVENT0_ICLR_RXPE_CLR) } } # [doc = "Clear LIN Capture 0 / Match Interrupt .\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_LINC0_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_LINC0_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_LINC0_CLR = 1 , } impl From < INT_EVENT0_ICLR_LINC0_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_LINC0_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_LINC0` writer - Clear LIN Capture 0 / Match Interrupt ."] pub type INT_EVENT0_ICLR_LINC0_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_LINC0_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_LINC0_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_linc0_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_LINC0_AW :: INT_EVENT0_ICLR_LINC0_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_linc0_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_LINC0_AW :: INT_EVENT0_ICLR_LINC0_CLR) } } # [doc = "Clear LIN Capture 1 Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_LINC1_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_LINC1_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_LINC1_CLR = 1 , } impl From < INT_EVENT0_ICLR_LINC1_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_LINC1_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_LINC1` writer - Clear LIN Capture 1 Interrupt."] pub type INT_EVENT0_ICLR_LINC1_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_LINC1_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_LINC1_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_linc1_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_LINC1_AW :: INT_EVENT0_ICLR_LINC1_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_linc1_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_LINC1_AW :: INT_EVENT0_ICLR_LINC1_CLR) } } # [doc = "Clear LIN Hardware Counter Overflow Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_LINOVF_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_LINOVF_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_LINOVF_CLR = 1 , } impl From < INT_EVENT0_ICLR_LINOVF_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_LINOVF_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_LINOVF` writer - Clear LIN Hardware Counter Overflow Interrupt."] pub type INT_EVENT0_ICLR_LINOVF_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_LINOVF_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_LINOVF_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_linovf_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_LINOVF_AW :: INT_EVENT0_ICLR_LINOVF_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_linovf_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_LINOVF_AW :: INT_EVENT0_ICLR_LINOVF_CLR) } } # [doc = "Clear UART Receive Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_RXINT_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_RXINT_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_RXINT_CLR = 1 , } impl From < INT_EVENT0_ICLR_RXINT_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_RXINT_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_RXINT` writer - Clear UART Receive Interrupt."] pub type INT_EVENT0_ICLR_RXINT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_RXINT_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_RXINT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_rxint_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_RXINT_AW :: INT_EVENT0_ICLR_RXINT_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_rxint_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_RXINT_AW :: INT_EVENT0_ICLR_RXINT_CLR) } } # [doc = "Clear UART Transmit Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_TXINT_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_TXINT_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_TXINT_CLR = 1 , } impl From < INT_EVENT0_ICLR_TXINT_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_TXINT_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_TXINT` writer - Clear UART Transmit Interrupt."] pub type INT_EVENT0_ICLR_TXINT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_TXINT_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_TXINT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_txint_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_TXINT_AW :: INT_EVENT0_ICLR_TXINT_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_txint_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_TXINT_AW :: INT_EVENT0_ICLR_TXINT_CLR) } } # [doc = "Clear UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_EOT_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_EOT_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_EOT_CLR = 1 , } impl From < INT_EVENT0_ICLR_EOT_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_EOT_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_EOT` writer - Clear UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] pub type INT_EVENT0_ICLR_EOT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_EOT_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_EOT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_eot_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_EOT_AW :: INT_EVENT0_ICLR_EOT_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_eot_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_EOT_AW :: INT_EVENT0_ICLR_EOT_CLR) } } # [doc = "Clear Address Match Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_ADDR_MATCH_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_ADDR_MATCH_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_ADDR_MATCH_CLR = 1 , } impl From < INT_EVENT0_ICLR_ADDR_MATCH_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_ADDR_MATCH_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_ADDR_MATCH` writer - Clear Address Match Interrupt."] pub type INT_EVENT0_ICLR_ADDR_MATCH_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_ADDR_MATCH_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_ADDR_MATCH_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_addr_match_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_ADDR_MATCH_AW :: INT_EVENT0_ICLR_ADDR_MATCH_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_addr_match_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_ADDR_MATCH_AW :: INT_EVENT0_ICLR_ADDR_MATCH_CLR) } } # [doc = "Clear UART Clear to Send Modem Interrupt. 0 = Interrupt disabled\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_CTS_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_CTS_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_CTS_CLR = 1 , } impl From < INT_EVENT0_ICLR_CTS_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_CTS_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_CTS` writer - Clear UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] pub type INT_EVENT0_ICLR_CTS_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_CTS_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_CTS_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_cts_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_CTS_AW :: INT_EVENT0_ICLR_CTS_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_cts_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_CTS_AW :: INT_EVENT0_ICLR_CTS_CLR) } } # [doc = "Clear DMA Done on RX Event Channel\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_DMA_DONE_RX_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_DMA_DONE_RX_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_DMA_DONE_RX_CLR = 1 , } impl From < INT_EVENT0_ICLR_DMA_DONE_RX_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_DMA_DONE_RX_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_DMA_DONE_RX` writer - Clear DMA Done on RX Event Channel"] pub type INT_EVENT0_ICLR_DMA_DONE_RX_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_DMA_DONE_RX_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_DMA_DONE_RX_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_dma_done_rx_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_DMA_DONE_RX_AW :: INT_EVENT0_ICLR_DMA_DONE_RX_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_dma_done_rx_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_DMA_DONE_RX_AW :: INT_EVENT0_ICLR_DMA_DONE_RX_CLR) } } # [doc = "Clear DMA Done on TX Event Channel\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_DMA_DONE_TX_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_DMA_DONE_TX_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_DMA_DONE_TX_CLR = 1 , } impl From < INT_EVENT0_ICLR_DMA_DONE_TX_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_DMA_DONE_TX_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_DMA_DONE_TX` writer - Clear DMA Done on TX Event Channel"] pub type INT_EVENT0_ICLR_DMA_DONE_TX_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_DMA_DONE_TX_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_DMA_DONE_TX_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_dma_done_tx_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_DMA_DONE_TX_AW :: INT_EVENT0_ICLR_DMA_DONE_TX_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_dma_done_tx_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_DMA_DONE_TX_AW :: INT_EVENT0_ICLR_DMA_DONE_TX_CLR) } } # [doc = "Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_NERR_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_NERR_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_NERR_CLR = 1 , } impl From < INT_EVENT0_ICLR_NERR_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_NERR_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_NERR` writer - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] pub type INT_EVENT0_ICLR_NERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_NERR_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_NERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_nerr_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_NERR_AW :: INT_EVENT0_ICLR_NERR_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_nerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_NERR_AW :: INT_EVENT0_ICLR_NERR_CLR) } } impl W { # [doc = "Bit 0 - Clear UARTOUT Receive Time-Out Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iclr_rtout (& mut self) -> INT_EVENT0_ICLR_RTOUT_W < INT_EVENT0_ICLR_SPEC , 0 > { INT_EVENT0_ICLR_RTOUT_W :: new (self) } # [doc = "Bit 1 - Clear UART Framing Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iclr_frmerr (& mut self) -> INT_EVENT0_ICLR_FRMERR_W < INT_EVENT0_ICLR_SPEC , 1 > { INT_EVENT0_ICLR_FRMERR_W :: new (self) } # [doc = "Bit 2 - Clear UART Parity Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iclr_parerr (& mut self) -> INT_EVENT0_ICLR_PARERR_W < INT_EVENT0_ICLR_SPEC , 2 > { INT_EVENT0_ICLR_PARERR_W :: new (self) } # [doc = "Bit 3 - Clear UART Break Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iclr_brkerr (& mut self) -> INT_EVENT0_ICLR_BRKERR_W < INT_EVENT0_ICLR_SPEC , 3 > { INT_EVENT0_ICLR_BRKERR_W :: new (self) } # [doc = "Bit 4 - Clear UART Receive Overrun Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iclr_ovrerr (& mut self) -> INT_EVENT0_ICLR_OVRERR_W < INT_EVENT0_ICLR_SPEC , 4 > { INT_EVENT0_ICLR_OVRERR_W :: new (self) } # [doc = "Bit 5 - Clear Negative Edge on UARTxRXD Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iclr_rxne (& mut self) -> INT_EVENT0_ICLR_RXNE_W < INT_EVENT0_ICLR_SPEC , 5 > { INT_EVENT0_ICLR_RXNE_W :: new (self) } # [doc = "Bit 6 - Clear Positive Edge on UARTxRXD Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iclr_rxpe (& mut self) -> INT_EVENT0_ICLR_RXPE_W < INT_EVENT0_ICLR_SPEC , 6 > { INT_EVENT0_ICLR_RXPE_W :: new (self) } # [doc = "Bit 7 - Clear LIN Capture 0 / Match Interrupt ."] # [inline (always)] # [must_use] pub fn int_event0_iclr_linc0 (& mut self) -> INT_EVENT0_ICLR_LINC0_W <'_,  INT_EVENT0_ICLR_SPEC , 7 > { INT_EVENT0_ICLR_LINC0_W :: new (self) } # [doc = "Bit 8 - Clear LIN Capture 1 Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iclr_linc1 (& mut self) -> INT_EVENT0_ICLR_LINC1_W < INT_EVENT0_ICLR_SPEC , 8 > { INT_EVENT0_ICLR_LINC1_W :: new (self) } # [doc = "Bit 9 - Clear LIN Hardware Counter Overflow Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iclr_linovf (& mut self) -> INT_EVENT0_ICLR_LINOVF_W < INT_EVENT0_ICLR_SPEC , 9 > { INT_EVENT0_ICLR_LINOVF_W :: new (self) } # [doc = "Bit 10 - Clear UART Receive Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iclr_rxint (& mut self) -> INT_EVENT0_ICLR_RXINT_W < INT_EVENT0_ICLR_SPEC , 10 > { INT_EVENT0_ICLR_RXINT_W :: new (self) } # [doc = "Bit 11 - Clear UART Transmit Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iclr_txint (& mut self) -> INT_EVENT0_ICLR_TXINT_W < INT_EVENT0_ICLR_SPEC , 11 > { INT_EVENT0_ICLR_TXINT_W :: new (self) } # [doc = "Bit 12 - Clear UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] # [inline (always)] # [must_use] pub fn int_event0_iclr_eot (& mut self) -> INT_EVENT0_ICLR_EOT_W < INT_EVENT0_ICLR_SPEC , 12 > { INT_EVENT0_ICLR_EOT_W :: new (self) } # [doc = "Bit 13 - Clear Address Match Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iclr_addr_match (& mut self) -> INT_EVENT0_ICLR_ADDR_MATCH_W < INT_EVENT0_ICLR_SPEC , 13 > { INT_EVENT0_ICLR_ADDR_MATCH_W :: new (self) } # [doc = "Bit 14 - Clear UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] # [inline (always)] # [must_use] pub fn int_event0_iclr_cts (& mut self) -> INT_EVENT0_ICLR_CTS_W < INT_EVENT0_ICLR_SPEC , 14 > { INT_EVENT0_ICLR_CTS_W :: new (self) } # [doc = "Bit 15 - Clear DMA Done on RX Event Channel"] # [inline (always)] # [must_use] pub fn int_event0_iclr_dma_done_rx (& mut self) -> INT_EVENT0_ICLR_DMA_DONE_RX_W < INT_EVENT0_ICLR_SPEC , 15 > { INT_EVENT0_ICLR_DMA_DONE_RX_W :: new (self) } # [doc = "Bit 16 - Clear DMA Done on TX Event Channel"] # [inline (always)] # [must_use] pub fn int_event0_iclr_dma_done_tx (& mut self) -> INT_EVENT0_ICLR_DMA_DONE_TX_W < INT_EVENT0_ICLR_SPEC , 16 > { INT_EVENT0_ICLR_DMA_DONE_TX_W :: new (self) } # [doc = "Bit 17 - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] # [inline (always)] # [must_use] pub fn int_event0_iclr_nerr (& mut self) -> INT_EVENT0_ICLR_NERR_W < INT_EVENT0_ICLR_SPEC , 17 > { INT_EVENT0_ICLR_NERR_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Interrupt clear\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_event0_iclr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct INT_EVENT0_ICLR_SPEC ; impl crate :: RegisterSpec for INT_EVENT0_ICLR_SPEC { type Ux = u32 ; } # [doc = "`write(|w| ..)` method takes [`int_event0_iclr::W`](W) writer structure"] impl crate :: Writable for INT_EVENT0_ICLR_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets INT_EVENT0_ICLR to value 0"] impl crate :: Resettable for INT_EVENT0_ICLR_SPEC { const RESET_VALUE : Self :: Ux = 0 ; }
[INFO] [stdout]   |                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                             +++
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing
[INFO] [stdout]  --> src/uart0/int_event0_iclr.rs:1:23525
[INFO] [stdout]   |
[INFO] [stdout] 1 | ...t0_iclr_linc1 (& mut self) -> INT_EVENT0_ICLR_LINC1_W < INT_EVENT0_ICLR_SPEC , 8 > { INT_EVENT0_ICLR_LINC1_W :: new (self) } # [do...
[INFO] [stdout]   |                   ^^^^^^^^^^     ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here
[INFO] [stdout]   |                   |
[INFO] [stdout]   |                   the lifetime is elided here
[INFO] [stdout]   |
[INFO] [stdout]   = help: the same lifetime is referred to in inconsistent ways, making the signature confusing
[INFO] [stdout] help: use `'_` for type paths
[INFO] [stdout]   |
[INFO] [stdout] 1 | # [doc = "Register `INT_EVENT0_ICLR` writer"] pub type W = crate :: W < INT_EVENT0_ICLR_SPEC > ; # [doc = "Clear UARTOUT Receive Time-Out Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_RTOUT_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_RTOUT_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_RTOUT_CLR = 1 , } impl From < INT_EVENT0_ICLR_RTOUT_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_RTOUT_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_RTOUT` writer - Clear UARTOUT Receive Time-Out Interrupt."] pub type INT_EVENT0_ICLR_RTOUT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_RTOUT_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_RTOUT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_rtout_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_RTOUT_AW :: INT_EVENT0_ICLR_RTOUT_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_rtout_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_RTOUT_AW :: INT_EVENT0_ICLR_RTOUT_CLR) } } # [doc = "Clear UART Framing Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_FRMERR_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_FRMERR_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_FRMERR_CLR = 1 , } impl From < INT_EVENT0_ICLR_FRMERR_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_FRMERR_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_FRMERR` writer - Clear UART Framing Error Interrupt."] pub type INT_EVENT0_ICLR_FRMERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_FRMERR_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_FRMERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_frmerr_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_FRMERR_AW :: INT_EVENT0_ICLR_FRMERR_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_frmerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_FRMERR_AW :: INT_EVENT0_ICLR_FRMERR_CLR) } } # [doc = "Clear UART Parity Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_PARERR_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_PARERR_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_PARERR_CLR = 1 , } impl From < INT_EVENT0_ICLR_PARERR_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_PARERR_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_PARERR` writer - Clear UART Parity Error Interrupt."] pub type INT_EVENT0_ICLR_PARERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_PARERR_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_PARERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_parerr_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_PARERR_AW :: INT_EVENT0_ICLR_PARERR_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_parerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_PARERR_AW :: INT_EVENT0_ICLR_PARERR_CLR) } } # [doc = "Clear UART Break Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_BRKERR_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_BRKERR_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_BRKERR_CLR = 1 , } impl From < INT_EVENT0_ICLR_BRKERR_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_BRKERR_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_BRKERR` writer - Clear UART Break Error Interrupt."] pub type INT_EVENT0_ICLR_BRKERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_BRKERR_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_BRKERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_brkerr_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_BRKERR_AW :: INT_EVENT0_ICLR_BRKERR_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_brkerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_BRKERR_AW :: INT_EVENT0_ICLR_BRKERR_CLR) } } # [doc = "Clear UART Receive Overrun Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_OVRERR_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_OVRERR_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_OVRERR_CLR = 1 , } impl From < INT_EVENT0_ICLR_OVRERR_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_OVRERR_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_OVRERR` writer - Clear UART Receive Overrun Error Interrupt."] pub type INT_EVENT0_ICLR_OVRERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_OVRERR_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_OVRERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_ovrerr_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_OVRERR_AW :: INT_EVENT0_ICLR_OVRERR_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_ovrerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_OVRERR_AW :: INT_EVENT0_ICLR_OVRERR_CLR) } } # [doc = "Clear Negative Edge on UARTxRXD Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_RXNE_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_RXNE_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_RXNE_CLR = 1 , } impl From < INT_EVENT0_ICLR_RXNE_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_RXNE_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_RXNE` writer - Clear Negative Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_ICLR_RXNE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_RXNE_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_RXNE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_rxne_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_RXNE_AW :: INT_EVENT0_ICLR_RXNE_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_rxne_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_RXNE_AW :: INT_EVENT0_ICLR_RXNE_CLR) } } # [doc = "Clear Positive Edge on UARTxRXD Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_RXPE_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_RXPE_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_RXPE_CLR = 1 , } impl From < INT_EVENT0_ICLR_RXPE_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_RXPE_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_RXPE` writer - Clear Positive Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_ICLR_RXPE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_RXPE_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_RXPE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_rxpe_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_RXPE_AW :: INT_EVENT0_ICLR_RXPE_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_rxpe_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_RXPE_AW :: INT_EVENT0_ICLR_RXPE_CLR) } } # [doc = "Clear LIN Capture 0 / Match Interrupt .\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_LINC0_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_LINC0_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_LINC0_CLR = 1 , } impl From < INT_EVENT0_ICLR_LINC0_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_LINC0_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_LINC0` writer - Clear LIN Capture 0 / Match Interrupt ."] pub type INT_EVENT0_ICLR_LINC0_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_LINC0_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_LINC0_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_linc0_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_LINC0_AW :: INT_EVENT0_ICLR_LINC0_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_linc0_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_LINC0_AW :: INT_EVENT0_ICLR_LINC0_CLR) } } # [doc = "Clear LIN Capture 1 Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_LINC1_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_LINC1_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_LINC1_CLR = 1 , } impl From < INT_EVENT0_ICLR_LINC1_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_LINC1_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_LINC1` writer - Clear LIN Capture 1 Interrupt."] pub type INT_EVENT0_ICLR_LINC1_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_LINC1_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_LINC1_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_linc1_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_LINC1_AW :: INT_EVENT0_ICLR_LINC1_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_linc1_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_LINC1_AW :: INT_EVENT0_ICLR_LINC1_CLR) } } # [doc = "Clear LIN Hardware Counter Overflow Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_LINOVF_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_LINOVF_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_LINOVF_CLR = 1 , } impl From < INT_EVENT0_ICLR_LINOVF_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_LINOVF_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_LINOVF` writer - Clear LIN Hardware Counter Overflow Interrupt."] pub type INT_EVENT0_ICLR_LINOVF_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_LINOVF_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_LINOVF_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_linovf_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_LINOVF_AW :: INT_EVENT0_ICLR_LINOVF_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_linovf_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_LINOVF_AW :: INT_EVENT0_ICLR_LINOVF_CLR) } } # [doc = "Clear UART Receive Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_RXINT_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_RXINT_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_RXINT_CLR = 1 , } impl From < INT_EVENT0_ICLR_RXINT_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_RXINT_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_RXINT` writer - Clear UART Receive Interrupt."] pub type INT_EVENT0_ICLR_RXINT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_RXINT_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_RXINT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_rxint_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_RXINT_AW :: INT_EVENT0_ICLR_RXINT_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_rxint_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_RXINT_AW :: INT_EVENT0_ICLR_RXINT_CLR) } } # [doc = "Clear UART Transmit Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_TXINT_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_TXINT_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_TXINT_CLR = 1 , } impl From < INT_EVENT0_ICLR_TXINT_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_TXINT_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_TXINT` writer - Clear UART Transmit Interrupt."] pub type INT_EVENT0_ICLR_TXINT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_TXINT_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_TXINT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_txint_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_TXINT_AW :: INT_EVENT0_ICLR_TXINT_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_txint_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_TXINT_AW :: INT_EVENT0_ICLR_TXINT_CLR) } } # [doc = "Clear UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_EOT_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_EOT_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_EOT_CLR = 1 , } impl From < INT_EVENT0_ICLR_EOT_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_EOT_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_EOT` writer - Clear UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] pub type INT_EVENT0_ICLR_EOT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_EOT_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_EOT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_eot_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_EOT_AW :: INT_EVENT0_ICLR_EOT_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_eot_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_EOT_AW :: INT_EVENT0_ICLR_EOT_CLR) } } # [doc = "Clear Address Match Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_ADDR_MATCH_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_ADDR_MATCH_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_ADDR_MATCH_CLR = 1 , } impl From < INT_EVENT0_ICLR_ADDR_MATCH_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_ADDR_MATCH_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_ADDR_MATCH` writer - Clear Address Match Interrupt."] pub type INT_EVENT0_ICLR_ADDR_MATCH_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_ADDR_MATCH_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_ADDR_MATCH_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_addr_match_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_ADDR_MATCH_AW :: INT_EVENT0_ICLR_ADDR_MATCH_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_addr_match_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_ADDR_MATCH_AW :: INT_EVENT0_ICLR_ADDR_MATCH_CLR) } } # [doc = "Clear UART Clear to Send Modem Interrupt. 0 = Interrupt disabled\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_CTS_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_CTS_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_CTS_CLR = 1 , } impl From < INT_EVENT0_ICLR_CTS_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_CTS_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_CTS` writer - Clear UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] pub type INT_EVENT0_ICLR_CTS_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_CTS_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_CTS_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_cts_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_CTS_AW :: INT_EVENT0_ICLR_CTS_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_cts_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_CTS_AW :: INT_EVENT0_ICLR_CTS_CLR) } } # [doc = "Clear DMA Done on RX Event Channel\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_DMA_DONE_RX_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_DMA_DONE_RX_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_DMA_DONE_RX_CLR = 1 , } impl From < INT_EVENT0_ICLR_DMA_DONE_RX_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_DMA_DONE_RX_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_DMA_DONE_RX` writer - Clear DMA Done on RX Event Channel"] pub type INT_EVENT0_ICLR_DMA_DONE_RX_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_DMA_DONE_RX_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_DMA_DONE_RX_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_dma_done_rx_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_DMA_DONE_RX_AW :: INT_EVENT0_ICLR_DMA_DONE_RX_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_dma_done_rx_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_DMA_DONE_RX_AW :: INT_EVENT0_ICLR_DMA_DONE_RX_CLR) } } # [doc = "Clear DMA Done on TX Event Channel\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_DMA_DONE_TX_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_DMA_DONE_TX_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_DMA_DONE_TX_CLR = 1 , } impl From < INT_EVENT0_ICLR_DMA_DONE_TX_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_DMA_DONE_TX_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_DMA_DONE_TX` writer - Clear DMA Done on TX Event Channel"] pub type INT_EVENT0_ICLR_DMA_DONE_TX_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_DMA_DONE_TX_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_DMA_DONE_TX_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_dma_done_tx_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_DMA_DONE_TX_AW :: INT_EVENT0_ICLR_DMA_DONE_TX_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_dma_done_tx_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_DMA_DONE_TX_AW :: INT_EVENT0_ICLR_DMA_DONE_TX_CLR) } } # [doc = "Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_NERR_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_NERR_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_NERR_CLR = 1 , } impl From < INT_EVENT0_ICLR_NERR_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_NERR_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_NERR` writer - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] pub type INT_EVENT0_ICLR_NERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_NERR_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_NERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_nerr_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_NERR_AW :: INT_EVENT0_ICLR_NERR_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_nerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_NERR_AW :: INT_EVENT0_ICLR_NERR_CLR) } } impl W { # [doc = "Bit 0 - Clear UARTOUT Receive Time-Out Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iclr_rtout (& mut self) -> INT_EVENT0_ICLR_RTOUT_W < INT_EVENT0_ICLR_SPEC , 0 > { INT_EVENT0_ICLR_RTOUT_W :: new (self) } # [doc = "Bit 1 - Clear UART Framing Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iclr_frmerr (& mut self) -> INT_EVENT0_ICLR_FRMERR_W < INT_EVENT0_ICLR_SPEC , 1 > { INT_EVENT0_ICLR_FRMERR_W :: new (self) } # [doc = "Bit 2 - Clear UART Parity Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iclr_parerr (& mut self) -> INT_EVENT0_ICLR_PARERR_W < INT_EVENT0_ICLR_SPEC , 2 > { INT_EVENT0_ICLR_PARERR_W :: new (self) } # [doc = "Bit 3 - Clear UART Break Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iclr_brkerr (& mut self) -> INT_EVENT0_ICLR_BRKERR_W < INT_EVENT0_ICLR_SPEC , 3 > { INT_EVENT0_ICLR_BRKERR_W :: new (self) } # [doc = "Bit 4 - Clear UART Receive Overrun Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iclr_ovrerr (& mut self) -> INT_EVENT0_ICLR_OVRERR_W < INT_EVENT0_ICLR_SPEC , 4 > { INT_EVENT0_ICLR_OVRERR_W :: new (self) } # [doc = "Bit 5 - Clear Negative Edge on UARTxRXD Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iclr_rxne (& mut self) -> INT_EVENT0_ICLR_RXNE_W < INT_EVENT0_ICLR_SPEC , 5 > { INT_EVENT0_ICLR_RXNE_W :: new (self) } # [doc = "Bit 6 - Clear Positive Edge on UARTxRXD Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iclr_rxpe (& mut self) -> INT_EVENT0_ICLR_RXPE_W < INT_EVENT0_ICLR_SPEC , 6 > { INT_EVENT0_ICLR_RXPE_W :: new (self) } # [doc = "Bit 7 - Clear LIN Capture 0 / Match Interrupt ."] # [inline (always)] # [must_use] pub fn int_event0_iclr_linc0 (& mut self) -> INT_EVENT0_ICLR_LINC0_W < INT_EVENT0_ICLR_SPEC , 7 > { INT_EVENT0_ICLR_LINC0_W :: new (self) } # [doc = "Bit 8 - Clear LIN Capture 1 Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iclr_linc1 (& mut self) -> INT_EVENT0_ICLR_LINC1_W <'_,  INT_EVENT0_ICLR_SPEC , 8 > { INT_EVENT0_ICLR_LINC1_W :: new (self) } # [doc = "Bit 9 - Clear LIN Hardware Counter Overflow Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iclr_linovf (& mut self) -> INT_EVENT0_ICLR_LINOVF_W < INT_EVENT0_ICLR_SPEC , 9 > { INT_EVENT0_ICLR_LINOVF_W :: new (self) } # [doc = "Bit 10 - Clear UART Receive Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iclr_rxint (& mut self) -> INT_EVENT0_ICLR_RXINT_W < INT_EVENT0_ICLR_SPEC , 10 > { INT_EVENT0_ICLR_RXINT_W :: new (self) } # [doc = "Bit 11 - Clear UART Transmit Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iclr_txint (& mut self) -> INT_EVENT0_ICLR_TXINT_W < INT_EVENT0_ICLR_SPEC , 11 > { INT_EVENT0_ICLR_TXINT_W :: new (self) } # [doc = "Bit 12 - Clear UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] # [inline (always)] # [must_use] pub fn int_event0_iclr_eot (& mut self) -> INT_EVENT0_ICLR_EOT_W < INT_EVENT0_ICLR_SPEC , 12 > { INT_EVENT0_ICLR_EOT_W :: new (self) } # [doc = "Bit 13 - Clear Address Match Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iclr_addr_match (& mut self) -> INT_EVENT0_ICLR_ADDR_MATCH_W < INT_EVENT0_ICLR_SPEC , 13 > { INT_EVENT0_ICLR_ADDR_MATCH_W :: new (self) } # [doc = "Bit 14 - Clear UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] # [inline (always)] # [must_use] pub fn int_event0_iclr_cts (& mut self) -> INT_EVENT0_ICLR_CTS_W < INT_EVENT0_ICLR_SPEC , 14 > { INT_EVENT0_ICLR_CTS_W :: new (self) } # [doc = "Bit 15 - Clear DMA Done on RX Event Channel"] # [inline (always)] # [must_use] pub fn int_event0_iclr_dma_done_rx (& mut self) -> INT_EVENT0_ICLR_DMA_DONE_RX_W < INT_EVENT0_ICLR_SPEC , 15 > { INT_EVENT0_ICLR_DMA_DONE_RX_W :: new (self) } # [doc = "Bit 16 - Clear DMA Done on TX Event Channel"] # [inline (always)] # [must_use] pub fn int_event0_iclr_dma_done_tx (& mut self) -> INT_EVENT0_ICLR_DMA_DONE_TX_W < INT_EVENT0_ICLR_SPEC , 16 > { INT_EVENT0_ICLR_DMA_DONE_TX_W :: new (self) } # [doc = "Bit 17 - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] # [inline (always)] # [must_use] pub fn int_event0_iclr_nerr (& mut self) -> INT_EVENT0_ICLR_NERR_W < INT_EVENT0_ICLR_SPEC , 17 > { INT_EVENT0_ICLR_NERR_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Interrupt clear\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_event0_iclr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct INT_EVENT0_ICLR_SPEC ; impl crate :: RegisterSpec for INT_EVENT0_ICLR_SPEC { type Ux = u32 ; } # [doc = "`write(|w| ..)` method takes [`int_event0_iclr::W`](W) writer structure"] impl crate :: Writable for INT_EVENT0_ICLR_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets INT_EVENT0_ICLR to value 0"] impl crate :: Resettable for INT_EVENT0_ICLR_SPEC { const RESET_VALUE : Self :: Ux = 0 ; }
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                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                              +++
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing
[INFO] [stdout]  --> src/uart0/int_event0_iclr.rs:1:23766
[INFO] [stdout]   |
[INFO] [stdout] 1 | ..._iclr_linovf (& mut self) -> INT_EVENT0_ICLR_LINOVF_W < INT_EVENT0_ICLR_SPEC , 9 > { INT_EVENT0_ICLR_LINOVF_W :: new (self) } # [d...
[INFO] [stdout]   |                  ^^^^^^^^^^     ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here
[INFO] [stdout]   |                  |
[INFO] [stdout]   |                  the lifetime is elided here
[INFO] [stdout]   |
[INFO] [stdout]   = help: the same lifetime is referred to in inconsistent ways, making the signature confusing
[INFO] [stdout] help: use `'_` for type paths
[INFO] [stdout]   |
[INFO] [stdout] 1 | # [doc = "Register `INT_EVENT0_ICLR` writer"] pub type W = crate :: W < INT_EVENT0_ICLR_SPEC > ; # [doc = "Clear UARTOUT Receive Time-Out Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_RTOUT_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_RTOUT_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_RTOUT_CLR = 1 , } impl From < INT_EVENT0_ICLR_RTOUT_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_RTOUT_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_RTOUT` writer - Clear UARTOUT Receive Time-Out Interrupt."] pub type INT_EVENT0_ICLR_RTOUT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_RTOUT_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_RTOUT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_rtout_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_RTOUT_AW :: INT_EVENT0_ICLR_RTOUT_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_rtout_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_RTOUT_AW :: INT_EVENT0_ICLR_RTOUT_CLR) } } # [doc = "Clear UART Framing Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_FRMERR_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_FRMERR_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_FRMERR_CLR = 1 , } impl From < INT_EVENT0_ICLR_FRMERR_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_FRMERR_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_FRMERR` writer - Clear UART Framing Error Interrupt."] pub type INT_EVENT0_ICLR_FRMERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_FRMERR_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_FRMERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_frmerr_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_FRMERR_AW :: INT_EVENT0_ICLR_FRMERR_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_frmerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_FRMERR_AW :: INT_EVENT0_ICLR_FRMERR_CLR) } } # [doc = "Clear UART Parity Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_PARERR_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_PARERR_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_PARERR_CLR = 1 , } impl From < INT_EVENT0_ICLR_PARERR_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_PARERR_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_PARERR` writer - Clear UART Parity Error Interrupt."] pub type INT_EVENT0_ICLR_PARERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_PARERR_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_PARERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_parerr_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_PARERR_AW :: INT_EVENT0_ICLR_PARERR_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_parerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_PARERR_AW :: INT_EVENT0_ICLR_PARERR_CLR) } } # [doc = "Clear UART Break Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_BRKERR_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_BRKERR_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_BRKERR_CLR = 1 , } impl From < INT_EVENT0_ICLR_BRKERR_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_BRKERR_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_BRKERR` writer - Clear UART Break Error Interrupt."] pub type INT_EVENT0_ICLR_BRKERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_BRKERR_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_BRKERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_brkerr_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_BRKERR_AW :: INT_EVENT0_ICLR_BRKERR_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_brkerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_BRKERR_AW :: INT_EVENT0_ICLR_BRKERR_CLR) } } # [doc = "Clear UART Receive Overrun Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_OVRERR_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_OVRERR_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_OVRERR_CLR = 1 , } impl From < INT_EVENT0_ICLR_OVRERR_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_OVRERR_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_OVRERR` writer - Clear UART Receive Overrun Error Interrupt."] pub type INT_EVENT0_ICLR_OVRERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_OVRERR_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_OVRERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_ovrerr_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_OVRERR_AW :: INT_EVENT0_ICLR_OVRERR_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_ovrerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_OVRERR_AW :: INT_EVENT0_ICLR_OVRERR_CLR) } } # [doc = "Clear Negative Edge on UARTxRXD Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_RXNE_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_RXNE_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_RXNE_CLR = 1 , } impl From < INT_EVENT0_ICLR_RXNE_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_RXNE_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_RXNE` writer - Clear Negative Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_ICLR_RXNE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_RXNE_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_RXNE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_rxne_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_RXNE_AW :: INT_EVENT0_ICLR_RXNE_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_rxne_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_RXNE_AW :: INT_EVENT0_ICLR_RXNE_CLR) } } # [doc = "Clear Positive Edge on UARTxRXD Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_RXPE_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_RXPE_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_RXPE_CLR = 1 , } impl From < INT_EVENT0_ICLR_RXPE_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_RXPE_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_RXPE` writer - Clear Positive Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_ICLR_RXPE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_RXPE_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_RXPE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_rxpe_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_RXPE_AW :: INT_EVENT0_ICLR_RXPE_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_rxpe_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_RXPE_AW :: INT_EVENT0_ICLR_RXPE_CLR) } } # [doc = "Clear LIN Capture 0 / Match Interrupt .\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_LINC0_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_LINC0_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_LINC0_CLR = 1 , } impl From < INT_EVENT0_ICLR_LINC0_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_LINC0_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_LINC0` writer - Clear LIN Capture 0 / Match Interrupt ."] pub type INT_EVENT0_ICLR_LINC0_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_LINC0_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_LINC0_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_linc0_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_LINC0_AW :: INT_EVENT0_ICLR_LINC0_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_linc0_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_LINC0_AW :: INT_EVENT0_ICLR_LINC0_CLR) } } # [doc = "Clear LIN Capture 1 Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_LINC1_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_LINC1_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_LINC1_CLR = 1 , } impl From < INT_EVENT0_ICLR_LINC1_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_LINC1_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_LINC1` writer - Clear LIN Capture 1 Interrupt."] pub type INT_EVENT0_ICLR_LINC1_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_LINC1_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_LINC1_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_linc1_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_LINC1_AW :: INT_EVENT0_ICLR_LINC1_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_linc1_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_LINC1_AW :: INT_EVENT0_ICLR_LINC1_CLR) } } # [doc = "Clear LIN Hardware Counter Overflow Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_LINOVF_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_LINOVF_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_LINOVF_CLR = 1 , } impl From < INT_EVENT0_ICLR_LINOVF_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_LINOVF_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_LINOVF` writer - Clear LIN Hardware Counter Overflow Interrupt."] pub type INT_EVENT0_ICLR_LINOVF_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_LINOVF_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_LINOVF_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_linovf_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_LINOVF_AW :: INT_EVENT0_ICLR_LINOVF_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_linovf_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_LINOVF_AW :: INT_EVENT0_ICLR_LINOVF_CLR) } } # [doc = "Clear UART Receive Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_RXINT_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_RXINT_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_RXINT_CLR = 1 , } impl From < INT_EVENT0_ICLR_RXINT_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_RXINT_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_RXINT` writer - Clear UART Receive Interrupt."] pub type INT_EVENT0_ICLR_RXINT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_RXINT_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_RXINT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_rxint_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_RXINT_AW :: INT_EVENT0_ICLR_RXINT_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_rxint_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_RXINT_AW :: INT_EVENT0_ICLR_RXINT_CLR) } } # [doc = "Clear UART Transmit Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_TXINT_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_TXINT_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_TXINT_CLR = 1 , } impl From < INT_EVENT0_ICLR_TXINT_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_TXINT_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_TXINT` writer - Clear UART Transmit Interrupt."] pub type INT_EVENT0_ICLR_TXINT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_TXINT_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_TXINT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_txint_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_TXINT_AW :: INT_EVENT0_ICLR_TXINT_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_txint_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_TXINT_AW :: INT_EVENT0_ICLR_TXINT_CLR) } } # [doc = "Clear UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_EOT_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_EOT_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_EOT_CLR = 1 , } impl From < INT_EVENT0_ICLR_EOT_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_EOT_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_EOT` writer - Clear UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] pub type INT_EVENT0_ICLR_EOT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_EOT_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_EOT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_eot_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_EOT_AW :: INT_EVENT0_ICLR_EOT_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_eot_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_EOT_AW :: INT_EVENT0_ICLR_EOT_CLR) } } # [doc = "Clear Address Match Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_ADDR_MATCH_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_ADDR_MATCH_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_ADDR_MATCH_CLR = 1 , } impl From < INT_EVENT0_ICLR_ADDR_MATCH_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_ADDR_MATCH_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_ADDR_MATCH` writer - Clear Address Match Interrupt."] pub type INT_EVENT0_ICLR_ADDR_MATCH_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_ADDR_MATCH_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_ADDR_MATCH_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_addr_match_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_ADDR_MATCH_AW :: INT_EVENT0_ICLR_ADDR_MATCH_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_addr_match_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_ADDR_MATCH_AW :: INT_EVENT0_ICLR_ADDR_MATCH_CLR) } } # [doc = "Clear UART Clear to Send Modem Interrupt. 0 = Interrupt disabled\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_CTS_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_CTS_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_CTS_CLR = 1 , } impl From < INT_EVENT0_ICLR_CTS_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_CTS_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_CTS` writer - Clear UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] pub type INT_EVENT0_ICLR_CTS_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_CTS_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_CTS_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_cts_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_CTS_AW :: INT_EVENT0_ICLR_CTS_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_cts_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_CTS_AW :: INT_EVENT0_ICLR_CTS_CLR) } } # [doc = "Clear DMA Done on RX Event Channel\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_DMA_DONE_RX_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_DMA_DONE_RX_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_DMA_DONE_RX_CLR = 1 , } impl From < INT_EVENT0_ICLR_DMA_DONE_RX_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_DMA_DONE_RX_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_DMA_DONE_RX` writer - Clear DMA Done on RX Event Channel"] pub type INT_EVENT0_ICLR_DMA_DONE_RX_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_DMA_DONE_RX_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_DMA_DONE_RX_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_dma_done_rx_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_DMA_DONE_RX_AW :: INT_EVENT0_ICLR_DMA_DONE_RX_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_dma_done_rx_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_DMA_DONE_RX_AW :: INT_EVENT0_ICLR_DMA_DONE_RX_CLR) } } # [doc = "Clear DMA Done on TX Event Channel\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_DMA_DONE_TX_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_DMA_DONE_TX_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_DMA_DONE_TX_CLR = 1 , } impl From < INT_EVENT0_ICLR_DMA_DONE_TX_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_DMA_DONE_TX_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_DMA_DONE_TX` writer - Clear DMA Done on TX Event Channel"] pub type INT_EVENT0_ICLR_DMA_DONE_TX_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_DMA_DONE_TX_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_DMA_DONE_TX_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_dma_done_tx_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_DMA_DONE_TX_AW :: INT_EVENT0_ICLR_DMA_DONE_TX_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_dma_done_tx_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_DMA_DONE_TX_AW :: INT_EVENT0_ICLR_DMA_DONE_TX_CLR) } } # [doc = "Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_NERR_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_NERR_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_NERR_CLR = 1 , } impl From < INT_EVENT0_ICLR_NERR_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_NERR_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_NERR` writer - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] pub type INT_EVENT0_ICLR_NERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_NERR_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_NERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_nerr_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_NERR_AW :: INT_EVENT0_ICLR_NERR_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_nerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_NERR_AW :: INT_EVENT0_ICLR_NERR_CLR) } } impl W { # [doc = "Bit 0 - Clear UARTOUT Receive Time-Out Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iclr_rtout (& mut self) -> INT_EVENT0_ICLR_RTOUT_W < INT_EVENT0_ICLR_SPEC , 0 > { INT_EVENT0_ICLR_RTOUT_W :: new (self) } # [doc = "Bit 1 - Clear UART Framing Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iclr_frmerr (& mut self) -> INT_EVENT0_ICLR_FRMERR_W < INT_EVENT0_ICLR_SPEC , 1 > { INT_EVENT0_ICLR_FRMERR_W :: new (self) } # [doc = "Bit 2 - Clear UART Parity Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iclr_parerr (& mut self) -> INT_EVENT0_ICLR_PARERR_W < INT_EVENT0_ICLR_SPEC , 2 > { INT_EVENT0_ICLR_PARERR_W :: new (self) } # [doc = "Bit 3 - Clear UART Break Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iclr_brkerr (& mut self) -> INT_EVENT0_ICLR_BRKERR_W < INT_EVENT0_ICLR_SPEC , 3 > { INT_EVENT0_ICLR_BRKERR_W :: new (self) } # [doc = "Bit 4 - Clear UART Receive Overrun Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iclr_ovrerr (& mut self) -> INT_EVENT0_ICLR_OVRERR_W < INT_EVENT0_ICLR_SPEC , 4 > { INT_EVENT0_ICLR_OVRERR_W :: new (self) } # [doc = "Bit 5 - Clear Negative Edge on UARTxRXD Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iclr_rxne (& mut self) -> INT_EVENT0_ICLR_RXNE_W < INT_EVENT0_ICLR_SPEC , 5 > { INT_EVENT0_ICLR_RXNE_W :: new (self) } # [doc = "Bit 6 - Clear Positive Edge on UARTxRXD Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iclr_rxpe (& mut self) -> INT_EVENT0_ICLR_RXPE_W < INT_EVENT0_ICLR_SPEC , 6 > { INT_EVENT0_ICLR_RXPE_W :: new (self) } # [doc = "Bit 7 - Clear LIN Capture 0 / Match Interrupt ."] # [inline (always)] # [must_use] pub fn int_event0_iclr_linc0 (& mut self) -> INT_EVENT0_ICLR_LINC0_W < INT_EVENT0_ICLR_SPEC , 7 > { INT_EVENT0_ICLR_LINC0_W :: new (self) } # [doc = "Bit 8 - Clear LIN Capture 1 Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iclr_linc1 (& mut self) -> INT_EVENT0_ICLR_LINC1_W < INT_EVENT0_ICLR_SPEC , 8 > { INT_EVENT0_ICLR_LINC1_W :: new (self) } # [doc = "Bit 9 - Clear LIN Hardware Counter Overflow Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iclr_linovf (& mut self) -> INT_EVENT0_ICLR_LINOVF_W <'_,  INT_EVENT0_ICLR_SPEC , 9 > { INT_EVENT0_ICLR_LINOVF_W :: new (self) } # [doc = "Bit 10 - Clear UART Receive Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iclr_rxint (& mut self) -> INT_EVENT0_ICLR_RXINT_W < INT_EVENT0_ICLR_SPEC , 10 > { INT_EVENT0_ICLR_RXINT_W :: new (self) } # [doc = "Bit 11 - Clear UART Transmit Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iclr_txint (& mut self) -> INT_EVENT0_ICLR_TXINT_W < INT_EVENT0_ICLR_SPEC , 11 > { INT_EVENT0_ICLR_TXINT_W :: new (self) } # [doc = "Bit 12 - Clear UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] # [inline (always)] # [must_use] pub fn int_event0_iclr_eot (& mut self) -> INT_EVENT0_ICLR_EOT_W < INT_EVENT0_ICLR_SPEC , 12 > { INT_EVENT0_ICLR_EOT_W :: new (self) } # [doc = "Bit 13 - Clear Address Match Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iclr_addr_match (& mut self) -> INT_EVENT0_ICLR_ADDR_MATCH_W < INT_EVENT0_ICLR_SPEC , 13 > { INT_EVENT0_ICLR_ADDR_MATCH_W :: new (self) } # [doc = "Bit 14 - Clear UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] # [inline (always)] # [must_use] pub fn int_event0_iclr_cts (& mut self) -> INT_EVENT0_ICLR_CTS_W < INT_EVENT0_ICLR_SPEC , 14 > { INT_EVENT0_ICLR_CTS_W :: new (self) } # [doc = "Bit 15 - Clear DMA Done on RX Event Channel"] # [inline (always)] # [must_use] pub fn int_event0_iclr_dma_done_rx (& mut self) -> INT_EVENT0_ICLR_DMA_DONE_RX_W < INT_EVENT0_ICLR_SPEC , 15 > { INT_EVENT0_ICLR_DMA_DONE_RX_W :: new (self) } # [doc = "Bit 16 - Clear DMA Done on TX Event Channel"] # [inline (always)] # [must_use] pub fn int_event0_iclr_dma_done_tx (& mut self) -> INT_EVENT0_ICLR_DMA_DONE_TX_W < INT_EVENT0_ICLR_SPEC , 16 > { INT_EVENT0_ICLR_DMA_DONE_TX_W :: new (self) } # [doc = "Bit 17 - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] # [inline (always)] # [must_use] pub fn int_event0_iclr_nerr (& mut self) -> INT_EVENT0_ICLR_NERR_W < INT_EVENT0_ICLR_SPEC , 17 > { INT_EVENT0_ICLR_NERR_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Interrupt clear\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_event0_iclr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct INT_EVENT0_ICLR_SPEC ; impl crate :: RegisterSpec for INT_EVENT0_ICLR_SPEC { type Ux = u32 ; } # [doc = "`write(|w| ..)` method takes [`int_event0_iclr::W`](W) writer structure"] impl crate :: Writable for INT_EVENT0_ICLR_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets INT_EVENT0_ICLR to value 0"] impl crate :: Resettable for INT_EVENT0_ICLR_SPEC { const RESET_VALUE : Self :: Ux = 0 ; }
[INFO] [stdout]   |                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                               +++
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing
[INFO] [stdout]  --> src/uart0/int_event0_imask.rs:1:40733
[INFO] [stdout]   |
[INFO] [stdout] 1 | ...mask_frmerr (& mut self) -> INT_EVENT0_IMASK_FRMERR_W < INT_EVENT0_IMASK_SPEC , 1 > { INT_EVENT0_IMASK_FRMERR_W :: new (self) } # ...
[INFO] [stdout]   |                 ^^^^^^^^^^     ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here
[INFO] [stdout]   |                 |
[INFO] [stdout]   |                 the lifetime is elided here
[INFO] [stdout]   |
[INFO] [stdout]   = help: the same lifetime is referred to in inconsistent ways, making the signature confusing
[INFO] [stdout] help: use `'_` for type paths
[INFO] [stdout]   |
[INFO] [stdout] 1 | # [doc = "Register `INT_EVENT0_IMASK` reader"] pub type R = crate :: R < INT_EVENT0_IMASK_SPEC > ; # [doc = "Register `INT_EVENT0_IMASK` writer"] pub type W = crate :: W < INT_EVENT0_IMASK_SPEC > ; # [doc = "Field `INT_EVENT0_IMASK_RTOUT` reader - Enable UARTOUT Receive Time-Out Interrupt."] pub type INT_EVENT0_IMASK_RTOUT_R = crate :: BitReader < INT_EVENT0_IMASK_RTOUT_A > ; # [doc = "Enable UARTOUT Receive Time-Out Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_RTOUT_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_RTOUT_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_RTOUT_SET = 1 , } impl From < INT_EVENT0_IMASK_RTOUT_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_RTOUT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_RTOUT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_RTOUT_A { match self . bits { false => INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_CLR , true => INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_rtout_clr (& self) -> bool { * self == INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_rtout_set (& self) -> bool { * self == INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_SET } } # [doc = "Field `INT_EVENT0_IMASK_RTOUT` writer - Enable UARTOUT Receive Time-Out Interrupt."] pub type INT_EVENT0_IMASK_RTOUT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_RTOUT_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_RTOUT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_rtout_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_rtout_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_SET) } } # [doc = "Field `INT_EVENT0_IMASK_FRMERR` reader - Enable UART Framing Error Interrupt."] pub type INT_EVENT0_IMASK_FRMERR_R = crate :: BitReader < INT_EVENT0_IMASK_FRMERR_A > ; # [doc = "Enable UART Framing Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_FRMERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_FRMERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_FRMERR_SET = 1 , } impl From < INT_EVENT0_IMASK_FRMERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_FRMERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_FRMERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_FRMERR_A { match self . bits { false => INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_CLR , true => INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_frmerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_frmerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_FRMERR` writer - Enable UART Framing Error Interrupt."] pub type INT_EVENT0_IMASK_FRMERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_FRMERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_FRMERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_frmerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_frmerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_SET) } } # [doc = "Field `INT_EVENT0_IMASK_PARERR` reader - Enable UART Parity Error Interrupt."] pub type INT_EVENT0_IMASK_PARERR_R = crate :: BitReader < INT_EVENT0_IMASK_PARERR_A > ; # [doc = "Enable UART Parity Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_PARERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_PARERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_PARERR_SET = 1 , } impl From < INT_EVENT0_IMASK_PARERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_PARERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_PARERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_PARERR_A { match self . bits { false => INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_CLR , true => INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_parerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_parerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_PARERR` writer - Enable UART Parity Error Interrupt."] pub type INT_EVENT0_IMASK_PARERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_PARERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_PARERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_parerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_parerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_SET) } } # [doc = "Field `INT_EVENT0_IMASK_BRKERR` reader - Enable UART Break Error Interrupt."] pub type INT_EVENT0_IMASK_BRKERR_R = crate :: BitReader < INT_EVENT0_IMASK_BRKERR_A > ; # [doc = "Enable UART Break Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_BRKERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_BRKERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_BRKERR_SET = 1 , } impl From < INT_EVENT0_IMASK_BRKERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_BRKERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_BRKERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_BRKERR_A { match self . bits { false => INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_CLR , true => INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_brkerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_brkerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_BRKERR` writer - Enable UART Break Error Interrupt."] pub type INT_EVENT0_IMASK_BRKERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_BRKERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_BRKERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_brkerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_brkerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_SET) } } # [doc = "Field `INT_EVENT0_IMASK_OVRERR` reader - Enable UART Receive Overrun Error Interrupt."] pub type INT_EVENT0_IMASK_OVRERR_R = crate :: BitReader < INT_EVENT0_IMASK_OVRERR_A > ; # [doc = "Enable UART Receive Overrun Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_OVRERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_OVRERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_OVRERR_SET = 1 , } impl From < INT_EVENT0_IMASK_OVRERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_OVRERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_OVRERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_OVRERR_A { match self . bits { false => INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_CLR , true => INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_ovrerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_ovrerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_OVRERR` writer - Enable UART Receive Overrun Error Interrupt."] pub type INT_EVENT0_IMASK_OVRERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_OVRERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_OVRERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_ovrerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_ovrerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_SET) } } # [doc = "Field `INT_EVENT0_IMASK_RXNE` reader - Enable Negative Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_IMASK_RXNE_R = crate :: BitReader < INT_EVENT0_IMASK_RXNE_A > ; # [doc = "Enable Negative Edge on UARTxRXD Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_RXNE_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_RXNE_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_RXNE_SET = 1 , } impl From < INT_EVENT0_IMASK_RXNE_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_RXNE_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_RXNE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_RXNE_A { match self . bits { false => INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_CLR , true => INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_rxne_clr (& self) -> bool { * self == INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_rxne_set (& self) -> bool { * self == INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_SET } } # [doc = "Field `INT_EVENT0_IMASK_RXNE` writer - Enable Negative Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_IMASK_RXNE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_RXNE_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_RXNE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_rxne_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_rxne_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_SET) } } # [doc = "Field `INT_EVENT0_IMASK_RXPE` reader - Enable Positive Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_IMASK_RXPE_R = crate :: BitReader < INT_EVENT0_IMASK_RXPE_A > ; # [doc = "Enable Positive Edge on UARTxRXD Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_RXPE_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_RXPE_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_RXPE_SET = 1 , } impl From < INT_EVENT0_IMASK_RXPE_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_RXPE_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_RXPE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_RXPE_A { match self . bits { false => INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_CLR , true => INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_rxpe_clr (& self) -> bool { * self == INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_rxpe_set (& self) -> bool { * self == INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_SET } } # [doc = "Field `INT_EVENT0_IMASK_RXPE` writer - Enable Positive Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_IMASK_RXPE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_RXPE_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_RXPE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_rxpe_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_rxpe_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_SET) } } # [doc = "Field `INT_EVENT0_IMASK_LINC0` reader - Enable LIN Capture 0 / Match Interrupt ."] pub type INT_EVENT0_IMASK_LINC0_R = crate :: BitReader < INT_EVENT0_IMASK_LINC0_A > ; # [doc = "Enable LIN Capture 0 / Match Interrupt .\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_LINC0_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_LINC0_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_LINC0_SET = 1 , } impl From < INT_EVENT0_IMASK_LINC0_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_LINC0_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_LINC0_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_LINC0_A { match self . bits { false => INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_CLR , true => INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_linc0_clr (& self) -> bool { * self == INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_linc0_set (& self) -> bool { * self == INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_SET } } # [doc = "Field `INT_EVENT0_IMASK_LINC0` writer - Enable LIN Capture 0 / Match Interrupt ."] pub type INT_EVENT0_IMASK_LINC0_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_LINC0_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_LINC0_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_linc0_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_linc0_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_SET) } } # [doc = "Field `INT_EVENT0_IMASK_LINC1` reader - Enable LIN Capture 1 Interrupt."] pub type INT_EVENT0_IMASK_LINC1_R = crate :: BitReader < INT_EVENT0_IMASK_LINC1_A > ; # [doc = "Enable LIN Capture 1 Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_LINC1_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_LINC1_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_LINC1_SET = 1 , } impl From < INT_EVENT0_IMASK_LINC1_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_LINC1_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_LINC1_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_LINC1_A { match self . bits { false => INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_CLR , true => INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_linc1_clr (& self) -> bool { * self == INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_linc1_set (& self) -> bool { * self == INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_SET } } # [doc = "Field `INT_EVENT0_IMASK_LINC1` writer - Enable LIN Capture 1 Interrupt."] pub type INT_EVENT0_IMASK_LINC1_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_LINC1_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_LINC1_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_linc1_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_linc1_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_SET) } } # [doc = "Field `INT_EVENT0_IMASK_LINOVF` reader - Enable LIN Hardware Counter Overflow Interrupt."] pub type INT_EVENT0_IMASK_LINOVF_R = crate :: BitReader < INT_EVENT0_IMASK_LINOVF_A > ; # [doc = "Enable LIN Hardware Counter Overflow Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_LINOVF_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_LINOVF_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_LINOVF_SET = 1 , } impl From < INT_EVENT0_IMASK_LINOVF_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_LINOVF_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_LINOVF_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_LINOVF_A { match self . bits { false => INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_CLR , true => INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_linovf_clr (& self) -> bool { * self == INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_linovf_set (& self) -> bool { * self == INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_SET } } # [doc = "Field `INT_EVENT0_IMASK_LINOVF` writer - Enable LIN Hardware Counter Overflow Interrupt."] pub type INT_EVENT0_IMASK_LINOVF_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_LINOVF_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_LINOVF_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_linovf_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_linovf_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_SET) } } # [doc = "Field `INT_EVENT0_IMASK_RXINT` reader - Enable UART Receive Interrupt."] pub type INT_EVENT0_IMASK_RXINT_R = crate :: BitReader < INT_EVENT0_IMASK_RXINT_A > ; # [doc = "Enable UART Receive Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_RXINT_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_RXINT_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_RXINT_SET = 1 , } impl From < INT_EVENT0_IMASK_RXINT_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_RXINT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_RXINT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_RXINT_A { match self . bits { false => INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_CLR , true => INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_rxint_clr (& self) -> bool { * self == INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_rxint_set (& self) -> bool { * self == INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_SET } } # [doc = "Field `INT_EVENT0_IMASK_RXINT` writer - Enable UART Receive Interrupt."] pub type INT_EVENT0_IMASK_RXINT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_RXINT_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_RXINT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_rxint_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_rxint_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_SET) } } # [doc = "Field `INT_EVENT0_IMASK_TXINT` reader - Enable UART Transmit Interrupt."] pub type INT_EVENT0_IMASK_TXINT_R = crate :: BitReader < INT_EVENT0_IMASK_TXINT_A > ; # [doc = "Enable UART Transmit Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_TXINT_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_TXINT_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_TXINT_SET = 1 , } impl From < INT_EVENT0_IMASK_TXINT_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_TXINT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_TXINT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_TXINT_A { match self . bits { false => INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_CLR , true => INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_txint_clr (& self) -> bool { * self == INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_txint_set (& self) -> bool { * self == INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_SET } } # [doc = "Field `INT_EVENT0_IMASK_TXINT` writer - Enable UART Transmit Interrupt."] pub type INT_EVENT0_IMASK_TXINT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_TXINT_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_TXINT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_txint_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_txint_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_SET) } } # [doc = "Field `INT_EVENT0_IMASK_EOT` reader - Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] pub type INT_EVENT0_IMASK_EOT_R = crate :: BitReader < INT_EVENT0_IMASK_EOT_A > ; # [doc = "Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_EOT_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_EOT_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_EOT_SET = 1 , } impl From < INT_EVENT0_IMASK_EOT_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_EOT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_EOT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_EOT_A { match self . bits { false => INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_CLR , true => INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_eot_clr (& self) -> bool { * self == INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_eot_set (& self) -> bool { * self == INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_SET } } # [doc = "Field `INT_EVENT0_IMASK_EOT` writer - Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] pub type INT_EVENT0_IMASK_EOT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_EOT_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_EOT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_eot_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_eot_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_SET) } } # [doc = "Field `INT_EVENT0_IMASK_ADDR_MATCH` reader - Enable Address Match Interrupt."] pub type INT_EVENT0_IMASK_ADDR_MATCH_R = crate :: BitReader < INT_EVENT0_IMASK_ADDR_MATCH_A > ; # [doc = "Enable Address Match Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_ADDR_MATCH_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_ADDR_MATCH_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_ADDR_MATCH_SET = 1 , } impl From < INT_EVENT0_IMASK_ADDR_MATCH_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_ADDR_MATCH_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_ADDR_MATCH_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_ADDR_MATCH_A { match self . bits { false => INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_CLR , true => INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_addr_match_clr (& self) -> bool { * self == INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_addr_match_set (& self) -> bool { * self == INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_SET } } # [doc = "Field `INT_EVENT0_IMASK_ADDR_MATCH` writer - Enable Address Match Interrupt."] pub type INT_EVENT0_IMASK_ADDR_MATCH_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_ADDR_MATCH_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_ADDR_MATCH_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_addr_match_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_addr_match_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_SET) } } # [doc = "Field `INT_EVENT0_IMASK_CTS` reader - Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] pub type INT_EVENT0_IMASK_CTS_R = crate :: BitReader < INT_EVENT0_IMASK_CTS_A > ; # [doc = "Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_CTS_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_CTS_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_CTS_SET = 1 , } impl From < INT_EVENT0_IMASK_CTS_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_CTS_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_CTS_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_CTS_A { match self . bits { false => INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_CLR , true => INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_cts_clr (& self) -> bool { * self == INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_cts_set (& self) -> bool { * self == INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_SET } } # [doc = "Field `INT_EVENT0_IMASK_CTS` writer - Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] pub type INT_EVENT0_IMASK_CTS_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_CTS_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_CTS_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_cts_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_cts_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DMA_DONE_RX` reader - Enable DMA Done on RX Event Channel"] pub type INT_EVENT0_IMASK_DMA_DONE_RX_R = crate :: BitReader < INT_EVENT0_IMASK_DMA_DONE_RX_A > ; # [doc = "Enable DMA Done on RX Event Channel\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DMA_DONE_RX_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DMA_DONE_RX_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DMA_DONE_RX_SET = 1 , } impl From < INT_EVENT0_IMASK_DMA_DONE_RX_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DMA_DONE_RX_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DMA_DONE_RX_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DMA_DONE_RX_A { match self . bits { false => INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_CLR , true => INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dma_done_rx_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dma_done_rx_set (& self) -> bool { * self == INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_SET } } # [doc = "Field `INT_EVENT0_IMASK_DMA_DONE_RX` writer - Enable DMA Done on RX Event Channel"] pub type INT_EVENT0_IMASK_DMA_DONE_RX_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DMA_DONE_RX_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DMA_DONE_RX_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dma_done_rx_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dma_done_rx_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DMA_DONE_TX` reader - Enable DMA Done on TX Event Channel"] pub type INT_EVENT0_IMASK_DMA_DONE_TX_R = crate :: BitReader < INT_EVENT0_IMASK_DMA_DONE_TX_A > ; # [doc = "Enable DMA Done on TX Event Channel\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DMA_DONE_TX_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DMA_DONE_TX_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DMA_DONE_TX_SET = 1 , } impl From < INT_EVENT0_IMASK_DMA_DONE_TX_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DMA_DONE_TX_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DMA_DONE_TX_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DMA_DONE_TX_A { match self . bits { false => INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_CLR , true => INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dma_done_tx_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dma_done_tx_set (& self) -> bool { * self == INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_SET } } # [doc = "Field `INT_EVENT0_IMASK_DMA_DONE_TX` writer - Enable DMA Done on TX Event Channel"] pub type INT_EVENT0_IMASK_DMA_DONE_TX_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DMA_DONE_TX_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DMA_DONE_TX_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dma_done_tx_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dma_done_tx_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_SET) } } # [doc = "Field `INT_EVENT0_IMASK_NERR` reader - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] pub type INT_EVENT0_IMASK_NERR_R = crate :: BitReader < INT_EVENT0_IMASK_NERR_A > ; # [doc = "Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_NERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_NERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_NERR_SET = 1 , } impl From < INT_EVENT0_IMASK_NERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_NERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_NERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_NERR_A { match self . bits { false => INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_CLR , true => INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_nerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_nerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_NERR` writer - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] pub type INT_EVENT0_IMASK_NERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_NERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_NERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_nerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_nerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_SET) } } impl R { # [doc = "Bit 0 - Enable UARTOUT Receive Time-Out Interrupt."] # [inline (always)] pub fn int_event0_imask_rtout (& self) -> INT_EVENT0_IMASK_RTOUT_R { INT_EVENT0_IMASK_RTOUT_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - Enable UART Framing Error Interrupt."] # [inline (always)] pub fn int_event0_imask_frmerr (& self) -> INT_EVENT0_IMASK_FRMERR_R { INT_EVENT0_IMASK_FRMERR_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - Enable UART Parity Error Interrupt."] # [inline (always)] pub fn int_event0_imask_parerr (& self) -> INT_EVENT0_IMASK_PARERR_R { INT_EVENT0_IMASK_PARERR_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - Enable UART Break Error Interrupt."] # [inline (always)] pub fn int_event0_imask_brkerr (& self) -> INT_EVENT0_IMASK_BRKERR_R { INT_EVENT0_IMASK_BRKERR_R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - Enable UART Receive Overrun Error Interrupt."] # [inline (always)] pub fn int_event0_imask_ovrerr (& self) -> INT_EVENT0_IMASK_OVRERR_R { INT_EVENT0_IMASK_OVRERR_R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - Enable Negative Edge on UARTxRXD Interrupt."] # [inline (always)] pub fn int_event0_imask_rxne (& self) -> INT_EVENT0_IMASK_RXNE_R { INT_EVENT0_IMASK_RXNE_R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - Enable Positive Edge on UARTxRXD Interrupt."] # [inline (always)] pub fn int_event0_imask_rxpe (& self) -> INT_EVENT0_IMASK_RXPE_R { INT_EVENT0_IMASK_RXPE_R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - Enable LIN Capture 0 / Match Interrupt ."] # [inline (always)] pub fn int_event0_imask_linc0 (& self) -> INT_EVENT0_IMASK_LINC0_R { INT_EVENT0_IMASK_LINC0_R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - Enable LIN Capture 1 Interrupt."] # [inline (always)] pub fn int_event0_imask_linc1 (& self) -> INT_EVENT0_IMASK_LINC1_R { INT_EVENT0_IMASK_LINC1_R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - Enable LIN Hardware Counter Overflow Interrupt."] # [inline (always)] pub fn int_event0_imask_linovf (& self) -> INT_EVENT0_IMASK_LINOVF_R { INT_EVENT0_IMASK_LINOVF_R :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - Enable UART Receive Interrupt."] # [inline (always)] pub fn int_event0_imask_rxint (& self) -> INT_EVENT0_IMASK_RXINT_R { INT_EVENT0_IMASK_RXINT_R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - Enable UART Transmit Interrupt."] # [inline (always)] pub fn int_event0_imask_txint (& self) -> INT_EVENT0_IMASK_TXINT_R { INT_EVENT0_IMASK_TXINT_R :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] # [inline (always)] pub fn int_event0_imask_eot (& self) -> INT_EVENT0_IMASK_EOT_R { INT_EVENT0_IMASK_EOT_R :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - Enable Address Match Interrupt."] # [inline (always)] pub fn int_event0_imask_addr_match (& self) -> INT_EVENT0_IMASK_ADDR_MATCH_R { INT_EVENT0_IMASK_ADDR_MATCH_R :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 14 - Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] # [inline (always)] pub fn int_event0_imask_cts (& self) -> INT_EVENT0_IMASK_CTS_R { INT_EVENT0_IMASK_CTS_R :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - Enable DMA Done on RX Event Channel"] # [inline (always)] pub fn int_event0_imask_dma_done_rx (& self) -> INT_EVENT0_IMASK_DMA_DONE_RX_R { INT_EVENT0_IMASK_DMA_DONE_RX_R :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bit 16 - Enable DMA Done on TX Event Channel"] # [inline (always)] pub fn int_event0_imask_dma_done_tx (& self) -> INT_EVENT0_IMASK_DMA_DONE_TX_R { INT_EVENT0_IMASK_DMA_DONE_TX_R :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] # [inline (always)] pub fn int_event0_imask_nerr (& self) -> INT_EVENT0_IMASK_NERR_R { INT_EVENT0_IMASK_NERR_R :: new (((self . bits >> 17) & 1) != 0) } } impl W { # [doc = "Bit 0 - Enable UARTOUT Receive Time-Out Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_rtout (& mut self) -> INT_EVENT0_IMASK_RTOUT_W < INT_EVENT0_IMASK_SPEC , 0 > { INT_EVENT0_IMASK_RTOUT_W :: new (self) } # [doc = "Bit 1 - Enable UART Framing Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_frmerr (& mut self) -> INT_EVENT0_IMASK_FRMERR_W <'_,  INT_EVENT0_IMASK_SPEC , 1 > { INT_EVENT0_IMASK_FRMERR_W :: new (self) } # [doc = "Bit 2 - Enable UART Parity Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_parerr (& mut self) -> INT_EVENT0_IMASK_PARERR_W < INT_EVENT0_IMASK_SPEC , 2 > { INT_EVENT0_IMASK_PARERR_W :: new (self) } # [doc = "Bit 3 - Enable UART Break Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_brkerr (& mut self) -> INT_EVENT0_IMASK_BRKERR_W < INT_EVENT0_IMASK_SPEC , 3 > { INT_EVENT0_IMASK_BRKERR_W :: new (self) } # [doc = "Bit 4 - Enable UART Receive Overrun Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_ovrerr (& mut self) -> INT_EVENT0_IMASK_OVRERR_W < INT_EVENT0_IMASK_SPEC , 4 > { INT_EVENT0_IMASK_OVRERR_W :: new (self) } # [doc = "Bit 5 - Enable Negative Edge on UARTxRXD Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_rxne (& mut self) -> INT_EVENT0_IMASK_RXNE_W < INT_EVENT0_IMASK_SPEC , 5 > { INT_EVENT0_IMASK_RXNE_W :: new (self) } # [doc = "Bit 6 - Enable Positive Edge on UARTxRXD Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_rxpe (& mut self) -> INT_EVENT0_IMASK_RXPE_W < INT_EVENT0_IMASK_SPEC , 6 > { INT_EVENT0_IMASK_RXPE_W :: new (self) } # [doc = "Bit 7 - Enable LIN Capture 0 / Match Interrupt ."] # [inline (always)] # [must_use] pub fn int_event0_imask_linc0 (& mut self) -> INT_EVENT0_IMASK_LINC0_W < INT_EVENT0_IMASK_SPEC , 7 > { INT_EVENT0_IMASK_LINC0_W :: new (self) } # [doc = "Bit 8 - Enable LIN Capture 1 Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_linc1 (& mut self) -> INT_EVENT0_IMASK_LINC1_W < INT_EVENT0_IMASK_SPEC , 8 > { INT_EVENT0_IMASK_LINC1_W :: new (self) } # [doc = "Bit 9 - Enable LIN Hardware Counter Overflow Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_linovf (& mut self) -> INT_EVENT0_IMASK_LINOVF_W < INT_EVENT0_IMASK_SPEC , 9 > { INT_EVENT0_IMASK_LINOVF_W :: new (self) } # [doc = "Bit 10 - Enable UART Receive Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_rxint (& mut self) -> INT_EVENT0_IMASK_RXINT_W < INT_EVENT0_IMASK_SPEC , 10 > { INT_EVENT0_IMASK_RXINT_W :: new (self) } # [doc = "Bit 11 - Enable UART Transmit Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_txint (& mut self) -> INT_EVENT0_IMASK_TXINT_W < INT_EVENT0_IMASK_SPEC , 11 > { INT_EVENT0_IMASK_TXINT_W :: new (self) } # [doc = "Bit 12 - Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] # [inline (always)] # [must_use] pub fn int_event0_imask_eot (& mut self) -> INT_EVENT0_IMASK_EOT_W < INT_EVENT0_IMASK_SPEC , 12 > { INT_EVENT0_IMASK_EOT_W :: new (self) } # [doc = "Bit 13 - Enable Address Match Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_addr_match (& mut self) -> INT_EVENT0_IMASK_ADDR_MATCH_W < INT_EVENT0_IMASK_SPEC , 13 > { INT_EVENT0_IMASK_ADDR_MATCH_W :: new (self) } # [doc = "Bit 14 - Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] # [inline (always)] # [must_use] pub fn int_event0_imask_cts (& mut self) -> INT_EVENT0_IMASK_CTS_W < INT_EVENT0_IMASK_SPEC , 14 > { INT_EVENT0_IMASK_CTS_W :: new (self) } # [doc = "Bit 15 - Enable DMA Done on RX Event Channel"] # [inline (always)] # [must_use] pub fn int_event0_imask_dma_done_rx (& mut self) -> INT_EVENT0_IMASK_DMA_DONE_RX_W < INT_EVENT0_IMASK_SPEC , 15 > { INT_EVENT0_IMASK_DMA_DONE_RX_W :: new (self) } # [doc = "Bit 16 - Enable DMA Done on TX Event Channel"] # [inline (always)] # [must_use] pub fn int_event0_imask_dma_done_tx (& mut self) -> INT_EVENT0_IMASK_DMA_DONE_TX_W < INT_EVENT0_IMASK_SPEC , 16 > { INT_EVENT0_IMASK_DMA_DONE_TX_W :: new (self) } # [doc = "Bit 17 - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] # [inline (always)] # [must_use] pub fn int_event0_imask_nerr (& mut self) -> INT_EVENT0_IMASK_NERR_W < INT_EVENT0_IMASK_SPEC , 17 > { INT_EVENT0_IMASK_NERR_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Interrupt mask\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_event0_imask::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_event0_imask::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct INT_EVENT0_IMASK_SPEC ; impl crate :: RegisterSpec for INT_EVENT0_IMASK_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`int_event0_imask::R`](R) reader structure"] impl crate :: Readable for INT_EVENT0_IMASK_SPEC { } # [doc = "`write(|w| ..)` method takes [`int_event0_imask::W`](W) writer structure"] impl crate :: Writable for INT_EVENT0_IMASK_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets INT_EVENT0_IMASK to value 0"] impl crate :: Resettable for INT_EVENT0_IMASK_SPEC { const RESET_VALUE : Self :: Ux = 0 ; }
[INFO] [stdout]   |                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                       +++
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing
[INFO] [stdout]  --> src/uart0/int_event0_iclr.rs:1:23992
[INFO] [stdout]   |
[INFO] [stdout] 1 | ...0_iclr_rxint (& mut self) -> INT_EVENT0_ICLR_RXINT_W < INT_EVENT0_ICLR_SPEC , 10 > { INT_EVENT0_ICLR_RXINT_W :: new (self) } # [do...
[INFO] [stdout]   |                  ^^^^^^^^^^     ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here
[INFO] [stdout]   |                  |
[INFO] [stdout]   |                  the lifetime is elided here
[INFO] [stdout]   |
[INFO] [stdout]   = help: the same lifetime is referred to in inconsistent ways, making the signature confusing
[INFO] [stdout] help: use `'_` for type paths
[INFO] [stdout]   |
[INFO] [stdout] 1 | # [doc = "Register `INT_EVENT0_ICLR` writer"] pub type W = crate :: W < INT_EVENT0_ICLR_SPEC > ; # [doc = "Clear UARTOUT Receive Time-Out Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_RTOUT_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_RTOUT_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_RTOUT_CLR = 1 , } impl From < INT_EVENT0_ICLR_RTOUT_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_RTOUT_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_RTOUT` writer - Clear UARTOUT Receive Time-Out Interrupt."] pub type INT_EVENT0_ICLR_RTOUT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_RTOUT_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_RTOUT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_rtout_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_RTOUT_AW :: INT_EVENT0_ICLR_RTOUT_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_rtout_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_RTOUT_AW :: INT_EVENT0_ICLR_RTOUT_CLR) } } # [doc = "Clear UART Framing Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_FRMERR_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_FRMERR_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_FRMERR_CLR = 1 , } impl From < INT_EVENT0_ICLR_FRMERR_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_FRMERR_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_FRMERR` writer - Clear UART Framing Error Interrupt."] pub type INT_EVENT0_ICLR_FRMERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_FRMERR_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_FRMERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_frmerr_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_FRMERR_AW :: INT_EVENT0_ICLR_FRMERR_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_frmerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_FRMERR_AW :: INT_EVENT0_ICLR_FRMERR_CLR) } } # [doc = "Clear UART Parity Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_PARERR_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_PARERR_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_PARERR_CLR = 1 , } impl From < INT_EVENT0_ICLR_PARERR_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_PARERR_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_PARERR` writer - Clear UART Parity Error Interrupt."] pub type INT_EVENT0_ICLR_PARERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_PARERR_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_PARERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_parerr_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_PARERR_AW :: INT_EVENT0_ICLR_PARERR_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_parerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_PARERR_AW :: INT_EVENT0_ICLR_PARERR_CLR) } } # [doc = "Clear UART Break Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_BRKERR_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_BRKERR_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_BRKERR_CLR = 1 , } impl From < INT_EVENT0_ICLR_BRKERR_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_BRKERR_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_BRKERR` writer - Clear UART Break Error Interrupt."] pub type INT_EVENT0_ICLR_BRKERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_BRKERR_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_BRKERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_brkerr_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_BRKERR_AW :: INT_EVENT0_ICLR_BRKERR_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_brkerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_BRKERR_AW :: INT_EVENT0_ICLR_BRKERR_CLR) } } # [doc = "Clear UART Receive Overrun Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_OVRERR_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_OVRERR_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_OVRERR_CLR = 1 , } impl From < INT_EVENT0_ICLR_OVRERR_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_OVRERR_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_OVRERR` writer - Clear UART Receive Overrun Error Interrupt."] pub type INT_EVENT0_ICLR_OVRERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_OVRERR_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_OVRERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_ovrerr_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_OVRERR_AW :: INT_EVENT0_ICLR_OVRERR_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_ovrerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_OVRERR_AW :: INT_EVENT0_ICLR_OVRERR_CLR) } } # [doc = "Clear Negative Edge on UARTxRXD Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_RXNE_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_RXNE_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_RXNE_CLR = 1 , } impl From < INT_EVENT0_ICLR_RXNE_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_RXNE_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_RXNE` writer - Clear Negative Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_ICLR_RXNE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_RXNE_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_RXNE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_rxne_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_RXNE_AW :: INT_EVENT0_ICLR_RXNE_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_rxne_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_RXNE_AW :: INT_EVENT0_ICLR_RXNE_CLR) } } # [doc = "Clear Positive Edge on UARTxRXD Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_RXPE_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_RXPE_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_RXPE_CLR = 1 , } impl From < INT_EVENT0_ICLR_RXPE_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_RXPE_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_RXPE` writer - Clear Positive Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_ICLR_RXPE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_RXPE_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_RXPE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_rxpe_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_RXPE_AW :: INT_EVENT0_ICLR_RXPE_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_rxpe_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_RXPE_AW :: INT_EVENT0_ICLR_RXPE_CLR) } } # [doc = "Clear LIN Capture 0 / Match Interrupt .\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_LINC0_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_LINC0_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_LINC0_CLR = 1 , } impl From < INT_EVENT0_ICLR_LINC0_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_LINC0_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_LINC0` writer - Clear LIN Capture 0 / Match Interrupt ."] pub type INT_EVENT0_ICLR_LINC0_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_LINC0_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_LINC0_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_linc0_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_LINC0_AW :: INT_EVENT0_ICLR_LINC0_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_linc0_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_LINC0_AW :: INT_EVENT0_ICLR_LINC0_CLR) } } # [doc = "Clear LIN Capture 1 Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_LINC1_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_LINC1_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_LINC1_CLR = 1 , } impl From < INT_EVENT0_ICLR_LINC1_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_LINC1_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_LINC1` writer - Clear LIN Capture 1 Interrupt."] pub type INT_EVENT0_ICLR_LINC1_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_LINC1_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_LINC1_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_linc1_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_LINC1_AW :: INT_EVENT0_ICLR_LINC1_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_linc1_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_LINC1_AW :: INT_EVENT0_ICLR_LINC1_CLR) } } # [doc = "Clear LIN Hardware Counter Overflow Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_LINOVF_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_LINOVF_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_LINOVF_CLR = 1 , } impl From < INT_EVENT0_ICLR_LINOVF_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_LINOVF_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_LINOVF` writer - Clear LIN Hardware Counter Overflow Interrupt."] pub type INT_EVENT0_ICLR_LINOVF_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_LINOVF_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_LINOVF_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_linovf_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_LINOVF_AW :: INT_EVENT0_ICLR_LINOVF_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_linovf_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_LINOVF_AW :: INT_EVENT0_ICLR_LINOVF_CLR) } } # [doc = "Clear UART Receive Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_RXINT_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_RXINT_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_RXINT_CLR = 1 , } impl From < INT_EVENT0_ICLR_RXINT_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_RXINT_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_RXINT` writer - Clear UART Receive Interrupt."] pub type INT_EVENT0_ICLR_RXINT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_RXINT_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_RXINT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_rxint_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_RXINT_AW :: INT_EVENT0_ICLR_RXINT_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_rxint_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_RXINT_AW :: INT_EVENT0_ICLR_RXINT_CLR) } } # [doc = "Clear UART Transmit Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_TXINT_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_TXINT_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_TXINT_CLR = 1 , } impl From < INT_EVENT0_ICLR_TXINT_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_TXINT_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_TXINT` writer - Clear UART Transmit Interrupt."] pub type INT_EVENT0_ICLR_TXINT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_TXINT_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_TXINT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_txint_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_TXINT_AW :: INT_EVENT0_ICLR_TXINT_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_txint_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_TXINT_AW :: INT_EVENT0_ICLR_TXINT_CLR) } } # [doc = "Clear UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_EOT_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_EOT_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_EOT_CLR = 1 , } impl From < INT_EVENT0_ICLR_EOT_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_EOT_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_EOT` writer - Clear UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] pub type INT_EVENT0_ICLR_EOT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_EOT_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_EOT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_eot_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_EOT_AW :: INT_EVENT0_ICLR_EOT_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_eot_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_EOT_AW :: INT_EVENT0_ICLR_EOT_CLR) } } # [doc = "Clear Address Match Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_ADDR_MATCH_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_ADDR_MATCH_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_ADDR_MATCH_CLR = 1 , } impl From < INT_EVENT0_ICLR_ADDR_MATCH_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_ADDR_MATCH_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_ADDR_MATCH` writer - Clear Address Match Interrupt."] pub type INT_EVENT0_ICLR_ADDR_MATCH_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_ADDR_MATCH_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_ADDR_MATCH_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_addr_match_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_ADDR_MATCH_AW :: INT_EVENT0_ICLR_ADDR_MATCH_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_addr_match_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_ADDR_MATCH_AW :: INT_EVENT0_ICLR_ADDR_MATCH_CLR) } } # [doc = "Clear UART Clear to Send Modem Interrupt. 0 = Interrupt disabled\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_CTS_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_CTS_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_CTS_CLR = 1 , } impl From < INT_EVENT0_ICLR_CTS_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_CTS_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_CTS` writer - Clear UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] pub type INT_EVENT0_ICLR_CTS_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_CTS_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_CTS_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_cts_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_CTS_AW :: INT_EVENT0_ICLR_CTS_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_cts_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_CTS_AW :: INT_EVENT0_ICLR_CTS_CLR) } } # [doc = "Clear DMA Done on RX Event Channel\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_DMA_DONE_RX_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_DMA_DONE_RX_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_DMA_DONE_RX_CLR = 1 , } impl From < INT_EVENT0_ICLR_DMA_DONE_RX_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_DMA_DONE_RX_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_DMA_DONE_RX` writer - Clear DMA Done on RX Event Channel"] pub type INT_EVENT0_ICLR_DMA_DONE_RX_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_DMA_DONE_RX_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_DMA_DONE_RX_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_dma_done_rx_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_DMA_DONE_RX_AW :: INT_EVENT0_ICLR_DMA_DONE_RX_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_dma_done_rx_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_DMA_DONE_RX_AW :: INT_EVENT0_ICLR_DMA_DONE_RX_CLR) } } # [doc = "Clear DMA Done on TX Event Channel\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_DMA_DONE_TX_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_DMA_DONE_TX_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_DMA_DONE_TX_CLR = 1 , } impl From < INT_EVENT0_ICLR_DMA_DONE_TX_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_DMA_DONE_TX_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_DMA_DONE_TX` writer - Clear DMA Done on TX Event Channel"] pub type INT_EVENT0_ICLR_DMA_DONE_TX_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_DMA_DONE_TX_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_DMA_DONE_TX_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_dma_done_tx_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_DMA_DONE_TX_AW :: INT_EVENT0_ICLR_DMA_DONE_TX_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_dma_done_tx_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_DMA_DONE_TX_AW :: INT_EVENT0_ICLR_DMA_DONE_TX_CLR) } } # [doc = "Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_NERR_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_NERR_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_NERR_CLR = 1 , } impl From < INT_EVENT0_ICLR_NERR_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_NERR_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_NERR` writer - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] pub type INT_EVENT0_ICLR_NERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_NERR_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_NERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_nerr_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_NERR_AW :: INT_EVENT0_ICLR_NERR_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_nerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_NERR_AW :: INT_EVENT0_ICLR_NERR_CLR) } } impl W { # [doc = "Bit 0 - Clear UARTOUT Receive Time-Out Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iclr_rtout (& mut self) -> INT_EVENT0_ICLR_RTOUT_W < INT_EVENT0_ICLR_SPEC , 0 > { INT_EVENT0_ICLR_RTOUT_W :: new (self) } # [doc = "Bit 1 - Clear UART Framing Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iclr_frmerr (& mut self) -> INT_EVENT0_ICLR_FRMERR_W < INT_EVENT0_ICLR_SPEC , 1 > { INT_EVENT0_ICLR_FRMERR_W :: new (self) } # [doc = "Bit 2 - Clear UART Parity Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iclr_parerr (& mut self) -> INT_EVENT0_ICLR_PARERR_W < INT_EVENT0_ICLR_SPEC , 2 > { INT_EVENT0_ICLR_PARERR_W :: new (self) } # [doc = "Bit 3 - Clear UART Break Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iclr_brkerr (& mut self) -> INT_EVENT0_ICLR_BRKERR_W < INT_EVENT0_ICLR_SPEC , 3 > { INT_EVENT0_ICLR_BRKERR_W :: new (self) } # [doc = "Bit 4 - Clear UART Receive Overrun Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iclr_ovrerr (& mut self) -> INT_EVENT0_ICLR_OVRERR_W < INT_EVENT0_ICLR_SPEC , 4 > { INT_EVENT0_ICLR_OVRERR_W :: new (self) } # [doc = "Bit 5 - Clear Negative Edge on UARTxRXD Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iclr_rxne (& mut self) -> INT_EVENT0_ICLR_RXNE_W < INT_EVENT0_ICLR_SPEC , 5 > { INT_EVENT0_ICLR_RXNE_W :: new (self) } # [doc = "Bit 6 - Clear Positive Edge on UARTxRXD Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iclr_rxpe (& mut self) -> INT_EVENT0_ICLR_RXPE_W < INT_EVENT0_ICLR_SPEC , 6 > { INT_EVENT0_ICLR_RXPE_W :: new (self) } # [doc = "Bit 7 - Clear LIN Capture 0 / Match Interrupt ."] # [inline (always)] # [must_use] pub fn int_event0_iclr_linc0 (& mut self) -> INT_EVENT0_ICLR_LINC0_W < INT_EVENT0_ICLR_SPEC , 7 > { INT_EVENT0_ICLR_LINC0_W :: new (self) } # [doc = "Bit 8 - Clear LIN Capture 1 Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iclr_linc1 (& mut self) -> INT_EVENT0_ICLR_LINC1_W < INT_EVENT0_ICLR_SPEC , 8 > { INT_EVENT0_ICLR_LINC1_W :: new (self) } # [doc = "Bit 9 - Clear LIN Hardware Counter Overflow Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iclr_linovf (& mut self) -> INT_EVENT0_ICLR_LINOVF_W < INT_EVENT0_ICLR_SPEC , 9 > { INT_EVENT0_ICLR_LINOVF_W :: new (self) } # [doc = "Bit 10 - Clear UART Receive Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iclr_rxint (& mut self) -> INT_EVENT0_ICLR_RXINT_W <'_,  INT_EVENT0_ICLR_SPEC , 10 > { INT_EVENT0_ICLR_RXINT_W :: new (self) } # [doc = "Bit 11 - Clear UART Transmit Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iclr_txint (& mut self) -> INT_EVENT0_ICLR_TXINT_W < INT_EVENT0_ICLR_SPEC , 11 > { INT_EVENT0_ICLR_TXINT_W :: new (self) } # [doc = "Bit 12 - Clear UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] # [inline (always)] # [must_use] pub fn int_event0_iclr_eot (& mut self) -> INT_EVENT0_ICLR_EOT_W < INT_EVENT0_ICLR_SPEC , 12 > { INT_EVENT0_ICLR_EOT_W :: new (self) } # [doc = "Bit 13 - Clear Address Match Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iclr_addr_match (& mut self) -> INT_EVENT0_ICLR_ADDR_MATCH_W < INT_EVENT0_ICLR_SPEC , 13 > { INT_EVENT0_ICLR_ADDR_MATCH_W :: new (self) } # [doc = "Bit 14 - Clear UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] # [inline (always)] # [must_use] pub fn int_event0_iclr_cts (& mut self) -> INT_EVENT0_ICLR_CTS_W < INT_EVENT0_ICLR_SPEC , 14 > { INT_EVENT0_ICLR_CTS_W :: new (self) } # [doc = "Bit 15 - Clear DMA Done on RX Event Channel"] # [inline (always)] # [must_use] pub fn int_event0_iclr_dma_done_rx (& mut self) -> INT_EVENT0_ICLR_DMA_DONE_RX_W < INT_EVENT0_ICLR_SPEC , 15 > { INT_EVENT0_ICLR_DMA_DONE_RX_W :: new (self) } # [doc = "Bit 16 - Clear DMA Done on TX Event Channel"] # [inline (always)] # [must_use] pub fn int_event0_iclr_dma_done_tx (& mut self) -> INT_EVENT0_ICLR_DMA_DONE_TX_W < INT_EVENT0_ICLR_SPEC , 16 > { INT_EVENT0_ICLR_DMA_DONE_TX_W :: new (self) } # [doc = "Bit 17 - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] # [inline (always)] # [must_use] pub fn int_event0_iclr_nerr (& mut self) -> INT_EVENT0_ICLR_NERR_W < INT_EVENT0_ICLR_SPEC , 17 > { INT_EVENT0_ICLR_NERR_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Interrupt clear\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_event0_iclr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct INT_EVENT0_ICLR_SPEC ; impl crate :: RegisterSpec for INT_EVENT0_ICLR_SPEC { type Ux = u32 ; } # [doc = "`write(|w| ..)` method takes [`int_event0_iclr::W`](W) writer structure"] impl crate :: Writable for INT_EVENT0_ICLR_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets INT_EVENT0_ICLR to value 0"] impl crate :: Resettable for INT_EVENT0_ICLR_SPEC { const RESET_VALUE : Self :: Ux = 0 ; }
[INFO] [stdout]   |                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                +++
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing
[INFO] [stdout]  --> src/uart0/int_event0_imask.rs:1:40969
[INFO] [stdout]   |
[INFO] [stdout] 1 | ...mask_parerr (& mut self) -> INT_EVENT0_IMASK_PARERR_W < INT_EVENT0_IMASK_SPEC , 2 > { INT_EVENT0_IMASK_PARERR_W :: new (self) } # ...
[INFO] [stdout]   |                 ^^^^^^^^^^     ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here
[INFO] [stdout]   |                 |
[INFO] [stdout]   |                 the lifetime is elided here
[INFO] [stdout]   |
[INFO] [stdout]   = help: the same lifetime is referred to in inconsistent ways, making the signature confusing
[INFO] [stdout] help: use `'_` for type paths
[INFO] [stdout]   |
[INFO] [stdout] 1 | # [doc = "Register `INT_EVENT0_IMASK` reader"] pub type R = crate :: R < INT_EVENT0_IMASK_SPEC > ; # [doc = "Register `INT_EVENT0_IMASK` writer"] pub type W = crate :: W < INT_EVENT0_IMASK_SPEC > ; # [doc = "Field `INT_EVENT0_IMASK_RTOUT` reader - Enable UARTOUT Receive Time-Out Interrupt."] pub type INT_EVENT0_IMASK_RTOUT_R = crate :: BitReader < INT_EVENT0_IMASK_RTOUT_A > ; # [doc = "Enable UARTOUT Receive Time-Out Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_RTOUT_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_RTOUT_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_RTOUT_SET = 1 , } impl From < INT_EVENT0_IMASK_RTOUT_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_RTOUT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_RTOUT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_RTOUT_A { match self . bits { false => INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_CLR , true => INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_rtout_clr (& self) -> bool { * self == INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_rtout_set (& self) -> bool { * self == INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_SET } } # [doc = "Field `INT_EVENT0_IMASK_RTOUT` writer - Enable UARTOUT Receive Time-Out Interrupt."] pub type INT_EVENT0_IMASK_RTOUT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_RTOUT_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_RTOUT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_rtout_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_rtout_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_SET) } } # [doc = "Field `INT_EVENT0_IMASK_FRMERR` reader - Enable UART Framing Error Interrupt."] pub type INT_EVENT0_IMASK_FRMERR_R = crate :: BitReader < INT_EVENT0_IMASK_FRMERR_A > ; # [doc = "Enable UART Framing Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_FRMERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_FRMERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_FRMERR_SET = 1 , } impl From < INT_EVENT0_IMASK_FRMERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_FRMERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_FRMERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_FRMERR_A { match self . bits { false => INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_CLR , true => INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_frmerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_frmerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_FRMERR` writer - Enable UART Framing Error Interrupt."] pub type INT_EVENT0_IMASK_FRMERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_FRMERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_FRMERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_frmerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_frmerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_SET) } } # [doc = "Field `INT_EVENT0_IMASK_PARERR` reader - Enable UART Parity Error Interrupt."] pub type INT_EVENT0_IMASK_PARERR_R = crate :: BitReader < INT_EVENT0_IMASK_PARERR_A > ; # [doc = "Enable UART Parity Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_PARERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_PARERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_PARERR_SET = 1 , } impl From < INT_EVENT0_IMASK_PARERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_PARERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_PARERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_PARERR_A { match self . bits { false => INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_CLR , true => INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_parerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_parerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_PARERR` writer - Enable UART Parity Error Interrupt."] pub type INT_EVENT0_IMASK_PARERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_PARERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_PARERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_parerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_parerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_SET) } } # [doc = "Field `INT_EVENT0_IMASK_BRKERR` reader - Enable UART Break Error Interrupt."] pub type INT_EVENT0_IMASK_BRKERR_R = crate :: BitReader < INT_EVENT0_IMASK_BRKERR_A > ; # [doc = "Enable UART Break Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_BRKERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_BRKERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_BRKERR_SET = 1 , } impl From < INT_EVENT0_IMASK_BRKERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_BRKERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_BRKERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_BRKERR_A { match self . bits { false => INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_CLR , true => INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_brkerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_brkerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_BRKERR` writer - Enable UART Break Error Interrupt."] pub type INT_EVENT0_IMASK_BRKERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_BRKERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_BRKERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_brkerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_brkerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_SET) } } # [doc = "Field `INT_EVENT0_IMASK_OVRERR` reader - Enable UART Receive Overrun Error Interrupt."] pub type INT_EVENT0_IMASK_OVRERR_R = crate :: BitReader < INT_EVENT0_IMASK_OVRERR_A > ; # [doc = "Enable UART Receive Overrun Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_OVRERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_OVRERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_OVRERR_SET = 1 , } impl From < INT_EVENT0_IMASK_OVRERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_OVRERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_OVRERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_OVRERR_A { match self . bits { false => INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_CLR , true => INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_ovrerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_ovrerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_OVRERR` writer - Enable UART Receive Overrun Error Interrupt."] pub type INT_EVENT0_IMASK_OVRERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_OVRERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_OVRERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_ovrerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_ovrerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_SET) } } # [doc = "Field `INT_EVENT0_IMASK_RXNE` reader - Enable Negative Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_IMASK_RXNE_R = crate :: BitReader < INT_EVENT0_IMASK_RXNE_A > ; # [doc = "Enable Negative Edge on UARTxRXD Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_RXNE_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_RXNE_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_RXNE_SET = 1 , } impl From < INT_EVENT0_IMASK_RXNE_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_RXNE_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_RXNE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_RXNE_A { match self . bits { false => INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_CLR , true => INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_rxne_clr (& self) -> bool { * self == INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_rxne_set (& self) -> bool { * self == INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_SET } } # [doc = "Field `INT_EVENT0_IMASK_RXNE` writer - Enable Negative Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_IMASK_RXNE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_RXNE_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_RXNE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_rxne_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_rxne_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_SET) } } # [doc = "Field `INT_EVENT0_IMASK_RXPE` reader - Enable Positive Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_IMASK_RXPE_R = crate :: BitReader < INT_EVENT0_IMASK_RXPE_A > ; # [doc = "Enable Positive Edge on UARTxRXD Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_RXPE_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_RXPE_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_RXPE_SET = 1 , } impl From < INT_EVENT0_IMASK_RXPE_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_RXPE_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_RXPE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_RXPE_A { match self . bits { false => INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_CLR , true => INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_rxpe_clr (& self) -> bool { * self == INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_rxpe_set (& self) -> bool { * self == INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_SET } } # [doc = "Field `INT_EVENT0_IMASK_RXPE` writer - Enable Positive Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_IMASK_RXPE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_RXPE_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_RXPE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_rxpe_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_rxpe_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_SET) } } # [doc = "Field `INT_EVENT0_IMASK_LINC0` reader - Enable LIN Capture 0 / Match Interrupt ."] pub type INT_EVENT0_IMASK_LINC0_R = crate :: BitReader < INT_EVENT0_IMASK_LINC0_A > ; # [doc = "Enable LIN Capture 0 / Match Interrupt .\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_LINC0_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_LINC0_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_LINC0_SET = 1 , } impl From < INT_EVENT0_IMASK_LINC0_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_LINC0_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_LINC0_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_LINC0_A { match self . bits { false => INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_CLR , true => INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_linc0_clr (& self) -> bool { * self == INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_linc0_set (& self) -> bool { * self == INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_SET } } # [doc = "Field `INT_EVENT0_IMASK_LINC0` writer - Enable LIN Capture 0 / Match Interrupt ."] pub type INT_EVENT0_IMASK_LINC0_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_LINC0_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_LINC0_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_linc0_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_linc0_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_SET) } } # [doc = "Field `INT_EVENT0_IMASK_LINC1` reader - Enable LIN Capture 1 Interrupt."] pub type INT_EVENT0_IMASK_LINC1_R = crate :: BitReader < INT_EVENT0_IMASK_LINC1_A > ; # [doc = "Enable LIN Capture 1 Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_LINC1_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_LINC1_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_LINC1_SET = 1 , } impl From < INT_EVENT0_IMASK_LINC1_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_LINC1_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_LINC1_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_LINC1_A { match self . bits { false => INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_CLR , true => INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_linc1_clr (& self) -> bool { * self == INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_linc1_set (& self) -> bool { * self == INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_SET } } # [doc = "Field `INT_EVENT0_IMASK_LINC1` writer - Enable LIN Capture 1 Interrupt."] pub type INT_EVENT0_IMASK_LINC1_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_LINC1_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_LINC1_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_linc1_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_linc1_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_SET) } } # [doc = "Field `INT_EVENT0_IMASK_LINOVF` reader - Enable LIN Hardware Counter Overflow Interrupt."] pub type INT_EVENT0_IMASK_LINOVF_R = crate :: BitReader < INT_EVENT0_IMASK_LINOVF_A > ; # [doc = "Enable LIN Hardware Counter Overflow Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_LINOVF_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_LINOVF_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_LINOVF_SET = 1 , } impl From < INT_EVENT0_IMASK_LINOVF_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_LINOVF_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_LINOVF_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_LINOVF_A { match self . bits { false => INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_CLR , true => INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_linovf_clr (& self) -> bool { * self == INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_linovf_set (& self) -> bool { * self == INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_SET } } # [doc = "Field `INT_EVENT0_IMASK_LINOVF` writer - Enable LIN Hardware Counter Overflow Interrupt."] pub type INT_EVENT0_IMASK_LINOVF_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_LINOVF_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_LINOVF_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_linovf_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_linovf_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_SET) } } # [doc = "Field `INT_EVENT0_IMASK_RXINT` reader - Enable UART Receive Interrupt."] pub type INT_EVENT0_IMASK_RXINT_R = crate :: BitReader < INT_EVENT0_IMASK_RXINT_A > ; # [doc = "Enable UART Receive Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_RXINT_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_RXINT_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_RXINT_SET = 1 , } impl From < INT_EVENT0_IMASK_RXINT_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_RXINT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_RXINT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_RXINT_A { match self . bits { false => INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_CLR , true => INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_rxint_clr (& self) -> bool { * self == INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_rxint_set (& self) -> bool { * self == INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_SET } } # [doc = "Field `INT_EVENT0_IMASK_RXINT` writer - Enable UART Receive Interrupt."] pub type INT_EVENT0_IMASK_RXINT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_RXINT_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_RXINT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_rxint_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_rxint_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_SET) } } # [doc = "Field `INT_EVENT0_IMASK_TXINT` reader - Enable UART Transmit Interrupt."] pub type INT_EVENT0_IMASK_TXINT_R = crate :: BitReader < INT_EVENT0_IMASK_TXINT_A > ; # [doc = "Enable UART Transmit Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_TXINT_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_TXINT_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_TXINT_SET = 1 , } impl From < INT_EVENT0_IMASK_TXINT_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_TXINT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_TXINT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_TXINT_A { match self . bits { false => INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_CLR , true => INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_txint_clr (& self) -> bool { * self == INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_txint_set (& self) -> bool { * self == INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_SET } } # [doc = "Field `INT_EVENT0_IMASK_TXINT` writer - Enable UART Transmit Interrupt."] pub type INT_EVENT0_IMASK_TXINT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_TXINT_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_TXINT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_txint_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_txint_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_SET) } } # [doc = "Field `INT_EVENT0_IMASK_EOT` reader - Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] pub type INT_EVENT0_IMASK_EOT_R = crate :: BitReader < INT_EVENT0_IMASK_EOT_A > ; # [doc = "Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_EOT_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_EOT_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_EOT_SET = 1 , } impl From < INT_EVENT0_IMASK_EOT_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_EOT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_EOT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_EOT_A { match self . bits { false => INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_CLR , true => INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_eot_clr (& self) -> bool { * self == INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_eot_set (& self) -> bool { * self == INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_SET } } # [doc = "Field `INT_EVENT0_IMASK_EOT` writer - Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] pub type INT_EVENT0_IMASK_EOT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_EOT_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_EOT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_eot_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_eot_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_SET) } } # [doc = "Field `INT_EVENT0_IMASK_ADDR_MATCH` reader - Enable Address Match Interrupt."] pub type INT_EVENT0_IMASK_ADDR_MATCH_R = crate :: BitReader < INT_EVENT0_IMASK_ADDR_MATCH_A > ; # [doc = "Enable Address Match Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_ADDR_MATCH_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_ADDR_MATCH_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_ADDR_MATCH_SET = 1 , } impl From < INT_EVENT0_IMASK_ADDR_MATCH_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_ADDR_MATCH_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_ADDR_MATCH_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_ADDR_MATCH_A { match self . bits { false => INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_CLR , true => INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_addr_match_clr (& self) -> bool { * self == INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_addr_match_set (& self) -> bool { * self == INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_SET } } # [doc = "Field `INT_EVENT0_IMASK_ADDR_MATCH` writer - Enable Address Match Interrupt."] pub type INT_EVENT0_IMASK_ADDR_MATCH_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_ADDR_MATCH_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_ADDR_MATCH_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_addr_match_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_addr_match_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_SET) } } # [doc = "Field `INT_EVENT0_IMASK_CTS` reader - Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] pub type INT_EVENT0_IMASK_CTS_R = crate :: BitReader < INT_EVENT0_IMASK_CTS_A > ; # [doc = "Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_CTS_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_CTS_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_CTS_SET = 1 , } impl From < INT_EVENT0_IMASK_CTS_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_CTS_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_CTS_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_CTS_A { match self . bits { false => INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_CLR , true => INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_cts_clr (& self) -> bool { * self == INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_cts_set (& self) -> bool { * self == INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_SET } } # [doc = "Field `INT_EVENT0_IMASK_CTS` writer - Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] pub type INT_EVENT0_IMASK_CTS_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_CTS_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_CTS_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_cts_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_cts_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DMA_DONE_RX` reader - Enable DMA Done on RX Event Channel"] pub type INT_EVENT0_IMASK_DMA_DONE_RX_R = crate :: BitReader < INT_EVENT0_IMASK_DMA_DONE_RX_A > ; # [doc = "Enable DMA Done on RX Event Channel\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DMA_DONE_RX_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DMA_DONE_RX_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DMA_DONE_RX_SET = 1 , } impl From < INT_EVENT0_IMASK_DMA_DONE_RX_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DMA_DONE_RX_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DMA_DONE_RX_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DMA_DONE_RX_A { match self . bits { false => INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_CLR , true => INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dma_done_rx_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dma_done_rx_set (& self) -> bool { * self == INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_SET } } # [doc = "Field `INT_EVENT0_IMASK_DMA_DONE_RX` writer - Enable DMA Done on RX Event Channel"] pub type INT_EVENT0_IMASK_DMA_DONE_RX_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DMA_DONE_RX_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DMA_DONE_RX_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dma_done_rx_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dma_done_rx_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DMA_DONE_TX` reader - Enable DMA Done on TX Event Channel"] pub type INT_EVENT0_IMASK_DMA_DONE_TX_R = crate :: BitReader < INT_EVENT0_IMASK_DMA_DONE_TX_A > ; # [doc = "Enable DMA Done on TX Event Channel\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DMA_DONE_TX_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DMA_DONE_TX_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DMA_DONE_TX_SET = 1 , } impl From < INT_EVENT0_IMASK_DMA_DONE_TX_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DMA_DONE_TX_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DMA_DONE_TX_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DMA_DONE_TX_A { match self . bits { false => INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_CLR , true => INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dma_done_tx_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dma_done_tx_set (& self) -> bool { * self == INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_SET } } # [doc = "Field `INT_EVENT0_IMASK_DMA_DONE_TX` writer - Enable DMA Done on TX Event Channel"] pub type INT_EVENT0_IMASK_DMA_DONE_TX_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DMA_DONE_TX_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DMA_DONE_TX_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dma_done_tx_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dma_done_tx_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_SET) } } # [doc = "Field `INT_EVENT0_IMASK_NERR` reader - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] pub type INT_EVENT0_IMASK_NERR_R = crate :: BitReader < INT_EVENT0_IMASK_NERR_A > ; # [doc = "Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_NERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_NERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_NERR_SET = 1 , } impl From < INT_EVENT0_IMASK_NERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_NERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_NERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_NERR_A { match self . bits { false => INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_CLR , true => INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_nerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_nerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_NERR` writer - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] pub type INT_EVENT0_IMASK_NERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_NERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_NERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_nerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_nerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_SET) } } impl R { # [doc = "Bit 0 - Enable UARTOUT Receive Time-Out Interrupt."] # [inline (always)] pub fn int_event0_imask_rtout (& self) -> INT_EVENT0_IMASK_RTOUT_R { INT_EVENT0_IMASK_RTOUT_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - Enable UART Framing Error Interrupt."] # [inline (always)] pub fn int_event0_imask_frmerr (& self) -> INT_EVENT0_IMASK_FRMERR_R { INT_EVENT0_IMASK_FRMERR_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - Enable UART Parity Error Interrupt."] # [inline (always)] pub fn int_event0_imask_parerr (& self) -> INT_EVENT0_IMASK_PARERR_R { INT_EVENT0_IMASK_PARERR_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - Enable UART Break Error Interrupt."] # [inline (always)] pub fn int_event0_imask_brkerr (& self) -> INT_EVENT0_IMASK_BRKERR_R { INT_EVENT0_IMASK_BRKERR_R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - Enable UART Receive Overrun Error Interrupt."] # [inline (always)] pub fn int_event0_imask_ovrerr (& self) -> INT_EVENT0_IMASK_OVRERR_R { INT_EVENT0_IMASK_OVRERR_R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - Enable Negative Edge on UARTxRXD Interrupt."] # [inline (always)] pub fn int_event0_imask_rxne (& self) -> INT_EVENT0_IMASK_RXNE_R { INT_EVENT0_IMASK_RXNE_R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - Enable Positive Edge on UARTxRXD Interrupt."] # [inline (always)] pub fn int_event0_imask_rxpe (& self) -> INT_EVENT0_IMASK_RXPE_R { INT_EVENT0_IMASK_RXPE_R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - Enable LIN Capture 0 / Match Interrupt ."] # [inline (always)] pub fn int_event0_imask_linc0 (& self) -> INT_EVENT0_IMASK_LINC0_R { INT_EVENT0_IMASK_LINC0_R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - Enable LIN Capture 1 Interrupt."] # [inline (always)] pub fn int_event0_imask_linc1 (& self) -> INT_EVENT0_IMASK_LINC1_R { INT_EVENT0_IMASK_LINC1_R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - Enable LIN Hardware Counter Overflow Interrupt."] # [inline (always)] pub fn int_event0_imask_linovf (& self) -> INT_EVENT0_IMASK_LINOVF_R { INT_EVENT0_IMASK_LINOVF_R :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - Enable UART Receive Interrupt."] # [inline (always)] pub fn int_event0_imask_rxint (& self) -> INT_EVENT0_IMASK_RXINT_R { INT_EVENT0_IMASK_RXINT_R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - Enable UART Transmit Interrupt."] # [inline (always)] pub fn int_event0_imask_txint (& self) -> INT_EVENT0_IMASK_TXINT_R { INT_EVENT0_IMASK_TXINT_R :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] # [inline (always)] pub fn int_event0_imask_eot (& self) -> INT_EVENT0_IMASK_EOT_R { INT_EVENT0_IMASK_EOT_R :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - Enable Address Match Interrupt."] # [inline (always)] pub fn int_event0_imask_addr_match (& self) -> INT_EVENT0_IMASK_ADDR_MATCH_R { INT_EVENT0_IMASK_ADDR_MATCH_R :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 14 - Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] # [inline (always)] pub fn int_event0_imask_cts (& self) -> INT_EVENT0_IMASK_CTS_R { INT_EVENT0_IMASK_CTS_R :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - Enable DMA Done on RX Event Channel"] # [inline (always)] pub fn int_event0_imask_dma_done_rx (& self) -> INT_EVENT0_IMASK_DMA_DONE_RX_R { INT_EVENT0_IMASK_DMA_DONE_RX_R :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bit 16 - Enable DMA Done on TX Event Channel"] # [inline (always)] pub fn int_event0_imask_dma_done_tx (& self) -> INT_EVENT0_IMASK_DMA_DONE_TX_R { INT_EVENT0_IMASK_DMA_DONE_TX_R :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] # [inline (always)] pub fn int_event0_imask_nerr (& self) -> INT_EVENT0_IMASK_NERR_R { INT_EVENT0_IMASK_NERR_R :: new (((self . bits >> 17) & 1) != 0) } } impl W { # [doc = "Bit 0 - Enable UARTOUT Receive Time-Out Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_rtout (& mut self) -> INT_EVENT0_IMASK_RTOUT_W < INT_EVENT0_IMASK_SPEC , 0 > { INT_EVENT0_IMASK_RTOUT_W :: new (self) } # [doc = "Bit 1 - Enable UART Framing Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_frmerr (& mut self) -> INT_EVENT0_IMASK_FRMERR_W < INT_EVENT0_IMASK_SPEC , 1 > { INT_EVENT0_IMASK_FRMERR_W :: new (self) } # [doc = "Bit 2 - Enable UART Parity Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_parerr (& mut self) -> INT_EVENT0_IMASK_PARERR_W <'_,  INT_EVENT0_IMASK_SPEC , 2 > { INT_EVENT0_IMASK_PARERR_W :: new (self) } # [doc = "Bit 3 - Enable UART Break Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_brkerr (& mut self) -> INT_EVENT0_IMASK_BRKERR_W < INT_EVENT0_IMASK_SPEC , 3 > { INT_EVENT0_IMASK_BRKERR_W :: new (self) } # [doc = "Bit 4 - Enable UART Receive Overrun Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_ovrerr (& mut self) -> INT_EVENT0_IMASK_OVRERR_W < INT_EVENT0_IMASK_SPEC , 4 > { INT_EVENT0_IMASK_OVRERR_W :: new (self) } # [doc = "Bit 5 - Enable Negative Edge on UARTxRXD Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_rxne (& mut self) -> INT_EVENT0_IMASK_RXNE_W < INT_EVENT0_IMASK_SPEC , 5 > { INT_EVENT0_IMASK_RXNE_W :: new (self) } # [doc = "Bit 6 - Enable Positive Edge on UARTxRXD Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_rxpe (& mut self) -> INT_EVENT0_IMASK_RXPE_W < INT_EVENT0_IMASK_SPEC , 6 > { INT_EVENT0_IMASK_RXPE_W :: new (self) } # [doc = "Bit 7 - Enable LIN Capture 0 / Match Interrupt ."] # [inline (always)] # [must_use] pub fn int_event0_imask_linc0 (& mut self) -> INT_EVENT0_IMASK_LINC0_W < INT_EVENT0_IMASK_SPEC , 7 > { INT_EVENT0_IMASK_LINC0_W :: new (self) } # [doc = "Bit 8 - Enable LIN Capture 1 Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_linc1 (& mut self) -> INT_EVENT0_IMASK_LINC1_W < INT_EVENT0_IMASK_SPEC , 8 > { INT_EVENT0_IMASK_LINC1_W :: new (self) } # [doc = "Bit 9 - Enable LIN Hardware Counter Overflow Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_linovf (& mut self) -> INT_EVENT0_IMASK_LINOVF_W < INT_EVENT0_IMASK_SPEC , 9 > { INT_EVENT0_IMASK_LINOVF_W :: new (self) } # [doc = "Bit 10 - Enable UART Receive Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_rxint (& mut self) -> INT_EVENT0_IMASK_RXINT_W < INT_EVENT0_IMASK_SPEC , 10 > { INT_EVENT0_IMASK_RXINT_W :: new (self) } # [doc = "Bit 11 - Enable UART Transmit Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_txint (& mut self) -> INT_EVENT0_IMASK_TXINT_W < INT_EVENT0_IMASK_SPEC , 11 > { INT_EVENT0_IMASK_TXINT_W :: new (self) } # [doc = "Bit 12 - Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] # [inline (always)] # [must_use] pub fn int_event0_imask_eot (& mut self) -> INT_EVENT0_IMASK_EOT_W < INT_EVENT0_IMASK_SPEC , 12 > { INT_EVENT0_IMASK_EOT_W :: new (self) } # [doc = "Bit 13 - Enable Address Match Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_addr_match (& mut self) -> INT_EVENT0_IMASK_ADDR_MATCH_W < INT_EVENT0_IMASK_SPEC , 13 > { INT_EVENT0_IMASK_ADDR_MATCH_W :: new (self) } # [doc = "Bit 14 - Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] # [inline (always)] # [must_use] pub fn int_event0_imask_cts (& mut self) -> INT_EVENT0_IMASK_CTS_W < INT_EVENT0_IMASK_SPEC , 14 > { INT_EVENT0_IMASK_CTS_W :: new (self) } # [doc = "Bit 15 - Enable DMA Done on RX Event Channel"] # [inline (always)] # [must_use] pub fn int_event0_imask_dma_done_rx (& mut self) -> INT_EVENT0_IMASK_DMA_DONE_RX_W < INT_EVENT0_IMASK_SPEC , 15 > { INT_EVENT0_IMASK_DMA_DONE_RX_W :: new (self) } # [doc = "Bit 16 - Enable DMA Done on TX Event Channel"] # [inline (always)] # [must_use] pub fn int_event0_imask_dma_done_tx (& mut self) -> INT_EVENT0_IMASK_DMA_DONE_TX_W < INT_EVENT0_IMASK_SPEC , 16 > { INT_EVENT0_IMASK_DMA_DONE_TX_W :: new (self) } # [doc = "Bit 17 - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] # [inline (always)] # [must_use] pub fn int_event0_imask_nerr (& mut self) -> INT_EVENT0_IMASK_NERR_W < INT_EVENT0_IMASK_SPEC , 17 > { INT_EVENT0_IMASK_NERR_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Interrupt mask\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_event0_imask::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_event0_imask::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct INT_EVENT0_IMASK_SPEC ; impl crate :: RegisterSpec for INT_EVENT0_IMASK_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`int_event0_imask::R`](R) reader structure"] impl crate :: Readable for INT_EVENT0_IMASK_SPEC { } # [doc = "`write(|w| ..)` method takes [`int_event0_imask::W`](W) writer structure"] impl crate :: Writable for INT_EVENT0_IMASK_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets INT_EVENT0_IMASK to value 0"] impl crate :: Resettable for INT_EVENT0_IMASK_SPEC { const RESET_VALUE : Self :: Ux = 0 ; }
[INFO] [stdout]   |                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                   +++
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing
[INFO] [stdout]  --> src/uart0/int_event0_iclr.rs:1:24218
[INFO] [stdout]   |
[INFO] [stdout] 1 | ...0_iclr_txint (& mut self) -> INT_EVENT0_ICLR_TXINT_W < INT_EVENT0_ICLR_SPEC , 11 > { INT_EVENT0_ICLR_TXINT_W :: new (self) } # [do...
[INFO] [stdout]   |                  ^^^^^^^^^^     ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here
[INFO] [stdout]   |                  |
[INFO] [stdout]   |                  the lifetime is elided here
[INFO] [stdout]   |
[INFO] [stdout]   = help: the same lifetime is referred to in inconsistent ways, making the signature confusing
[INFO] [stdout] help: use `'_` for type paths
[INFO] [stdout]   |
[INFO] [stdout] 1 | # [doc = "Register `INT_EVENT0_ICLR` writer"] pub type W = crate :: W < INT_EVENT0_ICLR_SPEC > ; # [doc = "Clear UARTOUT Receive Time-Out Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_RTOUT_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_RTOUT_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_RTOUT_CLR = 1 , } impl From < INT_EVENT0_ICLR_RTOUT_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_RTOUT_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_RTOUT` writer - Clear UARTOUT Receive Time-Out Interrupt."] pub type INT_EVENT0_ICLR_RTOUT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_RTOUT_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_RTOUT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_rtout_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_RTOUT_AW :: INT_EVENT0_ICLR_RTOUT_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_rtout_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_RTOUT_AW :: INT_EVENT0_ICLR_RTOUT_CLR) } } # [doc = "Clear UART Framing Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_FRMERR_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_FRMERR_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_FRMERR_CLR = 1 , } impl From < INT_EVENT0_ICLR_FRMERR_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_FRMERR_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_FRMERR` writer - Clear UART Framing Error Interrupt."] pub type INT_EVENT0_ICLR_FRMERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_FRMERR_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_FRMERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_frmerr_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_FRMERR_AW :: INT_EVENT0_ICLR_FRMERR_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_frmerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_FRMERR_AW :: INT_EVENT0_ICLR_FRMERR_CLR) } } # [doc = "Clear UART Parity Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_PARERR_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_PARERR_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_PARERR_CLR = 1 , } impl From < INT_EVENT0_ICLR_PARERR_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_PARERR_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_PARERR` writer - Clear UART Parity Error Interrupt."] pub type INT_EVENT0_ICLR_PARERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_PARERR_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_PARERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_parerr_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_PARERR_AW :: INT_EVENT0_ICLR_PARERR_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_parerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_PARERR_AW :: INT_EVENT0_ICLR_PARERR_CLR) } } # [doc = "Clear UART Break Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_BRKERR_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_BRKERR_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_BRKERR_CLR = 1 , } impl From < INT_EVENT0_ICLR_BRKERR_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_BRKERR_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_BRKERR` writer - Clear UART Break Error Interrupt."] pub type INT_EVENT0_ICLR_BRKERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_BRKERR_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_BRKERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_brkerr_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_BRKERR_AW :: INT_EVENT0_ICLR_BRKERR_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_brkerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_BRKERR_AW :: INT_EVENT0_ICLR_BRKERR_CLR) } } # [doc = "Clear UART Receive Overrun Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_OVRERR_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_OVRERR_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_OVRERR_CLR = 1 , } impl From < INT_EVENT0_ICLR_OVRERR_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_OVRERR_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_OVRERR` writer - Clear UART Receive Overrun Error Interrupt."] pub type INT_EVENT0_ICLR_OVRERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_OVRERR_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_OVRERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_ovrerr_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_OVRERR_AW :: INT_EVENT0_ICLR_OVRERR_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_ovrerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_OVRERR_AW :: INT_EVENT0_ICLR_OVRERR_CLR) } } # [doc = "Clear Negative Edge on UARTxRXD Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_RXNE_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_RXNE_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_RXNE_CLR = 1 , } impl From < INT_EVENT0_ICLR_RXNE_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_RXNE_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_RXNE` writer - Clear Negative Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_ICLR_RXNE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_RXNE_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_RXNE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_rxne_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_RXNE_AW :: INT_EVENT0_ICLR_RXNE_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_rxne_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_RXNE_AW :: INT_EVENT0_ICLR_RXNE_CLR) } } # [doc = "Clear Positive Edge on UARTxRXD Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_RXPE_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_RXPE_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_RXPE_CLR = 1 , } impl From < INT_EVENT0_ICLR_RXPE_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_RXPE_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_RXPE` writer - Clear Positive Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_ICLR_RXPE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_RXPE_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_RXPE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_rxpe_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_RXPE_AW :: INT_EVENT0_ICLR_RXPE_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_rxpe_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_RXPE_AW :: INT_EVENT0_ICLR_RXPE_CLR) } } # [doc = "Clear LIN Capture 0 / Match Interrupt .\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_LINC0_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_LINC0_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_LINC0_CLR = 1 , } impl From < INT_EVENT0_ICLR_LINC0_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_LINC0_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_LINC0` writer - Clear LIN Capture 0 / Match Interrupt ."] pub type INT_EVENT0_ICLR_LINC0_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_LINC0_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_LINC0_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_linc0_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_LINC0_AW :: INT_EVENT0_ICLR_LINC0_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_linc0_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_LINC0_AW :: INT_EVENT0_ICLR_LINC0_CLR) } } # [doc = "Clear LIN Capture 1 Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_LINC1_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_LINC1_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_LINC1_CLR = 1 , } impl From < INT_EVENT0_ICLR_LINC1_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_LINC1_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_LINC1` writer - Clear LIN Capture 1 Interrupt."] pub type INT_EVENT0_ICLR_LINC1_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_LINC1_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_LINC1_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_linc1_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_LINC1_AW :: INT_EVENT0_ICLR_LINC1_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_linc1_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_LINC1_AW :: INT_EVENT0_ICLR_LINC1_CLR) } } # [doc = "Clear LIN Hardware Counter Overflow Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_LINOVF_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_LINOVF_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_LINOVF_CLR = 1 , } impl From < INT_EVENT0_ICLR_LINOVF_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_LINOVF_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_LINOVF` writer - Clear LIN Hardware Counter Overflow Interrupt."] pub type INT_EVENT0_ICLR_LINOVF_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_LINOVF_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_LINOVF_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_linovf_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_LINOVF_AW :: INT_EVENT0_ICLR_LINOVF_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_linovf_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_LINOVF_AW :: INT_EVENT0_ICLR_LINOVF_CLR) } } # [doc = "Clear UART Receive Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_RXINT_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_RXINT_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_RXINT_CLR = 1 , } impl From < INT_EVENT0_ICLR_RXINT_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_RXINT_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_RXINT` writer - Clear UART Receive Interrupt."] pub type INT_EVENT0_ICLR_RXINT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_RXINT_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_RXINT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_rxint_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_RXINT_AW :: INT_EVENT0_ICLR_RXINT_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_rxint_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_RXINT_AW :: INT_EVENT0_ICLR_RXINT_CLR) } } # [doc = "Clear UART Transmit Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_TXINT_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_TXINT_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_TXINT_CLR = 1 , } impl From < INT_EVENT0_ICLR_TXINT_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_TXINT_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_TXINT` writer - Clear UART Transmit Interrupt."] pub type INT_EVENT0_ICLR_TXINT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_TXINT_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_TXINT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_txint_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_TXINT_AW :: INT_EVENT0_ICLR_TXINT_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_txint_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_TXINT_AW :: INT_EVENT0_ICLR_TXINT_CLR) } } # [doc = "Clear UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_EOT_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_EOT_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_EOT_CLR = 1 , } impl From < INT_EVENT0_ICLR_EOT_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_EOT_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_EOT` writer - Clear UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] pub type INT_EVENT0_ICLR_EOT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_EOT_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_EOT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_eot_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_EOT_AW :: INT_EVENT0_ICLR_EOT_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_eot_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_EOT_AW :: INT_EVENT0_ICLR_EOT_CLR) } } # [doc = "Clear Address Match Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_ADDR_MATCH_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_ADDR_MATCH_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_ADDR_MATCH_CLR = 1 , } impl From < INT_EVENT0_ICLR_ADDR_MATCH_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_ADDR_MATCH_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_ADDR_MATCH` writer - Clear Address Match Interrupt."] pub type INT_EVENT0_ICLR_ADDR_MATCH_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_ADDR_MATCH_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_ADDR_MATCH_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_addr_match_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_ADDR_MATCH_AW :: INT_EVENT0_ICLR_ADDR_MATCH_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_addr_match_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_ADDR_MATCH_AW :: INT_EVENT0_ICLR_ADDR_MATCH_CLR) } } # [doc = "Clear UART Clear to Send Modem Interrupt. 0 = Interrupt disabled\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_CTS_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_CTS_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_CTS_CLR = 1 , } impl From < INT_EVENT0_ICLR_CTS_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_CTS_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_CTS` writer - Clear UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] pub type INT_EVENT0_ICLR_CTS_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_CTS_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_CTS_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_cts_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_CTS_AW :: INT_EVENT0_ICLR_CTS_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_cts_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_CTS_AW :: INT_EVENT0_ICLR_CTS_CLR) } } # [doc = "Clear DMA Done on RX Event Channel\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_DMA_DONE_RX_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_DMA_DONE_RX_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_DMA_DONE_RX_CLR = 1 , } impl From < INT_EVENT0_ICLR_DMA_DONE_RX_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_DMA_DONE_RX_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_DMA_DONE_RX` writer - Clear DMA Done on RX Event Channel"] pub type INT_EVENT0_ICLR_DMA_DONE_RX_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_DMA_DONE_RX_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_DMA_DONE_RX_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_dma_done_rx_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_DMA_DONE_RX_AW :: INT_EVENT0_ICLR_DMA_DONE_RX_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_dma_done_rx_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_DMA_DONE_RX_AW :: INT_EVENT0_ICLR_DMA_DONE_RX_CLR) } } # [doc = "Clear DMA Done on TX Event Channel\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_DMA_DONE_TX_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_DMA_DONE_TX_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_DMA_DONE_TX_CLR = 1 , } impl From < INT_EVENT0_ICLR_DMA_DONE_TX_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_DMA_DONE_TX_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_DMA_DONE_TX` writer - Clear DMA Done on TX Event Channel"] pub type INT_EVENT0_ICLR_DMA_DONE_TX_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_DMA_DONE_TX_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_DMA_DONE_TX_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_dma_done_tx_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_DMA_DONE_TX_AW :: INT_EVENT0_ICLR_DMA_DONE_TX_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_dma_done_tx_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_DMA_DONE_TX_AW :: INT_EVENT0_ICLR_DMA_DONE_TX_CLR) } } # [doc = "Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_NERR_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_NERR_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_NERR_CLR = 1 , } impl From < INT_EVENT0_ICLR_NERR_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_NERR_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_NERR` writer - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] pub type INT_EVENT0_ICLR_NERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_NERR_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_NERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_nerr_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_NERR_AW :: INT_EVENT0_ICLR_NERR_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_nerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_NERR_AW :: INT_EVENT0_ICLR_NERR_CLR) } } impl W { # [doc = "Bit 0 - Clear UARTOUT Receive Time-Out Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iclr_rtout (& mut self) -> INT_EVENT0_ICLR_RTOUT_W < INT_EVENT0_ICLR_SPEC , 0 > { INT_EVENT0_ICLR_RTOUT_W :: new (self) } # [doc = "Bit 1 - Clear UART Framing Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iclr_frmerr (& mut self) -> INT_EVENT0_ICLR_FRMERR_W < INT_EVENT0_ICLR_SPEC , 1 > { INT_EVENT0_ICLR_FRMERR_W :: new (self) } # [doc = "Bit 2 - Clear UART Parity Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iclr_parerr (& mut self) -> INT_EVENT0_ICLR_PARERR_W < INT_EVENT0_ICLR_SPEC , 2 > { INT_EVENT0_ICLR_PARERR_W :: new (self) } # [doc = "Bit 3 - Clear UART Break Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iclr_brkerr (& mut self) -> INT_EVENT0_ICLR_BRKERR_W < INT_EVENT0_ICLR_SPEC , 3 > { INT_EVENT0_ICLR_BRKERR_W :: new (self) } # [doc = "Bit 4 - Clear UART Receive Overrun Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iclr_ovrerr (& mut self) -> INT_EVENT0_ICLR_OVRERR_W < INT_EVENT0_ICLR_SPEC , 4 > { INT_EVENT0_ICLR_OVRERR_W :: new (self) } # [doc = "Bit 5 - Clear Negative Edge on UARTxRXD Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iclr_rxne (& mut self) -> INT_EVENT0_ICLR_RXNE_W < INT_EVENT0_ICLR_SPEC , 5 > { INT_EVENT0_ICLR_RXNE_W :: new (self) } # [doc = "Bit 6 - Clear Positive Edge on UARTxRXD Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iclr_rxpe (& mut self) -> INT_EVENT0_ICLR_RXPE_W < INT_EVENT0_ICLR_SPEC , 6 > { INT_EVENT0_ICLR_RXPE_W :: new (self) } # [doc = "Bit 7 - Clear LIN Capture 0 / Match Interrupt ."] # [inline (always)] # [must_use] pub fn int_event0_iclr_linc0 (& mut self) -> INT_EVENT0_ICLR_LINC0_W < INT_EVENT0_ICLR_SPEC , 7 > { INT_EVENT0_ICLR_LINC0_W :: new (self) } # [doc = "Bit 8 - Clear LIN Capture 1 Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iclr_linc1 (& mut self) -> INT_EVENT0_ICLR_LINC1_W < INT_EVENT0_ICLR_SPEC , 8 > { INT_EVENT0_ICLR_LINC1_W :: new (self) } # [doc = "Bit 9 - Clear LIN Hardware Counter Overflow Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iclr_linovf (& mut self) -> INT_EVENT0_ICLR_LINOVF_W < INT_EVENT0_ICLR_SPEC , 9 > { INT_EVENT0_ICLR_LINOVF_W :: new (self) } # [doc = "Bit 10 - Clear UART Receive Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iclr_rxint (& mut self) -> INT_EVENT0_ICLR_RXINT_W < INT_EVENT0_ICLR_SPEC , 10 > { INT_EVENT0_ICLR_RXINT_W :: new (self) } # [doc = "Bit 11 - Clear UART Transmit Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iclr_txint (& mut self) -> INT_EVENT0_ICLR_TXINT_W <'_,  INT_EVENT0_ICLR_SPEC , 11 > { INT_EVENT0_ICLR_TXINT_W :: new (self) } # [doc = "Bit 12 - Clear UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] # [inline (always)] # [must_use] pub fn int_event0_iclr_eot (& mut self) -> INT_EVENT0_ICLR_EOT_W < INT_EVENT0_ICLR_SPEC , 12 > { INT_EVENT0_ICLR_EOT_W :: new (self) } # [doc = "Bit 13 - Clear Address Match Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iclr_addr_match (& mut self) -> INT_EVENT0_ICLR_ADDR_MATCH_W < INT_EVENT0_ICLR_SPEC , 13 > { INT_EVENT0_ICLR_ADDR_MATCH_W :: new (self) } # [doc = "Bit 14 - Clear UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] # [inline (always)] # [must_use] pub fn int_event0_iclr_cts (& mut self) -> INT_EVENT0_ICLR_CTS_W < INT_EVENT0_ICLR_SPEC , 14 > { INT_EVENT0_ICLR_CTS_W :: new (self) } # [doc = "Bit 15 - Clear DMA Done on RX Event Channel"] # [inline (always)] # [must_use] pub fn int_event0_iclr_dma_done_rx (& mut self) -> INT_EVENT0_ICLR_DMA_DONE_RX_W < INT_EVENT0_ICLR_SPEC , 15 > { INT_EVENT0_ICLR_DMA_DONE_RX_W :: new (self) } # [doc = "Bit 16 - Clear DMA Done on TX Event Channel"] # [inline (always)] # [must_use] pub fn int_event0_iclr_dma_done_tx (& mut self) -> INT_EVENT0_ICLR_DMA_DONE_TX_W < INT_EVENT0_ICLR_SPEC , 16 > { INT_EVENT0_ICLR_DMA_DONE_TX_W :: new (self) } # [doc = "Bit 17 - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] # [inline (always)] # [must_use] pub fn int_event0_iclr_nerr (& mut self) -> INT_EVENT0_ICLR_NERR_W < INT_EVENT0_ICLR_SPEC , 17 > { INT_EVENT0_ICLR_NERR_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Interrupt clear\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_event0_iclr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct INT_EVENT0_ICLR_SPEC ; impl crate :: RegisterSpec for INT_EVENT0_ICLR_SPEC { type Ux = u32 ; } # [doc = "`write(|w| ..)` method takes [`int_event0_iclr::W`](W) writer structure"] impl crate :: Writable for INT_EVENT0_ICLR_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets INT_EVENT0_ICLR to value 0"] impl crate :: Resettable for INT_EVENT0_ICLR_SPEC { const RESET_VALUE : Self :: Ux = 0 ; }
[INFO] [stdout]   |                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                  +++
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing
[INFO] [stdout]  --> src/uart0/int_event0_iclr.rs:1:24593
[INFO] [stdout]   |
[INFO] [stdout] 1 | ...ent0_iclr_eot (& mut self) -> INT_EVENT0_ICLR_EOT_W < INT_EVENT0_ICLR_SPEC , 12 > { INT_EVENT0_ICLR_EOT_W :: new (self) } # [doc =...
[INFO] [stdout]   |                   ^^^^^^^^^^     ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here
[INFO] [stdout]   |                   |
[INFO] [stdout]   |                   the lifetime is elided here
[INFO] [stdout]   |
[INFO] [stdout]   = help: the same lifetime is referred to in inconsistent ways, making the signature confusing
[INFO] [stdout] help: use `'_` for type paths
[INFO] [stdout]   |
[INFO] [stdout] 1 | # [doc = "Register `INT_EVENT0_ICLR` writer"] pub type W = crate :: W < INT_EVENT0_ICLR_SPEC > ; # [doc = "Clear UARTOUT Receive Time-Out Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_RTOUT_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_RTOUT_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_RTOUT_CLR = 1 , } impl From < INT_EVENT0_ICLR_RTOUT_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_RTOUT_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_RTOUT` writer - Clear UARTOUT Receive Time-Out Interrupt."] pub type INT_EVENT0_ICLR_RTOUT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_RTOUT_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_RTOUT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_rtout_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_RTOUT_AW :: INT_EVENT0_ICLR_RTOUT_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_rtout_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_RTOUT_AW :: INT_EVENT0_ICLR_RTOUT_CLR) } } # [doc = "Clear UART Framing Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_FRMERR_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_FRMERR_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_FRMERR_CLR = 1 , } impl From < INT_EVENT0_ICLR_FRMERR_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_FRMERR_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_FRMERR` writer - Clear UART Framing Error Interrupt."] pub type INT_EVENT0_ICLR_FRMERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_FRMERR_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_FRMERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_frmerr_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_FRMERR_AW :: INT_EVENT0_ICLR_FRMERR_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_frmerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_FRMERR_AW :: INT_EVENT0_ICLR_FRMERR_CLR) } } # [doc = "Clear UART Parity Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_PARERR_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_PARERR_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_PARERR_CLR = 1 , } impl From < INT_EVENT0_ICLR_PARERR_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_PARERR_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_PARERR` writer - Clear UART Parity Error Interrupt."] pub type INT_EVENT0_ICLR_PARERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_PARERR_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_PARERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_parerr_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_PARERR_AW :: INT_EVENT0_ICLR_PARERR_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_parerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_PARERR_AW :: INT_EVENT0_ICLR_PARERR_CLR) } } # [doc = "Clear UART Break Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_BRKERR_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_BRKERR_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_BRKERR_CLR = 1 , } impl From < INT_EVENT0_ICLR_BRKERR_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_BRKERR_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_BRKERR` writer - Clear UART Break Error Interrupt."] pub type INT_EVENT0_ICLR_BRKERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_BRKERR_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_BRKERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_brkerr_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_BRKERR_AW :: INT_EVENT0_ICLR_BRKERR_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_brkerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_BRKERR_AW :: INT_EVENT0_ICLR_BRKERR_CLR) } } # [doc = "Clear UART Receive Overrun Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_OVRERR_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_OVRERR_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_OVRERR_CLR = 1 , } impl From < INT_EVENT0_ICLR_OVRERR_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_OVRERR_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_OVRERR` writer - Clear UART Receive Overrun Error Interrupt."] pub type INT_EVENT0_ICLR_OVRERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_OVRERR_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_OVRERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_ovrerr_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_OVRERR_AW :: INT_EVENT0_ICLR_OVRERR_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_ovrerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_OVRERR_AW :: INT_EVENT0_ICLR_OVRERR_CLR) } } # [doc = "Clear Negative Edge on UARTxRXD Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_RXNE_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_RXNE_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_RXNE_CLR = 1 , } impl From < INT_EVENT0_ICLR_RXNE_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_RXNE_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_RXNE` writer - Clear Negative Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_ICLR_RXNE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_RXNE_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_RXNE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_rxne_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_RXNE_AW :: INT_EVENT0_ICLR_RXNE_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_rxne_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_RXNE_AW :: INT_EVENT0_ICLR_RXNE_CLR) } } # [doc = "Clear Positive Edge on UARTxRXD Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_RXPE_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_RXPE_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_RXPE_CLR = 1 , } impl From < INT_EVENT0_ICLR_RXPE_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_RXPE_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_RXPE` writer - Clear Positive Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_ICLR_RXPE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_RXPE_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_RXPE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_rxpe_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_RXPE_AW :: INT_EVENT0_ICLR_RXPE_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_rxpe_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_RXPE_AW :: INT_EVENT0_ICLR_RXPE_CLR) } } # [doc = "Clear LIN Capture 0 / Match Interrupt .\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_LINC0_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_LINC0_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_LINC0_CLR = 1 , } impl From < INT_EVENT0_ICLR_LINC0_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_LINC0_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_LINC0` writer - Clear LIN Capture 0 / Match Interrupt ."] pub type INT_EVENT0_ICLR_LINC0_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_LINC0_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_LINC0_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_linc0_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_LINC0_AW :: INT_EVENT0_ICLR_LINC0_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_linc0_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_LINC0_AW :: INT_EVENT0_ICLR_LINC0_CLR) } } # [doc = "Clear LIN Capture 1 Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_LINC1_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_LINC1_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_LINC1_CLR = 1 , } impl From < INT_EVENT0_ICLR_LINC1_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_LINC1_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_LINC1` writer - Clear LIN Capture 1 Interrupt."] pub type INT_EVENT0_ICLR_LINC1_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_LINC1_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_LINC1_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_linc1_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_LINC1_AW :: INT_EVENT0_ICLR_LINC1_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_linc1_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_LINC1_AW :: INT_EVENT0_ICLR_LINC1_CLR) } } # [doc = "Clear LIN Hardware Counter Overflow Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_LINOVF_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_LINOVF_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_LINOVF_CLR = 1 , } impl From < INT_EVENT0_ICLR_LINOVF_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_LINOVF_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_LINOVF` writer - Clear LIN Hardware Counter Overflow Interrupt."] pub type INT_EVENT0_ICLR_LINOVF_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_LINOVF_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_LINOVF_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_linovf_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_LINOVF_AW :: INT_EVENT0_ICLR_LINOVF_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_linovf_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_LINOVF_AW :: INT_EVENT0_ICLR_LINOVF_CLR) } } # [doc = "Clear UART Receive Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_RXINT_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_RXINT_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_RXINT_CLR = 1 , } impl From < INT_EVENT0_ICLR_RXINT_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_RXINT_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_RXINT` writer - Clear UART Receive Interrupt."] pub type INT_EVENT0_ICLR_RXINT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_RXINT_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_RXINT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_rxint_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_RXINT_AW :: INT_EVENT0_ICLR_RXINT_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_rxint_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_RXINT_AW :: INT_EVENT0_ICLR_RXINT_CLR) } } # [doc = "Clear UART Transmit Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_TXINT_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_TXINT_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_TXINT_CLR = 1 , } impl From < INT_EVENT0_ICLR_TXINT_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_TXINT_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_TXINT` writer - Clear UART Transmit Interrupt."] pub type INT_EVENT0_ICLR_TXINT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_TXINT_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_TXINT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_txint_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_TXINT_AW :: INT_EVENT0_ICLR_TXINT_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_txint_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_TXINT_AW :: INT_EVENT0_ICLR_TXINT_CLR) } } # [doc = "Clear UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_EOT_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_EOT_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_EOT_CLR = 1 , } impl From < INT_EVENT0_ICLR_EOT_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_EOT_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_EOT` writer - Clear UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] pub type INT_EVENT0_ICLR_EOT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_EOT_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_EOT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_eot_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_EOT_AW :: INT_EVENT0_ICLR_EOT_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_eot_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_EOT_AW :: INT_EVENT0_ICLR_EOT_CLR) } } # [doc = "Clear Address Match Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_ADDR_MATCH_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_ADDR_MATCH_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_ADDR_MATCH_CLR = 1 , } impl From < INT_EVENT0_ICLR_ADDR_MATCH_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_ADDR_MATCH_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_ADDR_MATCH` writer - Clear Address Match Interrupt."] pub type INT_EVENT0_ICLR_ADDR_MATCH_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_ADDR_MATCH_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_ADDR_MATCH_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_addr_match_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_ADDR_MATCH_AW :: INT_EVENT0_ICLR_ADDR_MATCH_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_addr_match_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_ADDR_MATCH_AW :: INT_EVENT0_ICLR_ADDR_MATCH_CLR) } } # [doc = "Clear UART Clear to Send Modem Interrupt. 0 = Interrupt disabled\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_CTS_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_CTS_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_CTS_CLR = 1 , } impl From < INT_EVENT0_ICLR_CTS_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_CTS_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_CTS` writer - Clear UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] pub type INT_EVENT0_ICLR_CTS_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_CTS_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_CTS_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_cts_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_CTS_AW :: INT_EVENT0_ICLR_CTS_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_cts_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_CTS_AW :: INT_EVENT0_ICLR_CTS_CLR) } } # [doc = "Clear DMA Done on RX Event Channel\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_DMA_DONE_RX_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_DMA_DONE_RX_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_DMA_DONE_RX_CLR = 1 , } impl From < INT_EVENT0_ICLR_DMA_DONE_RX_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_DMA_DONE_RX_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_DMA_DONE_RX` writer - Clear DMA Done on RX Event Channel"] pub type INT_EVENT0_ICLR_DMA_DONE_RX_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_DMA_DONE_RX_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_DMA_DONE_RX_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_dma_done_rx_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_DMA_DONE_RX_AW :: INT_EVENT0_ICLR_DMA_DONE_RX_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_dma_done_rx_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_DMA_DONE_RX_AW :: INT_EVENT0_ICLR_DMA_DONE_RX_CLR) } } # [doc = "Clear DMA Done on TX Event Channel\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_DMA_DONE_TX_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_DMA_DONE_TX_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_DMA_DONE_TX_CLR = 1 , } impl From < INT_EVENT0_ICLR_DMA_DONE_TX_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_DMA_DONE_TX_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_DMA_DONE_TX` writer - Clear DMA Done on TX Event Channel"] pub type INT_EVENT0_ICLR_DMA_DONE_TX_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_DMA_DONE_TX_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_DMA_DONE_TX_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_dma_done_tx_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_DMA_DONE_TX_AW :: INT_EVENT0_ICLR_DMA_DONE_TX_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_dma_done_tx_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_DMA_DONE_TX_AW :: INT_EVENT0_ICLR_DMA_DONE_TX_CLR) } } # [doc = "Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_NERR_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_NERR_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_NERR_CLR = 1 , } impl From < INT_EVENT0_ICLR_NERR_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_NERR_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_NERR` writer - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] pub type INT_EVENT0_ICLR_NERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_NERR_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_NERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_nerr_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_NERR_AW :: INT_EVENT0_ICLR_NERR_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_nerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_NERR_AW :: INT_EVENT0_ICLR_NERR_CLR) } } impl W { # [doc = "Bit 0 - Clear UARTOUT Receive Time-Out Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iclr_rtout (& mut self) -> INT_EVENT0_ICLR_RTOUT_W < INT_EVENT0_ICLR_SPEC , 0 > { INT_EVENT0_ICLR_RTOUT_W :: new (self) } # [doc = "Bit 1 - Clear UART Framing Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iclr_frmerr (& mut self) -> INT_EVENT0_ICLR_FRMERR_W < INT_EVENT0_ICLR_SPEC , 1 > { INT_EVENT0_ICLR_FRMERR_W :: new (self) } # [doc = "Bit 2 - Clear UART Parity Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iclr_parerr (& mut self) -> INT_EVENT0_ICLR_PARERR_W < INT_EVENT0_ICLR_SPEC , 2 > { INT_EVENT0_ICLR_PARERR_W :: new (self) } # [doc = "Bit 3 - Clear UART Break Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iclr_brkerr (& mut self) -> INT_EVENT0_ICLR_BRKERR_W < INT_EVENT0_ICLR_SPEC , 3 > { INT_EVENT0_ICLR_BRKERR_W :: new (self) } # [doc = "Bit 4 - Clear UART Receive Overrun Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iclr_ovrerr (& mut self) -> INT_EVENT0_ICLR_OVRERR_W < INT_EVENT0_ICLR_SPEC , 4 > { INT_EVENT0_ICLR_OVRERR_W :: new (self) } # [doc = "Bit 5 - Clear Negative Edge on UARTxRXD Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iclr_rxne (& mut self) -> INT_EVENT0_ICLR_RXNE_W < INT_EVENT0_ICLR_SPEC , 5 > { INT_EVENT0_ICLR_RXNE_W :: new (self) } # [doc = "Bit 6 - Clear Positive Edge on UARTxRXD Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iclr_rxpe (& mut self) -> INT_EVENT0_ICLR_RXPE_W < INT_EVENT0_ICLR_SPEC , 6 > { INT_EVENT0_ICLR_RXPE_W :: new (self) } # [doc = "Bit 7 - Clear LIN Capture 0 / Match Interrupt ."] # [inline (always)] # [must_use] pub fn int_event0_iclr_linc0 (& mut self) -> INT_EVENT0_ICLR_LINC0_W < INT_EVENT0_ICLR_SPEC , 7 > { INT_EVENT0_ICLR_LINC0_W :: new (self) } # [doc = "Bit 8 - Clear LIN Capture 1 Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iclr_linc1 (& mut self) -> INT_EVENT0_ICLR_LINC1_W < INT_EVENT0_ICLR_SPEC , 8 > { INT_EVENT0_ICLR_LINC1_W :: new (self) } # [doc = "Bit 9 - Clear LIN Hardware Counter Overflow Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iclr_linovf (& mut self) -> INT_EVENT0_ICLR_LINOVF_W < INT_EVENT0_ICLR_SPEC , 9 > { INT_EVENT0_ICLR_LINOVF_W :: new (self) } # [doc = "Bit 10 - Clear UART Receive Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iclr_rxint (& mut self) -> INT_EVENT0_ICLR_RXINT_W < INT_EVENT0_ICLR_SPEC , 10 > { INT_EVENT0_ICLR_RXINT_W :: new (self) } # [doc = "Bit 11 - Clear UART Transmit Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iclr_txint (& mut self) -> INT_EVENT0_ICLR_TXINT_W < INT_EVENT0_ICLR_SPEC , 11 > { INT_EVENT0_ICLR_TXINT_W :: new (self) } # [doc = "Bit 12 - Clear UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] # [inline (always)] # [must_use] pub fn int_event0_iclr_eot (& mut self) -> INT_EVENT0_ICLR_EOT_W <'_,  INT_EVENT0_ICLR_SPEC , 12 > { INT_EVENT0_ICLR_EOT_W :: new (self) } # [doc = "Bit 13 - Clear Address Match Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iclr_addr_match (& mut self) -> INT_EVENT0_ICLR_ADDR_MATCH_W < INT_EVENT0_ICLR_SPEC , 13 > { INT_EVENT0_ICLR_ADDR_MATCH_W :: new (self) } # [doc = "Bit 14 - Clear UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] # [inline (always)] # [must_use] pub fn int_event0_iclr_cts (& mut self) -> INT_EVENT0_ICLR_CTS_W < INT_EVENT0_ICLR_SPEC , 14 > { INT_EVENT0_ICLR_CTS_W :: new (self) } # [doc = "Bit 15 - Clear DMA Done on RX Event Channel"] # [inline (always)] # [must_use] pub fn int_event0_iclr_dma_done_rx (& mut self) -> INT_EVENT0_ICLR_DMA_DONE_RX_W < INT_EVENT0_ICLR_SPEC , 15 > { INT_EVENT0_ICLR_DMA_DONE_RX_W :: new (self) } # [doc = "Bit 16 - Clear DMA Done on TX Event Channel"] # [inline (always)] # [must_use] pub fn int_event0_iclr_dma_done_tx (& mut self) -> INT_EVENT0_ICLR_DMA_DONE_TX_W < INT_EVENT0_ICLR_SPEC , 16 > { INT_EVENT0_ICLR_DMA_DONE_TX_W :: new (self) } # [doc = "Bit 17 - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] # [inline (always)] # [must_use] pub fn int_event0_iclr_nerr (& mut self) -> INT_EVENT0_ICLR_NERR_W < INT_EVENT0_ICLR_SPEC , 17 > { INT_EVENT0_ICLR_NERR_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Interrupt clear\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_event0_iclr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct INT_EVENT0_ICLR_SPEC ; impl crate :: RegisterSpec for INT_EVENT0_ICLR_SPEC { type Ux = u32 ; } # [doc = "`write(|w| ..)` method takes [`int_event0_iclr::W`](W) writer structure"] impl crate :: Writable for INT_EVENT0_ICLR_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets INT_EVENT0_ICLR to value 0"] impl crate :: Resettable for INT_EVENT0_ICLR_SPEC { const RESET_VALUE : Self :: Ux = 0 ; }
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                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                        +++
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing
[INFO] [stdout]  --> src/uart0/int_event0_imask.rs:1:41204
[INFO] [stdout]   |
[INFO] [stdout] 1 | ...mask_brkerr (& mut self) -> INT_EVENT0_IMASK_BRKERR_W < INT_EVENT0_IMASK_SPEC , 3 > { INT_EVENT0_IMASK_BRKERR_W :: new (self) } # ...
[INFO] [stdout]   |                 ^^^^^^^^^^     ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here
[INFO] [stdout]   |                 |
[INFO] [stdout]   |                 the lifetime is elided here
[INFO] [stdout]   |
[INFO] [stdout]   = help: the same lifetime is referred to in inconsistent ways, making the signature confusing
[INFO] [stdout] help: use `'_` for type paths
[INFO] [stdout]   |
[INFO] [stdout] 1 | # [doc = "Register `INT_EVENT0_IMASK` reader"] pub type R = crate :: R < INT_EVENT0_IMASK_SPEC > ; # [doc = "Register `INT_EVENT0_IMASK` writer"] pub type W = crate :: W < INT_EVENT0_IMASK_SPEC > ; # [doc = "Field `INT_EVENT0_IMASK_RTOUT` reader - Enable UARTOUT Receive Time-Out Interrupt."] pub type INT_EVENT0_IMASK_RTOUT_R = crate :: BitReader < INT_EVENT0_IMASK_RTOUT_A > ; # [doc = "Enable UARTOUT Receive Time-Out Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_RTOUT_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_RTOUT_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_RTOUT_SET = 1 , } impl From < INT_EVENT0_IMASK_RTOUT_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_RTOUT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_RTOUT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_RTOUT_A { match self . bits { false => INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_CLR , true => INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_rtout_clr (& self) -> bool { * self == INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_rtout_set (& self) -> bool { * self == INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_SET } } # [doc = "Field `INT_EVENT0_IMASK_RTOUT` writer - Enable UARTOUT Receive Time-Out Interrupt."] pub type INT_EVENT0_IMASK_RTOUT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_RTOUT_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_RTOUT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_rtout_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_rtout_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_SET) } } # [doc = "Field `INT_EVENT0_IMASK_FRMERR` reader - Enable UART Framing Error Interrupt."] pub type INT_EVENT0_IMASK_FRMERR_R = crate :: BitReader < INT_EVENT0_IMASK_FRMERR_A > ; # [doc = "Enable UART Framing Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_FRMERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_FRMERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_FRMERR_SET = 1 , } impl From < INT_EVENT0_IMASK_FRMERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_FRMERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_FRMERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_FRMERR_A { match self . bits { false => INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_CLR , true => INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_frmerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_frmerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_FRMERR` writer - Enable UART Framing Error Interrupt."] pub type INT_EVENT0_IMASK_FRMERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_FRMERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_FRMERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_frmerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_frmerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_SET) } } # [doc = "Field `INT_EVENT0_IMASK_PARERR` reader - Enable UART Parity Error Interrupt."] pub type INT_EVENT0_IMASK_PARERR_R = crate :: BitReader < INT_EVENT0_IMASK_PARERR_A > ; # [doc = "Enable UART Parity Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_PARERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_PARERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_PARERR_SET = 1 , } impl From < INT_EVENT0_IMASK_PARERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_PARERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_PARERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_PARERR_A { match self . bits { false => INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_CLR , true => INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_parerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_parerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_PARERR` writer - Enable UART Parity Error Interrupt."] pub type INT_EVENT0_IMASK_PARERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_PARERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_PARERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_parerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_parerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_SET) } } # [doc = "Field `INT_EVENT0_IMASK_BRKERR` reader - Enable UART Break Error Interrupt."] pub type INT_EVENT0_IMASK_BRKERR_R = crate :: BitReader < INT_EVENT0_IMASK_BRKERR_A > ; # [doc = "Enable UART Break Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_BRKERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_BRKERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_BRKERR_SET = 1 , } impl From < INT_EVENT0_IMASK_BRKERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_BRKERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_BRKERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_BRKERR_A { match self . bits { false => INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_CLR , true => INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_brkerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_brkerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_BRKERR` writer - Enable UART Break Error Interrupt."] pub type INT_EVENT0_IMASK_BRKERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_BRKERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_BRKERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_brkerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_brkerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_SET) } } # [doc = "Field `INT_EVENT0_IMASK_OVRERR` reader - Enable UART Receive Overrun Error Interrupt."] pub type INT_EVENT0_IMASK_OVRERR_R = crate :: BitReader < INT_EVENT0_IMASK_OVRERR_A > ; # [doc = "Enable UART Receive Overrun Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_OVRERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_OVRERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_OVRERR_SET = 1 , } impl From < INT_EVENT0_IMASK_OVRERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_OVRERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_OVRERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_OVRERR_A { match self . bits { false => INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_CLR , true => INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_ovrerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_ovrerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_OVRERR` writer - Enable UART Receive Overrun Error Interrupt."] pub type INT_EVENT0_IMASK_OVRERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_OVRERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_OVRERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_ovrerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_ovrerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_SET) } } # [doc = "Field `INT_EVENT0_IMASK_RXNE` reader - Enable Negative Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_IMASK_RXNE_R = crate :: BitReader < INT_EVENT0_IMASK_RXNE_A > ; # [doc = "Enable Negative Edge on UARTxRXD Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_RXNE_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_RXNE_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_RXNE_SET = 1 , } impl From < INT_EVENT0_IMASK_RXNE_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_RXNE_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_RXNE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_RXNE_A { match self . bits { false => INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_CLR , true => INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_rxne_clr (& self) -> bool { * self == INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_rxne_set (& self) -> bool { * self == INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_SET } } # [doc = "Field `INT_EVENT0_IMASK_RXNE` writer - Enable Negative Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_IMASK_RXNE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_RXNE_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_RXNE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_rxne_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_rxne_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_SET) } } # [doc = "Field `INT_EVENT0_IMASK_RXPE` reader - Enable Positive Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_IMASK_RXPE_R = crate :: BitReader < INT_EVENT0_IMASK_RXPE_A > ; # [doc = "Enable Positive Edge on UARTxRXD Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_RXPE_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_RXPE_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_RXPE_SET = 1 , } impl From < INT_EVENT0_IMASK_RXPE_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_RXPE_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_RXPE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_RXPE_A { match self . bits { false => INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_CLR , true => INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_rxpe_clr (& self) -> bool { * self == INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_rxpe_set (& self) -> bool { * self == INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_SET } } # [doc = "Field `INT_EVENT0_IMASK_RXPE` writer - Enable Positive Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_IMASK_RXPE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_RXPE_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_RXPE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_rxpe_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_rxpe_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_SET) } } # [doc = "Field `INT_EVENT0_IMASK_LINC0` reader - Enable LIN Capture 0 / Match Interrupt ."] pub type INT_EVENT0_IMASK_LINC0_R = crate :: BitReader < INT_EVENT0_IMASK_LINC0_A > ; # [doc = "Enable LIN Capture 0 / Match Interrupt .\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_LINC0_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_LINC0_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_LINC0_SET = 1 , } impl From < INT_EVENT0_IMASK_LINC0_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_LINC0_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_LINC0_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_LINC0_A { match self . bits { false => INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_CLR , true => INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_linc0_clr (& self) -> bool { * self == INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_linc0_set (& self) -> bool { * self == INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_SET } } # [doc = "Field `INT_EVENT0_IMASK_LINC0` writer - Enable LIN Capture 0 / Match Interrupt ."] pub type INT_EVENT0_IMASK_LINC0_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_LINC0_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_LINC0_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_linc0_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_linc0_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_SET) } } # [doc = "Field `INT_EVENT0_IMASK_LINC1` reader - Enable LIN Capture 1 Interrupt."] pub type INT_EVENT0_IMASK_LINC1_R = crate :: BitReader < INT_EVENT0_IMASK_LINC1_A > ; # [doc = "Enable LIN Capture 1 Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_LINC1_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_LINC1_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_LINC1_SET = 1 , } impl From < INT_EVENT0_IMASK_LINC1_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_LINC1_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_LINC1_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_LINC1_A { match self . bits { false => INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_CLR , true => INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_linc1_clr (& self) -> bool { * self == INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_linc1_set (& self) -> bool { * self == INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_SET } } # [doc = "Field `INT_EVENT0_IMASK_LINC1` writer - Enable LIN Capture 1 Interrupt."] pub type INT_EVENT0_IMASK_LINC1_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_LINC1_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_LINC1_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_linc1_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_linc1_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_SET) } } # [doc = "Field `INT_EVENT0_IMASK_LINOVF` reader - Enable LIN Hardware Counter Overflow Interrupt."] pub type INT_EVENT0_IMASK_LINOVF_R = crate :: BitReader < INT_EVENT0_IMASK_LINOVF_A > ; # [doc = "Enable LIN Hardware Counter Overflow Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_LINOVF_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_LINOVF_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_LINOVF_SET = 1 , } impl From < INT_EVENT0_IMASK_LINOVF_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_LINOVF_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_LINOVF_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_LINOVF_A { match self . bits { false => INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_CLR , true => INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_linovf_clr (& self) -> bool { * self == INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_linovf_set (& self) -> bool { * self == INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_SET } } # [doc = "Field `INT_EVENT0_IMASK_LINOVF` writer - Enable LIN Hardware Counter Overflow Interrupt."] pub type INT_EVENT0_IMASK_LINOVF_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_LINOVF_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_LINOVF_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_linovf_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_linovf_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_SET) } } # [doc = "Field `INT_EVENT0_IMASK_RXINT` reader - Enable UART Receive Interrupt."] pub type INT_EVENT0_IMASK_RXINT_R = crate :: BitReader < INT_EVENT0_IMASK_RXINT_A > ; # [doc = "Enable UART Receive Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_RXINT_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_RXINT_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_RXINT_SET = 1 , } impl From < INT_EVENT0_IMASK_RXINT_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_RXINT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_RXINT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_RXINT_A { match self . bits { false => INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_CLR , true => INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_rxint_clr (& self) -> bool { * self == INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_rxint_set (& self) -> bool { * self == INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_SET } } # [doc = "Field `INT_EVENT0_IMASK_RXINT` writer - Enable UART Receive Interrupt."] pub type INT_EVENT0_IMASK_RXINT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_RXINT_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_RXINT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_rxint_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_rxint_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_SET) } } # [doc = "Field `INT_EVENT0_IMASK_TXINT` reader - Enable UART Transmit Interrupt."] pub type INT_EVENT0_IMASK_TXINT_R = crate :: BitReader < INT_EVENT0_IMASK_TXINT_A > ; # [doc = "Enable UART Transmit Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_TXINT_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_TXINT_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_TXINT_SET = 1 , } impl From < INT_EVENT0_IMASK_TXINT_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_TXINT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_TXINT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_TXINT_A { match self . bits { false => INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_CLR , true => INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_txint_clr (& self) -> bool { * self == INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_txint_set (& self) -> bool { * self == INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_SET } } # [doc = "Field `INT_EVENT0_IMASK_TXINT` writer - Enable UART Transmit Interrupt."] pub type INT_EVENT0_IMASK_TXINT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_TXINT_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_TXINT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_txint_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_txint_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_SET) } } # [doc = "Field `INT_EVENT0_IMASK_EOT` reader - Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] pub type INT_EVENT0_IMASK_EOT_R = crate :: BitReader < INT_EVENT0_IMASK_EOT_A > ; # [doc = "Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_EOT_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_EOT_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_EOT_SET = 1 , } impl From < INT_EVENT0_IMASK_EOT_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_EOT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_EOT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_EOT_A { match self . bits { false => INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_CLR , true => INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_eot_clr (& self) -> bool { * self == INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_eot_set (& self) -> bool { * self == INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_SET } } # [doc = "Field `INT_EVENT0_IMASK_EOT` writer - Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] pub type INT_EVENT0_IMASK_EOT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_EOT_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_EOT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_eot_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_eot_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_SET) } } # [doc = "Field `INT_EVENT0_IMASK_ADDR_MATCH` reader - Enable Address Match Interrupt."] pub type INT_EVENT0_IMASK_ADDR_MATCH_R = crate :: BitReader < INT_EVENT0_IMASK_ADDR_MATCH_A > ; # [doc = "Enable Address Match Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_ADDR_MATCH_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_ADDR_MATCH_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_ADDR_MATCH_SET = 1 , } impl From < INT_EVENT0_IMASK_ADDR_MATCH_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_ADDR_MATCH_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_ADDR_MATCH_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_ADDR_MATCH_A { match self . bits { false => INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_CLR , true => INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_addr_match_clr (& self) -> bool { * self == INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_addr_match_set (& self) -> bool { * self == INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_SET } } # [doc = "Field `INT_EVENT0_IMASK_ADDR_MATCH` writer - Enable Address Match Interrupt."] pub type INT_EVENT0_IMASK_ADDR_MATCH_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_ADDR_MATCH_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_ADDR_MATCH_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_addr_match_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_addr_match_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_SET) } } # [doc = "Field `INT_EVENT0_IMASK_CTS` reader - Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] pub type INT_EVENT0_IMASK_CTS_R = crate :: BitReader < INT_EVENT0_IMASK_CTS_A > ; # [doc = "Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_CTS_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_CTS_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_CTS_SET = 1 , } impl From < INT_EVENT0_IMASK_CTS_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_CTS_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_CTS_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_CTS_A { match self . bits { false => INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_CLR , true => INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_cts_clr (& self) -> bool { * self == INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_cts_set (& self) -> bool { * self == INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_SET } } # [doc = "Field `INT_EVENT0_IMASK_CTS` writer - Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] pub type INT_EVENT0_IMASK_CTS_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_CTS_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_CTS_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_cts_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_cts_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DMA_DONE_RX` reader - Enable DMA Done on RX Event Channel"] pub type INT_EVENT0_IMASK_DMA_DONE_RX_R = crate :: BitReader < INT_EVENT0_IMASK_DMA_DONE_RX_A > ; # [doc = "Enable DMA Done on RX Event Channel\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DMA_DONE_RX_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DMA_DONE_RX_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DMA_DONE_RX_SET = 1 , } impl From < INT_EVENT0_IMASK_DMA_DONE_RX_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DMA_DONE_RX_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DMA_DONE_RX_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DMA_DONE_RX_A { match self . bits { false => INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_CLR , true => INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dma_done_rx_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dma_done_rx_set (& self) -> bool { * self == INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_SET } } # [doc = "Field `INT_EVENT0_IMASK_DMA_DONE_RX` writer - Enable DMA Done on RX Event Channel"] pub type INT_EVENT0_IMASK_DMA_DONE_RX_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DMA_DONE_RX_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DMA_DONE_RX_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dma_done_rx_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dma_done_rx_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DMA_DONE_TX` reader - Enable DMA Done on TX Event Channel"] pub type INT_EVENT0_IMASK_DMA_DONE_TX_R = crate :: BitReader < INT_EVENT0_IMASK_DMA_DONE_TX_A > ; # [doc = "Enable DMA Done on TX Event Channel\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DMA_DONE_TX_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DMA_DONE_TX_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DMA_DONE_TX_SET = 1 , } impl From < INT_EVENT0_IMASK_DMA_DONE_TX_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DMA_DONE_TX_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DMA_DONE_TX_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DMA_DONE_TX_A { match self . bits { false => INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_CLR , true => INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dma_done_tx_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dma_done_tx_set (& self) -> bool { * self == INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_SET } } # [doc = "Field `INT_EVENT0_IMASK_DMA_DONE_TX` writer - Enable DMA Done on TX Event Channel"] pub type INT_EVENT0_IMASK_DMA_DONE_TX_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DMA_DONE_TX_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DMA_DONE_TX_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dma_done_tx_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dma_done_tx_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_SET) } } # [doc = "Field `INT_EVENT0_IMASK_NERR` reader - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] pub type INT_EVENT0_IMASK_NERR_R = crate :: BitReader < INT_EVENT0_IMASK_NERR_A > ; # [doc = "Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_NERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_NERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_NERR_SET = 1 , } impl From < INT_EVENT0_IMASK_NERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_NERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_NERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_NERR_A { match self . bits { false => INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_CLR , true => INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_nerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_nerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_NERR` writer - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] pub type INT_EVENT0_IMASK_NERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_NERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_NERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_nerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_nerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_SET) } } impl R { # [doc = "Bit 0 - Enable UARTOUT Receive Time-Out Interrupt."] # [inline (always)] pub fn int_event0_imask_rtout (& self) -> INT_EVENT0_IMASK_RTOUT_R { INT_EVENT0_IMASK_RTOUT_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - Enable UART Framing Error Interrupt."] # [inline (always)] pub fn int_event0_imask_frmerr (& self) -> INT_EVENT0_IMASK_FRMERR_R { INT_EVENT0_IMASK_FRMERR_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - Enable UART Parity Error Interrupt."] # [inline (always)] pub fn int_event0_imask_parerr (& self) -> INT_EVENT0_IMASK_PARERR_R { INT_EVENT0_IMASK_PARERR_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - Enable UART Break Error Interrupt."] # [inline (always)] pub fn int_event0_imask_brkerr (& self) -> INT_EVENT0_IMASK_BRKERR_R { INT_EVENT0_IMASK_BRKERR_R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - Enable UART Receive Overrun Error Interrupt."] # [inline (always)] pub fn int_event0_imask_ovrerr (& self) -> INT_EVENT0_IMASK_OVRERR_R { INT_EVENT0_IMASK_OVRERR_R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - Enable Negative Edge on UARTxRXD Interrupt."] # [inline (always)] pub fn int_event0_imask_rxne (& self) -> INT_EVENT0_IMASK_RXNE_R { INT_EVENT0_IMASK_RXNE_R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - Enable Positive Edge on UARTxRXD Interrupt."] # [inline (always)] pub fn int_event0_imask_rxpe (& self) -> INT_EVENT0_IMASK_RXPE_R { INT_EVENT0_IMASK_RXPE_R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - Enable LIN Capture 0 / Match Interrupt ."] # [inline (always)] pub fn int_event0_imask_linc0 (& self) -> INT_EVENT0_IMASK_LINC0_R { INT_EVENT0_IMASK_LINC0_R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - Enable LIN Capture 1 Interrupt."] # [inline (always)] pub fn int_event0_imask_linc1 (& self) -> INT_EVENT0_IMASK_LINC1_R { INT_EVENT0_IMASK_LINC1_R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - Enable LIN Hardware Counter Overflow Interrupt."] # [inline (always)] pub fn int_event0_imask_linovf (& self) -> INT_EVENT0_IMASK_LINOVF_R { INT_EVENT0_IMASK_LINOVF_R :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - Enable UART Receive Interrupt."] # [inline (always)] pub fn int_event0_imask_rxint (& self) -> INT_EVENT0_IMASK_RXINT_R { INT_EVENT0_IMASK_RXINT_R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - Enable UART Transmit Interrupt."] # [inline (always)] pub fn int_event0_imask_txint (& self) -> INT_EVENT0_IMASK_TXINT_R { INT_EVENT0_IMASK_TXINT_R :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] # [inline (always)] pub fn int_event0_imask_eot (& self) -> INT_EVENT0_IMASK_EOT_R { INT_EVENT0_IMASK_EOT_R :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - Enable Address Match Interrupt."] # [inline (always)] pub fn int_event0_imask_addr_match (& self) -> INT_EVENT0_IMASK_ADDR_MATCH_R { INT_EVENT0_IMASK_ADDR_MATCH_R :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 14 - Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] # [inline (always)] pub fn int_event0_imask_cts (& self) -> INT_EVENT0_IMASK_CTS_R { INT_EVENT0_IMASK_CTS_R :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - Enable DMA Done on RX Event Channel"] # [inline (always)] pub fn int_event0_imask_dma_done_rx (& self) -> INT_EVENT0_IMASK_DMA_DONE_RX_R { INT_EVENT0_IMASK_DMA_DONE_RX_R :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bit 16 - Enable DMA Done on TX Event Channel"] # [inline (always)] pub fn int_event0_imask_dma_done_tx (& self) -> INT_EVENT0_IMASK_DMA_DONE_TX_R { INT_EVENT0_IMASK_DMA_DONE_TX_R :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] # [inline (always)] pub fn int_event0_imask_nerr (& self) -> INT_EVENT0_IMASK_NERR_R { INT_EVENT0_IMASK_NERR_R :: new (((self . bits >> 17) & 1) != 0) } } impl W { # [doc = "Bit 0 - Enable UARTOUT Receive Time-Out Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_rtout (& mut self) -> INT_EVENT0_IMASK_RTOUT_W < INT_EVENT0_IMASK_SPEC , 0 > { INT_EVENT0_IMASK_RTOUT_W :: new (self) } # [doc = "Bit 1 - Enable UART Framing Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_frmerr (& mut self) -> INT_EVENT0_IMASK_FRMERR_W < INT_EVENT0_IMASK_SPEC , 1 > { INT_EVENT0_IMASK_FRMERR_W :: new (self) } # [doc = "Bit 2 - Enable UART Parity Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_parerr (& mut self) -> INT_EVENT0_IMASK_PARERR_W < INT_EVENT0_IMASK_SPEC , 2 > { INT_EVENT0_IMASK_PARERR_W :: new (self) } # [doc = "Bit 3 - Enable UART Break Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_brkerr (& mut self) -> INT_EVENT0_IMASK_BRKERR_W <'_,  INT_EVENT0_IMASK_SPEC , 3 > { INT_EVENT0_IMASK_BRKERR_W :: new (self) } # [doc = "Bit 4 - Enable UART Receive Overrun Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_ovrerr (& mut self) -> INT_EVENT0_IMASK_OVRERR_W < INT_EVENT0_IMASK_SPEC , 4 > { INT_EVENT0_IMASK_OVRERR_W :: new (self) } # [doc = "Bit 5 - Enable Negative Edge on UARTxRXD Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_rxne (& mut self) -> INT_EVENT0_IMASK_RXNE_W < INT_EVENT0_IMASK_SPEC , 5 > { INT_EVENT0_IMASK_RXNE_W :: new (self) } # [doc = "Bit 6 - Enable Positive Edge on UARTxRXD Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_rxpe (& mut self) -> INT_EVENT0_IMASK_RXPE_W < INT_EVENT0_IMASK_SPEC , 6 > { INT_EVENT0_IMASK_RXPE_W :: new (self) } # [doc = "Bit 7 - Enable LIN Capture 0 / Match Interrupt ."] # [inline (always)] # [must_use] pub fn int_event0_imask_linc0 (& mut self) -> INT_EVENT0_IMASK_LINC0_W < INT_EVENT0_IMASK_SPEC , 7 > { INT_EVENT0_IMASK_LINC0_W :: new (self) } # [doc = "Bit 8 - Enable LIN Capture 1 Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_linc1 (& mut self) -> INT_EVENT0_IMASK_LINC1_W < INT_EVENT0_IMASK_SPEC , 8 > { INT_EVENT0_IMASK_LINC1_W :: new (self) } # [doc = "Bit 9 - Enable LIN Hardware Counter Overflow Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_linovf (& mut self) -> INT_EVENT0_IMASK_LINOVF_W < INT_EVENT0_IMASK_SPEC , 9 > { INT_EVENT0_IMASK_LINOVF_W :: new (self) } # [doc = "Bit 10 - Enable UART Receive Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_rxint (& mut self) -> INT_EVENT0_IMASK_RXINT_W < INT_EVENT0_IMASK_SPEC , 10 > { INT_EVENT0_IMASK_RXINT_W :: new (self) } # [doc = "Bit 11 - Enable UART Transmit Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_txint (& mut self) -> INT_EVENT0_IMASK_TXINT_W < INT_EVENT0_IMASK_SPEC , 11 > { INT_EVENT0_IMASK_TXINT_W :: new (self) } # [doc = "Bit 12 - Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] # [inline (always)] # [must_use] pub fn int_event0_imask_eot (& mut self) -> INT_EVENT0_IMASK_EOT_W < INT_EVENT0_IMASK_SPEC , 12 > { INT_EVENT0_IMASK_EOT_W :: new (self) } # [doc = "Bit 13 - Enable Address Match Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_addr_match (& mut self) -> INT_EVENT0_IMASK_ADDR_MATCH_W < INT_EVENT0_IMASK_SPEC , 13 > { INT_EVENT0_IMASK_ADDR_MATCH_W :: new (self) } # [doc = "Bit 14 - Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] # [inline (always)] # [must_use] pub fn int_event0_imask_cts (& mut self) -> INT_EVENT0_IMASK_CTS_W < INT_EVENT0_IMASK_SPEC , 14 > { INT_EVENT0_IMASK_CTS_W :: new (self) } # [doc = "Bit 15 - Enable DMA Done on RX Event Channel"] # [inline (always)] # [must_use] pub fn int_event0_imask_dma_done_rx (& mut self) -> INT_EVENT0_IMASK_DMA_DONE_RX_W < INT_EVENT0_IMASK_SPEC , 15 > { INT_EVENT0_IMASK_DMA_DONE_RX_W :: new (self) } # [doc = "Bit 16 - Enable DMA Done on TX Event Channel"] # [inline (always)] # [must_use] pub fn int_event0_imask_dma_done_tx (& mut self) -> INT_EVENT0_IMASK_DMA_DONE_TX_W < INT_EVENT0_IMASK_SPEC , 16 > { INT_EVENT0_IMASK_DMA_DONE_TX_W :: new (self) } # [doc = "Bit 17 - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] # [inline (always)] # [must_use] pub fn int_event0_imask_nerr (& mut self) -> INT_EVENT0_IMASK_NERR_W < INT_EVENT0_IMASK_SPEC , 17 > { INT_EVENT0_IMASK_NERR_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Interrupt mask\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_event0_imask::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_event0_imask::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct INT_EVENT0_IMASK_SPEC ; impl crate :: RegisterSpec for INT_EVENT0_IMASK_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`int_event0_imask::R`](R) reader structure"] impl crate :: Readable for INT_EVENT0_IMASK_SPEC { } # [doc = "`write(|w| ..)` method takes [`int_event0_imask::W`](W) writer structure"] impl crate :: Writable for INT_EVENT0_IMASK_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets INT_EVENT0_IMASK to value 0"] impl crate :: Resettable for INT_EVENT0_IMASK_SPEC { const RESET_VALUE : Self :: Ux = 0 ; }
[INFO] [stdout]   |                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                              +++
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing
[INFO] [stdout]  --> src/uart0/int_event0_iclr.rs:1:24820
[INFO] [stdout]   |
[INFO] [stdout] 1 | ...addr_match (& mut self) -> INT_EVENT0_ICLR_ADDR_MATCH_W < INT_EVENT0_ICLR_SPEC , 13 > { INT_EVENT0_ICLR_ADDR_MATCH_W :: new (self)...
[INFO] [stdout]   |                ^^^^^^^^^^     ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here
[INFO] [stdout]   |                |
[INFO] [stdout]   |                the lifetime is elided here
[INFO] [stdout]   |
[INFO] [stdout]   = help: the same lifetime is referred to in inconsistent ways, making the signature confusing
[INFO] [stdout] help: use `'_` for type paths
[INFO] [stdout]   |
[INFO] [stdout] 1 | # [doc = "Register `INT_EVENT0_ICLR` writer"] pub type W = crate :: W < INT_EVENT0_ICLR_SPEC > ; # [doc = "Clear UARTOUT Receive Time-Out Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_RTOUT_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_RTOUT_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_RTOUT_CLR = 1 , } impl From < INT_EVENT0_ICLR_RTOUT_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_RTOUT_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_RTOUT` writer - Clear UARTOUT Receive Time-Out Interrupt."] pub type INT_EVENT0_ICLR_RTOUT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_RTOUT_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_RTOUT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_rtout_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_RTOUT_AW :: INT_EVENT0_ICLR_RTOUT_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_rtout_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_RTOUT_AW :: INT_EVENT0_ICLR_RTOUT_CLR) } } # [doc = "Clear UART Framing Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_FRMERR_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_FRMERR_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_FRMERR_CLR = 1 , } impl From < INT_EVENT0_ICLR_FRMERR_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_FRMERR_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_FRMERR` writer - Clear UART Framing Error Interrupt."] pub type INT_EVENT0_ICLR_FRMERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_FRMERR_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_FRMERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_frmerr_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_FRMERR_AW :: INT_EVENT0_ICLR_FRMERR_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_frmerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_FRMERR_AW :: INT_EVENT0_ICLR_FRMERR_CLR) } } # [doc = "Clear UART Parity Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_PARERR_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_PARERR_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_PARERR_CLR = 1 , } impl From < INT_EVENT0_ICLR_PARERR_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_PARERR_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_PARERR` writer - Clear UART Parity Error Interrupt."] pub type INT_EVENT0_ICLR_PARERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_PARERR_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_PARERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_parerr_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_PARERR_AW :: INT_EVENT0_ICLR_PARERR_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_parerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_PARERR_AW :: INT_EVENT0_ICLR_PARERR_CLR) } } # [doc = "Clear UART Break Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_BRKERR_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_BRKERR_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_BRKERR_CLR = 1 , } impl From < INT_EVENT0_ICLR_BRKERR_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_BRKERR_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_BRKERR` writer - Clear UART Break Error Interrupt."] pub type INT_EVENT0_ICLR_BRKERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_BRKERR_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_BRKERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_brkerr_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_BRKERR_AW :: INT_EVENT0_ICLR_BRKERR_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_brkerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_BRKERR_AW :: INT_EVENT0_ICLR_BRKERR_CLR) } } # [doc = "Clear UART Receive Overrun Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_OVRERR_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_OVRERR_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_OVRERR_CLR = 1 , } impl From < INT_EVENT0_ICLR_OVRERR_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_OVRERR_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_OVRERR` writer - Clear UART Receive Overrun Error Interrupt."] pub type INT_EVENT0_ICLR_OVRERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_OVRERR_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_OVRERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_ovrerr_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_OVRERR_AW :: INT_EVENT0_ICLR_OVRERR_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_ovrerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_OVRERR_AW :: INT_EVENT0_ICLR_OVRERR_CLR) } } # [doc = "Clear Negative Edge on UARTxRXD Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_RXNE_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_RXNE_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_RXNE_CLR = 1 , } impl From < INT_EVENT0_ICLR_RXNE_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_RXNE_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_RXNE` writer - Clear Negative Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_ICLR_RXNE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_RXNE_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_RXNE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_rxne_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_RXNE_AW :: INT_EVENT0_ICLR_RXNE_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_rxne_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_RXNE_AW :: INT_EVENT0_ICLR_RXNE_CLR) } } # [doc = "Clear Positive Edge on UARTxRXD Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_RXPE_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_RXPE_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_RXPE_CLR = 1 , } impl From < INT_EVENT0_ICLR_RXPE_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_RXPE_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_RXPE` writer - Clear Positive Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_ICLR_RXPE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_RXPE_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_RXPE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_rxpe_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_RXPE_AW :: INT_EVENT0_ICLR_RXPE_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_rxpe_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_RXPE_AW :: INT_EVENT0_ICLR_RXPE_CLR) } } # [doc = "Clear LIN Capture 0 / Match Interrupt .\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_LINC0_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_LINC0_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_LINC0_CLR = 1 , } impl From < INT_EVENT0_ICLR_LINC0_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_LINC0_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_LINC0` writer - Clear LIN Capture 0 / Match Interrupt ."] pub type INT_EVENT0_ICLR_LINC0_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_LINC0_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_LINC0_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_linc0_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_LINC0_AW :: INT_EVENT0_ICLR_LINC0_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_linc0_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_LINC0_AW :: INT_EVENT0_ICLR_LINC0_CLR) } } # [doc = "Clear LIN Capture 1 Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_LINC1_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_LINC1_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_LINC1_CLR = 1 , } impl From < INT_EVENT0_ICLR_LINC1_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_LINC1_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_LINC1` writer - Clear LIN Capture 1 Interrupt."] pub type INT_EVENT0_ICLR_LINC1_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_LINC1_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_LINC1_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_linc1_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_LINC1_AW :: INT_EVENT0_ICLR_LINC1_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_linc1_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_LINC1_AW :: INT_EVENT0_ICLR_LINC1_CLR) } } # [doc = "Clear LIN Hardware Counter Overflow Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_LINOVF_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_LINOVF_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_LINOVF_CLR = 1 , } impl From < INT_EVENT0_ICLR_LINOVF_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_LINOVF_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_LINOVF` writer - Clear LIN Hardware Counter Overflow Interrupt."] pub type INT_EVENT0_ICLR_LINOVF_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_LINOVF_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_LINOVF_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_linovf_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_LINOVF_AW :: INT_EVENT0_ICLR_LINOVF_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_linovf_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_LINOVF_AW :: INT_EVENT0_ICLR_LINOVF_CLR) } } # [doc = "Clear UART Receive Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_RXINT_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_RXINT_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_RXINT_CLR = 1 , } impl From < INT_EVENT0_ICLR_RXINT_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_RXINT_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_RXINT` writer - Clear UART Receive Interrupt."] pub type INT_EVENT0_ICLR_RXINT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_RXINT_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_RXINT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_rxint_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_RXINT_AW :: INT_EVENT0_ICLR_RXINT_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_rxint_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_RXINT_AW :: INT_EVENT0_ICLR_RXINT_CLR) } } # [doc = "Clear UART Transmit Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_TXINT_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_TXINT_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_TXINT_CLR = 1 , } impl From < INT_EVENT0_ICLR_TXINT_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_TXINT_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_TXINT` writer - Clear UART Transmit Interrupt."] pub type INT_EVENT0_ICLR_TXINT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_TXINT_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_TXINT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_txint_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_TXINT_AW :: INT_EVENT0_ICLR_TXINT_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_txint_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_TXINT_AW :: INT_EVENT0_ICLR_TXINT_CLR) } } # [doc = "Clear UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_EOT_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_EOT_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_EOT_CLR = 1 , } impl From < INT_EVENT0_ICLR_EOT_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_EOT_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_EOT` writer - Clear UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] pub type INT_EVENT0_ICLR_EOT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_EOT_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_EOT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_eot_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_EOT_AW :: INT_EVENT0_ICLR_EOT_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_eot_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_EOT_AW :: INT_EVENT0_ICLR_EOT_CLR) } } # [doc = "Clear Address Match Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_ADDR_MATCH_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_ADDR_MATCH_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_ADDR_MATCH_CLR = 1 , } impl From < INT_EVENT0_ICLR_ADDR_MATCH_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_ADDR_MATCH_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_ADDR_MATCH` writer - Clear Address Match Interrupt."] pub type INT_EVENT0_ICLR_ADDR_MATCH_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_ADDR_MATCH_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_ADDR_MATCH_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_addr_match_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_ADDR_MATCH_AW :: INT_EVENT0_ICLR_ADDR_MATCH_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_addr_match_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_ADDR_MATCH_AW :: INT_EVENT0_ICLR_ADDR_MATCH_CLR) } } # [doc = "Clear UART Clear to Send Modem Interrupt. 0 = Interrupt disabled\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_CTS_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_CTS_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_CTS_CLR = 1 , } impl From < INT_EVENT0_ICLR_CTS_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_CTS_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_CTS` writer - Clear UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] pub type INT_EVENT0_ICLR_CTS_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_CTS_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_CTS_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_cts_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_CTS_AW :: INT_EVENT0_ICLR_CTS_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_cts_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_CTS_AW :: INT_EVENT0_ICLR_CTS_CLR) } } # [doc = "Clear DMA Done on RX Event Channel\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_DMA_DONE_RX_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_DMA_DONE_RX_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_DMA_DONE_RX_CLR = 1 , } impl From < INT_EVENT0_ICLR_DMA_DONE_RX_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_DMA_DONE_RX_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_DMA_DONE_RX` writer - Clear DMA Done on RX Event Channel"] pub type INT_EVENT0_ICLR_DMA_DONE_RX_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_DMA_DONE_RX_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_DMA_DONE_RX_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_dma_done_rx_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_DMA_DONE_RX_AW :: INT_EVENT0_ICLR_DMA_DONE_RX_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_dma_done_rx_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_DMA_DONE_RX_AW :: INT_EVENT0_ICLR_DMA_DONE_RX_CLR) } } # [doc = "Clear DMA Done on TX Event Channel\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_DMA_DONE_TX_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_DMA_DONE_TX_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_DMA_DONE_TX_CLR = 1 , } impl From < INT_EVENT0_ICLR_DMA_DONE_TX_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_DMA_DONE_TX_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_DMA_DONE_TX` writer - Clear DMA Done on TX Event Channel"] pub type INT_EVENT0_ICLR_DMA_DONE_TX_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_DMA_DONE_TX_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_DMA_DONE_TX_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_dma_done_tx_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_DMA_DONE_TX_AW :: INT_EVENT0_ICLR_DMA_DONE_TX_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_dma_done_tx_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_DMA_DONE_TX_AW :: INT_EVENT0_ICLR_DMA_DONE_TX_CLR) } } # [doc = "Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_NERR_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_NERR_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_NERR_CLR = 1 , } impl From < INT_EVENT0_ICLR_NERR_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_NERR_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_NERR` writer - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] pub type INT_EVENT0_ICLR_NERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_NERR_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_NERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_nerr_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_NERR_AW :: INT_EVENT0_ICLR_NERR_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_nerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_NERR_AW :: INT_EVENT0_ICLR_NERR_CLR) } } impl W { # [doc = "Bit 0 - Clear UARTOUT Receive Time-Out Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iclr_rtout (& mut self) -> INT_EVENT0_ICLR_RTOUT_W < INT_EVENT0_ICLR_SPEC , 0 > { INT_EVENT0_ICLR_RTOUT_W :: new (self) } # [doc = "Bit 1 - Clear UART Framing Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iclr_frmerr (& mut self) -> INT_EVENT0_ICLR_FRMERR_W < INT_EVENT0_ICLR_SPEC , 1 > { INT_EVENT0_ICLR_FRMERR_W :: new (self) } # [doc = "Bit 2 - Clear UART Parity Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iclr_parerr (& mut self) -> INT_EVENT0_ICLR_PARERR_W < INT_EVENT0_ICLR_SPEC , 2 > { INT_EVENT0_ICLR_PARERR_W :: new (self) } # [doc = "Bit 3 - Clear UART Break Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iclr_brkerr (& mut self) -> INT_EVENT0_ICLR_BRKERR_W < INT_EVENT0_ICLR_SPEC , 3 > { INT_EVENT0_ICLR_BRKERR_W :: new (self) } # [doc = "Bit 4 - Clear UART Receive Overrun Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iclr_ovrerr (& mut self) -> INT_EVENT0_ICLR_OVRERR_W < INT_EVENT0_ICLR_SPEC , 4 > { INT_EVENT0_ICLR_OVRERR_W :: new (self) } # [doc = "Bit 5 - Clear Negative Edge on UARTxRXD Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iclr_rxne (& mut self) -> INT_EVENT0_ICLR_RXNE_W < INT_EVENT0_ICLR_SPEC , 5 > { INT_EVENT0_ICLR_RXNE_W :: new (self) } # [doc = "Bit 6 - Clear Positive Edge on UARTxRXD Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iclr_rxpe (& mut self) -> INT_EVENT0_ICLR_RXPE_W < INT_EVENT0_ICLR_SPEC , 6 > { INT_EVENT0_ICLR_RXPE_W :: new (self) } # [doc = "Bit 7 - Clear LIN Capture 0 / Match Interrupt ."] # [inline (always)] # [must_use] pub fn int_event0_iclr_linc0 (& mut self) -> INT_EVENT0_ICLR_LINC0_W < INT_EVENT0_ICLR_SPEC , 7 > { INT_EVENT0_ICLR_LINC0_W :: new (self) } # [doc = "Bit 8 - Clear LIN Capture 1 Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iclr_linc1 (& mut self) -> INT_EVENT0_ICLR_LINC1_W < INT_EVENT0_ICLR_SPEC , 8 > { INT_EVENT0_ICLR_LINC1_W :: new (self) } # [doc = "Bit 9 - Clear LIN Hardware Counter Overflow Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iclr_linovf (& mut self) -> INT_EVENT0_ICLR_LINOVF_W < INT_EVENT0_ICLR_SPEC , 9 > { INT_EVENT0_ICLR_LINOVF_W :: new (self) } # [doc = "Bit 10 - Clear UART Receive Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iclr_rxint (& mut self) -> INT_EVENT0_ICLR_RXINT_W < INT_EVENT0_ICLR_SPEC , 10 > { INT_EVENT0_ICLR_RXINT_W :: new (self) } # [doc = "Bit 11 - Clear UART Transmit Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iclr_txint (& mut self) -> INT_EVENT0_ICLR_TXINT_W < INT_EVENT0_ICLR_SPEC , 11 > { INT_EVENT0_ICLR_TXINT_W :: new (self) } # [doc = "Bit 12 - Clear UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] # [inline (always)] # [must_use] pub fn int_event0_iclr_eot (& mut self) -> INT_EVENT0_ICLR_EOT_W < INT_EVENT0_ICLR_SPEC , 12 > { INT_EVENT0_ICLR_EOT_W :: new (self) } # [doc = "Bit 13 - Clear Address Match Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iclr_addr_match (& mut self) -> INT_EVENT0_ICLR_ADDR_MATCH_W <'_,  INT_EVENT0_ICLR_SPEC , 13 > { INT_EVENT0_ICLR_ADDR_MATCH_W :: new (self) } # [doc = "Bit 14 - Clear UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] # [inline (always)] # [must_use] pub fn int_event0_iclr_cts (& mut self) -> INT_EVENT0_ICLR_CTS_W < INT_EVENT0_ICLR_SPEC , 14 > { INT_EVENT0_ICLR_CTS_W :: new (self) } # [doc = "Bit 15 - Clear DMA Done on RX Event Channel"] # [inline (always)] # [must_use] pub fn int_event0_iclr_dma_done_rx (& mut self) -> INT_EVENT0_ICLR_DMA_DONE_RX_W < INT_EVENT0_ICLR_SPEC , 15 > { INT_EVENT0_ICLR_DMA_DONE_RX_W :: new (self) } # [doc = "Bit 16 - Clear DMA Done on TX Event Channel"] # [inline (always)] # [must_use] pub fn int_event0_iclr_dma_done_tx (& mut self) -> INT_EVENT0_ICLR_DMA_DONE_TX_W < INT_EVENT0_ICLR_SPEC , 16 > { INT_EVENT0_ICLR_DMA_DONE_TX_W :: new (self) } # [doc = "Bit 17 - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] # [inline (always)] # [must_use] pub fn int_event0_iclr_nerr (& mut self) -> INT_EVENT0_ICLR_NERR_W < INT_EVENT0_ICLR_SPEC , 17 > { INT_EVENT0_ICLR_NERR_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Interrupt clear\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_event0_iclr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct INT_EVENT0_ICLR_SPEC ; impl crate :: RegisterSpec for INT_EVENT0_ICLR_SPEC { type Ux = u32 ; } # [doc = "`write(|w| ..)` method takes [`int_event0_iclr::W`](W) writer structure"] impl crate :: Writable for INT_EVENT0_ICLR_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets INT_EVENT0_ICLR to value 0"] impl crate :: Resettable for INT_EVENT0_ICLR_SPEC { const RESET_VALUE : Self :: Ux = 0 ; }
[INFO] [stdout]   |                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                 +++
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing
[INFO] [stdout]  --> src/uart0/int_event0_iclr.rs:1:25088
[INFO] [stdout]   |
[INFO] [stdout] 1 | ...ent0_iclr_cts (& mut self) -> INT_EVENT0_ICLR_CTS_W < INT_EVENT0_ICLR_SPEC , 14 > { INT_EVENT0_ICLR_CTS_W :: new (self) } # [doc =...
[INFO] [stdout]   |                   ^^^^^^^^^^     ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here
[INFO] [stdout]   |                   |
[INFO] [stdout]   |                   the lifetime is elided here
[INFO] [stdout]   |
[INFO] [stdout]   = help: the same lifetime is referred to in inconsistent ways, making the signature confusing
[INFO] [stdout] help: use `'_` for type paths
[INFO] [stdout]   |
[INFO] [stdout] 1 | # [doc = "Register `INT_EVENT0_ICLR` writer"] pub type W = crate :: W < INT_EVENT0_ICLR_SPEC > ; # [doc = "Clear UARTOUT Receive Time-Out Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_RTOUT_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_RTOUT_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_RTOUT_CLR = 1 , } impl From < INT_EVENT0_ICLR_RTOUT_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_RTOUT_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_RTOUT` writer - Clear UARTOUT Receive Time-Out Interrupt."] pub type INT_EVENT0_ICLR_RTOUT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_RTOUT_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_RTOUT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_rtout_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_RTOUT_AW :: INT_EVENT0_ICLR_RTOUT_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_rtout_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_RTOUT_AW :: INT_EVENT0_ICLR_RTOUT_CLR) } } # [doc = "Clear UART Framing Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_FRMERR_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_FRMERR_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_FRMERR_CLR = 1 , } impl From < INT_EVENT0_ICLR_FRMERR_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_FRMERR_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_FRMERR` writer - Clear UART Framing Error Interrupt."] pub type INT_EVENT0_ICLR_FRMERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_FRMERR_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_FRMERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_frmerr_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_FRMERR_AW :: INT_EVENT0_ICLR_FRMERR_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_frmerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_FRMERR_AW :: INT_EVENT0_ICLR_FRMERR_CLR) } } # [doc = "Clear UART Parity Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_PARERR_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_PARERR_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_PARERR_CLR = 1 , } impl From < INT_EVENT0_ICLR_PARERR_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_PARERR_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_PARERR` writer - Clear UART Parity Error Interrupt."] pub type INT_EVENT0_ICLR_PARERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_PARERR_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_PARERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_parerr_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_PARERR_AW :: INT_EVENT0_ICLR_PARERR_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_parerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_PARERR_AW :: INT_EVENT0_ICLR_PARERR_CLR) } } # [doc = "Clear UART Break Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_BRKERR_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_BRKERR_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_BRKERR_CLR = 1 , } impl From < INT_EVENT0_ICLR_BRKERR_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_BRKERR_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_BRKERR` writer - Clear UART Break Error Interrupt."] pub type INT_EVENT0_ICLR_BRKERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_BRKERR_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_BRKERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_brkerr_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_BRKERR_AW :: INT_EVENT0_ICLR_BRKERR_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_brkerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_BRKERR_AW :: INT_EVENT0_ICLR_BRKERR_CLR) } } # [doc = "Clear UART Receive Overrun Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_OVRERR_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_OVRERR_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_OVRERR_CLR = 1 , } impl From < INT_EVENT0_ICLR_OVRERR_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_OVRERR_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_OVRERR` writer - Clear UART Receive Overrun Error Interrupt."] pub type INT_EVENT0_ICLR_OVRERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_OVRERR_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_OVRERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_ovrerr_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_OVRERR_AW :: INT_EVENT0_ICLR_OVRERR_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_ovrerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_OVRERR_AW :: INT_EVENT0_ICLR_OVRERR_CLR) } } # [doc = "Clear Negative Edge on UARTxRXD Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_RXNE_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_RXNE_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_RXNE_CLR = 1 , } impl From < INT_EVENT0_ICLR_RXNE_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_RXNE_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_RXNE` writer - Clear Negative Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_ICLR_RXNE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_RXNE_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_RXNE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_rxne_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_RXNE_AW :: INT_EVENT0_ICLR_RXNE_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_rxne_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_RXNE_AW :: INT_EVENT0_ICLR_RXNE_CLR) } } # [doc = "Clear Positive Edge on UARTxRXD Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_RXPE_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_RXPE_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_RXPE_CLR = 1 , } impl From < INT_EVENT0_ICLR_RXPE_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_RXPE_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_RXPE` writer - Clear Positive Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_ICLR_RXPE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_RXPE_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_RXPE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_rxpe_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_RXPE_AW :: INT_EVENT0_ICLR_RXPE_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_rxpe_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_RXPE_AW :: INT_EVENT0_ICLR_RXPE_CLR) } } # [doc = "Clear LIN Capture 0 / Match Interrupt .\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_LINC0_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_LINC0_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_LINC0_CLR = 1 , } impl From < INT_EVENT0_ICLR_LINC0_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_LINC0_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_LINC0` writer - Clear LIN Capture 0 / Match Interrupt ."] pub type INT_EVENT0_ICLR_LINC0_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_LINC0_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_LINC0_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_linc0_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_LINC0_AW :: INT_EVENT0_ICLR_LINC0_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_linc0_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_LINC0_AW :: INT_EVENT0_ICLR_LINC0_CLR) } } # [doc = "Clear LIN Capture 1 Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_LINC1_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_LINC1_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_LINC1_CLR = 1 , } impl From < INT_EVENT0_ICLR_LINC1_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_LINC1_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_LINC1` writer - Clear LIN Capture 1 Interrupt."] pub type INT_EVENT0_ICLR_LINC1_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_LINC1_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_LINC1_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_linc1_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_LINC1_AW :: INT_EVENT0_ICLR_LINC1_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_linc1_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_LINC1_AW :: INT_EVENT0_ICLR_LINC1_CLR) } } # [doc = "Clear LIN Hardware Counter Overflow Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_LINOVF_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_LINOVF_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_LINOVF_CLR = 1 , } impl From < INT_EVENT0_ICLR_LINOVF_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_LINOVF_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_LINOVF` writer - Clear LIN Hardware Counter Overflow Interrupt."] pub type INT_EVENT0_ICLR_LINOVF_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_LINOVF_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_LINOVF_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_linovf_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_LINOVF_AW :: INT_EVENT0_ICLR_LINOVF_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_linovf_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_LINOVF_AW :: INT_EVENT0_ICLR_LINOVF_CLR) } } # [doc = "Clear UART Receive Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_RXINT_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_RXINT_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_RXINT_CLR = 1 , } impl From < INT_EVENT0_ICLR_RXINT_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_RXINT_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_RXINT` writer - Clear UART Receive Interrupt."] pub type INT_EVENT0_ICLR_RXINT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_RXINT_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_RXINT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_rxint_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_RXINT_AW :: INT_EVENT0_ICLR_RXINT_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_rxint_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_RXINT_AW :: INT_EVENT0_ICLR_RXINT_CLR) } } # [doc = "Clear UART Transmit Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_TXINT_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_TXINT_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_TXINT_CLR = 1 , } impl From < INT_EVENT0_ICLR_TXINT_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_TXINT_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_TXINT` writer - Clear UART Transmit Interrupt."] pub type INT_EVENT0_ICLR_TXINT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_TXINT_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_TXINT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_txint_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_TXINT_AW :: INT_EVENT0_ICLR_TXINT_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_txint_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_TXINT_AW :: INT_EVENT0_ICLR_TXINT_CLR) } } # [doc = "Clear UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_EOT_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_EOT_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_EOT_CLR = 1 , } impl From < INT_EVENT0_ICLR_EOT_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_EOT_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_EOT` writer - Clear UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] pub type INT_EVENT0_ICLR_EOT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_EOT_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_EOT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_eot_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_EOT_AW :: INT_EVENT0_ICLR_EOT_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_eot_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_EOT_AW :: INT_EVENT0_ICLR_EOT_CLR) } } # [doc = "Clear Address Match Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_ADDR_MATCH_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_ADDR_MATCH_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_ADDR_MATCH_CLR = 1 , } impl From < INT_EVENT0_ICLR_ADDR_MATCH_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_ADDR_MATCH_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_ADDR_MATCH` writer - Clear Address Match Interrupt."] pub type INT_EVENT0_ICLR_ADDR_MATCH_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_ADDR_MATCH_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_ADDR_MATCH_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_addr_match_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_ADDR_MATCH_AW :: INT_EVENT0_ICLR_ADDR_MATCH_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_addr_match_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_ADDR_MATCH_AW :: INT_EVENT0_ICLR_ADDR_MATCH_CLR) } } # [doc = "Clear UART Clear to Send Modem Interrupt. 0 = Interrupt disabled\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_CTS_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_CTS_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_CTS_CLR = 1 , } impl From < INT_EVENT0_ICLR_CTS_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_CTS_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_CTS` writer - Clear UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] pub type INT_EVENT0_ICLR_CTS_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_CTS_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_CTS_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_cts_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_CTS_AW :: INT_EVENT0_ICLR_CTS_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_cts_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_CTS_AW :: INT_EVENT0_ICLR_CTS_CLR) } } # [doc = "Clear DMA Done on RX Event Channel\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_DMA_DONE_RX_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_DMA_DONE_RX_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_DMA_DONE_RX_CLR = 1 , } impl From < INT_EVENT0_ICLR_DMA_DONE_RX_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_DMA_DONE_RX_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_DMA_DONE_RX` writer - Clear DMA Done on RX Event Channel"] pub type INT_EVENT0_ICLR_DMA_DONE_RX_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_DMA_DONE_RX_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_DMA_DONE_RX_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_dma_done_rx_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_DMA_DONE_RX_AW :: INT_EVENT0_ICLR_DMA_DONE_RX_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_dma_done_rx_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_DMA_DONE_RX_AW :: INT_EVENT0_ICLR_DMA_DONE_RX_CLR) } } # [doc = "Clear DMA Done on TX Event Channel\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_DMA_DONE_TX_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_DMA_DONE_TX_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_DMA_DONE_TX_CLR = 1 , } impl From < INT_EVENT0_ICLR_DMA_DONE_TX_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_DMA_DONE_TX_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_DMA_DONE_TX` writer - Clear DMA Done on TX Event Channel"] pub type INT_EVENT0_ICLR_DMA_DONE_TX_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_DMA_DONE_TX_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_DMA_DONE_TX_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_dma_done_tx_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_DMA_DONE_TX_AW :: INT_EVENT0_ICLR_DMA_DONE_TX_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_dma_done_tx_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_DMA_DONE_TX_AW :: INT_EVENT0_ICLR_DMA_DONE_TX_CLR) } } # [doc = "Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_NERR_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_NERR_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_NERR_CLR = 1 , } impl From < INT_EVENT0_ICLR_NERR_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_NERR_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_NERR` writer - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] pub type INT_EVENT0_ICLR_NERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_NERR_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_NERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_nerr_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_NERR_AW :: INT_EVENT0_ICLR_NERR_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_nerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_NERR_AW :: INT_EVENT0_ICLR_NERR_CLR) } } impl W { # [doc = "Bit 0 - Clear UARTOUT Receive Time-Out Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iclr_rtout (& mut self) -> INT_EVENT0_ICLR_RTOUT_W < INT_EVENT0_ICLR_SPEC , 0 > { INT_EVENT0_ICLR_RTOUT_W :: new (self) } # [doc = "Bit 1 - Clear UART Framing Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iclr_frmerr (& mut self) -> INT_EVENT0_ICLR_FRMERR_W < INT_EVENT0_ICLR_SPEC , 1 > { INT_EVENT0_ICLR_FRMERR_W :: new (self) } # [doc = "Bit 2 - Clear UART Parity Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iclr_parerr (& mut self) -> INT_EVENT0_ICLR_PARERR_W < INT_EVENT0_ICLR_SPEC , 2 > { INT_EVENT0_ICLR_PARERR_W :: new (self) } # [doc = "Bit 3 - Clear UART Break Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iclr_brkerr (& mut self) -> INT_EVENT0_ICLR_BRKERR_W < INT_EVENT0_ICLR_SPEC , 3 > { INT_EVENT0_ICLR_BRKERR_W :: new (self) } # [doc = "Bit 4 - Clear UART Receive Overrun Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iclr_ovrerr (& mut self) -> INT_EVENT0_ICLR_OVRERR_W < INT_EVENT0_ICLR_SPEC , 4 > { INT_EVENT0_ICLR_OVRERR_W :: new (self) } # [doc = "Bit 5 - Clear Negative Edge on UARTxRXD Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iclr_rxne (& mut self) -> INT_EVENT0_ICLR_RXNE_W < INT_EVENT0_ICLR_SPEC , 5 > { INT_EVENT0_ICLR_RXNE_W :: new (self) } # [doc = "Bit 6 - Clear Positive Edge on UARTxRXD Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iclr_rxpe (& mut self) -> INT_EVENT0_ICLR_RXPE_W < INT_EVENT0_ICLR_SPEC , 6 > { INT_EVENT0_ICLR_RXPE_W :: new (self) } # [doc = "Bit 7 - Clear LIN Capture 0 / Match Interrupt ."] # [inline (always)] # [must_use] pub fn int_event0_iclr_linc0 (& mut self) -> INT_EVENT0_ICLR_LINC0_W < INT_EVENT0_ICLR_SPEC , 7 > { INT_EVENT0_ICLR_LINC0_W :: new (self) } # [doc = "Bit 8 - Clear LIN Capture 1 Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iclr_linc1 (& mut self) -> INT_EVENT0_ICLR_LINC1_W < INT_EVENT0_ICLR_SPEC , 8 > { INT_EVENT0_ICLR_LINC1_W :: new (self) } # [doc = "Bit 9 - Clear LIN Hardware Counter Overflow Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iclr_linovf (& mut self) -> INT_EVENT0_ICLR_LINOVF_W < INT_EVENT0_ICLR_SPEC , 9 > { INT_EVENT0_ICLR_LINOVF_W :: new (self) } # [doc = "Bit 10 - Clear UART Receive Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iclr_rxint (& mut self) -> INT_EVENT0_ICLR_RXINT_W < INT_EVENT0_ICLR_SPEC , 10 > { INT_EVENT0_ICLR_RXINT_W :: new (self) } # [doc = "Bit 11 - Clear UART Transmit Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iclr_txint (& mut self) -> INT_EVENT0_ICLR_TXINT_W < INT_EVENT0_ICLR_SPEC , 11 > { INT_EVENT0_ICLR_TXINT_W :: new (self) } # [doc = "Bit 12 - Clear UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] # [inline (always)] # [must_use] pub fn int_event0_iclr_eot (& mut self) -> INT_EVENT0_ICLR_EOT_W < INT_EVENT0_ICLR_SPEC , 12 > { INT_EVENT0_ICLR_EOT_W :: new (self) } # [doc = "Bit 13 - Clear Address Match Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iclr_addr_match (& mut self) -> INT_EVENT0_ICLR_ADDR_MATCH_W < INT_EVENT0_ICLR_SPEC , 13 > { INT_EVENT0_ICLR_ADDR_MATCH_W :: new (self) } # [doc = "Bit 14 - Clear UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] # [inline (always)] # [must_use] pub fn int_event0_iclr_cts (& mut self) -> INT_EVENT0_ICLR_CTS_W <'_,  INT_EVENT0_ICLR_SPEC , 14 > { INT_EVENT0_ICLR_CTS_W :: new (self) } # [doc = "Bit 15 - Clear DMA Done on RX Event Channel"] # [inline (always)] # [must_use] pub fn int_event0_iclr_dma_done_rx (& mut self) -> INT_EVENT0_ICLR_DMA_DONE_RX_W < INT_EVENT0_ICLR_SPEC , 15 > { INT_EVENT0_ICLR_DMA_DONE_RX_W :: new (self) } # [doc = "Bit 16 - Clear DMA Done on TX Event Channel"] # [inline (always)] # [must_use] pub fn int_event0_iclr_dma_done_tx (& mut self) -> INT_EVENT0_ICLR_DMA_DONE_TX_W < INT_EVENT0_ICLR_SPEC , 16 > { INT_EVENT0_ICLR_DMA_DONE_TX_W :: new (self) } # [doc = "Bit 17 - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] # [inline (always)] # [must_use] pub fn int_event0_iclr_nerr (& mut self) -> INT_EVENT0_ICLR_NERR_W < INT_EVENT0_ICLR_SPEC , 17 > { INT_EVENT0_ICLR_NERR_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Interrupt clear\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_event0_iclr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct INT_EVENT0_ICLR_SPEC ; impl crate :: RegisterSpec for INT_EVENT0_ICLR_SPEC { type Ux = u32 ; } # [doc = "`write(|w| ..)` method takes [`int_event0_iclr::W`](W) writer structure"] impl crate :: Writable for INT_EVENT0_ICLR_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets INT_EVENT0_ICLR to value 0"] impl crate :: Resettable for INT_EVENT0_ICLR_SPEC { const RESET_VALUE : Self :: Ux = 0 ; }
[INFO] [stdout]   |                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                      +++
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing
[INFO] [stdout]  --> src/uart0/int_event0_imask.rs:1:41449
[INFO] [stdout]   |
[INFO] [stdout] 1 | ...mask_ovrerr (& mut self) -> INT_EVENT0_IMASK_OVRERR_W < INT_EVENT0_IMASK_SPEC , 4 > { INT_EVENT0_IMASK_OVRERR_W :: new (self) } # ...
[INFO] [stdout]   |                 ^^^^^^^^^^     ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here
[INFO] [stdout]   |                 |
[INFO] [stdout]   |                 the lifetime is elided here
[INFO] [stdout]   |
[INFO] [stdout]   = help: the same lifetime is referred to in inconsistent ways, making the signature confusing
[INFO] [stdout] help: use `'_` for type paths
[INFO] [stdout]   |
[INFO] [stdout] 1 | # [doc = "Register `INT_EVENT0_IMASK` reader"] pub type R = crate :: R < INT_EVENT0_IMASK_SPEC > ; # [doc = "Register `INT_EVENT0_IMASK` writer"] pub type W = crate :: W < INT_EVENT0_IMASK_SPEC > ; # [doc = "Field `INT_EVENT0_IMASK_RTOUT` reader - Enable UARTOUT Receive Time-Out Interrupt."] pub type INT_EVENT0_IMASK_RTOUT_R = crate :: BitReader < INT_EVENT0_IMASK_RTOUT_A > ; # [doc = "Enable UARTOUT Receive Time-Out Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_RTOUT_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_RTOUT_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_RTOUT_SET = 1 , } impl From < INT_EVENT0_IMASK_RTOUT_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_RTOUT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_RTOUT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_RTOUT_A { match self . bits { false => INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_CLR , true => INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_rtout_clr (& self) -> bool { * self == INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_rtout_set (& self) -> bool { * self == INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_SET } } # [doc = "Field `INT_EVENT0_IMASK_RTOUT` writer - Enable UARTOUT Receive Time-Out Interrupt."] pub type INT_EVENT0_IMASK_RTOUT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_RTOUT_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_RTOUT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_rtout_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_rtout_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_SET) } } # [doc = "Field `INT_EVENT0_IMASK_FRMERR` reader - Enable UART Framing Error Interrupt."] pub type INT_EVENT0_IMASK_FRMERR_R = crate :: BitReader < INT_EVENT0_IMASK_FRMERR_A > ; # [doc = "Enable UART Framing Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_FRMERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_FRMERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_FRMERR_SET = 1 , } impl From < INT_EVENT0_IMASK_FRMERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_FRMERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_FRMERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_FRMERR_A { match self . bits { false => INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_CLR , true => INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_frmerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_frmerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_FRMERR` writer - Enable UART Framing Error Interrupt."] pub type INT_EVENT0_IMASK_FRMERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_FRMERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_FRMERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_frmerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_frmerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_SET) } } # [doc = "Field `INT_EVENT0_IMASK_PARERR` reader - Enable UART Parity Error Interrupt."] pub type INT_EVENT0_IMASK_PARERR_R = crate :: BitReader < INT_EVENT0_IMASK_PARERR_A > ; # [doc = "Enable UART Parity Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_PARERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_PARERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_PARERR_SET = 1 , } impl From < INT_EVENT0_IMASK_PARERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_PARERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_PARERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_PARERR_A { match self . bits { false => INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_CLR , true => INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_parerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_parerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_PARERR` writer - Enable UART Parity Error Interrupt."] pub type INT_EVENT0_IMASK_PARERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_PARERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_PARERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_parerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_parerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_SET) } } # [doc = "Field `INT_EVENT0_IMASK_BRKERR` reader - Enable UART Break Error Interrupt."] pub type INT_EVENT0_IMASK_BRKERR_R = crate :: BitReader < INT_EVENT0_IMASK_BRKERR_A > ; # [doc = "Enable UART Break Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_BRKERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_BRKERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_BRKERR_SET = 1 , } impl From < INT_EVENT0_IMASK_BRKERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_BRKERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_BRKERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_BRKERR_A { match self . bits { false => INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_CLR , true => INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_brkerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_brkerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_BRKERR` writer - Enable UART Break Error Interrupt."] pub type INT_EVENT0_IMASK_BRKERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_BRKERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_BRKERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_brkerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_brkerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_SET) } } # [doc = "Field `INT_EVENT0_IMASK_OVRERR` reader - Enable UART Receive Overrun Error Interrupt."] pub type INT_EVENT0_IMASK_OVRERR_R = crate :: BitReader < INT_EVENT0_IMASK_OVRERR_A > ; # [doc = "Enable UART Receive Overrun Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_OVRERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_OVRERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_OVRERR_SET = 1 , } impl From < INT_EVENT0_IMASK_OVRERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_OVRERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_OVRERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_OVRERR_A { match self . bits { false => INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_CLR , true => INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_ovrerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_ovrerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_OVRERR` writer - Enable UART Receive Overrun Error Interrupt."] pub type INT_EVENT0_IMASK_OVRERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_OVRERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_OVRERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_ovrerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_ovrerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_SET) } } # [doc = "Field `INT_EVENT0_IMASK_RXNE` reader - Enable Negative Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_IMASK_RXNE_R = crate :: BitReader < INT_EVENT0_IMASK_RXNE_A > ; # [doc = "Enable Negative Edge on UARTxRXD Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_RXNE_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_RXNE_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_RXNE_SET = 1 , } impl From < INT_EVENT0_IMASK_RXNE_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_RXNE_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_RXNE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_RXNE_A { match self . bits { false => INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_CLR , true => INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_rxne_clr (& self) -> bool { * self == INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_rxne_set (& self) -> bool { * self == INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_SET } } # [doc = "Field `INT_EVENT0_IMASK_RXNE` writer - Enable Negative Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_IMASK_RXNE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_RXNE_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_RXNE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_rxne_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_rxne_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_SET) } } # [doc = "Field `INT_EVENT0_IMASK_RXPE` reader - Enable Positive Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_IMASK_RXPE_R = crate :: BitReader < INT_EVENT0_IMASK_RXPE_A > ; # [doc = "Enable Positive Edge on UARTxRXD Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_RXPE_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_RXPE_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_RXPE_SET = 1 , } impl From < INT_EVENT0_IMASK_RXPE_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_RXPE_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_RXPE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_RXPE_A { match self . bits { false => INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_CLR , true => INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_rxpe_clr (& self) -> bool { * self == INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_rxpe_set (& self) -> bool { * self == INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_SET } } # [doc = "Field `INT_EVENT0_IMASK_RXPE` writer - Enable Positive Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_IMASK_RXPE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_RXPE_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_RXPE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_rxpe_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_rxpe_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_SET) } } # [doc = "Field `INT_EVENT0_IMASK_LINC0` reader - Enable LIN Capture 0 / Match Interrupt ."] pub type INT_EVENT0_IMASK_LINC0_R = crate :: BitReader < INT_EVENT0_IMASK_LINC0_A > ; # [doc = "Enable LIN Capture 0 / Match Interrupt .\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_LINC0_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_LINC0_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_LINC0_SET = 1 , } impl From < INT_EVENT0_IMASK_LINC0_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_LINC0_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_LINC0_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_LINC0_A { match self . bits { false => INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_CLR , true => INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_linc0_clr (& self) -> bool { * self == INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_linc0_set (& self) -> bool { * self == INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_SET } } # [doc = "Field `INT_EVENT0_IMASK_LINC0` writer - Enable LIN Capture 0 / Match Interrupt ."] pub type INT_EVENT0_IMASK_LINC0_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_LINC0_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_LINC0_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_linc0_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_linc0_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_SET) } } # [doc = "Field `INT_EVENT0_IMASK_LINC1` reader - Enable LIN Capture 1 Interrupt."] pub type INT_EVENT0_IMASK_LINC1_R = crate :: BitReader < INT_EVENT0_IMASK_LINC1_A > ; # [doc = "Enable LIN Capture 1 Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_LINC1_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_LINC1_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_LINC1_SET = 1 , } impl From < INT_EVENT0_IMASK_LINC1_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_LINC1_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_LINC1_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_LINC1_A { match self . bits { false => INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_CLR , true => INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_linc1_clr (& self) -> bool { * self == INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_linc1_set (& self) -> bool { * self == INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_SET } } # [doc = "Field `INT_EVENT0_IMASK_LINC1` writer - Enable LIN Capture 1 Interrupt."] pub type INT_EVENT0_IMASK_LINC1_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_LINC1_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_LINC1_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_linc1_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_linc1_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_SET) } } # [doc = "Field `INT_EVENT0_IMASK_LINOVF` reader - Enable LIN Hardware Counter Overflow Interrupt."] pub type INT_EVENT0_IMASK_LINOVF_R = crate :: BitReader < INT_EVENT0_IMASK_LINOVF_A > ; # [doc = "Enable LIN Hardware Counter Overflow Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_LINOVF_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_LINOVF_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_LINOVF_SET = 1 , } impl From < INT_EVENT0_IMASK_LINOVF_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_LINOVF_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_LINOVF_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_LINOVF_A { match self . bits { false => INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_CLR , true => INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_linovf_clr (& self) -> bool { * self == INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_linovf_set (& self) -> bool { * self == INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_SET } } # [doc = "Field `INT_EVENT0_IMASK_LINOVF` writer - Enable LIN Hardware Counter Overflow Interrupt."] pub type INT_EVENT0_IMASK_LINOVF_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_LINOVF_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_LINOVF_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_linovf_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_linovf_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_SET) } } # [doc = "Field `INT_EVENT0_IMASK_RXINT` reader - Enable UART Receive Interrupt."] pub type INT_EVENT0_IMASK_RXINT_R = crate :: BitReader < INT_EVENT0_IMASK_RXINT_A > ; # [doc = "Enable UART Receive Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_RXINT_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_RXINT_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_RXINT_SET = 1 , } impl From < INT_EVENT0_IMASK_RXINT_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_RXINT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_RXINT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_RXINT_A { match self . bits { false => INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_CLR , true => INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_rxint_clr (& self) -> bool { * self == INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_rxint_set (& self) -> bool { * self == INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_SET } } # [doc = "Field `INT_EVENT0_IMASK_RXINT` writer - Enable UART Receive Interrupt."] pub type INT_EVENT0_IMASK_RXINT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_RXINT_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_RXINT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_rxint_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_rxint_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_SET) } } # [doc = "Field `INT_EVENT0_IMASK_TXINT` reader - Enable UART Transmit Interrupt."] pub type INT_EVENT0_IMASK_TXINT_R = crate :: BitReader < INT_EVENT0_IMASK_TXINT_A > ; # [doc = "Enable UART Transmit Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_TXINT_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_TXINT_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_TXINT_SET = 1 , } impl From < INT_EVENT0_IMASK_TXINT_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_TXINT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_TXINT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_TXINT_A { match self . bits { false => INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_CLR , true => INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_txint_clr (& self) -> bool { * self == INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_txint_set (& self) -> bool { * self == INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_SET } } # [doc = "Field `INT_EVENT0_IMASK_TXINT` writer - Enable UART Transmit Interrupt."] pub type INT_EVENT0_IMASK_TXINT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_TXINT_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_TXINT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_txint_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_txint_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_SET) } } # [doc = "Field `INT_EVENT0_IMASK_EOT` reader - Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] pub type INT_EVENT0_IMASK_EOT_R = crate :: BitReader < INT_EVENT0_IMASK_EOT_A > ; # [doc = "Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_EOT_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_EOT_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_EOT_SET = 1 , } impl From < INT_EVENT0_IMASK_EOT_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_EOT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_EOT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_EOT_A { match self . bits { false => INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_CLR , true => INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_eot_clr (& self) -> bool { * self == INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_eot_set (& self) -> bool { * self == INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_SET } } # [doc = "Field `INT_EVENT0_IMASK_EOT` writer - Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] pub type INT_EVENT0_IMASK_EOT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_EOT_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_EOT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_eot_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_eot_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_SET) } } # [doc = "Field `INT_EVENT0_IMASK_ADDR_MATCH` reader - Enable Address Match Interrupt."] pub type INT_EVENT0_IMASK_ADDR_MATCH_R = crate :: BitReader < INT_EVENT0_IMASK_ADDR_MATCH_A > ; # [doc = "Enable Address Match Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_ADDR_MATCH_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_ADDR_MATCH_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_ADDR_MATCH_SET = 1 , } impl From < INT_EVENT0_IMASK_ADDR_MATCH_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_ADDR_MATCH_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_ADDR_MATCH_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_ADDR_MATCH_A { match self . bits { false => INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_CLR , true => INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_addr_match_clr (& self) -> bool { * self == INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_addr_match_set (& self) -> bool { * self == INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_SET } } # [doc = "Field `INT_EVENT0_IMASK_ADDR_MATCH` writer - Enable Address Match Interrupt."] pub type INT_EVENT0_IMASK_ADDR_MATCH_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_ADDR_MATCH_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_ADDR_MATCH_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_addr_match_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_addr_match_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_SET) } } # [doc = "Field `INT_EVENT0_IMASK_CTS` reader - Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] pub type INT_EVENT0_IMASK_CTS_R = crate :: BitReader < INT_EVENT0_IMASK_CTS_A > ; # [doc = "Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_CTS_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_CTS_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_CTS_SET = 1 , } impl From < INT_EVENT0_IMASK_CTS_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_CTS_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_CTS_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_CTS_A { match self . bits { false => INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_CLR , true => INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_cts_clr (& self) -> bool { * self == INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_cts_set (& self) -> bool { * self == INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_SET } } # [doc = "Field `INT_EVENT0_IMASK_CTS` writer - Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] pub type INT_EVENT0_IMASK_CTS_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_CTS_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_CTS_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_cts_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_cts_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DMA_DONE_RX` reader - Enable DMA Done on RX Event Channel"] pub type INT_EVENT0_IMASK_DMA_DONE_RX_R = crate :: BitReader < INT_EVENT0_IMASK_DMA_DONE_RX_A > ; # [doc = "Enable DMA Done on RX Event Channel\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DMA_DONE_RX_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DMA_DONE_RX_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DMA_DONE_RX_SET = 1 , } impl From < INT_EVENT0_IMASK_DMA_DONE_RX_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DMA_DONE_RX_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DMA_DONE_RX_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DMA_DONE_RX_A { match self . bits { false => INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_CLR , true => INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dma_done_rx_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dma_done_rx_set (& self) -> bool { * self == INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_SET } } # [doc = "Field `INT_EVENT0_IMASK_DMA_DONE_RX` writer - Enable DMA Done on RX Event Channel"] pub type INT_EVENT0_IMASK_DMA_DONE_RX_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DMA_DONE_RX_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DMA_DONE_RX_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dma_done_rx_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dma_done_rx_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DMA_DONE_TX` reader - Enable DMA Done on TX Event Channel"] pub type INT_EVENT0_IMASK_DMA_DONE_TX_R = crate :: BitReader < INT_EVENT0_IMASK_DMA_DONE_TX_A > ; # [doc = "Enable DMA Done on TX Event Channel\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DMA_DONE_TX_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DMA_DONE_TX_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DMA_DONE_TX_SET = 1 , } impl From < INT_EVENT0_IMASK_DMA_DONE_TX_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DMA_DONE_TX_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DMA_DONE_TX_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DMA_DONE_TX_A { match self . bits { false => INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_CLR , true => INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dma_done_tx_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dma_done_tx_set (& self) -> bool { * self == INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_SET } } # [doc = "Field `INT_EVENT0_IMASK_DMA_DONE_TX` writer - Enable DMA Done on TX Event Channel"] pub type INT_EVENT0_IMASK_DMA_DONE_TX_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DMA_DONE_TX_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DMA_DONE_TX_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dma_done_tx_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dma_done_tx_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_SET) } } # [doc = "Field `INT_EVENT0_IMASK_NERR` reader - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] pub type INT_EVENT0_IMASK_NERR_R = crate :: BitReader < INT_EVENT0_IMASK_NERR_A > ; # [doc = "Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_NERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_NERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_NERR_SET = 1 , } impl From < INT_EVENT0_IMASK_NERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_NERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_NERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_NERR_A { match self . bits { false => INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_CLR , true => INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_nerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_nerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_NERR` writer - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] pub type INT_EVENT0_IMASK_NERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_NERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_NERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_nerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_nerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_SET) } } impl R { # [doc = "Bit 0 - Enable UARTOUT Receive Time-Out Interrupt."] # [inline (always)] pub fn int_event0_imask_rtout (& self) -> INT_EVENT0_IMASK_RTOUT_R { INT_EVENT0_IMASK_RTOUT_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - Enable UART Framing Error Interrupt."] # [inline (always)] pub fn int_event0_imask_frmerr (& self) -> INT_EVENT0_IMASK_FRMERR_R { INT_EVENT0_IMASK_FRMERR_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - Enable UART Parity Error Interrupt."] # [inline (always)] pub fn int_event0_imask_parerr (& self) -> INT_EVENT0_IMASK_PARERR_R { INT_EVENT0_IMASK_PARERR_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - Enable UART Break Error Interrupt."] # [inline (always)] pub fn int_event0_imask_brkerr (& self) -> INT_EVENT0_IMASK_BRKERR_R { INT_EVENT0_IMASK_BRKERR_R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - Enable UART Receive Overrun Error Interrupt."] # [inline (always)] pub fn int_event0_imask_ovrerr (& self) -> INT_EVENT0_IMASK_OVRERR_R { INT_EVENT0_IMASK_OVRERR_R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - Enable Negative Edge on UARTxRXD Interrupt."] # [inline (always)] pub fn int_event0_imask_rxne (& self) -> INT_EVENT0_IMASK_RXNE_R { INT_EVENT0_IMASK_RXNE_R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - Enable Positive Edge on UARTxRXD Interrupt."] # [inline (always)] pub fn int_event0_imask_rxpe (& self) -> INT_EVENT0_IMASK_RXPE_R { INT_EVENT0_IMASK_RXPE_R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - Enable LIN Capture 0 / Match Interrupt ."] # [inline (always)] pub fn int_event0_imask_linc0 (& self) -> INT_EVENT0_IMASK_LINC0_R { INT_EVENT0_IMASK_LINC0_R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - Enable LIN Capture 1 Interrupt."] # [inline (always)] pub fn int_event0_imask_linc1 (& self) -> INT_EVENT0_IMASK_LINC1_R { INT_EVENT0_IMASK_LINC1_R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - Enable LIN Hardware Counter Overflow Interrupt."] # [inline (always)] pub fn int_event0_imask_linovf (& self) -> INT_EVENT0_IMASK_LINOVF_R { INT_EVENT0_IMASK_LINOVF_R :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - Enable UART Receive Interrupt."] # [inline (always)] pub fn int_event0_imask_rxint (& self) -> INT_EVENT0_IMASK_RXINT_R { INT_EVENT0_IMASK_RXINT_R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - Enable UART Transmit Interrupt."] # [inline (always)] pub fn int_event0_imask_txint (& self) -> INT_EVENT0_IMASK_TXINT_R { INT_EVENT0_IMASK_TXINT_R :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] # [inline (always)] pub fn int_event0_imask_eot (& self) -> INT_EVENT0_IMASK_EOT_R { INT_EVENT0_IMASK_EOT_R :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - Enable Address Match Interrupt."] # [inline (always)] pub fn int_event0_imask_addr_match (& self) -> INT_EVENT0_IMASK_ADDR_MATCH_R { INT_EVENT0_IMASK_ADDR_MATCH_R :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 14 - Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] # [inline (always)] pub fn int_event0_imask_cts (& self) -> INT_EVENT0_IMASK_CTS_R { INT_EVENT0_IMASK_CTS_R :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - Enable DMA Done on RX Event Channel"] # [inline (always)] pub fn int_event0_imask_dma_done_rx (& self) -> INT_EVENT0_IMASK_DMA_DONE_RX_R { INT_EVENT0_IMASK_DMA_DONE_RX_R :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bit 16 - Enable DMA Done on TX Event Channel"] # [inline (always)] pub fn int_event0_imask_dma_done_tx (& self) -> INT_EVENT0_IMASK_DMA_DONE_TX_R { INT_EVENT0_IMASK_DMA_DONE_TX_R :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] # [inline (always)] pub fn int_event0_imask_nerr (& self) -> INT_EVENT0_IMASK_NERR_R { INT_EVENT0_IMASK_NERR_R :: new (((self . bits >> 17) & 1) != 0) } } impl W { # [doc = "Bit 0 - Enable UARTOUT Receive Time-Out Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_rtout (& mut self) -> INT_EVENT0_IMASK_RTOUT_W < INT_EVENT0_IMASK_SPEC , 0 > { INT_EVENT0_IMASK_RTOUT_W :: new (self) } # [doc = "Bit 1 - Enable UART Framing Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_frmerr (& mut self) -> INT_EVENT0_IMASK_FRMERR_W < INT_EVENT0_IMASK_SPEC , 1 > { INT_EVENT0_IMASK_FRMERR_W :: new (self) } # [doc = "Bit 2 - Enable UART Parity Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_parerr (& mut self) -> INT_EVENT0_IMASK_PARERR_W < INT_EVENT0_IMASK_SPEC , 2 > { INT_EVENT0_IMASK_PARERR_W :: new (self) } # [doc = "Bit 3 - Enable UART Break Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_brkerr (& mut self) -> INT_EVENT0_IMASK_BRKERR_W < INT_EVENT0_IMASK_SPEC , 3 > { INT_EVENT0_IMASK_BRKERR_W :: new (self) } # [doc = "Bit 4 - Enable UART Receive Overrun Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_ovrerr (& mut self) -> INT_EVENT0_IMASK_OVRERR_W <'_,  INT_EVENT0_IMASK_SPEC , 4 > { INT_EVENT0_IMASK_OVRERR_W :: new (self) } # [doc = "Bit 5 - Enable Negative Edge on UARTxRXD Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_rxne (& mut self) -> INT_EVENT0_IMASK_RXNE_W < INT_EVENT0_IMASK_SPEC , 5 > { INT_EVENT0_IMASK_RXNE_W :: new (self) } # [doc = "Bit 6 - Enable Positive Edge on UARTxRXD Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_rxpe (& mut self) -> INT_EVENT0_IMASK_RXPE_W < INT_EVENT0_IMASK_SPEC , 6 > { INT_EVENT0_IMASK_RXPE_W :: new (self) } # [doc = "Bit 7 - Enable LIN Capture 0 / Match Interrupt ."] # [inline (always)] # [must_use] pub fn int_event0_imask_linc0 (& mut self) -> INT_EVENT0_IMASK_LINC0_W < INT_EVENT0_IMASK_SPEC , 7 > { INT_EVENT0_IMASK_LINC0_W :: new (self) } # [doc = "Bit 8 - Enable LIN Capture 1 Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_linc1 (& mut self) -> INT_EVENT0_IMASK_LINC1_W < INT_EVENT0_IMASK_SPEC , 8 > { INT_EVENT0_IMASK_LINC1_W :: new (self) } # [doc = "Bit 9 - Enable LIN Hardware Counter Overflow Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_linovf (& mut self) -> INT_EVENT0_IMASK_LINOVF_W < INT_EVENT0_IMASK_SPEC , 9 > { INT_EVENT0_IMASK_LINOVF_W :: new (self) } # [doc = "Bit 10 - Enable UART Receive Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_rxint (& mut self) -> INT_EVENT0_IMASK_RXINT_W < INT_EVENT0_IMASK_SPEC , 10 > { INT_EVENT0_IMASK_RXINT_W :: new (self) } # [doc = "Bit 11 - Enable UART Transmit Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_txint (& mut self) -> INT_EVENT0_IMASK_TXINT_W < INT_EVENT0_IMASK_SPEC , 11 > { INT_EVENT0_IMASK_TXINT_W :: new (self) } # [doc = "Bit 12 - Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] # [inline (always)] # [must_use] pub fn int_event0_imask_eot (& mut self) -> INT_EVENT0_IMASK_EOT_W < INT_EVENT0_IMASK_SPEC , 12 > { INT_EVENT0_IMASK_EOT_W :: new (self) } # [doc = "Bit 13 - Enable Address Match Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_addr_match (& mut self) -> INT_EVENT0_IMASK_ADDR_MATCH_W < INT_EVENT0_IMASK_SPEC , 13 > { INT_EVENT0_IMASK_ADDR_MATCH_W :: new (self) } # [doc = "Bit 14 - Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] # [inline (always)] # [must_use] pub fn int_event0_imask_cts (& mut self) -> INT_EVENT0_IMASK_CTS_W < INT_EVENT0_IMASK_SPEC , 14 > { INT_EVENT0_IMASK_CTS_W :: new (self) } # [doc = "Bit 15 - Enable DMA Done on RX Event Channel"] # [inline (always)] # [must_use] pub fn int_event0_imask_dma_done_rx (& mut self) -> INT_EVENT0_IMASK_DMA_DONE_RX_W < INT_EVENT0_IMASK_SPEC , 15 > { INT_EVENT0_IMASK_DMA_DONE_RX_W :: new (self) } # [doc = "Bit 16 - Enable DMA Done on TX Event Channel"] # [inline (always)] # [must_use] pub fn int_event0_imask_dma_done_tx (& mut self) -> INT_EVENT0_IMASK_DMA_DONE_TX_W < INT_EVENT0_IMASK_SPEC , 16 > { INT_EVENT0_IMASK_DMA_DONE_TX_W :: new (self) } # [doc = "Bit 17 - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] # [inline (always)] # [must_use] pub fn int_event0_imask_nerr (& mut self) -> INT_EVENT0_IMASK_NERR_W < INT_EVENT0_IMASK_SPEC , 17 > { INT_EVENT0_IMASK_NERR_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Interrupt mask\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_event0_imask::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_event0_imask::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct INT_EVENT0_IMASK_SPEC ; impl crate :: RegisterSpec for INT_EVENT0_IMASK_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`int_event0_imask::R`](R) reader structure"] impl crate :: Readable for INT_EVENT0_IMASK_SPEC { } # [doc = "`write(|w| ..)` method takes [`int_event0_imask::W`](W) writer structure"] impl crate :: Writable for INT_EVENT0_IMASK_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets INT_EVENT0_IMASK to value 0"] impl crate :: Resettable for INT_EVENT0_IMASK_SPEC { const RESET_VALUE : Self :: Ux = 0 ; }
[INFO] [stdout]   |                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                   +++
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing
[INFO] [stdout]  --> src/uart0/int_event0_iclr.rs:1:25320
[INFO] [stdout]   |
[INFO] [stdout] 1 | ...a_done_rx (& mut self) -> INT_EVENT0_ICLR_DMA_DONE_RX_W < INT_EVENT0_ICLR_SPEC , 15 > { INT_EVENT0_ICLR_DMA_DONE_RX_W :: new (self...
[INFO] [stdout]   |               ^^^^^^^^^^     ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here
[INFO] [stdout]   |               |
[INFO] [stdout]   |               the lifetime is elided here
[INFO] [stdout]   |
[INFO] [stdout]   = help: the same lifetime is referred to in inconsistent ways, making the signature confusing
[INFO] [stdout] help: use `'_` for type paths
[INFO] [stdout]   |
[INFO] [stdout] 1 | # [doc = "Register `INT_EVENT0_ICLR` writer"] pub type W = crate :: W < INT_EVENT0_ICLR_SPEC > ; # [doc = "Clear UARTOUT Receive Time-Out Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_RTOUT_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_RTOUT_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_RTOUT_CLR = 1 , } impl From < INT_EVENT0_ICLR_RTOUT_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_RTOUT_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_RTOUT` writer - Clear UARTOUT Receive Time-Out Interrupt."] pub type INT_EVENT0_ICLR_RTOUT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_RTOUT_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_RTOUT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_rtout_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_RTOUT_AW :: INT_EVENT0_ICLR_RTOUT_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_rtout_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_RTOUT_AW :: INT_EVENT0_ICLR_RTOUT_CLR) } } # [doc = "Clear UART Framing Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_FRMERR_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_FRMERR_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_FRMERR_CLR = 1 , } impl From < INT_EVENT0_ICLR_FRMERR_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_FRMERR_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_FRMERR` writer - Clear UART Framing Error Interrupt."] pub type INT_EVENT0_ICLR_FRMERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_FRMERR_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_FRMERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_frmerr_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_FRMERR_AW :: INT_EVENT0_ICLR_FRMERR_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_frmerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_FRMERR_AW :: INT_EVENT0_ICLR_FRMERR_CLR) } } # [doc = "Clear UART Parity Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_PARERR_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_PARERR_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_PARERR_CLR = 1 , } impl From < INT_EVENT0_ICLR_PARERR_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_PARERR_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_PARERR` writer - Clear UART Parity Error Interrupt."] pub type INT_EVENT0_ICLR_PARERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_PARERR_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_PARERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_parerr_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_PARERR_AW :: INT_EVENT0_ICLR_PARERR_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_parerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_PARERR_AW :: INT_EVENT0_ICLR_PARERR_CLR) } } # [doc = "Clear UART Break Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_BRKERR_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_BRKERR_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_BRKERR_CLR = 1 , } impl From < INT_EVENT0_ICLR_BRKERR_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_BRKERR_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_BRKERR` writer - Clear UART Break Error Interrupt."] pub type INT_EVENT0_ICLR_BRKERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_BRKERR_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_BRKERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_brkerr_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_BRKERR_AW :: INT_EVENT0_ICLR_BRKERR_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_brkerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_BRKERR_AW :: INT_EVENT0_ICLR_BRKERR_CLR) } } # [doc = "Clear UART Receive Overrun Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_OVRERR_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_OVRERR_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_OVRERR_CLR = 1 , } impl From < INT_EVENT0_ICLR_OVRERR_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_OVRERR_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_OVRERR` writer - Clear UART Receive Overrun Error Interrupt."] pub type INT_EVENT0_ICLR_OVRERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_OVRERR_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_OVRERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_ovrerr_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_OVRERR_AW :: INT_EVENT0_ICLR_OVRERR_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_ovrerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_OVRERR_AW :: INT_EVENT0_ICLR_OVRERR_CLR) } } # [doc = "Clear Negative Edge on UARTxRXD Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_RXNE_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_RXNE_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_RXNE_CLR = 1 , } impl From < INT_EVENT0_ICLR_RXNE_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_RXNE_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_RXNE` writer - Clear Negative Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_ICLR_RXNE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_RXNE_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_RXNE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_rxne_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_RXNE_AW :: INT_EVENT0_ICLR_RXNE_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_rxne_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_RXNE_AW :: INT_EVENT0_ICLR_RXNE_CLR) } } # [doc = "Clear Positive Edge on UARTxRXD Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_RXPE_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_RXPE_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_RXPE_CLR = 1 , } impl From < INT_EVENT0_ICLR_RXPE_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_RXPE_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_RXPE` writer - Clear Positive Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_ICLR_RXPE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_RXPE_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_RXPE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_rxpe_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_RXPE_AW :: INT_EVENT0_ICLR_RXPE_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_rxpe_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_RXPE_AW :: INT_EVENT0_ICLR_RXPE_CLR) } } # [doc = "Clear LIN Capture 0 / Match Interrupt .\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_LINC0_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_LINC0_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_LINC0_CLR = 1 , } impl From < INT_EVENT0_ICLR_LINC0_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_LINC0_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_LINC0` writer - Clear LIN Capture 0 / Match Interrupt ."] pub type INT_EVENT0_ICLR_LINC0_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_LINC0_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_LINC0_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_linc0_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_LINC0_AW :: INT_EVENT0_ICLR_LINC0_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_linc0_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_LINC0_AW :: INT_EVENT0_ICLR_LINC0_CLR) } } # [doc = "Clear LIN Capture 1 Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_LINC1_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_LINC1_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_LINC1_CLR = 1 , } impl From < INT_EVENT0_ICLR_LINC1_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_LINC1_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_LINC1` writer - Clear LIN Capture 1 Interrupt."] pub type INT_EVENT0_ICLR_LINC1_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_LINC1_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_LINC1_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_linc1_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_LINC1_AW :: INT_EVENT0_ICLR_LINC1_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_linc1_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_LINC1_AW :: INT_EVENT0_ICLR_LINC1_CLR) } } # [doc = "Clear LIN Hardware Counter Overflow Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_LINOVF_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_LINOVF_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_LINOVF_CLR = 1 , } impl From < INT_EVENT0_ICLR_LINOVF_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_LINOVF_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_LINOVF` writer - Clear LIN Hardware Counter Overflow Interrupt."] pub type INT_EVENT0_ICLR_LINOVF_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_LINOVF_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_LINOVF_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_linovf_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_LINOVF_AW :: INT_EVENT0_ICLR_LINOVF_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_linovf_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_LINOVF_AW :: INT_EVENT0_ICLR_LINOVF_CLR) } } # [doc = "Clear UART Receive Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_RXINT_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_RXINT_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_RXINT_CLR = 1 , } impl From < INT_EVENT0_ICLR_RXINT_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_RXINT_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_RXINT` writer - Clear UART Receive Interrupt."] pub type INT_EVENT0_ICLR_RXINT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_RXINT_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_RXINT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_rxint_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_RXINT_AW :: INT_EVENT0_ICLR_RXINT_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_rxint_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_RXINT_AW :: INT_EVENT0_ICLR_RXINT_CLR) } } # [doc = "Clear UART Transmit Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_TXINT_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_TXINT_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_TXINT_CLR = 1 , } impl From < INT_EVENT0_ICLR_TXINT_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_TXINT_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_TXINT` writer - Clear UART Transmit Interrupt."] pub type INT_EVENT0_ICLR_TXINT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_TXINT_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_TXINT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_txint_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_TXINT_AW :: INT_EVENT0_ICLR_TXINT_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_txint_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_TXINT_AW :: INT_EVENT0_ICLR_TXINT_CLR) } } # [doc = "Clear UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_EOT_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_EOT_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_EOT_CLR = 1 , } impl From < INT_EVENT0_ICLR_EOT_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_EOT_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_EOT` writer - Clear UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] pub type INT_EVENT0_ICLR_EOT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_EOT_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_EOT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_eot_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_EOT_AW :: INT_EVENT0_ICLR_EOT_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_eot_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_EOT_AW :: INT_EVENT0_ICLR_EOT_CLR) } } # [doc = "Clear Address Match Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_ADDR_MATCH_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_ADDR_MATCH_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_ADDR_MATCH_CLR = 1 , } impl From < INT_EVENT0_ICLR_ADDR_MATCH_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_ADDR_MATCH_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_ADDR_MATCH` writer - Clear Address Match Interrupt."] pub type INT_EVENT0_ICLR_ADDR_MATCH_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_ADDR_MATCH_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_ADDR_MATCH_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_addr_match_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_ADDR_MATCH_AW :: INT_EVENT0_ICLR_ADDR_MATCH_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_addr_match_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_ADDR_MATCH_AW :: INT_EVENT0_ICLR_ADDR_MATCH_CLR) } } # [doc = "Clear UART Clear to Send Modem Interrupt. 0 = Interrupt disabled\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_CTS_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_CTS_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_CTS_CLR = 1 , } impl From < INT_EVENT0_ICLR_CTS_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_CTS_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_CTS` writer - Clear UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] pub type INT_EVENT0_ICLR_CTS_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_CTS_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_CTS_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_cts_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_CTS_AW :: INT_EVENT0_ICLR_CTS_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_cts_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_CTS_AW :: INT_EVENT0_ICLR_CTS_CLR) } } # [doc = "Clear DMA Done on RX Event Channel\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_DMA_DONE_RX_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_DMA_DONE_RX_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_DMA_DONE_RX_CLR = 1 , } impl From < INT_EVENT0_ICLR_DMA_DONE_RX_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_DMA_DONE_RX_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_DMA_DONE_RX` writer - Clear DMA Done on RX Event Channel"] pub type INT_EVENT0_ICLR_DMA_DONE_RX_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_DMA_DONE_RX_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_DMA_DONE_RX_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_dma_done_rx_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_DMA_DONE_RX_AW :: INT_EVENT0_ICLR_DMA_DONE_RX_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_dma_done_rx_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_DMA_DONE_RX_AW :: INT_EVENT0_ICLR_DMA_DONE_RX_CLR) } } # [doc = "Clear DMA Done on TX Event Channel\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_DMA_DONE_TX_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_DMA_DONE_TX_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_DMA_DONE_TX_CLR = 1 , } impl From < INT_EVENT0_ICLR_DMA_DONE_TX_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_DMA_DONE_TX_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_DMA_DONE_TX` writer - Clear DMA Done on TX Event Channel"] pub type INT_EVENT0_ICLR_DMA_DONE_TX_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_DMA_DONE_TX_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_DMA_DONE_TX_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_dma_done_tx_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_DMA_DONE_TX_AW :: INT_EVENT0_ICLR_DMA_DONE_TX_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_dma_done_tx_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_DMA_DONE_TX_AW :: INT_EVENT0_ICLR_DMA_DONE_TX_CLR) } } # [doc = "Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_NERR_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_NERR_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_NERR_CLR = 1 , } impl From < INT_EVENT0_ICLR_NERR_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_NERR_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_NERR` writer - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] pub type INT_EVENT0_ICLR_NERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_NERR_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_NERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_nerr_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_NERR_AW :: INT_EVENT0_ICLR_NERR_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_nerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_NERR_AW :: INT_EVENT0_ICLR_NERR_CLR) } } impl W { # [doc = "Bit 0 - Clear UARTOUT Receive Time-Out Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iclr_rtout (& mut self) -> INT_EVENT0_ICLR_RTOUT_W < INT_EVENT0_ICLR_SPEC , 0 > { INT_EVENT0_ICLR_RTOUT_W :: new (self) } # [doc = "Bit 1 - Clear UART Framing Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iclr_frmerr (& mut self) -> INT_EVENT0_ICLR_FRMERR_W < INT_EVENT0_ICLR_SPEC , 1 > { INT_EVENT0_ICLR_FRMERR_W :: new (self) } # [doc = "Bit 2 - Clear UART Parity Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iclr_parerr (& mut self) -> INT_EVENT0_ICLR_PARERR_W < INT_EVENT0_ICLR_SPEC , 2 > { INT_EVENT0_ICLR_PARERR_W :: new (self) } # [doc = "Bit 3 - Clear UART Break Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iclr_brkerr (& mut self) -> INT_EVENT0_ICLR_BRKERR_W < INT_EVENT0_ICLR_SPEC , 3 > { INT_EVENT0_ICLR_BRKERR_W :: new (self) } # [doc = "Bit 4 - Clear UART Receive Overrun Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iclr_ovrerr (& mut self) -> INT_EVENT0_ICLR_OVRERR_W < INT_EVENT0_ICLR_SPEC , 4 > { INT_EVENT0_ICLR_OVRERR_W :: new (self) } # [doc = "Bit 5 - Clear Negative Edge on UARTxRXD Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iclr_rxne (& mut self) -> INT_EVENT0_ICLR_RXNE_W < INT_EVENT0_ICLR_SPEC , 5 > { INT_EVENT0_ICLR_RXNE_W :: new (self) } # [doc = "Bit 6 - Clear Positive Edge on UARTxRXD Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iclr_rxpe (& mut self) -> INT_EVENT0_ICLR_RXPE_W < INT_EVENT0_ICLR_SPEC , 6 > { INT_EVENT0_ICLR_RXPE_W :: new (self) } # [doc = "Bit 7 - Clear LIN Capture 0 / Match Interrupt ."] # [inline (always)] # [must_use] pub fn int_event0_iclr_linc0 (& mut self) -> INT_EVENT0_ICLR_LINC0_W < INT_EVENT0_ICLR_SPEC , 7 > { INT_EVENT0_ICLR_LINC0_W :: new (self) } # [doc = "Bit 8 - Clear LIN Capture 1 Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iclr_linc1 (& mut self) -> INT_EVENT0_ICLR_LINC1_W < INT_EVENT0_ICLR_SPEC , 8 > { INT_EVENT0_ICLR_LINC1_W :: new (self) } # [doc = "Bit 9 - Clear LIN Hardware Counter Overflow Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iclr_linovf (& mut self) -> INT_EVENT0_ICLR_LINOVF_W < INT_EVENT0_ICLR_SPEC , 9 > { INT_EVENT0_ICLR_LINOVF_W :: new (self) } # [doc = "Bit 10 - Clear UART Receive Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iclr_rxint (& mut self) -> INT_EVENT0_ICLR_RXINT_W < INT_EVENT0_ICLR_SPEC , 10 > { INT_EVENT0_ICLR_RXINT_W :: new (self) } # [doc = "Bit 11 - Clear UART Transmit Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iclr_txint (& mut self) -> INT_EVENT0_ICLR_TXINT_W < INT_EVENT0_ICLR_SPEC , 11 > { INT_EVENT0_ICLR_TXINT_W :: new (self) } # [doc = "Bit 12 - Clear UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] # [inline (always)] # [must_use] pub fn int_event0_iclr_eot (& mut self) -> INT_EVENT0_ICLR_EOT_W < INT_EVENT0_ICLR_SPEC , 12 > { INT_EVENT0_ICLR_EOT_W :: new (self) } # [doc = "Bit 13 - Clear Address Match Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iclr_addr_match (& mut self) -> INT_EVENT0_ICLR_ADDR_MATCH_W < INT_EVENT0_ICLR_SPEC , 13 > { INT_EVENT0_ICLR_ADDR_MATCH_W :: new (self) } # [doc = "Bit 14 - Clear UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] # [inline (always)] # [must_use] pub fn int_event0_iclr_cts (& mut self) -> INT_EVENT0_ICLR_CTS_W < INT_EVENT0_ICLR_SPEC , 14 > { INT_EVENT0_ICLR_CTS_W :: new (self) } # [doc = "Bit 15 - Clear DMA Done on RX Event Channel"] # [inline (always)] # [must_use] pub fn int_event0_iclr_dma_done_rx (& mut self) -> INT_EVENT0_ICLR_DMA_DONE_RX_W <'_,  INT_EVENT0_ICLR_SPEC , 15 > { INT_EVENT0_ICLR_DMA_DONE_RX_W :: new (self) } # [doc = "Bit 16 - Clear DMA Done on TX Event Channel"] # [inline (always)] # [must_use] pub fn int_event0_iclr_dma_done_tx (& mut self) -> INT_EVENT0_ICLR_DMA_DONE_TX_W < INT_EVENT0_ICLR_SPEC , 16 > { INT_EVENT0_ICLR_DMA_DONE_TX_W :: new (self) } # [doc = "Bit 17 - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] # [inline (always)] # [must_use] pub fn int_event0_iclr_nerr (& mut self) -> INT_EVENT0_ICLR_NERR_W < INT_EVENT0_ICLR_SPEC , 17 > { INT_EVENT0_ICLR_NERR_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Interrupt clear\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_event0_iclr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct INT_EVENT0_ICLR_SPEC ; impl crate :: RegisterSpec for INT_EVENT0_ICLR_SPEC { type Ux = u32 ; } # [doc = "`write(|w| ..)` method takes [`int_event0_iclr::W`](W) writer structure"] impl crate :: Writable for INT_EVENT0_ICLR_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets INT_EVENT0_ICLR to value 0"] impl crate :: Resettable for INT_EVENT0_ICLR_SPEC { const RESET_VALUE : Self :: Ux = 0 ; }
[INFO] [stdout]   |                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                      +++
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing
[INFO] [stdout]  --> src/uart0/int_event0_imask.rs:1:41691
[INFO] [stdout]   |
[INFO] [stdout] 1 | ...0_imask_rxne (& mut self) -> INT_EVENT0_IMASK_RXNE_W < INT_EVENT0_IMASK_SPEC , 5 > { INT_EVENT0_IMASK_RXNE_W :: new (self) } # [do...
[INFO] [stdout]   |                  ^^^^^^^^^^     ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here
[INFO] [stdout]   |                  |
[INFO] [stdout]   |                  the lifetime is elided here
[INFO] [stdout]   |
[INFO] [stdout]   = help: the same lifetime is referred to in inconsistent ways, making the signature confusing
[INFO] [stdout] help: use `'_` for type paths
[INFO] [stdout]   |
[INFO] [stdout] 1 | # [doc = "Register `INT_EVENT0_IMASK` reader"] pub type R = crate :: R < INT_EVENT0_IMASK_SPEC > ; # [doc = "Register `INT_EVENT0_IMASK` writer"] pub type W = crate :: W < INT_EVENT0_IMASK_SPEC > ; # [doc = "Field `INT_EVENT0_IMASK_RTOUT` reader - Enable UARTOUT Receive Time-Out Interrupt."] pub type INT_EVENT0_IMASK_RTOUT_R = crate :: BitReader < INT_EVENT0_IMASK_RTOUT_A > ; # [doc = "Enable UARTOUT Receive Time-Out Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_RTOUT_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_RTOUT_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_RTOUT_SET = 1 , } impl From < INT_EVENT0_IMASK_RTOUT_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_RTOUT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_RTOUT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_RTOUT_A { match self . bits { false => INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_CLR , true => INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_rtout_clr (& self) -> bool { * self == INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_rtout_set (& self) -> bool { * self == INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_SET } } # [doc = "Field `INT_EVENT0_IMASK_RTOUT` writer - Enable UARTOUT Receive Time-Out Interrupt."] pub type INT_EVENT0_IMASK_RTOUT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_RTOUT_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_RTOUT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_rtout_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_rtout_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_SET) } } # [doc = "Field `INT_EVENT0_IMASK_FRMERR` reader - Enable UART Framing Error Interrupt."] pub type INT_EVENT0_IMASK_FRMERR_R = crate :: BitReader < INT_EVENT0_IMASK_FRMERR_A > ; # [doc = "Enable UART Framing Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_FRMERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_FRMERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_FRMERR_SET = 1 , } impl From < INT_EVENT0_IMASK_FRMERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_FRMERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_FRMERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_FRMERR_A { match self . bits { false => INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_CLR , true => INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_frmerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_frmerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_FRMERR` writer - Enable UART Framing Error Interrupt."] pub type INT_EVENT0_IMASK_FRMERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_FRMERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_FRMERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_frmerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_frmerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_SET) } } # [doc = "Field `INT_EVENT0_IMASK_PARERR` reader - Enable UART Parity Error Interrupt."] pub type INT_EVENT0_IMASK_PARERR_R = crate :: BitReader < INT_EVENT0_IMASK_PARERR_A > ; # [doc = "Enable UART Parity Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_PARERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_PARERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_PARERR_SET = 1 , } impl From < INT_EVENT0_IMASK_PARERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_PARERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_PARERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_PARERR_A { match self . bits { false => INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_CLR , true => INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_parerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_parerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_PARERR` writer - Enable UART Parity Error Interrupt."] pub type INT_EVENT0_IMASK_PARERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_PARERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_PARERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_parerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_parerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_SET) } } # [doc = "Field `INT_EVENT0_IMASK_BRKERR` reader - Enable UART Break Error Interrupt."] pub type INT_EVENT0_IMASK_BRKERR_R = crate :: BitReader < INT_EVENT0_IMASK_BRKERR_A > ; # [doc = "Enable UART Break Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_BRKERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_BRKERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_BRKERR_SET = 1 , } impl From < INT_EVENT0_IMASK_BRKERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_BRKERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_BRKERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_BRKERR_A { match self . bits { false => INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_CLR , true => INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_brkerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_brkerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_BRKERR` writer - Enable UART Break Error Interrupt."] pub type INT_EVENT0_IMASK_BRKERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_BRKERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_BRKERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_brkerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_brkerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_SET) } } # [doc = "Field `INT_EVENT0_IMASK_OVRERR` reader - Enable UART Receive Overrun Error Interrupt."] pub type INT_EVENT0_IMASK_OVRERR_R = crate :: BitReader < INT_EVENT0_IMASK_OVRERR_A > ; # [doc = "Enable UART Receive Overrun Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_OVRERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_OVRERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_OVRERR_SET = 1 , } impl From < INT_EVENT0_IMASK_OVRERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_OVRERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_OVRERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_OVRERR_A { match self . bits { false => INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_CLR , true => INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_ovrerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_ovrerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_OVRERR` writer - Enable UART Receive Overrun Error Interrupt."] pub type INT_EVENT0_IMASK_OVRERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_OVRERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_OVRERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_ovrerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_ovrerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_SET) } } # [doc = "Field `INT_EVENT0_IMASK_RXNE` reader - Enable Negative Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_IMASK_RXNE_R = crate :: BitReader < INT_EVENT0_IMASK_RXNE_A > ; # [doc = "Enable Negative Edge on UARTxRXD Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_RXNE_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_RXNE_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_RXNE_SET = 1 , } impl From < INT_EVENT0_IMASK_RXNE_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_RXNE_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_RXNE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_RXNE_A { match self . bits { false => INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_CLR , true => INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_rxne_clr (& self) -> bool { * self == INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_rxne_set (& self) -> bool { * self == INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_SET } } # [doc = "Field `INT_EVENT0_IMASK_RXNE` writer - Enable Negative Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_IMASK_RXNE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_RXNE_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_RXNE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_rxne_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_rxne_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_SET) } } # [doc = "Field `INT_EVENT0_IMASK_RXPE` reader - Enable Positive Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_IMASK_RXPE_R = crate :: BitReader < INT_EVENT0_IMASK_RXPE_A > ; # [doc = "Enable Positive Edge on UARTxRXD Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_RXPE_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_RXPE_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_RXPE_SET = 1 , } impl From < INT_EVENT0_IMASK_RXPE_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_RXPE_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_RXPE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_RXPE_A { match self . bits { false => INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_CLR , true => INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_rxpe_clr (& self) -> bool { * self == INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_rxpe_set (& self) -> bool { * self == INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_SET } } # [doc = "Field `INT_EVENT0_IMASK_RXPE` writer - Enable Positive Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_IMASK_RXPE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_RXPE_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_RXPE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_rxpe_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_rxpe_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_SET) } } # [doc = "Field `INT_EVENT0_IMASK_LINC0` reader - Enable LIN Capture 0 / Match Interrupt ."] pub type INT_EVENT0_IMASK_LINC0_R = crate :: BitReader < INT_EVENT0_IMASK_LINC0_A > ; # [doc = "Enable LIN Capture 0 / Match Interrupt .\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_LINC0_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_LINC0_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_LINC0_SET = 1 , } impl From < INT_EVENT0_IMASK_LINC0_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_LINC0_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_LINC0_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_LINC0_A { match self . bits { false => INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_CLR , true => INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_linc0_clr (& self) -> bool { * self == INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_linc0_set (& self) -> bool { * self == INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_SET } } # [doc = "Field `INT_EVENT0_IMASK_LINC0` writer - Enable LIN Capture 0 / Match Interrupt ."] pub type INT_EVENT0_IMASK_LINC0_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_LINC0_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_LINC0_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_linc0_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_linc0_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_SET) } } # [doc = "Field `INT_EVENT0_IMASK_LINC1` reader - Enable LIN Capture 1 Interrupt."] pub type INT_EVENT0_IMASK_LINC1_R = crate :: BitReader < INT_EVENT0_IMASK_LINC1_A > ; # [doc = "Enable LIN Capture 1 Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_LINC1_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_LINC1_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_LINC1_SET = 1 , } impl From < INT_EVENT0_IMASK_LINC1_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_LINC1_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_LINC1_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_LINC1_A { match self . bits { false => INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_CLR , true => INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_linc1_clr (& self) -> bool { * self == INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_linc1_set (& self) -> bool { * self == INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_SET } } # [doc = "Field `INT_EVENT0_IMASK_LINC1` writer - Enable LIN Capture 1 Interrupt."] pub type INT_EVENT0_IMASK_LINC1_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_LINC1_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_LINC1_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_linc1_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_linc1_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_SET) } } # [doc = "Field `INT_EVENT0_IMASK_LINOVF` reader - Enable LIN Hardware Counter Overflow Interrupt."] pub type INT_EVENT0_IMASK_LINOVF_R = crate :: BitReader < INT_EVENT0_IMASK_LINOVF_A > ; # [doc = "Enable LIN Hardware Counter Overflow Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_LINOVF_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_LINOVF_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_LINOVF_SET = 1 , } impl From < INT_EVENT0_IMASK_LINOVF_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_LINOVF_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_LINOVF_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_LINOVF_A { match self . bits { false => INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_CLR , true => INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_linovf_clr (& self) -> bool { * self == INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_linovf_set (& self) -> bool { * self == INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_SET } } # [doc = "Field `INT_EVENT0_IMASK_LINOVF` writer - Enable LIN Hardware Counter Overflow Interrupt."] pub type INT_EVENT0_IMASK_LINOVF_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_LINOVF_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_LINOVF_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_linovf_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_linovf_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_SET) } } # [doc = "Field `INT_EVENT0_IMASK_RXINT` reader - Enable UART Receive Interrupt."] pub type INT_EVENT0_IMASK_RXINT_R = crate :: BitReader < INT_EVENT0_IMASK_RXINT_A > ; # [doc = "Enable UART Receive Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_RXINT_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_RXINT_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_RXINT_SET = 1 , } impl From < INT_EVENT0_IMASK_RXINT_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_RXINT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_RXINT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_RXINT_A { match self . bits { false => INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_CLR , true => INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_rxint_clr (& self) -> bool { * self == INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_rxint_set (& self) -> bool { * self == INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_SET } } # [doc = "Field `INT_EVENT0_IMASK_RXINT` writer - Enable UART Receive Interrupt."] pub type INT_EVENT0_IMASK_RXINT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_RXINT_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_RXINT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_rxint_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_rxint_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_SET) } } # [doc = "Field `INT_EVENT0_IMASK_TXINT` reader - Enable UART Transmit Interrupt."] pub type INT_EVENT0_IMASK_TXINT_R = crate :: BitReader < INT_EVENT0_IMASK_TXINT_A > ; # [doc = "Enable UART Transmit Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_TXINT_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_TXINT_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_TXINT_SET = 1 , } impl From < INT_EVENT0_IMASK_TXINT_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_TXINT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_TXINT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_TXINT_A { match self . bits { false => INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_CLR , true => INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_txint_clr (& self) -> bool { * self == INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_txint_set (& self) -> bool { * self == INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_SET } } # [doc = "Field `INT_EVENT0_IMASK_TXINT` writer - Enable UART Transmit Interrupt."] pub type INT_EVENT0_IMASK_TXINT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_TXINT_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_TXINT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_txint_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_txint_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_SET) } } # [doc = "Field `INT_EVENT0_IMASK_EOT` reader - Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] pub type INT_EVENT0_IMASK_EOT_R = crate :: BitReader < INT_EVENT0_IMASK_EOT_A > ; # [doc = "Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_EOT_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_EOT_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_EOT_SET = 1 , } impl From < INT_EVENT0_IMASK_EOT_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_EOT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_EOT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_EOT_A { match self . bits { false => INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_CLR , true => INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_eot_clr (& self) -> bool { * self == INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_eot_set (& self) -> bool { * self == INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_SET } } # [doc = "Field `INT_EVENT0_IMASK_EOT` writer - Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] pub type INT_EVENT0_IMASK_EOT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_EOT_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_EOT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_eot_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_eot_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_SET) } } # [doc = "Field `INT_EVENT0_IMASK_ADDR_MATCH` reader - Enable Address Match Interrupt."] pub type INT_EVENT0_IMASK_ADDR_MATCH_R = crate :: BitReader < INT_EVENT0_IMASK_ADDR_MATCH_A > ; # [doc = "Enable Address Match Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_ADDR_MATCH_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_ADDR_MATCH_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_ADDR_MATCH_SET = 1 , } impl From < INT_EVENT0_IMASK_ADDR_MATCH_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_ADDR_MATCH_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_ADDR_MATCH_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_ADDR_MATCH_A { match self . bits { false => INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_CLR , true => INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_addr_match_clr (& self) -> bool { * self == INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_addr_match_set (& self) -> bool { * self == INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_SET } } # [doc = "Field `INT_EVENT0_IMASK_ADDR_MATCH` writer - Enable Address Match Interrupt."] pub type INT_EVENT0_IMASK_ADDR_MATCH_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_ADDR_MATCH_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_ADDR_MATCH_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_addr_match_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_addr_match_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_SET) } } # [doc = "Field `INT_EVENT0_IMASK_CTS` reader - Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] pub type INT_EVENT0_IMASK_CTS_R = crate :: BitReader < INT_EVENT0_IMASK_CTS_A > ; # [doc = "Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_CTS_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_CTS_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_CTS_SET = 1 , } impl From < INT_EVENT0_IMASK_CTS_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_CTS_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_CTS_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_CTS_A { match self . bits { false => INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_CLR , true => INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_cts_clr (& self) -> bool { * self == INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_cts_set (& self) -> bool { * self == INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_SET } } # [doc = "Field `INT_EVENT0_IMASK_CTS` writer - Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] pub type INT_EVENT0_IMASK_CTS_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_CTS_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_CTS_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_cts_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_cts_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DMA_DONE_RX` reader - Enable DMA Done on RX Event Channel"] pub type INT_EVENT0_IMASK_DMA_DONE_RX_R = crate :: BitReader < INT_EVENT0_IMASK_DMA_DONE_RX_A > ; # [doc = "Enable DMA Done on RX Event Channel\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DMA_DONE_RX_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DMA_DONE_RX_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DMA_DONE_RX_SET = 1 , } impl From < INT_EVENT0_IMASK_DMA_DONE_RX_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DMA_DONE_RX_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DMA_DONE_RX_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DMA_DONE_RX_A { match self . bits { false => INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_CLR , true => INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dma_done_rx_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dma_done_rx_set (& self) -> bool { * self == INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_SET } } # [doc = "Field `INT_EVENT0_IMASK_DMA_DONE_RX` writer - Enable DMA Done on RX Event Channel"] pub type INT_EVENT0_IMASK_DMA_DONE_RX_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DMA_DONE_RX_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DMA_DONE_RX_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dma_done_rx_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dma_done_rx_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DMA_DONE_TX` reader - Enable DMA Done on TX Event Channel"] pub type INT_EVENT0_IMASK_DMA_DONE_TX_R = crate :: BitReader < INT_EVENT0_IMASK_DMA_DONE_TX_A > ; # [doc = "Enable DMA Done on TX Event Channel\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DMA_DONE_TX_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DMA_DONE_TX_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DMA_DONE_TX_SET = 1 , } impl From < INT_EVENT0_IMASK_DMA_DONE_TX_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DMA_DONE_TX_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DMA_DONE_TX_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DMA_DONE_TX_A { match self . bits { false => INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_CLR , true => INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dma_done_tx_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dma_done_tx_set (& self) -> bool { * self == INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_SET } } # [doc = "Field `INT_EVENT0_IMASK_DMA_DONE_TX` writer - Enable DMA Done on TX Event Channel"] pub type INT_EVENT0_IMASK_DMA_DONE_TX_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DMA_DONE_TX_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DMA_DONE_TX_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dma_done_tx_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dma_done_tx_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_SET) } } # [doc = "Field `INT_EVENT0_IMASK_NERR` reader - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] pub type INT_EVENT0_IMASK_NERR_R = crate :: BitReader < INT_EVENT0_IMASK_NERR_A > ; # [doc = "Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_NERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_NERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_NERR_SET = 1 , } impl From < INT_EVENT0_IMASK_NERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_NERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_NERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_NERR_A { match self . bits { false => INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_CLR , true => INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_nerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_nerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_NERR` writer - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] pub type INT_EVENT0_IMASK_NERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_NERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_NERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_nerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_nerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_SET) } } impl R { # [doc = "Bit 0 - Enable UARTOUT Receive Time-Out Interrupt."] # [inline (always)] pub fn int_event0_imask_rtout (& self) -> INT_EVENT0_IMASK_RTOUT_R { INT_EVENT0_IMASK_RTOUT_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - Enable UART Framing Error Interrupt."] # [inline (always)] pub fn int_event0_imask_frmerr (& self) -> INT_EVENT0_IMASK_FRMERR_R { INT_EVENT0_IMASK_FRMERR_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - Enable UART Parity Error Interrupt."] # [inline (always)] pub fn int_event0_imask_parerr (& self) -> INT_EVENT0_IMASK_PARERR_R { INT_EVENT0_IMASK_PARERR_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - Enable UART Break Error Interrupt."] # [inline (always)] pub fn int_event0_imask_brkerr (& self) -> INT_EVENT0_IMASK_BRKERR_R { INT_EVENT0_IMASK_BRKERR_R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - Enable UART Receive Overrun Error Interrupt."] # [inline (always)] pub fn int_event0_imask_ovrerr (& self) -> INT_EVENT0_IMASK_OVRERR_R { INT_EVENT0_IMASK_OVRERR_R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - Enable Negative Edge on UARTxRXD Interrupt."] # [inline (always)] pub fn int_event0_imask_rxne (& self) -> INT_EVENT0_IMASK_RXNE_R { INT_EVENT0_IMASK_RXNE_R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - Enable Positive Edge on UARTxRXD Interrupt."] # [inline (always)] pub fn int_event0_imask_rxpe (& self) -> INT_EVENT0_IMASK_RXPE_R { INT_EVENT0_IMASK_RXPE_R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - Enable LIN Capture 0 / Match Interrupt ."] # [inline (always)] pub fn int_event0_imask_linc0 (& self) -> INT_EVENT0_IMASK_LINC0_R { INT_EVENT0_IMASK_LINC0_R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - Enable LIN Capture 1 Interrupt."] # [inline (always)] pub fn int_event0_imask_linc1 (& self) -> INT_EVENT0_IMASK_LINC1_R { INT_EVENT0_IMASK_LINC1_R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - Enable LIN Hardware Counter Overflow Interrupt."] # [inline (always)] pub fn int_event0_imask_linovf (& self) -> INT_EVENT0_IMASK_LINOVF_R { INT_EVENT0_IMASK_LINOVF_R :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - Enable UART Receive Interrupt."] # [inline (always)] pub fn int_event0_imask_rxint (& self) -> INT_EVENT0_IMASK_RXINT_R { INT_EVENT0_IMASK_RXINT_R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - Enable UART Transmit Interrupt."] # [inline (always)] pub fn int_event0_imask_txint (& self) -> INT_EVENT0_IMASK_TXINT_R { INT_EVENT0_IMASK_TXINT_R :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] # [inline (always)] pub fn int_event0_imask_eot (& self) -> INT_EVENT0_IMASK_EOT_R { INT_EVENT0_IMASK_EOT_R :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - Enable Address Match Interrupt."] # [inline (always)] pub fn int_event0_imask_addr_match (& self) -> INT_EVENT0_IMASK_ADDR_MATCH_R { INT_EVENT0_IMASK_ADDR_MATCH_R :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 14 - Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] # [inline (always)] pub fn int_event0_imask_cts (& self) -> INT_EVENT0_IMASK_CTS_R { INT_EVENT0_IMASK_CTS_R :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - Enable DMA Done on RX Event Channel"] # [inline (always)] pub fn int_event0_imask_dma_done_rx (& self) -> INT_EVENT0_IMASK_DMA_DONE_RX_R { INT_EVENT0_IMASK_DMA_DONE_RX_R :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bit 16 - Enable DMA Done on TX Event Channel"] # [inline (always)] pub fn int_event0_imask_dma_done_tx (& self) -> INT_EVENT0_IMASK_DMA_DONE_TX_R { INT_EVENT0_IMASK_DMA_DONE_TX_R :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] # [inline (always)] pub fn int_event0_imask_nerr (& self) -> INT_EVENT0_IMASK_NERR_R { INT_EVENT0_IMASK_NERR_R :: new (((self . bits >> 17) & 1) != 0) } } impl W { # [doc = "Bit 0 - Enable UARTOUT Receive Time-Out Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_rtout (& mut self) -> INT_EVENT0_IMASK_RTOUT_W < INT_EVENT0_IMASK_SPEC , 0 > { INT_EVENT0_IMASK_RTOUT_W :: new (self) } # [doc = "Bit 1 - Enable UART Framing Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_frmerr (& mut self) -> INT_EVENT0_IMASK_FRMERR_W < INT_EVENT0_IMASK_SPEC , 1 > { INT_EVENT0_IMASK_FRMERR_W :: new (self) } # [doc = "Bit 2 - Enable UART Parity Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_parerr (& mut self) -> INT_EVENT0_IMASK_PARERR_W < INT_EVENT0_IMASK_SPEC , 2 > { INT_EVENT0_IMASK_PARERR_W :: new (self) } # [doc = "Bit 3 - Enable UART Break Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_brkerr (& mut self) -> INT_EVENT0_IMASK_BRKERR_W < INT_EVENT0_IMASK_SPEC , 3 > { INT_EVENT0_IMASK_BRKERR_W :: new (self) } # [doc = "Bit 4 - Enable UART Receive Overrun Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_ovrerr (& mut self) -> INT_EVENT0_IMASK_OVRERR_W < INT_EVENT0_IMASK_SPEC , 4 > { INT_EVENT0_IMASK_OVRERR_W :: new (self) } # [doc = "Bit 5 - Enable Negative Edge on UARTxRXD Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_rxne (& mut self) -> INT_EVENT0_IMASK_RXNE_W <'_,  INT_EVENT0_IMASK_SPEC , 5 > { INT_EVENT0_IMASK_RXNE_W :: new (self) } # [doc = "Bit 6 - Enable Positive Edge on UARTxRXD Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_rxpe (& mut self) -> INT_EVENT0_IMASK_RXPE_W < INT_EVENT0_IMASK_SPEC , 6 > { INT_EVENT0_IMASK_RXPE_W :: new (self) } # [doc = "Bit 7 - Enable LIN Capture 0 / Match Interrupt ."] # [inline (always)] # [must_use] pub fn int_event0_imask_linc0 (& mut self) -> INT_EVENT0_IMASK_LINC0_W < INT_EVENT0_IMASK_SPEC , 7 > { INT_EVENT0_IMASK_LINC0_W :: new (self) } # [doc = "Bit 8 - Enable LIN Capture 1 Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_linc1 (& mut self) -> INT_EVENT0_IMASK_LINC1_W < INT_EVENT0_IMASK_SPEC , 8 > { INT_EVENT0_IMASK_LINC1_W :: new (self) } # [doc = "Bit 9 - Enable LIN Hardware Counter Overflow Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_linovf (& mut self) -> INT_EVENT0_IMASK_LINOVF_W < INT_EVENT0_IMASK_SPEC , 9 > { INT_EVENT0_IMASK_LINOVF_W :: new (self) } # [doc = "Bit 10 - Enable UART Receive Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_rxint (& mut self) -> INT_EVENT0_IMASK_RXINT_W < INT_EVENT0_IMASK_SPEC , 10 > { INT_EVENT0_IMASK_RXINT_W :: new (self) } # [doc = "Bit 11 - Enable UART Transmit Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_txint (& mut self) -> INT_EVENT0_IMASK_TXINT_W < INT_EVENT0_IMASK_SPEC , 11 > { INT_EVENT0_IMASK_TXINT_W :: new (self) } # [doc = "Bit 12 - Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] # [inline (always)] # [must_use] pub fn int_event0_imask_eot (& mut self) -> INT_EVENT0_IMASK_EOT_W < INT_EVENT0_IMASK_SPEC , 12 > { INT_EVENT0_IMASK_EOT_W :: new (self) } # [doc = "Bit 13 - Enable Address Match Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_addr_match (& mut self) -> INT_EVENT0_IMASK_ADDR_MATCH_W < INT_EVENT0_IMASK_SPEC , 13 > { INT_EVENT0_IMASK_ADDR_MATCH_W :: new (self) } # [doc = "Bit 14 - Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] # [inline (always)] # [must_use] pub fn int_event0_imask_cts (& mut self) -> INT_EVENT0_IMASK_CTS_W < INT_EVENT0_IMASK_SPEC , 14 > { INT_EVENT0_IMASK_CTS_W :: new (self) } # [doc = "Bit 15 - Enable DMA Done on RX Event Channel"] # [inline (always)] # [must_use] pub fn int_event0_imask_dma_done_rx (& mut self) -> INT_EVENT0_IMASK_DMA_DONE_RX_W < INT_EVENT0_IMASK_SPEC , 15 > { INT_EVENT0_IMASK_DMA_DONE_RX_W :: new (self) } # [doc = "Bit 16 - Enable DMA Done on TX Event Channel"] # [inline (always)] # [must_use] pub fn int_event0_imask_dma_done_tx (& mut self) -> INT_EVENT0_IMASK_DMA_DONE_TX_W < INT_EVENT0_IMASK_SPEC , 16 > { INT_EVENT0_IMASK_DMA_DONE_TX_W :: new (self) } # [doc = "Bit 17 - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] # [inline (always)] # [must_use] pub fn int_event0_imask_nerr (& mut self) -> INT_EVENT0_IMASK_NERR_W < INT_EVENT0_IMASK_SPEC , 17 > { INT_EVENT0_IMASK_NERR_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Interrupt mask\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_event0_imask::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_event0_imask::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct INT_EVENT0_IMASK_SPEC ; impl crate :: RegisterSpec for INT_EVENT0_IMASK_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`int_event0_imask::R`](R) reader structure"] impl crate :: Readable for INT_EVENT0_IMASK_SPEC { } # [doc = "`write(|w| ..)` method takes [`int_event0_imask::W`](W) writer structure"] impl crate :: Writable for INT_EVENT0_IMASK_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets INT_EVENT0_IMASK to value 0"] impl crate :: Resettable for INT_EVENT0_IMASK_SPEC { const RESET_VALUE : Self :: Ux = 0 ; }
[INFO] [stdout]   |                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                   +++
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing
[INFO] [stdout]  --> src/uart0/int_event0_iclr.rs:1:25568
[INFO] [stdout]   |
[INFO] [stdout] 1 | ...a_done_tx (& mut self) -> INT_EVENT0_ICLR_DMA_DONE_TX_W < INT_EVENT0_ICLR_SPEC , 16 > { INT_EVENT0_ICLR_DMA_DONE_TX_W :: new (self...
[INFO] [stdout]   |               ^^^^^^^^^^     ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here
[INFO] [stdout]   |               |
[INFO] [stdout]   |               the lifetime is elided here
[INFO] [stdout]   |
[INFO] [stdout]   = help: the same lifetime is referred to in inconsistent ways, making the signature confusing
[INFO] [stdout] help: use `'_` for type paths
[INFO] [stdout]   |
[INFO] [stdout] 1 | # [doc = "Register `INT_EVENT0_ICLR` writer"] pub type W = crate :: W < INT_EVENT0_ICLR_SPEC > ; # [doc = "Clear UARTOUT Receive Time-Out Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_RTOUT_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_RTOUT_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_RTOUT_CLR = 1 , } impl From < INT_EVENT0_ICLR_RTOUT_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_RTOUT_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_RTOUT` writer - Clear UARTOUT Receive Time-Out Interrupt."] pub type INT_EVENT0_ICLR_RTOUT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_RTOUT_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_RTOUT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_rtout_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_RTOUT_AW :: INT_EVENT0_ICLR_RTOUT_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_rtout_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_RTOUT_AW :: INT_EVENT0_ICLR_RTOUT_CLR) } } # [doc = "Clear UART Framing Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_FRMERR_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_FRMERR_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_FRMERR_CLR = 1 , } impl From < INT_EVENT0_ICLR_FRMERR_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_FRMERR_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_FRMERR` writer - Clear UART Framing Error Interrupt."] pub type INT_EVENT0_ICLR_FRMERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_FRMERR_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_FRMERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_frmerr_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_FRMERR_AW :: INT_EVENT0_ICLR_FRMERR_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_frmerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_FRMERR_AW :: INT_EVENT0_ICLR_FRMERR_CLR) } } # [doc = "Clear UART Parity Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_PARERR_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_PARERR_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_PARERR_CLR = 1 , } impl From < INT_EVENT0_ICLR_PARERR_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_PARERR_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_PARERR` writer - Clear UART Parity Error Interrupt."] pub type INT_EVENT0_ICLR_PARERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_PARERR_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_PARERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_parerr_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_PARERR_AW :: INT_EVENT0_ICLR_PARERR_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_parerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_PARERR_AW :: INT_EVENT0_ICLR_PARERR_CLR) } } # [doc = "Clear UART Break Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_BRKERR_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_BRKERR_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_BRKERR_CLR = 1 , } impl From < INT_EVENT0_ICLR_BRKERR_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_BRKERR_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_BRKERR` writer - Clear UART Break Error Interrupt."] pub type INT_EVENT0_ICLR_BRKERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_BRKERR_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_BRKERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_brkerr_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_BRKERR_AW :: INT_EVENT0_ICLR_BRKERR_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_brkerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_BRKERR_AW :: INT_EVENT0_ICLR_BRKERR_CLR) } } # [doc = "Clear UART Receive Overrun Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_OVRERR_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_OVRERR_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_OVRERR_CLR = 1 , } impl From < INT_EVENT0_ICLR_OVRERR_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_OVRERR_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_OVRERR` writer - Clear UART Receive Overrun Error Interrupt."] pub type INT_EVENT0_ICLR_OVRERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_OVRERR_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_OVRERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_ovrerr_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_OVRERR_AW :: INT_EVENT0_ICLR_OVRERR_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_ovrerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_OVRERR_AW :: INT_EVENT0_ICLR_OVRERR_CLR) } } # [doc = "Clear Negative Edge on UARTxRXD Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_RXNE_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_RXNE_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_RXNE_CLR = 1 , } impl From < INT_EVENT0_ICLR_RXNE_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_RXNE_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_RXNE` writer - Clear Negative Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_ICLR_RXNE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_RXNE_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_RXNE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_rxne_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_RXNE_AW :: INT_EVENT0_ICLR_RXNE_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_rxne_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_RXNE_AW :: INT_EVENT0_ICLR_RXNE_CLR) } } # [doc = "Clear Positive Edge on UARTxRXD Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_RXPE_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_RXPE_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_RXPE_CLR = 1 , } impl From < INT_EVENT0_ICLR_RXPE_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_RXPE_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_RXPE` writer - Clear Positive Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_ICLR_RXPE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_RXPE_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_RXPE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_rxpe_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_RXPE_AW :: INT_EVENT0_ICLR_RXPE_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_rxpe_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_RXPE_AW :: INT_EVENT0_ICLR_RXPE_CLR) } } # [doc = "Clear LIN Capture 0 / Match Interrupt .\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_LINC0_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_LINC0_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_LINC0_CLR = 1 , } impl From < INT_EVENT0_ICLR_LINC0_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_LINC0_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_LINC0` writer - Clear LIN Capture 0 / Match Interrupt ."] pub type INT_EVENT0_ICLR_LINC0_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_LINC0_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_LINC0_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_linc0_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_LINC0_AW :: INT_EVENT0_ICLR_LINC0_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_linc0_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_LINC0_AW :: INT_EVENT0_ICLR_LINC0_CLR) } } # [doc = "Clear LIN Capture 1 Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_LINC1_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_LINC1_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_LINC1_CLR = 1 , } impl From < INT_EVENT0_ICLR_LINC1_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_LINC1_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_LINC1` writer - Clear LIN Capture 1 Interrupt."] pub type INT_EVENT0_ICLR_LINC1_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_LINC1_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_LINC1_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_linc1_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_LINC1_AW :: INT_EVENT0_ICLR_LINC1_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_linc1_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_LINC1_AW :: INT_EVENT0_ICLR_LINC1_CLR) } } # [doc = "Clear LIN Hardware Counter Overflow Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_LINOVF_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_LINOVF_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_LINOVF_CLR = 1 , } impl From < INT_EVENT0_ICLR_LINOVF_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_LINOVF_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_LINOVF` writer - Clear LIN Hardware Counter Overflow Interrupt."] pub type INT_EVENT0_ICLR_LINOVF_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_LINOVF_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_LINOVF_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_linovf_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_LINOVF_AW :: INT_EVENT0_ICLR_LINOVF_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_linovf_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_LINOVF_AW :: INT_EVENT0_ICLR_LINOVF_CLR) } } # [doc = "Clear UART Receive Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_RXINT_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_RXINT_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_RXINT_CLR = 1 , } impl From < INT_EVENT0_ICLR_RXINT_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_RXINT_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_RXINT` writer - Clear UART Receive Interrupt."] pub type INT_EVENT0_ICLR_RXINT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_RXINT_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_RXINT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_rxint_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_RXINT_AW :: INT_EVENT0_ICLR_RXINT_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_rxint_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_RXINT_AW :: INT_EVENT0_ICLR_RXINT_CLR) } } # [doc = "Clear UART Transmit Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_TXINT_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_TXINT_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_TXINT_CLR = 1 , } impl From < INT_EVENT0_ICLR_TXINT_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_TXINT_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_TXINT` writer - Clear UART Transmit Interrupt."] pub type INT_EVENT0_ICLR_TXINT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_TXINT_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_TXINT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_txint_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_TXINT_AW :: INT_EVENT0_ICLR_TXINT_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_txint_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_TXINT_AW :: INT_EVENT0_ICLR_TXINT_CLR) } } # [doc = "Clear UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_EOT_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_EOT_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_EOT_CLR = 1 , } impl From < INT_EVENT0_ICLR_EOT_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_EOT_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_EOT` writer - Clear UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] pub type INT_EVENT0_ICLR_EOT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_EOT_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_EOT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_eot_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_EOT_AW :: INT_EVENT0_ICLR_EOT_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_eot_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_EOT_AW :: INT_EVENT0_ICLR_EOT_CLR) } } # [doc = "Clear Address Match Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_ADDR_MATCH_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_ADDR_MATCH_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_ADDR_MATCH_CLR = 1 , } impl From < INT_EVENT0_ICLR_ADDR_MATCH_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_ADDR_MATCH_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_ADDR_MATCH` writer - Clear Address Match Interrupt."] pub type INT_EVENT0_ICLR_ADDR_MATCH_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_ADDR_MATCH_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_ADDR_MATCH_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_addr_match_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_ADDR_MATCH_AW :: INT_EVENT0_ICLR_ADDR_MATCH_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_addr_match_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_ADDR_MATCH_AW :: INT_EVENT0_ICLR_ADDR_MATCH_CLR) } } # [doc = "Clear UART Clear to Send Modem Interrupt. 0 = Interrupt disabled\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_CTS_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_CTS_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_CTS_CLR = 1 , } impl From < INT_EVENT0_ICLR_CTS_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_CTS_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_CTS` writer - Clear UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] pub type INT_EVENT0_ICLR_CTS_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_CTS_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_CTS_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_cts_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_CTS_AW :: INT_EVENT0_ICLR_CTS_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_cts_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_CTS_AW :: INT_EVENT0_ICLR_CTS_CLR) } } # [doc = "Clear DMA Done on RX Event Channel\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_DMA_DONE_RX_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_DMA_DONE_RX_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_DMA_DONE_RX_CLR = 1 , } impl From < INT_EVENT0_ICLR_DMA_DONE_RX_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_DMA_DONE_RX_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_DMA_DONE_RX` writer - Clear DMA Done on RX Event Channel"] pub type INT_EVENT0_ICLR_DMA_DONE_RX_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_DMA_DONE_RX_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_DMA_DONE_RX_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_dma_done_rx_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_DMA_DONE_RX_AW :: INT_EVENT0_ICLR_DMA_DONE_RX_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_dma_done_rx_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_DMA_DONE_RX_AW :: INT_EVENT0_ICLR_DMA_DONE_RX_CLR) } } # [doc = "Clear DMA Done on TX Event Channel\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_DMA_DONE_TX_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_DMA_DONE_TX_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_DMA_DONE_TX_CLR = 1 , } impl From < INT_EVENT0_ICLR_DMA_DONE_TX_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_DMA_DONE_TX_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_DMA_DONE_TX` writer - Clear DMA Done on TX Event Channel"] pub type INT_EVENT0_ICLR_DMA_DONE_TX_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_DMA_DONE_TX_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_DMA_DONE_TX_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_dma_done_tx_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_DMA_DONE_TX_AW :: INT_EVENT0_ICLR_DMA_DONE_TX_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_dma_done_tx_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_DMA_DONE_TX_AW :: INT_EVENT0_ICLR_DMA_DONE_TX_CLR) } } # [doc = "Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_NERR_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_NERR_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_NERR_CLR = 1 , } impl From < INT_EVENT0_ICLR_NERR_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_NERR_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_NERR` writer - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] pub type INT_EVENT0_ICLR_NERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_NERR_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_NERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_nerr_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_NERR_AW :: INT_EVENT0_ICLR_NERR_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_nerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_NERR_AW :: INT_EVENT0_ICLR_NERR_CLR) } } impl W { # [doc = "Bit 0 - Clear UARTOUT Receive Time-Out Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iclr_rtout (& mut self) -> INT_EVENT0_ICLR_RTOUT_W < INT_EVENT0_ICLR_SPEC , 0 > { INT_EVENT0_ICLR_RTOUT_W :: new (self) } # [doc = "Bit 1 - Clear UART Framing Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iclr_frmerr (& mut self) -> INT_EVENT0_ICLR_FRMERR_W < INT_EVENT0_ICLR_SPEC , 1 > { INT_EVENT0_ICLR_FRMERR_W :: new (self) } # [doc = "Bit 2 - Clear UART Parity Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iclr_parerr (& mut self) -> INT_EVENT0_ICLR_PARERR_W < INT_EVENT0_ICLR_SPEC , 2 > { INT_EVENT0_ICLR_PARERR_W :: new (self) } # [doc = "Bit 3 - Clear UART Break Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iclr_brkerr (& mut self) -> INT_EVENT0_ICLR_BRKERR_W < INT_EVENT0_ICLR_SPEC , 3 > { INT_EVENT0_ICLR_BRKERR_W :: new (self) } # [doc = "Bit 4 - Clear UART Receive Overrun Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iclr_ovrerr (& mut self) -> INT_EVENT0_ICLR_OVRERR_W < INT_EVENT0_ICLR_SPEC , 4 > { INT_EVENT0_ICLR_OVRERR_W :: new (self) } # [doc = "Bit 5 - Clear Negative Edge on UARTxRXD Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iclr_rxne (& mut self) -> INT_EVENT0_ICLR_RXNE_W < INT_EVENT0_ICLR_SPEC , 5 > { INT_EVENT0_ICLR_RXNE_W :: new (self) } # [doc = "Bit 6 - Clear Positive Edge on UARTxRXD Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iclr_rxpe (& mut self) -> INT_EVENT0_ICLR_RXPE_W < INT_EVENT0_ICLR_SPEC , 6 > { INT_EVENT0_ICLR_RXPE_W :: new (self) } # [doc = "Bit 7 - Clear LIN Capture 0 / Match Interrupt ."] # [inline (always)] # [must_use] pub fn int_event0_iclr_linc0 (& mut self) -> INT_EVENT0_ICLR_LINC0_W < INT_EVENT0_ICLR_SPEC , 7 > { INT_EVENT0_ICLR_LINC0_W :: new (self) } # [doc = "Bit 8 - Clear LIN Capture 1 Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iclr_linc1 (& mut self) -> INT_EVENT0_ICLR_LINC1_W < INT_EVENT0_ICLR_SPEC , 8 > { INT_EVENT0_ICLR_LINC1_W :: new (self) } # [doc = "Bit 9 - Clear LIN Hardware Counter Overflow Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iclr_linovf (& mut self) -> INT_EVENT0_ICLR_LINOVF_W < INT_EVENT0_ICLR_SPEC , 9 > { INT_EVENT0_ICLR_LINOVF_W :: new (self) } # [doc = "Bit 10 - Clear UART Receive Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iclr_rxint (& mut self) -> INT_EVENT0_ICLR_RXINT_W < INT_EVENT0_ICLR_SPEC , 10 > { INT_EVENT0_ICLR_RXINT_W :: new (self) } # [doc = "Bit 11 - Clear UART Transmit Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iclr_txint (& mut self) -> INT_EVENT0_ICLR_TXINT_W < INT_EVENT0_ICLR_SPEC , 11 > { INT_EVENT0_ICLR_TXINT_W :: new (self) } # [doc = "Bit 12 - Clear UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] # [inline (always)] # [must_use] pub fn int_event0_iclr_eot (& mut self) -> INT_EVENT0_ICLR_EOT_W < INT_EVENT0_ICLR_SPEC , 12 > { INT_EVENT0_ICLR_EOT_W :: new (self) } # [doc = "Bit 13 - Clear Address Match Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iclr_addr_match (& mut self) -> INT_EVENT0_ICLR_ADDR_MATCH_W < INT_EVENT0_ICLR_SPEC , 13 > { INT_EVENT0_ICLR_ADDR_MATCH_W :: new (self) } # [doc = "Bit 14 - Clear UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] # [inline (always)] # [must_use] pub fn int_event0_iclr_cts (& mut self) -> INT_EVENT0_ICLR_CTS_W < INT_EVENT0_ICLR_SPEC , 14 > { INT_EVENT0_ICLR_CTS_W :: new (self) } # [doc = "Bit 15 - Clear DMA Done on RX Event Channel"] # [inline (always)] # [must_use] pub fn int_event0_iclr_dma_done_rx (& mut self) -> INT_EVENT0_ICLR_DMA_DONE_RX_W < INT_EVENT0_ICLR_SPEC , 15 > { INT_EVENT0_ICLR_DMA_DONE_RX_W :: new (self) } # [doc = "Bit 16 - Clear DMA Done on TX Event Channel"] # [inline (always)] # [must_use] pub fn int_event0_iclr_dma_done_tx (& mut self) -> INT_EVENT0_ICLR_DMA_DONE_TX_W <'_,  INT_EVENT0_ICLR_SPEC , 16 > { INT_EVENT0_ICLR_DMA_DONE_TX_W :: new (self) } # [doc = "Bit 17 - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] # [inline (always)] # [must_use] pub fn int_event0_iclr_nerr (& mut self) -> INT_EVENT0_ICLR_NERR_W < INT_EVENT0_ICLR_SPEC , 17 > { INT_EVENT0_ICLR_NERR_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Interrupt clear\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_event0_iclr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct INT_EVENT0_ICLR_SPEC ; impl crate :: RegisterSpec for INT_EVENT0_ICLR_SPEC { type Ux = u32 ; } # [doc = "`write(|w| ..)` method takes [`int_event0_iclr::W`](W) writer structure"] impl crate :: Writable for INT_EVENT0_ICLR_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets INT_EVENT0_ICLR to value 0"] impl crate :: Resettable for INT_EVENT0_ICLR_SPEC { const RESET_VALUE : Self :: Ux = 0 ; }
[INFO] [stdout]   |                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                              +++
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing
[INFO] [stdout]  --> src/uart0/int_event0_iclr.rs:1:25865
[INFO] [stdout]   |
[INFO] [stdout] 1 | ...nt0_iclr_nerr (& mut self) -> INT_EVENT0_ICLR_NERR_W < INT_EVENT0_ICLR_SPEC , 17 > { INT_EVENT0_ICLR_NERR_W :: new (self) } # [doc...
[INFO] [stdout]   |                   ^^^^^^^^^^     ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here
[INFO] [stdout]   |                   |
[INFO] [stdout]   |                   the lifetime is elided here
[INFO] [stdout]   |
[INFO] [stdout]   = help: the same lifetime is referred to in inconsistent ways, making the signature confusing
[INFO] [stdout] help: use `'_` for type paths
[INFO] [stdout]   |
[INFO] [stdout] 1 | # [doc = "Register `INT_EVENT0_ICLR` writer"] pub type W = crate :: W < INT_EVENT0_ICLR_SPEC > ; # [doc = "Clear UARTOUT Receive Time-Out Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_RTOUT_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_RTOUT_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_RTOUT_CLR = 1 , } impl From < INT_EVENT0_ICLR_RTOUT_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_RTOUT_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_RTOUT` writer - Clear UARTOUT Receive Time-Out Interrupt."] pub type INT_EVENT0_ICLR_RTOUT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_RTOUT_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_RTOUT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_rtout_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_RTOUT_AW :: INT_EVENT0_ICLR_RTOUT_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_rtout_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_RTOUT_AW :: INT_EVENT0_ICLR_RTOUT_CLR) } } # [doc = "Clear UART Framing Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_FRMERR_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_FRMERR_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_FRMERR_CLR = 1 , } impl From < INT_EVENT0_ICLR_FRMERR_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_FRMERR_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_FRMERR` writer - Clear UART Framing Error Interrupt."] pub type INT_EVENT0_ICLR_FRMERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_FRMERR_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_FRMERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_frmerr_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_FRMERR_AW :: INT_EVENT0_ICLR_FRMERR_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_frmerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_FRMERR_AW :: INT_EVENT0_ICLR_FRMERR_CLR) } } # [doc = "Clear UART Parity Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_PARERR_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_PARERR_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_PARERR_CLR = 1 , } impl From < INT_EVENT0_ICLR_PARERR_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_PARERR_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_PARERR` writer - Clear UART Parity Error Interrupt."] pub type INT_EVENT0_ICLR_PARERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_PARERR_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_PARERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_parerr_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_PARERR_AW :: INT_EVENT0_ICLR_PARERR_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_parerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_PARERR_AW :: INT_EVENT0_ICLR_PARERR_CLR) } } # [doc = "Clear UART Break Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_BRKERR_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_BRKERR_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_BRKERR_CLR = 1 , } impl From < INT_EVENT0_ICLR_BRKERR_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_BRKERR_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_BRKERR` writer - Clear UART Break Error Interrupt."] pub type INT_EVENT0_ICLR_BRKERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_BRKERR_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_BRKERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_brkerr_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_BRKERR_AW :: INT_EVENT0_ICLR_BRKERR_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_brkerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_BRKERR_AW :: INT_EVENT0_ICLR_BRKERR_CLR) } } # [doc = "Clear UART Receive Overrun Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_OVRERR_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_OVRERR_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_OVRERR_CLR = 1 , } impl From < INT_EVENT0_ICLR_OVRERR_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_OVRERR_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_OVRERR` writer - Clear UART Receive Overrun Error Interrupt."] pub type INT_EVENT0_ICLR_OVRERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_OVRERR_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_OVRERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_ovrerr_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_OVRERR_AW :: INT_EVENT0_ICLR_OVRERR_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_ovrerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_OVRERR_AW :: INT_EVENT0_ICLR_OVRERR_CLR) } } # [doc = "Clear Negative Edge on UARTxRXD Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_RXNE_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_RXNE_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_RXNE_CLR = 1 , } impl From < INT_EVENT0_ICLR_RXNE_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_RXNE_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_RXNE` writer - Clear Negative Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_ICLR_RXNE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_RXNE_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_RXNE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_rxne_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_RXNE_AW :: INT_EVENT0_ICLR_RXNE_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_rxne_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_RXNE_AW :: INT_EVENT0_ICLR_RXNE_CLR) } } # [doc = "Clear Positive Edge on UARTxRXD Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_RXPE_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_RXPE_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_RXPE_CLR = 1 , } impl From < INT_EVENT0_ICLR_RXPE_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_RXPE_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_RXPE` writer - Clear Positive Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_ICLR_RXPE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_RXPE_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_RXPE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_rxpe_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_RXPE_AW :: INT_EVENT0_ICLR_RXPE_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_rxpe_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_RXPE_AW :: INT_EVENT0_ICLR_RXPE_CLR) } } # [doc = "Clear LIN Capture 0 / Match Interrupt .\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_LINC0_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_LINC0_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_LINC0_CLR = 1 , } impl From < INT_EVENT0_ICLR_LINC0_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_LINC0_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_LINC0` writer - Clear LIN Capture 0 / Match Interrupt ."] pub type INT_EVENT0_ICLR_LINC0_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_LINC0_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_LINC0_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_linc0_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_LINC0_AW :: INT_EVENT0_ICLR_LINC0_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_linc0_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_LINC0_AW :: INT_EVENT0_ICLR_LINC0_CLR) } } # [doc = "Clear LIN Capture 1 Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_LINC1_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_LINC1_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_LINC1_CLR = 1 , } impl From < INT_EVENT0_ICLR_LINC1_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_LINC1_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_LINC1` writer - Clear LIN Capture 1 Interrupt."] pub type INT_EVENT0_ICLR_LINC1_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_LINC1_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_LINC1_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_linc1_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_LINC1_AW :: INT_EVENT0_ICLR_LINC1_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_linc1_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_LINC1_AW :: INT_EVENT0_ICLR_LINC1_CLR) } } # [doc = "Clear LIN Hardware Counter Overflow Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_LINOVF_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_LINOVF_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_LINOVF_CLR = 1 , } impl From < INT_EVENT0_ICLR_LINOVF_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_LINOVF_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_LINOVF` writer - Clear LIN Hardware Counter Overflow Interrupt."] pub type INT_EVENT0_ICLR_LINOVF_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_LINOVF_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_LINOVF_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_linovf_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_LINOVF_AW :: INT_EVENT0_ICLR_LINOVF_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_linovf_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_LINOVF_AW :: INT_EVENT0_ICLR_LINOVF_CLR) } } # [doc = "Clear UART Receive Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_RXINT_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_RXINT_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_RXINT_CLR = 1 , } impl From < INT_EVENT0_ICLR_RXINT_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_RXINT_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_RXINT` writer - Clear UART Receive Interrupt."] pub type INT_EVENT0_ICLR_RXINT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_RXINT_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_RXINT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_rxint_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_RXINT_AW :: INT_EVENT0_ICLR_RXINT_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_rxint_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_RXINT_AW :: INT_EVENT0_ICLR_RXINT_CLR) } } # [doc = "Clear UART Transmit Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_TXINT_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_TXINT_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_TXINT_CLR = 1 , } impl From < INT_EVENT0_ICLR_TXINT_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_TXINT_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_TXINT` writer - Clear UART Transmit Interrupt."] pub type INT_EVENT0_ICLR_TXINT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_TXINT_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_TXINT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_txint_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_TXINT_AW :: INT_EVENT0_ICLR_TXINT_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_txint_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_TXINT_AW :: INT_EVENT0_ICLR_TXINT_CLR) } } # [doc = "Clear UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_EOT_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_EOT_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_EOT_CLR = 1 , } impl From < INT_EVENT0_ICLR_EOT_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_EOT_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_EOT` writer - Clear UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] pub type INT_EVENT0_ICLR_EOT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_EOT_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_EOT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_eot_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_EOT_AW :: INT_EVENT0_ICLR_EOT_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_eot_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_EOT_AW :: INT_EVENT0_ICLR_EOT_CLR) } } # [doc = "Clear Address Match Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_ADDR_MATCH_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_ADDR_MATCH_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_ADDR_MATCH_CLR = 1 , } impl From < INT_EVENT0_ICLR_ADDR_MATCH_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_ADDR_MATCH_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_ADDR_MATCH` writer - Clear Address Match Interrupt."] pub type INT_EVENT0_ICLR_ADDR_MATCH_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_ADDR_MATCH_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_ADDR_MATCH_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_addr_match_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_ADDR_MATCH_AW :: INT_EVENT0_ICLR_ADDR_MATCH_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_addr_match_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_ADDR_MATCH_AW :: INT_EVENT0_ICLR_ADDR_MATCH_CLR) } } # [doc = "Clear UART Clear to Send Modem Interrupt. 0 = Interrupt disabled\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_CTS_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_CTS_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_CTS_CLR = 1 , } impl From < INT_EVENT0_ICLR_CTS_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_CTS_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_CTS` writer - Clear UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] pub type INT_EVENT0_ICLR_CTS_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_CTS_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_CTS_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_cts_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_CTS_AW :: INT_EVENT0_ICLR_CTS_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_cts_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_CTS_AW :: INT_EVENT0_ICLR_CTS_CLR) } } # [doc = "Clear DMA Done on RX Event Channel\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_DMA_DONE_RX_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_DMA_DONE_RX_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_DMA_DONE_RX_CLR = 1 , } impl From < INT_EVENT0_ICLR_DMA_DONE_RX_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_DMA_DONE_RX_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_DMA_DONE_RX` writer - Clear DMA Done on RX Event Channel"] pub type INT_EVENT0_ICLR_DMA_DONE_RX_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_DMA_DONE_RX_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_DMA_DONE_RX_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_dma_done_rx_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_DMA_DONE_RX_AW :: INT_EVENT0_ICLR_DMA_DONE_RX_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_dma_done_rx_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_DMA_DONE_RX_AW :: INT_EVENT0_ICLR_DMA_DONE_RX_CLR) } } # [doc = "Clear DMA Done on TX Event Channel\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_DMA_DONE_TX_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_DMA_DONE_TX_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_DMA_DONE_TX_CLR = 1 , } impl From < INT_EVENT0_ICLR_DMA_DONE_TX_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_DMA_DONE_TX_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_DMA_DONE_TX` writer - Clear DMA Done on TX Event Channel"] pub type INT_EVENT0_ICLR_DMA_DONE_TX_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_DMA_DONE_TX_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_DMA_DONE_TX_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_dma_done_tx_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_DMA_DONE_TX_AW :: INT_EVENT0_ICLR_DMA_DONE_TX_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_dma_done_tx_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_DMA_DONE_TX_AW :: INT_EVENT0_ICLR_DMA_DONE_TX_CLR) } } # [doc = "Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ICLR_NERR_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ICLR_NERR_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT0_ICLR_NERR_CLR = 1 , } impl From < INT_EVENT0_ICLR_NERR_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ICLR_NERR_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_NERR` writer - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] pub type INT_EVENT0_ICLR_NERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_NERR_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_NERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iclr_nerr_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_NERR_AW :: INT_EVENT0_ICLR_NERR_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event0_iclr_nerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_NERR_AW :: INT_EVENT0_ICLR_NERR_CLR) } } impl W { # [doc = "Bit 0 - Clear UARTOUT Receive Time-Out Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iclr_rtout (& mut self) -> INT_EVENT0_ICLR_RTOUT_W < INT_EVENT0_ICLR_SPEC , 0 > { INT_EVENT0_ICLR_RTOUT_W :: new (self) } # [doc = "Bit 1 - Clear UART Framing Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iclr_frmerr (& mut self) -> INT_EVENT0_ICLR_FRMERR_W < INT_EVENT0_ICLR_SPEC , 1 > { INT_EVENT0_ICLR_FRMERR_W :: new (self) } # [doc = "Bit 2 - Clear UART Parity Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iclr_parerr (& mut self) -> INT_EVENT0_ICLR_PARERR_W < INT_EVENT0_ICLR_SPEC , 2 > { INT_EVENT0_ICLR_PARERR_W :: new (self) } # [doc = "Bit 3 - Clear UART Break Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iclr_brkerr (& mut self) -> INT_EVENT0_ICLR_BRKERR_W < INT_EVENT0_ICLR_SPEC , 3 > { INT_EVENT0_ICLR_BRKERR_W :: new (self) } # [doc = "Bit 4 - Clear UART Receive Overrun Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iclr_ovrerr (& mut self) -> INT_EVENT0_ICLR_OVRERR_W < INT_EVENT0_ICLR_SPEC , 4 > { INT_EVENT0_ICLR_OVRERR_W :: new (self) } # [doc = "Bit 5 - Clear Negative Edge on UARTxRXD Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iclr_rxne (& mut self) -> INT_EVENT0_ICLR_RXNE_W < INT_EVENT0_ICLR_SPEC , 5 > { INT_EVENT0_ICLR_RXNE_W :: new (self) } # [doc = "Bit 6 - Clear Positive Edge on UARTxRXD Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iclr_rxpe (& mut self) -> INT_EVENT0_ICLR_RXPE_W < INT_EVENT0_ICLR_SPEC , 6 > { INT_EVENT0_ICLR_RXPE_W :: new (self) } # [doc = "Bit 7 - Clear LIN Capture 0 / Match Interrupt ."] # [inline (always)] # [must_use] pub fn int_event0_iclr_linc0 (& mut self) -> INT_EVENT0_ICLR_LINC0_W < INT_EVENT0_ICLR_SPEC , 7 > { INT_EVENT0_ICLR_LINC0_W :: new (self) } # [doc = "Bit 8 - Clear LIN Capture 1 Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iclr_linc1 (& mut self) -> INT_EVENT0_ICLR_LINC1_W < INT_EVENT0_ICLR_SPEC , 8 > { INT_EVENT0_ICLR_LINC1_W :: new (self) } # [doc = "Bit 9 - Clear LIN Hardware Counter Overflow Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iclr_linovf (& mut self) -> INT_EVENT0_ICLR_LINOVF_W < INT_EVENT0_ICLR_SPEC , 9 > { INT_EVENT0_ICLR_LINOVF_W :: new (self) } # [doc = "Bit 10 - Clear UART Receive Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iclr_rxint (& mut self) -> INT_EVENT0_ICLR_RXINT_W < INT_EVENT0_ICLR_SPEC , 10 > { INT_EVENT0_ICLR_RXINT_W :: new (self) } # [doc = "Bit 11 - Clear UART Transmit Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iclr_txint (& mut self) -> INT_EVENT0_ICLR_TXINT_W < INT_EVENT0_ICLR_SPEC , 11 > { INT_EVENT0_ICLR_TXINT_W :: new (self) } # [doc = "Bit 12 - Clear UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] # [inline (always)] # [must_use] pub fn int_event0_iclr_eot (& mut self) -> INT_EVENT0_ICLR_EOT_W < INT_EVENT0_ICLR_SPEC , 12 > { INT_EVENT0_ICLR_EOT_W :: new (self) } # [doc = "Bit 13 - Clear Address Match Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_iclr_addr_match (& mut self) -> INT_EVENT0_ICLR_ADDR_MATCH_W < INT_EVENT0_ICLR_SPEC , 13 > { INT_EVENT0_ICLR_ADDR_MATCH_W :: new (self) } # [doc = "Bit 14 - Clear UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] # [inline (always)] # [must_use] pub fn int_event0_iclr_cts (& mut self) -> INT_EVENT0_ICLR_CTS_W < INT_EVENT0_ICLR_SPEC , 14 > { INT_EVENT0_ICLR_CTS_W :: new (self) } # [doc = "Bit 15 - Clear DMA Done on RX Event Channel"] # [inline (always)] # [must_use] pub fn int_event0_iclr_dma_done_rx (& mut self) -> INT_EVENT0_ICLR_DMA_DONE_RX_W < INT_EVENT0_ICLR_SPEC , 15 > { INT_EVENT0_ICLR_DMA_DONE_RX_W :: new (self) } # [doc = "Bit 16 - Clear DMA Done on TX Event Channel"] # [inline (always)] # [must_use] pub fn int_event0_iclr_dma_done_tx (& mut self) -> INT_EVENT0_ICLR_DMA_DONE_TX_W < INT_EVENT0_ICLR_SPEC , 16 > { INT_EVENT0_ICLR_DMA_DONE_TX_W :: new (self) } # [doc = "Bit 17 - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] # [inline (always)] # [must_use] pub fn int_event0_iclr_nerr (& mut self) -> INT_EVENT0_ICLR_NERR_W <'_,  INT_EVENT0_ICLR_SPEC , 17 > { INT_EVENT0_ICLR_NERR_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Interrupt clear\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_event0_iclr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct INT_EVENT0_ICLR_SPEC ; impl crate :: RegisterSpec for INT_EVENT0_ICLR_SPEC { type Ux = u32 ; } # [doc = "`write(|w| ..)` method takes [`int_event0_iclr::W`](W) writer structure"] impl crate :: Writable for INT_EVENT0_ICLR_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets INT_EVENT0_ICLR to value 0"] impl crate :: Resettable for INT_EVENT0_ICLR_SPEC { const RESET_VALUE : Self :: Ux = 0 ; }
[INFO] [stdout]   |                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                +++
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing
[INFO] [stdout]  --> src/uart0/int_event1_imask.rs:1:4637
[INFO] [stdout]   |
[INFO] [stdout] 1 | ..._imask_rtout (& mut self) -> INT_EVENT1_IMASK_RTOUT_W < INT_EVENT1_IMASK_SPEC , 0 > { INT_EVENT1_IMASK_RTOUT_W :: new (self) } # [...
[INFO] [stdout]   |                  ^^^^^^^^^^     ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here
[INFO] [stdout]   |                  |
[INFO] [stdout]   |                  the lifetime is elided here
[INFO] [stdout]   |
[INFO] [stdout]   = help: the same lifetime is referred to in inconsistent ways, making the signature confusing
[INFO] [stdout] help: use `'_` for type paths
[INFO] [stdout]   |
[INFO] [stdout] 1 | # [doc = "Register `INT_EVENT1_IMASK` reader"] pub type R = crate :: R < INT_EVENT1_IMASK_SPEC > ; # [doc = "Register `INT_EVENT1_IMASK` writer"] pub type W = crate :: W < INT_EVENT1_IMASK_SPEC > ; # [doc = "Field `INT_EVENT1_IMASK_RTOUT` reader - Enable UARTOUT Receive Time-Out Interrupt."] pub type INT_EVENT1_IMASK_RTOUT_R = crate :: BitReader < INT_EVENT1_IMASK_RTOUT_A > ; # [doc = "Enable UARTOUT Receive Time-Out Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT1_IMASK_RTOUT_A { # [doc = "0: CLR"] INT_EVENT1_IMASK_RTOUT_CLR = 0 , # [doc = "1: SET"] INT_EVENT1_IMASK_RTOUT_SET = 1 , } impl From < INT_EVENT1_IMASK_RTOUT_A > for bool { # [inline (always)] fn from (variant : INT_EVENT1_IMASK_RTOUT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT1_IMASK_RTOUT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT1_IMASK_RTOUT_A { match self . bits { false => INT_EVENT1_IMASK_RTOUT_A :: INT_EVENT1_IMASK_RTOUT_CLR , true => INT_EVENT1_IMASK_RTOUT_A :: INT_EVENT1_IMASK_RTOUT_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event1_imask_rtout_clr (& self) -> bool { * self == INT_EVENT1_IMASK_RTOUT_A :: INT_EVENT1_IMASK_RTOUT_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event1_imask_rtout_set (& self) -> bool { * self == INT_EVENT1_IMASK_RTOUT_A :: INT_EVENT1_IMASK_RTOUT_SET } } # [doc = "Field `INT_EVENT1_IMASK_RTOUT` writer - Enable UARTOUT Receive Time-Out Interrupt."] pub type INT_EVENT1_IMASK_RTOUT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT1_IMASK_RTOUT_A > ; impl < 'a , REG , const O : u8 > INT_EVENT1_IMASK_RTOUT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event1_imask_rtout_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_IMASK_RTOUT_A :: INT_EVENT1_IMASK_RTOUT_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event1_imask_rtout_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_IMASK_RTOUT_A :: INT_EVENT1_IMASK_RTOUT_SET) } } # [doc = "Field `INT_EVENT1_IMASK_RXINT` reader - Enable UART Receive Interrupt."] pub type INT_EVENT1_IMASK_RXINT_R = crate :: BitReader < INT_EVENT1_IMASK_RXINT_A > ; # [doc = "Enable UART Receive Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT1_IMASK_RXINT_A { # [doc = "0: CLR"] INT_EVENT1_IMASK_RXINT_CLR = 0 , # [doc = "1: SET"] INT_EVENT1_IMASK_RXINT_SET = 1 , } impl From < INT_EVENT1_IMASK_RXINT_A > for bool { # [inline (always)] fn from (variant : INT_EVENT1_IMASK_RXINT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT1_IMASK_RXINT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT1_IMASK_RXINT_A { match self . bits { false => INT_EVENT1_IMASK_RXINT_A :: INT_EVENT1_IMASK_RXINT_CLR , true => INT_EVENT1_IMASK_RXINT_A :: INT_EVENT1_IMASK_RXINT_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event1_imask_rxint_clr (& self) -> bool { * self == INT_EVENT1_IMASK_RXINT_A :: INT_EVENT1_IMASK_RXINT_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event1_imask_rxint_set (& self) -> bool { * self == INT_EVENT1_IMASK_RXINT_A :: INT_EVENT1_IMASK_RXINT_SET } } # [doc = "Field `INT_EVENT1_IMASK_RXINT` writer - Enable UART Receive Interrupt."] pub type INT_EVENT1_IMASK_RXINT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT1_IMASK_RXINT_A > ; impl < 'a , REG , const O : u8 > INT_EVENT1_IMASK_RXINT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event1_imask_rxint_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_IMASK_RXINT_A :: INT_EVENT1_IMASK_RXINT_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event1_imask_rxint_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_IMASK_RXINT_A :: INT_EVENT1_IMASK_RXINT_SET) } } impl R { # [doc = "Bit 0 - Enable UARTOUT Receive Time-Out Interrupt."] # [inline (always)] pub fn int_event1_imask_rtout (& self) -> INT_EVENT1_IMASK_RTOUT_R { INT_EVENT1_IMASK_RTOUT_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 10 - Enable UART Receive Interrupt."] # [inline (always)] pub fn int_event1_imask_rxint (& self) -> INT_EVENT1_IMASK_RXINT_R { INT_EVENT1_IMASK_RXINT_R :: new (((self . bits >> 10) & 1) != 0) } } impl W { # [doc = "Bit 0 - Enable UARTOUT Receive Time-Out Interrupt."] # [inline (always)] # [must_use] pub fn int_event1_imask_rtout (& mut self) -> INT_EVENT1_IMASK_RTOUT_W <'_,  INT_EVENT1_IMASK_SPEC , 0 > { INT_EVENT1_IMASK_RTOUT_W :: new (self) } # [doc = "Bit 10 - Enable UART Receive Interrupt."] # [inline (always)] # [must_use] pub fn int_event1_imask_rxint (& mut self) -> INT_EVENT1_IMASK_RXINT_W < INT_EVENT1_IMASK_SPEC , 10 > { INT_EVENT1_IMASK_RXINT_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Interrupt mask\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_event1_imask::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_event1_imask::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct INT_EVENT1_IMASK_SPEC ; impl crate :: RegisterSpec for INT_EVENT1_IMASK_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`int_event1_imask::R`](R) reader structure"] impl crate :: Readable for INT_EVENT1_IMASK_SPEC { } # [doc = "`write(|w| ..)` method takes [`int_event1_imask::W`](W) writer structure"] impl crate :: Writable for INT_EVENT1_IMASK_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets INT_EVENT1_IMASK to value 0"] impl crate :: Resettable for INT_EVENT1_IMASK_SPEC { const RESET_VALUE : Self :: Ux = 0 ; }
[INFO] [stdout]   |                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                      +++
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing
[INFO] [stdout]  --> src/uart0/int_event1_imask.rs:1:4866
[INFO] [stdout]   |
[INFO] [stdout] 1 | ...imask_rxint (& mut self) -> INT_EVENT1_IMASK_RXINT_W < INT_EVENT1_IMASK_SPEC , 10 > { INT_EVENT1_IMASK_RXINT_W :: new (self) } # [...
[INFO] [stdout]   |                 ^^^^^^^^^^     ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here
[INFO] [stdout]   |                 |
[INFO] [stdout]   |                 the lifetime is elided here
[INFO] [stdout]   |
[INFO] [stdout]   = help: the same lifetime is referred to in inconsistent ways, making the signature confusing
[INFO] [stdout] help: use `'_` for type paths
[INFO] [stdout]   |
[INFO] [stdout] 1 | # [doc = "Register `INT_EVENT1_IMASK` reader"] pub type R = crate :: R < INT_EVENT1_IMASK_SPEC > ; # [doc = "Register `INT_EVENT1_IMASK` writer"] pub type W = crate :: W < INT_EVENT1_IMASK_SPEC > ; # [doc = "Field `INT_EVENT1_IMASK_RTOUT` reader - Enable UARTOUT Receive Time-Out Interrupt."] pub type INT_EVENT1_IMASK_RTOUT_R = crate :: BitReader < INT_EVENT1_IMASK_RTOUT_A > ; # [doc = "Enable UARTOUT Receive Time-Out Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT1_IMASK_RTOUT_A { # [doc = "0: CLR"] INT_EVENT1_IMASK_RTOUT_CLR = 0 , # [doc = "1: SET"] INT_EVENT1_IMASK_RTOUT_SET = 1 , } impl From < INT_EVENT1_IMASK_RTOUT_A > for bool { # [inline (always)] fn from (variant : INT_EVENT1_IMASK_RTOUT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT1_IMASK_RTOUT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT1_IMASK_RTOUT_A { match self . bits { false => INT_EVENT1_IMASK_RTOUT_A :: INT_EVENT1_IMASK_RTOUT_CLR , true => INT_EVENT1_IMASK_RTOUT_A :: INT_EVENT1_IMASK_RTOUT_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event1_imask_rtout_clr (& self) -> bool { * self == INT_EVENT1_IMASK_RTOUT_A :: INT_EVENT1_IMASK_RTOUT_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event1_imask_rtout_set (& self) -> bool { * self == INT_EVENT1_IMASK_RTOUT_A :: INT_EVENT1_IMASK_RTOUT_SET } } # [doc = "Field `INT_EVENT1_IMASK_RTOUT` writer - Enable UARTOUT Receive Time-Out Interrupt."] pub type INT_EVENT1_IMASK_RTOUT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT1_IMASK_RTOUT_A > ; impl < 'a , REG , const O : u8 > INT_EVENT1_IMASK_RTOUT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event1_imask_rtout_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_IMASK_RTOUT_A :: INT_EVENT1_IMASK_RTOUT_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event1_imask_rtout_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_IMASK_RTOUT_A :: INT_EVENT1_IMASK_RTOUT_SET) } } # [doc = "Field `INT_EVENT1_IMASK_RXINT` reader - Enable UART Receive Interrupt."] pub type INT_EVENT1_IMASK_RXINT_R = crate :: BitReader < INT_EVENT1_IMASK_RXINT_A > ; # [doc = "Enable UART Receive Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT1_IMASK_RXINT_A { # [doc = "0: CLR"] INT_EVENT1_IMASK_RXINT_CLR = 0 , # [doc = "1: SET"] INT_EVENT1_IMASK_RXINT_SET = 1 , } impl From < INT_EVENT1_IMASK_RXINT_A > for bool { # [inline (always)] fn from (variant : INT_EVENT1_IMASK_RXINT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT1_IMASK_RXINT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT1_IMASK_RXINT_A { match self . bits { false => INT_EVENT1_IMASK_RXINT_A :: INT_EVENT1_IMASK_RXINT_CLR , true => INT_EVENT1_IMASK_RXINT_A :: INT_EVENT1_IMASK_RXINT_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event1_imask_rxint_clr (& self) -> bool { * self == INT_EVENT1_IMASK_RXINT_A :: INT_EVENT1_IMASK_RXINT_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event1_imask_rxint_set (& self) -> bool { * self == INT_EVENT1_IMASK_RXINT_A :: INT_EVENT1_IMASK_RXINT_SET } } # [doc = "Field `INT_EVENT1_IMASK_RXINT` writer - Enable UART Receive Interrupt."] pub type INT_EVENT1_IMASK_RXINT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT1_IMASK_RXINT_A > ; impl < 'a , REG , const O : u8 > INT_EVENT1_IMASK_RXINT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event1_imask_rxint_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_IMASK_RXINT_A :: INT_EVENT1_IMASK_RXINT_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event1_imask_rxint_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_IMASK_RXINT_A :: INT_EVENT1_IMASK_RXINT_SET) } } impl R { # [doc = "Bit 0 - Enable UARTOUT Receive Time-Out Interrupt."] # [inline (always)] pub fn int_event1_imask_rtout (& self) -> INT_EVENT1_IMASK_RTOUT_R { INT_EVENT1_IMASK_RTOUT_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 10 - Enable UART Receive Interrupt."] # [inline (always)] pub fn int_event1_imask_rxint (& self) -> INT_EVENT1_IMASK_RXINT_R { INT_EVENT1_IMASK_RXINT_R :: new (((self . bits >> 10) & 1) != 0) } } impl W { # [doc = "Bit 0 - Enable UARTOUT Receive Time-Out Interrupt."] # [inline (always)] # [must_use] pub fn int_event1_imask_rtout (& mut self) -> INT_EVENT1_IMASK_RTOUT_W < INT_EVENT1_IMASK_SPEC , 0 > { INT_EVENT1_IMASK_RTOUT_W :: new (self) } # [doc = "Bit 10 - Enable UART Receive Interrupt."] # [inline (always)] # [must_use] pub fn int_event1_imask_rxint (& mut self) -> INT_EVENT1_IMASK_RXINT_W <'_,  INT_EVENT1_IMASK_SPEC , 10 > { INT_EVENT1_IMASK_RXINT_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Interrupt mask\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_event1_imask::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_event1_imask::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct INT_EVENT1_IMASK_SPEC ; impl crate :: RegisterSpec for INT_EVENT1_IMASK_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`int_event1_imask::R`](R) reader structure"] impl crate :: Readable for INT_EVENT1_IMASK_SPEC { } # [doc = "`write(|w| ..)` method takes [`int_event1_imask::W`](W) writer structure"] impl crate :: Writable for INT_EVENT1_IMASK_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets INT_EVENT1_IMASK to value 0"] impl crate :: Resettable for INT_EVENT1_IMASK_SPEC { const RESET_VALUE : Self :: Ux = 0 ; }
[INFO] [stdout]   |                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                           +++
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing
[INFO] [stdout]  --> src/uart0/int_event0_imask.rs:1:41929
[INFO] [stdout]   |
[INFO] [stdout] 1 | ...0_imask_rxpe (& mut self) -> INT_EVENT0_IMASK_RXPE_W < INT_EVENT0_IMASK_SPEC , 6 > { INT_EVENT0_IMASK_RXPE_W :: new (self) } # [do...
[INFO] [stdout]   |                  ^^^^^^^^^^     ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here
[INFO] [stdout]   |                  |
[INFO] [stdout]   |                  the lifetime is elided here
[INFO] [stdout]   |
[INFO] [stdout]   = help: the same lifetime is referred to in inconsistent ways, making the signature confusing
[INFO] [stdout] help: use `'_` for type paths
[INFO] [stdout]   |
[INFO] [stdout] 1 | # [doc = "Register `INT_EVENT0_IMASK` reader"] pub type R = crate :: R < INT_EVENT0_IMASK_SPEC > ; # [doc = "Register `INT_EVENT0_IMASK` writer"] pub type W = crate :: W < INT_EVENT0_IMASK_SPEC > ; # [doc = "Field `INT_EVENT0_IMASK_RTOUT` reader - Enable UARTOUT Receive Time-Out Interrupt."] pub type INT_EVENT0_IMASK_RTOUT_R = crate :: BitReader < INT_EVENT0_IMASK_RTOUT_A > ; # [doc = "Enable UARTOUT Receive Time-Out Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_RTOUT_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_RTOUT_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_RTOUT_SET = 1 , } impl From < INT_EVENT0_IMASK_RTOUT_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_RTOUT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_RTOUT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_RTOUT_A { match self . bits { false => INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_CLR , true => INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_rtout_clr (& self) -> bool { * self == INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_rtout_set (& self) -> bool { * self == INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_SET } } # [doc = "Field `INT_EVENT0_IMASK_RTOUT` writer - Enable UARTOUT Receive Time-Out Interrupt."] pub type INT_EVENT0_IMASK_RTOUT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_RTOUT_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_RTOUT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_rtout_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_rtout_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_SET) } } # [doc = "Field `INT_EVENT0_IMASK_FRMERR` reader - Enable UART Framing Error Interrupt."] pub type INT_EVENT0_IMASK_FRMERR_R = crate :: BitReader < INT_EVENT0_IMASK_FRMERR_A > ; # [doc = "Enable UART Framing Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_FRMERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_FRMERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_FRMERR_SET = 1 , } impl From < INT_EVENT0_IMASK_FRMERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_FRMERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_FRMERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_FRMERR_A { match self . bits { false => INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_CLR , true => INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_frmerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_frmerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_FRMERR` writer - Enable UART Framing Error Interrupt."] pub type INT_EVENT0_IMASK_FRMERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_FRMERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_FRMERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_frmerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_frmerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_SET) } } # [doc = "Field `INT_EVENT0_IMASK_PARERR` reader - Enable UART Parity Error Interrupt."] pub type INT_EVENT0_IMASK_PARERR_R = crate :: BitReader < INT_EVENT0_IMASK_PARERR_A > ; # [doc = "Enable UART Parity Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_PARERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_PARERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_PARERR_SET = 1 , } impl From < INT_EVENT0_IMASK_PARERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_PARERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_PARERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_PARERR_A { match self . bits { false => INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_CLR , true => INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_parerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_parerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_PARERR` writer - Enable UART Parity Error Interrupt."] pub type INT_EVENT0_IMASK_PARERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_PARERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_PARERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_parerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_parerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_SET) } } # [doc = "Field `INT_EVENT0_IMASK_BRKERR` reader - Enable UART Break Error Interrupt."] pub type INT_EVENT0_IMASK_BRKERR_R = crate :: BitReader < INT_EVENT0_IMASK_BRKERR_A > ; # [doc = "Enable UART Break Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_BRKERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_BRKERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_BRKERR_SET = 1 , } impl From < INT_EVENT0_IMASK_BRKERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_BRKERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_BRKERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_BRKERR_A { match self . bits { false => INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_CLR , true => INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_brkerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_brkerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_BRKERR` writer - Enable UART Break Error Interrupt."] pub type INT_EVENT0_IMASK_BRKERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_BRKERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_BRKERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_brkerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_brkerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_SET) } } # [doc = "Field `INT_EVENT0_IMASK_OVRERR` reader - Enable UART Receive Overrun Error Interrupt."] pub type INT_EVENT0_IMASK_OVRERR_R = crate :: BitReader < INT_EVENT0_IMASK_OVRERR_A > ; # [doc = "Enable UART Receive Overrun Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_OVRERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_OVRERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_OVRERR_SET = 1 , } impl From < INT_EVENT0_IMASK_OVRERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_OVRERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_OVRERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_OVRERR_A { match self . bits { false => INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_CLR , true => INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_ovrerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_ovrerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_OVRERR` writer - Enable UART Receive Overrun Error Interrupt."] pub type INT_EVENT0_IMASK_OVRERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_OVRERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_OVRERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_ovrerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_ovrerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_SET) } } # [doc = "Field `INT_EVENT0_IMASK_RXNE` reader - Enable Negative Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_IMASK_RXNE_R = crate :: BitReader < INT_EVENT0_IMASK_RXNE_A > ; # [doc = "Enable Negative Edge on UARTxRXD Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_RXNE_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_RXNE_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_RXNE_SET = 1 , } impl From < INT_EVENT0_IMASK_RXNE_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_RXNE_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_RXNE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_RXNE_A { match self . bits { false => INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_CLR , true => INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_rxne_clr (& self) -> bool { * self == INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_rxne_set (& self) -> bool { * self == INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_SET } } # [doc = "Field `INT_EVENT0_IMASK_RXNE` writer - Enable Negative Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_IMASK_RXNE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_RXNE_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_RXNE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_rxne_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_rxne_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_SET) } } # [doc = "Field `INT_EVENT0_IMASK_RXPE` reader - Enable Positive Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_IMASK_RXPE_R = crate :: BitReader < INT_EVENT0_IMASK_RXPE_A > ; # [doc = "Enable Positive Edge on UARTxRXD Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_RXPE_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_RXPE_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_RXPE_SET = 1 , } impl From < INT_EVENT0_IMASK_RXPE_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_RXPE_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_RXPE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_RXPE_A { match self . bits { false => INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_CLR , true => INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_rxpe_clr (& self) -> bool { * self == INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_rxpe_set (& self) -> bool { * self == INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_SET } } # [doc = "Field `INT_EVENT0_IMASK_RXPE` writer - Enable Positive Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_IMASK_RXPE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_RXPE_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_RXPE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_rxpe_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_rxpe_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_SET) } } # [doc = "Field `INT_EVENT0_IMASK_LINC0` reader - Enable LIN Capture 0 / Match Interrupt ."] pub type INT_EVENT0_IMASK_LINC0_R = crate :: BitReader < INT_EVENT0_IMASK_LINC0_A > ; # [doc = "Enable LIN Capture 0 / Match Interrupt .\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_LINC0_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_LINC0_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_LINC0_SET = 1 , } impl From < INT_EVENT0_IMASK_LINC0_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_LINC0_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_LINC0_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_LINC0_A { match self . bits { false => INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_CLR , true => INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_linc0_clr (& self) -> bool { * self == INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_linc0_set (& self) -> bool { * self == INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_SET } } # [doc = "Field `INT_EVENT0_IMASK_LINC0` writer - Enable LIN Capture 0 / Match Interrupt ."] pub type INT_EVENT0_IMASK_LINC0_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_LINC0_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_LINC0_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_linc0_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_linc0_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_SET) } } # [doc = "Field `INT_EVENT0_IMASK_LINC1` reader - Enable LIN Capture 1 Interrupt."] pub type INT_EVENT0_IMASK_LINC1_R = crate :: BitReader < INT_EVENT0_IMASK_LINC1_A > ; # [doc = "Enable LIN Capture 1 Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_LINC1_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_LINC1_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_LINC1_SET = 1 , } impl From < INT_EVENT0_IMASK_LINC1_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_LINC1_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_LINC1_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_LINC1_A { match self . bits { false => INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_CLR , true => INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_linc1_clr (& self) -> bool { * self == INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_linc1_set (& self) -> bool { * self == INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_SET } } # [doc = "Field `INT_EVENT0_IMASK_LINC1` writer - Enable LIN Capture 1 Interrupt."] pub type INT_EVENT0_IMASK_LINC1_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_LINC1_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_LINC1_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_linc1_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_linc1_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_SET) } } # [doc = "Field `INT_EVENT0_IMASK_LINOVF` reader - Enable LIN Hardware Counter Overflow Interrupt."] pub type INT_EVENT0_IMASK_LINOVF_R = crate :: BitReader < INT_EVENT0_IMASK_LINOVF_A > ; # [doc = "Enable LIN Hardware Counter Overflow Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_LINOVF_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_LINOVF_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_LINOVF_SET = 1 , } impl From < INT_EVENT0_IMASK_LINOVF_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_LINOVF_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_LINOVF_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_LINOVF_A { match self . bits { false => INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_CLR , true => INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_linovf_clr (& self) -> bool { * self == INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_linovf_set (& self) -> bool { * self == INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_SET } } # [doc = "Field `INT_EVENT0_IMASK_LINOVF` writer - Enable LIN Hardware Counter Overflow Interrupt."] pub type INT_EVENT0_IMASK_LINOVF_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_LINOVF_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_LINOVF_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_linovf_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_linovf_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_SET) } } # [doc = "Field `INT_EVENT0_IMASK_RXINT` reader - Enable UART Receive Interrupt."] pub type INT_EVENT0_IMASK_RXINT_R = crate :: BitReader < INT_EVENT0_IMASK_RXINT_A > ; # [doc = "Enable UART Receive Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_RXINT_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_RXINT_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_RXINT_SET = 1 , } impl From < INT_EVENT0_IMASK_RXINT_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_RXINT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_RXINT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_RXINT_A { match self . bits { false => INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_CLR , true => INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_rxint_clr (& self) -> bool { * self == INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_rxint_set (& self) -> bool { * self == INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_SET } } # [doc = "Field `INT_EVENT0_IMASK_RXINT` writer - Enable UART Receive Interrupt."] pub type INT_EVENT0_IMASK_RXINT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_RXINT_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_RXINT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_rxint_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_rxint_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_SET) } } # [doc = "Field `INT_EVENT0_IMASK_TXINT` reader - Enable UART Transmit Interrupt."] pub type INT_EVENT0_IMASK_TXINT_R = crate :: BitReader < INT_EVENT0_IMASK_TXINT_A > ; # [doc = "Enable UART Transmit Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_TXINT_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_TXINT_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_TXINT_SET = 1 , } impl From < INT_EVENT0_IMASK_TXINT_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_TXINT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_TXINT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_TXINT_A { match self . bits { false => INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_CLR , true => INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_txint_clr (& self) -> bool { * self == INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_txint_set (& self) -> bool { * self == INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_SET } } # [doc = "Field `INT_EVENT0_IMASK_TXINT` writer - Enable UART Transmit Interrupt."] pub type INT_EVENT0_IMASK_TXINT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_TXINT_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_TXINT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_txint_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_txint_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_SET) } } # [doc = "Field `INT_EVENT0_IMASK_EOT` reader - Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] pub type INT_EVENT0_IMASK_EOT_R = crate :: BitReader < INT_EVENT0_IMASK_EOT_A > ; # [doc = "Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_EOT_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_EOT_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_EOT_SET = 1 , } impl From < INT_EVENT0_IMASK_EOT_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_EOT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_EOT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_EOT_A { match self . bits { false => INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_CLR , true => INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_eot_clr (& self) -> bool { * self == INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_eot_set (& self) -> bool { * self == INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_SET } } # [doc = "Field `INT_EVENT0_IMASK_EOT` writer - Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] pub type INT_EVENT0_IMASK_EOT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_EOT_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_EOT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_eot_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_eot_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_SET) } } # [doc = "Field `INT_EVENT0_IMASK_ADDR_MATCH` reader - Enable Address Match Interrupt."] pub type INT_EVENT0_IMASK_ADDR_MATCH_R = crate :: BitReader < INT_EVENT0_IMASK_ADDR_MATCH_A > ; # [doc = "Enable Address Match Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_ADDR_MATCH_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_ADDR_MATCH_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_ADDR_MATCH_SET = 1 , } impl From < INT_EVENT0_IMASK_ADDR_MATCH_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_ADDR_MATCH_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_ADDR_MATCH_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_ADDR_MATCH_A { match self . bits { false => INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_CLR , true => INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_addr_match_clr (& self) -> bool { * self == INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_addr_match_set (& self) -> bool { * self == INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_SET } } # [doc = "Field `INT_EVENT0_IMASK_ADDR_MATCH` writer - Enable Address Match Interrupt."] pub type INT_EVENT0_IMASK_ADDR_MATCH_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_ADDR_MATCH_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_ADDR_MATCH_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_addr_match_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_addr_match_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_SET) } } # [doc = "Field `INT_EVENT0_IMASK_CTS` reader - Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] pub type INT_EVENT0_IMASK_CTS_R = crate :: BitReader < INT_EVENT0_IMASK_CTS_A > ; # [doc = "Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_CTS_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_CTS_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_CTS_SET = 1 , } impl From < INT_EVENT0_IMASK_CTS_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_CTS_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_CTS_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_CTS_A { match self . bits { false => INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_CLR , true => INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_cts_clr (& self) -> bool { * self == INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_cts_set (& self) -> bool { * self == INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_SET } } # [doc = "Field `INT_EVENT0_IMASK_CTS` writer - Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] pub type INT_EVENT0_IMASK_CTS_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_CTS_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_CTS_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_cts_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_cts_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DMA_DONE_RX` reader - Enable DMA Done on RX Event Channel"] pub type INT_EVENT0_IMASK_DMA_DONE_RX_R = crate :: BitReader < INT_EVENT0_IMASK_DMA_DONE_RX_A > ; # [doc = "Enable DMA Done on RX Event Channel\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DMA_DONE_RX_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DMA_DONE_RX_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DMA_DONE_RX_SET = 1 , } impl From < INT_EVENT0_IMASK_DMA_DONE_RX_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DMA_DONE_RX_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DMA_DONE_RX_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DMA_DONE_RX_A { match self . bits { false => INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_CLR , true => INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dma_done_rx_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dma_done_rx_set (& self) -> bool { * self == INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_SET } } # [doc = "Field `INT_EVENT0_IMASK_DMA_DONE_RX` writer - Enable DMA Done on RX Event Channel"] pub type INT_EVENT0_IMASK_DMA_DONE_RX_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DMA_DONE_RX_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DMA_DONE_RX_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dma_done_rx_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dma_done_rx_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DMA_DONE_TX` reader - Enable DMA Done on TX Event Channel"] pub type INT_EVENT0_IMASK_DMA_DONE_TX_R = crate :: BitReader < INT_EVENT0_IMASK_DMA_DONE_TX_A > ; # [doc = "Enable DMA Done on TX Event Channel\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DMA_DONE_TX_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DMA_DONE_TX_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DMA_DONE_TX_SET = 1 , } impl From < INT_EVENT0_IMASK_DMA_DONE_TX_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DMA_DONE_TX_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DMA_DONE_TX_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DMA_DONE_TX_A { match self . bits { false => INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_CLR , true => INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dma_done_tx_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dma_done_tx_set (& self) -> bool { * self == INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_SET } } # [doc = "Field `INT_EVENT0_IMASK_DMA_DONE_TX` writer - Enable DMA Done on TX Event Channel"] pub type INT_EVENT0_IMASK_DMA_DONE_TX_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DMA_DONE_TX_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DMA_DONE_TX_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dma_done_tx_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dma_done_tx_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_SET) } } # [doc = "Field `INT_EVENT0_IMASK_NERR` reader - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] pub type INT_EVENT0_IMASK_NERR_R = crate :: BitReader < INT_EVENT0_IMASK_NERR_A > ; # [doc = "Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_NERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_NERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_NERR_SET = 1 , } impl From < INT_EVENT0_IMASK_NERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_NERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_NERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_NERR_A { match self . bits { false => INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_CLR , true => INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_nerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_nerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_NERR` writer - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] pub type INT_EVENT0_IMASK_NERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_NERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_NERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_nerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_nerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_SET) } } impl R { # [doc = "Bit 0 - Enable UARTOUT Receive Time-Out Interrupt."] # [inline (always)] pub fn int_event0_imask_rtout (& self) -> INT_EVENT0_IMASK_RTOUT_R { INT_EVENT0_IMASK_RTOUT_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - Enable UART Framing Error Interrupt."] # [inline (always)] pub fn int_event0_imask_frmerr (& self) -> INT_EVENT0_IMASK_FRMERR_R { INT_EVENT0_IMASK_FRMERR_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - Enable UART Parity Error Interrupt."] # [inline (always)] pub fn int_event0_imask_parerr (& self) -> INT_EVENT0_IMASK_PARERR_R { INT_EVENT0_IMASK_PARERR_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - Enable UART Break Error Interrupt."] # [inline (always)] pub fn int_event0_imask_brkerr (& self) -> INT_EVENT0_IMASK_BRKERR_R { INT_EVENT0_IMASK_BRKERR_R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - Enable UART Receive Overrun Error Interrupt."] # [inline (always)] pub fn int_event0_imask_ovrerr (& self) -> INT_EVENT0_IMASK_OVRERR_R { INT_EVENT0_IMASK_OVRERR_R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - Enable Negative Edge on UARTxRXD Interrupt."] # [inline (always)] pub fn int_event0_imask_rxne (& self) -> INT_EVENT0_IMASK_RXNE_R { INT_EVENT0_IMASK_RXNE_R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - Enable Positive Edge on UARTxRXD Interrupt."] # [inline (always)] pub fn int_event0_imask_rxpe (& self) -> INT_EVENT0_IMASK_RXPE_R { INT_EVENT0_IMASK_RXPE_R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - Enable LIN Capture 0 / Match Interrupt ."] # [inline (always)] pub fn int_event0_imask_linc0 (& self) -> INT_EVENT0_IMASK_LINC0_R { INT_EVENT0_IMASK_LINC0_R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - Enable LIN Capture 1 Interrupt."] # [inline (always)] pub fn int_event0_imask_linc1 (& self) -> INT_EVENT0_IMASK_LINC1_R { INT_EVENT0_IMASK_LINC1_R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - Enable LIN Hardware Counter Overflow Interrupt."] # [inline (always)] pub fn int_event0_imask_linovf (& self) -> INT_EVENT0_IMASK_LINOVF_R { INT_EVENT0_IMASK_LINOVF_R :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - Enable UART Receive Interrupt."] # [inline (always)] pub fn int_event0_imask_rxint (& self) -> INT_EVENT0_IMASK_RXINT_R { INT_EVENT0_IMASK_RXINT_R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - Enable UART Transmit Interrupt."] # [inline (always)] pub fn int_event0_imask_txint (& self) -> INT_EVENT0_IMASK_TXINT_R { INT_EVENT0_IMASK_TXINT_R :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] # [inline (always)] pub fn int_event0_imask_eot (& self) -> INT_EVENT0_IMASK_EOT_R { INT_EVENT0_IMASK_EOT_R :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - Enable Address Match Interrupt."] # [inline (always)] pub fn int_event0_imask_addr_match (& self) -> INT_EVENT0_IMASK_ADDR_MATCH_R { INT_EVENT0_IMASK_ADDR_MATCH_R :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 14 - Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] # [inline (always)] pub fn int_event0_imask_cts (& self) -> INT_EVENT0_IMASK_CTS_R { INT_EVENT0_IMASK_CTS_R :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - Enable DMA Done on RX Event Channel"] # [inline (always)] pub fn int_event0_imask_dma_done_rx (& self) -> INT_EVENT0_IMASK_DMA_DONE_RX_R { INT_EVENT0_IMASK_DMA_DONE_RX_R :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bit 16 - Enable DMA Done on TX Event Channel"] # [inline (always)] pub fn int_event0_imask_dma_done_tx (& self) -> INT_EVENT0_IMASK_DMA_DONE_TX_R { INT_EVENT0_IMASK_DMA_DONE_TX_R :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] # [inline (always)] pub fn int_event0_imask_nerr (& self) -> INT_EVENT0_IMASK_NERR_R { INT_EVENT0_IMASK_NERR_R :: new (((self . bits >> 17) & 1) != 0) } } impl W { # [doc = "Bit 0 - Enable UARTOUT Receive Time-Out Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_rtout (& mut self) -> INT_EVENT0_IMASK_RTOUT_W < INT_EVENT0_IMASK_SPEC , 0 > { INT_EVENT0_IMASK_RTOUT_W :: new (self) } # [doc = "Bit 1 - Enable UART Framing Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_frmerr (& mut self) -> INT_EVENT0_IMASK_FRMERR_W < INT_EVENT0_IMASK_SPEC , 1 > { INT_EVENT0_IMASK_FRMERR_W :: new (self) } # [doc = "Bit 2 - Enable UART Parity Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_parerr (& mut self) -> INT_EVENT0_IMASK_PARERR_W < INT_EVENT0_IMASK_SPEC , 2 > { INT_EVENT0_IMASK_PARERR_W :: new (self) } # [doc = "Bit 3 - Enable UART Break Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_brkerr (& mut self) -> INT_EVENT0_IMASK_BRKERR_W < INT_EVENT0_IMASK_SPEC , 3 > { INT_EVENT0_IMASK_BRKERR_W :: new (self) } # [doc = "Bit 4 - Enable UART Receive Overrun Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_ovrerr (& mut self) -> INT_EVENT0_IMASK_OVRERR_W < INT_EVENT0_IMASK_SPEC , 4 > { INT_EVENT0_IMASK_OVRERR_W :: new (self) } # [doc = "Bit 5 - Enable Negative Edge on UARTxRXD Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_rxne (& mut self) -> INT_EVENT0_IMASK_RXNE_W < INT_EVENT0_IMASK_SPEC , 5 > { INT_EVENT0_IMASK_RXNE_W :: new (self) } # [doc = "Bit 6 - Enable Positive Edge on UARTxRXD Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_rxpe (& mut self) -> INT_EVENT0_IMASK_RXPE_W <'_,  INT_EVENT0_IMASK_SPEC , 6 > { INT_EVENT0_IMASK_RXPE_W :: new (self) } # [doc = "Bit 7 - Enable LIN Capture 0 / Match Interrupt ."] # [inline (always)] # [must_use] pub fn int_event0_imask_linc0 (& mut self) -> INT_EVENT0_IMASK_LINC0_W < INT_EVENT0_IMASK_SPEC , 7 > { INT_EVENT0_IMASK_LINC0_W :: new (self) } # [doc = "Bit 8 - Enable LIN Capture 1 Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_linc1 (& mut self) -> INT_EVENT0_IMASK_LINC1_W < INT_EVENT0_IMASK_SPEC , 8 > { INT_EVENT0_IMASK_LINC1_W :: new (self) } # [doc = "Bit 9 - Enable LIN Hardware Counter Overflow Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_linovf (& mut self) -> INT_EVENT0_IMASK_LINOVF_W < INT_EVENT0_IMASK_SPEC , 9 > { INT_EVENT0_IMASK_LINOVF_W :: new (self) } # [doc = "Bit 10 - Enable UART Receive Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_rxint (& mut self) -> INT_EVENT0_IMASK_RXINT_W < INT_EVENT0_IMASK_SPEC , 10 > { INT_EVENT0_IMASK_RXINT_W :: new (self) } # [doc = "Bit 11 - Enable UART Transmit Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_txint (& mut self) -> INT_EVENT0_IMASK_TXINT_W < INT_EVENT0_IMASK_SPEC , 11 > { INT_EVENT0_IMASK_TXINT_W :: new (self) } # [doc = "Bit 12 - Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] # [inline (always)] # [must_use] pub fn int_event0_imask_eot (& mut self) -> INT_EVENT0_IMASK_EOT_W < INT_EVENT0_IMASK_SPEC , 12 > { INT_EVENT0_IMASK_EOT_W :: new (self) } # [doc = "Bit 13 - Enable Address Match Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_addr_match (& mut self) -> INT_EVENT0_IMASK_ADDR_MATCH_W < INT_EVENT0_IMASK_SPEC , 13 > { INT_EVENT0_IMASK_ADDR_MATCH_W :: new (self) } # [doc = "Bit 14 - Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] # [inline (always)] # [must_use] pub fn int_event0_imask_cts (& mut self) -> INT_EVENT0_IMASK_CTS_W < INT_EVENT0_IMASK_SPEC , 14 > { INT_EVENT0_IMASK_CTS_W :: new (self) } # [doc = "Bit 15 - Enable DMA Done on RX Event Channel"] # [inline (always)] # [must_use] pub fn int_event0_imask_dma_done_rx (& mut self) -> INT_EVENT0_IMASK_DMA_DONE_RX_W < INT_EVENT0_IMASK_SPEC , 15 > { INT_EVENT0_IMASK_DMA_DONE_RX_W :: new (self) } # [doc = "Bit 16 - Enable DMA Done on TX Event Channel"] # [inline (always)] # [must_use] pub fn int_event0_imask_dma_done_tx (& mut self) -> INT_EVENT0_IMASK_DMA_DONE_TX_W < INT_EVENT0_IMASK_SPEC , 16 > { INT_EVENT0_IMASK_DMA_DONE_TX_W :: new (self) } # [doc = "Bit 17 - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] # [inline (always)] # [must_use] pub fn int_event0_imask_nerr (& mut self) -> INT_EVENT0_IMASK_NERR_W < INT_EVENT0_IMASK_SPEC , 17 > { INT_EVENT0_IMASK_NERR_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Interrupt mask\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_event0_imask::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_event0_imask::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct INT_EVENT0_IMASK_SPEC ; impl crate :: RegisterSpec for INT_EVENT0_IMASK_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`int_event0_imask::R`](R) reader structure"] impl crate :: Readable for INT_EVENT0_IMASK_SPEC { } # [doc = "`write(|w| ..)` method takes [`int_event0_imask::W`](W) writer structure"] impl crate :: Writable for INT_EVENT0_IMASK_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets INT_EVENT0_IMASK to value 0"] impl crate :: Resettable for INT_EVENT0_IMASK_SPEC { const RESET_VALUE : Self :: Ux = 0 ; }
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                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                  +++
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing
[INFO] [stdout]  --> src/uart0/int_event1_iset.rs:1:2524
[INFO] [stdout]   |
[INFO] [stdout] 1 | ...t1_iset_rtout (& mut self) -> INT_EVENT1_ISET_RTOUT_W < INT_EVENT1_ISET_SPEC , 0 > { INT_EVENT1_ISET_RTOUT_W :: new (self) } # [do...
[INFO] [stdout]   |                   ^^^^^^^^^^     ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here
[INFO] [stdout]   |                   |
[INFO] [stdout]   |                   the lifetime is elided here
[INFO] [stdout]   |
[INFO] [stdout]   = help: the same lifetime is referred to in inconsistent ways, making the signature confusing
[INFO] [stdout] help: use `'_` for type paths
[INFO] [stdout]   |
[INFO] [stdout] 1 | # [doc = "Register `INT_EVENT1_ISET` writer"] pub type W = crate :: W < INT_EVENT1_ISET_SPEC > ; # [doc = "Set UARTOUT Receive Time-Out Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT1_ISET_RTOUT_AW { # [doc = "0: NO_EFFECT"] INT_EVENT1_ISET_RTOUT_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT1_ISET_RTOUT_SET = 1 , } impl From < INT_EVENT1_ISET_RTOUT_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT1_ISET_RTOUT_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT1_ISET_RTOUT` writer - Set UARTOUT Receive Time-Out Interrupt."] pub type INT_EVENT1_ISET_RTOUT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT1_ISET_RTOUT_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT1_ISET_RTOUT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event1_iset_rtout_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_ISET_RTOUT_AW :: INT_EVENT1_ISET_RTOUT_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event1_iset_rtout_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_ISET_RTOUT_AW :: INT_EVENT1_ISET_RTOUT_SET) } } # [doc = "Set UART Receive Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT1_ISET_RXINT_AW { # [doc = "0: NO_EFFECT"] INT_EVENT1_ISET_RXINT_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT1_ISET_RXINT_SET = 1 , } impl From < INT_EVENT1_ISET_RXINT_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT1_ISET_RXINT_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT1_ISET_RXINT` writer - Set UART Receive Interrupt."] pub type INT_EVENT1_ISET_RXINT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT1_ISET_RXINT_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT1_ISET_RXINT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event1_iset_rxint_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_ISET_RXINT_AW :: INT_EVENT1_ISET_RXINT_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event1_iset_rxint_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_ISET_RXINT_AW :: INT_EVENT1_ISET_RXINT_SET) } } impl W { # [doc = "Bit 0 - Set UARTOUT Receive Time-Out Interrupt."] # [inline (always)] # [must_use] pub fn int_event1_iset_rtout (& mut self) -> INT_EVENT1_ISET_RTOUT_W <'_,  INT_EVENT1_ISET_SPEC , 0 > { INT_EVENT1_ISET_RTOUT_W :: new (self) } # [doc = "Bit 10 - Set UART Receive Interrupt."] # [inline (always)] # [must_use] pub fn int_event1_iset_rxint (& mut self) -> INT_EVENT1_ISET_RXINT_W < INT_EVENT1_ISET_SPEC , 10 > { INT_EVENT1_ISET_RXINT_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Interrupt set\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_event1_iset::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct INT_EVENT1_ISET_SPEC ; impl crate :: RegisterSpec for INT_EVENT1_ISET_SPEC { type Ux = u32 ; } # [doc = "`write(|w| ..)` method takes [`int_event1_iset::W`](W) writer structure"] impl crate :: Writable for INT_EVENT1_ISET_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets INT_EVENT1_ISET to value 0"] impl crate :: Resettable for INT_EVENT1_ISET_SPEC { const RESET_VALUE : Self :: Ux = 0 ; }
[INFO] [stdout]   |                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                    +++
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing
[INFO] [stdout]  --> src/uart0/int_event1_iset.rs:1:2746
[INFO] [stdout]   |
[INFO] [stdout] 1 | ...1_iset_rxint (& mut self) -> INT_EVENT1_ISET_RXINT_W < INT_EVENT1_ISET_SPEC , 10 > { INT_EVENT1_ISET_RXINT_W :: new (self) } # [do...
[INFO] [stdout]   |                  ^^^^^^^^^^     ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here
[INFO] [stdout]   |                  |
[INFO] [stdout]   |                  the lifetime is elided here
[INFO] [stdout]   |
[INFO] [stdout]   = help: the same lifetime is referred to in inconsistent ways, making the signature confusing
[INFO] [stdout] help: use `'_` for type paths
[INFO] [stdout]   |
[INFO] [stdout] 1 | # [doc = "Register `INT_EVENT1_ISET` writer"] pub type W = crate :: W < INT_EVENT1_ISET_SPEC > ; # [doc = "Set UARTOUT Receive Time-Out Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT1_ISET_RTOUT_AW { # [doc = "0: NO_EFFECT"] INT_EVENT1_ISET_RTOUT_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT1_ISET_RTOUT_SET = 1 , } impl From < INT_EVENT1_ISET_RTOUT_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT1_ISET_RTOUT_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT1_ISET_RTOUT` writer - Set UARTOUT Receive Time-Out Interrupt."] pub type INT_EVENT1_ISET_RTOUT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT1_ISET_RTOUT_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT1_ISET_RTOUT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event1_iset_rtout_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_ISET_RTOUT_AW :: INT_EVENT1_ISET_RTOUT_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event1_iset_rtout_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_ISET_RTOUT_AW :: INT_EVENT1_ISET_RTOUT_SET) } } # [doc = "Set UART Receive Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT1_ISET_RXINT_AW { # [doc = "0: NO_EFFECT"] INT_EVENT1_ISET_RXINT_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT1_ISET_RXINT_SET = 1 , } impl From < INT_EVENT1_ISET_RXINT_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT1_ISET_RXINT_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT1_ISET_RXINT` writer - Set UART Receive Interrupt."] pub type INT_EVENT1_ISET_RXINT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT1_ISET_RXINT_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT1_ISET_RXINT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event1_iset_rxint_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_ISET_RXINT_AW :: INT_EVENT1_ISET_RXINT_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event1_iset_rxint_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_ISET_RXINT_AW :: INT_EVENT1_ISET_RXINT_SET) } } impl W { # [doc = "Bit 0 - Set UARTOUT Receive Time-Out Interrupt."] # [inline (always)] # [must_use] pub fn int_event1_iset_rtout (& mut self) -> INT_EVENT1_ISET_RTOUT_W < INT_EVENT1_ISET_SPEC , 0 > { INT_EVENT1_ISET_RTOUT_W :: new (self) } # [doc = "Bit 10 - Set UART Receive Interrupt."] # [inline (always)] # [must_use] pub fn int_event1_iset_rxint (& mut self) -> INT_EVENT1_ISET_RXINT_W <'_,  INT_EVENT1_ISET_SPEC , 10 > { INT_EVENT1_ISET_RXINT_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Interrupt set\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_event1_iset::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct INT_EVENT1_ISET_SPEC ; impl crate :: RegisterSpec for INT_EVENT1_ISET_SPEC { type Ux = u32 ; } # [doc = "`write(|w| ..)` method takes [`int_event1_iset::W`](W) writer structure"] impl crate :: Writable for INT_EVENT1_ISET_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets INT_EVENT1_ISET to value 0"] impl crate :: Resettable for INT_EVENT1_ISET_SPEC { const RESET_VALUE : Self :: Ux = 0 ; }
[INFO] [stdout]   |                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                  +++
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing
[INFO] [stdout]  --> src/uart0/int_event1_iclr.rs:1:2534
[INFO] [stdout]   |
[INFO] [stdout] 1 | ...t1_iclr_rtout (& mut self) -> INT_EVENT1_ICLR_RTOUT_W < INT_EVENT1_ICLR_SPEC , 0 > { INT_EVENT1_ICLR_RTOUT_W :: new (self) } # [do...
[INFO] [stdout]   |                   ^^^^^^^^^^     ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here
[INFO] [stdout]   |                   |
[INFO] [stdout]   |                   the lifetime is elided here
[INFO] [stdout]   |
[INFO] [stdout]   = help: the same lifetime is referred to in inconsistent ways, making the signature confusing
[INFO] [stdout] help: use `'_` for type paths
[INFO] [stdout]   |
[INFO] [stdout] 1 | # [doc = "Register `INT_EVENT1_ICLR` writer"] pub type W = crate :: W < INT_EVENT1_ICLR_SPEC > ; # [doc = "Clear UARTOUT Receive Time-Out Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT1_ICLR_RTOUT_AW { # [doc = "0: NO_EFFECT"] INT_EVENT1_ICLR_RTOUT_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT1_ICLR_RTOUT_CLR = 1 , } impl From < INT_EVENT1_ICLR_RTOUT_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT1_ICLR_RTOUT_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT1_ICLR_RTOUT` writer - Clear UARTOUT Receive Time-Out Interrupt."] pub type INT_EVENT1_ICLR_RTOUT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT1_ICLR_RTOUT_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT1_ICLR_RTOUT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event1_iclr_rtout_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_ICLR_RTOUT_AW :: INT_EVENT1_ICLR_RTOUT_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event1_iclr_rtout_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_ICLR_RTOUT_AW :: INT_EVENT1_ICLR_RTOUT_CLR) } } # [doc = "Clear UART Receive Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT1_ICLR_RXINT_AW { # [doc = "0: NO_EFFECT"] INT_EVENT1_ICLR_RXINT_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT1_ICLR_RXINT_CLR = 1 , } impl From < INT_EVENT1_ICLR_RXINT_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT1_ICLR_RXINT_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT1_ICLR_RXINT` writer - Clear UART Receive Interrupt."] pub type INT_EVENT1_ICLR_RXINT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT1_ICLR_RXINT_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT1_ICLR_RXINT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event1_iclr_rxint_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_ICLR_RXINT_AW :: INT_EVENT1_ICLR_RXINT_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event1_iclr_rxint_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_ICLR_RXINT_AW :: INT_EVENT1_ICLR_RXINT_CLR) } } impl W { # [doc = "Bit 0 - Clear UARTOUT Receive Time-Out Interrupt."] # [inline (always)] # [must_use] pub fn int_event1_iclr_rtout (& mut self) -> INT_EVENT1_ICLR_RTOUT_W <'_,  INT_EVENT1_ICLR_SPEC , 0 > { INT_EVENT1_ICLR_RTOUT_W :: new (self) } # [doc = "Bit 10 - Clear UART Receive Interrupt."] # [inline (always)] # [must_use] pub fn int_event1_iclr_rxint (& mut self) -> INT_EVENT1_ICLR_RXINT_W < INT_EVENT1_ICLR_SPEC , 10 > { INT_EVENT1_ICLR_RXINT_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Interrupt clear\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_event1_iclr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct INT_EVENT1_ICLR_SPEC ; impl crate :: RegisterSpec for INT_EVENT1_ICLR_SPEC { type Ux = u32 ; } # [doc = "`write(|w| ..)` method takes [`int_event1_iclr::W`](W) writer structure"] impl crate :: Writable for INT_EVENT1_ICLR_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets INT_EVENT1_ICLR to value 0"] impl crate :: Resettable for INT_EVENT1_ICLR_SPEC { const RESET_VALUE : Self :: Ux = 0 ; }
[INFO] [stdout]   |                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                              +++
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing
[INFO] [stdout]  --> src/uart0/int_event1_iclr.rs:1:2758
[INFO] [stdout]   |
[INFO] [stdout] 1 | ...1_iclr_rxint (& mut self) -> INT_EVENT1_ICLR_RXINT_W < INT_EVENT1_ICLR_SPEC , 10 > { INT_EVENT1_ICLR_RXINT_W :: new (self) } # [do...
[INFO] [stdout]   |                  ^^^^^^^^^^     ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here
[INFO] [stdout]   |                  |
[INFO] [stdout]   |                  the lifetime is elided here
[INFO] [stdout]   |
[INFO] [stdout]   = help: the same lifetime is referred to in inconsistent ways, making the signature confusing
[INFO] [stdout] help: use `'_` for type paths
[INFO] [stdout]   |
[INFO] [stdout] 1 | # [doc = "Register `INT_EVENT1_ICLR` writer"] pub type W = crate :: W < INT_EVENT1_ICLR_SPEC > ; # [doc = "Clear UARTOUT Receive Time-Out Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT1_ICLR_RTOUT_AW { # [doc = "0: NO_EFFECT"] INT_EVENT1_ICLR_RTOUT_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT1_ICLR_RTOUT_CLR = 1 , } impl From < INT_EVENT1_ICLR_RTOUT_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT1_ICLR_RTOUT_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT1_ICLR_RTOUT` writer - Clear UARTOUT Receive Time-Out Interrupt."] pub type INT_EVENT1_ICLR_RTOUT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT1_ICLR_RTOUT_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT1_ICLR_RTOUT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event1_iclr_rtout_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_ICLR_RTOUT_AW :: INT_EVENT1_ICLR_RTOUT_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event1_iclr_rtout_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_ICLR_RTOUT_AW :: INT_EVENT1_ICLR_RTOUT_CLR) } } # [doc = "Clear UART Receive Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT1_ICLR_RXINT_AW { # [doc = "0: NO_EFFECT"] INT_EVENT1_ICLR_RXINT_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT1_ICLR_RXINT_CLR = 1 , } impl From < INT_EVENT1_ICLR_RXINT_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT1_ICLR_RXINT_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT1_ICLR_RXINT` writer - Clear UART Receive Interrupt."] pub type INT_EVENT1_ICLR_RXINT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT1_ICLR_RXINT_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT1_ICLR_RXINT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event1_iclr_rxint_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_ICLR_RXINT_AW :: INT_EVENT1_ICLR_RXINT_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event1_iclr_rxint_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_ICLR_RXINT_AW :: INT_EVENT1_ICLR_RXINT_CLR) } } impl W { # [doc = "Bit 0 - Clear UARTOUT Receive Time-Out Interrupt."] # [inline (always)] # [must_use] pub fn int_event1_iclr_rtout (& mut self) -> INT_EVENT1_ICLR_RTOUT_W < INT_EVENT1_ICLR_SPEC , 0 > { INT_EVENT1_ICLR_RTOUT_W :: new (self) } # [doc = "Bit 10 - Clear UART Receive Interrupt."] # [inline (always)] # [must_use] pub fn int_event1_iclr_rxint (& mut self) -> INT_EVENT1_ICLR_RXINT_W <'_,  INT_EVENT1_ICLR_SPEC , 10 > { INT_EVENT1_ICLR_RXINT_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Interrupt clear\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_event1_iclr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct INT_EVENT1_ICLR_SPEC ; impl crate :: RegisterSpec for INT_EVENT1_ICLR_SPEC { type Ux = u32 ; } # [doc = "`write(|w| ..)` method takes [`int_event1_iclr::W`](W) writer structure"] impl crate :: Writable for INT_EVENT1_ICLR_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets INT_EVENT1_ICLR to value 0"] impl crate :: Resettable for INT_EVENT1_ICLR_SPEC { const RESET_VALUE : Self :: Ux = 0 ; }
[INFO] [stdout]   |                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                              +++
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing
[INFO] [stdout]  --> src/uart0/int_event2_imask.rs:1:2466
[INFO] [stdout]   |
[INFO] [stdout] 1 | ...imask_txint (& mut self) -> INT_EVENT2_IMASK_TXINT_W < INT_EVENT2_IMASK_SPEC , 11 > { INT_EVENT2_IMASK_TXINT_W :: new (self) } # [...
[INFO] [stdout]   |                 ^^^^^^^^^^     ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here
[INFO] [stdout]   |                 |
[INFO] [stdout]   |                 the lifetime is elided here
[INFO] [stdout]   |
[INFO] [stdout]   = help: the same lifetime is referred to in inconsistent ways, making the signature confusing
[INFO] [stdout] help: use `'_` for type paths
[INFO] [stdout]   |
[INFO] [stdout] 1 | # [doc = "Register `INT_EVENT2_IMASK` reader"] pub type R = crate :: R < INT_EVENT2_IMASK_SPEC > ; # [doc = "Register `INT_EVENT2_IMASK` writer"] pub type W = crate :: W < INT_EVENT2_IMASK_SPEC > ; # [doc = "Field `INT_EVENT2_IMASK_TXINT` reader - Enable UART Transmit Interrupt."] pub type INT_EVENT2_IMASK_TXINT_R = crate :: BitReader < INT_EVENT2_IMASK_TXINT_A > ; # [doc = "Enable UART Transmit Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT2_IMASK_TXINT_A { # [doc = "0: CLR"] INT_EVENT2_IMASK_TXINT_CLR = 0 , # [doc = "1: SET"] INT_EVENT2_IMASK_TXINT_SET = 1 , } impl From < INT_EVENT2_IMASK_TXINT_A > for bool { # [inline (always)] fn from (variant : INT_EVENT2_IMASK_TXINT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT2_IMASK_TXINT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT2_IMASK_TXINT_A { match self . bits { false => INT_EVENT2_IMASK_TXINT_A :: INT_EVENT2_IMASK_TXINT_CLR , true => INT_EVENT2_IMASK_TXINT_A :: INT_EVENT2_IMASK_TXINT_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event2_imask_txint_clr (& self) -> bool { * self == INT_EVENT2_IMASK_TXINT_A :: INT_EVENT2_IMASK_TXINT_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event2_imask_txint_set (& self) -> bool { * self == INT_EVENT2_IMASK_TXINT_A :: INT_EVENT2_IMASK_TXINT_SET } } # [doc = "Field `INT_EVENT2_IMASK_TXINT` writer - Enable UART Transmit Interrupt."] pub type INT_EVENT2_IMASK_TXINT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT2_IMASK_TXINT_A > ; impl < 'a , REG , const O : u8 > INT_EVENT2_IMASK_TXINT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event2_imask_txint_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT2_IMASK_TXINT_A :: INT_EVENT2_IMASK_TXINT_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event2_imask_txint_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT2_IMASK_TXINT_A :: INT_EVENT2_IMASK_TXINT_SET) } } impl R { # [doc = "Bit 11 - Enable UART Transmit Interrupt."] # [inline (always)] pub fn int_event2_imask_txint (& self) -> INT_EVENT2_IMASK_TXINT_R { INT_EVENT2_IMASK_TXINT_R :: new (((self . bits >> 11) & 1) != 0) } } impl W { # [doc = "Bit 11 - Enable UART Transmit Interrupt."] # [inline (always)] # [must_use] pub fn int_event2_imask_txint (& mut self) -> INT_EVENT2_IMASK_TXINT_W <'_,  INT_EVENT2_IMASK_SPEC , 11 > { INT_EVENT2_IMASK_TXINT_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Interrupt mask\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_event2_imask::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_event2_imask::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct INT_EVENT2_IMASK_SPEC ; impl crate :: RegisterSpec for INT_EVENT2_IMASK_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`int_event2_imask::R`](R) reader structure"] impl crate :: Readable for INT_EVENT2_IMASK_SPEC { } # [doc = "`write(|w| ..)` method takes [`int_event2_imask::W`](W) writer structure"] impl crate :: Writable for INT_EVENT2_IMASK_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets INT_EVENT2_IMASK to value 0"] impl crate :: Resettable for INT_EVENT2_IMASK_SPEC { const RESET_VALUE : Self :: Ux = 0 ; }
[INFO] [stdout]   |                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                           +++
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing
[INFO] [stdout]  --> src/uart0/int_event2_iset.rs:1:1357
[INFO] [stdout]   |
[INFO] [stdout] 1 | ...2_iset_txint (& mut self) -> INT_EVENT2_ISET_TXINT_W < INT_EVENT2_ISET_SPEC , 11 > { INT_EVENT2_ISET_TXINT_W :: new (self) } # [do...
[INFO] [stdout]   |                  ^^^^^^^^^^     ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here
[INFO] [stdout]   |                  |
[INFO] [stdout]   |                  the lifetime is elided here
[INFO] [stdout]   |
[INFO] [stdout]   = help: the same lifetime is referred to in inconsistent ways, making the signature confusing
[INFO] [stdout] help: use `'_` for type paths
[INFO] [stdout]   |
[INFO] [stdout] 1 | # [doc = "Register `INT_EVENT2_ISET` writer"] pub type W = crate :: W < INT_EVENT2_ISET_SPEC > ; # [doc = "Set UART Transmit Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT2_ISET_TXINT_AW { # [doc = "0: NO_EFFECT"] INT_EVENT2_ISET_TXINT_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT2_ISET_TXINT_SET = 1 , } impl From < INT_EVENT2_ISET_TXINT_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT2_ISET_TXINT_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT2_ISET_TXINT` writer - Set UART Transmit Interrupt."] pub type INT_EVENT2_ISET_TXINT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT2_ISET_TXINT_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT2_ISET_TXINT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event2_iset_txint_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT2_ISET_TXINT_AW :: INT_EVENT2_ISET_TXINT_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event2_iset_txint_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT2_ISET_TXINT_AW :: INT_EVENT2_ISET_TXINT_SET) } } impl W { # [doc = "Bit 11 - Set UART Transmit Interrupt."] # [inline (always)] # [must_use] pub fn int_event2_iset_txint (& mut self) -> INT_EVENT2_ISET_TXINT_W <'_,  INT_EVENT2_ISET_SPEC , 11 > { INT_EVENT2_ISET_TXINT_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Interrupt set\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_event2_iset::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct INT_EVENT2_ISET_SPEC ; impl crate :: RegisterSpec for INT_EVENT2_ISET_SPEC { type Ux = u32 ; } # [doc = "`write(|w| ..)` method takes [`int_event2_iset::W`](W) writer structure"] impl crate :: Writable for INT_EVENT2_ISET_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets INT_EVENT2_ISET to value 0"] impl crate :: Resettable for INT_EVENT2_ISET_SPEC { const RESET_VALUE : Self :: Ux = 0 ; }
[INFO] [stdout]   |                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                     +++
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing
[INFO] [stdout]  --> src/uart0/int_event2_iclr.rs:1:1363
[INFO] [stdout]   |
[INFO] [stdout] 1 | ...2_iclr_txint (& mut self) -> INT_EVENT2_ICLR_TXINT_W < INT_EVENT2_ICLR_SPEC , 11 > { INT_EVENT2_ICLR_TXINT_W :: new (self) } # [do...
[INFO] [stdout]   |                  ^^^^^^^^^^     ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here
[INFO] [stdout]   |                  |
[INFO] [stdout]   |                  the lifetime is elided here
[INFO] [stdout]   |
[INFO] [stdout]   = help: the same lifetime is referred to in inconsistent ways, making the signature confusing
[INFO] [stdout] help: use `'_` for type paths
[INFO] [stdout]   |
[INFO] [stdout] 1 | # [doc = "Register `INT_EVENT2_ICLR` writer"] pub type W = crate :: W < INT_EVENT2_ICLR_SPEC > ; # [doc = "Clear UART Transmit Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT2_ICLR_TXINT_AW { # [doc = "0: NO_EFFECT"] INT_EVENT2_ICLR_TXINT_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT2_ICLR_TXINT_CLR = 1 , } impl From < INT_EVENT2_ICLR_TXINT_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT2_ICLR_TXINT_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT2_ICLR_TXINT` writer - Clear UART Transmit Interrupt."] pub type INT_EVENT2_ICLR_TXINT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT2_ICLR_TXINT_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT2_ICLR_TXINT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event2_iclr_txint_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT2_ICLR_TXINT_AW :: INT_EVENT2_ICLR_TXINT_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event2_iclr_txint_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT2_ICLR_TXINT_AW :: INT_EVENT2_ICLR_TXINT_CLR) } } impl W { # [doc = "Bit 11 - Clear UART Transmit Interrupt."] # [inline (always)] # [must_use] pub fn int_event2_iclr_txint (& mut self) -> INT_EVENT2_ICLR_TXINT_W <'_,  INT_EVENT2_ICLR_SPEC , 11 > { INT_EVENT2_ICLR_TXINT_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Interrupt clear\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_event2_iclr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct INT_EVENT2_ICLR_SPEC ; impl crate :: RegisterSpec for INT_EVENT2_ICLR_SPEC { type Ux = u32 ; } # [doc = "`write(|w| ..)` method takes [`int_event2_iclr::W`](W) writer structure"] impl crate :: Writable for INT_EVENT2_ICLR_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets INT_EVENT2_ICLR to value 0"] impl crate :: Resettable for INT_EVENT2_ICLR_SPEC { const RESET_VALUE : Self :: Ux = 0 ; }
[INFO] [stdout]   |                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                           +++
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing
[INFO] [stdout]  --> src/uart0/int_event0_imask.rs:1:42165
[INFO] [stdout]   |
[INFO] [stdout] 1 | ..._imask_linc0 (& mut self) -> INT_EVENT0_IMASK_LINC0_W < INT_EVENT0_IMASK_SPEC , 7 > { INT_EVENT0_IMASK_LINC0_W :: new (self) } # [...
[INFO] [stdout]   |                  ^^^^^^^^^^     ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here
[INFO] [stdout]   |                  |
[INFO] [stdout]   |                  the lifetime is elided here
[INFO] [stdout]   |
[INFO] [stdout]   = help: the same lifetime is referred to in inconsistent ways, making the signature confusing
[INFO] [stdout] help: use `'_` for type paths
[INFO] [stdout]   |
[INFO] [stdout] 1 | # [doc = "Register `INT_EVENT0_IMASK` reader"] pub type R = crate :: R < INT_EVENT0_IMASK_SPEC > ; # [doc = "Register `INT_EVENT0_IMASK` writer"] pub type W = crate :: W < INT_EVENT0_IMASK_SPEC > ; # [doc = "Field `INT_EVENT0_IMASK_RTOUT` reader - Enable UARTOUT Receive Time-Out Interrupt."] pub type INT_EVENT0_IMASK_RTOUT_R = crate :: BitReader < INT_EVENT0_IMASK_RTOUT_A > ; # [doc = "Enable UARTOUT Receive Time-Out Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_RTOUT_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_RTOUT_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_RTOUT_SET = 1 , } impl From < INT_EVENT0_IMASK_RTOUT_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_RTOUT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_RTOUT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_RTOUT_A { match self . bits { false => INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_CLR , true => INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_rtout_clr (& self) -> bool { * self == INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_rtout_set (& self) -> bool { * self == INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_SET } } # [doc = "Field `INT_EVENT0_IMASK_RTOUT` writer - Enable UARTOUT Receive Time-Out Interrupt."] pub type INT_EVENT0_IMASK_RTOUT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_RTOUT_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_RTOUT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_rtout_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_rtout_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_SET) } } # [doc = "Field `INT_EVENT0_IMASK_FRMERR` reader - Enable UART Framing Error Interrupt."] pub type INT_EVENT0_IMASK_FRMERR_R = crate :: BitReader < INT_EVENT0_IMASK_FRMERR_A > ; # [doc = "Enable UART Framing Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_FRMERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_FRMERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_FRMERR_SET = 1 , } impl From < INT_EVENT0_IMASK_FRMERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_FRMERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_FRMERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_FRMERR_A { match self . bits { false => INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_CLR , true => INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_frmerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_frmerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_FRMERR` writer - Enable UART Framing Error Interrupt."] pub type INT_EVENT0_IMASK_FRMERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_FRMERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_FRMERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_frmerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_frmerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_SET) } } # [doc = "Field `INT_EVENT0_IMASK_PARERR` reader - Enable UART Parity Error Interrupt."] pub type INT_EVENT0_IMASK_PARERR_R = crate :: BitReader < INT_EVENT0_IMASK_PARERR_A > ; # [doc = "Enable UART Parity Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_PARERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_PARERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_PARERR_SET = 1 , } impl From < INT_EVENT0_IMASK_PARERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_PARERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_PARERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_PARERR_A { match self . bits { false => INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_CLR , true => INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_parerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_parerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_PARERR` writer - Enable UART Parity Error Interrupt."] pub type INT_EVENT0_IMASK_PARERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_PARERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_PARERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_parerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_parerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_SET) } } # [doc = "Field `INT_EVENT0_IMASK_BRKERR` reader - Enable UART Break Error Interrupt."] pub type INT_EVENT0_IMASK_BRKERR_R = crate :: BitReader < INT_EVENT0_IMASK_BRKERR_A > ; # [doc = "Enable UART Break Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_BRKERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_BRKERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_BRKERR_SET = 1 , } impl From < INT_EVENT0_IMASK_BRKERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_BRKERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_BRKERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_BRKERR_A { match self . bits { false => INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_CLR , true => INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_brkerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_brkerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_BRKERR` writer - Enable UART Break Error Interrupt."] pub type INT_EVENT0_IMASK_BRKERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_BRKERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_BRKERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_brkerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_brkerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_SET) } } # [doc = "Field `INT_EVENT0_IMASK_OVRERR` reader - Enable UART Receive Overrun Error Interrupt."] pub type INT_EVENT0_IMASK_OVRERR_R = crate :: BitReader < INT_EVENT0_IMASK_OVRERR_A > ; # [doc = "Enable UART Receive Overrun Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_OVRERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_OVRERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_OVRERR_SET = 1 , } impl From < INT_EVENT0_IMASK_OVRERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_OVRERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_OVRERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_OVRERR_A { match self . bits { false => INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_CLR , true => INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_ovrerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_ovrerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_OVRERR` writer - Enable UART Receive Overrun Error Interrupt."] pub type INT_EVENT0_IMASK_OVRERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_OVRERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_OVRERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_ovrerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_ovrerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_SET) } } # [doc = "Field `INT_EVENT0_IMASK_RXNE` reader - Enable Negative Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_IMASK_RXNE_R = crate :: BitReader < INT_EVENT0_IMASK_RXNE_A > ; # [doc = "Enable Negative Edge on UARTxRXD Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_RXNE_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_RXNE_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_RXNE_SET = 1 , } impl From < INT_EVENT0_IMASK_RXNE_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_RXNE_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_RXNE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_RXNE_A { match self . bits { false => INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_CLR , true => INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_rxne_clr (& self) -> bool { * self == INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_rxne_set (& self) -> bool { * self == INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_SET } } # [doc = "Field `INT_EVENT0_IMASK_RXNE` writer - Enable Negative Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_IMASK_RXNE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_RXNE_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_RXNE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_rxne_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_rxne_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_SET) } } # [doc = "Field `INT_EVENT0_IMASK_RXPE` reader - Enable Positive Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_IMASK_RXPE_R = crate :: BitReader < INT_EVENT0_IMASK_RXPE_A > ; # [doc = "Enable Positive Edge on UARTxRXD Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_RXPE_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_RXPE_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_RXPE_SET = 1 , } impl From < INT_EVENT0_IMASK_RXPE_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_RXPE_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_RXPE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_RXPE_A { match self . bits { false => INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_CLR , true => INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_rxpe_clr (& self) -> bool { * self == INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_rxpe_set (& self) -> bool { * self == INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_SET } } # [doc = "Field `INT_EVENT0_IMASK_RXPE` writer - Enable Positive Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_IMASK_RXPE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_RXPE_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_RXPE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_rxpe_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_rxpe_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_SET) } } # [doc = "Field `INT_EVENT0_IMASK_LINC0` reader - Enable LIN Capture 0 / Match Interrupt ."] pub type INT_EVENT0_IMASK_LINC0_R = crate :: BitReader < INT_EVENT0_IMASK_LINC0_A > ; # [doc = "Enable LIN Capture 0 / Match Interrupt .\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_LINC0_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_LINC0_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_LINC0_SET = 1 , } impl From < INT_EVENT0_IMASK_LINC0_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_LINC0_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_LINC0_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_LINC0_A { match self . bits { false => INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_CLR , true => INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_linc0_clr (& self) -> bool { * self == INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_linc0_set (& self) -> bool { * self == INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_SET } } # [doc = "Field `INT_EVENT0_IMASK_LINC0` writer - Enable LIN Capture 0 / Match Interrupt ."] pub type INT_EVENT0_IMASK_LINC0_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_LINC0_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_LINC0_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_linc0_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_linc0_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_SET) } } # [doc = "Field `INT_EVENT0_IMASK_LINC1` reader - Enable LIN Capture 1 Interrupt."] pub type INT_EVENT0_IMASK_LINC1_R = crate :: BitReader < INT_EVENT0_IMASK_LINC1_A > ; # [doc = "Enable LIN Capture 1 Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_LINC1_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_LINC1_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_LINC1_SET = 1 , } impl From < INT_EVENT0_IMASK_LINC1_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_LINC1_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_LINC1_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_LINC1_A { match self . bits { false => INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_CLR , true => INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_linc1_clr (& self) -> bool { * self == INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_linc1_set (& self) -> bool { * self == INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_SET } } # [doc = "Field `INT_EVENT0_IMASK_LINC1` writer - Enable LIN Capture 1 Interrupt."] pub type INT_EVENT0_IMASK_LINC1_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_LINC1_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_LINC1_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_linc1_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_linc1_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_SET) } } # [doc = "Field `INT_EVENT0_IMASK_LINOVF` reader - Enable LIN Hardware Counter Overflow Interrupt."] pub type INT_EVENT0_IMASK_LINOVF_R = crate :: BitReader < INT_EVENT0_IMASK_LINOVF_A > ; # [doc = "Enable LIN Hardware Counter Overflow Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_LINOVF_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_LINOVF_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_LINOVF_SET = 1 , } impl From < INT_EVENT0_IMASK_LINOVF_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_LINOVF_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_LINOVF_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_LINOVF_A { match self . bits { false => INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_CLR , true => INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_linovf_clr (& self) -> bool { * self == INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_linovf_set (& self) -> bool { * self == INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_SET } } # [doc = "Field `INT_EVENT0_IMASK_LINOVF` writer - Enable LIN Hardware Counter Overflow Interrupt."] pub type INT_EVENT0_IMASK_LINOVF_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_LINOVF_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_LINOVF_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_linovf_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_linovf_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_SET) } } # [doc = "Field `INT_EVENT0_IMASK_RXINT` reader - Enable UART Receive Interrupt."] pub type INT_EVENT0_IMASK_RXINT_R = crate :: BitReader < INT_EVENT0_IMASK_RXINT_A > ; # [doc = "Enable UART Receive Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_RXINT_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_RXINT_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_RXINT_SET = 1 , } impl From < INT_EVENT0_IMASK_RXINT_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_RXINT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_RXINT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_RXINT_A { match self . bits { false => INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_CLR , true => INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_rxint_clr (& self) -> bool { * self == INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_rxint_set (& self) -> bool { * self == INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_SET } } # [doc = "Field `INT_EVENT0_IMASK_RXINT` writer - Enable UART Receive Interrupt."] pub type INT_EVENT0_IMASK_RXINT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_RXINT_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_RXINT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_rxint_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_rxint_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_SET) } } # [doc = "Field `INT_EVENT0_IMASK_TXINT` reader - Enable UART Transmit Interrupt."] pub type INT_EVENT0_IMASK_TXINT_R = crate :: BitReader < INT_EVENT0_IMASK_TXINT_A > ; # [doc = "Enable UART Transmit Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_TXINT_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_TXINT_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_TXINT_SET = 1 , } impl From < INT_EVENT0_IMASK_TXINT_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_TXINT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_TXINT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_TXINT_A { match self . bits { false => INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_CLR , true => INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_txint_clr (& self) -> bool { * self == INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_txint_set (& self) -> bool { * self == INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_SET } } # [doc = "Field `INT_EVENT0_IMASK_TXINT` writer - Enable UART Transmit Interrupt."] pub type INT_EVENT0_IMASK_TXINT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_TXINT_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_TXINT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_txint_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_txint_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_SET) } } # [doc = "Field `INT_EVENT0_IMASK_EOT` reader - Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] pub type INT_EVENT0_IMASK_EOT_R = crate :: BitReader < INT_EVENT0_IMASK_EOT_A > ; # [doc = "Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_EOT_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_EOT_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_EOT_SET = 1 , } impl From < INT_EVENT0_IMASK_EOT_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_EOT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_EOT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_EOT_A { match self . bits { false => INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_CLR , true => INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_eot_clr (& self) -> bool { * self == INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_eot_set (& self) -> bool { * self == INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_SET } } # [doc = "Field `INT_EVENT0_IMASK_EOT` writer - Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] pub type INT_EVENT0_IMASK_EOT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_EOT_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_EOT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_eot_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_eot_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_SET) } } # [doc = "Field `INT_EVENT0_IMASK_ADDR_MATCH` reader - Enable Address Match Interrupt."] pub type INT_EVENT0_IMASK_ADDR_MATCH_R = crate :: BitReader < INT_EVENT0_IMASK_ADDR_MATCH_A > ; # [doc = "Enable Address Match Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_ADDR_MATCH_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_ADDR_MATCH_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_ADDR_MATCH_SET = 1 , } impl From < INT_EVENT0_IMASK_ADDR_MATCH_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_ADDR_MATCH_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_ADDR_MATCH_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_ADDR_MATCH_A { match self . bits { false => INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_CLR , true => INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_addr_match_clr (& self) -> bool { * self == INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_addr_match_set (& self) -> bool { * self == INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_SET } } # [doc = "Field `INT_EVENT0_IMASK_ADDR_MATCH` writer - Enable Address Match Interrupt."] pub type INT_EVENT0_IMASK_ADDR_MATCH_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_ADDR_MATCH_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_ADDR_MATCH_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_addr_match_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_addr_match_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_SET) } } # [doc = "Field `INT_EVENT0_IMASK_CTS` reader - Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] pub type INT_EVENT0_IMASK_CTS_R = crate :: BitReader < INT_EVENT0_IMASK_CTS_A > ; # [doc = "Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_CTS_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_CTS_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_CTS_SET = 1 , } impl From < INT_EVENT0_IMASK_CTS_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_CTS_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_CTS_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_CTS_A { match self . bits { false => INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_CLR , true => INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_cts_clr (& self) -> bool { * self == INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_cts_set (& self) -> bool { * self == INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_SET } } # [doc = "Field `INT_EVENT0_IMASK_CTS` writer - Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] pub type INT_EVENT0_IMASK_CTS_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_CTS_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_CTS_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_cts_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_cts_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DMA_DONE_RX` reader - Enable DMA Done on RX Event Channel"] pub type INT_EVENT0_IMASK_DMA_DONE_RX_R = crate :: BitReader < INT_EVENT0_IMASK_DMA_DONE_RX_A > ; # [doc = "Enable DMA Done on RX Event Channel\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DMA_DONE_RX_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DMA_DONE_RX_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DMA_DONE_RX_SET = 1 , } impl From < INT_EVENT0_IMASK_DMA_DONE_RX_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DMA_DONE_RX_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DMA_DONE_RX_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DMA_DONE_RX_A { match self . bits { false => INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_CLR , true => INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dma_done_rx_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dma_done_rx_set (& self) -> bool { * self == INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_SET } } # [doc = "Field `INT_EVENT0_IMASK_DMA_DONE_RX` writer - Enable DMA Done on RX Event Channel"] pub type INT_EVENT0_IMASK_DMA_DONE_RX_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DMA_DONE_RX_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DMA_DONE_RX_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dma_done_rx_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dma_done_rx_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DMA_DONE_TX` reader - Enable DMA Done on TX Event Channel"] pub type INT_EVENT0_IMASK_DMA_DONE_TX_R = crate :: BitReader < INT_EVENT0_IMASK_DMA_DONE_TX_A > ; # [doc = "Enable DMA Done on TX Event Channel\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DMA_DONE_TX_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DMA_DONE_TX_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DMA_DONE_TX_SET = 1 , } impl From < INT_EVENT0_IMASK_DMA_DONE_TX_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DMA_DONE_TX_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DMA_DONE_TX_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DMA_DONE_TX_A { match self . bits { false => INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_CLR , true => INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dma_done_tx_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dma_done_tx_set (& self) -> bool { * self == INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_SET } } # [doc = "Field `INT_EVENT0_IMASK_DMA_DONE_TX` writer - Enable DMA Done on TX Event Channel"] pub type INT_EVENT0_IMASK_DMA_DONE_TX_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DMA_DONE_TX_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DMA_DONE_TX_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dma_done_tx_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dma_done_tx_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_SET) } } # [doc = "Field `INT_EVENT0_IMASK_NERR` reader - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] pub type INT_EVENT0_IMASK_NERR_R = crate :: BitReader < INT_EVENT0_IMASK_NERR_A > ; # [doc = "Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_NERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_NERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_NERR_SET = 1 , } impl From < INT_EVENT0_IMASK_NERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_NERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_NERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_NERR_A { match self . bits { false => INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_CLR , true => INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_nerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_nerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_NERR` writer - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] pub type INT_EVENT0_IMASK_NERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_NERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_NERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_nerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_nerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_SET) } } impl R { # [doc = "Bit 0 - Enable UARTOUT Receive Time-Out Interrupt."] # [inline (always)] pub fn int_event0_imask_rtout (& self) -> INT_EVENT0_IMASK_RTOUT_R { INT_EVENT0_IMASK_RTOUT_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - Enable UART Framing Error Interrupt."] # [inline (always)] pub fn int_event0_imask_frmerr (& self) -> INT_EVENT0_IMASK_FRMERR_R { INT_EVENT0_IMASK_FRMERR_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - Enable UART Parity Error Interrupt."] # [inline (always)] pub fn int_event0_imask_parerr (& self) -> INT_EVENT0_IMASK_PARERR_R { INT_EVENT0_IMASK_PARERR_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - Enable UART Break Error Interrupt."] # [inline (always)] pub fn int_event0_imask_brkerr (& self) -> INT_EVENT0_IMASK_BRKERR_R { INT_EVENT0_IMASK_BRKERR_R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - Enable UART Receive Overrun Error Interrupt."] # [inline (always)] pub fn int_event0_imask_ovrerr (& self) -> INT_EVENT0_IMASK_OVRERR_R { INT_EVENT0_IMASK_OVRERR_R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - Enable Negative Edge on UARTxRXD Interrupt."] # [inline (always)] pub fn int_event0_imask_rxne (& self) -> INT_EVENT0_IMASK_RXNE_R { INT_EVENT0_IMASK_RXNE_R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - Enable Positive Edge on UARTxRXD Interrupt."] # [inline (always)] pub fn int_event0_imask_rxpe (& self) -> INT_EVENT0_IMASK_RXPE_R { INT_EVENT0_IMASK_RXPE_R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - Enable LIN Capture 0 / Match Interrupt ."] # [inline (always)] pub fn int_event0_imask_linc0 (& self) -> INT_EVENT0_IMASK_LINC0_R { INT_EVENT0_IMASK_LINC0_R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - Enable LIN Capture 1 Interrupt."] # [inline (always)] pub fn int_event0_imask_linc1 (& self) -> INT_EVENT0_IMASK_LINC1_R { INT_EVENT0_IMASK_LINC1_R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - Enable LIN Hardware Counter Overflow Interrupt."] # [inline (always)] pub fn int_event0_imask_linovf (& self) -> INT_EVENT0_IMASK_LINOVF_R { INT_EVENT0_IMASK_LINOVF_R :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - Enable UART Receive Interrupt."] # [inline (always)] pub fn int_event0_imask_rxint (& self) -> INT_EVENT0_IMASK_RXINT_R { INT_EVENT0_IMASK_RXINT_R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - Enable UART Transmit Interrupt."] # [inline (always)] pub fn int_event0_imask_txint (& self) -> INT_EVENT0_IMASK_TXINT_R { INT_EVENT0_IMASK_TXINT_R :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] # [inline (always)] pub fn int_event0_imask_eot (& self) -> INT_EVENT0_IMASK_EOT_R { INT_EVENT0_IMASK_EOT_R :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - Enable Address Match Interrupt."] # [inline (always)] pub fn int_event0_imask_addr_match (& self) -> INT_EVENT0_IMASK_ADDR_MATCH_R { INT_EVENT0_IMASK_ADDR_MATCH_R :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 14 - Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] # [inline (always)] pub fn int_event0_imask_cts (& self) -> INT_EVENT0_IMASK_CTS_R { INT_EVENT0_IMASK_CTS_R :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - Enable DMA Done on RX Event Channel"] # [inline (always)] pub fn int_event0_imask_dma_done_rx (& self) -> INT_EVENT0_IMASK_DMA_DONE_RX_R { INT_EVENT0_IMASK_DMA_DONE_RX_R :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bit 16 - Enable DMA Done on TX Event Channel"] # [inline (always)] pub fn int_event0_imask_dma_done_tx (& self) -> INT_EVENT0_IMASK_DMA_DONE_TX_R { INT_EVENT0_IMASK_DMA_DONE_TX_R :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] # [inline (always)] pub fn int_event0_imask_nerr (& self) -> INT_EVENT0_IMASK_NERR_R { INT_EVENT0_IMASK_NERR_R :: new (((self . bits >> 17) & 1) != 0) } } impl W { # [doc = "Bit 0 - Enable UARTOUT Receive Time-Out Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_rtout (& mut self) -> INT_EVENT0_IMASK_RTOUT_W < INT_EVENT0_IMASK_SPEC , 0 > { INT_EVENT0_IMASK_RTOUT_W :: new (self) } # [doc = "Bit 1 - Enable UART Framing Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_frmerr (& mut self) -> INT_EVENT0_IMASK_FRMERR_W < INT_EVENT0_IMASK_SPEC , 1 > { INT_EVENT0_IMASK_FRMERR_W :: new (self) } # [doc = "Bit 2 - Enable UART Parity Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_parerr (& mut self) -> INT_EVENT0_IMASK_PARERR_W < INT_EVENT0_IMASK_SPEC , 2 > { INT_EVENT0_IMASK_PARERR_W :: new (self) } # [doc = "Bit 3 - Enable UART Break Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_brkerr (& mut self) -> INT_EVENT0_IMASK_BRKERR_W < INT_EVENT0_IMASK_SPEC , 3 > { INT_EVENT0_IMASK_BRKERR_W :: new (self) } # [doc = "Bit 4 - Enable UART Receive Overrun Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_ovrerr (& mut self) -> INT_EVENT0_IMASK_OVRERR_W < INT_EVENT0_IMASK_SPEC , 4 > { INT_EVENT0_IMASK_OVRERR_W :: new (self) } # [doc = "Bit 5 - Enable Negative Edge on UARTxRXD Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_rxne (& mut self) -> INT_EVENT0_IMASK_RXNE_W < INT_EVENT0_IMASK_SPEC , 5 > { INT_EVENT0_IMASK_RXNE_W :: new (self) } # [doc = "Bit 6 - Enable Positive Edge on UARTxRXD Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_rxpe (& mut self) -> INT_EVENT0_IMASK_RXPE_W < INT_EVENT0_IMASK_SPEC , 6 > { INT_EVENT0_IMASK_RXPE_W :: new (self) } # [doc = "Bit 7 - Enable LIN Capture 0 / Match Interrupt ."] # [inline (always)] # [must_use] pub fn int_event0_imask_linc0 (& mut self) -> INT_EVENT0_IMASK_LINC0_W <'_,  INT_EVENT0_IMASK_SPEC , 7 > { INT_EVENT0_IMASK_LINC0_W :: new (self) } # [doc = "Bit 8 - Enable LIN Capture 1 Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_linc1 (& mut self) -> INT_EVENT0_IMASK_LINC1_W < INT_EVENT0_IMASK_SPEC , 8 > { INT_EVENT0_IMASK_LINC1_W :: new (self) } # [doc = "Bit 9 - Enable LIN Hardware Counter Overflow Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_linovf (& mut self) -> INT_EVENT0_IMASK_LINOVF_W < INT_EVENT0_IMASK_SPEC , 9 > { INT_EVENT0_IMASK_LINOVF_W :: new (self) } # [doc = "Bit 10 - Enable UART Receive Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_rxint (& mut self) -> INT_EVENT0_IMASK_RXINT_W < INT_EVENT0_IMASK_SPEC , 10 > { INT_EVENT0_IMASK_RXINT_W :: new (self) } # [doc = "Bit 11 - Enable UART Transmit Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_txint (& mut self) -> INT_EVENT0_IMASK_TXINT_W < INT_EVENT0_IMASK_SPEC , 11 > { INT_EVENT0_IMASK_TXINT_W :: new (self) } # [doc = "Bit 12 - Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] # [inline (always)] # [must_use] pub fn int_event0_imask_eot (& mut self) -> INT_EVENT0_IMASK_EOT_W < INT_EVENT0_IMASK_SPEC , 12 > { INT_EVENT0_IMASK_EOT_W :: new (self) } # [doc = "Bit 13 - Enable Address Match Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_addr_match (& mut self) -> INT_EVENT0_IMASK_ADDR_MATCH_W < INT_EVENT0_IMASK_SPEC , 13 > { INT_EVENT0_IMASK_ADDR_MATCH_W :: new (self) } # [doc = "Bit 14 - Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] # [inline (always)] # [must_use] pub fn int_event0_imask_cts (& mut self) -> INT_EVENT0_IMASK_CTS_W < INT_EVENT0_IMASK_SPEC , 14 > { INT_EVENT0_IMASK_CTS_W :: new (self) } # [doc = "Bit 15 - Enable DMA Done on RX Event Channel"] # [inline (always)] # [must_use] pub fn int_event0_imask_dma_done_rx (& mut self) -> INT_EVENT0_IMASK_DMA_DONE_RX_W < INT_EVENT0_IMASK_SPEC , 15 > { INT_EVENT0_IMASK_DMA_DONE_RX_W :: new (self) } # [doc = "Bit 16 - Enable DMA Done on TX Event Channel"] # [inline (always)] # [must_use] pub fn int_event0_imask_dma_done_tx (& mut self) -> INT_EVENT0_IMASK_DMA_DONE_TX_W < INT_EVENT0_IMASK_SPEC , 16 > { INT_EVENT0_IMASK_DMA_DONE_TX_W :: new (self) } # [doc = "Bit 17 - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] # [inline (always)] # [must_use] pub fn int_event0_imask_nerr (& mut self) -> INT_EVENT0_IMASK_NERR_W < INT_EVENT0_IMASK_SPEC , 17 > { INT_EVENT0_IMASK_NERR_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Interrupt mask\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_event0_imask::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_event0_imask::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct INT_EVENT0_IMASK_SPEC ; impl crate :: RegisterSpec for INT_EVENT0_IMASK_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`int_event0_imask::R`](R) reader structure"] impl crate :: Readable for INT_EVENT0_IMASK_SPEC { } # [doc = "`write(|w| ..)` method takes [`int_event0_imask::W`](W) writer structure"] impl crate :: Writable for INT_EVENT0_IMASK_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets INT_EVENT0_IMASK to value 0"] impl crate :: Resettable for INT_EVENT0_IMASK_SPEC { const RESET_VALUE : Self :: Ux = 0 ; }
[INFO] [stdout]   |                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                              +++
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing
[INFO] [stdout]  --> src/uart0/ctl0.rs:1:38665
[INFO] [stdout]   |
[INFO] [stdout] 1 | ...use] pub fn ctl0_enable (& mut self) -> CTL0_ENABLE_W < CTL0_SPEC , 0 > { CTL0_ENABLE_W :: new (self) } # [doc = "Bit 2 - UART Loo...
[INFO] [stdout]   |                             ^^^^^^^^^^     ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here
[INFO] [stdout]   |                             |
[INFO] [stdout]   |                             the lifetime is elided here
[INFO] [stdout]   |
[INFO] [stdout]   = help: the same lifetime is referred to in inconsistent ways, making the signature confusing
[INFO] [stdout] help: use `'_` for type paths
[INFO] [stdout]   |
[INFO] [stdout] 1 | # [doc = "Register `CTL0` reader"] pub type R = crate :: R < CTL0_SPEC > ; # [doc = "Register `CTL0` writer"] pub type W = crate :: W < CTL0_SPEC > ; # [doc = "Field `CTL0_ENABLE` reader - UART Module Enable. If the UART is disabled in the middle of transmission or reception, it completes the current character before stopping. If the ENABLE bit is not set, all registers can still be accessed and updated. It is recommended to setup and change the UART operation mode with having the ENABLE bit cleared to avoid unpredictable behavior during the setup or update. If disabled the UART module will not send or receive any data and the logic is held in reset state."] pub type CTL0_ENABLE_R = crate :: BitReader < CTL0_ENABLE_A > ; # [doc = "UART Module Enable. If the UART is disabled in the middle of transmission or reception, it completes the current character before stopping. If the ENABLE bit is not set, all registers can still be accessed and updated. It is recommended to setup and change the UART operation mode with having the ENABLE bit cleared to avoid unpredictable behavior during the setup or update. If disabled the UART module will not send or receive any data and the logic is held in reset state.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CTL0_ENABLE_A { # [doc = "0: DISABLE"] CTL0_ENABLE_DISABLE = 0 , # [doc = "1: ENABLE"] CTL0_ENABLE_ENABLE = 1 , } impl From < CTL0_ENABLE_A > for bool { # [inline (always)] fn from (variant : CTL0_ENABLE_A) -> Self { variant as u8 != 0 } } impl CTL0_ENABLE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CTL0_ENABLE_A { match self . bits { false => CTL0_ENABLE_A :: CTL0_ENABLE_DISABLE , true => CTL0_ENABLE_A :: CTL0_ENABLE_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_ctl0_enable_disable (& self) -> bool { * self == CTL0_ENABLE_A :: CTL0_ENABLE_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_ctl0_enable_enable (& self) -> bool { * self == CTL0_ENABLE_A :: CTL0_ENABLE_ENABLE } } # [doc = "Field `CTL0_ENABLE` writer - UART Module Enable. If the UART is disabled in the middle of transmission or reception, it completes the current character before stopping. If the ENABLE bit is not set, all registers can still be accessed and updated. It is recommended to setup and change the UART operation mode with having the ENABLE bit cleared to avoid unpredictable behavior during the setup or update. If disabled the UART module will not send or receive any data and the logic is held in reset state."] pub type CTL0_ENABLE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL0_ENABLE_A > ; impl < 'a , REG , const O : u8 > CTL0_ENABLE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn ctl0_enable_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_ENABLE_A :: CTL0_ENABLE_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn ctl0_enable_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_ENABLE_A :: CTL0_ENABLE_ENABLE) } } # [doc = "Field `CTL0_LBE` reader - UART Loop Back Enable"] pub type CTL0_LBE_R = crate :: BitReader < CTL0_LBE_A > ; # [doc = "UART Loop Back Enable\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CTL0_LBE_A { # [doc = "0: DISABLE"] CTL0_LBE_DISABLE = 0 , # [doc = "1: ENABLE"] CTL0_LBE_ENABLE = 1 , } impl From < CTL0_LBE_A > for bool { # [inline (always)] fn from (variant : CTL0_LBE_A) -> Self { variant as u8 != 0 } } impl CTL0_LBE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CTL0_LBE_A { match self . bits { false => CTL0_LBE_A :: CTL0_LBE_DISABLE , true => CTL0_LBE_A :: CTL0_LBE_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_ctl0_lbe_disable (& self) -> bool { * self == CTL0_LBE_A :: CTL0_LBE_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_ctl0_lbe_enable (& self) -> bool { * self == CTL0_LBE_A :: CTL0_LBE_ENABLE } } # [doc = "Field `CTL0_LBE` writer - UART Loop Back Enable"] pub type CTL0_LBE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL0_LBE_A > ; impl < 'a , REG , const O : u8 > CTL0_LBE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn ctl0_lbe_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_LBE_A :: CTL0_LBE_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn ctl0_lbe_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_LBE_A :: CTL0_LBE_ENABLE) } } # [doc = "Field `CTL0_RXE` reader - UART Receive Enable If the UART is disabled in the middle of a receive, it completes the current character before stopping. #b#NOTE:#/b# To enable reception, the UARTEN bit must be set."] pub type CTL0_RXE_R = crate :: BitReader < CTL0_RXE_A > ; # [doc = "UART Receive Enable If the UART is disabled in the middle of a receive, it completes the current character before stopping. #b#NOTE:#/b# To enable reception, the UARTEN bit must be set.\n\nValue on reset: 1"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CTL0_RXE_A { # [doc = "0: DISABLE"] CTL0_RXE_DISABLE = 0 , # [doc = "1: ENABLE"] CTL0_RXE_ENABLE = 1 , } impl From < CTL0_RXE_A > for bool { # [inline (always)] fn from (variant : CTL0_RXE_A) -> Self { variant as u8 != 0 } } impl CTL0_RXE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CTL0_RXE_A { match self . bits { false => CTL0_RXE_A :: CTL0_RXE_DISABLE , true => CTL0_RXE_A :: CTL0_RXE_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_ctl0_rxe_disable (& self) -> bool { * self == CTL0_RXE_A :: CTL0_RXE_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_ctl0_rxe_enable (& self) -> bool { * self == CTL0_RXE_A :: CTL0_RXE_ENABLE } } # [doc = "Field `CTL0_RXE` writer - UART Receive Enable If the UART is disabled in the middle of a receive, it completes the current character before stopping. #b#NOTE:#/b# To enable reception, the UARTEN bit must be set."] pub type CTL0_RXE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL0_RXE_A > ; impl < 'a , REG , const O : u8 > CTL0_RXE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn ctl0_rxe_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_RXE_A :: CTL0_RXE_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn ctl0_rxe_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_RXE_A :: CTL0_RXE_ENABLE) } } # [doc = "Field `CTL0_TXE` reader - UART Transmit Enable If the UART is disabled in the middle of a transmission, it completes the current character before stopping. #b#NOTE:#/b# To enable transmission, the UARTEN bit must be set."] pub type CTL0_TXE_R = crate :: BitReader < CTL0_TXE_A > ; # [doc = "UART Transmit Enable If the UART is disabled in the middle of a transmission, it completes the current character before stopping. #b#NOTE:#/b# To enable transmission, the UARTEN bit must be set.\n\nValue on reset: 1"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CTL0_TXE_A { # [doc = "0: DISABLE"] CTL0_TXE_DISABLE = 0 , # [doc = "1: ENABLE"] CTL0_TXE_ENABLE = 1 , } impl From < CTL0_TXE_A > for bool { # [inline (always)] fn from (variant : CTL0_TXE_A) -> Self { variant as u8 != 0 } } impl CTL0_TXE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CTL0_TXE_A { match self . bits { false => CTL0_TXE_A :: CTL0_TXE_DISABLE , true => CTL0_TXE_A :: CTL0_TXE_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_ctl0_txe_disable (& self) -> bool { * self == CTL0_TXE_A :: CTL0_TXE_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_ctl0_txe_enable (& self) -> bool { * self == CTL0_TXE_A :: CTL0_TXE_ENABLE } } # [doc = "Field `CTL0_TXE` writer - UART Transmit Enable If the UART is disabled in the middle of a transmission, it completes the current character before stopping. #b#NOTE:#/b# To enable transmission, the UARTEN bit must be set."] pub type CTL0_TXE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL0_TXE_A > ; impl < 'a , REG , const O : u8 > CTL0_TXE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn ctl0_txe_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_TXE_A :: CTL0_TXE_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn ctl0_txe_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_TXE_A :: CTL0_TXE_ENABLE) } } # [doc = "Field `CTL0_TXD_OUT_EN` reader - TXD Pin Control Enable. When the transmit section of the UART is disabled (TXE = 0), the TXD pin can be controlled by the TXD_OUT bit. 1 = UARTxTXD pin can be controlled by TXD_OUT, if TXE = 0"] pub type CTL0_TXD_OUT_EN_R = crate :: BitReader < CTL0_TXD_OUT_EN_A > ; # [doc = "TXD Pin Control Enable. When the transmit section of the UART is disabled (TXE = 0), the TXD pin can be controlled by the TXD_OUT bit. 1 = UARTxTXD pin can be controlled by TXD_OUT, if TXE = 0\n\nValue on reset: 1"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CTL0_TXD_OUT_EN_A { # [doc = "0: DISABLE"] CTL0_TXD_OUT_EN_DISABLE = 0 , # [doc = "1: ENABLE"] CTL0_TXD_OUT_EN_ENABLE = 1 , } impl From < CTL0_TXD_OUT_EN_A > for bool { # [inline (always)] fn from (variant : CTL0_TXD_OUT_EN_A) -> Self { variant as u8 != 0 } } impl CTL0_TXD_OUT_EN_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CTL0_TXD_OUT_EN_A { match self . bits { false => CTL0_TXD_OUT_EN_A :: CTL0_TXD_OUT_EN_DISABLE , true => CTL0_TXD_OUT_EN_A :: CTL0_TXD_OUT_EN_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_ctl0_txd_out_en_disable (& self) -> bool { * self == CTL0_TXD_OUT_EN_A :: CTL0_TXD_OUT_EN_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_ctl0_txd_out_en_enable (& self) -> bool { * self == CTL0_TXD_OUT_EN_A :: CTL0_TXD_OUT_EN_ENABLE } } # [doc = "Field `CTL0_TXD_OUT_EN` writer - TXD Pin Control Enable. When the transmit section of the UART is disabled (TXE = 0), the TXD pin can be controlled by the TXD_OUT bit. 1 = UARTxTXD pin can be controlled by TXD_OUT, if TXE = 0"] pub type CTL0_TXD_OUT_EN_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL0_TXD_OUT_EN_A > ; impl < 'a , REG , const O : u8 > CTL0_TXD_OUT_EN_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn ctl0_txd_out_en_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_TXD_OUT_EN_A :: CTL0_TXD_OUT_EN_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn ctl0_txd_out_en_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_TXD_OUT_EN_A :: CTL0_TXD_OUT_EN_ENABLE) } } # [doc = "Field `CTL0_TXD_OUT` reader - TXD Pin Control Controls the TXD pin when TXD_OUT_EN = 1 and TXE = 0."] pub type CTL0_TXD_OUT_R = crate :: BitReader < CTL0_TXD_OUT_A > ; # [doc = "TXD Pin Control Controls the TXD pin when TXD_OUT_EN = 1 and TXE = 0.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CTL0_TXD_OUT_A { # [doc = "0: LOW"] CTL0_TXD_OUT_LOW = 0 , # [doc = "1: HIGH"] CTL0_TXD_OUT_HIGH = 1 , } impl From < CTL0_TXD_OUT_A > for bool { # [inline (always)] fn from (variant : CTL0_TXD_OUT_A) -> Self { variant as u8 != 0 } } impl CTL0_TXD_OUT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CTL0_TXD_OUT_A { match self . bits { false => CTL0_TXD_OUT_A :: CTL0_TXD_OUT_LOW , true => CTL0_TXD_OUT_A :: CTL0_TXD_OUT_HIGH , } } # [doc = "LOW"] # [inline (always)] pub fn is_ctl0_txd_out_low (& self) -> bool { * self == CTL0_TXD_OUT_A :: CTL0_TXD_OUT_LOW } # [doc = "HIGH"] # [inline (always)] pub fn is_ctl0_txd_out_high (& self) -> bool { * self == CTL0_TXD_OUT_A :: CTL0_TXD_OUT_HIGH } } # [doc = "Field `CTL0_TXD_OUT` writer - TXD Pin Control Controls the TXD pin when TXD_OUT_EN = 1 and TXE = 0."] pub type CTL0_TXD_OUT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL0_TXD_OUT_A > ; impl < 'a , REG , const O : u8 > CTL0_TXD_OUT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "LOW"] # [inline (always)] pub fn ctl0_txd_out_low (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_TXD_OUT_A :: CTL0_TXD_OUT_LOW) } # [doc = "HIGH"] # [inline (always)] pub fn ctl0_txd_out_high (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_TXD_OUT_A :: CTL0_TXD_OUT_HIGH) } } # [doc = "Field `CTL0_MENC` reader - Manchester Encode enable"] pub type CTL0_MENC_R = crate :: BitReader < CTL0_MENC_A > ; # [doc = "Manchester Encode enable\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CTL0_MENC_A { # [doc = "0: DISABLE"] CTL0_MENC_DISABLE = 0 , # [doc = "1: ENABLE"] CTL0_MENC_ENABLE = 1 , } impl From < CTL0_MENC_A > for bool { # [inline (always)] fn from (variant : CTL0_MENC_A) -> Self { variant as u8 != 0 } } impl CTL0_MENC_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CTL0_MENC_A { match self . bits { false => CTL0_MENC_A :: CTL0_MENC_DISABLE , true => CTL0_MENC_A :: CTL0_MENC_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_ctl0_menc_disable (& self) -> bool { * self == CTL0_MENC_A :: CTL0_MENC_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_ctl0_menc_enable (& self) -> bool { * self == CTL0_MENC_A :: CTL0_MENC_ENABLE } } # [doc = "Field `CTL0_MENC` writer - Manchester Encode enable"] pub type CTL0_MENC_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL0_MENC_A > ; impl < 'a , REG , const O : u8 > CTL0_MENC_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn ctl0_menc_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_MENC_A :: CTL0_MENC_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn ctl0_menc_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_MENC_A :: CTL0_MENC_ENABLE) } } # [doc = "Field `CTL0_MODE` reader - Set the communication mode and protocol used. (Not defined settings uses the default setting: 0)"] pub type CTL0_MODE_R = crate :: FieldReader < CTL0_MODE_A > ; # [doc = "Set the communication mode and protocol used. (Not defined settings uses the default setting: 0)\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum CTL0_MODE_A { # [doc = "0: UART"] CTL0_MODE_UART = 0 , # [doc = "1: RS485"] CTL0_MODE_RS485 = 1 , # [doc = "2: IDLELINE"] CTL0_MODE_IDLELINE = 2 , # [doc = "3: ADDR9BIT"] CTL0_MODE_ADDR9BIT = 3 , # [doc = "4: SMART"] CTL0_MODE_SMART = 4 , # [doc = "5: DALI"] CTL0_MODE_DALI = 5 , } impl From < CTL0_MODE_A > for u8 { # [inline (always)] fn from (variant : CTL0_MODE_A) -> Self { variant as _ } } impl crate :: FieldSpec for CTL0_MODE_A { type Ux = u8 ; } impl CTL0_MODE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < CTL0_MODE_A > { match self . bits { 0 => Some (CTL0_MODE_A :: CTL0_MODE_UART) , 1 => Some (CTL0_MODE_A :: CTL0_MODE_RS485) , 2 => Some (CTL0_MODE_A :: CTL0_MODE_IDLELINE) , 3 => Some (CTL0_MODE_A :: CTL0_MODE_ADDR9BIT) , 4 => Some (CTL0_MODE_A :: CTL0_MODE_SMART) , 5 => Some (CTL0_MODE_A :: CTL0_MODE_DALI) , _ => None , } } # [doc = "UART"] # [inline (always)] pub fn is_ctl0_mode_uart (& self) -> bool { * self == CTL0_MODE_A :: CTL0_MODE_UART } # [doc = "RS485"] # [inline (always)] pub fn is_ctl0_mode_rs485 (& self) -> bool { * self == CTL0_MODE_A :: CTL0_MODE_RS485 } # [doc = "IDLELINE"] # [inline (always)] pub fn is_ctl0_mode_idleline (& self) -> bool { * self == CTL0_MODE_A :: CTL0_MODE_IDLELINE } # [doc = "ADDR9BIT"] # [inline (always)] pub fn is_ctl0_mode_addr9bit (& self) -> bool { * self == CTL0_MODE_A :: CTL0_MODE_ADDR9BIT } # [doc = "SMART"] # [inline (always)] pub fn is_ctl0_mode_smart (& self) -> bool { * self == CTL0_MODE_A :: CTL0_MODE_SMART } # [doc = "DALI"] # [inline (always)] pub fn is_ctl0_mode_dali (& self) -> bool { * self == CTL0_MODE_A :: CTL0_MODE_DALI } } # [doc = "Field `CTL0_MODE` writer - Set the communication mode and protocol used. (Not defined settings uses the default setting: 0)"] pub type CTL0_MODE_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 3 , O , CTL0_MODE_A > ; impl < 'a , REG , const O : u8 > CTL0_MODE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "UART"] # [inline (always)] pub fn ctl0_mode_uart (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_MODE_A :: CTL0_MODE_UART) } # [doc = "RS485"] # [inline (always)] pub fn ctl0_mode_rs485 (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_MODE_A :: CTL0_MODE_RS485) } # [doc = "IDLELINE"] # [inline (always)] pub fn ctl0_mode_idleline (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_MODE_A :: CTL0_MODE_IDLELINE) } # [doc = "ADDR9BIT"] # [inline (always)] pub fn ctl0_mode_addr9bit (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_MODE_A :: CTL0_MODE_ADDR9BIT) } # [doc = "SMART"] # [inline (always)] pub fn ctl0_mode_smart (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_MODE_A :: CTL0_MODE_SMART) } # [doc = "DALI"] # [inline (always)] pub fn ctl0_mode_dali (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_MODE_A :: CTL0_MODE_DALI) } } # [doc = "Field `CTL0_RTS` reader - Request to Send If RTSEN is set the RTS output signals is controlled by the hardware logic using the FIFO fill level or TXDATA buffer. If RTSEN is cleared the RTS output is controlled by the RTS bit. The bit is the complement of the UART request to send, RTS modem status output."] pub type CTL0_RTS_R = crate :: BitReader < CTL0_RTS_A > ; # [doc = "Request to Send If RTSEN is set the RTS output signals is controlled by the hardware logic using the FIFO fill level or TXDATA buffer. If RTSEN is cleared the RTS output is controlled by the RTS bit. The bit is the complement of the UART request to send, RTS modem status output.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CTL0_RTS_A { # [doc = "0: CLR"] CTL0_RTS_CLR = 0 , # [doc = "1: SET"] CTL0_RTS_SET = 1 , } impl From < CTL0_RTS_A > for bool { # [inline (always)] fn from (variant : CTL0_RTS_A) -> Self { variant as u8 != 0 } } impl CTL0_RTS_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CTL0_RTS_A { match self . bits { false => CTL0_RTS_A :: CTL0_RTS_CLR , true => CTL0_RTS_A :: CTL0_RTS_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_ctl0_rts_clr (& self) -> bool { * self == CTL0_RTS_A :: CTL0_RTS_CLR } # [doc = "SET"] # [inline (always)] pub fn is_ctl0_rts_set (& self) -> bool { * self == CTL0_RTS_A :: CTL0_RTS_SET } } # [doc = "Field `CTL0_RTS` writer - Request to Send If RTSEN is set the RTS output signals is controlled by the hardware logic using the FIFO fill level or TXDATA buffer. If RTSEN is cleared the RTS output is controlled by the RTS bit. The bit is the complement of the UART request to send, RTS modem status output."] pub type CTL0_RTS_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL0_RTS_A > ; impl < 'a , REG , const O : u8 > CTL0_RTS_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn ctl0_rts_clr (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_RTS_A :: CTL0_RTS_CLR) } # [doc = "SET"] # [inline (always)] pub fn ctl0_rts_set (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_RTS_A :: CTL0_RTS_SET) } } # [doc = "Field `CTL0_RTSEN` reader - Enable hardware controlled Request to Send"] pub type CTL0_RTSEN_R = crate :: BitReader < CTL0_RTSEN_A > ; # [doc = "Enable hardware controlled Request to Send\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CTL0_RTSEN_A { # [doc = "0: DISABLE"] CTL0_RTSEN_DISABLE = 0 , # [doc = "1: ENABLE"] CTL0_RTSEN_ENABLE = 1 , } impl From < CTL0_RTSEN_A > for bool { # [inline (always)] fn from (variant : CTL0_RTSEN_A) -> Self { variant as u8 != 0 } } impl CTL0_RTSEN_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CTL0_RTSEN_A { match self . bits { false => CTL0_RTSEN_A :: CTL0_RTSEN_DISABLE , true => CTL0_RTSEN_A :: CTL0_RTSEN_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_ctl0_rtsen_disable (& self) -> bool { * self == CTL0_RTSEN_A :: CTL0_RTSEN_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_ctl0_rtsen_enable (& self) -> bool { * self == CTL0_RTSEN_A :: CTL0_RTSEN_ENABLE } } # [doc = "Field `CTL0_RTSEN` writer - Enable hardware controlled Request to Send"] pub type CTL0_RTSEN_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL0_RTSEN_A > ; impl < 'a , REG , const O : u8 > CTL0_RTSEN_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn ctl0_rtsen_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_RTSEN_A :: CTL0_RTSEN_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn ctl0_rtsen_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_RTSEN_A :: CTL0_RTSEN_ENABLE) } } # [doc = "Field `CTL0_CTSEN` reader - Enable Clear To Send"] pub type CTL0_CTSEN_R = crate :: BitReader < CTL0_CTSEN_A > ; # [doc = "Enable Clear To Send\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CTL0_CTSEN_A { # [doc = "0: DISABLE"] CTL0_CTSEN_DISABLE = 0 , # [doc = "1: ENABLE"] CTL0_CTSEN_ENABLE = 1 , } impl From < CTL0_CTSEN_A > for bool { # [inline (always)] fn from (variant : CTL0_CTSEN_A) -> Self { variant as u8 != 0 } } impl CTL0_CTSEN_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CTL0_CTSEN_A { match self . bits { false => CTL0_CTSEN_A :: CTL0_CTSEN_DISABLE , true => CTL0_CTSEN_A :: CTL0_CTSEN_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_ctl0_ctsen_disable (& self) -> bool { * self == CTL0_CTSEN_A :: CTL0_CTSEN_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_ctl0_ctsen_enable (& self) -> bool { * self == CTL0_CTSEN_A :: CTL0_CTSEN_ENABLE } } # [doc = "Field `CTL0_CTSEN` writer - Enable Clear To Send"] pub type CTL0_CTSEN_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL0_CTSEN_A > ; impl < 'a , REG , const O : u8 > CTL0_CTSEN_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn ctl0_ctsen_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_CTSEN_A :: CTL0_CTSEN_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn ctl0_ctsen_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_CTSEN_A :: CTL0_CTSEN_ENABLE) } } # [doc = "Field `CTL0_HSE` reader - High-Speed Bit Oversampling Enable #b#NOTE:#/b# The bit oversampling influences the UART baud-rate configuration (see and ). The state of this bit has no effect on clock generation in ISO7816 smart card mode (the SMART bit is set)."] pub type CTL0_HSE_R = crate :: FieldReader < CTL0_HSE_A > ; # [doc = "High-Speed Bit Oversampling Enable #b#NOTE:#/b# The bit oversampling influences the UART baud-rate configuration (see and ). The state of this bit has no effect on clock generation in ISO7816 smart card mode (the SMART bit is set).\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum CTL0_HSE_A { # [doc = "0: OVS16"] CTL0_HSE_OVS16 = 0 , # [doc = "1: OVS8"] CTL0_HSE_OVS8 = 1 , # [doc = "2: OVS3"] CTL0_HSE_OVS3 = 2 , } impl From < CTL0_HSE_A > for u8 { # [inline (always)] fn from (variant : CTL0_HSE_A) -> Self { variant as _ } } impl crate :: FieldSpec for CTL0_HSE_A { type Ux = u8 ; } impl CTL0_HSE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < CTL0_HSE_A > { match self . bits { 0 => Some (CTL0_HSE_A :: CTL0_HSE_OVS16) , 1 => Some (CTL0_HSE_A :: CTL0_HSE_OVS8) , 2 => Some (CTL0_HSE_A :: CTL0_HSE_OVS3) , _ => None , } } # [doc = "OVS16"] # [inline (always)] pub fn is_ctl0_hse_ovs16 (& self) -> bool { * self == CTL0_HSE_A :: CTL0_HSE_OVS16 } # [doc = "OVS8"] # [inline (always)] pub fn is_ctl0_hse_ovs8 (& self) -> bool { * self == CTL0_HSE_A :: CTL0_HSE_OVS8 } # [doc = "OVS3"] # [inline (always)] pub fn is_ctl0_hse_ovs3 (& self) -> bool { * self == CTL0_HSE_A :: CTL0_HSE_OVS3 } } # [doc = "Field `CTL0_HSE` writer - High-Speed Bit Oversampling Enable #b#NOTE:#/b# The bit oversampling influences the UART baud-rate configuration (see and ). The state of this bit has no effect on clock generation in ISO7816 smart card mode (the SMART bit is set)."] pub type CTL0_HSE_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 2 , O , CTL0_HSE_A > ; impl < 'a , REG , const O : u8 > CTL0_HSE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "OVS16"] # [inline (always)] pub fn ctl0_hse_ovs16 (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_HSE_A :: CTL0_HSE_OVS16) } # [doc = "OVS8"] # [inline (always)] pub fn ctl0_hse_ovs8 (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_HSE_A :: CTL0_HSE_OVS8) } # [doc = "OVS3"] # [inline (always)] pub fn ctl0_hse_ovs3 (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_HSE_A :: CTL0_HSE_OVS3) } } # [doc = "Field `CTL0_FEN` reader - UART Enable FIFOs"] pub type CTL0_FEN_R = crate :: BitReader < CTL0_FEN_A > ; # [doc = "UART Enable FIFOs\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CTL0_FEN_A { # [doc = "0: DISABLE"] CTL0_FEN_DISABLE = 0 , # [doc = "1: ENABLE"] CTL0_FEN_ENABLE = 1 , } impl From < CTL0_FEN_A > for bool { # [inline (always)] fn from (variant : CTL0_FEN_A) -> Self { variant as u8 != 0 } } impl CTL0_FEN_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CTL0_FEN_A { match self . bits { false => CTL0_FEN_A :: CTL0_FEN_DISABLE , true => CTL0_FEN_A :: CTL0_FEN_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_ctl0_fen_disable (& self) -> bool { * self == CTL0_FEN_A :: CTL0_FEN_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_ctl0_fen_enable (& self) -> bool { * self == CTL0_FEN_A :: CTL0_FEN_ENABLE } } # [doc = "Field `CTL0_FEN` writer - UART Enable FIFOs"] pub type CTL0_FEN_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL0_FEN_A > ; impl < 'a , REG , const O : u8 > CTL0_FEN_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn ctl0_fen_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_FEN_A :: CTL0_FEN_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn ctl0_fen_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_FEN_A :: CTL0_FEN_ENABLE) } } # [doc = "Field `CTL0_MAJVOTE` reader - When enabled with oversmapling of 16, samples samples 7, 8, and 9 are majority voted to decide the sampled bit value. The value correspond to al least 2 of the 3 samples is considered to be the received value. In case the 3 values do not match, RIS.NERR bit is set along with RDR.NERR When enabled with oversmapling of 8, samples samples 3, 4, and 5 are majority voted to decide the sampled bit value. The value correspond to al least 2 of the 3 samples is considered to be the received value. In case the 3 values donot match, RIS.NERR bit is set along with RDR.NERR When disabled, only a single sample of received bit is taken."] pub type CTL0_MAJVOTE_R = crate :: BitReader < CTL0_MAJVOTE_A > ; # [doc = "When enabled with oversmapling of 16, samples samples 7, 8, and 9 are majority voted to decide the sampled bit value. The value correspond to al least 2 of the 3 samples is considered to be the received value. In case the 3 values do not match, RIS.NERR bit is set along with RDR.NERR When enabled with oversmapling of 8, samples samples 3, 4, and 5 are majority voted to decide the sampled bit value. The value correspond to al least 2 of the 3 samples is considered to be the received value. In case the 3 values donot match, RIS.NERR bit is set along with RDR.NERR When disabled, only a single sample of received bit is taken.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CTL0_MAJVOTE_A { # [doc = "0: DISABLE"] CTL0_MAJVOTE_DISABLE = 0 , # [doc = "1: ENABLE"] CTL0_MAJVOTE_ENABLE = 1 , } impl From < CTL0_MAJVOTE_A > for bool { # [inline (always)] fn from (variant : CTL0_MAJVOTE_A) -> Self { variant as u8 != 0 } } impl CTL0_MAJVOTE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CTL0_MAJVOTE_A { match self . bits { false => CTL0_MAJVOTE_A :: CTL0_MAJVOTE_DISABLE , true => CTL0_MAJVOTE_A :: CTL0_MAJVOTE_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_ctl0_majvote_disable (& self) -> bool { * self == CTL0_MAJVOTE_A :: CTL0_MAJVOTE_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_ctl0_majvote_enable (& self) -> bool { * self == CTL0_MAJVOTE_A :: CTL0_MAJVOTE_ENABLE } } # [doc = "Field `CTL0_MAJVOTE` writer - When enabled with oversmapling of 16, samples samples 7, 8, and 9 are majority voted to decide the sampled bit value. The value correspond to al least 2 of the 3 samples is considered to be the received value. In case the 3 values do not match, RIS.NERR bit is set along with RDR.NERR When enabled with oversmapling of 8, samples samples 3, 4, and 5 are majority voted to decide the sampled bit value. The value correspond to al least 2 of the 3 samples is considered to be the received value. In case the 3 values donot match, RIS.NERR bit is set along with RDR.NERR When disabled, only a single sample of received bit is taken."] pub type CTL0_MAJVOTE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL0_MAJVOTE_A > ; impl < 'a , REG , const O : u8 > CTL0_MAJVOTE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn ctl0_majvote_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_MAJVOTE_A :: CTL0_MAJVOTE_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn ctl0_majvote_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_MAJVOTE_A :: CTL0_MAJVOTE_ENABLE) } } # [doc = "Field `CTL0_MSBFIRST` reader - Most Significant Bit First This bit has effect both on the way protocol byte is transmitted and received. Notes: User needs to match the protocol to the correct value of this bit to send MSb or LSb first. The hardware engine will send the byte entirely based on this bit."] pub type CTL0_MSBFIRST_R = crate :: BitReader < CTL0_MSBFIRST_A > ; # [doc = "Most Significant Bit First This bit has effect both on the way protocol byte is transmitted and received. Notes: User needs to match the protocol to the correct value of this bit to send MSb or LSb first. The hardware engine will send the byte entirely based on this bit.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CTL0_MSBFIRST_A { # [doc = "0: DISABLE"] CTL0_MSBFIRST_DISABLE = 0 , # [doc = "1: ENABLE"] CTL0_MSBFIRST_ENABLE = 1 , } impl From < CTL0_MSBFIRST_A > for bool { # [inline (always)] fn from (variant : CTL0_MSBFIRST_A) -> Self { variant as u8 != 0 } } impl CTL0_MSBFIRST_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CTL0_MSBFIRST_A { match self . bits { false => CTL0_MSBFIRST_A :: CTL0_MSBFIRST_DISABLE , true => CTL0_MSBFIRST_A :: CTL0_MSBFIRST_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_ctl0_msbfirst_disable (& self) -> bool { * self == CTL0_MSBFIRST_A :: CTL0_MSBFIRST_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_ctl0_msbfirst_enable (& self) -> bool { * self == CTL0_MSBFIRST_A :: CTL0_MSBFIRST_ENABLE } } # [doc = "Field `CTL0_MSBFIRST` writer - Most Significant Bit First This bit has effect both on the way protocol byte is transmitted and received. Notes: User needs to match the protocol to the correct value of this bit to send MSb or LSb first. The hardware engine will send the byte entirely based on this bit."] pub type CTL0_MSBFIRST_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL0_MSBFIRST_A > ; impl < 'a , REG , const O : u8 > CTL0_MSBFIRST_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn ctl0_msbfirst_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_MSBFIRST_A :: CTL0_MSBFIRST_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn ctl0_msbfirst_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_MSBFIRST_A :: CTL0_MSBFIRST_ENABLE) } } impl R { # [doc = "Bit 0 - UART Module Enable. If the UART is disabled in the middle of transmission or reception, it completes the current character before stopping. If the ENABLE bit is not set, all registers can still be accessed and updated. It is recommended to setup and change the UART operation mode with having the ENABLE bit cleared to avoid unpredictable behavior during the setup or update. If disabled the UART module will not send or receive any data and the logic is held in reset state."] # [inline (always)] pub fn ctl0_enable (& self) -> CTL0_ENABLE_R { CTL0_ENABLE_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 2 - UART Loop Back Enable"] # [inline (always)] pub fn ctl0_lbe (& self) -> CTL0_LBE_R { CTL0_LBE_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - UART Receive Enable If the UART is disabled in the middle of a receive, it completes the current character before stopping. #b#NOTE:#/b# To enable reception, the UARTEN bit must be set."] # [inline (always)] pub fn ctl0_rxe (& self) -> CTL0_RXE_R { CTL0_RXE_R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - UART Transmit Enable If the UART is disabled in the middle of a transmission, it completes the current character before stopping. #b#NOTE:#/b# To enable transmission, the UARTEN bit must be set."] # [inline (always)] pub fn ctl0_txe (& self) -> CTL0_TXE_R { CTL0_TXE_R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - TXD Pin Control Enable. When the transmit section of the UART is disabled (TXE = 0), the TXD pin can be controlled by the TXD_OUT bit. 1 = UARTxTXD pin can be controlled by TXD_OUT, if TXE = 0"] # [inline (always)] pub fn ctl0_txd_out_en (& self) -> CTL0_TXD_OUT_EN_R { CTL0_TXD_OUT_EN_R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - TXD Pin Control Controls the TXD pin when TXD_OUT_EN = 1 and TXE = 0."] # [inline (always)] pub fn ctl0_txd_out (& self) -> CTL0_TXD_OUT_R { CTL0_TXD_OUT_R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - Manchester Encode enable"] # [inline (always)] pub fn ctl0_menc (& self) -> CTL0_MENC_R { CTL0_MENC_R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bits 8:10 - Set the communication mode and protocol used. (Not defined settings uses the default setting: 0)"] # [inline (always)] pub fn ctl0_mode (& self) -> CTL0_MODE_R { CTL0_MODE_R :: new (((self . bits >> 8) & 7) as u8) } # [doc = "Bit 12 - Request to Send If RTSEN is set the RTS output signals is controlled by the hardware logic using the FIFO fill level or TXDATA buffer. If RTSEN is cleared the RTS output is controlled by the RTS bit. The bit is the complement of the UART request to send, RTS modem status output."] # [inline (always)] pub fn ctl0_rts (& self) -> CTL0_RTS_R { CTL0_RTS_R :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - Enable hardware controlled Request to Send"] # [inline (always)] pub fn ctl0_rtsen (& self) -> CTL0_RTSEN_R { CTL0_RTSEN_R :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 14 - Enable Clear To Send"] # [inline (always)] pub fn ctl0_ctsen (& self) -> CTL0_CTSEN_R { CTL0_CTSEN_R :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bits 15:16 - High-Speed Bit Oversampling Enable #b#NOTE:#/b# The bit oversampling influences the UART baud-rate configuration (see and ). The state of this bit has no effect on clock generation in ISO7816 smart card mode (the SMART bit is set)."] # [inline (always)] pub fn ctl0_hse (& self) -> CTL0_HSE_R { CTL0_HSE_R :: new (((self . bits >> 15) & 3) as u8) } # [doc = "Bit 17 - UART Enable FIFOs"] # [inline (always)] pub fn ctl0_fen (& self) -> CTL0_FEN_R { CTL0_FEN_R :: new (((self . bits >> 17) & 1) != 0) } # [doc = "Bit 18 - When enabled with oversmapling of 16, samples samples 7, 8, and 9 are majority voted to decide the sampled bit value. The value correspond to al least 2 of the 3 samples is considered to be the received value. In case the 3 values do not match, RIS.NERR bit is set along with RDR.NERR When enabled with oversmapling of 8, samples samples 3, 4, and 5 are majority voted to decide the sampled bit value. The value correspond to al least 2 of the 3 samples is considered to be the received value. In case the 3 values donot match, RIS.NERR bit is set along with RDR.NERR When disabled, only a single sample of received bit is taken."] # [inline (always)] pub fn ctl0_majvote (& self) -> CTL0_MAJVOTE_R { CTL0_MAJVOTE_R :: new (((self . bits >> 18) & 1) != 0) } # [doc = "Bit 19 - Most Significant Bit First This bit has effect both on the way protocol byte is transmitted and received. Notes: User needs to match the protocol to the correct value of this bit to send MSb or LSb first. The hardware engine will send the byte entirely based on this bit."] # [inline (always)] pub fn ctl0_msbfirst (& self) -> CTL0_MSBFIRST_R { CTL0_MSBFIRST_R :: new (((self . bits >> 19) & 1) != 0) } } impl W { # [doc = "Bit 0 - UART Module Enable. If the UART is disabled in the middle of transmission or reception, it completes the current character before stopping. If the ENABLE bit is not set, all registers can still be accessed and updated. It is recommended to setup and change the UART operation mode with having the ENABLE bit cleared to avoid unpredictable behavior during the setup or update. If disabled the UART module will not send or receive any data and the logic is held in reset state."] # [inline (always)] # [must_use] pub fn ctl0_enable (& mut self) -> CTL0_ENABLE_W <'_,  CTL0_SPEC , 0 > { CTL0_ENABLE_W :: new (self) } # [doc = "Bit 2 - UART Loop Back Enable"] # [inline (always)] # [must_use] pub fn ctl0_lbe (& mut self) -> CTL0_LBE_W < CTL0_SPEC , 2 > { CTL0_LBE_W :: new (self) } # [doc = "Bit 3 - UART Receive Enable If the UART is disabled in the middle of a receive, it completes the current character before stopping. #b#NOTE:#/b# To enable reception, the UARTEN bit must be set."] # [inline (always)] # [must_use] pub fn ctl0_rxe (& mut self) -> CTL0_RXE_W < CTL0_SPEC , 3 > { CTL0_RXE_W :: new (self) } # [doc = "Bit 4 - UART Transmit Enable If the UART is disabled in the middle of a transmission, it completes the current character before stopping. #b#NOTE:#/b# To enable transmission, the UARTEN bit must be set."] # [inline (always)] # [must_use] pub fn ctl0_txe (& mut self) -> CTL0_TXE_W < CTL0_SPEC , 4 > { CTL0_TXE_W :: new (self) } # [doc = "Bit 5 - TXD Pin Control Enable. When the transmit section of the UART is disabled (TXE = 0), the TXD pin can be controlled by the TXD_OUT bit. 1 = UARTxTXD pin can be controlled by TXD_OUT, if TXE = 0"] # [inline (always)] # [must_use] pub fn ctl0_txd_out_en (& mut self) -> CTL0_TXD_OUT_EN_W < CTL0_SPEC , 5 > { CTL0_TXD_OUT_EN_W :: new (self) } # [doc = "Bit 6 - TXD Pin Control Controls the TXD pin when TXD_OUT_EN = 1 and TXE = 0."] # [inline (always)] # [must_use] pub fn ctl0_txd_out (& mut self) -> CTL0_TXD_OUT_W < CTL0_SPEC , 6 > { CTL0_TXD_OUT_W :: new (self) } # [doc = "Bit 7 - Manchester Encode enable"] # [inline (always)] # [must_use] pub fn ctl0_menc (& mut self) -> CTL0_MENC_W < CTL0_SPEC , 7 > { CTL0_MENC_W :: new (self) } # [doc = "Bits 8:10 - Set the communication mode and protocol used. (Not defined settings uses the default setting: 0)"] # [inline (always)] # [must_use] pub fn ctl0_mode (& mut self) -> CTL0_MODE_W < CTL0_SPEC , 8 > { CTL0_MODE_W :: new (self) } # [doc = "Bit 12 - Request to Send If RTSEN is set the RTS output signals is controlled by the hardware logic using the FIFO fill level or TXDATA buffer. If RTSEN is cleared the RTS output is controlled by the RTS bit. The bit is the complement of the UART request to send, RTS modem status output."] # [inline (always)] # [must_use] pub fn ctl0_rts (& mut self) -> CTL0_RTS_W < CTL0_SPEC , 12 > { CTL0_RTS_W :: new (self) } # [doc = "Bit 13 - Enable hardware controlled Request to Send"] # [inline (always)] # [must_use] pub fn ctl0_rtsen (& mut self) -> CTL0_RTSEN_W < CTL0_SPEC , 13 > { CTL0_RTSEN_W :: new (self) } # [doc = "Bit 14 - Enable Clear To Send"] # [inline (always)] # [must_use] pub fn ctl0_ctsen (& mut self) -> CTL0_CTSEN_W < CTL0_SPEC , 14 > { CTL0_CTSEN_W :: new (self) } # [doc = "Bits 15:16 - High-Speed Bit Oversampling Enable #b#NOTE:#/b# The bit oversampling influences the UART baud-rate configuration (see and ). The state of this bit has no effect on clock generation in ISO7816 smart card mode (the SMART bit is set)."] # [inline (always)] # [must_use] pub fn ctl0_hse (& mut self) -> CTL0_HSE_W < CTL0_SPEC , 15 > { CTL0_HSE_W :: new (self) } # [doc = "Bit 17 - UART Enable FIFOs"] # [inline (always)] # [must_use] pub fn ctl0_fen (& mut self) -> CTL0_FEN_W < CTL0_SPEC , 17 > { CTL0_FEN_W :: new (self) } # [doc = "Bit 18 - When enabled with oversmapling of 16, samples samples 7, 8, and 9 are majority voted to decide the sampled bit value. The value correspond to al least 2 of the 3 samples is considered to be the received value. In case the 3 values do not match, RIS.NERR bit is set along with RDR.NERR When enabled with oversmapling of 8, samples samples 3, 4, and 5 are majority voted to decide the sampled bit value. The value correspond to al least 2 of the 3 samples is considered to be the received value. In case the 3 values donot match, RIS.NERR bit is set along with RDR.NERR When disabled, only a single sample of received bit is taken."] # [inline (always)] # [must_use] pub fn ctl0_majvote (& mut self) -> CTL0_MAJVOTE_W < CTL0_SPEC , 18 > { CTL0_MAJVOTE_W :: new (self) } # [doc = "Bit 19 - Most Significant Bit First This bit has effect both on the way protocol byte is transmitted and received. Notes: User needs to match the protocol to the correct value of this bit to send MSb or LSb first. The hardware engine will send the byte entirely based on this bit."] # [inline (always)] # [must_use] pub fn ctl0_msbfirst (& mut self) -> CTL0_MSBFIRST_W < CTL0_SPEC , 19 > { CTL0_MSBFIRST_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "UART Control Register 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctl0::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctl0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CTL0_SPEC ; impl crate :: RegisterSpec for CTL0_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`ctl0::R`](R) reader structure"] impl crate :: Readable for CTL0_SPEC { } # [doc = "`write(|w| ..)` method takes [`ctl0::W`](W) writer structure"] impl crate :: Writable for CTL0_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets CTL0 to value 0x38"] impl crate :: Resettable for CTL0_SPEC { const RESET_VALUE : Self :: Ux = 0x38 ; }
[INFO] [stdout]   |                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                       +++
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing
[INFO] [stdout]  --> src/uart0/int_event0_imask.rs:1:42394
[INFO] [stdout]   |
[INFO] [stdout] 1 | ..._imask_linc1 (& mut self) -> INT_EVENT0_IMASK_LINC1_W < INT_EVENT0_IMASK_SPEC , 8 > { INT_EVENT0_IMASK_LINC1_W :: new (self) } # [...
[INFO] [stdout]   |                  ^^^^^^^^^^     ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here
[INFO] [stdout]   |                  |
[INFO] [stdout]   |                  the lifetime is elided here
[INFO] [stdout]   |
[INFO] [stdout]   = help: the same lifetime is referred to in inconsistent ways, making the signature confusing
[INFO] [stdout] help: use `'_` for type paths
[INFO] [stdout]   |
[INFO] [stdout] 1 | # [doc = "Register `INT_EVENT0_IMASK` reader"] pub type R = crate :: R < INT_EVENT0_IMASK_SPEC > ; # [doc = "Register `INT_EVENT0_IMASK` writer"] pub type W = crate :: W < INT_EVENT0_IMASK_SPEC > ; # [doc = "Field `INT_EVENT0_IMASK_RTOUT` reader - Enable UARTOUT Receive Time-Out Interrupt."] pub type INT_EVENT0_IMASK_RTOUT_R = crate :: BitReader < INT_EVENT0_IMASK_RTOUT_A > ; # [doc = "Enable UARTOUT Receive Time-Out Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_RTOUT_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_RTOUT_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_RTOUT_SET = 1 , } impl From < INT_EVENT0_IMASK_RTOUT_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_RTOUT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_RTOUT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_RTOUT_A { match self . bits { false => INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_CLR , true => INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_rtout_clr (& self) -> bool { * self == INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_rtout_set (& self) -> bool { * self == INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_SET } } # [doc = "Field `INT_EVENT0_IMASK_RTOUT` writer - Enable UARTOUT Receive Time-Out Interrupt."] pub type INT_EVENT0_IMASK_RTOUT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_RTOUT_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_RTOUT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_rtout_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_rtout_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_SET) } } # [doc = "Field `INT_EVENT0_IMASK_FRMERR` reader - Enable UART Framing Error Interrupt."] pub type INT_EVENT0_IMASK_FRMERR_R = crate :: BitReader < INT_EVENT0_IMASK_FRMERR_A > ; # [doc = "Enable UART Framing Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_FRMERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_FRMERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_FRMERR_SET = 1 , } impl From < INT_EVENT0_IMASK_FRMERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_FRMERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_FRMERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_FRMERR_A { match self . bits { false => INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_CLR , true => INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_frmerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_frmerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_FRMERR` writer - Enable UART Framing Error Interrupt."] pub type INT_EVENT0_IMASK_FRMERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_FRMERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_FRMERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_frmerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_frmerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_SET) } } # [doc = "Field `INT_EVENT0_IMASK_PARERR` reader - Enable UART Parity Error Interrupt."] pub type INT_EVENT0_IMASK_PARERR_R = crate :: BitReader < INT_EVENT0_IMASK_PARERR_A > ; # [doc = "Enable UART Parity Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_PARERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_PARERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_PARERR_SET = 1 , } impl From < INT_EVENT0_IMASK_PARERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_PARERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_PARERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_PARERR_A { match self . bits { false => INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_CLR , true => INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_parerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_parerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_PARERR` writer - Enable UART Parity Error Interrupt."] pub type INT_EVENT0_IMASK_PARERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_PARERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_PARERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_parerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_parerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_SET) } } # [doc = "Field `INT_EVENT0_IMASK_BRKERR` reader - Enable UART Break Error Interrupt."] pub type INT_EVENT0_IMASK_BRKERR_R = crate :: BitReader < INT_EVENT0_IMASK_BRKERR_A > ; # [doc = "Enable UART Break Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_BRKERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_BRKERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_BRKERR_SET = 1 , } impl From < INT_EVENT0_IMASK_BRKERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_BRKERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_BRKERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_BRKERR_A { match self . bits { false => INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_CLR , true => INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_brkerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_brkerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_BRKERR` writer - Enable UART Break Error Interrupt."] pub type INT_EVENT0_IMASK_BRKERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_BRKERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_BRKERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_brkerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_brkerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_SET) } } # [doc = "Field `INT_EVENT0_IMASK_OVRERR` reader - Enable UART Receive Overrun Error Interrupt."] pub type INT_EVENT0_IMASK_OVRERR_R = crate :: BitReader < INT_EVENT0_IMASK_OVRERR_A > ; # [doc = "Enable UART Receive Overrun Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_OVRERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_OVRERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_OVRERR_SET = 1 , } impl From < INT_EVENT0_IMASK_OVRERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_OVRERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_OVRERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_OVRERR_A { match self . bits { false => INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_CLR , true => INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_ovrerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_ovrerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_OVRERR` writer - Enable UART Receive Overrun Error Interrupt."] pub type INT_EVENT0_IMASK_OVRERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_OVRERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_OVRERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_ovrerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_ovrerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_SET) } } # [doc = "Field `INT_EVENT0_IMASK_RXNE` reader - Enable Negative Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_IMASK_RXNE_R = crate :: BitReader < INT_EVENT0_IMASK_RXNE_A > ; # [doc = "Enable Negative Edge on UARTxRXD Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_RXNE_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_RXNE_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_RXNE_SET = 1 , } impl From < INT_EVENT0_IMASK_RXNE_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_RXNE_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_RXNE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_RXNE_A { match self . bits { false => INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_CLR , true => INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_rxne_clr (& self) -> bool { * self == INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_rxne_set (& self) -> bool { * self == INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_SET } } # [doc = "Field `INT_EVENT0_IMASK_RXNE` writer - Enable Negative Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_IMASK_RXNE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_RXNE_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_RXNE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_rxne_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_rxne_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_SET) } } # [doc = "Field `INT_EVENT0_IMASK_RXPE` reader - Enable Positive Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_IMASK_RXPE_R = crate :: BitReader < INT_EVENT0_IMASK_RXPE_A > ; # [doc = "Enable Positive Edge on UARTxRXD Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_RXPE_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_RXPE_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_RXPE_SET = 1 , } impl From < INT_EVENT0_IMASK_RXPE_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_RXPE_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_RXPE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_RXPE_A { match self . bits { false => INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_CLR , true => INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_rxpe_clr (& self) -> bool { * self == INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_rxpe_set (& self) -> bool { * self == INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_SET } } # [doc = "Field `INT_EVENT0_IMASK_RXPE` writer - Enable Positive Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_IMASK_RXPE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_RXPE_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_RXPE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_rxpe_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_rxpe_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_SET) } } # [doc = "Field `INT_EVENT0_IMASK_LINC0` reader - Enable LIN Capture 0 / Match Interrupt ."] pub type INT_EVENT0_IMASK_LINC0_R = crate :: BitReader < INT_EVENT0_IMASK_LINC0_A > ; # [doc = "Enable LIN Capture 0 / Match Interrupt .\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_LINC0_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_LINC0_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_LINC0_SET = 1 , } impl From < INT_EVENT0_IMASK_LINC0_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_LINC0_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_LINC0_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_LINC0_A { match self . bits { false => INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_CLR , true => INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_linc0_clr (& self) -> bool { * self == INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_linc0_set (& self) -> bool { * self == INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_SET } } # [doc = "Field `INT_EVENT0_IMASK_LINC0` writer - Enable LIN Capture 0 / Match Interrupt ."] pub type INT_EVENT0_IMASK_LINC0_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_LINC0_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_LINC0_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_linc0_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_linc0_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_SET) } } # [doc = "Field `INT_EVENT0_IMASK_LINC1` reader - Enable LIN Capture 1 Interrupt."] pub type INT_EVENT0_IMASK_LINC1_R = crate :: BitReader < INT_EVENT0_IMASK_LINC1_A > ; # [doc = "Enable LIN Capture 1 Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_LINC1_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_LINC1_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_LINC1_SET = 1 , } impl From < INT_EVENT0_IMASK_LINC1_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_LINC1_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_LINC1_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_LINC1_A { match self . bits { false => INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_CLR , true => INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_linc1_clr (& self) -> bool { * self == INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_linc1_set (& self) -> bool { * self == INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_SET } } # [doc = "Field `INT_EVENT0_IMASK_LINC1` writer - Enable LIN Capture 1 Interrupt."] pub type INT_EVENT0_IMASK_LINC1_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_LINC1_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_LINC1_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_linc1_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_linc1_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_SET) } } # [doc = "Field `INT_EVENT0_IMASK_LINOVF` reader - Enable LIN Hardware Counter Overflow Interrupt."] pub type INT_EVENT0_IMASK_LINOVF_R = crate :: BitReader < INT_EVENT0_IMASK_LINOVF_A > ; # [doc = "Enable LIN Hardware Counter Overflow Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_LINOVF_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_LINOVF_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_LINOVF_SET = 1 , } impl From < INT_EVENT0_IMASK_LINOVF_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_LINOVF_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_LINOVF_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_LINOVF_A { match self . bits { false => INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_CLR , true => INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_linovf_clr (& self) -> bool { * self == INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_linovf_set (& self) -> bool { * self == INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_SET } } # [doc = "Field `INT_EVENT0_IMASK_LINOVF` writer - Enable LIN Hardware Counter Overflow Interrupt."] pub type INT_EVENT0_IMASK_LINOVF_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_LINOVF_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_LINOVF_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_linovf_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_linovf_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_SET) } } # [doc = "Field `INT_EVENT0_IMASK_RXINT` reader - Enable UART Receive Interrupt."] pub type INT_EVENT0_IMASK_RXINT_R = crate :: BitReader < INT_EVENT0_IMASK_RXINT_A > ; # [doc = "Enable UART Receive Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_RXINT_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_RXINT_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_RXINT_SET = 1 , } impl From < INT_EVENT0_IMASK_RXINT_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_RXINT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_RXINT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_RXINT_A { match self . bits { false => INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_CLR , true => INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_rxint_clr (& self) -> bool { * self == INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_rxint_set (& self) -> bool { * self == INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_SET } } # [doc = "Field `INT_EVENT0_IMASK_RXINT` writer - Enable UART Receive Interrupt."] pub type INT_EVENT0_IMASK_RXINT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_RXINT_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_RXINT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_rxint_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_rxint_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_SET) } } # [doc = "Field `INT_EVENT0_IMASK_TXINT` reader - Enable UART Transmit Interrupt."] pub type INT_EVENT0_IMASK_TXINT_R = crate :: BitReader < INT_EVENT0_IMASK_TXINT_A > ; # [doc = "Enable UART Transmit Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_TXINT_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_TXINT_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_TXINT_SET = 1 , } impl From < INT_EVENT0_IMASK_TXINT_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_TXINT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_TXINT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_TXINT_A { match self . bits { false => INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_CLR , true => INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_txint_clr (& self) -> bool { * self == INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_txint_set (& self) -> bool { * self == INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_SET } } # [doc = "Field `INT_EVENT0_IMASK_TXINT` writer - Enable UART Transmit Interrupt."] pub type INT_EVENT0_IMASK_TXINT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_TXINT_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_TXINT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_txint_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_txint_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_SET) } } # [doc = "Field `INT_EVENT0_IMASK_EOT` reader - Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] pub type INT_EVENT0_IMASK_EOT_R = crate :: BitReader < INT_EVENT0_IMASK_EOT_A > ; # [doc = "Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_EOT_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_EOT_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_EOT_SET = 1 , } impl From < INT_EVENT0_IMASK_EOT_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_EOT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_EOT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_EOT_A { match self . bits { false => INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_CLR , true => INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_eot_clr (& self) -> bool { * self == INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_eot_set (& self) -> bool { * self == INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_SET } } # [doc = "Field `INT_EVENT0_IMASK_EOT` writer - Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] pub type INT_EVENT0_IMASK_EOT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_EOT_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_EOT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_eot_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_eot_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_SET) } } # [doc = "Field `INT_EVENT0_IMASK_ADDR_MATCH` reader - Enable Address Match Interrupt."] pub type INT_EVENT0_IMASK_ADDR_MATCH_R = crate :: BitReader < INT_EVENT0_IMASK_ADDR_MATCH_A > ; # [doc = "Enable Address Match Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_ADDR_MATCH_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_ADDR_MATCH_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_ADDR_MATCH_SET = 1 , } impl From < INT_EVENT0_IMASK_ADDR_MATCH_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_ADDR_MATCH_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_ADDR_MATCH_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_ADDR_MATCH_A { match self . bits { false => INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_CLR , true => INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_addr_match_clr (& self) -> bool { * self == INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_addr_match_set (& self) -> bool { * self == INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_SET } } # [doc = "Field `INT_EVENT0_IMASK_ADDR_MATCH` writer - Enable Address Match Interrupt."] pub type INT_EVENT0_IMASK_ADDR_MATCH_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_ADDR_MATCH_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_ADDR_MATCH_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_addr_match_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_addr_match_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_SET) } } # [doc = "Field `INT_EVENT0_IMASK_CTS` reader - Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] pub type INT_EVENT0_IMASK_CTS_R = crate :: BitReader < INT_EVENT0_IMASK_CTS_A > ; # [doc = "Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_CTS_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_CTS_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_CTS_SET = 1 , } impl From < INT_EVENT0_IMASK_CTS_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_CTS_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_CTS_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_CTS_A { match self . bits { false => INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_CLR , true => INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_cts_clr (& self) -> bool { * self == INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_cts_set (& self) -> bool { * self == INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_SET } } # [doc = "Field `INT_EVENT0_IMASK_CTS` writer - Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] pub type INT_EVENT0_IMASK_CTS_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_CTS_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_CTS_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_cts_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_cts_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DMA_DONE_RX` reader - Enable DMA Done on RX Event Channel"] pub type INT_EVENT0_IMASK_DMA_DONE_RX_R = crate :: BitReader < INT_EVENT0_IMASK_DMA_DONE_RX_A > ; # [doc = "Enable DMA Done on RX Event Channel\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DMA_DONE_RX_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DMA_DONE_RX_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DMA_DONE_RX_SET = 1 , } impl From < INT_EVENT0_IMASK_DMA_DONE_RX_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DMA_DONE_RX_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DMA_DONE_RX_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DMA_DONE_RX_A { match self . bits { false => INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_CLR , true => INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dma_done_rx_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dma_done_rx_set (& self) -> bool { * self == INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_SET } } # [doc = "Field `INT_EVENT0_IMASK_DMA_DONE_RX` writer - Enable DMA Done on RX Event Channel"] pub type INT_EVENT0_IMASK_DMA_DONE_RX_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DMA_DONE_RX_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DMA_DONE_RX_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dma_done_rx_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dma_done_rx_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DMA_DONE_TX` reader - Enable DMA Done on TX Event Channel"] pub type INT_EVENT0_IMASK_DMA_DONE_TX_R = crate :: BitReader < INT_EVENT0_IMASK_DMA_DONE_TX_A > ; # [doc = "Enable DMA Done on TX Event Channel\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DMA_DONE_TX_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DMA_DONE_TX_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DMA_DONE_TX_SET = 1 , } impl From < INT_EVENT0_IMASK_DMA_DONE_TX_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DMA_DONE_TX_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DMA_DONE_TX_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DMA_DONE_TX_A { match self . bits { false => INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_CLR , true => INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dma_done_tx_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dma_done_tx_set (& self) -> bool { * self == INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_SET } } # [doc = "Field `INT_EVENT0_IMASK_DMA_DONE_TX` writer - Enable DMA Done on TX Event Channel"] pub type INT_EVENT0_IMASK_DMA_DONE_TX_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DMA_DONE_TX_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DMA_DONE_TX_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dma_done_tx_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dma_done_tx_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_SET) } } # [doc = "Field `INT_EVENT0_IMASK_NERR` reader - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] pub type INT_EVENT0_IMASK_NERR_R = crate :: BitReader < INT_EVENT0_IMASK_NERR_A > ; # [doc = "Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_NERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_NERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_NERR_SET = 1 , } impl From < INT_EVENT0_IMASK_NERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_NERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_NERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_NERR_A { match self . bits { false => INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_CLR , true => INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_nerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_nerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_NERR` writer - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] pub type INT_EVENT0_IMASK_NERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_NERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_NERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_nerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_nerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_SET) } } impl R { # [doc = "Bit 0 - Enable UARTOUT Receive Time-Out Interrupt."] # [inline (always)] pub fn int_event0_imask_rtout (& self) -> INT_EVENT0_IMASK_RTOUT_R { INT_EVENT0_IMASK_RTOUT_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - Enable UART Framing Error Interrupt."] # [inline (always)] pub fn int_event0_imask_frmerr (& self) -> INT_EVENT0_IMASK_FRMERR_R { INT_EVENT0_IMASK_FRMERR_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - Enable UART Parity Error Interrupt."] # [inline (always)] pub fn int_event0_imask_parerr (& self) -> INT_EVENT0_IMASK_PARERR_R { INT_EVENT0_IMASK_PARERR_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - Enable UART Break Error Interrupt."] # [inline (always)] pub fn int_event0_imask_brkerr (& self) -> INT_EVENT0_IMASK_BRKERR_R { INT_EVENT0_IMASK_BRKERR_R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - Enable UART Receive Overrun Error Interrupt."] # [inline (always)] pub fn int_event0_imask_ovrerr (& self) -> INT_EVENT0_IMASK_OVRERR_R { INT_EVENT0_IMASK_OVRERR_R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - Enable Negative Edge on UARTxRXD Interrupt."] # [inline (always)] pub fn int_event0_imask_rxne (& self) -> INT_EVENT0_IMASK_RXNE_R { INT_EVENT0_IMASK_RXNE_R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - Enable Positive Edge on UARTxRXD Interrupt."] # [inline (always)] pub fn int_event0_imask_rxpe (& self) -> INT_EVENT0_IMASK_RXPE_R { INT_EVENT0_IMASK_RXPE_R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - Enable LIN Capture 0 / Match Interrupt ."] # [inline (always)] pub fn int_event0_imask_linc0 (& self) -> INT_EVENT0_IMASK_LINC0_R { INT_EVENT0_IMASK_LINC0_R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - Enable LIN Capture 1 Interrupt."] # [inline (always)] pub fn int_event0_imask_linc1 (& self) -> INT_EVENT0_IMASK_LINC1_R { INT_EVENT0_IMASK_LINC1_R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - Enable LIN Hardware Counter Overflow Interrupt."] # [inline (always)] pub fn int_event0_imask_linovf (& self) -> INT_EVENT0_IMASK_LINOVF_R { INT_EVENT0_IMASK_LINOVF_R :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - Enable UART Receive Interrupt."] # [inline (always)] pub fn int_event0_imask_rxint (& self) -> INT_EVENT0_IMASK_RXINT_R { INT_EVENT0_IMASK_RXINT_R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - Enable UART Transmit Interrupt."] # [inline (always)] pub fn int_event0_imask_txint (& self) -> INT_EVENT0_IMASK_TXINT_R { INT_EVENT0_IMASK_TXINT_R :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] # [inline (always)] pub fn int_event0_imask_eot (& self) -> INT_EVENT0_IMASK_EOT_R { INT_EVENT0_IMASK_EOT_R :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - Enable Address Match Interrupt."] # [inline (always)] pub fn int_event0_imask_addr_match (& self) -> INT_EVENT0_IMASK_ADDR_MATCH_R { INT_EVENT0_IMASK_ADDR_MATCH_R :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 14 - Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] # [inline (always)] pub fn int_event0_imask_cts (& self) -> INT_EVENT0_IMASK_CTS_R { INT_EVENT0_IMASK_CTS_R :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - Enable DMA Done on RX Event Channel"] # [inline (always)] pub fn int_event0_imask_dma_done_rx (& self) -> INT_EVENT0_IMASK_DMA_DONE_RX_R { INT_EVENT0_IMASK_DMA_DONE_RX_R :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bit 16 - Enable DMA Done on TX Event Channel"] # [inline (always)] pub fn int_event0_imask_dma_done_tx (& self) -> INT_EVENT0_IMASK_DMA_DONE_TX_R { INT_EVENT0_IMASK_DMA_DONE_TX_R :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] # [inline (always)] pub fn int_event0_imask_nerr (& self) -> INT_EVENT0_IMASK_NERR_R { INT_EVENT0_IMASK_NERR_R :: new (((self . bits >> 17) & 1) != 0) } } impl W { # [doc = "Bit 0 - Enable UARTOUT Receive Time-Out Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_rtout (& mut self) -> INT_EVENT0_IMASK_RTOUT_W < INT_EVENT0_IMASK_SPEC , 0 > { INT_EVENT0_IMASK_RTOUT_W :: new (self) } # [doc = "Bit 1 - Enable UART Framing Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_frmerr (& mut self) -> INT_EVENT0_IMASK_FRMERR_W < INT_EVENT0_IMASK_SPEC , 1 > { INT_EVENT0_IMASK_FRMERR_W :: new (self) } # [doc = "Bit 2 - Enable UART Parity Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_parerr (& mut self) -> INT_EVENT0_IMASK_PARERR_W < INT_EVENT0_IMASK_SPEC , 2 > { INT_EVENT0_IMASK_PARERR_W :: new (self) } # [doc = "Bit 3 - Enable UART Break Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_brkerr (& mut self) -> INT_EVENT0_IMASK_BRKERR_W < INT_EVENT0_IMASK_SPEC , 3 > { INT_EVENT0_IMASK_BRKERR_W :: new (self) } # [doc = "Bit 4 - Enable UART Receive Overrun Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_ovrerr (& mut self) -> INT_EVENT0_IMASK_OVRERR_W < INT_EVENT0_IMASK_SPEC , 4 > { INT_EVENT0_IMASK_OVRERR_W :: new (self) } # [doc = "Bit 5 - Enable Negative Edge on UARTxRXD Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_rxne (& mut self) -> INT_EVENT0_IMASK_RXNE_W < INT_EVENT0_IMASK_SPEC , 5 > { INT_EVENT0_IMASK_RXNE_W :: new (self) } # [doc = "Bit 6 - Enable Positive Edge on UARTxRXD Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_rxpe (& mut self) -> INT_EVENT0_IMASK_RXPE_W < INT_EVENT0_IMASK_SPEC , 6 > { INT_EVENT0_IMASK_RXPE_W :: new (self) } # [doc = "Bit 7 - Enable LIN Capture 0 / Match Interrupt ."] # [inline (always)] # [must_use] pub fn int_event0_imask_linc0 (& mut self) -> INT_EVENT0_IMASK_LINC0_W < INT_EVENT0_IMASK_SPEC , 7 > { INT_EVENT0_IMASK_LINC0_W :: new (self) } # [doc = "Bit 8 - Enable LIN Capture 1 Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_linc1 (& mut self) -> INT_EVENT0_IMASK_LINC1_W <'_,  INT_EVENT0_IMASK_SPEC , 8 > { INT_EVENT0_IMASK_LINC1_W :: new (self) } # [doc = "Bit 9 - Enable LIN Hardware Counter Overflow Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_linovf (& mut self) -> INT_EVENT0_IMASK_LINOVF_W < INT_EVENT0_IMASK_SPEC , 9 > { INT_EVENT0_IMASK_LINOVF_W :: new (self) } # [doc = "Bit 10 - Enable UART Receive Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_rxint (& mut self) -> INT_EVENT0_IMASK_RXINT_W < INT_EVENT0_IMASK_SPEC , 10 > { INT_EVENT0_IMASK_RXINT_W :: new (self) } # [doc = "Bit 11 - Enable UART Transmit Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_txint (& mut self) -> INT_EVENT0_IMASK_TXINT_W < INT_EVENT0_IMASK_SPEC , 11 > { INT_EVENT0_IMASK_TXINT_W :: new (self) } # [doc = "Bit 12 - Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] # [inline (always)] # [must_use] pub fn int_event0_imask_eot (& mut self) -> INT_EVENT0_IMASK_EOT_W < INT_EVENT0_IMASK_SPEC , 12 > { INT_EVENT0_IMASK_EOT_W :: new (self) } # [doc = "Bit 13 - Enable Address Match Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_addr_match (& mut self) -> INT_EVENT0_IMASK_ADDR_MATCH_W < INT_EVENT0_IMASK_SPEC , 13 > { INT_EVENT0_IMASK_ADDR_MATCH_W :: new (self) } # [doc = "Bit 14 - Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] # [inline (always)] # [must_use] pub fn int_event0_imask_cts (& mut self) -> INT_EVENT0_IMASK_CTS_W < INT_EVENT0_IMASK_SPEC , 14 > { INT_EVENT0_IMASK_CTS_W :: new (self) } # [doc = "Bit 15 - Enable DMA Done on RX Event Channel"] # [inline (always)] # [must_use] pub fn int_event0_imask_dma_done_rx (& mut self) -> INT_EVENT0_IMASK_DMA_DONE_RX_W < INT_EVENT0_IMASK_SPEC , 15 > { INT_EVENT0_IMASK_DMA_DONE_RX_W :: new (self) } # [doc = "Bit 16 - Enable DMA Done on TX Event Channel"] # [inline (always)] # [must_use] pub fn int_event0_imask_dma_done_tx (& mut self) -> INT_EVENT0_IMASK_DMA_DONE_TX_W < INT_EVENT0_IMASK_SPEC , 16 > { INT_EVENT0_IMASK_DMA_DONE_TX_W :: new (self) } # [doc = "Bit 17 - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] # [inline (always)] # [must_use] pub fn int_event0_imask_nerr (& mut self) -> INT_EVENT0_IMASK_NERR_W < INT_EVENT0_IMASK_SPEC , 17 > { INT_EVENT0_IMASK_NERR_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Interrupt mask\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_event0_imask::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_event0_imask::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct INT_EVENT0_IMASK_SPEC ; impl crate :: RegisterSpec for INT_EVENT0_IMASK_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`int_event0_imask::R`](R) reader structure"] impl crate :: Readable for INT_EVENT0_IMASK_SPEC { } # [doc = "`write(|w| ..)` method takes [`int_event0_imask::W`](W) writer structure"] impl crate :: Writable for INT_EVENT0_IMASK_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets INT_EVENT0_IMASK to value 0"] impl crate :: Resettable for INT_EVENT0_IMASK_SPEC { const RESET_VALUE : Self :: Ux = 0 ; }
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                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                    +++
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing
[INFO] [stdout]  --> src/uart0/ctl0.rs:1:38836
[INFO] [stdout]   |
[INFO] [stdout] 1 | ...must_use] pub fn ctl0_lbe (& mut self) -> CTL0_LBE_W < CTL0_SPEC , 2 > { CTL0_LBE_W :: new (self) } # [doc = "Bit 3 - UART Receive...
[INFO] [stdout]   |                               ^^^^^^^^^^     ^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here
[INFO] [stdout]   |                               |
[INFO] [stdout]   |                               the lifetime is elided here
[INFO] [stdout]   |
[INFO] [stdout]   = help: the same lifetime is referred to in inconsistent ways, making the signature confusing
[INFO] [stdout] help: use `'_` for type paths
[INFO] [stdout]   |
[INFO] [stdout] 1 | # [doc = "Register `CTL0` reader"] pub type R = crate :: R < CTL0_SPEC > ; # [doc = "Register `CTL0` writer"] pub type W = crate :: W < CTL0_SPEC > ; # [doc = "Field `CTL0_ENABLE` reader - UART Module Enable. If the UART is disabled in the middle of transmission or reception, it completes the current character before stopping. If the ENABLE bit is not set, all registers can still be accessed and updated. It is recommended to setup and change the UART operation mode with having the ENABLE bit cleared to avoid unpredictable behavior during the setup or update. If disabled the UART module will not send or receive any data and the logic is held in reset state."] pub type CTL0_ENABLE_R = crate :: BitReader < CTL0_ENABLE_A > ; # [doc = "UART Module Enable. If the UART is disabled in the middle of transmission or reception, it completes the current character before stopping. If the ENABLE bit is not set, all registers can still be accessed and updated. It is recommended to setup and change the UART operation mode with having the ENABLE bit cleared to avoid unpredictable behavior during the setup or update. If disabled the UART module will not send or receive any data and the logic is held in reset state.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CTL0_ENABLE_A { # [doc = "0: DISABLE"] CTL0_ENABLE_DISABLE = 0 , # [doc = "1: ENABLE"] CTL0_ENABLE_ENABLE = 1 , } impl From < CTL0_ENABLE_A > for bool { # [inline (always)] fn from (variant : CTL0_ENABLE_A) -> Self { variant as u8 != 0 } } impl CTL0_ENABLE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CTL0_ENABLE_A { match self . bits { false => CTL0_ENABLE_A :: CTL0_ENABLE_DISABLE , true => CTL0_ENABLE_A :: CTL0_ENABLE_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_ctl0_enable_disable (& self) -> bool { * self == CTL0_ENABLE_A :: CTL0_ENABLE_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_ctl0_enable_enable (& self) -> bool { * self == CTL0_ENABLE_A :: CTL0_ENABLE_ENABLE } } # [doc = "Field `CTL0_ENABLE` writer - UART Module Enable. If the UART is disabled in the middle of transmission or reception, it completes the current character before stopping. If the ENABLE bit is not set, all registers can still be accessed and updated. It is recommended to setup and change the UART operation mode with having the ENABLE bit cleared to avoid unpredictable behavior during the setup or update. If disabled the UART module will not send or receive any data and the logic is held in reset state."] pub type CTL0_ENABLE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL0_ENABLE_A > ; impl < 'a , REG , const O : u8 > CTL0_ENABLE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn ctl0_enable_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_ENABLE_A :: CTL0_ENABLE_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn ctl0_enable_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_ENABLE_A :: CTL0_ENABLE_ENABLE) } } # [doc = "Field `CTL0_LBE` reader - UART Loop Back Enable"] pub type CTL0_LBE_R = crate :: BitReader < CTL0_LBE_A > ; # [doc = "UART Loop Back Enable\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CTL0_LBE_A { # [doc = "0: DISABLE"] CTL0_LBE_DISABLE = 0 , # [doc = "1: ENABLE"] CTL0_LBE_ENABLE = 1 , } impl From < CTL0_LBE_A > for bool { # [inline (always)] fn from (variant : CTL0_LBE_A) -> Self { variant as u8 != 0 } } impl CTL0_LBE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CTL0_LBE_A { match self . bits { false => CTL0_LBE_A :: CTL0_LBE_DISABLE , true => CTL0_LBE_A :: CTL0_LBE_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_ctl0_lbe_disable (& self) -> bool { * self == CTL0_LBE_A :: CTL0_LBE_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_ctl0_lbe_enable (& self) -> bool { * self == CTL0_LBE_A :: CTL0_LBE_ENABLE } } # [doc = "Field `CTL0_LBE` writer - UART Loop Back Enable"] pub type CTL0_LBE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL0_LBE_A > ; impl < 'a , REG , const O : u8 > CTL0_LBE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn ctl0_lbe_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_LBE_A :: CTL0_LBE_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn ctl0_lbe_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_LBE_A :: CTL0_LBE_ENABLE) } } # [doc = "Field `CTL0_RXE` reader - UART Receive Enable If the UART is disabled in the middle of a receive, it completes the current character before stopping. #b#NOTE:#/b# To enable reception, the UARTEN bit must be set."] pub type CTL0_RXE_R = crate :: BitReader < CTL0_RXE_A > ; # [doc = "UART Receive Enable If the UART is disabled in the middle of a receive, it completes the current character before stopping. #b#NOTE:#/b# To enable reception, the UARTEN bit must be set.\n\nValue on reset: 1"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CTL0_RXE_A { # [doc = "0: DISABLE"] CTL0_RXE_DISABLE = 0 , # [doc = "1: ENABLE"] CTL0_RXE_ENABLE = 1 , } impl From < CTL0_RXE_A > for bool { # [inline (always)] fn from (variant : CTL0_RXE_A) -> Self { variant as u8 != 0 } } impl CTL0_RXE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CTL0_RXE_A { match self . bits { false => CTL0_RXE_A :: CTL0_RXE_DISABLE , true => CTL0_RXE_A :: CTL0_RXE_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_ctl0_rxe_disable (& self) -> bool { * self == CTL0_RXE_A :: CTL0_RXE_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_ctl0_rxe_enable (& self) -> bool { * self == CTL0_RXE_A :: CTL0_RXE_ENABLE } } # [doc = "Field `CTL0_RXE` writer - UART Receive Enable If the UART is disabled in the middle of a receive, it completes the current character before stopping. #b#NOTE:#/b# To enable reception, the UARTEN bit must be set."] pub type CTL0_RXE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL0_RXE_A > ; impl < 'a , REG , const O : u8 > CTL0_RXE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn ctl0_rxe_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_RXE_A :: CTL0_RXE_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn ctl0_rxe_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_RXE_A :: CTL0_RXE_ENABLE) } } # [doc = "Field `CTL0_TXE` reader - UART Transmit Enable If the UART is disabled in the middle of a transmission, it completes the current character before stopping. #b#NOTE:#/b# To enable transmission, the UARTEN bit must be set."] pub type CTL0_TXE_R = crate :: BitReader < CTL0_TXE_A > ; # [doc = "UART Transmit Enable If the UART is disabled in the middle of a transmission, it completes the current character before stopping. #b#NOTE:#/b# To enable transmission, the UARTEN bit must be set.\n\nValue on reset: 1"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CTL0_TXE_A { # [doc = "0: DISABLE"] CTL0_TXE_DISABLE = 0 , # [doc = "1: ENABLE"] CTL0_TXE_ENABLE = 1 , } impl From < CTL0_TXE_A > for bool { # [inline (always)] fn from (variant : CTL0_TXE_A) -> Self { variant as u8 != 0 } } impl CTL0_TXE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CTL0_TXE_A { match self . bits { false => CTL0_TXE_A :: CTL0_TXE_DISABLE , true => CTL0_TXE_A :: CTL0_TXE_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_ctl0_txe_disable (& self) -> bool { * self == CTL0_TXE_A :: CTL0_TXE_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_ctl0_txe_enable (& self) -> bool { * self == CTL0_TXE_A :: CTL0_TXE_ENABLE } } # [doc = "Field `CTL0_TXE` writer - UART Transmit Enable If the UART is disabled in the middle of a transmission, it completes the current character before stopping. #b#NOTE:#/b# To enable transmission, the UARTEN bit must be set."] pub type CTL0_TXE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL0_TXE_A > ; impl < 'a , REG , const O : u8 > CTL0_TXE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn ctl0_txe_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_TXE_A :: CTL0_TXE_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn ctl0_txe_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_TXE_A :: CTL0_TXE_ENABLE) } } # [doc = "Field `CTL0_TXD_OUT_EN` reader - TXD Pin Control Enable. When the transmit section of the UART is disabled (TXE = 0), the TXD pin can be controlled by the TXD_OUT bit. 1 = UARTxTXD pin can be controlled by TXD_OUT, if TXE = 0"] pub type CTL0_TXD_OUT_EN_R = crate :: BitReader < CTL0_TXD_OUT_EN_A > ; # [doc = "TXD Pin Control Enable. When the transmit section of the UART is disabled (TXE = 0), the TXD pin can be controlled by the TXD_OUT bit. 1 = UARTxTXD pin can be controlled by TXD_OUT, if TXE = 0\n\nValue on reset: 1"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CTL0_TXD_OUT_EN_A { # [doc = "0: DISABLE"] CTL0_TXD_OUT_EN_DISABLE = 0 , # [doc = "1: ENABLE"] CTL0_TXD_OUT_EN_ENABLE = 1 , } impl From < CTL0_TXD_OUT_EN_A > for bool { # [inline (always)] fn from (variant : CTL0_TXD_OUT_EN_A) -> Self { variant as u8 != 0 } } impl CTL0_TXD_OUT_EN_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CTL0_TXD_OUT_EN_A { match self . bits { false => CTL0_TXD_OUT_EN_A :: CTL0_TXD_OUT_EN_DISABLE , true => CTL0_TXD_OUT_EN_A :: CTL0_TXD_OUT_EN_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_ctl0_txd_out_en_disable (& self) -> bool { * self == CTL0_TXD_OUT_EN_A :: CTL0_TXD_OUT_EN_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_ctl0_txd_out_en_enable (& self) -> bool { * self == CTL0_TXD_OUT_EN_A :: CTL0_TXD_OUT_EN_ENABLE } } # [doc = "Field `CTL0_TXD_OUT_EN` writer - TXD Pin Control Enable. When the transmit section of the UART is disabled (TXE = 0), the TXD pin can be controlled by the TXD_OUT bit. 1 = UARTxTXD pin can be controlled by TXD_OUT, if TXE = 0"] pub type CTL0_TXD_OUT_EN_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL0_TXD_OUT_EN_A > ; impl < 'a , REG , const O : u8 > CTL0_TXD_OUT_EN_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn ctl0_txd_out_en_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_TXD_OUT_EN_A :: CTL0_TXD_OUT_EN_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn ctl0_txd_out_en_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_TXD_OUT_EN_A :: CTL0_TXD_OUT_EN_ENABLE) } } # [doc = "Field `CTL0_TXD_OUT` reader - TXD Pin Control Controls the TXD pin when TXD_OUT_EN = 1 and TXE = 0."] pub type CTL0_TXD_OUT_R = crate :: BitReader < CTL0_TXD_OUT_A > ; # [doc = "TXD Pin Control Controls the TXD pin when TXD_OUT_EN = 1 and TXE = 0.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CTL0_TXD_OUT_A { # [doc = "0: LOW"] CTL0_TXD_OUT_LOW = 0 , # [doc = "1: HIGH"] CTL0_TXD_OUT_HIGH = 1 , } impl From < CTL0_TXD_OUT_A > for bool { # [inline (always)] fn from (variant : CTL0_TXD_OUT_A) -> Self { variant as u8 != 0 } } impl CTL0_TXD_OUT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CTL0_TXD_OUT_A { match self . bits { false => CTL0_TXD_OUT_A :: CTL0_TXD_OUT_LOW , true => CTL0_TXD_OUT_A :: CTL0_TXD_OUT_HIGH , } } # [doc = "LOW"] # [inline (always)] pub fn is_ctl0_txd_out_low (& self) -> bool { * self == CTL0_TXD_OUT_A :: CTL0_TXD_OUT_LOW } # [doc = "HIGH"] # [inline (always)] pub fn is_ctl0_txd_out_high (& self) -> bool { * self == CTL0_TXD_OUT_A :: CTL0_TXD_OUT_HIGH } } # [doc = "Field `CTL0_TXD_OUT` writer - TXD Pin Control Controls the TXD pin when TXD_OUT_EN = 1 and TXE = 0."] pub type CTL0_TXD_OUT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL0_TXD_OUT_A > ; impl < 'a , REG , const O : u8 > CTL0_TXD_OUT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "LOW"] # [inline (always)] pub fn ctl0_txd_out_low (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_TXD_OUT_A :: CTL0_TXD_OUT_LOW) } # [doc = "HIGH"] # [inline (always)] pub fn ctl0_txd_out_high (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_TXD_OUT_A :: CTL0_TXD_OUT_HIGH) } } # [doc = "Field `CTL0_MENC` reader - Manchester Encode enable"] pub type CTL0_MENC_R = crate :: BitReader < CTL0_MENC_A > ; # [doc = "Manchester Encode enable\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CTL0_MENC_A { # [doc = "0: DISABLE"] CTL0_MENC_DISABLE = 0 , # [doc = "1: ENABLE"] CTL0_MENC_ENABLE = 1 , } impl From < CTL0_MENC_A > for bool { # [inline (always)] fn from (variant : CTL0_MENC_A) -> Self { variant as u8 != 0 } } impl CTL0_MENC_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CTL0_MENC_A { match self . bits { false => CTL0_MENC_A :: CTL0_MENC_DISABLE , true => CTL0_MENC_A :: CTL0_MENC_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_ctl0_menc_disable (& self) -> bool { * self == CTL0_MENC_A :: CTL0_MENC_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_ctl0_menc_enable (& self) -> bool { * self == CTL0_MENC_A :: CTL0_MENC_ENABLE } } # [doc = "Field `CTL0_MENC` writer - Manchester Encode enable"] pub type CTL0_MENC_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL0_MENC_A > ; impl < 'a , REG , const O : u8 > CTL0_MENC_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn ctl0_menc_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_MENC_A :: CTL0_MENC_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn ctl0_menc_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_MENC_A :: CTL0_MENC_ENABLE) } } # [doc = "Field `CTL0_MODE` reader - Set the communication mode and protocol used. (Not defined settings uses the default setting: 0)"] pub type CTL0_MODE_R = crate :: FieldReader < CTL0_MODE_A > ; # [doc = "Set the communication mode and protocol used. (Not defined settings uses the default setting: 0)\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum CTL0_MODE_A { # [doc = "0: UART"] CTL0_MODE_UART = 0 , # [doc = "1: RS485"] CTL0_MODE_RS485 = 1 , # [doc = "2: IDLELINE"] CTL0_MODE_IDLELINE = 2 , # [doc = "3: ADDR9BIT"] CTL0_MODE_ADDR9BIT = 3 , # [doc = "4: SMART"] CTL0_MODE_SMART = 4 , # [doc = "5: DALI"] CTL0_MODE_DALI = 5 , } impl From < CTL0_MODE_A > for u8 { # [inline (always)] fn from (variant : CTL0_MODE_A) -> Self { variant as _ } } impl crate :: FieldSpec for CTL0_MODE_A { type Ux = u8 ; } impl CTL0_MODE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < CTL0_MODE_A > { match self . bits { 0 => Some (CTL0_MODE_A :: CTL0_MODE_UART) , 1 => Some (CTL0_MODE_A :: CTL0_MODE_RS485) , 2 => Some (CTL0_MODE_A :: CTL0_MODE_IDLELINE) , 3 => Some (CTL0_MODE_A :: CTL0_MODE_ADDR9BIT) , 4 => Some (CTL0_MODE_A :: CTL0_MODE_SMART) , 5 => Some (CTL0_MODE_A :: CTL0_MODE_DALI) , _ => None , } } # [doc = "UART"] # [inline (always)] pub fn is_ctl0_mode_uart (& self) -> bool { * self == CTL0_MODE_A :: CTL0_MODE_UART } # [doc = "RS485"] # [inline (always)] pub fn is_ctl0_mode_rs485 (& self) -> bool { * self == CTL0_MODE_A :: CTL0_MODE_RS485 } # [doc = "IDLELINE"] # [inline (always)] pub fn is_ctl0_mode_idleline (& self) -> bool { * self == CTL0_MODE_A :: CTL0_MODE_IDLELINE } # [doc = "ADDR9BIT"] # [inline (always)] pub fn is_ctl0_mode_addr9bit (& self) -> bool { * self == CTL0_MODE_A :: CTL0_MODE_ADDR9BIT } # [doc = "SMART"] # [inline (always)] pub fn is_ctl0_mode_smart (& self) -> bool { * self == CTL0_MODE_A :: CTL0_MODE_SMART } # [doc = "DALI"] # [inline (always)] pub fn is_ctl0_mode_dali (& self) -> bool { * self == CTL0_MODE_A :: CTL0_MODE_DALI } } # [doc = "Field `CTL0_MODE` writer - Set the communication mode and protocol used. (Not defined settings uses the default setting: 0)"] pub type CTL0_MODE_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 3 , O , CTL0_MODE_A > ; impl < 'a , REG , const O : u8 > CTL0_MODE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "UART"] # [inline (always)] pub fn ctl0_mode_uart (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_MODE_A :: CTL0_MODE_UART) } # [doc = "RS485"] # [inline (always)] pub fn ctl0_mode_rs485 (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_MODE_A :: CTL0_MODE_RS485) } # [doc = "IDLELINE"] # [inline (always)] pub fn ctl0_mode_idleline (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_MODE_A :: CTL0_MODE_IDLELINE) } # [doc = "ADDR9BIT"] # [inline (always)] pub fn ctl0_mode_addr9bit (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_MODE_A :: CTL0_MODE_ADDR9BIT) } # [doc = "SMART"] # [inline (always)] pub fn ctl0_mode_smart (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_MODE_A :: CTL0_MODE_SMART) } # [doc = "DALI"] # [inline (always)] pub fn ctl0_mode_dali (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_MODE_A :: CTL0_MODE_DALI) } } # [doc = "Field `CTL0_RTS` reader - Request to Send If RTSEN is set the RTS output signals is controlled by the hardware logic using the FIFO fill level or TXDATA buffer. If RTSEN is cleared the RTS output is controlled by the RTS bit. The bit is the complement of the UART request to send, RTS modem status output."] pub type CTL0_RTS_R = crate :: BitReader < CTL0_RTS_A > ; # [doc = "Request to Send If RTSEN is set the RTS output signals is controlled by the hardware logic using the FIFO fill level or TXDATA buffer. If RTSEN is cleared the RTS output is controlled by the RTS bit. The bit is the complement of the UART request to send, RTS modem status output.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CTL0_RTS_A { # [doc = "0: CLR"] CTL0_RTS_CLR = 0 , # [doc = "1: SET"] CTL0_RTS_SET = 1 , } impl From < CTL0_RTS_A > for bool { # [inline (always)] fn from (variant : CTL0_RTS_A) -> Self { variant as u8 != 0 } } impl CTL0_RTS_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CTL0_RTS_A { match self . bits { false => CTL0_RTS_A :: CTL0_RTS_CLR , true => CTL0_RTS_A :: CTL0_RTS_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_ctl0_rts_clr (& self) -> bool { * self == CTL0_RTS_A :: CTL0_RTS_CLR } # [doc = "SET"] # [inline (always)] pub fn is_ctl0_rts_set (& self) -> bool { * self == CTL0_RTS_A :: CTL0_RTS_SET } } # [doc = "Field `CTL0_RTS` writer - Request to Send If RTSEN is set the RTS output signals is controlled by the hardware logic using the FIFO fill level or TXDATA buffer. If RTSEN is cleared the RTS output is controlled by the RTS bit. The bit is the complement of the UART request to send, RTS modem status output."] pub type CTL0_RTS_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL0_RTS_A > ; impl < 'a , REG , const O : u8 > CTL0_RTS_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn ctl0_rts_clr (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_RTS_A :: CTL0_RTS_CLR) } # [doc = "SET"] # [inline (always)] pub fn ctl0_rts_set (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_RTS_A :: CTL0_RTS_SET) } } # [doc = "Field `CTL0_RTSEN` reader - Enable hardware controlled Request to Send"] pub type CTL0_RTSEN_R = crate :: BitReader < CTL0_RTSEN_A > ; # [doc = "Enable hardware controlled Request to Send\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CTL0_RTSEN_A { # [doc = "0: DISABLE"] CTL0_RTSEN_DISABLE = 0 , # [doc = "1: ENABLE"] CTL0_RTSEN_ENABLE = 1 , } impl From < CTL0_RTSEN_A > for bool { # [inline (always)] fn from (variant : CTL0_RTSEN_A) -> Self { variant as u8 != 0 } } impl CTL0_RTSEN_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CTL0_RTSEN_A { match self . bits { false => CTL0_RTSEN_A :: CTL0_RTSEN_DISABLE , true => CTL0_RTSEN_A :: CTL0_RTSEN_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_ctl0_rtsen_disable (& self) -> bool { * self == CTL0_RTSEN_A :: CTL0_RTSEN_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_ctl0_rtsen_enable (& self) -> bool { * self == CTL0_RTSEN_A :: CTL0_RTSEN_ENABLE } } # [doc = "Field `CTL0_RTSEN` writer - Enable hardware controlled Request to Send"] pub type CTL0_RTSEN_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL0_RTSEN_A > ; impl < 'a , REG , const O : u8 > CTL0_RTSEN_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn ctl0_rtsen_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_RTSEN_A :: CTL0_RTSEN_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn ctl0_rtsen_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_RTSEN_A :: CTL0_RTSEN_ENABLE) } } # [doc = "Field `CTL0_CTSEN` reader - Enable Clear To Send"] pub type CTL0_CTSEN_R = crate :: BitReader < CTL0_CTSEN_A > ; # [doc = "Enable Clear To Send\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CTL0_CTSEN_A { # [doc = "0: DISABLE"] CTL0_CTSEN_DISABLE = 0 , # [doc = "1: ENABLE"] CTL0_CTSEN_ENABLE = 1 , } impl From < CTL0_CTSEN_A > for bool { # [inline (always)] fn from (variant : CTL0_CTSEN_A) -> Self { variant as u8 != 0 } } impl CTL0_CTSEN_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CTL0_CTSEN_A { match self . bits { false => CTL0_CTSEN_A :: CTL0_CTSEN_DISABLE , true => CTL0_CTSEN_A :: CTL0_CTSEN_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_ctl0_ctsen_disable (& self) -> bool { * self == CTL0_CTSEN_A :: CTL0_CTSEN_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_ctl0_ctsen_enable (& self) -> bool { * self == CTL0_CTSEN_A :: CTL0_CTSEN_ENABLE } } # [doc = "Field `CTL0_CTSEN` writer - Enable Clear To Send"] pub type CTL0_CTSEN_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL0_CTSEN_A > ; impl < 'a , REG , const O : u8 > CTL0_CTSEN_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn ctl0_ctsen_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_CTSEN_A :: CTL0_CTSEN_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn ctl0_ctsen_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_CTSEN_A :: CTL0_CTSEN_ENABLE) } } # [doc = "Field `CTL0_HSE` reader - High-Speed Bit Oversampling Enable #b#NOTE:#/b# The bit oversampling influences the UART baud-rate configuration (see and ). The state of this bit has no effect on clock generation in ISO7816 smart card mode (the SMART bit is set)."] pub type CTL0_HSE_R = crate :: FieldReader < CTL0_HSE_A > ; # [doc = "High-Speed Bit Oversampling Enable #b#NOTE:#/b# The bit oversampling influences the UART baud-rate configuration (see and ). The state of this bit has no effect on clock generation in ISO7816 smart card mode (the SMART bit is set).\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum CTL0_HSE_A { # [doc = "0: OVS16"] CTL0_HSE_OVS16 = 0 , # [doc = "1: OVS8"] CTL0_HSE_OVS8 = 1 , # [doc = "2: OVS3"] CTL0_HSE_OVS3 = 2 , } impl From < CTL0_HSE_A > for u8 { # [inline (always)] fn from (variant : CTL0_HSE_A) -> Self { variant as _ } } impl crate :: FieldSpec for CTL0_HSE_A { type Ux = u8 ; } impl CTL0_HSE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < CTL0_HSE_A > { match self . bits { 0 => Some (CTL0_HSE_A :: CTL0_HSE_OVS16) , 1 => Some (CTL0_HSE_A :: CTL0_HSE_OVS8) , 2 => Some (CTL0_HSE_A :: CTL0_HSE_OVS3) , _ => None , } } # [doc = "OVS16"] # [inline (always)] pub fn is_ctl0_hse_ovs16 (& self) -> bool { * self == CTL0_HSE_A :: CTL0_HSE_OVS16 } # [doc = "OVS8"] # [inline (always)] pub fn is_ctl0_hse_ovs8 (& self) -> bool { * self == CTL0_HSE_A :: CTL0_HSE_OVS8 } # [doc = "OVS3"] # [inline (always)] pub fn is_ctl0_hse_ovs3 (& self) -> bool { * self == CTL0_HSE_A :: CTL0_HSE_OVS3 } } # [doc = "Field `CTL0_HSE` writer - High-Speed Bit Oversampling Enable #b#NOTE:#/b# The bit oversampling influences the UART baud-rate configuration (see and ). The state of this bit has no effect on clock generation in ISO7816 smart card mode (the SMART bit is set)."] pub type CTL0_HSE_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 2 , O , CTL0_HSE_A > ; impl < 'a , REG , const O : u8 > CTL0_HSE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "OVS16"] # [inline (always)] pub fn ctl0_hse_ovs16 (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_HSE_A :: CTL0_HSE_OVS16) } # [doc = "OVS8"] # [inline (always)] pub fn ctl0_hse_ovs8 (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_HSE_A :: CTL0_HSE_OVS8) } # [doc = "OVS3"] # [inline (always)] pub fn ctl0_hse_ovs3 (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_HSE_A :: CTL0_HSE_OVS3) } } # [doc = "Field `CTL0_FEN` reader - UART Enable FIFOs"] pub type CTL0_FEN_R = crate :: BitReader < CTL0_FEN_A > ; # [doc = "UART Enable FIFOs\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CTL0_FEN_A { # [doc = "0: DISABLE"] CTL0_FEN_DISABLE = 0 , # [doc = "1: ENABLE"] CTL0_FEN_ENABLE = 1 , } impl From < CTL0_FEN_A > for bool { # [inline (always)] fn from (variant : CTL0_FEN_A) -> Self { variant as u8 != 0 } } impl CTL0_FEN_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CTL0_FEN_A { match self . bits { false => CTL0_FEN_A :: CTL0_FEN_DISABLE , true => CTL0_FEN_A :: CTL0_FEN_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_ctl0_fen_disable (& self) -> bool { * self == CTL0_FEN_A :: CTL0_FEN_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_ctl0_fen_enable (& self) -> bool { * self == CTL0_FEN_A :: CTL0_FEN_ENABLE } } # [doc = "Field `CTL0_FEN` writer - UART Enable FIFOs"] pub type CTL0_FEN_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL0_FEN_A > ; impl < 'a , REG , const O : u8 > CTL0_FEN_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn ctl0_fen_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_FEN_A :: CTL0_FEN_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn ctl0_fen_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_FEN_A :: CTL0_FEN_ENABLE) } } # [doc = "Field `CTL0_MAJVOTE` reader - When enabled with oversmapling of 16, samples samples 7, 8, and 9 are majority voted to decide the sampled bit value. The value correspond to al least 2 of the 3 samples is considered to be the received value. In case the 3 values do not match, RIS.NERR bit is set along with RDR.NERR When enabled with oversmapling of 8, samples samples 3, 4, and 5 are majority voted to decide the sampled bit value. The value correspond to al least 2 of the 3 samples is considered to be the received value. In case the 3 values donot match, RIS.NERR bit is set along with RDR.NERR When disabled, only a single sample of received bit is taken."] pub type CTL0_MAJVOTE_R = crate :: BitReader < CTL0_MAJVOTE_A > ; # [doc = "When enabled with oversmapling of 16, samples samples 7, 8, and 9 are majority voted to decide the sampled bit value. The value correspond to al least 2 of the 3 samples is considered to be the received value. In case the 3 values do not match, RIS.NERR bit is set along with RDR.NERR When enabled with oversmapling of 8, samples samples 3, 4, and 5 are majority voted to decide the sampled bit value. The value correspond to al least 2 of the 3 samples is considered to be the received value. In case the 3 values donot match, RIS.NERR bit is set along with RDR.NERR When disabled, only a single sample of received bit is taken.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CTL0_MAJVOTE_A { # [doc = "0: DISABLE"] CTL0_MAJVOTE_DISABLE = 0 , # [doc = "1: ENABLE"] CTL0_MAJVOTE_ENABLE = 1 , } impl From < CTL0_MAJVOTE_A > for bool { # [inline (always)] fn from (variant : CTL0_MAJVOTE_A) -> Self { variant as u8 != 0 } } impl CTL0_MAJVOTE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CTL0_MAJVOTE_A { match self . bits { false => CTL0_MAJVOTE_A :: CTL0_MAJVOTE_DISABLE , true => CTL0_MAJVOTE_A :: CTL0_MAJVOTE_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_ctl0_majvote_disable (& self) -> bool { * self == CTL0_MAJVOTE_A :: CTL0_MAJVOTE_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_ctl0_majvote_enable (& self) -> bool { * self == CTL0_MAJVOTE_A :: CTL0_MAJVOTE_ENABLE } } # [doc = "Field `CTL0_MAJVOTE` writer - When enabled with oversmapling of 16, samples samples 7, 8, and 9 are majority voted to decide the sampled bit value. The value correspond to al least 2 of the 3 samples is considered to be the received value. In case the 3 values do not match, RIS.NERR bit is set along with RDR.NERR When enabled with oversmapling of 8, samples samples 3, 4, and 5 are majority voted to decide the sampled bit value. The value correspond to al least 2 of the 3 samples is considered to be the received value. In case the 3 values donot match, RIS.NERR bit is set along with RDR.NERR When disabled, only a single sample of received bit is taken."] pub type CTL0_MAJVOTE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL0_MAJVOTE_A > ; impl < 'a , REG , const O : u8 > CTL0_MAJVOTE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn ctl0_majvote_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_MAJVOTE_A :: CTL0_MAJVOTE_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn ctl0_majvote_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_MAJVOTE_A :: CTL0_MAJVOTE_ENABLE) } } # [doc = "Field `CTL0_MSBFIRST` reader - Most Significant Bit First This bit has effect both on the way protocol byte is transmitted and received. Notes: User needs to match the protocol to the correct value of this bit to send MSb or LSb first. The hardware engine will send the byte entirely based on this bit."] pub type CTL0_MSBFIRST_R = crate :: BitReader < CTL0_MSBFIRST_A > ; # [doc = "Most Significant Bit First This bit has effect both on the way protocol byte is transmitted and received. Notes: User needs to match the protocol to the correct value of this bit to send MSb or LSb first. The hardware engine will send the byte entirely based on this bit.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CTL0_MSBFIRST_A { # [doc = "0: DISABLE"] CTL0_MSBFIRST_DISABLE = 0 , # [doc = "1: ENABLE"] CTL0_MSBFIRST_ENABLE = 1 , } impl From < CTL0_MSBFIRST_A > for bool { # [inline (always)] fn from (variant : CTL0_MSBFIRST_A) -> Self { variant as u8 != 0 } } impl CTL0_MSBFIRST_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CTL0_MSBFIRST_A { match self . bits { false => CTL0_MSBFIRST_A :: CTL0_MSBFIRST_DISABLE , true => CTL0_MSBFIRST_A :: CTL0_MSBFIRST_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_ctl0_msbfirst_disable (& self) -> bool { * self == CTL0_MSBFIRST_A :: CTL0_MSBFIRST_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_ctl0_msbfirst_enable (& self) -> bool { * self == CTL0_MSBFIRST_A :: CTL0_MSBFIRST_ENABLE } } # [doc = "Field `CTL0_MSBFIRST` writer - Most Significant Bit First This bit has effect both on the way protocol byte is transmitted and received. Notes: User needs to match the protocol to the correct value of this bit to send MSb or LSb first. The hardware engine will send the byte entirely based on this bit."] pub type CTL0_MSBFIRST_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL0_MSBFIRST_A > ; impl < 'a , REG , const O : u8 > CTL0_MSBFIRST_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn ctl0_msbfirst_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_MSBFIRST_A :: CTL0_MSBFIRST_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn ctl0_msbfirst_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_MSBFIRST_A :: CTL0_MSBFIRST_ENABLE) } } impl R { # [doc = "Bit 0 - UART Module Enable. If the UART is disabled in the middle of transmission or reception, it completes the current character before stopping. If the ENABLE bit is not set, all registers can still be accessed and updated. It is recommended to setup and change the UART operation mode with having the ENABLE bit cleared to avoid unpredictable behavior during the setup or update. If disabled the UART module will not send or receive any data and the logic is held in reset state."] # [inline (always)] pub fn ctl0_enable (& self) -> CTL0_ENABLE_R { CTL0_ENABLE_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 2 - UART Loop Back Enable"] # [inline (always)] pub fn ctl0_lbe (& self) -> CTL0_LBE_R { CTL0_LBE_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - UART Receive Enable If the UART is disabled in the middle of a receive, it completes the current character before stopping. #b#NOTE:#/b# To enable reception, the UARTEN bit must be set."] # [inline (always)] pub fn ctl0_rxe (& self) -> CTL0_RXE_R { CTL0_RXE_R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - UART Transmit Enable If the UART is disabled in the middle of a transmission, it completes the current character before stopping. #b#NOTE:#/b# To enable transmission, the UARTEN bit must be set."] # [inline (always)] pub fn ctl0_txe (& self) -> CTL0_TXE_R { CTL0_TXE_R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - TXD Pin Control Enable. When the transmit section of the UART is disabled (TXE = 0), the TXD pin can be controlled by the TXD_OUT bit. 1 = UARTxTXD pin can be controlled by TXD_OUT, if TXE = 0"] # [inline (always)] pub fn ctl0_txd_out_en (& self) -> CTL0_TXD_OUT_EN_R { CTL0_TXD_OUT_EN_R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - TXD Pin Control Controls the TXD pin when TXD_OUT_EN = 1 and TXE = 0."] # [inline (always)] pub fn ctl0_txd_out (& self) -> CTL0_TXD_OUT_R { CTL0_TXD_OUT_R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - Manchester Encode enable"] # [inline (always)] pub fn ctl0_menc (& self) -> CTL0_MENC_R { CTL0_MENC_R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bits 8:10 - Set the communication mode and protocol used. (Not defined settings uses the default setting: 0)"] # [inline (always)] pub fn ctl0_mode (& self) -> CTL0_MODE_R { CTL0_MODE_R :: new (((self . bits >> 8) & 7) as u8) } # [doc = "Bit 12 - Request to Send If RTSEN is set the RTS output signals is controlled by the hardware logic using the FIFO fill level or TXDATA buffer. If RTSEN is cleared the RTS output is controlled by the RTS bit. The bit is the complement of the UART request to send, RTS modem status output."] # [inline (always)] pub fn ctl0_rts (& self) -> CTL0_RTS_R { CTL0_RTS_R :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - Enable hardware controlled Request to Send"] # [inline (always)] pub fn ctl0_rtsen (& self) -> CTL0_RTSEN_R { CTL0_RTSEN_R :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 14 - Enable Clear To Send"] # [inline (always)] pub fn ctl0_ctsen (& self) -> CTL0_CTSEN_R { CTL0_CTSEN_R :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bits 15:16 - High-Speed Bit Oversampling Enable #b#NOTE:#/b# The bit oversampling influences the UART baud-rate configuration (see and ). The state of this bit has no effect on clock generation in ISO7816 smart card mode (the SMART bit is set)."] # [inline (always)] pub fn ctl0_hse (& self) -> CTL0_HSE_R { CTL0_HSE_R :: new (((self . bits >> 15) & 3) as u8) } # [doc = "Bit 17 - UART Enable FIFOs"] # [inline (always)] pub fn ctl0_fen (& self) -> CTL0_FEN_R { CTL0_FEN_R :: new (((self . bits >> 17) & 1) != 0) } # [doc = "Bit 18 - When enabled with oversmapling of 16, samples samples 7, 8, and 9 are majority voted to decide the sampled bit value. The value correspond to al least 2 of the 3 samples is considered to be the received value. In case the 3 values do not match, RIS.NERR bit is set along with RDR.NERR When enabled with oversmapling of 8, samples samples 3, 4, and 5 are majority voted to decide the sampled bit value. The value correspond to al least 2 of the 3 samples is considered to be the received value. In case the 3 values donot match, RIS.NERR bit is set along with RDR.NERR When disabled, only a single sample of received bit is taken."] # [inline (always)] pub fn ctl0_majvote (& self) -> CTL0_MAJVOTE_R { CTL0_MAJVOTE_R :: new (((self . bits >> 18) & 1) != 0) } # [doc = "Bit 19 - Most Significant Bit First This bit has effect both on the way protocol byte is transmitted and received. Notes: User needs to match the protocol to the correct value of this bit to send MSb or LSb first. The hardware engine will send the byte entirely based on this bit."] # [inline (always)] pub fn ctl0_msbfirst (& self) -> CTL0_MSBFIRST_R { CTL0_MSBFIRST_R :: new (((self . bits >> 19) & 1) != 0) } } impl W { # [doc = "Bit 0 - UART Module Enable. If the UART is disabled in the middle of transmission or reception, it completes the current character before stopping. If the ENABLE bit is not set, all registers can still be accessed and updated. It is recommended to setup and change the UART operation mode with having the ENABLE bit cleared to avoid unpredictable behavior during the setup or update. If disabled the UART module will not send or receive any data and the logic is held in reset state."] # [inline (always)] # [must_use] pub fn ctl0_enable (& mut self) -> CTL0_ENABLE_W < CTL0_SPEC , 0 > { CTL0_ENABLE_W :: new (self) } # [doc = "Bit 2 - UART Loop Back Enable"] # [inline (always)] # [must_use] pub fn ctl0_lbe (& mut self) -> CTL0_LBE_W <'_,  CTL0_SPEC , 2 > { CTL0_LBE_W :: new (self) } # [doc = "Bit 3 - UART Receive Enable If the UART is disabled in the middle of a receive, it completes the current character before stopping. #b#NOTE:#/b# To enable reception, the UARTEN bit must be set."] # [inline (always)] # [must_use] pub fn ctl0_rxe (& mut self) -> CTL0_RXE_W < CTL0_SPEC , 3 > { CTL0_RXE_W :: new (self) } # [doc = "Bit 4 - UART Transmit Enable If the UART is disabled in the middle of a transmission, it completes the current character before stopping. #b#NOTE:#/b# To enable transmission, the UARTEN bit must be set."] # [inline (always)] # [must_use] pub fn ctl0_txe (& mut self) -> CTL0_TXE_W < CTL0_SPEC , 4 > { CTL0_TXE_W :: new (self) } # [doc = "Bit 5 - TXD Pin Control Enable. When the transmit section of the UART is disabled (TXE = 0), the TXD pin can be controlled by the TXD_OUT bit. 1 = UARTxTXD pin can be controlled by TXD_OUT, if TXE = 0"] # [inline (always)] # [must_use] pub fn ctl0_txd_out_en (& mut self) -> CTL0_TXD_OUT_EN_W < CTL0_SPEC , 5 > { CTL0_TXD_OUT_EN_W :: new (self) } # [doc = "Bit 6 - TXD Pin Control Controls the TXD pin when TXD_OUT_EN = 1 and TXE = 0."] # [inline (always)] # [must_use] pub fn ctl0_txd_out (& mut self) -> CTL0_TXD_OUT_W < CTL0_SPEC , 6 > { CTL0_TXD_OUT_W :: new (self) } # [doc = "Bit 7 - Manchester Encode enable"] # [inline (always)] # [must_use] pub fn ctl0_menc (& mut self) -> CTL0_MENC_W < CTL0_SPEC , 7 > { CTL0_MENC_W :: new (self) } # [doc = "Bits 8:10 - Set the communication mode and protocol used. (Not defined settings uses the default setting: 0)"] # [inline (always)] # [must_use] pub fn ctl0_mode (& mut self) -> CTL0_MODE_W < CTL0_SPEC , 8 > { CTL0_MODE_W :: new (self) } # [doc = "Bit 12 - Request to Send If RTSEN is set the RTS output signals is controlled by the hardware logic using the FIFO fill level or TXDATA buffer. If RTSEN is cleared the RTS output is controlled by the RTS bit. The bit is the complement of the UART request to send, RTS modem status output."] # [inline (always)] # [must_use] pub fn ctl0_rts (& mut self) -> CTL0_RTS_W < CTL0_SPEC , 12 > { CTL0_RTS_W :: new (self) } # [doc = "Bit 13 - Enable hardware controlled Request to Send"] # [inline (always)] # [must_use] pub fn ctl0_rtsen (& mut self) -> CTL0_RTSEN_W < CTL0_SPEC , 13 > { CTL0_RTSEN_W :: new (self) } # [doc = "Bit 14 - Enable Clear To Send"] # [inline (always)] # [must_use] pub fn ctl0_ctsen (& mut self) -> CTL0_CTSEN_W < CTL0_SPEC , 14 > { CTL0_CTSEN_W :: new (self) } # [doc = "Bits 15:16 - High-Speed Bit Oversampling Enable #b#NOTE:#/b# The bit oversampling influences the UART baud-rate configuration (see and ). The state of this bit has no effect on clock generation in ISO7816 smart card mode (the SMART bit is set)."] # [inline (always)] # [must_use] pub fn ctl0_hse (& mut self) -> CTL0_HSE_W < CTL0_SPEC , 15 > { CTL0_HSE_W :: new (self) } # [doc = "Bit 17 - UART Enable FIFOs"] # [inline (always)] # [must_use] pub fn ctl0_fen (& mut self) -> CTL0_FEN_W < CTL0_SPEC , 17 > { CTL0_FEN_W :: new (self) } # [doc = "Bit 18 - When enabled with oversmapling of 16, samples samples 7, 8, and 9 are majority voted to decide the sampled bit value. The value correspond to al least 2 of the 3 samples is considered to be the received value. In case the 3 values do not match, RIS.NERR bit is set along with RDR.NERR When enabled with oversmapling of 8, samples samples 3, 4, and 5 are majority voted to decide the sampled bit value. The value correspond to al least 2 of the 3 samples is considered to be the received value. In case the 3 values donot match, RIS.NERR bit is set along with RDR.NERR When disabled, only a single sample of received bit is taken."] # [inline (always)] # [must_use] pub fn ctl0_majvote (& mut self) -> CTL0_MAJVOTE_W < CTL0_SPEC , 18 > { CTL0_MAJVOTE_W :: new (self) } # [doc = "Bit 19 - Most Significant Bit First This bit has effect both on the way protocol byte is transmitted and received. Notes: User needs to match the protocol to the correct value of this bit to send MSb or LSb first. The hardware engine will send the byte entirely based on this bit."] # [inline (always)] # [must_use] pub fn ctl0_msbfirst (& mut self) -> CTL0_MSBFIRST_W < CTL0_SPEC , 19 > { CTL0_MSBFIRST_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "UART Control Register 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctl0::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctl0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CTL0_SPEC ; impl crate :: RegisterSpec for CTL0_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`ctl0::R`](R) reader structure"] impl crate :: Readable for CTL0_SPEC { } # [doc = "`write(|w| ..)` method takes [`ctl0::W`](W) writer structure"] impl crate :: Writable for CTL0_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets CTL0 to value 0x38"] impl crate :: Resettable for CTL0_SPEC { const RESET_VALUE : Self :: Ux = 0x38 ; }
[INFO] [stdout]   |                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                               +++
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing
[INFO] [stdout]  --> src/uart0/int_event0_imask.rs:1:42640
[INFO] [stdout]   |
[INFO] [stdout] 1 | ...mask_linovf (& mut self) -> INT_EVENT0_IMASK_LINOVF_W < INT_EVENT0_IMASK_SPEC , 9 > { INT_EVENT0_IMASK_LINOVF_W :: new (self) } # ...
[INFO] [stdout]   |                 ^^^^^^^^^^     ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here
[INFO] [stdout]   |                 |
[INFO] [stdout]   |                 the lifetime is elided here
[INFO] [stdout]   |
[INFO] [stdout]   = help: the same lifetime is referred to in inconsistent ways, making the signature confusing
[INFO] [stdout] help: use `'_` for type paths
[INFO] [stdout]   |
[INFO] [stdout] 1 | # [doc = "Register `INT_EVENT0_IMASK` reader"] pub type R = crate :: R < INT_EVENT0_IMASK_SPEC > ; # [doc = "Register `INT_EVENT0_IMASK` writer"] pub type W = crate :: W < INT_EVENT0_IMASK_SPEC > ; # [doc = "Field `INT_EVENT0_IMASK_RTOUT` reader - Enable UARTOUT Receive Time-Out Interrupt."] pub type INT_EVENT0_IMASK_RTOUT_R = crate :: BitReader < INT_EVENT0_IMASK_RTOUT_A > ; # [doc = "Enable UARTOUT Receive Time-Out Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_RTOUT_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_RTOUT_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_RTOUT_SET = 1 , } impl From < INT_EVENT0_IMASK_RTOUT_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_RTOUT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_RTOUT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_RTOUT_A { match self . bits { false => INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_CLR , true => INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_rtout_clr (& self) -> bool { * self == INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_rtout_set (& self) -> bool { * self == INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_SET } } # [doc = "Field `INT_EVENT0_IMASK_RTOUT` writer - Enable UARTOUT Receive Time-Out Interrupt."] pub type INT_EVENT0_IMASK_RTOUT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_RTOUT_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_RTOUT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_rtout_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_rtout_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_SET) } } # [doc = "Field `INT_EVENT0_IMASK_FRMERR` reader - Enable UART Framing Error Interrupt."] pub type INT_EVENT0_IMASK_FRMERR_R = crate :: BitReader < INT_EVENT0_IMASK_FRMERR_A > ; # [doc = "Enable UART Framing Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_FRMERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_FRMERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_FRMERR_SET = 1 , } impl From < INT_EVENT0_IMASK_FRMERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_FRMERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_FRMERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_FRMERR_A { match self . bits { false => INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_CLR , true => INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_frmerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_frmerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_FRMERR` writer - Enable UART Framing Error Interrupt."] pub type INT_EVENT0_IMASK_FRMERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_FRMERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_FRMERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_frmerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_frmerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_SET) } } # [doc = "Field `INT_EVENT0_IMASK_PARERR` reader - Enable UART Parity Error Interrupt."] pub type INT_EVENT0_IMASK_PARERR_R = crate :: BitReader < INT_EVENT0_IMASK_PARERR_A > ; # [doc = "Enable UART Parity Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_PARERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_PARERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_PARERR_SET = 1 , } impl From < INT_EVENT0_IMASK_PARERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_PARERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_PARERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_PARERR_A { match self . bits { false => INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_CLR , true => INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_parerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_parerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_PARERR` writer - Enable UART Parity Error Interrupt."] pub type INT_EVENT0_IMASK_PARERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_PARERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_PARERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_parerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_parerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_SET) } } # [doc = "Field `INT_EVENT0_IMASK_BRKERR` reader - Enable UART Break Error Interrupt."] pub type INT_EVENT0_IMASK_BRKERR_R = crate :: BitReader < INT_EVENT0_IMASK_BRKERR_A > ; # [doc = "Enable UART Break Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_BRKERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_BRKERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_BRKERR_SET = 1 , } impl From < INT_EVENT0_IMASK_BRKERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_BRKERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_BRKERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_BRKERR_A { match self . bits { false => INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_CLR , true => INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_brkerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_brkerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_BRKERR` writer - Enable UART Break Error Interrupt."] pub type INT_EVENT0_IMASK_BRKERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_BRKERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_BRKERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_brkerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_brkerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_SET) } } # [doc = "Field `INT_EVENT0_IMASK_OVRERR` reader - Enable UART Receive Overrun Error Interrupt."] pub type INT_EVENT0_IMASK_OVRERR_R = crate :: BitReader < INT_EVENT0_IMASK_OVRERR_A > ; # [doc = "Enable UART Receive Overrun Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_OVRERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_OVRERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_OVRERR_SET = 1 , } impl From < INT_EVENT0_IMASK_OVRERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_OVRERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_OVRERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_OVRERR_A { match self . bits { false => INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_CLR , true => INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_ovrerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_ovrerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_OVRERR` writer - Enable UART Receive Overrun Error Interrupt."] pub type INT_EVENT0_IMASK_OVRERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_OVRERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_OVRERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_ovrerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_ovrerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_SET) } } # [doc = "Field `INT_EVENT0_IMASK_RXNE` reader - Enable Negative Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_IMASK_RXNE_R = crate :: BitReader < INT_EVENT0_IMASK_RXNE_A > ; # [doc = "Enable Negative Edge on UARTxRXD Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_RXNE_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_RXNE_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_RXNE_SET = 1 , } impl From < INT_EVENT0_IMASK_RXNE_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_RXNE_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_RXNE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_RXNE_A { match self . bits { false => INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_CLR , true => INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_rxne_clr (& self) -> bool { * self == INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_rxne_set (& self) -> bool { * self == INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_SET } } # [doc = "Field `INT_EVENT0_IMASK_RXNE` writer - Enable Negative Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_IMASK_RXNE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_RXNE_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_RXNE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_rxne_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_rxne_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_SET) } } # [doc = "Field `INT_EVENT0_IMASK_RXPE` reader - Enable Positive Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_IMASK_RXPE_R = crate :: BitReader < INT_EVENT0_IMASK_RXPE_A > ; # [doc = "Enable Positive Edge on UARTxRXD Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_RXPE_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_RXPE_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_RXPE_SET = 1 , } impl From < INT_EVENT0_IMASK_RXPE_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_RXPE_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_RXPE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_RXPE_A { match self . bits { false => INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_CLR , true => INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_rxpe_clr (& self) -> bool { * self == INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_rxpe_set (& self) -> bool { * self == INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_SET } } # [doc = "Field `INT_EVENT0_IMASK_RXPE` writer - Enable Positive Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_IMASK_RXPE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_RXPE_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_RXPE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_rxpe_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_rxpe_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_SET) } } # [doc = "Field `INT_EVENT0_IMASK_LINC0` reader - Enable LIN Capture 0 / Match Interrupt ."] pub type INT_EVENT0_IMASK_LINC0_R = crate :: BitReader < INT_EVENT0_IMASK_LINC0_A > ; # [doc = "Enable LIN Capture 0 / Match Interrupt .\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_LINC0_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_LINC0_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_LINC0_SET = 1 , } impl From < INT_EVENT0_IMASK_LINC0_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_LINC0_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_LINC0_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_LINC0_A { match self . bits { false => INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_CLR , true => INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_linc0_clr (& self) -> bool { * self == INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_linc0_set (& self) -> bool { * self == INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_SET } } # [doc = "Field `INT_EVENT0_IMASK_LINC0` writer - Enable LIN Capture 0 / Match Interrupt ."] pub type INT_EVENT0_IMASK_LINC0_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_LINC0_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_LINC0_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_linc0_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_linc0_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_SET) } } # [doc = "Field `INT_EVENT0_IMASK_LINC1` reader - Enable LIN Capture 1 Interrupt."] pub type INT_EVENT0_IMASK_LINC1_R = crate :: BitReader < INT_EVENT0_IMASK_LINC1_A > ; # [doc = "Enable LIN Capture 1 Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_LINC1_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_LINC1_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_LINC1_SET = 1 , } impl From < INT_EVENT0_IMASK_LINC1_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_LINC1_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_LINC1_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_LINC1_A { match self . bits { false => INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_CLR , true => INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_linc1_clr (& self) -> bool { * self == INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_linc1_set (& self) -> bool { * self == INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_SET } } # [doc = "Field `INT_EVENT0_IMASK_LINC1` writer - Enable LIN Capture 1 Interrupt."] pub type INT_EVENT0_IMASK_LINC1_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_LINC1_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_LINC1_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_linc1_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_linc1_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_SET) } } # [doc = "Field `INT_EVENT0_IMASK_LINOVF` reader - Enable LIN Hardware Counter Overflow Interrupt."] pub type INT_EVENT0_IMASK_LINOVF_R = crate :: BitReader < INT_EVENT0_IMASK_LINOVF_A > ; # [doc = "Enable LIN Hardware Counter Overflow Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_LINOVF_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_LINOVF_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_LINOVF_SET = 1 , } impl From < INT_EVENT0_IMASK_LINOVF_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_LINOVF_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_LINOVF_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_LINOVF_A { match self . bits { false => INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_CLR , true => INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_linovf_clr (& self) -> bool { * self == INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_linovf_set (& self) -> bool { * self == INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_SET } } # [doc = "Field `INT_EVENT0_IMASK_LINOVF` writer - Enable LIN Hardware Counter Overflow Interrupt."] pub type INT_EVENT0_IMASK_LINOVF_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_LINOVF_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_LINOVF_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_linovf_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_linovf_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_SET) } } # [doc = "Field `INT_EVENT0_IMASK_RXINT` reader - Enable UART Receive Interrupt."] pub type INT_EVENT0_IMASK_RXINT_R = crate :: BitReader < INT_EVENT0_IMASK_RXINT_A > ; # [doc = "Enable UART Receive Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_RXINT_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_RXINT_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_RXINT_SET = 1 , } impl From < INT_EVENT0_IMASK_RXINT_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_RXINT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_RXINT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_RXINT_A { match self . bits { false => INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_CLR , true => INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_rxint_clr (& self) -> bool { * self == INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_rxint_set (& self) -> bool { * self == INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_SET } } # [doc = "Field `INT_EVENT0_IMASK_RXINT` writer - Enable UART Receive Interrupt."] pub type INT_EVENT0_IMASK_RXINT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_RXINT_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_RXINT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_rxint_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_rxint_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_SET) } } # [doc = "Field `INT_EVENT0_IMASK_TXINT` reader - Enable UART Transmit Interrupt."] pub type INT_EVENT0_IMASK_TXINT_R = crate :: BitReader < INT_EVENT0_IMASK_TXINT_A > ; # [doc = "Enable UART Transmit Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_TXINT_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_TXINT_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_TXINT_SET = 1 , } impl From < INT_EVENT0_IMASK_TXINT_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_TXINT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_TXINT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_TXINT_A { match self . bits { false => INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_CLR , true => INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_txint_clr (& self) -> bool { * self == INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_txint_set (& self) -> bool { * self == INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_SET } } # [doc = "Field `INT_EVENT0_IMASK_TXINT` writer - Enable UART Transmit Interrupt."] pub type INT_EVENT0_IMASK_TXINT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_TXINT_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_TXINT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_txint_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_txint_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_SET) } } # [doc = "Field `INT_EVENT0_IMASK_EOT` reader - Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] pub type INT_EVENT0_IMASK_EOT_R = crate :: BitReader < INT_EVENT0_IMASK_EOT_A > ; # [doc = "Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_EOT_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_EOT_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_EOT_SET = 1 , } impl From < INT_EVENT0_IMASK_EOT_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_EOT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_EOT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_EOT_A { match self . bits { false => INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_CLR , true => INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_eot_clr (& self) -> bool { * self == INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_eot_set (& self) -> bool { * self == INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_SET } } # [doc = "Field `INT_EVENT0_IMASK_EOT` writer - Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] pub type INT_EVENT0_IMASK_EOT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_EOT_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_EOT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_eot_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_eot_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_SET) } } # [doc = "Field `INT_EVENT0_IMASK_ADDR_MATCH` reader - Enable Address Match Interrupt."] pub type INT_EVENT0_IMASK_ADDR_MATCH_R = crate :: BitReader < INT_EVENT0_IMASK_ADDR_MATCH_A > ; # [doc = "Enable Address Match Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_ADDR_MATCH_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_ADDR_MATCH_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_ADDR_MATCH_SET = 1 , } impl From < INT_EVENT0_IMASK_ADDR_MATCH_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_ADDR_MATCH_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_ADDR_MATCH_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_ADDR_MATCH_A { match self . bits { false => INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_CLR , true => INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_addr_match_clr (& self) -> bool { * self == INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_addr_match_set (& self) -> bool { * self == INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_SET } } # [doc = "Field `INT_EVENT0_IMASK_ADDR_MATCH` writer - Enable Address Match Interrupt."] pub type INT_EVENT0_IMASK_ADDR_MATCH_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_ADDR_MATCH_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_ADDR_MATCH_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_addr_match_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_addr_match_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_SET) } } # [doc = "Field `INT_EVENT0_IMASK_CTS` reader - Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] pub type INT_EVENT0_IMASK_CTS_R = crate :: BitReader < INT_EVENT0_IMASK_CTS_A > ; # [doc = "Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_CTS_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_CTS_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_CTS_SET = 1 , } impl From < INT_EVENT0_IMASK_CTS_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_CTS_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_CTS_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_CTS_A { match self . bits { false => INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_CLR , true => INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_cts_clr (& self) -> bool { * self == INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_cts_set (& self) -> bool { * self == INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_SET } } # [doc = "Field `INT_EVENT0_IMASK_CTS` writer - Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] pub type INT_EVENT0_IMASK_CTS_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_CTS_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_CTS_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_cts_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_cts_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DMA_DONE_RX` reader - Enable DMA Done on RX Event Channel"] pub type INT_EVENT0_IMASK_DMA_DONE_RX_R = crate :: BitReader < INT_EVENT0_IMASK_DMA_DONE_RX_A > ; # [doc = "Enable DMA Done on RX Event Channel\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DMA_DONE_RX_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DMA_DONE_RX_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DMA_DONE_RX_SET = 1 , } impl From < INT_EVENT0_IMASK_DMA_DONE_RX_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DMA_DONE_RX_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DMA_DONE_RX_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DMA_DONE_RX_A { match self . bits { false => INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_CLR , true => INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dma_done_rx_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dma_done_rx_set (& self) -> bool { * self == INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_SET } } # [doc = "Field `INT_EVENT0_IMASK_DMA_DONE_RX` writer - Enable DMA Done on RX Event Channel"] pub type INT_EVENT0_IMASK_DMA_DONE_RX_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DMA_DONE_RX_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DMA_DONE_RX_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dma_done_rx_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dma_done_rx_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DMA_DONE_TX` reader - Enable DMA Done on TX Event Channel"] pub type INT_EVENT0_IMASK_DMA_DONE_TX_R = crate :: BitReader < INT_EVENT0_IMASK_DMA_DONE_TX_A > ; # [doc = "Enable DMA Done on TX Event Channel\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DMA_DONE_TX_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DMA_DONE_TX_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DMA_DONE_TX_SET = 1 , } impl From < INT_EVENT0_IMASK_DMA_DONE_TX_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DMA_DONE_TX_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DMA_DONE_TX_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DMA_DONE_TX_A { match self . bits { false => INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_CLR , true => INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dma_done_tx_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dma_done_tx_set (& self) -> bool { * self == INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_SET } } # [doc = "Field `INT_EVENT0_IMASK_DMA_DONE_TX` writer - Enable DMA Done on TX Event Channel"] pub type INT_EVENT0_IMASK_DMA_DONE_TX_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DMA_DONE_TX_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DMA_DONE_TX_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dma_done_tx_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dma_done_tx_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_SET) } } # [doc = "Field `INT_EVENT0_IMASK_NERR` reader - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] pub type INT_EVENT0_IMASK_NERR_R = crate :: BitReader < INT_EVENT0_IMASK_NERR_A > ; # [doc = "Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_NERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_NERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_NERR_SET = 1 , } impl From < INT_EVENT0_IMASK_NERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_NERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_NERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_NERR_A { match self . bits { false => INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_CLR , true => INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_nerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_nerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_NERR` writer - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] pub type INT_EVENT0_IMASK_NERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_NERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_NERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_nerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_nerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_SET) } } impl R { # [doc = "Bit 0 - Enable UARTOUT Receive Time-Out Interrupt."] # [inline (always)] pub fn int_event0_imask_rtout (& self) -> INT_EVENT0_IMASK_RTOUT_R { INT_EVENT0_IMASK_RTOUT_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - Enable UART Framing Error Interrupt."] # [inline (always)] pub fn int_event0_imask_frmerr (& self) -> INT_EVENT0_IMASK_FRMERR_R { INT_EVENT0_IMASK_FRMERR_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - Enable UART Parity Error Interrupt."] # [inline (always)] pub fn int_event0_imask_parerr (& self) -> INT_EVENT0_IMASK_PARERR_R { INT_EVENT0_IMASK_PARERR_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - Enable UART Break Error Interrupt."] # [inline (always)] pub fn int_event0_imask_brkerr (& self) -> INT_EVENT0_IMASK_BRKERR_R { INT_EVENT0_IMASK_BRKERR_R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - Enable UART Receive Overrun Error Interrupt."] # [inline (always)] pub fn int_event0_imask_ovrerr (& self) -> INT_EVENT0_IMASK_OVRERR_R { INT_EVENT0_IMASK_OVRERR_R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - Enable Negative Edge on UARTxRXD Interrupt."] # [inline (always)] pub fn int_event0_imask_rxne (& self) -> INT_EVENT0_IMASK_RXNE_R { INT_EVENT0_IMASK_RXNE_R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - Enable Positive Edge on UARTxRXD Interrupt."] # [inline (always)] pub fn int_event0_imask_rxpe (& self) -> INT_EVENT0_IMASK_RXPE_R { INT_EVENT0_IMASK_RXPE_R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - Enable LIN Capture 0 / Match Interrupt ."] # [inline (always)] pub fn int_event0_imask_linc0 (& self) -> INT_EVENT0_IMASK_LINC0_R { INT_EVENT0_IMASK_LINC0_R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - Enable LIN Capture 1 Interrupt."] # [inline (always)] pub fn int_event0_imask_linc1 (& self) -> INT_EVENT0_IMASK_LINC1_R { INT_EVENT0_IMASK_LINC1_R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - Enable LIN Hardware Counter Overflow Interrupt."] # [inline (always)] pub fn int_event0_imask_linovf (& self) -> INT_EVENT0_IMASK_LINOVF_R { INT_EVENT0_IMASK_LINOVF_R :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - Enable UART Receive Interrupt."] # [inline (always)] pub fn int_event0_imask_rxint (& self) -> INT_EVENT0_IMASK_RXINT_R { INT_EVENT0_IMASK_RXINT_R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - Enable UART Transmit Interrupt."] # [inline (always)] pub fn int_event0_imask_txint (& self) -> INT_EVENT0_IMASK_TXINT_R { INT_EVENT0_IMASK_TXINT_R :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] # [inline (always)] pub fn int_event0_imask_eot (& self) -> INT_EVENT0_IMASK_EOT_R { INT_EVENT0_IMASK_EOT_R :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - Enable Address Match Interrupt."] # [inline (always)] pub fn int_event0_imask_addr_match (& self) -> INT_EVENT0_IMASK_ADDR_MATCH_R { INT_EVENT0_IMASK_ADDR_MATCH_R :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 14 - Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] # [inline (always)] pub fn int_event0_imask_cts (& self) -> INT_EVENT0_IMASK_CTS_R { INT_EVENT0_IMASK_CTS_R :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - Enable DMA Done on RX Event Channel"] # [inline (always)] pub fn int_event0_imask_dma_done_rx (& self) -> INT_EVENT0_IMASK_DMA_DONE_RX_R { INT_EVENT0_IMASK_DMA_DONE_RX_R :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bit 16 - Enable DMA Done on TX Event Channel"] # [inline (always)] pub fn int_event0_imask_dma_done_tx (& self) -> INT_EVENT0_IMASK_DMA_DONE_TX_R { INT_EVENT0_IMASK_DMA_DONE_TX_R :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] # [inline (always)] pub fn int_event0_imask_nerr (& self) -> INT_EVENT0_IMASK_NERR_R { INT_EVENT0_IMASK_NERR_R :: new (((self . bits >> 17) & 1) != 0) } } impl W { # [doc = "Bit 0 - Enable UARTOUT Receive Time-Out Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_rtout (& mut self) -> INT_EVENT0_IMASK_RTOUT_W < INT_EVENT0_IMASK_SPEC , 0 > { INT_EVENT0_IMASK_RTOUT_W :: new (self) } # [doc = "Bit 1 - Enable UART Framing Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_frmerr (& mut self) -> INT_EVENT0_IMASK_FRMERR_W < INT_EVENT0_IMASK_SPEC , 1 > { INT_EVENT0_IMASK_FRMERR_W :: new (self) } # [doc = "Bit 2 - Enable UART Parity Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_parerr (& mut self) -> INT_EVENT0_IMASK_PARERR_W < INT_EVENT0_IMASK_SPEC , 2 > { INT_EVENT0_IMASK_PARERR_W :: new (self) } # [doc = "Bit 3 - Enable UART Break Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_brkerr (& mut self) -> INT_EVENT0_IMASK_BRKERR_W < INT_EVENT0_IMASK_SPEC , 3 > { INT_EVENT0_IMASK_BRKERR_W :: new (self) } # [doc = "Bit 4 - Enable UART Receive Overrun Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_ovrerr (& mut self) -> INT_EVENT0_IMASK_OVRERR_W < INT_EVENT0_IMASK_SPEC , 4 > { INT_EVENT0_IMASK_OVRERR_W :: new (self) } # [doc = "Bit 5 - Enable Negative Edge on UARTxRXD Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_rxne (& mut self) -> INT_EVENT0_IMASK_RXNE_W < INT_EVENT0_IMASK_SPEC , 5 > { INT_EVENT0_IMASK_RXNE_W :: new (self) } # [doc = "Bit 6 - Enable Positive Edge on UARTxRXD Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_rxpe (& mut self) -> INT_EVENT0_IMASK_RXPE_W < INT_EVENT0_IMASK_SPEC , 6 > { INT_EVENT0_IMASK_RXPE_W :: new (self) } # [doc = "Bit 7 - Enable LIN Capture 0 / Match Interrupt ."] # [inline (always)] # [must_use] pub fn int_event0_imask_linc0 (& mut self) -> INT_EVENT0_IMASK_LINC0_W < INT_EVENT0_IMASK_SPEC , 7 > { INT_EVENT0_IMASK_LINC0_W :: new (self) } # [doc = "Bit 8 - Enable LIN Capture 1 Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_linc1 (& mut self) -> INT_EVENT0_IMASK_LINC1_W < INT_EVENT0_IMASK_SPEC , 8 > { INT_EVENT0_IMASK_LINC1_W :: new (self) } # [doc = "Bit 9 - Enable LIN Hardware Counter Overflow Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_linovf (& mut self) -> INT_EVENT0_IMASK_LINOVF_W <'_,  INT_EVENT0_IMASK_SPEC , 9 > { INT_EVENT0_IMASK_LINOVF_W :: new (self) } # [doc = "Bit 10 - Enable UART Receive Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_rxint (& mut self) -> INT_EVENT0_IMASK_RXINT_W < INT_EVENT0_IMASK_SPEC , 10 > { INT_EVENT0_IMASK_RXINT_W :: new (self) } # [doc = "Bit 11 - Enable UART Transmit Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_txint (& mut self) -> INT_EVENT0_IMASK_TXINT_W < INT_EVENT0_IMASK_SPEC , 11 > { INT_EVENT0_IMASK_TXINT_W :: new (self) } # [doc = "Bit 12 - Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] # [inline (always)] # [must_use] pub fn int_event0_imask_eot (& mut self) -> INT_EVENT0_IMASK_EOT_W < INT_EVENT0_IMASK_SPEC , 12 > { INT_EVENT0_IMASK_EOT_W :: new (self) } # [doc = "Bit 13 - Enable Address Match Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_addr_match (& mut self) -> INT_EVENT0_IMASK_ADDR_MATCH_W < INT_EVENT0_IMASK_SPEC , 13 > { INT_EVENT0_IMASK_ADDR_MATCH_W :: new (self) } # [doc = "Bit 14 - Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] # [inline (always)] # [must_use] pub fn int_event0_imask_cts (& mut self) -> INT_EVENT0_IMASK_CTS_W < INT_EVENT0_IMASK_SPEC , 14 > { INT_EVENT0_IMASK_CTS_W :: new (self) } # [doc = "Bit 15 - Enable DMA Done on RX Event Channel"] # [inline (always)] # [must_use] pub fn int_event0_imask_dma_done_rx (& mut self) -> INT_EVENT0_IMASK_DMA_DONE_RX_W < INT_EVENT0_IMASK_SPEC , 15 > { INT_EVENT0_IMASK_DMA_DONE_RX_W :: new (self) } # [doc = "Bit 16 - Enable DMA Done on TX Event Channel"] # [inline (always)] # [must_use] pub fn int_event0_imask_dma_done_tx (& mut self) -> INT_EVENT0_IMASK_DMA_DONE_TX_W < INT_EVENT0_IMASK_SPEC , 16 > { INT_EVENT0_IMASK_DMA_DONE_TX_W :: new (self) } # [doc = "Bit 17 - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] # [inline (always)] # [must_use] pub fn int_event0_imask_nerr (& mut self) -> INT_EVENT0_IMASK_NERR_W < INT_EVENT0_IMASK_SPEC , 17 > { INT_EVENT0_IMASK_NERR_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Interrupt mask\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_event0_imask::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_event0_imask::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct INT_EVENT0_IMASK_SPEC ; impl crate :: RegisterSpec for INT_EVENT0_IMASK_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`int_event0_imask::R`](R) reader structure"] impl crate :: Readable for INT_EVENT0_IMASK_SPEC { } # [doc = "`write(|w| ..)` method takes [`int_event0_imask::W`](W) writer structure"] impl crate :: Writable for INT_EVENT0_IMASK_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets INT_EVENT0_IMASK to value 0"] impl crate :: Resettable for INT_EVENT0_IMASK_SPEC { const RESET_VALUE : Self :: Ux = 0 ; }
[INFO] [stdout]   |                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                          +++
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing
[INFO] [stdout]  --> src/uart0/ctl0.rs:1:39165
[INFO] [stdout]   |
[INFO] [stdout] 1 | ...must_use] pub fn ctl0_rxe (& mut self) -> CTL0_RXE_W < CTL0_SPEC , 3 > { CTL0_RXE_W :: new (self) } # [doc = "Bit 4 - UART Transmi...
[INFO] [stdout]   |                               ^^^^^^^^^^     ^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here
[INFO] [stdout]   |                               |
[INFO] [stdout]   |                               the lifetime is elided here
[INFO] [stdout]   |
[INFO] [stdout]   = help: the same lifetime is referred to in inconsistent ways, making the signature confusing
[INFO] [stdout] help: use `'_` for type paths
[INFO] [stdout]   |
[INFO] [stdout] 1 | # [doc = "Register `CTL0` reader"] pub type R = crate :: R < CTL0_SPEC > ; # [doc = "Register `CTL0` writer"] pub type W = crate :: W < CTL0_SPEC > ; # [doc = "Field `CTL0_ENABLE` reader - UART Module Enable. If the UART is disabled in the middle of transmission or reception, it completes the current character before stopping. If the ENABLE bit is not set, all registers can still be accessed and updated. It is recommended to setup and change the UART operation mode with having the ENABLE bit cleared to avoid unpredictable behavior during the setup or update. If disabled the UART module will not send or receive any data and the logic is held in reset state."] pub type CTL0_ENABLE_R = crate :: BitReader < CTL0_ENABLE_A > ; # [doc = "UART Module Enable. If the UART is disabled in the middle of transmission or reception, it completes the current character before stopping. If the ENABLE bit is not set, all registers can still be accessed and updated. It is recommended to setup and change the UART operation mode with having the ENABLE bit cleared to avoid unpredictable behavior during the setup or update. If disabled the UART module will not send or receive any data and the logic is held in reset state.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CTL0_ENABLE_A { # [doc = "0: DISABLE"] CTL0_ENABLE_DISABLE = 0 , # [doc = "1: ENABLE"] CTL0_ENABLE_ENABLE = 1 , } impl From < CTL0_ENABLE_A > for bool { # [inline (always)] fn from (variant : CTL0_ENABLE_A) -> Self { variant as u8 != 0 } } impl CTL0_ENABLE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CTL0_ENABLE_A { match self . bits { false => CTL0_ENABLE_A :: CTL0_ENABLE_DISABLE , true => CTL0_ENABLE_A :: CTL0_ENABLE_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_ctl0_enable_disable (& self) -> bool { * self == CTL0_ENABLE_A :: CTL0_ENABLE_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_ctl0_enable_enable (& self) -> bool { * self == CTL0_ENABLE_A :: CTL0_ENABLE_ENABLE } } # [doc = "Field `CTL0_ENABLE` writer - UART Module Enable. If the UART is disabled in the middle of transmission or reception, it completes the current character before stopping. If the ENABLE bit is not set, all registers can still be accessed and updated. It is recommended to setup and change the UART operation mode with having the ENABLE bit cleared to avoid unpredictable behavior during the setup or update. If disabled the UART module will not send or receive any data and the logic is held in reset state."] pub type CTL0_ENABLE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL0_ENABLE_A > ; impl < 'a , REG , const O : u8 > CTL0_ENABLE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn ctl0_enable_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_ENABLE_A :: CTL0_ENABLE_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn ctl0_enable_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_ENABLE_A :: CTL0_ENABLE_ENABLE) } } # [doc = "Field `CTL0_LBE` reader - UART Loop Back Enable"] pub type CTL0_LBE_R = crate :: BitReader < CTL0_LBE_A > ; # [doc = "UART Loop Back Enable\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CTL0_LBE_A { # [doc = "0: DISABLE"] CTL0_LBE_DISABLE = 0 , # [doc = "1: ENABLE"] CTL0_LBE_ENABLE = 1 , } impl From < CTL0_LBE_A > for bool { # [inline (always)] fn from (variant : CTL0_LBE_A) -> Self { variant as u8 != 0 } } impl CTL0_LBE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CTL0_LBE_A { match self . bits { false => CTL0_LBE_A :: CTL0_LBE_DISABLE , true => CTL0_LBE_A :: CTL0_LBE_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_ctl0_lbe_disable (& self) -> bool { * self == CTL0_LBE_A :: CTL0_LBE_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_ctl0_lbe_enable (& self) -> bool { * self == CTL0_LBE_A :: CTL0_LBE_ENABLE } } # [doc = "Field `CTL0_LBE` writer - UART Loop Back Enable"] pub type CTL0_LBE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL0_LBE_A > ; impl < 'a , REG , const O : u8 > CTL0_LBE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn ctl0_lbe_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_LBE_A :: CTL0_LBE_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn ctl0_lbe_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_LBE_A :: CTL0_LBE_ENABLE) } } # [doc = "Field `CTL0_RXE` reader - UART Receive Enable If the UART is disabled in the middle of a receive, it completes the current character before stopping. #b#NOTE:#/b# To enable reception, the UARTEN bit must be set."] pub type CTL0_RXE_R = crate :: BitReader < CTL0_RXE_A > ; # [doc = "UART Receive Enable If the UART is disabled in the middle of a receive, it completes the current character before stopping. #b#NOTE:#/b# To enable reception, the UARTEN bit must be set.\n\nValue on reset: 1"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CTL0_RXE_A { # [doc = "0: DISABLE"] CTL0_RXE_DISABLE = 0 , # [doc = "1: ENABLE"] CTL0_RXE_ENABLE = 1 , } impl From < CTL0_RXE_A > for bool { # [inline (always)] fn from (variant : CTL0_RXE_A) -> Self { variant as u8 != 0 } } impl CTL0_RXE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CTL0_RXE_A { match self . bits { false => CTL0_RXE_A :: CTL0_RXE_DISABLE , true => CTL0_RXE_A :: CTL0_RXE_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_ctl0_rxe_disable (& self) -> bool { * self == CTL0_RXE_A :: CTL0_RXE_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_ctl0_rxe_enable (& self) -> bool { * self == CTL0_RXE_A :: CTL0_RXE_ENABLE } } # [doc = "Field `CTL0_RXE` writer - UART Receive Enable If the UART is disabled in the middle of a receive, it completes the current character before stopping. #b#NOTE:#/b# To enable reception, the UARTEN bit must be set."] pub type CTL0_RXE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL0_RXE_A > ; impl < 'a , REG , const O : u8 > CTL0_RXE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn ctl0_rxe_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_RXE_A :: CTL0_RXE_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn ctl0_rxe_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_RXE_A :: CTL0_RXE_ENABLE) } } # [doc = "Field `CTL0_TXE` reader - UART Transmit Enable If the UART is disabled in the middle of a transmission, it completes the current character before stopping. #b#NOTE:#/b# To enable transmission, the UARTEN bit must be set."] pub type CTL0_TXE_R = crate :: BitReader < CTL0_TXE_A > ; # [doc = "UART Transmit Enable If the UART is disabled in the middle of a transmission, it completes the current character before stopping. #b#NOTE:#/b# To enable transmission, the UARTEN bit must be set.\n\nValue on reset: 1"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CTL0_TXE_A { # [doc = "0: DISABLE"] CTL0_TXE_DISABLE = 0 , # [doc = "1: ENABLE"] CTL0_TXE_ENABLE = 1 , } impl From < CTL0_TXE_A > for bool { # [inline (always)] fn from (variant : CTL0_TXE_A) -> Self { variant as u8 != 0 } } impl CTL0_TXE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CTL0_TXE_A { match self . bits { false => CTL0_TXE_A :: CTL0_TXE_DISABLE , true => CTL0_TXE_A :: CTL0_TXE_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_ctl0_txe_disable (& self) -> bool { * self == CTL0_TXE_A :: CTL0_TXE_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_ctl0_txe_enable (& self) -> bool { * self == CTL0_TXE_A :: CTL0_TXE_ENABLE } } # [doc = "Field `CTL0_TXE` writer - UART Transmit Enable If the UART is disabled in the middle of a transmission, it completes the current character before stopping. #b#NOTE:#/b# To enable transmission, the UARTEN bit must be set."] pub type CTL0_TXE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL0_TXE_A > ; impl < 'a , REG , const O : u8 > CTL0_TXE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn ctl0_txe_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_TXE_A :: CTL0_TXE_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn ctl0_txe_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_TXE_A :: CTL0_TXE_ENABLE) } } # [doc = "Field `CTL0_TXD_OUT_EN` reader - TXD Pin Control Enable. When the transmit section of the UART is disabled (TXE = 0), the TXD pin can be controlled by the TXD_OUT bit. 1 = UARTxTXD pin can be controlled by TXD_OUT, if TXE = 0"] pub type CTL0_TXD_OUT_EN_R = crate :: BitReader < CTL0_TXD_OUT_EN_A > ; # [doc = "TXD Pin Control Enable. When the transmit section of the UART is disabled (TXE = 0), the TXD pin can be controlled by the TXD_OUT bit. 1 = UARTxTXD pin can be controlled by TXD_OUT, if TXE = 0\n\nValue on reset: 1"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CTL0_TXD_OUT_EN_A { # [doc = "0: DISABLE"] CTL0_TXD_OUT_EN_DISABLE = 0 , # [doc = "1: ENABLE"] CTL0_TXD_OUT_EN_ENABLE = 1 , } impl From < CTL0_TXD_OUT_EN_A > for bool { # [inline (always)] fn from (variant : CTL0_TXD_OUT_EN_A) -> Self { variant as u8 != 0 } } impl CTL0_TXD_OUT_EN_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CTL0_TXD_OUT_EN_A { match self . bits { false => CTL0_TXD_OUT_EN_A :: CTL0_TXD_OUT_EN_DISABLE , true => CTL0_TXD_OUT_EN_A :: CTL0_TXD_OUT_EN_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_ctl0_txd_out_en_disable (& self) -> bool { * self == CTL0_TXD_OUT_EN_A :: CTL0_TXD_OUT_EN_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_ctl0_txd_out_en_enable (& self) -> bool { * self == CTL0_TXD_OUT_EN_A :: CTL0_TXD_OUT_EN_ENABLE } } # [doc = "Field `CTL0_TXD_OUT_EN` writer - TXD Pin Control Enable. When the transmit section of the UART is disabled (TXE = 0), the TXD pin can be controlled by the TXD_OUT bit. 1 = UARTxTXD pin can be controlled by TXD_OUT, if TXE = 0"] pub type CTL0_TXD_OUT_EN_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL0_TXD_OUT_EN_A > ; impl < 'a , REG , const O : u8 > CTL0_TXD_OUT_EN_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn ctl0_txd_out_en_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_TXD_OUT_EN_A :: CTL0_TXD_OUT_EN_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn ctl0_txd_out_en_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_TXD_OUT_EN_A :: CTL0_TXD_OUT_EN_ENABLE) } } # [doc = "Field `CTL0_TXD_OUT` reader - TXD Pin Control Controls the TXD pin when TXD_OUT_EN = 1 and TXE = 0."] pub type CTL0_TXD_OUT_R = crate :: BitReader < CTL0_TXD_OUT_A > ; # [doc = "TXD Pin Control Controls the TXD pin when TXD_OUT_EN = 1 and TXE = 0.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CTL0_TXD_OUT_A { # [doc = "0: LOW"] CTL0_TXD_OUT_LOW = 0 , # [doc = "1: HIGH"] CTL0_TXD_OUT_HIGH = 1 , } impl From < CTL0_TXD_OUT_A > for bool { # [inline (always)] fn from (variant : CTL0_TXD_OUT_A) -> Self { variant as u8 != 0 } } impl CTL0_TXD_OUT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CTL0_TXD_OUT_A { match self . bits { false => CTL0_TXD_OUT_A :: CTL0_TXD_OUT_LOW , true => CTL0_TXD_OUT_A :: CTL0_TXD_OUT_HIGH , } } # [doc = "LOW"] # [inline (always)] pub fn is_ctl0_txd_out_low (& self) -> bool { * self == CTL0_TXD_OUT_A :: CTL0_TXD_OUT_LOW } # [doc = "HIGH"] # [inline (always)] pub fn is_ctl0_txd_out_high (& self) -> bool { * self == CTL0_TXD_OUT_A :: CTL0_TXD_OUT_HIGH } } # [doc = "Field `CTL0_TXD_OUT` writer - TXD Pin Control Controls the TXD pin when TXD_OUT_EN = 1 and TXE = 0."] pub type CTL0_TXD_OUT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL0_TXD_OUT_A > ; impl < 'a , REG , const O : u8 > CTL0_TXD_OUT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "LOW"] # [inline (always)] pub fn ctl0_txd_out_low (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_TXD_OUT_A :: CTL0_TXD_OUT_LOW) } # [doc = "HIGH"] # [inline (always)] pub fn ctl0_txd_out_high (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_TXD_OUT_A :: CTL0_TXD_OUT_HIGH) } } # [doc = "Field `CTL0_MENC` reader - Manchester Encode enable"] pub type CTL0_MENC_R = crate :: BitReader < CTL0_MENC_A > ; # [doc = "Manchester Encode enable\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CTL0_MENC_A { # [doc = "0: DISABLE"] CTL0_MENC_DISABLE = 0 , # [doc = "1: ENABLE"] CTL0_MENC_ENABLE = 1 , } impl From < CTL0_MENC_A > for bool { # [inline (always)] fn from (variant : CTL0_MENC_A) -> Self { variant as u8 != 0 } } impl CTL0_MENC_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CTL0_MENC_A { match self . bits { false => CTL0_MENC_A :: CTL0_MENC_DISABLE , true => CTL0_MENC_A :: CTL0_MENC_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_ctl0_menc_disable (& self) -> bool { * self == CTL0_MENC_A :: CTL0_MENC_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_ctl0_menc_enable (& self) -> bool { * self == CTL0_MENC_A :: CTL0_MENC_ENABLE } } # [doc = "Field `CTL0_MENC` writer - Manchester Encode enable"] pub type CTL0_MENC_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL0_MENC_A > ; impl < 'a , REG , const O : u8 > CTL0_MENC_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn ctl0_menc_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_MENC_A :: CTL0_MENC_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn ctl0_menc_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_MENC_A :: CTL0_MENC_ENABLE) } } # [doc = "Field `CTL0_MODE` reader - Set the communication mode and protocol used. (Not defined settings uses the default setting: 0)"] pub type CTL0_MODE_R = crate :: FieldReader < CTL0_MODE_A > ; # [doc = "Set the communication mode and protocol used. (Not defined settings uses the default setting: 0)\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum CTL0_MODE_A { # [doc = "0: UART"] CTL0_MODE_UART = 0 , # [doc = "1: RS485"] CTL0_MODE_RS485 = 1 , # [doc = "2: IDLELINE"] CTL0_MODE_IDLELINE = 2 , # [doc = "3: ADDR9BIT"] CTL0_MODE_ADDR9BIT = 3 , # [doc = "4: SMART"] CTL0_MODE_SMART = 4 , # [doc = "5: DALI"] CTL0_MODE_DALI = 5 , } impl From < CTL0_MODE_A > for u8 { # [inline (always)] fn from (variant : CTL0_MODE_A) -> Self { variant as _ } } impl crate :: FieldSpec for CTL0_MODE_A { type Ux = u8 ; } impl CTL0_MODE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < CTL0_MODE_A > { match self . bits { 0 => Some (CTL0_MODE_A :: CTL0_MODE_UART) , 1 => Some (CTL0_MODE_A :: CTL0_MODE_RS485) , 2 => Some (CTL0_MODE_A :: CTL0_MODE_IDLELINE) , 3 => Some (CTL0_MODE_A :: CTL0_MODE_ADDR9BIT) , 4 => Some (CTL0_MODE_A :: CTL0_MODE_SMART) , 5 => Some (CTL0_MODE_A :: CTL0_MODE_DALI) , _ => None , } } # [doc = "UART"] # [inline (always)] pub fn is_ctl0_mode_uart (& self) -> bool { * self == CTL0_MODE_A :: CTL0_MODE_UART } # [doc = "RS485"] # [inline (always)] pub fn is_ctl0_mode_rs485 (& self) -> bool { * self == CTL0_MODE_A :: CTL0_MODE_RS485 } # [doc = "IDLELINE"] # [inline (always)] pub fn is_ctl0_mode_idleline (& self) -> bool { * self == CTL0_MODE_A :: CTL0_MODE_IDLELINE } # [doc = "ADDR9BIT"] # [inline (always)] pub fn is_ctl0_mode_addr9bit (& self) -> bool { * self == CTL0_MODE_A :: CTL0_MODE_ADDR9BIT } # [doc = "SMART"] # [inline (always)] pub fn is_ctl0_mode_smart (& self) -> bool { * self == CTL0_MODE_A :: CTL0_MODE_SMART } # [doc = "DALI"] # [inline (always)] pub fn is_ctl0_mode_dali (& self) -> bool { * self == CTL0_MODE_A :: CTL0_MODE_DALI } } # [doc = "Field `CTL0_MODE` writer - Set the communication mode and protocol used. (Not defined settings uses the default setting: 0)"] pub type CTL0_MODE_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 3 , O , CTL0_MODE_A > ; impl < 'a , REG , const O : u8 > CTL0_MODE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "UART"] # [inline (always)] pub fn ctl0_mode_uart (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_MODE_A :: CTL0_MODE_UART) } # [doc = "RS485"] # [inline (always)] pub fn ctl0_mode_rs485 (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_MODE_A :: CTL0_MODE_RS485) } # [doc = "IDLELINE"] # [inline (always)] pub fn ctl0_mode_idleline (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_MODE_A :: CTL0_MODE_IDLELINE) } # [doc = "ADDR9BIT"] # [inline (always)] pub fn ctl0_mode_addr9bit (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_MODE_A :: CTL0_MODE_ADDR9BIT) } # [doc = "SMART"] # [inline (always)] pub fn ctl0_mode_smart (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_MODE_A :: CTL0_MODE_SMART) } # [doc = "DALI"] # [inline (always)] pub fn ctl0_mode_dali (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_MODE_A :: CTL0_MODE_DALI) } } # [doc = "Field `CTL0_RTS` reader - Request to Send If RTSEN is set the RTS output signals is controlled by the hardware logic using the FIFO fill level or TXDATA buffer. If RTSEN is cleared the RTS output is controlled by the RTS bit. The bit is the complement of the UART request to send, RTS modem status output."] pub type CTL0_RTS_R = crate :: BitReader < CTL0_RTS_A > ; # [doc = "Request to Send If RTSEN is set the RTS output signals is controlled by the hardware logic using the FIFO fill level or TXDATA buffer. If RTSEN is cleared the RTS output is controlled by the RTS bit. The bit is the complement of the UART request to send, RTS modem status output.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CTL0_RTS_A { # [doc = "0: CLR"] CTL0_RTS_CLR = 0 , # [doc = "1: SET"] CTL0_RTS_SET = 1 , } impl From < CTL0_RTS_A > for bool { # [inline (always)] fn from (variant : CTL0_RTS_A) -> Self { variant as u8 != 0 } } impl CTL0_RTS_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CTL0_RTS_A { match self . bits { false => CTL0_RTS_A :: CTL0_RTS_CLR , true => CTL0_RTS_A :: CTL0_RTS_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_ctl0_rts_clr (& self) -> bool { * self == CTL0_RTS_A :: CTL0_RTS_CLR } # [doc = "SET"] # [inline (always)] pub fn is_ctl0_rts_set (& self) -> bool { * self == CTL0_RTS_A :: CTL0_RTS_SET } } # [doc = "Field `CTL0_RTS` writer - Request to Send If RTSEN is set the RTS output signals is controlled by the hardware logic using the FIFO fill level or TXDATA buffer. If RTSEN is cleared the RTS output is controlled by the RTS bit. The bit is the complement of the UART request to send, RTS modem status output."] pub type CTL0_RTS_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL0_RTS_A > ; impl < 'a , REG , const O : u8 > CTL0_RTS_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn ctl0_rts_clr (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_RTS_A :: CTL0_RTS_CLR) } # [doc = "SET"] # [inline (always)] pub fn ctl0_rts_set (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_RTS_A :: CTL0_RTS_SET) } } # [doc = "Field `CTL0_RTSEN` reader - Enable hardware controlled Request to Send"] pub type CTL0_RTSEN_R = crate :: BitReader < CTL0_RTSEN_A > ; # [doc = "Enable hardware controlled Request to Send\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CTL0_RTSEN_A { # [doc = "0: DISABLE"] CTL0_RTSEN_DISABLE = 0 , # [doc = "1: ENABLE"] CTL0_RTSEN_ENABLE = 1 , } impl From < CTL0_RTSEN_A > for bool { # [inline (always)] fn from (variant : CTL0_RTSEN_A) -> Self { variant as u8 != 0 } } impl CTL0_RTSEN_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CTL0_RTSEN_A { match self . bits { false => CTL0_RTSEN_A :: CTL0_RTSEN_DISABLE , true => CTL0_RTSEN_A :: CTL0_RTSEN_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_ctl0_rtsen_disable (& self) -> bool { * self == CTL0_RTSEN_A :: CTL0_RTSEN_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_ctl0_rtsen_enable (& self) -> bool { * self == CTL0_RTSEN_A :: CTL0_RTSEN_ENABLE } } # [doc = "Field `CTL0_RTSEN` writer - Enable hardware controlled Request to Send"] pub type CTL0_RTSEN_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL0_RTSEN_A > ; impl < 'a , REG , const O : u8 > CTL0_RTSEN_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn ctl0_rtsen_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_RTSEN_A :: CTL0_RTSEN_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn ctl0_rtsen_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_RTSEN_A :: CTL0_RTSEN_ENABLE) } } # [doc = "Field `CTL0_CTSEN` reader - Enable Clear To Send"] pub type CTL0_CTSEN_R = crate :: BitReader < CTL0_CTSEN_A > ; # [doc = "Enable Clear To Send\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CTL0_CTSEN_A { # [doc = "0: DISABLE"] CTL0_CTSEN_DISABLE = 0 , # [doc = "1: ENABLE"] CTL0_CTSEN_ENABLE = 1 , } impl From < CTL0_CTSEN_A > for bool { # [inline (always)] fn from (variant : CTL0_CTSEN_A) -> Self { variant as u8 != 0 } } impl CTL0_CTSEN_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CTL0_CTSEN_A { match self . bits { false => CTL0_CTSEN_A :: CTL0_CTSEN_DISABLE , true => CTL0_CTSEN_A :: CTL0_CTSEN_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_ctl0_ctsen_disable (& self) -> bool { * self == CTL0_CTSEN_A :: CTL0_CTSEN_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_ctl0_ctsen_enable (& self) -> bool { * self == CTL0_CTSEN_A :: CTL0_CTSEN_ENABLE } } # [doc = "Field `CTL0_CTSEN` writer - Enable Clear To Send"] pub type CTL0_CTSEN_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL0_CTSEN_A > ; impl < 'a , REG , const O : u8 > CTL0_CTSEN_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn ctl0_ctsen_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_CTSEN_A :: CTL0_CTSEN_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn ctl0_ctsen_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_CTSEN_A :: CTL0_CTSEN_ENABLE) } } # [doc = "Field `CTL0_HSE` reader - High-Speed Bit Oversampling Enable #b#NOTE:#/b# The bit oversampling influences the UART baud-rate configuration (see and ). The state of this bit has no effect on clock generation in ISO7816 smart card mode (the SMART bit is set)."] pub type CTL0_HSE_R = crate :: FieldReader < CTL0_HSE_A > ; # [doc = "High-Speed Bit Oversampling Enable #b#NOTE:#/b# The bit oversampling influences the UART baud-rate configuration (see and ). The state of this bit has no effect on clock generation in ISO7816 smart card mode (the SMART bit is set).\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum CTL0_HSE_A { # [doc = "0: OVS16"] CTL0_HSE_OVS16 = 0 , # [doc = "1: OVS8"] CTL0_HSE_OVS8 = 1 , # [doc = "2: OVS3"] CTL0_HSE_OVS3 = 2 , } impl From < CTL0_HSE_A > for u8 { # [inline (always)] fn from (variant : CTL0_HSE_A) -> Self { variant as _ } } impl crate :: FieldSpec for CTL0_HSE_A { type Ux = u8 ; } impl CTL0_HSE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < CTL0_HSE_A > { match self . bits { 0 => Some (CTL0_HSE_A :: CTL0_HSE_OVS16) , 1 => Some (CTL0_HSE_A :: CTL0_HSE_OVS8) , 2 => Some (CTL0_HSE_A :: CTL0_HSE_OVS3) , _ => None , } } # [doc = "OVS16"] # [inline (always)] pub fn is_ctl0_hse_ovs16 (& self) -> bool { * self == CTL0_HSE_A :: CTL0_HSE_OVS16 } # [doc = "OVS8"] # [inline (always)] pub fn is_ctl0_hse_ovs8 (& self) -> bool { * self == CTL0_HSE_A :: CTL0_HSE_OVS8 } # [doc = "OVS3"] # [inline (always)] pub fn is_ctl0_hse_ovs3 (& self) -> bool { * self == CTL0_HSE_A :: CTL0_HSE_OVS3 } } # [doc = "Field `CTL0_HSE` writer - High-Speed Bit Oversampling Enable #b#NOTE:#/b# The bit oversampling influences the UART baud-rate configuration (see and ). The state of this bit has no effect on clock generation in ISO7816 smart card mode (the SMART bit is set)."] pub type CTL0_HSE_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 2 , O , CTL0_HSE_A > ; impl < 'a , REG , const O : u8 > CTL0_HSE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "OVS16"] # [inline (always)] pub fn ctl0_hse_ovs16 (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_HSE_A :: CTL0_HSE_OVS16) } # [doc = "OVS8"] # [inline (always)] pub fn ctl0_hse_ovs8 (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_HSE_A :: CTL0_HSE_OVS8) } # [doc = "OVS3"] # [inline (always)] pub fn ctl0_hse_ovs3 (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_HSE_A :: CTL0_HSE_OVS3) } } # [doc = "Field `CTL0_FEN` reader - UART Enable FIFOs"] pub type CTL0_FEN_R = crate :: BitReader < CTL0_FEN_A > ; # [doc = "UART Enable FIFOs\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CTL0_FEN_A { # [doc = "0: DISABLE"] CTL0_FEN_DISABLE = 0 , # [doc = "1: ENABLE"] CTL0_FEN_ENABLE = 1 , } impl From < CTL0_FEN_A > for bool { # [inline (always)] fn from (variant : CTL0_FEN_A) -> Self { variant as u8 != 0 } } impl CTL0_FEN_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CTL0_FEN_A { match self . bits { false => CTL0_FEN_A :: CTL0_FEN_DISABLE , true => CTL0_FEN_A :: CTL0_FEN_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_ctl0_fen_disable (& self) -> bool { * self == CTL0_FEN_A :: CTL0_FEN_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_ctl0_fen_enable (& self) -> bool { * self == CTL0_FEN_A :: CTL0_FEN_ENABLE } } # [doc = "Field `CTL0_FEN` writer - UART Enable FIFOs"] pub type CTL0_FEN_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL0_FEN_A > ; impl < 'a , REG , const O : u8 > CTL0_FEN_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn ctl0_fen_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_FEN_A :: CTL0_FEN_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn ctl0_fen_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_FEN_A :: CTL0_FEN_ENABLE) } } # [doc = "Field `CTL0_MAJVOTE` reader - When enabled with oversmapling of 16, samples samples 7, 8, and 9 are majority voted to decide the sampled bit value. The value correspond to al least 2 of the 3 samples is considered to be the received value. In case the 3 values do not match, RIS.NERR bit is set along with RDR.NERR When enabled with oversmapling of 8, samples samples 3, 4, and 5 are majority voted to decide the sampled bit value. The value correspond to al least 2 of the 3 samples is considered to be the received value. In case the 3 values donot match, RIS.NERR bit is set along with RDR.NERR When disabled, only a single sample of received bit is taken."] pub type CTL0_MAJVOTE_R = crate :: BitReader < CTL0_MAJVOTE_A > ; # [doc = "When enabled with oversmapling of 16, samples samples 7, 8, and 9 are majority voted to decide the sampled bit value. The value correspond to al least 2 of the 3 samples is considered to be the received value. In case the 3 values do not match, RIS.NERR bit is set along with RDR.NERR When enabled with oversmapling of 8, samples samples 3, 4, and 5 are majority voted to decide the sampled bit value. The value correspond to al least 2 of the 3 samples is considered to be the received value. In case the 3 values donot match, RIS.NERR bit is set along with RDR.NERR When disabled, only a single sample of received bit is taken.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CTL0_MAJVOTE_A { # [doc = "0: DISABLE"] CTL0_MAJVOTE_DISABLE = 0 , # [doc = "1: ENABLE"] CTL0_MAJVOTE_ENABLE = 1 , } impl From < CTL0_MAJVOTE_A > for bool { # [inline (always)] fn from (variant : CTL0_MAJVOTE_A) -> Self { variant as u8 != 0 } } impl CTL0_MAJVOTE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CTL0_MAJVOTE_A { match self . bits { false => CTL0_MAJVOTE_A :: CTL0_MAJVOTE_DISABLE , true => CTL0_MAJVOTE_A :: CTL0_MAJVOTE_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_ctl0_majvote_disable (& self) -> bool { * self == CTL0_MAJVOTE_A :: CTL0_MAJVOTE_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_ctl0_majvote_enable (& self) -> bool { * self == CTL0_MAJVOTE_A :: CTL0_MAJVOTE_ENABLE } } # [doc = "Field `CTL0_MAJVOTE` writer - When enabled with oversmapling of 16, samples samples 7, 8, and 9 are majority voted to decide the sampled bit value. The value correspond to al least 2 of the 3 samples is considered to be the received value. In case the 3 values do not match, RIS.NERR bit is set along with RDR.NERR When enabled with oversmapling of 8, samples samples 3, 4, and 5 are majority voted to decide the sampled bit value. The value correspond to al least 2 of the 3 samples is considered to be the received value. In case the 3 values donot match, RIS.NERR bit is set along with RDR.NERR When disabled, only a single sample of received bit is taken."] pub type CTL0_MAJVOTE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL0_MAJVOTE_A > ; impl < 'a , REG , const O : u8 > CTL0_MAJVOTE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn ctl0_majvote_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_MAJVOTE_A :: CTL0_MAJVOTE_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn ctl0_majvote_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_MAJVOTE_A :: CTL0_MAJVOTE_ENABLE) } } # [doc = "Field `CTL0_MSBFIRST` reader - Most Significant Bit First This bit has effect both on the way protocol byte is transmitted and received. Notes: User needs to match the protocol to the correct value of this bit to send MSb or LSb first. The hardware engine will send the byte entirely based on this bit."] pub type CTL0_MSBFIRST_R = crate :: BitReader < CTL0_MSBFIRST_A > ; # [doc = "Most Significant Bit First This bit has effect both on the way protocol byte is transmitted and received. Notes: User needs to match the protocol to the correct value of this bit to send MSb or LSb first. The hardware engine will send the byte entirely based on this bit.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CTL0_MSBFIRST_A { # [doc = "0: DISABLE"] CTL0_MSBFIRST_DISABLE = 0 , # [doc = "1: ENABLE"] CTL0_MSBFIRST_ENABLE = 1 , } impl From < CTL0_MSBFIRST_A > for bool { # [inline (always)] fn from (variant : CTL0_MSBFIRST_A) -> Self { variant as u8 != 0 } } impl CTL0_MSBFIRST_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CTL0_MSBFIRST_A { match self . bits { false => CTL0_MSBFIRST_A :: CTL0_MSBFIRST_DISABLE , true => CTL0_MSBFIRST_A :: CTL0_MSBFIRST_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_ctl0_msbfirst_disable (& self) -> bool { * self == CTL0_MSBFIRST_A :: CTL0_MSBFIRST_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_ctl0_msbfirst_enable (& self) -> bool { * self == CTL0_MSBFIRST_A :: CTL0_MSBFIRST_ENABLE } } # [doc = "Field `CTL0_MSBFIRST` writer - Most Significant Bit First This bit has effect both on the way protocol byte is transmitted and received. Notes: User needs to match the protocol to the correct value of this bit to send MSb or LSb first. The hardware engine will send the byte entirely based on this bit."] pub type CTL0_MSBFIRST_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL0_MSBFIRST_A > ; impl < 'a , REG , const O : u8 > CTL0_MSBFIRST_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn ctl0_msbfirst_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_MSBFIRST_A :: CTL0_MSBFIRST_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn ctl0_msbfirst_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_MSBFIRST_A :: CTL0_MSBFIRST_ENABLE) } } impl R { # [doc = "Bit 0 - UART Module Enable. If the UART is disabled in the middle of transmission or reception, it completes the current character before stopping. If the ENABLE bit is not set, all registers can still be accessed and updated. It is recommended to setup and change the UART operation mode with having the ENABLE bit cleared to avoid unpredictable behavior during the setup or update. If disabled the UART module will not send or receive any data and the logic is held in reset state."] # [inline (always)] pub fn ctl0_enable (& self) -> CTL0_ENABLE_R { CTL0_ENABLE_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 2 - UART Loop Back Enable"] # [inline (always)] pub fn ctl0_lbe (& self) -> CTL0_LBE_R { CTL0_LBE_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - UART Receive Enable If the UART is disabled in the middle of a receive, it completes the current character before stopping. #b#NOTE:#/b# To enable reception, the UARTEN bit must be set."] # [inline (always)] pub fn ctl0_rxe (& self) -> CTL0_RXE_R { CTL0_RXE_R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - UART Transmit Enable If the UART is disabled in the middle of a transmission, it completes the current character before stopping. #b#NOTE:#/b# To enable transmission, the UARTEN bit must be set."] # [inline (always)] pub fn ctl0_txe (& self) -> CTL0_TXE_R { CTL0_TXE_R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - TXD Pin Control Enable. When the transmit section of the UART is disabled (TXE = 0), the TXD pin can be controlled by the TXD_OUT bit. 1 = UARTxTXD pin can be controlled by TXD_OUT, if TXE = 0"] # [inline (always)] pub fn ctl0_txd_out_en (& self) -> CTL0_TXD_OUT_EN_R { CTL0_TXD_OUT_EN_R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - TXD Pin Control Controls the TXD pin when TXD_OUT_EN = 1 and TXE = 0."] # [inline (always)] pub fn ctl0_txd_out (& self) -> CTL0_TXD_OUT_R { CTL0_TXD_OUT_R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - Manchester Encode enable"] # [inline (always)] pub fn ctl0_menc (& self) -> CTL0_MENC_R { CTL0_MENC_R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bits 8:10 - Set the communication mode and protocol used. (Not defined settings uses the default setting: 0)"] # [inline (always)] pub fn ctl0_mode (& self) -> CTL0_MODE_R { CTL0_MODE_R :: new (((self . bits >> 8) & 7) as u8) } # [doc = "Bit 12 - Request to Send If RTSEN is set the RTS output signals is controlled by the hardware logic using the FIFO fill level or TXDATA buffer. If RTSEN is cleared the RTS output is controlled by the RTS bit. The bit is the complement of the UART request to send, RTS modem status output."] # [inline (always)] pub fn ctl0_rts (& self) -> CTL0_RTS_R { CTL0_RTS_R :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - Enable hardware controlled Request to Send"] # [inline (always)] pub fn ctl0_rtsen (& self) -> CTL0_RTSEN_R { CTL0_RTSEN_R :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 14 - Enable Clear To Send"] # [inline (always)] pub fn ctl0_ctsen (& self) -> CTL0_CTSEN_R { CTL0_CTSEN_R :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bits 15:16 - High-Speed Bit Oversampling Enable #b#NOTE:#/b# The bit oversampling influences the UART baud-rate configuration (see and ). The state of this bit has no effect on clock generation in ISO7816 smart card mode (the SMART bit is set)."] # [inline (always)] pub fn ctl0_hse (& self) -> CTL0_HSE_R { CTL0_HSE_R :: new (((self . bits >> 15) & 3) as u8) } # [doc = "Bit 17 - UART Enable FIFOs"] # [inline (always)] pub fn ctl0_fen (& self) -> CTL0_FEN_R { CTL0_FEN_R :: new (((self . bits >> 17) & 1) != 0) } # [doc = "Bit 18 - When enabled with oversmapling of 16, samples samples 7, 8, and 9 are majority voted to decide the sampled bit value. The value correspond to al least 2 of the 3 samples is considered to be the received value. In case the 3 values do not match, RIS.NERR bit is set along with RDR.NERR When enabled with oversmapling of 8, samples samples 3, 4, and 5 are majority voted to decide the sampled bit value. The value correspond to al least 2 of the 3 samples is considered to be the received value. In case the 3 values donot match, RIS.NERR bit is set along with RDR.NERR When disabled, only a single sample of received bit is taken."] # [inline (always)] pub fn ctl0_majvote (& self) -> CTL0_MAJVOTE_R { CTL0_MAJVOTE_R :: new (((self . bits >> 18) & 1) != 0) } # [doc = "Bit 19 - Most Significant Bit First This bit has effect both on the way protocol byte is transmitted and received. Notes: User needs to match the protocol to the correct value of this bit to send MSb or LSb first. The hardware engine will send the byte entirely based on this bit."] # [inline (always)] pub fn ctl0_msbfirst (& self) -> CTL0_MSBFIRST_R { CTL0_MSBFIRST_R :: new (((self . bits >> 19) & 1) != 0) } } impl W { # [doc = "Bit 0 - UART Module Enable. If the UART is disabled in the middle of transmission or reception, it completes the current character before stopping. If the ENABLE bit is not set, all registers can still be accessed and updated. It is recommended to setup and change the UART operation mode with having the ENABLE bit cleared to avoid unpredictable behavior during the setup or update. If disabled the UART module will not send or receive any data and the logic is held in reset state."] # [inline (always)] # [must_use] pub fn ctl0_enable (& mut self) -> CTL0_ENABLE_W < CTL0_SPEC , 0 > { CTL0_ENABLE_W :: new (self) } # [doc = "Bit 2 - UART Loop Back Enable"] # [inline (always)] # [must_use] pub fn ctl0_lbe (& mut self) -> CTL0_LBE_W < CTL0_SPEC , 2 > { CTL0_LBE_W :: new (self) } # [doc = "Bit 3 - UART Receive Enable If the UART is disabled in the middle of a receive, it completes the current character before stopping. #b#NOTE:#/b# To enable reception, the UARTEN bit must be set."] # [inline (always)] # [must_use] pub fn ctl0_rxe (& mut self) -> CTL0_RXE_W <'_,  CTL0_SPEC , 3 > { CTL0_RXE_W :: new (self) } # [doc = "Bit 4 - UART Transmit Enable If the UART is disabled in the middle of a transmission, it completes the current character before stopping. #b#NOTE:#/b# To enable transmission, the UARTEN bit must be set."] # [inline (always)] # [must_use] pub fn ctl0_txe (& mut self) -> CTL0_TXE_W < CTL0_SPEC , 4 > { CTL0_TXE_W :: new (self) } # [doc = "Bit 5 - TXD Pin Control Enable. When the transmit section of the UART is disabled (TXE = 0), the TXD pin can be controlled by the TXD_OUT bit. 1 = UARTxTXD pin can be controlled by TXD_OUT, if TXE = 0"] # [inline (always)] # [must_use] pub fn ctl0_txd_out_en (& mut self) -> CTL0_TXD_OUT_EN_W < CTL0_SPEC , 5 > { CTL0_TXD_OUT_EN_W :: new (self) } # [doc = "Bit 6 - TXD Pin Control Controls the TXD pin when TXD_OUT_EN = 1 and TXE = 0."] # [inline (always)] # [must_use] pub fn ctl0_txd_out (& mut self) -> CTL0_TXD_OUT_W < CTL0_SPEC , 6 > { CTL0_TXD_OUT_W :: new (self) } # [doc = "Bit 7 - Manchester Encode enable"] # [inline (always)] # [must_use] pub fn ctl0_menc (& mut self) -> CTL0_MENC_W < CTL0_SPEC , 7 > { CTL0_MENC_W :: new (self) } # [doc = "Bits 8:10 - Set the communication mode and protocol used. (Not defined settings uses the default setting: 0)"] # [inline (always)] # [must_use] pub fn ctl0_mode (& mut self) -> CTL0_MODE_W < CTL0_SPEC , 8 > { CTL0_MODE_W :: new (self) } # [doc = "Bit 12 - Request to Send If RTSEN is set the RTS output signals is controlled by the hardware logic using the FIFO fill level or TXDATA buffer. If RTSEN is cleared the RTS output is controlled by the RTS bit. The bit is the complement of the UART request to send, RTS modem status output."] # [inline (always)] # [must_use] pub fn ctl0_rts (& mut self) -> CTL0_RTS_W < CTL0_SPEC , 12 > { CTL0_RTS_W :: new (self) } # [doc = "Bit 13 - Enable hardware controlled Request to Send"] # [inline (always)] # [must_use] pub fn ctl0_rtsen (& mut self) -> CTL0_RTSEN_W < CTL0_SPEC , 13 > { CTL0_RTSEN_W :: new (self) } # [doc = "Bit 14 - Enable Clear To Send"] # [inline (always)] # [must_use] pub fn ctl0_ctsen (& mut self) -> CTL0_CTSEN_W < CTL0_SPEC , 14 > { CTL0_CTSEN_W :: new (self) } # [doc = "Bits 15:16 - High-Speed Bit Oversampling Enable #b#NOTE:#/b# The bit oversampling influences the UART baud-rate configuration (see and ). The state of this bit has no effect on clock generation in ISO7816 smart card mode (the SMART bit is set)."] # [inline (always)] # [must_use] pub fn ctl0_hse (& mut self) -> CTL0_HSE_W < CTL0_SPEC , 15 > { CTL0_HSE_W :: new (self) } # [doc = "Bit 17 - UART Enable FIFOs"] # [inline (always)] # [must_use] pub fn ctl0_fen (& mut self) -> CTL0_FEN_W < CTL0_SPEC , 17 > { CTL0_FEN_W :: new (self) } # [doc = "Bit 18 - When enabled with oversmapling of 16, samples samples 7, 8, and 9 are majority voted to decide the sampled bit value. The value correspond to al least 2 of the 3 samples is considered to be the received value. In case the 3 values do not match, RIS.NERR bit is set along with RDR.NERR When enabled with oversmapling of 8, samples samples 3, 4, and 5 are majority voted to decide the sampled bit value. The value correspond to al least 2 of the 3 samples is considered to be the received value. In case the 3 values donot match, RIS.NERR bit is set along with RDR.NERR When disabled, only a single sample of received bit is taken."] # [inline (always)] # [must_use] pub fn ctl0_majvote (& mut self) -> CTL0_MAJVOTE_W < CTL0_SPEC , 18 > { CTL0_MAJVOTE_W :: new (self) } # [doc = "Bit 19 - Most Significant Bit First This bit has effect both on the way protocol byte is transmitted and received. Notes: User needs to match the protocol to the correct value of this bit to send MSb or LSb first. The hardware engine will send the byte entirely based on this bit."] # [inline (always)] # [must_use] pub fn ctl0_msbfirst (& mut self) -> CTL0_MSBFIRST_W < CTL0_SPEC , 19 > { CTL0_MSBFIRST_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "UART Control Register 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctl0::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctl0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CTL0_SPEC ; impl crate :: RegisterSpec for CTL0_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`ctl0::R`](R) reader structure"] impl crate :: Readable for CTL0_SPEC { } # [doc = "`write(|w| ..)` method takes [`ctl0::W`](W) writer structure"] impl crate :: Writable for CTL0_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets CTL0 to value 0x38"] impl crate :: Resettable for CTL0_SPEC { const RESET_VALUE : Self :: Ux = 0x38 ; }
[INFO] [stdout]   |                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                        +++
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing
[INFO] [stdout]  --> src/uart0/int_event0_imask.rs:1:42871
[INFO] [stdout]   |
[INFO] [stdout] 1 | ...imask_rxint (& mut self) -> INT_EVENT0_IMASK_RXINT_W < INT_EVENT0_IMASK_SPEC , 10 > { INT_EVENT0_IMASK_RXINT_W :: new (self) } # [...
[INFO] [stdout]   |                 ^^^^^^^^^^     ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here
[INFO] [stdout]   |                 |
[INFO] [stdout]   |                 the lifetime is elided here
[INFO] [stdout]   |
[INFO] [stdout]   = help: the same lifetime is referred to in inconsistent ways, making the signature confusing
[INFO] [stdout] help: use `'_` for type paths
[INFO] [stdout]   |
[INFO] [stdout] 1 | # [doc = "Register `INT_EVENT0_IMASK` reader"] pub type R = crate :: R < INT_EVENT0_IMASK_SPEC > ; # [doc = "Register `INT_EVENT0_IMASK` writer"] pub type W = crate :: W < INT_EVENT0_IMASK_SPEC > ; # [doc = "Field `INT_EVENT0_IMASK_RTOUT` reader - Enable UARTOUT Receive Time-Out Interrupt."] pub type INT_EVENT0_IMASK_RTOUT_R = crate :: BitReader < INT_EVENT0_IMASK_RTOUT_A > ; # [doc = "Enable UARTOUT Receive Time-Out Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_RTOUT_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_RTOUT_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_RTOUT_SET = 1 , } impl From < INT_EVENT0_IMASK_RTOUT_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_RTOUT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_RTOUT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_RTOUT_A { match self . bits { false => INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_CLR , true => INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_rtout_clr (& self) -> bool { * self == INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_rtout_set (& self) -> bool { * self == INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_SET } } # [doc = "Field `INT_EVENT0_IMASK_RTOUT` writer - Enable UARTOUT Receive Time-Out Interrupt."] pub type INT_EVENT0_IMASK_RTOUT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_RTOUT_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_RTOUT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_rtout_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_rtout_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_SET) } } # [doc = "Field `INT_EVENT0_IMASK_FRMERR` reader - Enable UART Framing Error Interrupt."] pub type INT_EVENT0_IMASK_FRMERR_R = crate :: BitReader < INT_EVENT0_IMASK_FRMERR_A > ; # [doc = "Enable UART Framing Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_FRMERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_FRMERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_FRMERR_SET = 1 , } impl From < INT_EVENT0_IMASK_FRMERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_FRMERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_FRMERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_FRMERR_A { match self . bits { false => INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_CLR , true => INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_frmerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_frmerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_FRMERR` writer - Enable UART Framing Error Interrupt."] pub type INT_EVENT0_IMASK_FRMERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_FRMERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_FRMERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_frmerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_frmerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_SET) } } # [doc = "Field `INT_EVENT0_IMASK_PARERR` reader - Enable UART Parity Error Interrupt."] pub type INT_EVENT0_IMASK_PARERR_R = crate :: BitReader < INT_EVENT0_IMASK_PARERR_A > ; # [doc = "Enable UART Parity Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_PARERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_PARERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_PARERR_SET = 1 , } impl From < INT_EVENT0_IMASK_PARERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_PARERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_PARERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_PARERR_A { match self . bits { false => INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_CLR , true => INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_parerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_parerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_PARERR` writer - Enable UART Parity Error Interrupt."] pub type INT_EVENT0_IMASK_PARERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_PARERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_PARERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_parerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_parerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_SET) } } # [doc = "Field `INT_EVENT0_IMASK_BRKERR` reader - Enable UART Break Error Interrupt."] pub type INT_EVENT0_IMASK_BRKERR_R = crate :: BitReader < INT_EVENT0_IMASK_BRKERR_A > ; # [doc = "Enable UART Break Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_BRKERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_BRKERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_BRKERR_SET = 1 , } impl From < INT_EVENT0_IMASK_BRKERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_BRKERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_BRKERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_BRKERR_A { match self . bits { false => INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_CLR , true => INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_brkerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_brkerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_BRKERR` writer - Enable UART Break Error Interrupt."] pub type INT_EVENT0_IMASK_BRKERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_BRKERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_BRKERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_brkerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_brkerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_SET) } } # [doc = "Field `INT_EVENT0_IMASK_OVRERR` reader - Enable UART Receive Overrun Error Interrupt."] pub type INT_EVENT0_IMASK_OVRERR_R = crate :: BitReader < INT_EVENT0_IMASK_OVRERR_A > ; # [doc = "Enable UART Receive Overrun Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_OVRERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_OVRERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_OVRERR_SET = 1 , } impl From < INT_EVENT0_IMASK_OVRERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_OVRERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_OVRERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_OVRERR_A { match self . bits { false => INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_CLR , true => INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_ovrerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_ovrerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_OVRERR` writer - Enable UART Receive Overrun Error Interrupt."] pub type INT_EVENT0_IMASK_OVRERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_OVRERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_OVRERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_ovrerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_ovrerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_SET) } } # [doc = "Field `INT_EVENT0_IMASK_RXNE` reader - Enable Negative Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_IMASK_RXNE_R = crate :: BitReader < INT_EVENT0_IMASK_RXNE_A > ; # [doc = "Enable Negative Edge on UARTxRXD Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_RXNE_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_RXNE_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_RXNE_SET = 1 , } impl From < INT_EVENT0_IMASK_RXNE_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_RXNE_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_RXNE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_RXNE_A { match self . bits { false => INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_CLR , true => INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_rxne_clr (& self) -> bool { * self == INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_rxne_set (& self) -> bool { * self == INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_SET } } # [doc = "Field `INT_EVENT0_IMASK_RXNE` writer - Enable Negative Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_IMASK_RXNE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_RXNE_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_RXNE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_rxne_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_rxne_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_SET) } } # [doc = "Field `INT_EVENT0_IMASK_RXPE` reader - Enable Positive Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_IMASK_RXPE_R = crate :: BitReader < INT_EVENT0_IMASK_RXPE_A > ; # [doc = "Enable Positive Edge on UARTxRXD Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_RXPE_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_RXPE_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_RXPE_SET = 1 , } impl From < INT_EVENT0_IMASK_RXPE_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_RXPE_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_RXPE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_RXPE_A { match self . bits { false => INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_CLR , true => INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_rxpe_clr (& self) -> bool { * self == INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_rxpe_set (& self) -> bool { * self == INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_SET } } # [doc = "Field `INT_EVENT0_IMASK_RXPE` writer - Enable Positive Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_IMASK_RXPE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_RXPE_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_RXPE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_rxpe_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_rxpe_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_SET) } } # [doc = "Field `INT_EVENT0_IMASK_LINC0` reader - Enable LIN Capture 0 / Match Interrupt ."] pub type INT_EVENT0_IMASK_LINC0_R = crate :: BitReader < INT_EVENT0_IMASK_LINC0_A > ; # [doc = "Enable LIN Capture 0 / Match Interrupt .\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_LINC0_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_LINC0_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_LINC0_SET = 1 , } impl From < INT_EVENT0_IMASK_LINC0_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_LINC0_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_LINC0_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_LINC0_A { match self . bits { false => INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_CLR , true => INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_linc0_clr (& self) -> bool { * self == INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_linc0_set (& self) -> bool { * self == INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_SET } } # [doc = "Field `INT_EVENT0_IMASK_LINC0` writer - Enable LIN Capture 0 / Match Interrupt ."] pub type INT_EVENT0_IMASK_LINC0_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_LINC0_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_LINC0_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_linc0_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_linc0_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_SET) } } # [doc = "Field `INT_EVENT0_IMASK_LINC1` reader - Enable LIN Capture 1 Interrupt."] pub type INT_EVENT0_IMASK_LINC1_R = crate :: BitReader < INT_EVENT0_IMASK_LINC1_A > ; # [doc = "Enable LIN Capture 1 Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_LINC1_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_LINC1_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_LINC1_SET = 1 , } impl From < INT_EVENT0_IMASK_LINC1_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_LINC1_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_LINC1_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_LINC1_A { match self . bits { false => INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_CLR , true => INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_linc1_clr (& self) -> bool { * self == INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_linc1_set (& self) -> bool { * self == INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_SET } } # [doc = "Field `INT_EVENT0_IMASK_LINC1` writer - Enable LIN Capture 1 Interrupt."] pub type INT_EVENT0_IMASK_LINC1_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_LINC1_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_LINC1_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_linc1_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_linc1_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_SET) } } # [doc = "Field `INT_EVENT0_IMASK_LINOVF` reader - Enable LIN Hardware Counter Overflow Interrupt."] pub type INT_EVENT0_IMASK_LINOVF_R = crate :: BitReader < INT_EVENT0_IMASK_LINOVF_A > ; # [doc = "Enable LIN Hardware Counter Overflow Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_LINOVF_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_LINOVF_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_LINOVF_SET = 1 , } impl From < INT_EVENT0_IMASK_LINOVF_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_LINOVF_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_LINOVF_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_LINOVF_A { match self . bits { false => INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_CLR , true => INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_linovf_clr (& self) -> bool { * self == INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_linovf_set (& self) -> bool { * self == INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_SET } } # [doc = "Field `INT_EVENT0_IMASK_LINOVF` writer - Enable LIN Hardware Counter Overflow Interrupt."] pub type INT_EVENT0_IMASK_LINOVF_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_LINOVF_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_LINOVF_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_linovf_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_linovf_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_SET) } } # [doc = "Field `INT_EVENT0_IMASK_RXINT` reader - Enable UART Receive Interrupt."] pub type INT_EVENT0_IMASK_RXINT_R = crate :: BitReader < INT_EVENT0_IMASK_RXINT_A > ; # [doc = "Enable UART Receive Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_RXINT_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_RXINT_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_RXINT_SET = 1 , } impl From < INT_EVENT0_IMASK_RXINT_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_RXINT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_RXINT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_RXINT_A { match self . bits { false => INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_CLR , true => INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_rxint_clr (& self) -> bool { * self == INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_rxint_set (& self) -> bool { * self == INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_SET } } # [doc = "Field `INT_EVENT0_IMASK_RXINT` writer - Enable UART Receive Interrupt."] pub type INT_EVENT0_IMASK_RXINT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_RXINT_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_RXINT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_rxint_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_rxint_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_SET) } } # [doc = "Field `INT_EVENT0_IMASK_TXINT` reader - Enable UART Transmit Interrupt."] pub type INT_EVENT0_IMASK_TXINT_R = crate :: BitReader < INT_EVENT0_IMASK_TXINT_A > ; # [doc = "Enable UART Transmit Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_TXINT_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_TXINT_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_TXINT_SET = 1 , } impl From < INT_EVENT0_IMASK_TXINT_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_TXINT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_TXINT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_TXINT_A { match self . bits { false => INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_CLR , true => INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_txint_clr (& self) -> bool { * self == INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_txint_set (& self) -> bool { * self == INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_SET } } # [doc = "Field `INT_EVENT0_IMASK_TXINT` writer - Enable UART Transmit Interrupt."] pub type INT_EVENT0_IMASK_TXINT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_TXINT_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_TXINT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_txint_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_txint_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_SET) } } # [doc = "Field `INT_EVENT0_IMASK_EOT` reader - Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] pub type INT_EVENT0_IMASK_EOT_R = crate :: BitReader < INT_EVENT0_IMASK_EOT_A > ; # [doc = "Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_EOT_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_EOT_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_EOT_SET = 1 , } impl From < INT_EVENT0_IMASK_EOT_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_EOT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_EOT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_EOT_A { match self . bits { false => INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_CLR , true => INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_eot_clr (& self) -> bool { * self == INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_eot_set (& self) -> bool { * self == INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_SET } } # [doc = "Field `INT_EVENT0_IMASK_EOT` writer - Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] pub type INT_EVENT0_IMASK_EOT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_EOT_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_EOT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_eot_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_eot_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_SET) } } # [doc = "Field `INT_EVENT0_IMASK_ADDR_MATCH` reader - Enable Address Match Interrupt."] pub type INT_EVENT0_IMASK_ADDR_MATCH_R = crate :: BitReader < INT_EVENT0_IMASK_ADDR_MATCH_A > ; # [doc = "Enable Address Match Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_ADDR_MATCH_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_ADDR_MATCH_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_ADDR_MATCH_SET = 1 , } impl From < INT_EVENT0_IMASK_ADDR_MATCH_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_ADDR_MATCH_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_ADDR_MATCH_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_ADDR_MATCH_A { match self . bits { false => INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_CLR , true => INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_addr_match_clr (& self) -> bool { * self == INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_addr_match_set (& self) -> bool { * self == INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_SET } } # [doc = "Field `INT_EVENT0_IMASK_ADDR_MATCH` writer - Enable Address Match Interrupt."] pub type INT_EVENT0_IMASK_ADDR_MATCH_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_ADDR_MATCH_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_ADDR_MATCH_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_addr_match_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_addr_match_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_SET) } } # [doc = "Field `INT_EVENT0_IMASK_CTS` reader - Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] pub type INT_EVENT0_IMASK_CTS_R = crate :: BitReader < INT_EVENT0_IMASK_CTS_A > ; # [doc = "Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_CTS_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_CTS_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_CTS_SET = 1 , } impl From < INT_EVENT0_IMASK_CTS_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_CTS_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_CTS_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_CTS_A { match self . bits { false => INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_CLR , true => INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_cts_clr (& self) -> bool { * self == INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_cts_set (& self) -> bool { * self == INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_SET } } # [doc = "Field `INT_EVENT0_IMASK_CTS` writer - Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] pub type INT_EVENT0_IMASK_CTS_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_CTS_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_CTS_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_cts_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_cts_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DMA_DONE_RX` reader - Enable DMA Done on RX Event Channel"] pub type INT_EVENT0_IMASK_DMA_DONE_RX_R = crate :: BitReader < INT_EVENT0_IMASK_DMA_DONE_RX_A > ; # [doc = "Enable DMA Done on RX Event Channel\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DMA_DONE_RX_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DMA_DONE_RX_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DMA_DONE_RX_SET = 1 , } impl From < INT_EVENT0_IMASK_DMA_DONE_RX_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DMA_DONE_RX_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DMA_DONE_RX_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DMA_DONE_RX_A { match self . bits { false => INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_CLR , true => INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dma_done_rx_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dma_done_rx_set (& self) -> bool { * self == INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_SET } } # [doc = "Field `INT_EVENT0_IMASK_DMA_DONE_RX` writer - Enable DMA Done on RX Event Channel"] pub type INT_EVENT0_IMASK_DMA_DONE_RX_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DMA_DONE_RX_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DMA_DONE_RX_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dma_done_rx_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dma_done_rx_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DMA_DONE_TX` reader - Enable DMA Done on TX Event Channel"] pub type INT_EVENT0_IMASK_DMA_DONE_TX_R = crate :: BitReader < INT_EVENT0_IMASK_DMA_DONE_TX_A > ; # [doc = "Enable DMA Done on TX Event Channel\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DMA_DONE_TX_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DMA_DONE_TX_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DMA_DONE_TX_SET = 1 , } impl From < INT_EVENT0_IMASK_DMA_DONE_TX_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DMA_DONE_TX_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DMA_DONE_TX_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DMA_DONE_TX_A { match self . bits { false => INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_CLR , true => INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dma_done_tx_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dma_done_tx_set (& self) -> bool { * self == INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_SET } } # [doc = "Field `INT_EVENT0_IMASK_DMA_DONE_TX` writer - Enable DMA Done on TX Event Channel"] pub type INT_EVENT0_IMASK_DMA_DONE_TX_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DMA_DONE_TX_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DMA_DONE_TX_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dma_done_tx_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dma_done_tx_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_SET) } } # [doc = "Field `INT_EVENT0_IMASK_NERR` reader - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] pub type INT_EVENT0_IMASK_NERR_R = crate :: BitReader < INT_EVENT0_IMASK_NERR_A > ; # [doc = "Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_NERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_NERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_NERR_SET = 1 , } impl From < INT_EVENT0_IMASK_NERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_NERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_NERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_NERR_A { match self . bits { false => INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_CLR , true => INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_nerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_nerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_NERR` writer - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] pub type INT_EVENT0_IMASK_NERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_NERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_NERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_nerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_nerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_SET) } } impl R { # [doc = "Bit 0 - Enable UARTOUT Receive Time-Out Interrupt."] # [inline (always)] pub fn int_event0_imask_rtout (& self) -> INT_EVENT0_IMASK_RTOUT_R { INT_EVENT0_IMASK_RTOUT_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - Enable UART Framing Error Interrupt."] # [inline (always)] pub fn int_event0_imask_frmerr (& self) -> INT_EVENT0_IMASK_FRMERR_R { INT_EVENT0_IMASK_FRMERR_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - Enable UART Parity Error Interrupt."] # [inline (always)] pub fn int_event0_imask_parerr (& self) -> INT_EVENT0_IMASK_PARERR_R { INT_EVENT0_IMASK_PARERR_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - Enable UART Break Error Interrupt."] # [inline (always)] pub fn int_event0_imask_brkerr (& self) -> INT_EVENT0_IMASK_BRKERR_R { INT_EVENT0_IMASK_BRKERR_R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - Enable UART Receive Overrun Error Interrupt."] # [inline (always)] pub fn int_event0_imask_ovrerr (& self) -> INT_EVENT0_IMASK_OVRERR_R { INT_EVENT0_IMASK_OVRERR_R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - Enable Negative Edge on UARTxRXD Interrupt."] # [inline (always)] pub fn int_event0_imask_rxne (& self) -> INT_EVENT0_IMASK_RXNE_R { INT_EVENT0_IMASK_RXNE_R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - Enable Positive Edge on UARTxRXD Interrupt."] # [inline (always)] pub fn int_event0_imask_rxpe (& self) -> INT_EVENT0_IMASK_RXPE_R { INT_EVENT0_IMASK_RXPE_R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - Enable LIN Capture 0 / Match Interrupt ."] # [inline (always)] pub fn int_event0_imask_linc0 (& self) -> INT_EVENT0_IMASK_LINC0_R { INT_EVENT0_IMASK_LINC0_R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - Enable LIN Capture 1 Interrupt."] # [inline (always)] pub fn int_event0_imask_linc1 (& self) -> INT_EVENT0_IMASK_LINC1_R { INT_EVENT0_IMASK_LINC1_R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - Enable LIN Hardware Counter Overflow Interrupt."] # [inline (always)] pub fn int_event0_imask_linovf (& self) -> INT_EVENT0_IMASK_LINOVF_R { INT_EVENT0_IMASK_LINOVF_R :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - Enable UART Receive Interrupt."] # [inline (always)] pub fn int_event0_imask_rxint (& self) -> INT_EVENT0_IMASK_RXINT_R { INT_EVENT0_IMASK_RXINT_R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - Enable UART Transmit Interrupt."] # [inline (always)] pub fn int_event0_imask_txint (& self) -> INT_EVENT0_IMASK_TXINT_R { INT_EVENT0_IMASK_TXINT_R :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] # [inline (always)] pub fn int_event0_imask_eot (& self) -> INT_EVENT0_IMASK_EOT_R { INT_EVENT0_IMASK_EOT_R :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - Enable Address Match Interrupt."] # [inline (always)] pub fn int_event0_imask_addr_match (& self) -> INT_EVENT0_IMASK_ADDR_MATCH_R { INT_EVENT0_IMASK_ADDR_MATCH_R :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 14 - Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] # [inline (always)] pub fn int_event0_imask_cts (& self) -> INT_EVENT0_IMASK_CTS_R { INT_EVENT0_IMASK_CTS_R :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - Enable DMA Done on RX Event Channel"] # [inline (always)] pub fn int_event0_imask_dma_done_rx (& self) -> INT_EVENT0_IMASK_DMA_DONE_RX_R { INT_EVENT0_IMASK_DMA_DONE_RX_R :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bit 16 - Enable DMA Done on TX Event Channel"] # [inline (always)] pub fn int_event0_imask_dma_done_tx (& self) -> INT_EVENT0_IMASK_DMA_DONE_TX_R { INT_EVENT0_IMASK_DMA_DONE_TX_R :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] # [inline (always)] pub fn int_event0_imask_nerr (& self) -> INT_EVENT0_IMASK_NERR_R { INT_EVENT0_IMASK_NERR_R :: new (((self . bits >> 17) & 1) != 0) } } impl W { # [doc = "Bit 0 - Enable UARTOUT Receive Time-Out Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_rtout (& mut self) -> INT_EVENT0_IMASK_RTOUT_W < INT_EVENT0_IMASK_SPEC , 0 > { INT_EVENT0_IMASK_RTOUT_W :: new (self) } # [doc = "Bit 1 - Enable UART Framing Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_frmerr (& mut self) -> INT_EVENT0_IMASK_FRMERR_W < INT_EVENT0_IMASK_SPEC , 1 > { INT_EVENT0_IMASK_FRMERR_W :: new (self) } # [doc = "Bit 2 - Enable UART Parity Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_parerr (& mut self) -> INT_EVENT0_IMASK_PARERR_W < INT_EVENT0_IMASK_SPEC , 2 > { INT_EVENT0_IMASK_PARERR_W :: new (self) } # [doc = "Bit 3 - Enable UART Break Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_brkerr (& mut self) -> INT_EVENT0_IMASK_BRKERR_W < INT_EVENT0_IMASK_SPEC , 3 > { INT_EVENT0_IMASK_BRKERR_W :: new (self) } # [doc = "Bit 4 - Enable UART Receive Overrun Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_ovrerr (& mut self) -> INT_EVENT0_IMASK_OVRERR_W < INT_EVENT0_IMASK_SPEC , 4 > { INT_EVENT0_IMASK_OVRERR_W :: new (self) } # [doc = "Bit 5 - Enable Negative Edge on UARTxRXD Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_rxne (& mut self) -> INT_EVENT0_IMASK_RXNE_W < INT_EVENT0_IMASK_SPEC , 5 > { INT_EVENT0_IMASK_RXNE_W :: new (self) } # [doc = "Bit 6 - Enable Positive Edge on UARTxRXD Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_rxpe (& mut self) -> INT_EVENT0_IMASK_RXPE_W < INT_EVENT0_IMASK_SPEC , 6 > { INT_EVENT0_IMASK_RXPE_W :: new (self) } # [doc = "Bit 7 - Enable LIN Capture 0 / Match Interrupt ."] # [inline (always)] # [must_use] pub fn int_event0_imask_linc0 (& mut self) -> INT_EVENT0_IMASK_LINC0_W < INT_EVENT0_IMASK_SPEC , 7 > { INT_EVENT0_IMASK_LINC0_W :: new (self) } # [doc = "Bit 8 - Enable LIN Capture 1 Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_linc1 (& mut self) -> INT_EVENT0_IMASK_LINC1_W < INT_EVENT0_IMASK_SPEC , 8 > { INT_EVENT0_IMASK_LINC1_W :: new (self) } # [doc = "Bit 9 - Enable LIN Hardware Counter Overflow Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_linovf (& mut self) -> INT_EVENT0_IMASK_LINOVF_W < INT_EVENT0_IMASK_SPEC , 9 > { INT_EVENT0_IMASK_LINOVF_W :: new (self) } # [doc = "Bit 10 - Enable UART Receive Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_rxint (& mut self) -> INT_EVENT0_IMASK_RXINT_W <'_,  INT_EVENT0_IMASK_SPEC , 10 > { INT_EVENT0_IMASK_RXINT_W :: new (self) } # [doc = "Bit 11 - Enable UART Transmit Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_txint (& mut self) -> INT_EVENT0_IMASK_TXINT_W < INT_EVENT0_IMASK_SPEC , 11 > { INT_EVENT0_IMASK_TXINT_W :: new (self) } # [doc = "Bit 12 - Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] # [inline (always)] # [must_use] pub fn int_event0_imask_eot (& mut self) -> INT_EVENT0_IMASK_EOT_W < INT_EVENT0_IMASK_SPEC , 12 > { INT_EVENT0_IMASK_EOT_W :: new (self) } # [doc = "Bit 13 - Enable Address Match Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_addr_match (& mut self) -> INT_EVENT0_IMASK_ADDR_MATCH_W < INT_EVENT0_IMASK_SPEC , 13 > { INT_EVENT0_IMASK_ADDR_MATCH_W :: new (self) } # [doc = "Bit 14 - Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] # [inline (always)] # [must_use] pub fn int_event0_imask_cts (& mut self) -> INT_EVENT0_IMASK_CTS_W < INT_EVENT0_IMASK_SPEC , 14 > { INT_EVENT0_IMASK_CTS_W :: new (self) } # [doc = "Bit 15 - Enable DMA Done on RX Event Channel"] # [inline (always)] # [must_use] pub fn int_event0_imask_dma_done_rx (& mut self) -> INT_EVENT0_IMASK_DMA_DONE_RX_W < INT_EVENT0_IMASK_SPEC , 15 > { INT_EVENT0_IMASK_DMA_DONE_RX_W :: new (self) } # [doc = "Bit 16 - Enable DMA Done on TX Event Channel"] # [inline (always)] # [must_use] pub fn int_event0_imask_dma_done_tx (& mut self) -> INT_EVENT0_IMASK_DMA_DONE_TX_W < INT_EVENT0_IMASK_SPEC , 16 > { INT_EVENT0_IMASK_DMA_DONE_TX_W :: new (self) } # [doc = "Bit 17 - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] # [inline (always)] # [must_use] pub fn int_event0_imask_nerr (& mut self) -> INT_EVENT0_IMASK_NERR_W < INT_EVENT0_IMASK_SPEC , 17 > { INT_EVENT0_IMASK_NERR_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Interrupt mask\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_event0_imask::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_event0_imask::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct INT_EVENT0_IMASK_SPEC ; impl crate :: RegisterSpec for INT_EVENT0_IMASK_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`int_event0_imask::R`](R) reader structure"] impl crate :: Readable for INT_EVENT0_IMASK_SPEC { } # [doc = "`write(|w| ..)` method takes [`int_event0_imask::W`](W) writer structure"] impl crate :: Writable for INT_EVENT0_IMASK_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets INT_EVENT0_IMASK to value 0"] impl crate :: Resettable for INT_EVENT0_IMASK_SPEC { const RESET_VALUE : Self :: Ux = 0 ; }
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                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                 +++
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing
[INFO] [stdout]  --> src/uart0/ctl0.rs:1:39503
[INFO] [stdout]   |
[INFO] [stdout] 1 | ...must_use] pub fn ctl0_txe (& mut self) -> CTL0_TXE_W < CTL0_SPEC , 4 > { CTL0_TXE_W :: new (self) } # [doc = "Bit 5 - TXD Pin Cont...
[INFO] [stdout]   |                               ^^^^^^^^^^     ^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here
[INFO] [stdout]   |                               |
[INFO] [stdout]   |                               the lifetime is elided here
[INFO] [stdout]   |
[INFO] [stdout]   = help: the same lifetime is referred to in inconsistent ways, making the signature confusing
[INFO] [stdout] help: use `'_` for type paths
[INFO] [stdout]   |
[INFO] [stdout] 1 | # [doc = "Register `CTL0` reader"] pub type R = crate :: R < CTL0_SPEC > ; # [doc = "Register `CTL0` writer"] pub type W = crate :: W < CTL0_SPEC > ; # [doc = "Field `CTL0_ENABLE` reader - UART Module Enable. If the UART is disabled in the middle of transmission or reception, it completes the current character before stopping. If the ENABLE bit is not set, all registers can still be accessed and updated. It is recommended to setup and change the UART operation mode with having the ENABLE bit cleared to avoid unpredictable behavior during the setup or update. If disabled the UART module will not send or receive any data and the logic is held in reset state."] pub type CTL0_ENABLE_R = crate :: BitReader < CTL0_ENABLE_A > ; # [doc = "UART Module Enable. If the UART is disabled in the middle of transmission or reception, it completes the current character before stopping. If the ENABLE bit is not set, all registers can still be accessed and updated. It is recommended to setup and change the UART operation mode with having the ENABLE bit cleared to avoid unpredictable behavior during the setup or update. If disabled the UART module will not send or receive any data and the logic is held in reset state.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CTL0_ENABLE_A { # [doc = "0: DISABLE"] CTL0_ENABLE_DISABLE = 0 , # [doc = "1: ENABLE"] CTL0_ENABLE_ENABLE = 1 , } impl From < CTL0_ENABLE_A > for bool { # [inline (always)] fn from (variant : CTL0_ENABLE_A) -> Self { variant as u8 != 0 } } impl CTL0_ENABLE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CTL0_ENABLE_A { match self . bits { false => CTL0_ENABLE_A :: CTL0_ENABLE_DISABLE , true => CTL0_ENABLE_A :: CTL0_ENABLE_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_ctl0_enable_disable (& self) -> bool { * self == CTL0_ENABLE_A :: CTL0_ENABLE_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_ctl0_enable_enable (& self) -> bool { * self == CTL0_ENABLE_A :: CTL0_ENABLE_ENABLE } } # [doc = "Field `CTL0_ENABLE` writer - UART Module Enable. If the UART is disabled in the middle of transmission or reception, it completes the current character before stopping. If the ENABLE bit is not set, all registers can still be accessed and updated. It is recommended to setup and change the UART operation mode with having the ENABLE bit cleared to avoid unpredictable behavior during the setup or update. If disabled the UART module will not send or receive any data and the logic is held in reset state."] pub type CTL0_ENABLE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL0_ENABLE_A > ; impl < 'a , REG , const O : u8 > CTL0_ENABLE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn ctl0_enable_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_ENABLE_A :: CTL0_ENABLE_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn ctl0_enable_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_ENABLE_A :: CTL0_ENABLE_ENABLE) } } # [doc = "Field `CTL0_LBE` reader - UART Loop Back Enable"] pub type CTL0_LBE_R = crate :: BitReader < CTL0_LBE_A > ; # [doc = "UART Loop Back Enable\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CTL0_LBE_A { # [doc = "0: DISABLE"] CTL0_LBE_DISABLE = 0 , # [doc = "1: ENABLE"] CTL0_LBE_ENABLE = 1 , } impl From < CTL0_LBE_A > for bool { # [inline (always)] fn from (variant : CTL0_LBE_A) -> Self { variant as u8 != 0 } } impl CTL0_LBE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CTL0_LBE_A { match self . bits { false => CTL0_LBE_A :: CTL0_LBE_DISABLE , true => CTL0_LBE_A :: CTL0_LBE_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_ctl0_lbe_disable (& self) -> bool { * self == CTL0_LBE_A :: CTL0_LBE_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_ctl0_lbe_enable (& self) -> bool { * self == CTL0_LBE_A :: CTL0_LBE_ENABLE } } # [doc = "Field `CTL0_LBE` writer - UART Loop Back Enable"] pub type CTL0_LBE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL0_LBE_A > ; impl < 'a , REG , const O : u8 > CTL0_LBE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn ctl0_lbe_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_LBE_A :: CTL0_LBE_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn ctl0_lbe_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_LBE_A :: CTL0_LBE_ENABLE) } } # [doc = "Field `CTL0_RXE` reader - UART Receive Enable If the UART is disabled in the middle of a receive, it completes the current character before stopping. #b#NOTE:#/b# To enable reception, the UARTEN bit must be set."] pub type CTL0_RXE_R = crate :: BitReader < CTL0_RXE_A > ; # [doc = "UART Receive Enable If the UART is disabled in the middle of a receive, it completes the current character before stopping. #b#NOTE:#/b# To enable reception, the UARTEN bit must be set.\n\nValue on reset: 1"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CTL0_RXE_A { # [doc = "0: DISABLE"] CTL0_RXE_DISABLE = 0 , # [doc = "1: ENABLE"] CTL0_RXE_ENABLE = 1 , } impl From < CTL0_RXE_A > for bool { # [inline (always)] fn from (variant : CTL0_RXE_A) -> Self { variant as u8 != 0 } } impl CTL0_RXE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CTL0_RXE_A { match self . bits { false => CTL0_RXE_A :: CTL0_RXE_DISABLE , true => CTL0_RXE_A :: CTL0_RXE_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_ctl0_rxe_disable (& self) -> bool { * self == CTL0_RXE_A :: CTL0_RXE_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_ctl0_rxe_enable (& self) -> bool { * self == CTL0_RXE_A :: CTL0_RXE_ENABLE } } # [doc = "Field `CTL0_RXE` writer - UART Receive Enable If the UART is disabled in the middle of a receive, it completes the current character before stopping. #b#NOTE:#/b# To enable reception, the UARTEN bit must be set."] pub type CTL0_RXE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL0_RXE_A > ; impl < 'a , REG , const O : u8 > CTL0_RXE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn ctl0_rxe_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_RXE_A :: CTL0_RXE_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn ctl0_rxe_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_RXE_A :: CTL0_RXE_ENABLE) } } # [doc = "Field `CTL0_TXE` reader - UART Transmit Enable If the UART is disabled in the middle of a transmission, it completes the current character before stopping. #b#NOTE:#/b# To enable transmission, the UARTEN bit must be set."] pub type CTL0_TXE_R = crate :: BitReader < CTL0_TXE_A > ; # [doc = "UART Transmit Enable If the UART is disabled in the middle of a transmission, it completes the current character before stopping. #b#NOTE:#/b# To enable transmission, the UARTEN bit must be set.\n\nValue on reset: 1"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CTL0_TXE_A { # [doc = "0: DISABLE"] CTL0_TXE_DISABLE = 0 , # [doc = "1: ENABLE"] CTL0_TXE_ENABLE = 1 , } impl From < CTL0_TXE_A > for bool { # [inline (always)] fn from (variant : CTL0_TXE_A) -> Self { variant as u8 != 0 } } impl CTL0_TXE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CTL0_TXE_A { match self . bits { false => CTL0_TXE_A :: CTL0_TXE_DISABLE , true => CTL0_TXE_A :: CTL0_TXE_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_ctl0_txe_disable (& self) -> bool { * self == CTL0_TXE_A :: CTL0_TXE_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_ctl0_txe_enable (& self) -> bool { * self == CTL0_TXE_A :: CTL0_TXE_ENABLE } } # [doc = "Field `CTL0_TXE` writer - UART Transmit Enable If the UART is disabled in the middle of a transmission, it completes the current character before stopping. #b#NOTE:#/b# To enable transmission, the UARTEN bit must be set."] pub type CTL0_TXE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL0_TXE_A > ; impl < 'a , REG , const O : u8 > CTL0_TXE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn ctl0_txe_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_TXE_A :: CTL0_TXE_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn ctl0_txe_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_TXE_A :: CTL0_TXE_ENABLE) } } # [doc = "Field `CTL0_TXD_OUT_EN` reader - TXD Pin Control Enable. When the transmit section of the UART is disabled (TXE = 0), the TXD pin can be controlled by the TXD_OUT bit. 1 = UARTxTXD pin can be controlled by TXD_OUT, if TXE = 0"] pub type CTL0_TXD_OUT_EN_R = crate :: BitReader < CTL0_TXD_OUT_EN_A > ; # [doc = "TXD Pin Control Enable. When the transmit section of the UART is disabled (TXE = 0), the TXD pin can be controlled by the TXD_OUT bit. 1 = UARTxTXD pin can be controlled by TXD_OUT, if TXE = 0\n\nValue on reset: 1"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CTL0_TXD_OUT_EN_A { # [doc = "0: DISABLE"] CTL0_TXD_OUT_EN_DISABLE = 0 , # [doc = "1: ENABLE"] CTL0_TXD_OUT_EN_ENABLE = 1 , } impl From < CTL0_TXD_OUT_EN_A > for bool { # [inline (always)] fn from (variant : CTL0_TXD_OUT_EN_A) -> Self { variant as u8 != 0 } } impl CTL0_TXD_OUT_EN_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CTL0_TXD_OUT_EN_A { match self . bits { false => CTL0_TXD_OUT_EN_A :: CTL0_TXD_OUT_EN_DISABLE , true => CTL0_TXD_OUT_EN_A :: CTL0_TXD_OUT_EN_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_ctl0_txd_out_en_disable (& self) -> bool { * self == CTL0_TXD_OUT_EN_A :: CTL0_TXD_OUT_EN_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_ctl0_txd_out_en_enable (& self) -> bool { * self == CTL0_TXD_OUT_EN_A :: CTL0_TXD_OUT_EN_ENABLE } } # [doc = "Field `CTL0_TXD_OUT_EN` writer - TXD Pin Control Enable. When the transmit section of the UART is disabled (TXE = 0), the TXD pin can be controlled by the TXD_OUT bit. 1 = UARTxTXD pin can be controlled by TXD_OUT, if TXE = 0"] pub type CTL0_TXD_OUT_EN_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL0_TXD_OUT_EN_A > ; impl < 'a , REG , const O : u8 > CTL0_TXD_OUT_EN_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn ctl0_txd_out_en_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_TXD_OUT_EN_A :: CTL0_TXD_OUT_EN_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn ctl0_txd_out_en_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_TXD_OUT_EN_A :: CTL0_TXD_OUT_EN_ENABLE) } } # [doc = "Field `CTL0_TXD_OUT` reader - TXD Pin Control Controls the TXD pin when TXD_OUT_EN = 1 and TXE = 0."] pub type CTL0_TXD_OUT_R = crate :: BitReader < CTL0_TXD_OUT_A > ; # [doc = "TXD Pin Control Controls the TXD pin when TXD_OUT_EN = 1 and TXE = 0.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CTL0_TXD_OUT_A { # [doc = "0: LOW"] CTL0_TXD_OUT_LOW = 0 , # [doc = "1: HIGH"] CTL0_TXD_OUT_HIGH = 1 , } impl From < CTL0_TXD_OUT_A > for bool { # [inline (always)] fn from (variant : CTL0_TXD_OUT_A) -> Self { variant as u8 != 0 } } impl CTL0_TXD_OUT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CTL0_TXD_OUT_A { match self . bits { false => CTL0_TXD_OUT_A :: CTL0_TXD_OUT_LOW , true => CTL0_TXD_OUT_A :: CTL0_TXD_OUT_HIGH , } } # [doc = "LOW"] # [inline (always)] pub fn is_ctl0_txd_out_low (& self) -> bool { * self == CTL0_TXD_OUT_A :: CTL0_TXD_OUT_LOW } # [doc = "HIGH"] # [inline (always)] pub fn is_ctl0_txd_out_high (& self) -> bool { * self == CTL0_TXD_OUT_A :: CTL0_TXD_OUT_HIGH } } # [doc = "Field `CTL0_TXD_OUT` writer - TXD Pin Control Controls the TXD pin when TXD_OUT_EN = 1 and TXE = 0."] pub type CTL0_TXD_OUT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL0_TXD_OUT_A > ; impl < 'a , REG , const O : u8 > CTL0_TXD_OUT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "LOW"] # [inline (always)] pub fn ctl0_txd_out_low (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_TXD_OUT_A :: CTL0_TXD_OUT_LOW) } # [doc = "HIGH"] # [inline (always)] pub fn ctl0_txd_out_high (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_TXD_OUT_A :: CTL0_TXD_OUT_HIGH) } } # [doc = "Field `CTL0_MENC` reader - Manchester Encode enable"] pub type CTL0_MENC_R = crate :: BitReader < CTL0_MENC_A > ; # [doc = "Manchester Encode enable\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CTL0_MENC_A { # [doc = "0: DISABLE"] CTL0_MENC_DISABLE = 0 , # [doc = "1: ENABLE"] CTL0_MENC_ENABLE = 1 , } impl From < CTL0_MENC_A > for bool { # [inline (always)] fn from (variant : CTL0_MENC_A) -> Self { variant as u8 != 0 } } impl CTL0_MENC_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CTL0_MENC_A { match self . bits { false => CTL0_MENC_A :: CTL0_MENC_DISABLE , true => CTL0_MENC_A :: CTL0_MENC_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_ctl0_menc_disable (& self) -> bool { * self == CTL0_MENC_A :: CTL0_MENC_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_ctl0_menc_enable (& self) -> bool { * self == CTL0_MENC_A :: CTL0_MENC_ENABLE } } # [doc = "Field `CTL0_MENC` writer - Manchester Encode enable"] pub type CTL0_MENC_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL0_MENC_A > ; impl < 'a , REG , const O : u8 > CTL0_MENC_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn ctl0_menc_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_MENC_A :: CTL0_MENC_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn ctl0_menc_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_MENC_A :: CTL0_MENC_ENABLE) } } # [doc = "Field `CTL0_MODE` reader - Set the communication mode and protocol used. (Not defined settings uses the default setting: 0)"] pub type CTL0_MODE_R = crate :: FieldReader < CTL0_MODE_A > ; # [doc = "Set the communication mode and protocol used. (Not defined settings uses the default setting: 0)\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum CTL0_MODE_A { # [doc = "0: UART"] CTL0_MODE_UART = 0 , # [doc = "1: RS485"] CTL0_MODE_RS485 = 1 , # [doc = "2: IDLELINE"] CTL0_MODE_IDLELINE = 2 , # [doc = "3: ADDR9BIT"] CTL0_MODE_ADDR9BIT = 3 , # [doc = "4: SMART"] CTL0_MODE_SMART = 4 , # [doc = "5: DALI"] CTL0_MODE_DALI = 5 , } impl From < CTL0_MODE_A > for u8 { # [inline (always)] fn from (variant : CTL0_MODE_A) -> Self { variant as _ } } impl crate :: FieldSpec for CTL0_MODE_A { type Ux = u8 ; } impl CTL0_MODE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < CTL0_MODE_A > { match self . bits { 0 => Some (CTL0_MODE_A :: CTL0_MODE_UART) , 1 => Some (CTL0_MODE_A :: CTL0_MODE_RS485) , 2 => Some (CTL0_MODE_A :: CTL0_MODE_IDLELINE) , 3 => Some (CTL0_MODE_A :: CTL0_MODE_ADDR9BIT) , 4 => Some (CTL0_MODE_A :: CTL0_MODE_SMART) , 5 => Some (CTL0_MODE_A :: CTL0_MODE_DALI) , _ => None , } } # [doc = "UART"] # [inline (always)] pub fn is_ctl0_mode_uart (& self) -> bool { * self == CTL0_MODE_A :: CTL0_MODE_UART } # [doc = "RS485"] # [inline (always)] pub fn is_ctl0_mode_rs485 (& self) -> bool { * self == CTL0_MODE_A :: CTL0_MODE_RS485 } # [doc = "IDLELINE"] # [inline (always)] pub fn is_ctl0_mode_idleline (& self) -> bool { * self == CTL0_MODE_A :: CTL0_MODE_IDLELINE } # [doc = "ADDR9BIT"] # [inline (always)] pub fn is_ctl0_mode_addr9bit (& self) -> bool { * self == CTL0_MODE_A :: CTL0_MODE_ADDR9BIT } # [doc = "SMART"] # [inline (always)] pub fn is_ctl0_mode_smart (& self) -> bool { * self == CTL0_MODE_A :: CTL0_MODE_SMART } # [doc = "DALI"] # [inline (always)] pub fn is_ctl0_mode_dali (& self) -> bool { * self == CTL0_MODE_A :: CTL0_MODE_DALI } } # [doc = "Field `CTL0_MODE` writer - Set the communication mode and protocol used. (Not defined settings uses the default setting: 0)"] pub type CTL0_MODE_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 3 , O , CTL0_MODE_A > ; impl < 'a , REG , const O : u8 > CTL0_MODE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "UART"] # [inline (always)] pub fn ctl0_mode_uart (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_MODE_A :: CTL0_MODE_UART) } # [doc = "RS485"] # [inline (always)] pub fn ctl0_mode_rs485 (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_MODE_A :: CTL0_MODE_RS485) } # [doc = "IDLELINE"] # [inline (always)] pub fn ctl0_mode_idleline (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_MODE_A :: CTL0_MODE_IDLELINE) } # [doc = "ADDR9BIT"] # [inline (always)] pub fn ctl0_mode_addr9bit (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_MODE_A :: CTL0_MODE_ADDR9BIT) } # [doc = "SMART"] # [inline (always)] pub fn ctl0_mode_smart (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_MODE_A :: CTL0_MODE_SMART) } # [doc = "DALI"] # [inline (always)] pub fn ctl0_mode_dali (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_MODE_A :: CTL0_MODE_DALI) } } # [doc = "Field `CTL0_RTS` reader - Request to Send If RTSEN is set the RTS output signals is controlled by the hardware logic using the FIFO fill level or TXDATA buffer. If RTSEN is cleared the RTS output is controlled by the RTS bit. The bit is the complement of the UART request to send, RTS modem status output."] pub type CTL0_RTS_R = crate :: BitReader < CTL0_RTS_A > ; # [doc = "Request to Send If RTSEN is set the RTS output signals is controlled by the hardware logic using the FIFO fill level or TXDATA buffer. If RTSEN is cleared the RTS output is controlled by the RTS bit. The bit is the complement of the UART request to send, RTS modem status output.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CTL0_RTS_A { # [doc = "0: CLR"] CTL0_RTS_CLR = 0 , # [doc = "1: SET"] CTL0_RTS_SET = 1 , } impl From < CTL0_RTS_A > for bool { # [inline (always)] fn from (variant : CTL0_RTS_A) -> Self { variant as u8 != 0 } } impl CTL0_RTS_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CTL0_RTS_A { match self . bits { false => CTL0_RTS_A :: CTL0_RTS_CLR , true => CTL0_RTS_A :: CTL0_RTS_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_ctl0_rts_clr (& self) -> bool { * self == CTL0_RTS_A :: CTL0_RTS_CLR } # [doc = "SET"] # [inline (always)] pub fn is_ctl0_rts_set (& self) -> bool { * self == CTL0_RTS_A :: CTL0_RTS_SET } } # [doc = "Field `CTL0_RTS` writer - Request to Send If RTSEN is set the RTS output signals is controlled by the hardware logic using the FIFO fill level or TXDATA buffer. If RTSEN is cleared the RTS output is controlled by the RTS bit. The bit is the complement of the UART request to send, RTS modem status output."] pub type CTL0_RTS_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL0_RTS_A > ; impl < 'a , REG , const O : u8 > CTL0_RTS_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn ctl0_rts_clr (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_RTS_A :: CTL0_RTS_CLR) } # [doc = "SET"] # [inline (always)] pub fn ctl0_rts_set (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_RTS_A :: CTL0_RTS_SET) } } # [doc = "Field `CTL0_RTSEN` reader - Enable hardware controlled Request to Send"] pub type CTL0_RTSEN_R = crate :: BitReader < CTL0_RTSEN_A > ; # [doc = "Enable hardware controlled Request to Send\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CTL0_RTSEN_A { # [doc = "0: DISABLE"] CTL0_RTSEN_DISABLE = 0 , # [doc = "1: ENABLE"] CTL0_RTSEN_ENABLE = 1 , } impl From < CTL0_RTSEN_A > for bool { # [inline (always)] fn from (variant : CTL0_RTSEN_A) -> Self { variant as u8 != 0 } } impl CTL0_RTSEN_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CTL0_RTSEN_A { match self . bits { false => CTL0_RTSEN_A :: CTL0_RTSEN_DISABLE , true => CTL0_RTSEN_A :: CTL0_RTSEN_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_ctl0_rtsen_disable (& self) -> bool { * self == CTL0_RTSEN_A :: CTL0_RTSEN_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_ctl0_rtsen_enable (& self) -> bool { * self == CTL0_RTSEN_A :: CTL0_RTSEN_ENABLE } } # [doc = "Field `CTL0_RTSEN` writer - Enable hardware controlled Request to Send"] pub type CTL0_RTSEN_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL0_RTSEN_A > ; impl < 'a , REG , const O : u8 > CTL0_RTSEN_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn ctl0_rtsen_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_RTSEN_A :: CTL0_RTSEN_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn ctl0_rtsen_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_RTSEN_A :: CTL0_RTSEN_ENABLE) } } # [doc = "Field `CTL0_CTSEN` reader - Enable Clear To Send"] pub type CTL0_CTSEN_R = crate :: BitReader < CTL0_CTSEN_A > ; # [doc = "Enable Clear To Send\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CTL0_CTSEN_A { # [doc = "0: DISABLE"] CTL0_CTSEN_DISABLE = 0 , # [doc = "1: ENABLE"] CTL0_CTSEN_ENABLE = 1 , } impl From < CTL0_CTSEN_A > for bool { # [inline (always)] fn from (variant : CTL0_CTSEN_A) -> Self { variant as u8 != 0 } } impl CTL0_CTSEN_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CTL0_CTSEN_A { match self . bits { false => CTL0_CTSEN_A :: CTL0_CTSEN_DISABLE , true => CTL0_CTSEN_A :: CTL0_CTSEN_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_ctl0_ctsen_disable (& self) -> bool { * self == CTL0_CTSEN_A :: CTL0_CTSEN_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_ctl0_ctsen_enable (& self) -> bool { * self == CTL0_CTSEN_A :: CTL0_CTSEN_ENABLE } } # [doc = "Field `CTL0_CTSEN` writer - Enable Clear To Send"] pub type CTL0_CTSEN_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL0_CTSEN_A > ; impl < 'a , REG , const O : u8 > CTL0_CTSEN_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn ctl0_ctsen_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_CTSEN_A :: CTL0_CTSEN_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn ctl0_ctsen_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_CTSEN_A :: CTL0_CTSEN_ENABLE) } } # [doc = "Field `CTL0_HSE` reader - High-Speed Bit Oversampling Enable #b#NOTE:#/b# The bit oversampling influences the UART baud-rate configuration (see and ). The state of this bit has no effect on clock generation in ISO7816 smart card mode (the SMART bit is set)."] pub type CTL0_HSE_R = crate :: FieldReader < CTL0_HSE_A > ; # [doc = "High-Speed Bit Oversampling Enable #b#NOTE:#/b# The bit oversampling influences the UART baud-rate configuration (see and ). The state of this bit has no effect on clock generation in ISO7816 smart card mode (the SMART bit is set).\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum CTL0_HSE_A { # [doc = "0: OVS16"] CTL0_HSE_OVS16 = 0 , # [doc = "1: OVS8"] CTL0_HSE_OVS8 = 1 , # [doc = "2: OVS3"] CTL0_HSE_OVS3 = 2 , } impl From < CTL0_HSE_A > for u8 { # [inline (always)] fn from (variant : CTL0_HSE_A) -> Self { variant as _ } } impl crate :: FieldSpec for CTL0_HSE_A { type Ux = u8 ; } impl CTL0_HSE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < CTL0_HSE_A > { match self . bits { 0 => Some (CTL0_HSE_A :: CTL0_HSE_OVS16) , 1 => Some (CTL0_HSE_A :: CTL0_HSE_OVS8) , 2 => Some (CTL0_HSE_A :: CTL0_HSE_OVS3) , _ => None , } } # [doc = "OVS16"] # [inline (always)] pub fn is_ctl0_hse_ovs16 (& self) -> bool { * self == CTL0_HSE_A :: CTL0_HSE_OVS16 } # [doc = "OVS8"] # [inline (always)] pub fn is_ctl0_hse_ovs8 (& self) -> bool { * self == CTL0_HSE_A :: CTL0_HSE_OVS8 } # [doc = "OVS3"] # [inline (always)] pub fn is_ctl0_hse_ovs3 (& self) -> bool { * self == CTL0_HSE_A :: CTL0_HSE_OVS3 } } # [doc = "Field `CTL0_HSE` writer - High-Speed Bit Oversampling Enable #b#NOTE:#/b# The bit oversampling influences the UART baud-rate configuration (see and ). The state of this bit has no effect on clock generation in ISO7816 smart card mode (the SMART bit is set)."] pub type CTL0_HSE_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 2 , O , CTL0_HSE_A > ; impl < 'a , REG , const O : u8 > CTL0_HSE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "OVS16"] # [inline (always)] pub fn ctl0_hse_ovs16 (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_HSE_A :: CTL0_HSE_OVS16) } # [doc = "OVS8"] # [inline (always)] pub fn ctl0_hse_ovs8 (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_HSE_A :: CTL0_HSE_OVS8) } # [doc = "OVS3"] # [inline (always)] pub fn ctl0_hse_ovs3 (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_HSE_A :: CTL0_HSE_OVS3) } } # [doc = "Field `CTL0_FEN` reader - UART Enable FIFOs"] pub type CTL0_FEN_R = crate :: BitReader < CTL0_FEN_A > ; # [doc = "UART Enable FIFOs\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CTL0_FEN_A { # [doc = "0: DISABLE"] CTL0_FEN_DISABLE = 0 , # [doc = "1: ENABLE"] CTL0_FEN_ENABLE = 1 , } impl From < CTL0_FEN_A > for bool { # [inline (always)] fn from (variant : CTL0_FEN_A) -> Self { variant as u8 != 0 } } impl CTL0_FEN_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CTL0_FEN_A { match self . bits { false => CTL0_FEN_A :: CTL0_FEN_DISABLE , true => CTL0_FEN_A :: CTL0_FEN_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_ctl0_fen_disable (& self) -> bool { * self == CTL0_FEN_A :: CTL0_FEN_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_ctl0_fen_enable (& self) -> bool { * self == CTL0_FEN_A :: CTL0_FEN_ENABLE } } # [doc = "Field `CTL0_FEN` writer - UART Enable FIFOs"] pub type CTL0_FEN_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL0_FEN_A > ; impl < 'a , REG , const O : u8 > CTL0_FEN_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn ctl0_fen_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_FEN_A :: CTL0_FEN_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn ctl0_fen_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_FEN_A :: CTL0_FEN_ENABLE) } } # [doc = "Field `CTL0_MAJVOTE` reader - When enabled with oversmapling of 16, samples samples 7, 8, and 9 are majority voted to decide the sampled bit value. The value correspond to al least 2 of the 3 samples is considered to be the received value. In case the 3 values do not match, RIS.NERR bit is set along with RDR.NERR When enabled with oversmapling of 8, samples samples 3, 4, and 5 are majority voted to decide the sampled bit value. The value correspond to al least 2 of the 3 samples is considered to be the received value. In case the 3 values donot match, RIS.NERR bit is set along with RDR.NERR When disabled, only a single sample of received bit is taken."] pub type CTL0_MAJVOTE_R = crate :: BitReader < CTL0_MAJVOTE_A > ; # [doc = "When enabled with oversmapling of 16, samples samples 7, 8, and 9 are majority voted to decide the sampled bit value. The value correspond to al least 2 of the 3 samples is considered to be the received value. In case the 3 values do not match, RIS.NERR bit is set along with RDR.NERR When enabled with oversmapling of 8, samples samples 3, 4, and 5 are majority voted to decide the sampled bit value. The value correspond to al least 2 of the 3 samples is considered to be the received value. In case the 3 values donot match, RIS.NERR bit is set along with RDR.NERR When disabled, only a single sample of received bit is taken.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CTL0_MAJVOTE_A { # [doc = "0: DISABLE"] CTL0_MAJVOTE_DISABLE = 0 , # [doc = "1: ENABLE"] CTL0_MAJVOTE_ENABLE = 1 , } impl From < CTL0_MAJVOTE_A > for bool { # [inline (always)] fn from (variant : CTL0_MAJVOTE_A) -> Self { variant as u8 != 0 } } impl CTL0_MAJVOTE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CTL0_MAJVOTE_A { match self . bits { false => CTL0_MAJVOTE_A :: CTL0_MAJVOTE_DISABLE , true => CTL0_MAJVOTE_A :: CTL0_MAJVOTE_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_ctl0_majvote_disable (& self) -> bool { * self == CTL0_MAJVOTE_A :: CTL0_MAJVOTE_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_ctl0_majvote_enable (& self) -> bool { * self == CTL0_MAJVOTE_A :: CTL0_MAJVOTE_ENABLE } } # [doc = "Field `CTL0_MAJVOTE` writer - When enabled with oversmapling of 16, samples samples 7, 8, and 9 are majority voted to decide the sampled bit value. The value correspond to al least 2 of the 3 samples is considered to be the received value. In case the 3 values do not match, RIS.NERR bit is set along with RDR.NERR When enabled with oversmapling of 8, samples samples 3, 4, and 5 are majority voted to decide the sampled bit value. The value correspond to al least 2 of the 3 samples is considered to be the received value. In case the 3 values donot match, RIS.NERR bit is set along with RDR.NERR When disabled, only a single sample of received bit is taken."] pub type CTL0_MAJVOTE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL0_MAJVOTE_A > ; impl < 'a , REG , const O : u8 > CTL0_MAJVOTE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn ctl0_majvote_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_MAJVOTE_A :: CTL0_MAJVOTE_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn ctl0_majvote_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_MAJVOTE_A :: CTL0_MAJVOTE_ENABLE) } } # [doc = "Field `CTL0_MSBFIRST` reader - Most Significant Bit First This bit has effect both on the way protocol byte is transmitted and received. Notes: User needs to match the protocol to the correct value of this bit to send MSb or LSb first. The hardware engine will send the byte entirely based on this bit."] pub type CTL0_MSBFIRST_R = crate :: BitReader < CTL0_MSBFIRST_A > ; # [doc = "Most Significant Bit First This bit has effect both on the way protocol byte is transmitted and received. Notes: User needs to match the protocol to the correct value of this bit to send MSb or LSb first. The hardware engine will send the byte entirely based on this bit.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CTL0_MSBFIRST_A { # [doc = "0: DISABLE"] CTL0_MSBFIRST_DISABLE = 0 , # [doc = "1: ENABLE"] CTL0_MSBFIRST_ENABLE = 1 , } impl From < CTL0_MSBFIRST_A > for bool { # [inline (always)] fn from (variant : CTL0_MSBFIRST_A) -> Self { variant as u8 != 0 } } impl CTL0_MSBFIRST_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CTL0_MSBFIRST_A { match self . bits { false => CTL0_MSBFIRST_A :: CTL0_MSBFIRST_DISABLE , true => CTL0_MSBFIRST_A :: CTL0_MSBFIRST_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_ctl0_msbfirst_disable (& self) -> bool { * self == CTL0_MSBFIRST_A :: CTL0_MSBFIRST_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_ctl0_msbfirst_enable (& self) -> bool { * self == CTL0_MSBFIRST_A :: CTL0_MSBFIRST_ENABLE } } # [doc = "Field `CTL0_MSBFIRST` writer - Most Significant Bit First This bit has effect both on the way protocol byte is transmitted and received. Notes: User needs to match the protocol to the correct value of this bit to send MSb or LSb first. The hardware engine will send the byte entirely based on this bit."] pub type CTL0_MSBFIRST_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL0_MSBFIRST_A > ; impl < 'a , REG , const O : u8 > CTL0_MSBFIRST_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn ctl0_msbfirst_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_MSBFIRST_A :: CTL0_MSBFIRST_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn ctl0_msbfirst_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_MSBFIRST_A :: CTL0_MSBFIRST_ENABLE) } } impl R { # [doc = "Bit 0 - UART Module Enable. If the UART is disabled in the middle of transmission or reception, it completes the current character before stopping. If the ENABLE bit is not set, all registers can still be accessed and updated. It is recommended to setup and change the UART operation mode with having the ENABLE bit cleared to avoid unpredictable behavior during the setup or update. If disabled the UART module will not send or receive any data and the logic is held in reset state."] # [inline (always)] pub fn ctl0_enable (& self) -> CTL0_ENABLE_R { CTL0_ENABLE_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 2 - UART Loop Back Enable"] # [inline (always)] pub fn ctl0_lbe (& self) -> CTL0_LBE_R { CTL0_LBE_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - UART Receive Enable If the UART is disabled in the middle of a receive, it completes the current character before stopping. #b#NOTE:#/b# To enable reception, the UARTEN bit must be set."] # [inline (always)] pub fn ctl0_rxe (& self) -> CTL0_RXE_R { CTL0_RXE_R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - UART Transmit Enable If the UART is disabled in the middle of a transmission, it completes the current character before stopping. #b#NOTE:#/b# To enable transmission, the UARTEN bit must be set."] # [inline (always)] pub fn ctl0_txe (& self) -> CTL0_TXE_R { CTL0_TXE_R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - TXD Pin Control Enable. When the transmit section of the UART is disabled (TXE = 0), the TXD pin can be controlled by the TXD_OUT bit. 1 = UARTxTXD pin can be controlled by TXD_OUT, if TXE = 0"] # [inline (always)] pub fn ctl0_txd_out_en (& self) -> CTL0_TXD_OUT_EN_R { CTL0_TXD_OUT_EN_R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - TXD Pin Control Controls the TXD pin when TXD_OUT_EN = 1 and TXE = 0."] # [inline (always)] pub fn ctl0_txd_out (& self) -> CTL0_TXD_OUT_R { CTL0_TXD_OUT_R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - Manchester Encode enable"] # [inline (always)] pub fn ctl0_menc (& self) -> CTL0_MENC_R { CTL0_MENC_R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bits 8:10 - Set the communication mode and protocol used. (Not defined settings uses the default setting: 0)"] # [inline (always)] pub fn ctl0_mode (& self) -> CTL0_MODE_R { CTL0_MODE_R :: new (((self . bits >> 8) & 7) as u8) } # [doc = "Bit 12 - Request to Send If RTSEN is set the RTS output signals is controlled by the hardware logic using the FIFO fill level or TXDATA buffer. If RTSEN is cleared the RTS output is controlled by the RTS bit. The bit is the complement of the UART request to send, RTS modem status output."] # [inline (always)] pub fn ctl0_rts (& self) -> CTL0_RTS_R { CTL0_RTS_R :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - Enable hardware controlled Request to Send"] # [inline (always)] pub fn ctl0_rtsen (& self) -> CTL0_RTSEN_R { CTL0_RTSEN_R :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 14 - Enable Clear To Send"] # [inline (always)] pub fn ctl0_ctsen (& self) -> CTL0_CTSEN_R { CTL0_CTSEN_R :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bits 15:16 - High-Speed Bit Oversampling Enable #b#NOTE:#/b# The bit oversampling influences the UART baud-rate configuration (see and ). The state of this bit has no effect on clock generation in ISO7816 smart card mode (the SMART bit is set)."] # [inline (always)] pub fn ctl0_hse (& self) -> CTL0_HSE_R { CTL0_HSE_R :: new (((self . bits >> 15) & 3) as u8) } # [doc = "Bit 17 - UART Enable FIFOs"] # [inline (always)] pub fn ctl0_fen (& self) -> CTL0_FEN_R { CTL0_FEN_R :: new (((self . bits >> 17) & 1) != 0) } # [doc = "Bit 18 - When enabled with oversmapling of 16, samples samples 7, 8, and 9 are majority voted to decide the sampled bit value. The value correspond to al least 2 of the 3 samples is considered to be the received value. In case the 3 values do not match, RIS.NERR bit is set along with RDR.NERR When enabled with oversmapling of 8, samples samples 3, 4, and 5 are majority voted to decide the sampled bit value. The value correspond to al least 2 of the 3 samples is considered to be the received value. In case the 3 values donot match, RIS.NERR bit is set along with RDR.NERR When disabled, only a single sample of received bit is taken."] # [inline (always)] pub fn ctl0_majvote (& self) -> CTL0_MAJVOTE_R { CTL0_MAJVOTE_R :: new (((self . bits >> 18) & 1) != 0) } # [doc = "Bit 19 - Most Significant Bit First This bit has effect both on the way protocol byte is transmitted and received. Notes: User needs to match the protocol to the correct value of this bit to send MSb or LSb first. The hardware engine will send the byte entirely based on this bit."] # [inline (always)] pub fn ctl0_msbfirst (& self) -> CTL0_MSBFIRST_R { CTL0_MSBFIRST_R :: new (((self . bits >> 19) & 1) != 0) } } impl W { # [doc = "Bit 0 - UART Module Enable. If the UART is disabled in the middle of transmission or reception, it completes the current character before stopping. If the ENABLE bit is not set, all registers can still be accessed and updated. It is recommended to setup and change the UART operation mode with having the ENABLE bit cleared to avoid unpredictable behavior during the setup or update. If disabled the UART module will not send or receive any data and the logic is held in reset state."] # [inline (always)] # [must_use] pub fn ctl0_enable (& mut self) -> CTL0_ENABLE_W < CTL0_SPEC , 0 > { CTL0_ENABLE_W :: new (self) } # [doc = "Bit 2 - UART Loop Back Enable"] # [inline (always)] # [must_use] pub fn ctl0_lbe (& mut self) -> CTL0_LBE_W < CTL0_SPEC , 2 > { CTL0_LBE_W :: new (self) } # [doc = "Bit 3 - UART Receive Enable If the UART is disabled in the middle of a receive, it completes the current character before stopping. #b#NOTE:#/b# To enable reception, the UARTEN bit must be set."] # [inline (always)] # [must_use] pub fn ctl0_rxe (& mut self) -> CTL0_RXE_W < CTL0_SPEC , 3 > { CTL0_RXE_W :: new (self) } # [doc = "Bit 4 - UART Transmit Enable If the UART is disabled in the middle of a transmission, it completes the current character before stopping. #b#NOTE:#/b# To enable transmission, the UARTEN bit must be set."] # [inline (always)] # [must_use] pub fn ctl0_txe (& mut self) -> CTL0_TXE_W <'_,  CTL0_SPEC , 4 > { CTL0_TXE_W :: new (self) } # [doc = "Bit 5 - TXD Pin Control Enable. When the transmit section of the UART is disabled (TXE = 0), the TXD pin can be controlled by the TXD_OUT bit. 1 = UARTxTXD pin can be controlled by TXD_OUT, if TXE = 0"] # [inline (always)] # [must_use] pub fn ctl0_txd_out_en (& mut self) -> CTL0_TXD_OUT_EN_W < CTL0_SPEC , 5 > { CTL0_TXD_OUT_EN_W :: new (self) } # [doc = "Bit 6 - TXD Pin Control Controls the TXD pin when TXD_OUT_EN = 1 and TXE = 0."] # [inline (always)] # [must_use] pub fn ctl0_txd_out (& mut self) -> CTL0_TXD_OUT_W < CTL0_SPEC , 6 > { CTL0_TXD_OUT_W :: new (self) } # [doc = "Bit 7 - Manchester Encode enable"] # [inline (always)] # [must_use] pub fn ctl0_menc (& mut self) -> CTL0_MENC_W < CTL0_SPEC , 7 > { CTL0_MENC_W :: new (self) } # [doc = "Bits 8:10 - Set the communication mode and protocol used. (Not defined settings uses the default setting: 0)"] # [inline (always)] # [must_use] pub fn ctl0_mode (& mut self) -> CTL0_MODE_W < CTL0_SPEC , 8 > { CTL0_MODE_W :: new (self) } # [doc = "Bit 12 - Request to Send If RTSEN is set the RTS output signals is controlled by the hardware logic using the FIFO fill level or TXDATA buffer. If RTSEN is cleared the RTS output is controlled by the RTS bit. The bit is the complement of the UART request to send, RTS modem status output."] # [inline (always)] # [must_use] pub fn ctl0_rts (& mut self) -> CTL0_RTS_W < CTL0_SPEC , 12 > { CTL0_RTS_W :: new (self) } # [doc = "Bit 13 - Enable hardware controlled Request to Send"] # [inline (always)] # [must_use] pub fn ctl0_rtsen (& mut self) -> CTL0_RTSEN_W < CTL0_SPEC , 13 > { CTL0_RTSEN_W :: new (self) } # [doc = "Bit 14 - Enable Clear To Send"] # [inline (always)] # [must_use] pub fn ctl0_ctsen (& mut self) -> CTL0_CTSEN_W < CTL0_SPEC , 14 > { CTL0_CTSEN_W :: new (self) } # [doc = "Bits 15:16 - High-Speed Bit Oversampling Enable #b#NOTE:#/b# The bit oversampling influences the UART baud-rate configuration (see and ). The state of this bit has no effect on clock generation in ISO7816 smart card mode (the SMART bit is set)."] # [inline (always)] # [must_use] pub fn ctl0_hse (& mut self) -> CTL0_HSE_W < CTL0_SPEC , 15 > { CTL0_HSE_W :: new (self) } # [doc = "Bit 17 - UART Enable FIFOs"] # [inline (always)] # [must_use] pub fn ctl0_fen (& mut self) -> CTL0_FEN_W < CTL0_SPEC , 17 > { CTL0_FEN_W :: new (self) } # [doc = "Bit 18 - When enabled with oversmapling of 16, samples samples 7, 8, and 9 are majority voted to decide the sampled bit value. The value correspond to al least 2 of the 3 samples is considered to be the received value. In case the 3 values do not match, RIS.NERR bit is set along with RDR.NERR When enabled with oversmapling of 8, samples samples 3, 4, and 5 are majority voted to decide the sampled bit value. The value correspond to al least 2 of the 3 samples is considered to be the received value. In case the 3 values donot match, RIS.NERR bit is set along with RDR.NERR When disabled, only a single sample of received bit is taken."] # [inline (always)] # [must_use] pub fn ctl0_majvote (& mut self) -> CTL0_MAJVOTE_W < CTL0_SPEC , 18 > { CTL0_MAJVOTE_W :: new (self) } # [doc = "Bit 19 - Most Significant Bit First This bit has effect both on the way protocol byte is transmitted and received. Notes: User needs to match the protocol to the correct value of this bit to send MSb or LSb first. The hardware engine will send the byte entirely based on this bit."] # [inline (always)] # [must_use] pub fn ctl0_msbfirst (& mut self) -> CTL0_MSBFIRST_W < CTL0_SPEC , 19 > { CTL0_MSBFIRST_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "UART Control Register 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctl0::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctl0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CTL0_SPEC ; impl crate :: RegisterSpec for CTL0_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`ctl0::R`](R) reader structure"] impl crate :: Readable for CTL0_SPEC { } # [doc = "`write(|w| ..)` method takes [`ctl0::W`](W) writer structure"] impl crate :: Writable for CTL0_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets CTL0 to value 0x38"] impl crate :: Resettable for CTL0_SPEC { const RESET_VALUE : Self :: Ux = 0x38 ; }
[INFO] [stdout]   |                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                          +++
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing
[INFO] [stdout]  --> src/uart0/int_event0_imask.rs:1:43102
[INFO] [stdout]   |
[INFO] [stdout] 1 | ...imask_txint (& mut self) -> INT_EVENT0_IMASK_TXINT_W < INT_EVENT0_IMASK_SPEC , 11 > { INT_EVENT0_IMASK_TXINT_W :: new (self) } # [...
[INFO] [stdout]   |                 ^^^^^^^^^^     ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here
[INFO] [stdout]   |                 |
[INFO] [stdout]   |                 the lifetime is elided here
[INFO] [stdout]   |
[INFO] [stdout]   = help: the same lifetime is referred to in inconsistent ways, making the signature confusing
[INFO] [stdout] help: use `'_` for type paths
[INFO] [stdout]   |
[INFO] [stdout] 1 | # [doc = "Register `INT_EVENT0_IMASK` reader"] pub type R = crate :: R < INT_EVENT0_IMASK_SPEC > ; # [doc = "Register `INT_EVENT0_IMASK` writer"] pub type W = crate :: W < INT_EVENT0_IMASK_SPEC > ; # [doc = "Field `INT_EVENT0_IMASK_RTOUT` reader - Enable UARTOUT Receive Time-Out Interrupt."] pub type INT_EVENT0_IMASK_RTOUT_R = crate :: BitReader < INT_EVENT0_IMASK_RTOUT_A > ; # [doc = "Enable UARTOUT Receive Time-Out Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_RTOUT_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_RTOUT_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_RTOUT_SET = 1 , } impl From < INT_EVENT0_IMASK_RTOUT_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_RTOUT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_RTOUT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_RTOUT_A { match self . bits { false => INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_CLR , true => INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_rtout_clr (& self) -> bool { * self == INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_rtout_set (& self) -> bool { * self == INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_SET } } # [doc = "Field `INT_EVENT0_IMASK_RTOUT` writer - Enable UARTOUT Receive Time-Out Interrupt."] pub type INT_EVENT0_IMASK_RTOUT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_RTOUT_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_RTOUT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_rtout_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_rtout_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_SET) } } # [doc = "Field `INT_EVENT0_IMASK_FRMERR` reader - Enable UART Framing Error Interrupt."] pub type INT_EVENT0_IMASK_FRMERR_R = crate :: BitReader < INT_EVENT0_IMASK_FRMERR_A > ; # [doc = "Enable UART Framing Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_FRMERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_FRMERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_FRMERR_SET = 1 , } impl From < INT_EVENT0_IMASK_FRMERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_FRMERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_FRMERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_FRMERR_A { match self . bits { false => INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_CLR , true => INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_frmerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_frmerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_FRMERR` writer - Enable UART Framing Error Interrupt."] pub type INT_EVENT0_IMASK_FRMERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_FRMERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_FRMERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_frmerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_frmerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_SET) } } # [doc = "Field `INT_EVENT0_IMASK_PARERR` reader - Enable UART Parity Error Interrupt."] pub type INT_EVENT0_IMASK_PARERR_R = crate :: BitReader < INT_EVENT0_IMASK_PARERR_A > ; # [doc = "Enable UART Parity Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_PARERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_PARERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_PARERR_SET = 1 , } impl From < INT_EVENT0_IMASK_PARERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_PARERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_PARERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_PARERR_A { match self . bits { false => INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_CLR , true => INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_parerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_parerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_PARERR` writer - Enable UART Parity Error Interrupt."] pub type INT_EVENT0_IMASK_PARERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_PARERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_PARERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_parerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_parerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_SET) } } # [doc = "Field `INT_EVENT0_IMASK_BRKERR` reader - Enable UART Break Error Interrupt."] pub type INT_EVENT0_IMASK_BRKERR_R = crate :: BitReader < INT_EVENT0_IMASK_BRKERR_A > ; # [doc = "Enable UART Break Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_BRKERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_BRKERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_BRKERR_SET = 1 , } impl From < INT_EVENT0_IMASK_BRKERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_BRKERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_BRKERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_BRKERR_A { match self . bits { false => INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_CLR , true => INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_brkerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_brkerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_BRKERR` writer - Enable UART Break Error Interrupt."] pub type INT_EVENT0_IMASK_BRKERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_BRKERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_BRKERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_brkerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_brkerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_SET) } } # [doc = "Field `INT_EVENT0_IMASK_OVRERR` reader - Enable UART Receive Overrun Error Interrupt."] pub type INT_EVENT0_IMASK_OVRERR_R = crate :: BitReader < INT_EVENT0_IMASK_OVRERR_A > ; # [doc = "Enable UART Receive Overrun Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_OVRERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_OVRERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_OVRERR_SET = 1 , } impl From < INT_EVENT0_IMASK_OVRERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_OVRERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_OVRERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_OVRERR_A { match self . bits { false => INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_CLR , true => INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_ovrerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_ovrerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_OVRERR` writer - Enable UART Receive Overrun Error Interrupt."] pub type INT_EVENT0_IMASK_OVRERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_OVRERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_OVRERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_ovrerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_ovrerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_SET) } } # [doc = "Field `INT_EVENT0_IMASK_RXNE` reader - Enable Negative Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_IMASK_RXNE_R = crate :: BitReader < INT_EVENT0_IMASK_RXNE_A > ; # [doc = "Enable Negative Edge on UARTxRXD Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_RXNE_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_RXNE_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_RXNE_SET = 1 , } impl From < INT_EVENT0_IMASK_RXNE_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_RXNE_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_RXNE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_RXNE_A { match self . bits { false => INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_CLR , true => INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_rxne_clr (& self) -> bool { * self == INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_rxne_set (& self) -> bool { * self == INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_SET } } # [doc = "Field `INT_EVENT0_IMASK_RXNE` writer - Enable Negative Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_IMASK_RXNE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_RXNE_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_RXNE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_rxne_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_rxne_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_SET) } } # [doc = "Field `INT_EVENT0_IMASK_RXPE` reader - Enable Positive Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_IMASK_RXPE_R = crate :: BitReader < INT_EVENT0_IMASK_RXPE_A > ; # [doc = "Enable Positive Edge on UARTxRXD Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_RXPE_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_RXPE_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_RXPE_SET = 1 , } impl From < INT_EVENT0_IMASK_RXPE_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_RXPE_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_RXPE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_RXPE_A { match self . bits { false => INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_CLR , true => INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_rxpe_clr (& self) -> bool { * self == INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_rxpe_set (& self) -> bool { * self == INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_SET } } # [doc = "Field `INT_EVENT0_IMASK_RXPE` writer - Enable Positive Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_IMASK_RXPE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_RXPE_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_RXPE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_rxpe_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_rxpe_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_SET) } } # [doc = "Field `INT_EVENT0_IMASK_LINC0` reader - Enable LIN Capture 0 / Match Interrupt ."] pub type INT_EVENT0_IMASK_LINC0_R = crate :: BitReader < INT_EVENT0_IMASK_LINC0_A > ; # [doc = "Enable LIN Capture 0 / Match Interrupt .\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_LINC0_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_LINC0_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_LINC0_SET = 1 , } impl From < INT_EVENT0_IMASK_LINC0_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_LINC0_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_LINC0_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_LINC0_A { match self . bits { false => INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_CLR , true => INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_linc0_clr (& self) -> bool { * self == INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_linc0_set (& self) -> bool { * self == INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_SET } } # [doc = "Field `INT_EVENT0_IMASK_LINC0` writer - Enable LIN Capture 0 / Match Interrupt ."] pub type INT_EVENT0_IMASK_LINC0_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_LINC0_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_LINC0_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_linc0_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_linc0_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_SET) } } # [doc = "Field `INT_EVENT0_IMASK_LINC1` reader - Enable LIN Capture 1 Interrupt."] pub type INT_EVENT0_IMASK_LINC1_R = crate :: BitReader < INT_EVENT0_IMASK_LINC1_A > ; # [doc = "Enable LIN Capture 1 Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_LINC1_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_LINC1_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_LINC1_SET = 1 , } impl From < INT_EVENT0_IMASK_LINC1_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_LINC1_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_LINC1_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_LINC1_A { match self . bits { false => INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_CLR , true => INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_linc1_clr (& self) -> bool { * self == INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_linc1_set (& self) -> bool { * self == INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_SET } } # [doc = "Field `INT_EVENT0_IMASK_LINC1` writer - Enable LIN Capture 1 Interrupt."] pub type INT_EVENT0_IMASK_LINC1_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_LINC1_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_LINC1_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_linc1_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_linc1_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_SET) } } # [doc = "Field `INT_EVENT0_IMASK_LINOVF` reader - Enable LIN Hardware Counter Overflow Interrupt."] pub type INT_EVENT0_IMASK_LINOVF_R = crate :: BitReader < INT_EVENT0_IMASK_LINOVF_A > ; # [doc = "Enable LIN Hardware Counter Overflow Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_LINOVF_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_LINOVF_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_LINOVF_SET = 1 , } impl From < INT_EVENT0_IMASK_LINOVF_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_LINOVF_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_LINOVF_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_LINOVF_A { match self . bits { false => INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_CLR , true => INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_linovf_clr (& self) -> bool { * self == INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_linovf_set (& self) -> bool { * self == INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_SET } } # [doc = "Field `INT_EVENT0_IMASK_LINOVF` writer - Enable LIN Hardware Counter Overflow Interrupt."] pub type INT_EVENT0_IMASK_LINOVF_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_LINOVF_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_LINOVF_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_linovf_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_linovf_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_SET) } } # [doc = "Field `INT_EVENT0_IMASK_RXINT` reader - Enable UART Receive Interrupt."] pub type INT_EVENT0_IMASK_RXINT_R = crate :: BitReader < INT_EVENT0_IMASK_RXINT_A > ; # [doc = "Enable UART Receive Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_RXINT_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_RXINT_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_RXINT_SET = 1 , } impl From < INT_EVENT0_IMASK_RXINT_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_RXINT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_RXINT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_RXINT_A { match self . bits { false => INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_CLR , true => INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_rxint_clr (& self) -> bool { * self == INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_rxint_set (& self) -> bool { * self == INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_SET } } # [doc = "Field `INT_EVENT0_IMASK_RXINT` writer - Enable UART Receive Interrupt."] pub type INT_EVENT0_IMASK_RXINT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_RXINT_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_RXINT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_rxint_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_rxint_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_SET) } } # [doc = "Field `INT_EVENT0_IMASK_TXINT` reader - Enable UART Transmit Interrupt."] pub type INT_EVENT0_IMASK_TXINT_R = crate :: BitReader < INT_EVENT0_IMASK_TXINT_A > ; # [doc = "Enable UART Transmit Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_TXINT_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_TXINT_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_TXINT_SET = 1 , } impl From < INT_EVENT0_IMASK_TXINT_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_TXINT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_TXINT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_TXINT_A { match self . bits { false => INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_CLR , true => INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_txint_clr (& self) -> bool { * self == INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_txint_set (& self) -> bool { * self == INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_SET } } # [doc = "Field `INT_EVENT0_IMASK_TXINT` writer - Enable UART Transmit Interrupt."] pub type INT_EVENT0_IMASK_TXINT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_TXINT_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_TXINT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_txint_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_txint_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_SET) } } # [doc = "Field `INT_EVENT0_IMASK_EOT` reader - Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] pub type INT_EVENT0_IMASK_EOT_R = crate :: BitReader < INT_EVENT0_IMASK_EOT_A > ; # [doc = "Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_EOT_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_EOT_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_EOT_SET = 1 , } impl From < INT_EVENT0_IMASK_EOT_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_EOT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_EOT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_EOT_A { match self . bits { false => INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_CLR , true => INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_eot_clr (& self) -> bool { * self == INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_eot_set (& self) -> bool { * self == INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_SET } } # [doc = "Field `INT_EVENT0_IMASK_EOT` writer - Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] pub type INT_EVENT0_IMASK_EOT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_EOT_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_EOT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_eot_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_eot_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_SET) } } # [doc = "Field `INT_EVENT0_IMASK_ADDR_MATCH` reader - Enable Address Match Interrupt."] pub type INT_EVENT0_IMASK_ADDR_MATCH_R = crate :: BitReader < INT_EVENT0_IMASK_ADDR_MATCH_A > ; # [doc = "Enable Address Match Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_ADDR_MATCH_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_ADDR_MATCH_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_ADDR_MATCH_SET = 1 , } impl From < INT_EVENT0_IMASK_ADDR_MATCH_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_ADDR_MATCH_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_ADDR_MATCH_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_ADDR_MATCH_A { match self . bits { false => INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_CLR , true => INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_addr_match_clr (& self) -> bool { * self == INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_addr_match_set (& self) -> bool { * self == INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_SET } } # [doc = "Field `INT_EVENT0_IMASK_ADDR_MATCH` writer - Enable Address Match Interrupt."] pub type INT_EVENT0_IMASK_ADDR_MATCH_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_ADDR_MATCH_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_ADDR_MATCH_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_addr_match_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_addr_match_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_SET) } } # [doc = "Field `INT_EVENT0_IMASK_CTS` reader - Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] pub type INT_EVENT0_IMASK_CTS_R = crate :: BitReader < INT_EVENT0_IMASK_CTS_A > ; # [doc = "Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_CTS_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_CTS_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_CTS_SET = 1 , } impl From < INT_EVENT0_IMASK_CTS_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_CTS_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_CTS_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_CTS_A { match self . bits { false => INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_CLR , true => INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_cts_clr (& self) -> bool { * self == INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_cts_set (& self) -> bool { * self == INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_SET } } # [doc = "Field `INT_EVENT0_IMASK_CTS` writer - Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] pub type INT_EVENT0_IMASK_CTS_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_CTS_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_CTS_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_cts_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_cts_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DMA_DONE_RX` reader - Enable DMA Done on RX Event Channel"] pub type INT_EVENT0_IMASK_DMA_DONE_RX_R = crate :: BitReader < INT_EVENT0_IMASK_DMA_DONE_RX_A > ; # [doc = "Enable DMA Done on RX Event Channel\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DMA_DONE_RX_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DMA_DONE_RX_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DMA_DONE_RX_SET = 1 , } impl From < INT_EVENT0_IMASK_DMA_DONE_RX_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DMA_DONE_RX_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DMA_DONE_RX_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DMA_DONE_RX_A { match self . bits { false => INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_CLR , true => INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dma_done_rx_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dma_done_rx_set (& self) -> bool { * self == INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_SET } } # [doc = "Field `INT_EVENT0_IMASK_DMA_DONE_RX` writer - Enable DMA Done on RX Event Channel"] pub type INT_EVENT0_IMASK_DMA_DONE_RX_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DMA_DONE_RX_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DMA_DONE_RX_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dma_done_rx_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dma_done_rx_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DMA_DONE_TX` reader - Enable DMA Done on TX Event Channel"] pub type INT_EVENT0_IMASK_DMA_DONE_TX_R = crate :: BitReader < INT_EVENT0_IMASK_DMA_DONE_TX_A > ; # [doc = "Enable DMA Done on TX Event Channel\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DMA_DONE_TX_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DMA_DONE_TX_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DMA_DONE_TX_SET = 1 , } impl From < INT_EVENT0_IMASK_DMA_DONE_TX_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DMA_DONE_TX_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DMA_DONE_TX_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DMA_DONE_TX_A { match self . bits { false => INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_CLR , true => INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dma_done_tx_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dma_done_tx_set (& self) -> bool { * self == INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_SET } } # [doc = "Field `INT_EVENT0_IMASK_DMA_DONE_TX` writer - Enable DMA Done on TX Event Channel"] pub type INT_EVENT0_IMASK_DMA_DONE_TX_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DMA_DONE_TX_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DMA_DONE_TX_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dma_done_tx_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dma_done_tx_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_SET) } } # [doc = "Field `INT_EVENT0_IMASK_NERR` reader - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] pub type INT_EVENT0_IMASK_NERR_R = crate :: BitReader < INT_EVENT0_IMASK_NERR_A > ; # [doc = "Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_NERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_NERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_NERR_SET = 1 , } impl From < INT_EVENT0_IMASK_NERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_NERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_NERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_NERR_A { match self . bits { false => INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_CLR , true => INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_nerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_nerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_NERR` writer - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] pub type INT_EVENT0_IMASK_NERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_NERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_NERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_nerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_nerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_SET) } } impl R { # [doc = "Bit 0 - Enable UARTOUT Receive Time-Out Interrupt."] # [inline (always)] pub fn int_event0_imask_rtout (& self) -> INT_EVENT0_IMASK_RTOUT_R { INT_EVENT0_IMASK_RTOUT_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - Enable UART Framing Error Interrupt."] # [inline (always)] pub fn int_event0_imask_frmerr (& self) -> INT_EVENT0_IMASK_FRMERR_R { INT_EVENT0_IMASK_FRMERR_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - Enable UART Parity Error Interrupt."] # [inline (always)] pub fn int_event0_imask_parerr (& self) -> INT_EVENT0_IMASK_PARERR_R { INT_EVENT0_IMASK_PARERR_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - Enable UART Break Error Interrupt."] # [inline (always)] pub fn int_event0_imask_brkerr (& self) -> INT_EVENT0_IMASK_BRKERR_R { INT_EVENT0_IMASK_BRKERR_R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - Enable UART Receive Overrun Error Interrupt."] # [inline (always)] pub fn int_event0_imask_ovrerr (& self) -> INT_EVENT0_IMASK_OVRERR_R { INT_EVENT0_IMASK_OVRERR_R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - Enable Negative Edge on UARTxRXD Interrupt."] # [inline (always)] pub fn int_event0_imask_rxne (& self) -> INT_EVENT0_IMASK_RXNE_R { INT_EVENT0_IMASK_RXNE_R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - Enable Positive Edge on UARTxRXD Interrupt."] # [inline (always)] pub fn int_event0_imask_rxpe (& self) -> INT_EVENT0_IMASK_RXPE_R { INT_EVENT0_IMASK_RXPE_R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - Enable LIN Capture 0 / Match Interrupt ."] # [inline (always)] pub fn int_event0_imask_linc0 (& self) -> INT_EVENT0_IMASK_LINC0_R { INT_EVENT0_IMASK_LINC0_R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - Enable LIN Capture 1 Interrupt."] # [inline (always)] pub fn int_event0_imask_linc1 (& self) -> INT_EVENT0_IMASK_LINC1_R { INT_EVENT0_IMASK_LINC1_R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - Enable LIN Hardware Counter Overflow Interrupt."] # [inline (always)] pub fn int_event0_imask_linovf (& self) -> INT_EVENT0_IMASK_LINOVF_R { INT_EVENT0_IMASK_LINOVF_R :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - Enable UART Receive Interrupt."] # [inline (always)] pub fn int_event0_imask_rxint (& self) -> INT_EVENT0_IMASK_RXINT_R { INT_EVENT0_IMASK_RXINT_R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - Enable UART Transmit Interrupt."] # [inline (always)] pub fn int_event0_imask_txint (& self) -> INT_EVENT0_IMASK_TXINT_R { INT_EVENT0_IMASK_TXINT_R :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] # [inline (always)] pub fn int_event0_imask_eot (& self) -> INT_EVENT0_IMASK_EOT_R { INT_EVENT0_IMASK_EOT_R :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - Enable Address Match Interrupt."] # [inline (always)] pub fn int_event0_imask_addr_match (& self) -> INT_EVENT0_IMASK_ADDR_MATCH_R { INT_EVENT0_IMASK_ADDR_MATCH_R :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 14 - Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] # [inline (always)] pub fn int_event0_imask_cts (& self) -> INT_EVENT0_IMASK_CTS_R { INT_EVENT0_IMASK_CTS_R :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - Enable DMA Done on RX Event Channel"] # [inline (always)] pub fn int_event0_imask_dma_done_rx (& self) -> INT_EVENT0_IMASK_DMA_DONE_RX_R { INT_EVENT0_IMASK_DMA_DONE_RX_R :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bit 16 - Enable DMA Done on TX Event Channel"] # [inline (always)] pub fn int_event0_imask_dma_done_tx (& self) -> INT_EVENT0_IMASK_DMA_DONE_TX_R { INT_EVENT0_IMASK_DMA_DONE_TX_R :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] # [inline (always)] pub fn int_event0_imask_nerr (& self) -> INT_EVENT0_IMASK_NERR_R { INT_EVENT0_IMASK_NERR_R :: new (((self . bits >> 17) & 1) != 0) } } impl W { # [doc = "Bit 0 - Enable UARTOUT Receive Time-Out Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_rtout (& mut self) -> INT_EVENT0_IMASK_RTOUT_W < INT_EVENT0_IMASK_SPEC , 0 > { INT_EVENT0_IMASK_RTOUT_W :: new (self) } # [doc = "Bit 1 - Enable UART Framing Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_frmerr (& mut self) -> INT_EVENT0_IMASK_FRMERR_W < INT_EVENT0_IMASK_SPEC , 1 > { INT_EVENT0_IMASK_FRMERR_W :: new (self) } # [doc = "Bit 2 - Enable UART Parity Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_parerr (& mut self) -> INT_EVENT0_IMASK_PARERR_W < INT_EVENT0_IMASK_SPEC , 2 > { INT_EVENT0_IMASK_PARERR_W :: new (self) } # [doc = "Bit 3 - Enable UART Break Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_brkerr (& mut self) -> INT_EVENT0_IMASK_BRKERR_W < INT_EVENT0_IMASK_SPEC , 3 > { INT_EVENT0_IMASK_BRKERR_W :: new (self) } # [doc = "Bit 4 - Enable UART Receive Overrun Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_ovrerr (& mut self) -> INT_EVENT0_IMASK_OVRERR_W < INT_EVENT0_IMASK_SPEC , 4 > { INT_EVENT0_IMASK_OVRERR_W :: new (self) } # [doc = "Bit 5 - Enable Negative Edge on UARTxRXD Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_rxne (& mut self) -> INT_EVENT0_IMASK_RXNE_W < INT_EVENT0_IMASK_SPEC , 5 > { INT_EVENT0_IMASK_RXNE_W :: new (self) } # [doc = "Bit 6 - Enable Positive Edge on UARTxRXD Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_rxpe (& mut self) -> INT_EVENT0_IMASK_RXPE_W < INT_EVENT0_IMASK_SPEC , 6 > { INT_EVENT0_IMASK_RXPE_W :: new (self) } # [doc = "Bit 7 - Enable LIN Capture 0 / Match Interrupt ."] # [inline (always)] # [must_use] pub fn int_event0_imask_linc0 (& mut self) -> INT_EVENT0_IMASK_LINC0_W < INT_EVENT0_IMASK_SPEC , 7 > { INT_EVENT0_IMASK_LINC0_W :: new (self) } # [doc = "Bit 8 - Enable LIN Capture 1 Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_linc1 (& mut self) -> INT_EVENT0_IMASK_LINC1_W < INT_EVENT0_IMASK_SPEC , 8 > { INT_EVENT0_IMASK_LINC1_W :: new (self) } # [doc = "Bit 9 - Enable LIN Hardware Counter Overflow Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_linovf (& mut self) -> INT_EVENT0_IMASK_LINOVF_W < INT_EVENT0_IMASK_SPEC , 9 > { INT_EVENT0_IMASK_LINOVF_W :: new (self) } # [doc = "Bit 10 - Enable UART Receive Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_rxint (& mut self) -> INT_EVENT0_IMASK_RXINT_W < INT_EVENT0_IMASK_SPEC , 10 > { INT_EVENT0_IMASK_RXINT_W :: new (self) } # [doc = "Bit 11 - Enable UART Transmit Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_txint (& mut self) -> INT_EVENT0_IMASK_TXINT_W <'_,  INT_EVENT0_IMASK_SPEC , 11 > { INT_EVENT0_IMASK_TXINT_W :: new (self) } # [doc = "Bit 12 - Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] # [inline (always)] # [must_use] pub fn int_event0_imask_eot (& mut self) -> INT_EVENT0_IMASK_EOT_W < INT_EVENT0_IMASK_SPEC , 12 > { INT_EVENT0_IMASK_EOT_W :: new (self) } # [doc = "Bit 13 - Enable Address Match Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_addr_match (& mut self) -> INT_EVENT0_IMASK_ADDR_MATCH_W < INT_EVENT0_IMASK_SPEC , 13 > { INT_EVENT0_IMASK_ADDR_MATCH_W :: new (self) } # [doc = "Bit 14 - Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] # [inline (always)] # [must_use] pub fn int_event0_imask_cts (& mut self) -> INT_EVENT0_IMASK_CTS_W < INT_EVENT0_IMASK_SPEC , 14 > { INT_EVENT0_IMASK_CTS_W :: new (self) } # [doc = "Bit 15 - Enable DMA Done on RX Event Channel"] # [inline (always)] # [must_use] pub fn int_event0_imask_dma_done_rx (& mut self) -> INT_EVENT0_IMASK_DMA_DONE_RX_W < INT_EVENT0_IMASK_SPEC , 15 > { INT_EVENT0_IMASK_DMA_DONE_RX_W :: new (self) } # [doc = "Bit 16 - Enable DMA Done on TX Event Channel"] # [inline (always)] # [must_use] pub fn int_event0_imask_dma_done_tx (& mut self) -> INT_EVENT0_IMASK_DMA_DONE_TX_W < INT_EVENT0_IMASK_SPEC , 16 > { INT_EVENT0_IMASK_DMA_DONE_TX_W :: new (self) } # [doc = "Bit 17 - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] # [inline (always)] # [must_use] pub fn int_event0_imask_nerr (& mut self) -> INT_EVENT0_IMASK_NERR_W < INT_EVENT0_IMASK_SPEC , 17 > { INT_EVENT0_IMASK_NERR_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Interrupt mask\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_event0_imask::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_event0_imask::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct INT_EVENT0_IMASK_SPEC ; impl crate :: RegisterSpec for INT_EVENT0_IMASK_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`int_event0_imask::R`](R) reader structure"] impl crate :: Readable for INT_EVENT0_IMASK_SPEC { } # [doc = "`write(|w| ..)` method takes [`int_event0_imask::W`](W) writer structure"] impl crate :: Writable for INT_EVENT0_IMASK_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets INT_EVENT0_IMASK to value 0"] impl crate :: Resettable for INT_EVENT0_IMASK_SPEC { const RESET_VALUE : Self :: Ux = 0 ; }
[INFO] [stdout]   |                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                       +++
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing
[INFO] [stdout]  --> src/uart0/ctl0.rs:1:39846
[INFO] [stdout]   |
[INFO] [stdout] 1 | ...ub fn ctl0_txd_out_en (& mut self) -> CTL0_TXD_OUT_EN_W < CTL0_SPEC , 5 > { CTL0_TXD_OUT_EN_W :: new (self) } # [doc = "Bit 6 - TX...
[INFO] [stdout]   |                           ^^^^^^^^^^     ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here
[INFO] [stdout]   |                           |
[INFO] [stdout]   |                           the lifetime is elided here
[INFO] [stdout]   |
[INFO] [stdout]   = help: the same lifetime is referred to in inconsistent ways, making the signature confusing
[INFO] [stdout] help: use `'_` for type paths
[INFO] [stdout]   |
[INFO] [stdout] 1 | # [doc = "Register `CTL0` reader"] pub type R = crate :: R < CTL0_SPEC > ; # [doc = "Register `CTL0` writer"] pub type W = crate :: W < CTL0_SPEC > ; # [doc = "Field `CTL0_ENABLE` reader - UART Module Enable. If the UART is disabled in the middle of transmission or reception, it completes the current character before stopping. If the ENABLE bit is not set, all registers can still be accessed and updated. It is recommended to setup and change the UART operation mode with having the ENABLE bit cleared to avoid unpredictable behavior during the setup or update. If disabled the UART module will not send or receive any data and the logic is held in reset state."] pub type CTL0_ENABLE_R = crate :: BitReader < CTL0_ENABLE_A > ; # [doc = "UART Module Enable. If the UART is disabled in the middle of transmission or reception, it completes the current character before stopping. If the ENABLE bit is not set, all registers can still be accessed and updated. It is recommended to setup and change the UART operation mode with having the ENABLE bit cleared to avoid unpredictable behavior during the setup or update. If disabled the UART module will not send or receive any data and the logic is held in reset state.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CTL0_ENABLE_A { # [doc = "0: DISABLE"] CTL0_ENABLE_DISABLE = 0 , # [doc = "1: ENABLE"] CTL0_ENABLE_ENABLE = 1 , } impl From < CTL0_ENABLE_A > for bool { # [inline (always)] fn from (variant : CTL0_ENABLE_A) -> Self { variant as u8 != 0 } } impl CTL0_ENABLE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CTL0_ENABLE_A { match self . bits { false => CTL0_ENABLE_A :: CTL0_ENABLE_DISABLE , true => CTL0_ENABLE_A :: CTL0_ENABLE_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_ctl0_enable_disable (& self) -> bool { * self == CTL0_ENABLE_A :: CTL0_ENABLE_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_ctl0_enable_enable (& self) -> bool { * self == CTL0_ENABLE_A :: CTL0_ENABLE_ENABLE } } # [doc = "Field `CTL0_ENABLE` writer - UART Module Enable. If the UART is disabled in the middle of transmission or reception, it completes the current character before stopping. If the ENABLE bit is not set, all registers can still be accessed and updated. It is recommended to setup and change the UART operation mode with having the ENABLE bit cleared to avoid unpredictable behavior during the setup or update. If disabled the UART module will not send or receive any data and the logic is held in reset state."] pub type CTL0_ENABLE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL0_ENABLE_A > ; impl < 'a , REG , const O : u8 > CTL0_ENABLE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn ctl0_enable_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_ENABLE_A :: CTL0_ENABLE_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn ctl0_enable_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_ENABLE_A :: CTL0_ENABLE_ENABLE) } } # [doc = "Field `CTL0_LBE` reader - UART Loop Back Enable"] pub type CTL0_LBE_R = crate :: BitReader < CTL0_LBE_A > ; # [doc = "UART Loop Back Enable\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CTL0_LBE_A { # [doc = "0: DISABLE"] CTL0_LBE_DISABLE = 0 , # [doc = "1: ENABLE"] CTL0_LBE_ENABLE = 1 , } impl From < CTL0_LBE_A > for bool { # [inline (always)] fn from (variant : CTL0_LBE_A) -> Self { variant as u8 != 0 } } impl CTL0_LBE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CTL0_LBE_A { match self . bits { false => CTL0_LBE_A :: CTL0_LBE_DISABLE , true => CTL0_LBE_A :: CTL0_LBE_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_ctl0_lbe_disable (& self) -> bool { * self == CTL0_LBE_A :: CTL0_LBE_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_ctl0_lbe_enable (& self) -> bool { * self == CTL0_LBE_A :: CTL0_LBE_ENABLE } } # [doc = "Field `CTL0_LBE` writer - UART Loop Back Enable"] pub type CTL0_LBE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL0_LBE_A > ; impl < 'a , REG , const O : u8 > CTL0_LBE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn ctl0_lbe_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_LBE_A :: CTL0_LBE_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn ctl0_lbe_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_LBE_A :: CTL0_LBE_ENABLE) } } # [doc = "Field `CTL0_RXE` reader - UART Receive Enable If the UART is disabled in the middle of a receive, it completes the current character before stopping. #b#NOTE:#/b# To enable reception, the UARTEN bit must be set."] pub type CTL0_RXE_R = crate :: BitReader < CTL0_RXE_A > ; # [doc = "UART Receive Enable If the UART is disabled in the middle of a receive, it completes the current character before stopping. #b#NOTE:#/b# To enable reception, the UARTEN bit must be set.\n\nValue on reset: 1"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CTL0_RXE_A { # [doc = "0: DISABLE"] CTL0_RXE_DISABLE = 0 , # [doc = "1: ENABLE"] CTL0_RXE_ENABLE = 1 , } impl From < CTL0_RXE_A > for bool { # [inline (always)] fn from (variant : CTL0_RXE_A) -> Self { variant as u8 != 0 } } impl CTL0_RXE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CTL0_RXE_A { match self . bits { false => CTL0_RXE_A :: CTL0_RXE_DISABLE , true => CTL0_RXE_A :: CTL0_RXE_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_ctl0_rxe_disable (& self) -> bool { * self == CTL0_RXE_A :: CTL0_RXE_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_ctl0_rxe_enable (& self) -> bool { * self == CTL0_RXE_A :: CTL0_RXE_ENABLE } } # [doc = "Field `CTL0_RXE` writer - UART Receive Enable If the UART is disabled in the middle of a receive, it completes the current character before stopping. #b#NOTE:#/b# To enable reception, the UARTEN bit must be set."] pub type CTL0_RXE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL0_RXE_A > ; impl < 'a , REG , const O : u8 > CTL0_RXE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn ctl0_rxe_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_RXE_A :: CTL0_RXE_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn ctl0_rxe_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_RXE_A :: CTL0_RXE_ENABLE) } } # [doc = "Field `CTL0_TXE` reader - UART Transmit Enable If the UART is disabled in the middle of a transmission, it completes the current character before stopping. #b#NOTE:#/b# To enable transmission, the UARTEN bit must be set."] pub type CTL0_TXE_R = crate :: BitReader < CTL0_TXE_A > ; # [doc = "UART Transmit Enable If the UART is disabled in the middle of a transmission, it completes the current character before stopping. #b#NOTE:#/b# To enable transmission, the UARTEN bit must be set.\n\nValue on reset: 1"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CTL0_TXE_A { # [doc = "0: DISABLE"] CTL0_TXE_DISABLE = 0 , # [doc = "1: ENABLE"] CTL0_TXE_ENABLE = 1 , } impl From < CTL0_TXE_A > for bool { # [inline (always)] fn from (variant : CTL0_TXE_A) -> Self { variant as u8 != 0 } } impl CTL0_TXE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CTL0_TXE_A { match self . bits { false => CTL0_TXE_A :: CTL0_TXE_DISABLE , true => CTL0_TXE_A :: CTL0_TXE_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_ctl0_txe_disable (& self) -> bool { * self == CTL0_TXE_A :: CTL0_TXE_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_ctl0_txe_enable (& self) -> bool { * self == CTL0_TXE_A :: CTL0_TXE_ENABLE } } # [doc = "Field `CTL0_TXE` writer - UART Transmit Enable If the UART is disabled in the middle of a transmission, it completes the current character before stopping. #b#NOTE:#/b# To enable transmission, the UARTEN bit must be set."] pub type CTL0_TXE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL0_TXE_A > ; impl < 'a , REG , const O : u8 > CTL0_TXE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn ctl0_txe_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_TXE_A :: CTL0_TXE_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn ctl0_txe_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_TXE_A :: CTL0_TXE_ENABLE) } } # [doc = "Field `CTL0_TXD_OUT_EN` reader - TXD Pin Control Enable. When the transmit section of the UART is disabled (TXE = 0), the TXD pin can be controlled by the TXD_OUT bit. 1 = UARTxTXD pin can be controlled by TXD_OUT, if TXE = 0"] pub type CTL0_TXD_OUT_EN_R = crate :: BitReader < CTL0_TXD_OUT_EN_A > ; # [doc = "TXD Pin Control Enable. When the transmit section of the UART is disabled (TXE = 0), the TXD pin can be controlled by the TXD_OUT bit. 1 = UARTxTXD pin can be controlled by TXD_OUT, if TXE = 0\n\nValue on reset: 1"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CTL0_TXD_OUT_EN_A { # [doc = "0: DISABLE"] CTL0_TXD_OUT_EN_DISABLE = 0 , # [doc = "1: ENABLE"] CTL0_TXD_OUT_EN_ENABLE = 1 , } impl From < CTL0_TXD_OUT_EN_A > for bool { # [inline (always)] fn from (variant : CTL0_TXD_OUT_EN_A) -> Self { variant as u8 != 0 } } impl CTL0_TXD_OUT_EN_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CTL0_TXD_OUT_EN_A { match self . bits { false => CTL0_TXD_OUT_EN_A :: CTL0_TXD_OUT_EN_DISABLE , true => CTL0_TXD_OUT_EN_A :: CTL0_TXD_OUT_EN_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_ctl0_txd_out_en_disable (& self) -> bool { * self == CTL0_TXD_OUT_EN_A :: CTL0_TXD_OUT_EN_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_ctl0_txd_out_en_enable (& self) -> bool { * self == CTL0_TXD_OUT_EN_A :: CTL0_TXD_OUT_EN_ENABLE } } # [doc = "Field `CTL0_TXD_OUT_EN` writer - TXD Pin Control Enable. When the transmit section of the UART is disabled (TXE = 0), the TXD pin can be controlled by the TXD_OUT bit. 1 = UARTxTXD pin can be controlled by TXD_OUT, if TXE = 0"] pub type CTL0_TXD_OUT_EN_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL0_TXD_OUT_EN_A > ; impl < 'a , REG , const O : u8 > CTL0_TXD_OUT_EN_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn ctl0_txd_out_en_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_TXD_OUT_EN_A :: CTL0_TXD_OUT_EN_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn ctl0_txd_out_en_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_TXD_OUT_EN_A :: CTL0_TXD_OUT_EN_ENABLE) } } # [doc = "Field `CTL0_TXD_OUT` reader - TXD Pin Control Controls the TXD pin when TXD_OUT_EN = 1 and TXE = 0."] pub type CTL0_TXD_OUT_R = crate :: BitReader < CTL0_TXD_OUT_A > ; # [doc = "TXD Pin Control Controls the TXD pin when TXD_OUT_EN = 1 and TXE = 0.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CTL0_TXD_OUT_A { # [doc = "0: LOW"] CTL0_TXD_OUT_LOW = 0 , # [doc = "1: HIGH"] CTL0_TXD_OUT_HIGH = 1 , } impl From < CTL0_TXD_OUT_A > for bool { # [inline (always)] fn from (variant : CTL0_TXD_OUT_A) -> Self { variant as u8 != 0 } } impl CTL0_TXD_OUT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CTL0_TXD_OUT_A { match self . bits { false => CTL0_TXD_OUT_A :: CTL0_TXD_OUT_LOW , true => CTL0_TXD_OUT_A :: CTL0_TXD_OUT_HIGH , } } # [doc = "LOW"] # [inline (always)] pub fn is_ctl0_txd_out_low (& self) -> bool { * self == CTL0_TXD_OUT_A :: CTL0_TXD_OUT_LOW } # [doc = "HIGH"] # [inline (always)] pub fn is_ctl0_txd_out_high (& self) -> bool { * self == CTL0_TXD_OUT_A :: CTL0_TXD_OUT_HIGH } } # [doc = "Field `CTL0_TXD_OUT` writer - TXD Pin Control Controls the TXD pin when TXD_OUT_EN = 1 and TXE = 0."] pub type CTL0_TXD_OUT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL0_TXD_OUT_A > ; impl < 'a , REG , const O : u8 > CTL0_TXD_OUT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "LOW"] # [inline (always)] pub fn ctl0_txd_out_low (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_TXD_OUT_A :: CTL0_TXD_OUT_LOW) } # [doc = "HIGH"] # [inline (always)] pub fn ctl0_txd_out_high (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_TXD_OUT_A :: CTL0_TXD_OUT_HIGH) } } # [doc = "Field `CTL0_MENC` reader - Manchester Encode enable"] pub type CTL0_MENC_R = crate :: BitReader < CTL0_MENC_A > ; # [doc = "Manchester Encode enable\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CTL0_MENC_A { # [doc = "0: DISABLE"] CTL0_MENC_DISABLE = 0 , # [doc = "1: ENABLE"] CTL0_MENC_ENABLE = 1 , } impl From < CTL0_MENC_A > for bool { # [inline (always)] fn from (variant : CTL0_MENC_A) -> Self { variant as u8 != 0 } } impl CTL0_MENC_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CTL0_MENC_A { match self . bits { false => CTL0_MENC_A :: CTL0_MENC_DISABLE , true => CTL0_MENC_A :: CTL0_MENC_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_ctl0_menc_disable (& self) -> bool { * self == CTL0_MENC_A :: CTL0_MENC_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_ctl0_menc_enable (& self) -> bool { * self == CTL0_MENC_A :: CTL0_MENC_ENABLE } } # [doc = "Field `CTL0_MENC` writer - Manchester Encode enable"] pub type CTL0_MENC_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL0_MENC_A > ; impl < 'a , REG , const O : u8 > CTL0_MENC_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn ctl0_menc_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_MENC_A :: CTL0_MENC_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn ctl0_menc_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_MENC_A :: CTL0_MENC_ENABLE) } } # [doc = "Field `CTL0_MODE` reader - Set the communication mode and protocol used. (Not defined settings uses the default setting: 0)"] pub type CTL0_MODE_R = crate :: FieldReader < CTL0_MODE_A > ; # [doc = "Set the communication mode and protocol used. (Not defined settings uses the default setting: 0)\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum CTL0_MODE_A { # [doc = "0: UART"] CTL0_MODE_UART = 0 , # [doc = "1: RS485"] CTL0_MODE_RS485 = 1 , # [doc = "2: IDLELINE"] CTL0_MODE_IDLELINE = 2 , # [doc = "3: ADDR9BIT"] CTL0_MODE_ADDR9BIT = 3 , # [doc = "4: SMART"] CTL0_MODE_SMART = 4 , # [doc = "5: DALI"] CTL0_MODE_DALI = 5 , } impl From < CTL0_MODE_A > for u8 { # [inline (always)] fn from (variant : CTL0_MODE_A) -> Self { variant as _ } } impl crate :: FieldSpec for CTL0_MODE_A { type Ux = u8 ; } impl CTL0_MODE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < CTL0_MODE_A > { match self . bits { 0 => Some (CTL0_MODE_A :: CTL0_MODE_UART) , 1 => Some (CTL0_MODE_A :: CTL0_MODE_RS485) , 2 => Some (CTL0_MODE_A :: CTL0_MODE_IDLELINE) , 3 => Some (CTL0_MODE_A :: CTL0_MODE_ADDR9BIT) , 4 => Some (CTL0_MODE_A :: CTL0_MODE_SMART) , 5 => Some (CTL0_MODE_A :: CTL0_MODE_DALI) , _ => None , } } # [doc = "UART"] # [inline (always)] pub fn is_ctl0_mode_uart (& self) -> bool { * self == CTL0_MODE_A :: CTL0_MODE_UART } # [doc = "RS485"] # [inline (always)] pub fn is_ctl0_mode_rs485 (& self) -> bool { * self == CTL0_MODE_A :: CTL0_MODE_RS485 } # [doc = "IDLELINE"] # [inline (always)] pub fn is_ctl0_mode_idleline (& self) -> bool { * self == CTL0_MODE_A :: CTL0_MODE_IDLELINE } # [doc = "ADDR9BIT"] # [inline (always)] pub fn is_ctl0_mode_addr9bit (& self) -> bool { * self == CTL0_MODE_A :: CTL0_MODE_ADDR9BIT } # [doc = "SMART"] # [inline (always)] pub fn is_ctl0_mode_smart (& self) -> bool { * self == CTL0_MODE_A :: CTL0_MODE_SMART } # [doc = "DALI"] # [inline (always)] pub fn is_ctl0_mode_dali (& self) -> bool { * self == CTL0_MODE_A :: CTL0_MODE_DALI } } # [doc = "Field `CTL0_MODE` writer - Set the communication mode and protocol used. (Not defined settings uses the default setting: 0)"] pub type CTL0_MODE_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 3 , O , CTL0_MODE_A > ; impl < 'a , REG , const O : u8 > CTL0_MODE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "UART"] # [inline (always)] pub fn ctl0_mode_uart (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_MODE_A :: CTL0_MODE_UART) } # [doc = "RS485"] # [inline (always)] pub fn ctl0_mode_rs485 (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_MODE_A :: CTL0_MODE_RS485) } # [doc = "IDLELINE"] # [inline (always)] pub fn ctl0_mode_idleline (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_MODE_A :: CTL0_MODE_IDLELINE) } # [doc = "ADDR9BIT"] # [inline (always)] pub fn ctl0_mode_addr9bit (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_MODE_A :: CTL0_MODE_ADDR9BIT) } # [doc = "SMART"] # [inline (always)] pub fn ctl0_mode_smart (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_MODE_A :: CTL0_MODE_SMART) } # [doc = "DALI"] # [inline (always)] pub fn ctl0_mode_dali (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_MODE_A :: CTL0_MODE_DALI) } } # [doc = "Field `CTL0_RTS` reader - Request to Send If RTSEN is set the RTS output signals is controlled by the hardware logic using the FIFO fill level or TXDATA buffer. If RTSEN is cleared the RTS output is controlled by the RTS bit. The bit is the complement of the UART request to send, RTS modem status output."] pub type CTL0_RTS_R = crate :: BitReader < CTL0_RTS_A > ; # [doc = "Request to Send If RTSEN is set the RTS output signals is controlled by the hardware logic using the FIFO fill level or TXDATA buffer. If RTSEN is cleared the RTS output is controlled by the RTS bit. The bit is the complement of the UART request to send, RTS modem status output.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CTL0_RTS_A { # [doc = "0: CLR"] CTL0_RTS_CLR = 0 , # [doc = "1: SET"] CTL0_RTS_SET = 1 , } impl From < CTL0_RTS_A > for bool { # [inline (always)] fn from (variant : CTL0_RTS_A) -> Self { variant as u8 != 0 } } impl CTL0_RTS_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CTL0_RTS_A { match self . bits { false => CTL0_RTS_A :: CTL0_RTS_CLR , true => CTL0_RTS_A :: CTL0_RTS_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_ctl0_rts_clr (& self) -> bool { * self == CTL0_RTS_A :: CTL0_RTS_CLR } # [doc = "SET"] # [inline (always)] pub fn is_ctl0_rts_set (& self) -> bool { * self == CTL0_RTS_A :: CTL0_RTS_SET } } # [doc = "Field `CTL0_RTS` writer - Request to Send If RTSEN is set the RTS output signals is controlled by the hardware logic using the FIFO fill level or TXDATA buffer. If RTSEN is cleared the RTS output is controlled by the RTS bit. The bit is the complement of the UART request to send, RTS modem status output."] pub type CTL0_RTS_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL0_RTS_A > ; impl < 'a , REG , const O : u8 > CTL0_RTS_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn ctl0_rts_clr (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_RTS_A :: CTL0_RTS_CLR) } # [doc = "SET"] # [inline (always)] pub fn ctl0_rts_set (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_RTS_A :: CTL0_RTS_SET) } } # [doc = "Field `CTL0_RTSEN` reader - Enable hardware controlled Request to Send"] pub type CTL0_RTSEN_R = crate :: BitReader < CTL0_RTSEN_A > ; # [doc = "Enable hardware controlled Request to Send\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CTL0_RTSEN_A { # [doc = "0: DISABLE"] CTL0_RTSEN_DISABLE = 0 , # [doc = "1: ENABLE"] CTL0_RTSEN_ENABLE = 1 , } impl From < CTL0_RTSEN_A > for bool { # [inline (always)] fn from (variant : CTL0_RTSEN_A) -> Self { variant as u8 != 0 } } impl CTL0_RTSEN_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CTL0_RTSEN_A { match self . bits { false => CTL0_RTSEN_A :: CTL0_RTSEN_DISABLE , true => CTL0_RTSEN_A :: CTL0_RTSEN_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_ctl0_rtsen_disable (& self) -> bool { * self == CTL0_RTSEN_A :: CTL0_RTSEN_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_ctl0_rtsen_enable (& self) -> bool { * self == CTL0_RTSEN_A :: CTL0_RTSEN_ENABLE } } # [doc = "Field `CTL0_RTSEN` writer - Enable hardware controlled Request to Send"] pub type CTL0_RTSEN_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL0_RTSEN_A > ; impl < 'a , REG , const O : u8 > CTL0_RTSEN_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn ctl0_rtsen_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_RTSEN_A :: CTL0_RTSEN_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn ctl0_rtsen_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_RTSEN_A :: CTL0_RTSEN_ENABLE) } } # [doc = "Field `CTL0_CTSEN` reader - Enable Clear To Send"] pub type CTL0_CTSEN_R = crate :: BitReader < CTL0_CTSEN_A > ; # [doc = "Enable Clear To Send\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CTL0_CTSEN_A { # [doc = "0: DISABLE"] CTL0_CTSEN_DISABLE = 0 , # [doc = "1: ENABLE"] CTL0_CTSEN_ENABLE = 1 , } impl From < CTL0_CTSEN_A > for bool { # [inline (always)] fn from (variant : CTL0_CTSEN_A) -> Self { variant as u8 != 0 } } impl CTL0_CTSEN_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CTL0_CTSEN_A { match self . bits { false => CTL0_CTSEN_A :: CTL0_CTSEN_DISABLE , true => CTL0_CTSEN_A :: CTL0_CTSEN_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_ctl0_ctsen_disable (& self) -> bool { * self == CTL0_CTSEN_A :: CTL0_CTSEN_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_ctl0_ctsen_enable (& self) -> bool { * self == CTL0_CTSEN_A :: CTL0_CTSEN_ENABLE } } # [doc = "Field `CTL0_CTSEN` writer - Enable Clear To Send"] pub type CTL0_CTSEN_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL0_CTSEN_A > ; impl < 'a , REG , const O : u8 > CTL0_CTSEN_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn ctl0_ctsen_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_CTSEN_A :: CTL0_CTSEN_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn ctl0_ctsen_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_CTSEN_A :: CTL0_CTSEN_ENABLE) } } # [doc = "Field `CTL0_HSE` reader - High-Speed Bit Oversampling Enable #b#NOTE:#/b# The bit oversampling influences the UART baud-rate configuration (see and ). The state of this bit has no effect on clock generation in ISO7816 smart card mode (the SMART bit is set)."] pub type CTL0_HSE_R = crate :: FieldReader < CTL0_HSE_A > ; # [doc = "High-Speed Bit Oversampling Enable #b#NOTE:#/b# The bit oversampling influences the UART baud-rate configuration (see and ). The state of this bit has no effect on clock generation in ISO7816 smart card mode (the SMART bit is set).\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum CTL0_HSE_A { # [doc = "0: OVS16"] CTL0_HSE_OVS16 = 0 , # [doc = "1: OVS8"] CTL0_HSE_OVS8 = 1 , # [doc = "2: OVS3"] CTL0_HSE_OVS3 = 2 , } impl From < CTL0_HSE_A > for u8 { # [inline (always)] fn from (variant : CTL0_HSE_A) -> Self { variant as _ } } impl crate :: FieldSpec for CTL0_HSE_A { type Ux = u8 ; } impl CTL0_HSE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < CTL0_HSE_A > { match self . bits { 0 => Some (CTL0_HSE_A :: CTL0_HSE_OVS16) , 1 => Some (CTL0_HSE_A :: CTL0_HSE_OVS8) , 2 => Some (CTL0_HSE_A :: CTL0_HSE_OVS3) , _ => None , } } # [doc = "OVS16"] # [inline (always)] pub fn is_ctl0_hse_ovs16 (& self) -> bool { * self == CTL0_HSE_A :: CTL0_HSE_OVS16 } # [doc = "OVS8"] # [inline (always)] pub fn is_ctl0_hse_ovs8 (& self) -> bool { * self == CTL0_HSE_A :: CTL0_HSE_OVS8 } # [doc = "OVS3"] # [inline (always)] pub fn is_ctl0_hse_ovs3 (& self) -> bool { * self == CTL0_HSE_A :: CTL0_HSE_OVS3 } } # [doc = "Field `CTL0_HSE` writer - High-Speed Bit Oversampling Enable #b#NOTE:#/b# The bit oversampling influences the UART baud-rate configuration (see and ). The state of this bit has no effect on clock generation in ISO7816 smart card mode (the SMART bit is set)."] pub type CTL0_HSE_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 2 , O , CTL0_HSE_A > ; impl < 'a , REG , const O : u8 > CTL0_HSE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "OVS16"] # [inline (always)] pub fn ctl0_hse_ovs16 (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_HSE_A :: CTL0_HSE_OVS16) } # [doc = "OVS8"] # [inline (always)] pub fn ctl0_hse_ovs8 (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_HSE_A :: CTL0_HSE_OVS8) } # [doc = "OVS3"] # [inline (always)] pub fn ctl0_hse_ovs3 (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_HSE_A :: CTL0_HSE_OVS3) } } # [doc = "Field `CTL0_FEN` reader - UART Enable FIFOs"] pub type CTL0_FEN_R = crate :: BitReader < CTL0_FEN_A > ; # [doc = "UART Enable FIFOs\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CTL0_FEN_A { # [doc = "0: DISABLE"] CTL0_FEN_DISABLE = 0 , # [doc = "1: ENABLE"] CTL0_FEN_ENABLE = 1 , } impl From < CTL0_FEN_A > for bool { # [inline (always)] fn from (variant : CTL0_FEN_A) -> Self { variant as u8 != 0 } } impl CTL0_FEN_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CTL0_FEN_A { match self . bits { false => CTL0_FEN_A :: CTL0_FEN_DISABLE , true => CTL0_FEN_A :: CTL0_FEN_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_ctl0_fen_disable (& self) -> bool { * self == CTL0_FEN_A :: CTL0_FEN_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_ctl0_fen_enable (& self) -> bool { * self == CTL0_FEN_A :: CTL0_FEN_ENABLE } } # [doc = "Field `CTL0_FEN` writer - UART Enable FIFOs"] pub type CTL0_FEN_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL0_FEN_A > ; impl < 'a , REG , const O : u8 > CTL0_FEN_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn ctl0_fen_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_FEN_A :: CTL0_FEN_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn ctl0_fen_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_FEN_A :: CTL0_FEN_ENABLE) } } # [doc = "Field `CTL0_MAJVOTE` reader - When enabled with oversmapling of 16, samples samples 7, 8, and 9 are majority voted to decide the sampled bit value. The value correspond to al least 2 of the 3 samples is considered to be the received value. In case the 3 values do not match, RIS.NERR bit is set along with RDR.NERR When enabled with oversmapling of 8, samples samples 3, 4, and 5 are majority voted to decide the sampled bit value. The value correspond to al least 2 of the 3 samples is considered to be the received value. In case the 3 values donot match, RIS.NERR bit is set along with RDR.NERR When disabled, only a single sample of received bit is taken."] pub type CTL0_MAJVOTE_R = crate :: BitReader < CTL0_MAJVOTE_A > ; # [doc = "When enabled with oversmapling of 16, samples samples 7, 8, and 9 are majority voted to decide the sampled bit value. The value correspond to al least 2 of the 3 samples is considered to be the received value. In case the 3 values do not match, RIS.NERR bit is set along with RDR.NERR When enabled with oversmapling of 8, samples samples 3, 4, and 5 are majority voted to decide the sampled bit value. The value correspond to al least 2 of the 3 samples is considered to be the received value. In case the 3 values donot match, RIS.NERR bit is set along with RDR.NERR When disabled, only a single sample of received bit is taken.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CTL0_MAJVOTE_A { # [doc = "0: DISABLE"] CTL0_MAJVOTE_DISABLE = 0 , # [doc = "1: ENABLE"] CTL0_MAJVOTE_ENABLE = 1 , } impl From < CTL0_MAJVOTE_A > for bool { # [inline (always)] fn from (variant : CTL0_MAJVOTE_A) -> Self { variant as u8 != 0 } } impl CTL0_MAJVOTE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CTL0_MAJVOTE_A { match self . bits { false => CTL0_MAJVOTE_A :: CTL0_MAJVOTE_DISABLE , true => CTL0_MAJVOTE_A :: CTL0_MAJVOTE_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_ctl0_majvote_disable (& self) -> bool { * self == CTL0_MAJVOTE_A :: CTL0_MAJVOTE_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_ctl0_majvote_enable (& self) -> bool { * self == CTL0_MAJVOTE_A :: CTL0_MAJVOTE_ENABLE } } # [doc = "Field `CTL0_MAJVOTE` writer - When enabled with oversmapling of 16, samples samples 7, 8, and 9 are majority voted to decide the sampled bit value. The value correspond to al least 2 of the 3 samples is considered to be the received value. In case the 3 values do not match, RIS.NERR bit is set along with RDR.NERR When enabled with oversmapling of 8, samples samples 3, 4, and 5 are majority voted to decide the sampled bit value. The value correspond to al least 2 of the 3 samples is considered to be the received value. In case the 3 values donot match, RIS.NERR bit is set along with RDR.NERR When disabled, only a single sample of received bit is taken."] pub type CTL0_MAJVOTE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL0_MAJVOTE_A > ; impl < 'a , REG , const O : u8 > CTL0_MAJVOTE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn ctl0_majvote_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_MAJVOTE_A :: CTL0_MAJVOTE_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn ctl0_majvote_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_MAJVOTE_A :: CTL0_MAJVOTE_ENABLE) } } # [doc = "Field `CTL0_MSBFIRST` reader - Most Significant Bit First This bit has effect both on the way protocol byte is transmitted and received. Notes: User needs to match the protocol to the correct value of this bit to send MSb or LSb first. The hardware engine will send the byte entirely based on this bit."] pub type CTL0_MSBFIRST_R = crate :: BitReader < CTL0_MSBFIRST_A > ; # [doc = "Most Significant Bit First This bit has effect both on the way protocol byte is transmitted and received. Notes: User needs to match the protocol to the correct value of this bit to send MSb or LSb first. The hardware engine will send the byte entirely based on this bit.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CTL0_MSBFIRST_A { # [doc = "0: DISABLE"] CTL0_MSBFIRST_DISABLE = 0 , # [doc = "1: ENABLE"] CTL0_MSBFIRST_ENABLE = 1 , } impl From < CTL0_MSBFIRST_A > for bool { # [inline (always)] fn from (variant : CTL0_MSBFIRST_A) -> Self { variant as u8 != 0 } } impl CTL0_MSBFIRST_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CTL0_MSBFIRST_A { match self . bits { false => CTL0_MSBFIRST_A :: CTL0_MSBFIRST_DISABLE , true => CTL0_MSBFIRST_A :: CTL0_MSBFIRST_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_ctl0_msbfirst_disable (& self) -> bool { * self == CTL0_MSBFIRST_A :: CTL0_MSBFIRST_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_ctl0_msbfirst_enable (& self) -> bool { * self == CTL0_MSBFIRST_A :: CTL0_MSBFIRST_ENABLE } } # [doc = "Field `CTL0_MSBFIRST` writer - Most Significant Bit First This bit has effect both on the way protocol byte is transmitted and received. Notes: User needs to match the protocol to the correct value of this bit to send MSb or LSb first. The hardware engine will send the byte entirely based on this bit."] pub type CTL0_MSBFIRST_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL0_MSBFIRST_A > ; impl < 'a , REG , const O : u8 > CTL0_MSBFIRST_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn ctl0_msbfirst_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_MSBFIRST_A :: CTL0_MSBFIRST_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn ctl0_msbfirst_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_MSBFIRST_A :: CTL0_MSBFIRST_ENABLE) } } impl R { # [doc = "Bit 0 - UART Module Enable. If the UART is disabled in the middle of transmission or reception, it completes the current character before stopping. If the ENABLE bit is not set, all registers can still be accessed and updated. It is recommended to setup and change the UART operation mode with having the ENABLE bit cleared to avoid unpredictable behavior during the setup or update. If disabled the UART module will not send or receive any data and the logic is held in reset state."] # [inline (always)] pub fn ctl0_enable (& self) -> CTL0_ENABLE_R { CTL0_ENABLE_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 2 - UART Loop Back Enable"] # [inline (always)] pub fn ctl0_lbe (& self) -> CTL0_LBE_R { CTL0_LBE_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - UART Receive Enable If the UART is disabled in the middle of a receive, it completes the current character before stopping. #b#NOTE:#/b# To enable reception, the UARTEN bit must be set."] # [inline (always)] pub fn ctl0_rxe (& self) -> CTL0_RXE_R { CTL0_RXE_R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - UART Transmit Enable If the UART is disabled in the middle of a transmission, it completes the current character before stopping. #b#NOTE:#/b# To enable transmission, the UARTEN bit must be set."] # [inline (always)] pub fn ctl0_txe (& self) -> CTL0_TXE_R { CTL0_TXE_R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - TXD Pin Control Enable. When the transmit section of the UART is disabled (TXE = 0), the TXD pin can be controlled by the TXD_OUT bit. 1 = UARTxTXD pin can be controlled by TXD_OUT, if TXE = 0"] # [inline (always)] pub fn ctl0_txd_out_en (& self) -> CTL0_TXD_OUT_EN_R { CTL0_TXD_OUT_EN_R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - TXD Pin Control Controls the TXD pin when TXD_OUT_EN = 1 and TXE = 0."] # [inline (always)] pub fn ctl0_txd_out (& self) -> CTL0_TXD_OUT_R { CTL0_TXD_OUT_R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - Manchester Encode enable"] # [inline (always)] pub fn ctl0_menc (& self) -> CTL0_MENC_R { CTL0_MENC_R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bits 8:10 - Set the communication mode and protocol used. (Not defined settings uses the default setting: 0)"] # [inline (always)] pub fn ctl0_mode (& self) -> CTL0_MODE_R { CTL0_MODE_R :: new (((self . bits >> 8) & 7) as u8) } # [doc = "Bit 12 - Request to Send If RTSEN is set the RTS output signals is controlled by the hardware logic using the FIFO fill level or TXDATA buffer. If RTSEN is cleared the RTS output is controlled by the RTS bit. The bit is the complement of the UART request to send, RTS modem status output."] # [inline (always)] pub fn ctl0_rts (& self) -> CTL0_RTS_R { CTL0_RTS_R :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - Enable hardware controlled Request to Send"] # [inline (always)] pub fn ctl0_rtsen (& self) -> CTL0_RTSEN_R { CTL0_RTSEN_R :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 14 - Enable Clear To Send"] # [inline (always)] pub fn ctl0_ctsen (& self) -> CTL0_CTSEN_R { CTL0_CTSEN_R :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bits 15:16 - High-Speed Bit Oversampling Enable #b#NOTE:#/b# The bit oversampling influences the UART baud-rate configuration (see and ). The state of this bit has no effect on clock generation in ISO7816 smart card mode (the SMART bit is set)."] # [inline (always)] pub fn ctl0_hse (& self) -> CTL0_HSE_R { CTL0_HSE_R :: new (((self . bits >> 15) & 3) as u8) } # [doc = "Bit 17 - UART Enable FIFOs"] # [inline (always)] pub fn ctl0_fen (& self) -> CTL0_FEN_R { CTL0_FEN_R :: new (((self . bits >> 17) & 1) != 0) } # [doc = "Bit 18 - When enabled with oversmapling of 16, samples samples 7, 8, and 9 are majority voted to decide the sampled bit value. The value correspond to al least 2 of the 3 samples is considered to be the received value. In case the 3 values do not match, RIS.NERR bit is set along with RDR.NERR When enabled with oversmapling of 8, samples samples 3, 4, and 5 are majority voted to decide the sampled bit value. The value correspond to al least 2 of the 3 samples is considered to be the received value. In case the 3 values donot match, RIS.NERR bit is set along with RDR.NERR When disabled, only a single sample of received bit is taken."] # [inline (always)] pub fn ctl0_majvote (& self) -> CTL0_MAJVOTE_R { CTL0_MAJVOTE_R :: new (((self . bits >> 18) & 1) != 0) } # [doc = "Bit 19 - Most Significant Bit First This bit has effect both on the way protocol byte is transmitted and received. Notes: User needs to match the protocol to the correct value of this bit to send MSb or LSb first. The hardware engine will send the byte entirely based on this bit."] # [inline (always)] pub fn ctl0_msbfirst (& self) -> CTL0_MSBFIRST_R { CTL0_MSBFIRST_R :: new (((self . bits >> 19) & 1) != 0) } } impl W { # [doc = "Bit 0 - UART Module Enable. If the UART is disabled in the middle of transmission or reception, it completes the current character before stopping. If the ENABLE bit is not set, all registers can still be accessed and updated. It is recommended to setup and change the UART operation mode with having the ENABLE bit cleared to avoid unpredictable behavior during the setup or update. If disabled the UART module will not send or receive any data and the logic is held in reset state."] # [inline (always)] # [must_use] pub fn ctl0_enable (& mut self) -> CTL0_ENABLE_W < CTL0_SPEC , 0 > { CTL0_ENABLE_W :: new (self) } # [doc = "Bit 2 - UART Loop Back Enable"] # [inline (always)] # [must_use] pub fn ctl0_lbe (& mut self) -> CTL0_LBE_W < CTL0_SPEC , 2 > { CTL0_LBE_W :: new (self) } # [doc = "Bit 3 - UART Receive Enable If the UART is disabled in the middle of a receive, it completes the current character before stopping. #b#NOTE:#/b# To enable reception, the UARTEN bit must be set."] # [inline (always)] # [must_use] pub fn ctl0_rxe (& mut self) -> CTL0_RXE_W < CTL0_SPEC , 3 > { CTL0_RXE_W :: new (self) } # [doc = "Bit 4 - UART Transmit Enable If the UART is disabled in the middle of a transmission, it completes the current character before stopping. #b#NOTE:#/b# To enable transmission, the UARTEN bit must be set."] # [inline (always)] # [must_use] pub fn ctl0_txe (& mut self) -> CTL0_TXE_W < CTL0_SPEC , 4 > { CTL0_TXE_W :: new (self) } # [doc = "Bit 5 - TXD Pin Control Enable. When the transmit section of the UART is disabled (TXE = 0), the TXD pin can be controlled by the TXD_OUT bit. 1 = UARTxTXD pin can be controlled by TXD_OUT, if TXE = 0"] # [inline (always)] # [must_use] pub fn ctl0_txd_out_en (& mut self) -> CTL0_TXD_OUT_EN_W <'_,  CTL0_SPEC , 5 > { CTL0_TXD_OUT_EN_W :: new (self) } # [doc = "Bit 6 - TXD Pin Control Controls the TXD pin when TXD_OUT_EN = 1 and TXE = 0."] # [inline (always)] # [must_use] pub fn ctl0_txd_out (& mut self) -> CTL0_TXD_OUT_W < CTL0_SPEC , 6 > { CTL0_TXD_OUT_W :: new (self) } # [doc = "Bit 7 - Manchester Encode enable"] # [inline (always)] # [must_use] pub fn ctl0_menc (& mut self) -> CTL0_MENC_W < CTL0_SPEC , 7 > { CTL0_MENC_W :: new (self) } # [doc = "Bits 8:10 - Set the communication mode and protocol used. (Not defined settings uses the default setting: 0)"] # [inline (always)] # [must_use] pub fn ctl0_mode (& mut self) -> CTL0_MODE_W < CTL0_SPEC , 8 > { CTL0_MODE_W :: new (self) } # [doc = "Bit 12 - Request to Send If RTSEN is set the RTS output signals is controlled by the hardware logic using the FIFO fill level or TXDATA buffer. If RTSEN is cleared the RTS output is controlled by the RTS bit. The bit is the complement of the UART request to send, RTS modem status output."] # [inline (always)] # [must_use] pub fn ctl0_rts (& mut self) -> CTL0_RTS_W < CTL0_SPEC , 12 > { CTL0_RTS_W :: new (self) } # [doc = "Bit 13 - Enable hardware controlled Request to Send"] # [inline (always)] # [must_use] pub fn ctl0_rtsen (& mut self) -> CTL0_RTSEN_W < CTL0_SPEC , 13 > { CTL0_RTSEN_W :: new (self) } # [doc = "Bit 14 - Enable Clear To Send"] # [inline (always)] # [must_use] pub fn ctl0_ctsen (& mut self) -> CTL0_CTSEN_W < CTL0_SPEC , 14 > { CTL0_CTSEN_W :: new (self) } # [doc = "Bits 15:16 - High-Speed Bit Oversampling Enable #b#NOTE:#/b# The bit oversampling influences the UART baud-rate configuration (see and ). The state of this bit has no effect on clock generation in ISO7816 smart card mode (the SMART bit is set)."] # [inline (always)] # [must_use] pub fn ctl0_hse (& mut self) -> CTL0_HSE_W < CTL0_SPEC , 15 > { CTL0_HSE_W :: new (self) } # [doc = "Bit 17 - UART Enable FIFOs"] # [inline (always)] # [must_use] pub fn ctl0_fen (& mut self) -> CTL0_FEN_W < CTL0_SPEC , 17 > { CTL0_FEN_W :: new (self) } # [doc = "Bit 18 - When enabled with oversmapling of 16, samples samples 7, 8, and 9 are majority voted to decide the sampled bit value. The value correspond to al least 2 of the 3 samples is considered to be the received value. In case the 3 values do not match, RIS.NERR bit is set along with RDR.NERR When enabled with oversmapling of 8, samples samples 3, 4, and 5 are majority voted to decide the sampled bit value. The value correspond to al least 2 of the 3 samples is considered to be the received value. In case the 3 values donot match, RIS.NERR bit is set along with RDR.NERR When disabled, only a single sample of received bit is taken."] # [inline (always)] # [must_use] pub fn ctl0_majvote (& mut self) -> CTL0_MAJVOTE_W < CTL0_SPEC , 18 > { CTL0_MAJVOTE_W :: new (self) } # [doc = "Bit 19 - Most Significant Bit First This bit has effect both on the way protocol byte is transmitted and received. Notes: User needs to match the protocol to the correct value of this bit to send MSb or LSb first. The hardware engine will send the byte entirely based on this bit."] # [inline (always)] # [must_use] pub fn ctl0_msbfirst (& mut self) -> CTL0_MSBFIRST_W < CTL0_SPEC , 19 > { CTL0_MSBFIRST_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "UART Control Register 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctl0::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctl0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CTL0_SPEC ; impl crate :: RegisterSpec for CTL0_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`ctl0::R`](R) reader structure"] impl crate :: Readable for CTL0_SPEC { } # [doc = "`write(|w| ..)` method takes [`ctl0::W`](W) writer structure"] impl crate :: Writable for CTL0_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets CTL0 to value 0x38"] impl crate :: Resettable for CTL0_SPEC { const RESET_VALUE : Self :: Ux = 0x38 ; }
[WARN] too much data in the log, truncating it
