[INFO] fetching crate mspm0l130x 0.1.5... [INFO] building mspm0l130x-0.1.5 against try#4987e9d4227139400384ab59296ffee3b0fb1183 for pr-146237-2 [INFO] extracting crate mspm0l130x 0.1.5 into /workspace/builds/worker-4-tc2/source [INFO] started tweaking crates.io crate mspm0l130x 0.1.5 [INFO] finished tweaking crates.io crate mspm0l130x 0.1.5 [INFO] tweaked toml for crates.io crate mspm0l130x 0.1.5 written to /workspace/builds/worker-4-tc2/source/Cargo.toml [INFO] validating manifest of crates.io crate mspm0l130x 0.1.5 on toolchain 4987e9d4227139400384ab59296ffee3b0fb1183 [INFO] running `Command { std: CARGO_HOME="/workspace/cargo-home" RUSTUP_HOME="/workspace/rustup-home" "/workspace/cargo-home/bin/cargo" "+4987e9d4227139400384ab59296ffee3b0fb1183" "metadata" "--manifest-path" "Cargo.toml" "--no-deps", kill_on_drop: false }` [INFO] running `Command { std: CARGO_HOME="/workspace/cargo-home" RUSTUP_HOME="/workspace/rustup-home" "/workspace/cargo-home/bin/cargo" "+4987e9d4227139400384ab59296ffee3b0fb1183" "generate-lockfile" "--manifest-path" "Cargo.toml", kill_on_drop: false }` [INFO] [stderr] Blocking waiting for file lock on package cache [INFO] [stderr] Updating crates.io index [INFO] [stderr] Locking 28 packages to latest compatible versions [INFO] [stderr] Adding cortex-m v0.6.7 (available: v0.7.7) [INFO] [stderr] Adding cortex-m-rt v0.6.15 (available: v0.7.5) [INFO] running `Command { std: CARGO_HOME="/workspace/cargo-home" RUSTUP_HOME="/workspace/rustup-home" "/workspace/cargo-home/bin/cargo" "+4987e9d4227139400384ab59296ffee3b0fb1183" "fetch" "--manifest-path" "Cargo.toml", kill_on_drop: false }` [INFO] running `Command { std: "docker" "create" "-v" "/var/lib/crater-agent-workspace/builds/worker-4-tc2/target:/opt/rustwide/target:rw,Z" "-v" "/var/lib/crater-agent-workspace/builds/worker-4-tc2/source:/opt/rustwide/workdir:ro,Z" "-v" "/var/lib/crater-agent-workspace/cargo-home:/opt/rustwide/cargo-home:ro,Z" "-v" "/var/lib/crater-agent-workspace/rustup-home:/opt/rustwide/rustup-home:ro,Z" "-e" "SOURCE_DIR=/opt/rustwide/workdir" "-e" "CARGO_TARGET_DIR=/opt/rustwide/target" "-e" "CARGO_HOME=/opt/rustwide/cargo-home" "-e" "RUSTUP_HOME=/opt/rustwide/rustup-home" "-w" "/opt/rustwide/workdir" "-m" "1610612736" "--user" "0:0" "--network" "none" "ghcr.io/rust-lang/crates-build-env/linux@sha256:e90291280db7d1fac5b66fc6dad9f9662629e7365a55743daf9bdf73ebc4ea79" "/opt/rustwide/cargo-home/bin/cargo" "+4987e9d4227139400384ab59296ffee3b0fb1183" "metadata" "--no-deps" "--format-version=1", kill_on_drop: false }` [INFO] [stdout] b9d1ae814c54547e73d2d2f4cb7d1852f479adaa8e99a8071ce59eb0bfbf4007 [INFO] running `Command { std: "docker" "start" "-a" "b9d1ae814c54547e73d2d2f4cb7d1852f479adaa8e99a8071ce59eb0bfbf4007", kill_on_drop: false }` [INFO] running `Command { std: "docker" "inspect" "b9d1ae814c54547e73d2d2f4cb7d1852f479adaa8e99a8071ce59eb0bfbf4007", kill_on_drop: false }` [INFO] running `Command { std: "docker" "rm" "-f" "b9d1ae814c54547e73d2d2f4cb7d1852f479adaa8e99a8071ce59eb0bfbf4007", kill_on_drop: false }` [INFO] [stdout] b9d1ae814c54547e73d2d2f4cb7d1852f479adaa8e99a8071ce59eb0bfbf4007 [INFO] running `Command { std: "docker" "create" "-v" "/var/lib/crater-agent-workspace/builds/worker-4-tc2/target:/opt/rustwide/target:rw,Z" "-v" "/var/lib/crater-agent-workspace/builds/worker-4-tc2/source:/opt/rustwide/workdir:ro,Z" "-v" "/var/lib/crater-agent-workspace/cargo-home:/opt/rustwide/cargo-home:ro,Z" "-v" "/var/lib/crater-agent-workspace/rustup-home:/opt/rustwide/rustup-home:ro,Z" "-e" "SOURCE_DIR=/opt/rustwide/workdir" "-e" "CARGO_TARGET_DIR=/opt/rustwide/target" "-e" "CARGO_INCREMENTAL=0" "-e" "RUST_BACKTRACE=full" "-e" "RUSTFLAGS=--cap-lints=forbid" "-e" "RUSTDOCFLAGS=--cap-lints=forbid" "-e" "CARGO_HOME=/opt/rustwide/cargo-home" "-e" "RUSTUP_HOME=/opt/rustwide/rustup-home" "-w" "/opt/rustwide/workdir" "-m" "1610612736" "--user" "0:0" "--network" "none" "ghcr.io/rust-lang/crates-build-env/linux@sha256:e90291280db7d1fac5b66fc6dad9f9662629e7365a55743daf9bdf73ebc4ea79" "/opt/rustwide/cargo-home/bin/cargo" "+4987e9d4227139400384ab59296ffee3b0fb1183" "build" "--frozen" "--message-format=json", kill_on_drop: false }` [INFO] [stdout] 452b61a38c5d3dfd1c2c2e5841f407d71d2e90ff142bf3abdf3629daf0851ee1 [INFO] running `Command { std: "docker" "start" "-a" "452b61a38c5d3dfd1c2c2e5841f407d71d2e90ff142bf3abdf3629daf0851ee1", kill_on_drop: false }` [INFO] [stderr] Compiling cortex-m v0.7.7 [INFO] [stderr] Compiling nb v1.1.0 [INFO] [stderr] Compiling stable_deref_trait v1.2.0 [INFO] [stderr] Compiling void v1.0.2 [INFO] [stderr] Compiling vcell v0.1.3 [INFO] [stderr] Compiling cortex-m v0.6.7 [INFO] [stderr] Compiling bitfield v0.13.2 [INFO] [stderr] Compiling mspm0l130x v0.1.5 (/opt/rustwide/workdir) [INFO] [stderr] Compiling generic-array v0.14.7 [INFO] [stderr] Compiling generic-array v0.13.3 [INFO] [stderr] Compiling generic-array v0.12.4 [INFO] [stderr] Compiling bare-metal v0.2.5 [INFO] [stderr] Compiling volatile-register v0.2.2 [INFO] [stderr] Compiling nb v0.1.3 [INFO] [stderr] Compiling embedded-hal v0.2.7 [INFO] [stderr] Compiling as-slice v0.1.5 [INFO] [stderr] Compiling aligned v0.3.5 [INFO] [stdout] warning: unexpected `cfg` condition value: `critical-section` [INFO] [stdout] --> src/lib.rs:2:42742 [INFO] [stdout] | [INFO] [stdout] 2 | ...c = r" Returns all the peripherals *once*."] # [cfg (feature = "critical-section")] # [inline] pub fn take () -> Option < Self > { cri... [INFO] [stdout] | ^^^^^^^^^^^^^^^^^^^^^^^^^^^^ [INFO] [stdout] | [INFO] [stdout] = note: expected values for `feature` are: `cortex-m-rt` and `rt` [INFO] [stdout] = help: consider adding `critical-section` as a feature in `Cargo.toml` [INFO] [stdout] = note: see for more information about checking conditional configuration [INFO] [stdout] = note: `#[warn(unexpected_cfgs)]` on by default [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/uart0/pwren.rs:1:2941 [INFO] [stdout] | [INFO] [stdout] 1 | ...use] pub fn pwren_enable (& mut self) -> PWREN_ENABLE_W < PWREN_SPEC , 0 > { PWREN_ENABLE_W :: new (self) } # [doc = "Bits 24:31 - KEY... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] = note: `#[warn(mismatched_lifetime_syntaxes)]` on by default [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `PWREN` reader"] pub type R = crate :: R < PWREN_SPEC > ; # [doc = "Register `PWREN` writer"] pub type W = crate :: W < PWREN_SPEC > ; # [doc = "Field `PWREN_ENABLE` reader - Enable the power"] pub type PWREN_ENABLE_R = crate :: BitReader < PWREN_ENABLE_A > ; # [doc = "Enable the power\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum PWREN_ENABLE_A { # [doc = "0: DISABLE"] PWREN_ENABLE_DISABLE = 0 , # [doc = "1: ENABLE"] PWREN_ENABLE_ENABLE = 1 , } impl From < PWREN_ENABLE_A > for bool { # [inline (always)] fn from (variant : PWREN_ENABLE_A) -> Self { variant as u8 != 0 } } impl PWREN_ENABLE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> PWREN_ENABLE_A { match self . bits { false => PWREN_ENABLE_A :: PWREN_ENABLE_DISABLE , true => PWREN_ENABLE_A :: PWREN_ENABLE_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_pwren_enable_disable (& self) -> bool { * self == PWREN_ENABLE_A :: PWREN_ENABLE_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_pwren_enable_enable (& self) -> bool { * self == PWREN_ENABLE_A :: PWREN_ENABLE_ENABLE } } # [doc = "Field `PWREN_ENABLE` writer - Enable the power"] pub type PWREN_ENABLE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , PWREN_ENABLE_A > ; impl < 'a , REG , const O : u8 > PWREN_ENABLE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn pwren_enable_disable (self) -> & 'a mut crate :: W < REG > { self . variant (PWREN_ENABLE_A :: PWREN_ENABLE_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn pwren_enable_enable (self) -> & 'a mut crate :: W < REG > { self . variant (PWREN_ENABLE_A :: PWREN_ENABLE_ENABLE) } } # [doc = "KEY to allow Power State Change\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum PWREN_KEY_AW { # [doc = "38: _TO_UNLOCK_W_"] PWREN_KEY_UNLOCK_W = 38 , } impl From < PWREN_KEY_AW > for u8 { # [inline (always)] fn from (variant : PWREN_KEY_AW) -> Self { variant as _ } } impl crate :: FieldSpec for PWREN_KEY_AW { type Ux = u8 ; } # [doc = "Field `PWREN_KEY` writer - KEY to allow Power State Change"] pub type PWREN_KEY_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 8 , O , PWREN_KEY_AW > ; impl < 'a , REG , const O : u8 > PWREN_KEY_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "_TO_UNLOCK_W_"] # [inline (always)] pub fn pwren_key_unlock_w (self) -> & 'a mut crate :: W < REG > { self . variant (PWREN_KEY_AW :: PWREN_KEY_UNLOCK_W) } } impl R { # [doc = "Bit 0 - Enable the power"] # [inline (always)] pub fn pwren_enable (& self) -> PWREN_ENABLE_R { PWREN_ENABLE_R :: new ((self . bits & 1) != 0) } } impl W { # [doc = "Bit 0 - Enable the power"] # [inline (always)] # [must_use] pub fn pwren_enable (& mut self) -> PWREN_ENABLE_W <'_, PWREN_SPEC , 0 > { PWREN_ENABLE_W :: new (self) } # [doc = "Bits 24:31 - KEY to allow Power State Change"] # [inline (always)] # [must_use] pub fn pwren_key (& mut self) -> PWREN_KEY_W < PWREN_SPEC , 24 > { PWREN_KEY_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Power enable\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pwren::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pwren::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PWREN_SPEC ; impl crate :: RegisterSpec for PWREN_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`pwren::R`](R) reader structure"] impl crate :: Readable for PWREN_SPEC { } # [doc = "`write(|w| ..)` method takes [`pwren::W`](W) writer structure"] impl crate :: Writable for PWREN_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets PWREN to value 0"] impl crate :: Resettable for PWREN_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/uart0/pwren.rs:1:3131 [INFO] [stdout] | [INFO] [stdout] 1 | ...ust_use] pub fn pwren_key (& mut self) -> PWREN_KEY_W < PWREN_SPEC , 24 > { PWREN_KEY_W :: new (self) } # [doc = r" Writes raw bits to... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `PWREN` reader"] pub type R = crate :: R < PWREN_SPEC > ; # [doc = "Register `PWREN` writer"] pub type W = crate :: W < PWREN_SPEC > ; # [doc = "Field `PWREN_ENABLE` reader - Enable the power"] pub type PWREN_ENABLE_R = crate :: BitReader < PWREN_ENABLE_A > ; # [doc = "Enable the power\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum PWREN_ENABLE_A { # [doc = "0: DISABLE"] PWREN_ENABLE_DISABLE = 0 , # [doc = "1: ENABLE"] PWREN_ENABLE_ENABLE = 1 , } impl From < PWREN_ENABLE_A > for bool { # [inline (always)] fn from (variant : PWREN_ENABLE_A) -> Self { variant as u8 != 0 } } impl PWREN_ENABLE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> PWREN_ENABLE_A { match self . bits { false => PWREN_ENABLE_A :: PWREN_ENABLE_DISABLE , true => PWREN_ENABLE_A :: PWREN_ENABLE_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_pwren_enable_disable (& self) -> bool { * self == PWREN_ENABLE_A :: PWREN_ENABLE_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_pwren_enable_enable (& self) -> bool { * self == PWREN_ENABLE_A :: PWREN_ENABLE_ENABLE } } # [doc = "Field `PWREN_ENABLE` writer - Enable the power"] pub type PWREN_ENABLE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , PWREN_ENABLE_A > ; impl < 'a , REG , const O : u8 > PWREN_ENABLE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn pwren_enable_disable (self) -> & 'a mut crate :: W < REG > { self . variant (PWREN_ENABLE_A :: PWREN_ENABLE_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn pwren_enable_enable (self) -> & 'a mut crate :: W < REG > { self . variant (PWREN_ENABLE_A :: PWREN_ENABLE_ENABLE) } } # [doc = "KEY to allow Power State Change\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum PWREN_KEY_AW { # [doc = "38: _TO_UNLOCK_W_"] PWREN_KEY_UNLOCK_W = 38 , } impl From < PWREN_KEY_AW > for u8 { # [inline (always)] fn from (variant : PWREN_KEY_AW) -> Self { variant as _ } } impl crate :: FieldSpec for PWREN_KEY_AW { type Ux = u8 ; } # [doc = "Field `PWREN_KEY` writer - KEY to allow Power State Change"] pub type PWREN_KEY_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 8 , O , PWREN_KEY_AW > ; impl < 'a , REG , const O : u8 > PWREN_KEY_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "_TO_UNLOCK_W_"] # [inline (always)] pub fn pwren_key_unlock_w (self) -> & 'a mut crate :: W < REG > { self . variant (PWREN_KEY_AW :: PWREN_KEY_UNLOCK_W) } } impl R { # [doc = "Bit 0 - Enable the power"] # [inline (always)] pub fn pwren_enable (& self) -> PWREN_ENABLE_R { PWREN_ENABLE_R :: new ((self . bits & 1) != 0) } } impl W { # [doc = "Bit 0 - Enable the power"] # [inline (always)] # [must_use] pub fn pwren_enable (& mut self) -> PWREN_ENABLE_W < PWREN_SPEC , 0 > { PWREN_ENABLE_W :: new (self) } # [doc = "Bits 24:31 - KEY to allow Power State Change"] # [inline (always)] # [must_use] pub fn pwren_key (& mut self) -> PWREN_KEY_W <'_, PWREN_SPEC , 24 > { PWREN_KEY_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Power enable\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pwren::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pwren::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PWREN_SPEC ; impl crate :: RegisterSpec for PWREN_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`pwren::R`](R) reader structure"] impl crate :: Readable for PWREN_SPEC { } # [doc = "`write(|w| ..)` method takes [`pwren::W`](W) writer structure"] impl crate :: Writable for PWREN_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets PWREN to value 0"] impl crate :: Resettable for PWREN_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/cpuss/int_group0_iset.rs:1:1312 [INFO] [stdout] | [INFO] [stdout] 1 | ..._group0_iset_int (& mut self) -> INT_GROUP0_ISET_INT_W < INT_GROUP0_ISET_SPEC , 0 > { INT_GROUP0_ISET_INT_W :: new (self) } # [doc = r... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `INT_GROUP0_ISET` writer"] pub type W = crate :: W < INT_GROUP0_ISET_SPEC > ; # [doc = "Sets INT in RIS register\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_GROUP0_ISET_INT_AW { # [doc = "0: NO_EFFECT"] INT_GROUP0_ISET_INT_NO_EFFECT = 0 , # [doc = "1: SET"] INT_GROUP0_ISET_INT_SET = 1 , } impl From < INT_GROUP0_ISET_INT_AW > for bool { # [inline (always)] fn from (variant : INT_GROUP0_ISET_INT_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_GROUP0_ISET_INT` writer - Sets INT in RIS register"] pub type INT_GROUP0_ISET_INT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_GROUP0_ISET_INT_AW > ; impl < 'a , REG , const O : u8 > INT_GROUP0_ISET_INT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_group0_iset_int_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_GROUP0_ISET_INT_AW :: INT_GROUP0_ISET_INT_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_group0_iset_int_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_GROUP0_ISET_INT_AW :: INT_GROUP0_ISET_INT_SET) } } impl W { # [doc = "Bit 0 - Sets INT in RIS register"] # [inline (always)] # [must_use] pub fn int_group0_iset_int (& mut self) -> INT_GROUP0_ISET_INT_W <'_, INT_GROUP0_ISET_SPEC , 0 > { INT_GROUP0_ISET_INT_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Interrupt set\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_group0_iset::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct INT_GROUP0_ISET_SPEC ; impl crate :: RegisterSpec for INT_GROUP0_ISET_SPEC { type Ux = u32 ; } # [doc = "`write(|w| ..)` method takes [`int_group0_iset::W`](W) writer structure"] impl crate :: Writable for INT_GROUP0_ISET_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets INT_GROUP0_ISET to value 0"] impl crate :: Resettable for INT_GROUP0_ISET_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/opa1/pwrctl.rs:1:2896 [INFO] [stdout] | [INFO] [stdout] 1 | ...pub fn pwrctl_auto_off (& mut self) -> PWRCTL_AUTO_OFF_W < PWRCTL_SPEC , 0 > { PWRCTL_AUTO_OFF_W :: new (self) } # [doc = r" Writes ra... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `PWRCTL` reader"] pub type R = crate :: R < PWRCTL_SPEC > ; # [doc = "Register `PWRCTL` writer"] pub type W = crate :: W < PWRCTL_SPEC > ; # [doc = "Field `PWRCTL_AUTO_OFF` reader - When set the peripheral will remove its local IP request for enable so that it can be disabled if no other entities in the system are requesting it to be enabled."] pub type PWRCTL_AUTO_OFF_R = crate :: BitReader < PWRCTL_AUTO_OFF_A > ; # [doc = "When set the peripheral will remove its local IP request for enable so that it can be disabled if no other entities in the system are requesting it to be enabled.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum PWRCTL_AUTO_OFF_A { # [doc = "0: DISABLE"] PWRCTL_AUTO_OFF_DISABLE = 0 , # [doc = "1: ENABLE"] PWRCTL_AUTO_OFF_ENABLE = 1 , } impl From < PWRCTL_AUTO_OFF_A > for bool { # [inline (always)] fn from (variant : PWRCTL_AUTO_OFF_A) -> Self { variant as u8 != 0 } } impl PWRCTL_AUTO_OFF_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> PWRCTL_AUTO_OFF_A { match self . bits { false => PWRCTL_AUTO_OFF_A :: PWRCTL_AUTO_OFF_DISABLE , true => PWRCTL_AUTO_OFF_A :: PWRCTL_AUTO_OFF_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_pwrctl_auto_off_disable (& self) -> bool { * self == PWRCTL_AUTO_OFF_A :: PWRCTL_AUTO_OFF_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_pwrctl_auto_off_enable (& self) -> bool { * self == PWRCTL_AUTO_OFF_A :: PWRCTL_AUTO_OFF_ENABLE } } # [doc = "Field `PWRCTL_AUTO_OFF` writer - When set the peripheral will remove its local IP request for enable so that it can be disabled if no other entities in the system are requesting it to be enabled."] pub type PWRCTL_AUTO_OFF_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , PWRCTL_AUTO_OFF_A > ; impl < 'a , REG , const O : u8 > PWRCTL_AUTO_OFF_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn pwrctl_auto_off_disable (self) -> & 'a mut crate :: W < REG > { self . variant (PWRCTL_AUTO_OFF_A :: PWRCTL_AUTO_OFF_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn pwrctl_auto_off_enable (self) -> & 'a mut crate :: W < REG > { self . variant (PWRCTL_AUTO_OFF_A :: PWRCTL_AUTO_OFF_ENABLE) } } impl R { # [doc = "Bit 0 - When set the peripheral will remove its local IP request for enable so that it can be disabled if no other entities in the system are requesting it to be enabled."] # [inline (always)] pub fn pwrctl_auto_off (& self) -> PWRCTL_AUTO_OFF_R { PWRCTL_AUTO_OFF_R :: new ((self . bits & 1) != 0) } } impl W { # [doc = "Bit 0 - When set the peripheral will remove its local IP request for enable so that it can be disabled if no other entities in the system are requesting it to be enabled."] # [inline (always)] # [must_use] pub fn pwrctl_auto_off (& mut self) -> PWRCTL_AUTO_OFF_W <'_, PWRCTL_SPEC , 0 > { PWRCTL_AUTO_OFF_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Power Control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pwrctl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pwrctl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PWRCTL_SPEC ; impl crate :: RegisterSpec for PWRCTL_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`pwrctl::R`](R) reader structure"] impl crate :: Readable for PWRCTL_SPEC { } # [doc = "`write(|w| ..)` method takes [`pwrctl::W`](W) writer structure"] impl crate :: Writable for PWRCTL_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets PWRCTL to value 0"] impl crate :: Resettable for PWRCTL_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/timg4/ccctl_01.rs:1:33709 [INFO] [stdout] | [INFO] [stdout] 1 | ... pub fn ccctl_01_ccond (& mut self) -> CCCTL_01_CCOND_W < CCCTL_01_SPEC , 0 > { CCCTL_01_CCOND_W :: new (self) } # [doc = "Bits 4:6 - ... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `CCCTL_01[%s]` reader"] pub type R = crate :: R < CCCTL_01_SPEC > ; # [doc = "Register `CCCTL_01[%s]` writer"] pub type W = crate :: W < CCCTL_01_SPEC > ; # [doc = "Field `CCCTL_01_CCOND` reader - Capture Condition. #br# Specifies the condition that generates a capture pulse. 4h-Fh = Reserved"] pub type CCCTL_01_CCOND_R = crate :: FieldReader < CCCTL_01_CCOND_A > ; # [doc = "Capture Condition. #br# Specifies the condition that generates a capture pulse. 4h-Fh = Reserved\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum CCCTL_01_CCOND_A { # [doc = "0: NOCAPTURE"] CCCTL_01_CCOND_NOCAPTURE = 0 , # [doc = "1: CC_TRIG_RISE"] CCCTL_01_CCOND_CC_TRIG_RISE = 1 , # [doc = "2: CC_TRIG_FALL"] CCCTL_01_CCOND_CC_TRIG_FALL = 2 , # [doc = "3: CC_TRIG_EDGE"] CCCTL_01_CCOND_CC_TRIG_EDGE = 3 , } impl From < CCCTL_01_CCOND_A > for u8 { # [inline (always)] fn from (variant : CCCTL_01_CCOND_A) -> Self { variant as _ } } impl crate :: FieldSpec for CCCTL_01_CCOND_A { type Ux = u8 ; } impl CCCTL_01_CCOND_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < CCCTL_01_CCOND_A > { match self . bits { 0 => Some (CCCTL_01_CCOND_A :: CCCTL_01_CCOND_NOCAPTURE) , 1 => Some (CCCTL_01_CCOND_A :: CCCTL_01_CCOND_CC_TRIG_RISE) , 2 => Some (CCCTL_01_CCOND_A :: CCCTL_01_CCOND_CC_TRIG_FALL) , 3 => Some (CCCTL_01_CCOND_A :: CCCTL_01_CCOND_CC_TRIG_EDGE) , _ => None , } } # [doc = "NOCAPTURE"] # [inline (always)] pub fn is_ccctl_01_ccond_nocapture (& self) -> bool { * self == CCCTL_01_CCOND_A :: CCCTL_01_CCOND_NOCAPTURE } # [doc = "CC_TRIG_RISE"] # [inline (always)] pub fn is_ccctl_01_ccond_cc_trig_rise (& self) -> bool { * self == CCCTL_01_CCOND_A :: CCCTL_01_CCOND_CC_TRIG_RISE } # [doc = "CC_TRIG_FALL"] # [inline (always)] pub fn is_ccctl_01_ccond_cc_trig_fall (& self) -> bool { * self == CCCTL_01_CCOND_A :: CCCTL_01_CCOND_CC_TRIG_FALL } # [doc = "CC_TRIG_EDGE"] # [inline (always)] pub fn is_ccctl_01_ccond_cc_trig_edge (& self) -> bool { * self == CCCTL_01_CCOND_A :: CCCTL_01_CCOND_CC_TRIG_EDGE } } # [doc = "Field `CCCTL_01_CCOND` writer - Capture Condition. #br# Specifies the condition that generates a capture pulse. 4h-Fh = Reserved"] pub type CCCTL_01_CCOND_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 3 , O , CCCTL_01_CCOND_A > ; impl < 'a , REG , const O : u8 > CCCTL_01_CCOND_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "NOCAPTURE"] # [inline (always)] pub fn ccctl_01_ccond_nocapture (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CCOND_A :: CCCTL_01_CCOND_NOCAPTURE) } # [doc = "CC_TRIG_RISE"] # [inline (always)] pub fn ccctl_01_ccond_cc_trig_rise (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CCOND_A :: CCCTL_01_CCOND_CC_TRIG_RISE) } # [doc = "CC_TRIG_FALL"] # [inline (always)] pub fn ccctl_01_ccond_cc_trig_fall (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CCOND_A :: CCCTL_01_CCOND_CC_TRIG_FALL) } # [doc = "CC_TRIG_EDGE"] # [inline (always)] pub fn ccctl_01_ccond_cc_trig_edge (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CCOND_A :: CCCTL_01_CCOND_CC_TRIG_EDGE) } } # [doc = "Field `CCCTL_01_ACOND` reader - Advance Condition. #br# Specifies the condition that generates an advance pulse. 6h-Fh = Reserved"] pub type CCCTL_01_ACOND_R = crate :: FieldReader < CCCTL_01_ACOND_A > ; # [doc = "Advance Condition. #br# Specifies the condition that generates an advance pulse. 6h-Fh = Reserved\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum CCCTL_01_ACOND_A { # [doc = "0: TIMCLK"] CCCTL_01_ACOND_TIMCLK = 0 , # [doc = "1: CC_TRIG_RISE"] CCCTL_01_ACOND_CC_TRIG_RISE = 1 , # [doc = "2: CC_TRIG_FALL"] CCCTL_01_ACOND_CC_TRIG_FALL = 2 , # [doc = "3: CC_TRIG_EDGE"] CCCTL_01_ACOND_CC_TRIG_EDGE = 3 , # [doc = "5: CC_TRIG_HIGH"] CCCTL_01_ACOND_CC_TRIG_HIGH = 5 , } impl From < CCCTL_01_ACOND_A > for u8 { # [inline (always)] fn from (variant : CCCTL_01_ACOND_A) -> Self { variant as _ } } impl crate :: FieldSpec for CCCTL_01_ACOND_A { type Ux = u8 ; } impl CCCTL_01_ACOND_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < CCCTL_01_ACOND_A > { match self . bits { 0 => Some (CCCTL_01_ACOND_A :: CCCTL_01_ACOND_TIMCLK) , 1 => Some (CCCTL_01_ACOND_A :: CCCTL_01_ACOND_CC_TRIG_RISE) , 2 => Some (CCCTL_01_ACOND_A :: CCCTL_01_ACOND_CC_TRIG_FALL) , 3 => Some (CCCTL_01_ACOND_A :: CCCTL_01_ACOND_CC_TRIG_EDGE) , 5 => Some (CCCTL_01_ACOND_A :: CCCTL_01_ACOND_CC_TRIG_HIGH) , _ => None , } } # [doc = "TIMCLK"] # [inline (always)] pub fn is_ccctl_01_acond_timclk (& self) -> bool { * self == CCCTL_01_ACOND_A :: CCCTL_01_ACOND_TIMCLK } # [doc = "CC_TRIG_RISE"] # [inline (always)] pub fn is_ccctl_01_acond_cc_trig_rise (& self) -> bool { * self == CCCTL_01_ACOND_A :: CCCTL_01_ACOND_CC_TRIG_RISE } # [doc = "CC_TRIG_FALL"] # [inline (always)] pub fn is_ccctl_01_acond_cc_trig_fall (& self) -> bool { * self == CCCTL_01_ACOND_A :: CCCTL_01_ACOND_CC_TRIG_FALL } # [doc = "CC_TRIG_EDGE"] # [inline (always)] pub fn is_ccctl_01_acond_cc_trig_edge (& self) -> bool { * self == CCCTL_01_ACOND_A :: CCCTL_01_ACOND_CC_TRIG_EDGE } # [doc = "CC_TRIG_HIGH"] # [inline (always)] pub fn is_ccctl_01_acond_cc_trig_high (& self) -> bool { * self == CCCTL_01_ACOND_A :: CCCTL_01_ACOND_CC_TRIG_HIGH } } # [doc = "Field `CCCTL_01_ACOND` writer - Advance Condition. #br# Specifies the condition that generates an advance pulse. 6h-Fh = Reserved"] pub type CCCTL_01_ACOND_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 3 , O , CCCTL_01_ACOND_A > ; impl < 'a , REG , const O : u8 > CCCTL_01_ACOND_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "TIMCLK"] # [inline (always)] pub fn ccctl_01_acond_timclk (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_ACOND_A :: CCCTL_01_ACOND_TIMCLK) } # [doc = "CC_TRIG_RISE"] # [inline (always)] pub fn ccctl_01_acond_cc_trig_rise (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_ACOND_A :: CCCTL_01_ACOND_CC_TRIG_RISE) } # [doc = "CC_TRIG_FALL"] # [inline (always)] pub fn ccctl_01_acond_cc_trig_fall (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_ACOND_A :: CCCTL_01_ACOND_CC_TRIG_FALL) } # [doc = "CC_TRIG_EDGE"] # [inline (always)] pub fn ccctl_01_acond_cc_trig_edge (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_ACOND_A :: CCCTL_01_ACOND_CC_TRIG_EDGE) } # [doc = "CC_TRIG_HIGH"] # [inline (always)] pub fn ccctl_01_acond_cc_trig_high (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_ACOND_A :: CCCTL_01_ACOND_CC_TRIG_HIGH) } } # [doc = "Field `CCCTL_01_LCOND` reader - Load Condition. #br# Specifies the condition that generates a load pulse. 4h-Fh = Reserved"] pub type CCCTL_01_LCOND_R = crate :: FieldReader < CCCTL_01_LCOND_A > ; # [doc = "Load Condition. #br# Specifies the condition that generates a load pulse. 4h-Fh = Reserved\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum CCCTL_01_LCOND_A { # [doc = "1: CC_TRIG_RISE"] CCCTL_01_LCOND_CC_TRIG_RISE = 1 , # [doc = "2: CC_TRIG_FALL"] CCCTL_01_LCOND_CC_TRIG_FALL = 2 , # [doc = "3: CC_TRIG_EDGE"] CCCTL_01_LCOND_CC_TRIG_EDGE = 3 , } impl From < CCCTL_01_LCOND_A > for u8 { # [inline (always)] fn from (variant : CCCTL_01_LCOND_A) -> Self { variant as _ } } impl crate :: FieldSpec for CCCTL_01_LCOND_A { type Ux = u8 ; } impl CCCTL_01_LCOND_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < CCCTL_01_LCOND_A > { match self . bits { 1 => Some (CCCTL_01_LCOND_A :: CCCTL_01_LCOND_CC_TRIG_RISE) , 2 => Some (CCCTL_01_LCOND_A :: CCCTL_01_LCOND_CC_TRIG_FALL) , 3 => Some (CCCTL_01_LCOND_A :: CCCTL_01_LCOND_CC_TRIG_EDGE) , _ => None , } } # [doc = "CC_TRIG_RISE"] # [inline (always)] pub fn is_ccctl_01_lcond_cc_trig_rise (& self) -> bool { * self == CCCTL_01_LCOND_A :: CCCTL_01_LCOND_CC_TRIG_RISE } # [doc = "CC_TRIG_FALL"] # [inline (always)] pub fn is_ccctl_01_lcond_cc_trig_fall (& self) -> bool { * self == CCCTL_01_LCOND_A :: CCCTL_01_LCOND_CC_TRIG_FALL } # [doc = "CC_TRIG_EDGE"] # [inline (always)] pub fn is_ccctl_01_lcond_cc_trig_edge (& self) -> bool { * self == CCCTL_01_LCOND_A :: CCCTL_01_LCOND_CC_TRIG_EDGE } } # [doc = "Field `CCCTL_01_LCOND` writer - Load Condition. #br# Specifies the condition that generates a load pulse. 4h-Fh = Reserved"] pub type CCCTL_01_LCOND_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 3 , O , CCCTL_01_LCOND_A > ; impl < 'a , REG , const O : u8 > CCCTL_01_LCOND_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "CC_TRIG_RISE"] # [inline (always)] pub fn ccctl_01_lcond_cc_trig_rise (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_LCOND_A :: CCCTL_01_LCOND_CC_TRIG_RISE) } # [doc = "CC_TRIG_FALL"] # [inline (always)] pub fn ccctl_01_lcond_cc_trig_fall (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_LCOND_A :: CCCTL_01_LCOND_CC_TRIG_FALL) } # [doc = "CC_TRIG_EDGE"] # [inline (always)] pub fn ccctl_01_lcond_cc_trig_edge (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_LCOND_A :: CCCTL_01_LCOND_CC_TRIG_EDGE) } } # [doc = "Field `CCCTL_01_ZCOND` reader - Zero Condition. #br# This field specifies the condition that generates a zero pulse. 4h-Fh = Reserved"] pub type CCCTL_01_ZCOND_R = crate :: FieldReader < CCCTL_01_ZCOND_A > ; # [doc = "Zero Condition. #br# This field specifies the condition that generates a zero pulse. 4h-Fh = Reserved\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum CCCTL_01_ZCOND_A { # [doc = "1: CC_TRIG_RISE"] CCCTL_01_ZCOND_CC_TRIG_RISE = 1 , # [doc = "2: CC_TRIG_FALL"] CCCTL_01_ZCOND_CC_TRIG_FALL = 2 , # [doc = "3: CC_TRIG_EDGE"] CCCTL_01_ZCOND_CC_TRIG_EDGE = 3 , } impl From < CCCTL_01_ZCOND_A > for u8 { # [inline (always)] fn from (variant : CCCTL_01_ZCOND_A) -> Self { variant as _ } } impl crate :: FieldSpec for CCCTL_01_ZCOND_A { type Ux = u8 ; } impl CCCTL_01_ZCOND_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < CCCTL_01_ZCOND_A > { match self . bits { 1 => Some (CCCTL_01_ZCOND_A :: CCCTL_01_ZCOND_CC_TRIG_RISE) , 2 => Some (CCCTL_01_ZCOND_A :: CCCTL_01_ZCOND_CC_TRIG_FALL) , 3 => Some (CCCTL_01_ZCOND_A :: CCCTL_01_ZCOND_CC_TRIG_EDGE) , _ => None , } } # [doc = "CC_TRIG_RISE"] # [inline (always)] pub fn is_ccctl_01_zcond_cc_trig_rise (& self) -> bool { * self == CCCTL_01_ZCOND_A :: CCCTL_01_ZCOND_CC_TRIG_RISE } # [doc = "CC_TRIG_FALL"] # [inline (always)] pub fn is_ccctl_01_zcond_cc_trig_fall (& self) -> bool { * self == CCCTL_01_ZCOND_A :: CCCTL_01_ZCOND_CC_TRIG_FALL } # [doc = "CC_TRIG_EDGE"] # [inline (always)] pub fn is_ccctl_01_zcond_cc_trig_edge (& self) -> bool { * self == CCCTL_01_ZCOND_A :: CCCTL_01_ZCOND_CC_TRIG_EDGE } } # [doc = "Field `CCCTL_01_ZCOND` writer - Zero Condition. #br# This field specifies the condition that generates a zero pulse. 4h-Fh = Reserved"] pub type CCCTL_01_ZCOND_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 3 , O , CCCTL_01_ZCOND_A > ; impl < 'a , REG , const O : u8 > CCCTL_01_ZCOND_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "CC_TRIG_RISE"] # [inline (always)] pub fn ccctl_01_zcond_cc_trig_rise (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_ZCOND_A :: CCCTL_01_ZCOND_CC_TRIG_RISE) } # [doc = "CC_TRIG_FALL"] # [inline (always)] pub fn ccctl_01_zcond_cc_trig_fall (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_ZCOND_A :: CCCTL_01_ZCOND_CC_TRIG_FALL) } # [doc = "CC_TRIG_EDGE"] # [inline (always)] pub fn ccctl_01_zcond_cc_trig_edge (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_ZCOND_A :: CCCTL_01_ZCOND_CC_TRIG_EDGE) } } # [doc = "Field `CCCTL_01_COC` reader - Capture or Compare. #br# Specifies whether the corresponding CC register is used as a capture register or a compare register (never both)."] pub type CCCTL_01_COC_R = crate :: BitReader < CCCTL_01_COC_A > ; # [doc = "Capture or Compare. #br# Specifies whether the corresponding CC register is used as a capture register or a compare register (never both).\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CCCTL_01_COC_A { # [doc = "0: COMPARE"] CCCTL_01_COC_COMPARE = 0 , # [doc = "1: CAPTURE"] CCCTL_01_COC_CAPTURE = 1 , } impl From < CCCTL_01_COC_A > for bool { # [inline (always)] fn from (variant : CCCTL_01_COC_A) -> Self { variant as u8 != 0 } } impl CCCTL_01_COC_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CCCTL_01_COC_A { match self . bits { false => CCCTL_01_COC_A :: CCCTL_01_COC_COMPARE , true => CCCTL_01_COC_A :: CCCTL_01_COC_CAPTURE , } } # [doc = "COMPARE"] # [inline (always)] pub fn is_ccctl_01_coc_compare (& self) -> bool { * self == CCCTL_01_COC_A :: CCCTL_01_COC_COMPARE } # [doc = "CAPTURE"] # [inline (always)] pub fn is_ccctl_01_coc_capture (& self) -> bool { * self == CCCTL_01_COC_A :: CCCTL_01_COC_CAPTURE } } # [doc = "Field `CCCTL_01_COC` writer - Capture or Compare. #br# Specifies whether the corresponding CC register is used as a capture register or a compare register (never both)."] pub type CCCTL_01_COC_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CCCTL_01_COC_A > ; impl < 'a , REG , const O : u8 > CCCTL_01_COC_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "COMPARE"] # [inline (always)] pub fn ccctl_01_coc_compare (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_COC_A :: CCCTL_01_COC_COMPARE) } # [doc = "CAPTURE"] # [inline (always)] pub fn ccctl_01_coc_capture (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_COC_A :: CCCTL_01_COC_CAPTURE) } } # [doc = "Field `CCCTL_01_CCUPD` reader - Capture and Compare Update Method This field controls how updates to the pipelined capture and compare register are performed (when operating in compare mode, COC=0)."] pub type CCCTL_01_CCUPD_R = crate :: FieldReader < CCCTL_01_CCUPD_A > ; # [doc = "Capture and Compare Update Method This field controls how updates to the pipelined capture and compare register are performed (when operating in compare mode, COC=0).\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum CCCTL_01_CCUPD_A { # [doc = "0: IMMEDIATELY"] CCCTL_01_CCUPD_IMMEDIATELY = 0 , # [doc = "1: ZERO_EVT"] CCCTL_01_CCUPD_ZERO_EVT = 1 , # [doc = "2: COMPARE_DOWN_EVT"] CCCTL_01_CCUPD_COMPARE_DOWN_EVT = 2 , # [doc = "3: COMPARE_UP_EVT"] CCCTL_01_CCUPD_COMPARE_UP_EVT = 3 , # [doc = "4: ZERO_LOAD_EVT"] CCCTL_01_CCUPD_ZERO_LOAD_EVT = 4 , # [doc = "5: ZERO_RC_ZERO_EVT"] CCCTL_01_CCUPD_ZERO_RC_ZERO_EVT = 5 , # [doc = "6: TRIG"] CCCTL_01_CCUPD_TRIG = 6 , } impl From < CCCTL_01_CCUPD_A > for u8 { # [inline (always)] fn from (variant : CCCTL_01_CCUPD_A) -> Self { variant as _ } } impl crate :: FieldSpec for CCCTL_01_CCUPD_A { type Ux = u8 ; } impl CCCTL_01_CCUPD_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < CCCTL_01_CCUPD_A > { match self . bits { 0 => Some (CCCTL_01_CCUPD_A :: CCCTL_01_CCUPD_IMMEDIATELY) , 1 => Some (CCCTL_01_CCUPD_A :: CCCTL_01_CCUPD_ZERO_EVT) , 2 => Some (CCCTL_01_CCUPD_A :: CCCTL_01_CCUPD_COMPARE_DOWN_EVT) , 3 => Some (CCCTL_01_CCUPD_A :: CCCTL_01_CCUPD_COMPARE_UP_EVT) , 4 => Some (CCCTL_01_CCUPD_A :: CCCTL_01_CCUPD_ZERO_LOAD_EVT) , 5 => Some (CCCTL_01_CCUPD_A :: CCCTL_01_CCUPD_ZERO_RC_ZERO_EVT) , 6 => Some (CCCTL_01_CCUPD_A :: CCCTL_01_CCUPD_TRIG) , _ => None , } } # [doc = "IMMEDIATELY"] # [inline (always)] pub fn is_ccctl_01_ccupd_immediately (& self) -> bool { * self == CCCTL_01_CCUPD_A :: CCCTL_01_CCUPD_IMMEDIATELY } # [doc = "ZERO_EVT"] # [inline (always)] pub fn is_ccctl_01_ccupd_zero_evt (& self) -> bool { * self == CCCTL_01_CCUPD_A :: CCCTL_01_CCUPD_ZERO_EVT } # [doc = "COMPARE_DOWN_EVT"] # [inline (always)] pub fn is_ccctl_01_ccupd_compare_down_evt (& self) -> bool { * self == CCCTL_01_CCUPD_A :: CCCTL_01_CCUPD_COMPARE_DOWN_EVT } # [doc = "COMPARE_UP_EVT"] # [inline (always)] pub fn is_ccctl_01_ccupd_compare_up_evt (& self) -> bool { * self == CCCTL_01_CCUPD_A :: CCCTL_01_CCUPD_COMPARE_UP_EVT } # [doc = "ZERO_LOAD_EVT"] # [inline (always)] pub fn is_ccctl_01_ccupd_zero_load_evt (& self) -> bool { * self == CCCTL_01_CCUPD_A :: CCCTL_01_CCUPD_ZERO_LOAD_EVT } # [doc = "ZERO_RC_ZERO_EVT"] # [inline (always)] pub fn is_ccctl_01_ccupd_zero_rc_zero_evt (& self) -> bool { * self == CCCTL_01_CCUPD_A :: CCCTL_01_CCUPD_ZERO_RC_ZERO_EVT } # [doc = "TRIG"] # [inline (always)] pub fn is_ccctl_01_ccupd_trig (& self) -> bool { * self == CCCTL_01_CCUPD_A :: CCCTL_01_CCUPD_TRIG } } # [doc = "Field `CCCTL_01_CCUPD` writer - Capture and Compare Update Method This field controls how updates to the pipelined capture and compare register are performed (when operating in compare mode, COC=0)."] pub type CCCTL_01_CCUPD_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 3 , O , CCCTL_01_CCUPD_A > ; impl < 'a , REG , const O : u8 > CCCTL_01_CCUPD_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "IMMEDIATELY"] # [inline (always)] pub fn ccctl_01_ccupd_immediately (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CCUPD_A :: CCCTL_01_CCUPD_IMMEDIATELY) } # [doc = "ZERO_EVT"] # [inline (always)] pub fn ccctl_01_ccupd_zero_evt (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CCUPD_A :: CCCTL_01_CCUPD_ZERO_EVT) } # [doc = "COMPARE_DOWN_EVT"] # [inline (always)] pub fn ccctl_01_ccupd_compare_down_evt (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CCUPD_A :: CCCTL_01_CCUPD_COMPARE_DOWN_EVT) } # [doc = "COMPARE_UP_EVT"] # [inline (always)] pub fn ccctl_01_ccupd_compare_up_evt (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CCUPD_A :: CCCTL_01_CCUPD_COMPARE_UP_EVT) } # [doc = "ZERO_LOAD_EVT"] # [inline (always)] pub fn ccctl_01_ccupd_zero_load_evt (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CCUPD_A :: CCCTL_01_CCUPD_ZERO_LOAD_EVT) } # [doc = "ZERO_RC_ZERO_EVT"] # [inline (always)] pub fn ccctl_01_ccupd_zero_rc_zero_evt (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CCUPD_A :: CCCTL_01_CCUPD_ZERO_RC_ZERO_EVT) } # [doc = "TRIG"] # [inline (always)] pub fn ccctl_01_ccupd_trig (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CCUPD_A :: CCCTL_01_CCUPD_TRIG) } } # [doc = "Field `CCCTL_01_CC2SELU` reader - Selects the source second CCU event."] pub type CCCTL_01_CC2SELU_R = crate :: FieldReader < CCCTL_01_CC2SELU_A > ; # [doc = "Selects the source second CCU event.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum CCCTL_01_CC2SELU_A { # [doc = "0: SEL_CCU0"] CCCTL_01_CC2SELU_SEL_CCU0 = 0 , # [doc = "1: SEL_CCU1"] CCCTL_01_CC2SELU_SEL_CCU1 = 1 , # [doc = "2: SEL_CCU2"] CCCTL_01_CC2SELU_SEL_CCU2 = 2 , # [doc = "3: SEL_CCU3"] CCCTL_01_CC2SELU_SEL_CCU3 = 3 , # [doc = "4: SEL_CCU4"] CCCTL_01_CC2SELU_SEL_CCU4 = 4 , # [doc = "5: SEL_CCU5"] CCCTL_01_CC2SELU_SEL_CCU5 = 5 , } impl From < CCCTL_01_CC2SELU_A > for u8 { # [inline (always)] fn from (variant : CCCTL_01_CC2SELU_A) -> Self { variant as _ } } impl crate :: FieldSpec for CCCTL_01_CC2SELU_A { type Ux = u8 ; } impl CCCTL_01_CC2SELU_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < CCCTL_01_CC2SELU_A > { match self . bits { 0 => Some (CCCTL_01_CC2SELU_A :: CCCTL_01_CC2SELU_SEL_CCU0) , 1 => Some (CCCTL_01_CC2SELU_A :: CCCTL_01_CC2SELU_SEL_CCU1) , 2 => Some (CCCTL_01_CC2SELU_A :: CCCTL_01_CC2SELU_SEL_CCU2) , 3 => Some (CCCTL_01_CC2SELU_A :: CCCTL_01_CC2SELU_SEL_CCU3) , 4 => Some (CCCTL_01_CC2SELU_A :: CCCTL_01_CC2SELU_SEL_CCU4) , 5 => Some (CCCTL_01_CC2SELU_A :: CCCTL_01_CC2SELU_SEL_CCU5) , _ => None , } } # [doc = "SEL_CCU0"] # [inline (always)] pub fn is_ccctl_01_cc2selu_sel_ccu0 (& self) -> bool { * self == CCCTL_01_CC2SELU_A :: CCCTL_01_CC2SELU_SEL_CCU0 } # [doc = "SEL_CCU1"] # [inline (always)] pub fn is_ccctl_01_cc2selu_sel_ccu1 (& self) -> bool { * self == CCCTL_01_CC2SELU_A :: CCCTL_01_CC2SELU_SEL_CCU1 } # [doc = "SEL_CCU2"] # [inline (always)] pub fn is_ccctl_01_cc2selu_sel_ccu2 (& self) -> bool { * self == CCCTL_01_CC2SELU_A :: CCCTL_01_CC2SELU_SEL_CCU2 } # [doc = "SEL_CCU3"] # [inline (always)] pub fn is_ccctl_01_cc2selu_sel_ccu3 (& self) -> bool { * self == CCCTL_01_CC2SELU_A :: CCCTL_01_CC2SELU_SEL_CCU3 } # [doc = "SEL_CCU4"] # [inline (always)] pub fn is_ccctl_01_cc2selu_sel_ccu4 (& self) -> bool { * self == CCCTL_01_CC2SELU_A :: CCCTL_01_CC2SELU_SEL_CCU4 } # [doc = "SEL_CCU5"] # [inline (always)] pub fn is_ccctl_01_cc2selu_sel_ccu5 (& self) -> bool { * self == CCCTL_01_CC2SELU_A :: CCCTL_01_CC2SELU_SEL_CCU5 } } # [doc = "Field `CCCTL_01_CC2SELU` writer - Selects the source second CCU event."] pub type CCCTL_01_CC2SELU_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 3 , O , CCCTL_01_CC2SELU_A > ; impl < 'a , REG , const O : u8 > CCCTL_01_CC2SELU_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "SEL_CCU0"] # [inline (always)] pub fn ccctl_01_cc2selu_sel_ccu0 (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CC2SELU_A :: CCCTL_01_CC2SELU_SEL_CCU0) } # [doc = "SEL_CCU1"] # [inline (always)] pub fn ccctl_01_cc2selu_sel_ccu1 (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CC2SELU_A :: CCCTL_01_CC2SELU_SEL_CCU1) } # [doc = "SEL_CCU2"] # [inline (always)] pub fn ccctl_01_cc2selu_sel_ccu2 (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CC2SELU_A :: CCCTL_01_CC2SELU_SEL_CCU2) } # [doc = "SEL_CCU3"] # [inline (always)] pub fn ccctl_01_cc2selu_sel_ccu3 (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CC2SELU_A :: CCCTL_01_CC2SELU_SEL_CCU3) } # [doc = "SEL_CCU4"] # [inline (always)] pub fn ccctl_01_cc2selu_sel_ccu4 (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CC2SELU_A :: CCCTL_01_CC2SELU_SEL_CCU4) } # [doc = "SEL_CCU5"] # [inline (always)] pub fn ccctl_01_cc2selu_sel_ccu5 (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CC2SELU_A :: CCCTL_01_CC2SELU_SEL_CCU5) } } # [doc = "Field `CCCTL_01_CCACTUPD` reader - CCACT shadow register Update Method This field controls how updates to the CCCACT shadow register are performed"] pub type CCCTL_01_CCACTUPD_R = crate :: FieldReader < CCCTL_01_CCACTUPD_A > ; # [doc = "CCACT shadow register Update Method This field controls how updates to the CCCACT shadow register are performed\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum CCCTL_01_CCACTUPD_A { # [doc = "0: IMMEDIATELY"] CCCTL_01_CCACTUPD_IMMEDIATELY = 0 , # [doc = "1: ZERO_EVT"] CCCTL_01_CCACTUPD_ZERO_EVT = 1 , # [doc = "2: COMPARE_DOWN_EVT"] CCCTL_01_CCACTUPD_COMPARE_DOWN_EVT = 2 , # [doc = "3: COMPARE_UP_EVT"] CCCTL_01_CCACTUPD_COMPARE_UP_EVT = 3 , # [doc = "4: ZERO_LOAD_EVT"] CCCTL_01_CCACTUPD_ZERO_LOAD_EVT = 4 , # [doc = "5: ZERO_RC_ZERO_EVT"] CCCTL_01_CCACTUPD_ZERO_RC_ZERO_EVT = 5 , # [doc = "6: TRIG"] CCCTL_01_CCACTUPD_TRIG = 6 , } impl From < CCCTL_01_CCACTUPD_A > for u8 { # [inline (always)] fn from (variant : CCCTL_01_CCACTUPD_A) -> Self { variant as _ } } impl crate :: FieldSpec for CCCTL_01_CCACTUPD_A { type Ux = u8 ; } impl CCCTL_01_CCACTUPD_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < CCCTL_01_CCACTUPD_A > { match self . bits { 0 => Some (CCCTL_01_CCACTUPD_A :: CCCTL_01_CCACTUPD_IMMEDIATELY) , 1 => Some (CCCTL_01_CCACTUPD_A :: CCCTL_01_CCACTUPD_ZERO_EVT) , 2 => Some (CCCTL_01_CCACTUPD_A :: CCCTL_01_CCACTUPD_COMPARE_DOWN_EVT) , 3 => Some (CCCTL_01_CCACTUPD_A :: CCCTL_01_CCACTUPD_COMPARE_UP_EVT) , 4 => Some (CCCTL_01_CCACTUPD_A :: CCCTL_01_CCACTUPD_ZERO_LOAD_EVT) , 5 => Some (CCCTL_01_CCACTUPD_A :: CCCTL_01_CCACTUPD_ZERO_RC_ZERO_EVT) , 6 => Some (CCCTL_01_CCACTUPD_A :: CCCTL_01_CCACTUPD_TRIG) , _ => None , } } # [doc = "IMMEDIATELY"] # [inline (always)] pub fn is_ccctl_01_ccactupd_immediately (& self) -> bool { * self == CCCTL_01_CCACTUPD_A :: CCCTL_01_CCACTUPD_IMMEDIATELY } # [doc = "ZERO_EVT"] # [inline (always)] pub fn is_ccctl_01_ccactupd_zero_evt (& self) -> bool { * self == CCCTL_01_CCACTUPD_A :: CCCTL_01_CCACTUPD_ZERO_EVT } # [doc = "COMPARE_DOWN_EVT"] # [inline (always)] pub fn is_ccctl_01_ccactupd_compare_down_evt (& self) -> bool { * self == CCCTL_01_CCACTUPD_A :: CCCTL_01_CCACTUPD_COMPARE_DOWN_EVT } # [doc = "COMPARE_UP_EVT"] # [inline (always)] pub fn is_ccctl_01_ccactupd_compare_up_evt (& self) -> bool { * self == CCCTL_01_CCACTUPD_A :: CCCTL_01_CCACTUPD_COMPARE_UP_EVT } # [doc = "ZERO_LOAD_EVT"] # [inline (always)] pub fn is_ccctl_01_ccactupd_zero_load_evt (& self) -> bool { * self == CCCTL_01_CCACTUPD_A :: CCCTL_01_CCACTUPD_ZERO_LOAD_EVT } # [doc = "ZERO_RC_ZERO_EVT"] # [inline (always)] pub fn is_ccctl_01_ccactupd_zero_rc_zero_evt (& self) -> bool { * self == CCCTL_01_CCACTUPD_A :: CCCTL_01_CCACTUPD_ZERO_RC_ZERO_EVT } # [doc = "TRIG"] # [inline (always)] pub fn is_ccctl_01_ccactupd_trig (& self) -> bool { * self == CCCTL_01_CCACTUPD_A :: CCCTL_01_CCACTUPD_TRIG } } # [doc = "Field `CCCTL_01_CCACTUPD` writer - CCACT shadow register Update Method This field controls how updates to the CCCACT shadow register are performed"] pub type CCCTL_01_CCACTUPD_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 3 , O , CCCTL_01_CCACTUPD_A > ; impl < 'a , REG , const O : u8 > CCCTL_01_CCACTUPD_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "IMMEDIATELY"] # [inline (always)] pub fn ccctl_01_ccactupd_immediately (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CCACTUPD_A :: CCCTL_01_CCACTUPD_IMMEDIATELY) } # [doc = "ZERO_EVT"] # [inline (always)] pub fn ccctl_01_ccactupd_zero_evt (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CCACTUPD_A :: CCCTL_01_CCACTUPD_ZERO_EVT) } # [doc = "COMPARE_DOWN_EVT"] # [inline (always)] pub fn ccctl_01_ccactupd_compare_down_evt (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CCACTUPD_A :: CCCTL_01_CCACTUPD_COMPARE_DOWN_EVT) } # [doc = "COMPARE_UP_EVT"] # [inline (always)] pub fn ccctl_01_ccactupd_compare_up_evt (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CCACTUPD_A :: CCCTL_01_CCACTUPD_COMPARE_UP_EVT) } # [doc = "ZERO_LOAD_EVT"] # [inline (always)] pub fn ccctl_01_ccactupd_zero_load_evt (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CCACTUPD_A :: CCCTL_01_CCACTUPD_ZERO_LOAD_EVT) } # [doc = "ZERO_RC_ZERO_EVT"] # [inline (always)] pub fn ccctl_01_ccactupd_zero_rc_zero_evt (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CCACTUPD_A :: CCCTL_01_CCACTUPD_ZERO_RC_ZERO_EVT) } # [doc = "TRIG"] # [inline (always)] pub fn ccctl_01_ccactupd_trig (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CCACTUPD_A :: CCCTL_01_CCACTUPD_TRIG) } } # [doc = "Field `CCCTL_01_CC2SELD` reader - Selects the source second CCD event."] pub type CCCTL_01_CC2SELD_R = crate :: FieldReader < CCCTL_01_CC2SELD_A > ; # [doc = "Selects the source second CCD event.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum CCCTL_01_CC2SELD_A { # [doc = "0: SEL_CCD0"] CCCTL_01_CC2SELD_SEL_CCD0 = 0 , # [doc = "1: SEL_CCD1"] CCCTL_01_CC2SELD_SEL_CCD1 = 1 , # [doc = "2: SEL_CCD2"] CCCTL_01_CC2SELD_SEL_CCD2 = 2 , # [doc = "3: SEL_CCD3"] CCCTL_01_CC2SELD_SEL_CCD3 = 3 , # [doc = "4: SEL_CCD4"] CCCTL_01_CC2SELD_SEL_CCD4 = 4 , # [doc = "5: SEL_CCD5"] CCCTL_01_CC2SELD_SEL_CCD5 = 5 , } impl From < CCCTL_01_CC2SELD_A > for u8 { # [inline (always)] fn from (variant : CCCTL_01_CC2SELD_A) -> Self { variant as _ } } impl crate :: FieldSpec for CCCTL_01_CC2SELD_A { type Ux = u8 ; } impl CCCTL_01_CC2SELD_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < CCCTL_01_CC2SELD_A > { match self . bits { 0 => Some (CCCTL_01_CC2SELD_A :: CCCTL_01_CC2SELD_SEL_CCD0) , 1 => Some (CCCTL_01_CC2SELD_A :: CCCTL_01_CC2SELD_SEL_CCD1) , 2 => Some (CCCTL_01_CC2SELD_A :: CCCTL_01_CC2SELD_SEL_CCD2) , 3 => Some (CCCTL_01_CC2SELD_A :: CCCTL_01_CC2SELD_SEL_CCD3) , 4 => Some (CCCTL_01_CC2SELD_A :: CCCTL_01_CC2SELD_SEL_CCD4) , 5 => Some (CCCTL_01_CC2SELD_A :: CCCTL_01_CC2SELD_SEL_CCD5) , _ => None , } } # [doc = "SEL_CCD0"] # [inline (always)] pub fn is_ccctl_01_cc2seld_sel_ccd0 (& self) -> bool { * self == CCCTL_01_CC2SELD_A :: CCCTL_01_CC2SELD_SEL_CCD0 } # [doc = "SEL_CCD1"] # [inline (always)] pub fn is_ccctl_01_cc2seld_sel_ccd1 (& self) -> bool { * self == CCCTL_01_CC2SELD_A :: CCCTL_01_CC2SELD_SEL_CCD1 } # [doc = "SEL_CCD2"] # [inline (always)] pub fn is_ccctl_01_cc2seld_sel_ccd2 (& self) -> bool { * self == CCCTL_01_CC2SELD_A :: CCCTL_01_CC2SELD_SEL_CCD2 } # [doc = "SEL_CCD3"] # [inline (always)] pub fn is_ccctl_01_cc2seld_sel_ccd3 (& self) -> bool { * self == CCCTL_01_CC2SELD_A :: CCCTL_01_CC2SELD_SEL_CCD3 } # [doc = "SEL_CCD4"] # [inline (always)] pub fn is_ccctl_01_cc2seld_sel_ccd4 (& self) -> bool { * self == CCCTL_01_CC2SELD_A :: CCCTL_01_CC2SELD_SEL_CCD4 } # [doc = "SEL_CCD5"] # [inline (always)] pub fn is_ccctl_01_cc2seld_sel_ccd5 (& self) -> bool { * self == CCCTL_01_CC2SELD_A :: CCCTL_01_CC2SELD_SEL_CCD5 } } # [doc = "Field `CCCTL_01_CC2SELD` writer - Selects the source second CCD event."] pub type CCCTL_01_CC2SELD_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 3 , O , CCCTL_01_CC2SELD_A > ; impl < 'a , REG , const O : u8 > CCCTL_01_CC2SELD_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "SEL_CCD0"] # [inline (always)] pub fn ccctl_01_cc2seld_sel_ccd0 (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CC2SELD_A :: CCCTL_01_CC2SELD_SEL_CCD0) } # [doc = "SEL_CCD1"] # [inline (always)] pub fn ccctl_01_cc2seld_sel_ccd1 (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CC2SELD_A :: CCCTL_01_CC2SELD_SEL_CCD1) } # [doc = "SEL_CCD2"] # [inline (always)] pub fn ccctl_01_cc2seld_sel_ccd2 (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CC2SELD_A :: CCCTL_01_CC2SELD_SEL_CCD2) } # [doc = "SEL_CCD3"] # [inline (always)] pub fn ccctl_01_cc2seld_sel_ccd3 (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CC2SELD_A :: CCCTL_01_CC2SELD_SEL_CCD3) } # [doc = "SEL_CCD4"] # [inline (always)] pub fn ccctl_01_cc2seld_sel_ccd4 (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CC2SELD_A :: CCCTL_01_CC2SELD_SEL_CCD4) } # [doc = "SEL_CCD5"] # [inline (always)] pub fn ccctl_01_cc2seld_sel_ccd5 (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CC2SELD_A :: CCCTL_01_CC2SELD_SEL_CCD5) } } impl R { # [doc = "Bits 0:2 - Capture Condition. #br# Specifies the condition that generates a capture pulse. 4h-Fh = Reserved"] # [inline (always)] pub fn ccctl_01_ccond (& self) -> CCCTL_01_CCOND_R { CCCTL_01_CCOND_R :: new ((self . bits & 7) as u8) } # [doc = "Bits 4:6 - Advance Condition. #br# Specifies the condition that generates an advance pulse. 6h-Fh = Reserved"] # [inline (always)] pub fn ccctl_01_acond (& self) -> CCCTL_01_ACOND_R { CCCTL_01_ACOND_R :: new (((self . bits >> 4) & 7) as u8) } # [doc = "Bits 8:10 - Load Condition. #br# Specifies the condition that generates a load pulse. 4h-Fh = Reserved"] # [inline (always)] pub fn ccctl_01_lcond (& self) -> CCCTL_01_LCOND_R { CCCTL_01_LCOND_R :: new (((self . bits >> 8) & 7) as u8) } # [doc = "Bits 12:14 - Zero Condition. #br# This field specifies the condition that generates a zero pulse. 4h-Fh = Reserved"] # [inline (always)] pub fn ccctl_01_zcond (& self) -> CCCTL_01_ZCOND_R { CCCTL_01_ZCOND_R :: new (((self . bits >> 12) & 7) as u8) } # [doc = "Bit 17 - Capture or Compare. #br# Specifies whether the corresponding CC register is used as a capture register or a compare register (never both)."] # [inline (always)] pub fn ccctl_01_coc (& self) -> CCCTL_01_COC_R { CCCTL_01_COC_R :: new (((self . bits >> 17) & 1) != 0) } # [doc = "Bits 18:20 - Capture and Compare Update Method This field controls how updates to the pipelined capture and compare register are performed (when operating in compare mode, COC=0)."] # [inline (always)] pub fn ccctl_01_ccupd (& self) -> CCCTL_01_CCUPD_R { CCCTL_01_CCUPD_R :: new (((self . bits >> 18) & 7) as u8) } # [doc = "Bits 22:24 - Selects the source second CCU event."] # [inline (always)] pub fn ccctl_01_cc2selu (& self) -> CCCTL_01_CC2SELU_R { CCCTL_01_CC2SELU_R :: new (((self . bits >> 22) & 7) as u8) } # [doc = "Bits 26:28 - CCACT shadow register Update Method This field controls how updates to the CCCACT shadow register are performed"] # [inline (always)] pub fn ccctl_01_ccactupd (& self) -> CCCTL_01_CCACTUPD_R { CCCTL_01_CCACTUPD_R :: new (((self . bits >> 26) & 7) as u8) } # [doc = "Bits 29:31 - Selects the source second CCD event."] # [inline (always)] pub fn ccctl_01_cc2seld (& self) -> CCCTL_01_CC2SELD_R { CCCTL_01_CC2SELD_R :: new (((self . bits >> 29) & 7) as u8) } } impl W { # [doc = "Bits 0:2 - Capture Condition. #br# Specifies the condition that generates a capture pulse. 4h-Fh = Reserved"] # [inline (always)] # [must_use] pub fn ccctl_01_ccond (& mut self) -> CCCTL_01_CCOND_W <'_, CCCTL_01_SPEC , 0 > { CCCTL_01_CCOND_W :: new (self) } # [doc = "Bits 4:6 - Advance Condition. #br# Specifies the condition that generates an advance pulse. 6h-Fh = Reserved"] # [inline (always)] # [must_use] pub fn ccctl_01_acond (& mut self) -> CCCTL_01_ACOND_W < CCCTL_01_SPEC , 4 > { CCCTL_01_ACOND_W :: new (self) } # [doc = "Bits 8:10 - Load Condition. #br# Specifies the condition that generates a load pulse. 4h-Fh = Reserved"] # [inline (always)] # [must_use] pub fn ccctl_01_lcond (& mut self) -> CCCTL_01_LCOND_W < CCCTL_01_SPEC , 8 > { CCCTL_01_LCOND_W :: new (self) } # [doc = "Bits 12:14 - Zero Condition. #br# This field specifies the condition that generates a zero pulse. 4h-Fh = Reserved"] # [inline (always)] # [must_use] pub fn ccctl_01_zcond (& mut self) -> CCCTL_01_ZCOND_W < CCCTL_01_SPEC , 12 > { CCCTL_01_ZCOND_W :: new (self) } # [doc = "Bit 17 - Capture or Compare. #br# Specifies whether the corresponding CC register is used as a capture register or a compare register (never both)."] # [inline (always)] # [must_use] pub fn ccctl_01_coc (& mut self) -> CCCTL_01_COC_W < CCCTL_01_SPEC , 17 > { CCCTL_01_COC_W :: new (self) } # [doc = "Bits 18:20 - Capture and Compare Update Method This field controls how updates to the pipelined capture and compare register are performed (when operating in compare mode, COC=0)."] # [inline (always)] # [must_use] pub fn ccctl_01_ccupd (& mut self) -> CCCTL_01_CCUPD_W < CCCTL_01_SPEC , 18 > { CCCTL_01_CCUPD_W :: new (self) } # [doc = "Bits 22:24 - Selects the source second CCU event."] # [inline (always)] # [must_use] pub fn ccctl_01_cc2selu (& mut self) -> CCCTL_01_CC2SELU_W < CCCTL_01_SPEC , 22 > { CCCTL_01_CC2SELU_W :: new (self) } # [doc = "Bits 26:28 - CCACT shadow register Update Method This field controls how updates to the CCCACT shadow register are performed"] # [inline (always)] # [must_use] pub fn ccctl_01_ccactupd (& mut self) -> CCCTL_01_CCACTUPD_W < CCCTL_01_SPEC , 26 > { CCCTL_01_CCACTUPD_W :: new (self) } # [doc = "Bits 29:31 - Selects the source second CCD event."] # [inline (always)] # [must_use] pub fn ccctl_01_cc2seld (& mut self) -> CCCTL_01_CC2SELD_W < CCCTL_01_SPEC , 29 > { CCCTL_01_CC2SELD_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Capture or Compare Control Registers\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ccctl_01::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ccctl_01::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CCCTL_01_SPEC ; impl crate :: RegisterSpec for CCCTL_01_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`ccctl_01::R`](R) reader structure"] impl crate :: Readable for CCCTL_01_SPEC { } # [doc = "`write(|w| ..)` method takes [`ccctl_01::W`](W) writer structure"] impl crate :: Writable for CCCTL_01_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets CCCTL_01[%s] [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/opa1/ctl.rs:1:1892 [INFO] [stdout] | [INFO] [stdout] 1 | ...ust_use] pub fn ctl_enable (& mut self) -> CTL_ENABLE_W < CTL_SPEC , 0 > { CTL_ENABLE_W :: new (self) } # [doc = r" Writes raw bits to... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `CTL` reader"] pub type R = crate :: R < CTL_SPEC > ; # [doc = "Register `CTL` writer"] pub type W = crate :: W < CTL_SPEC > ; # [doc = "Field `CTL_ENABLE` reader - OAxn Enable."] pub type CTL_ENABLE_R = crate :: BitReader < CTL_ENABLE_A > ; # [doc = "OAxn Enable.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CTL_ENABLE_A { # [doc = "0: OFF"] CTL_ENABLE_OFF = 0 , # [doc = "1: ON"] CTL_ENABLE_ON = 1 , } impl From < CTL_ENABLE_A > for bool { # [inline (always)] fn from (variant : CTL_ENABLE_A) -> Self { variant as u8 != 0 } } impl CTL_ENABLE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CTL_ENABLE_A { match self . bits { false => CTL_ENABLE_A :: CTL_ENABLE_OFF , true => CTL_ENABLE_A :: CTL_ENABLE_ON , } } # [doc = "OFF"] # [inline (always)] pub fn is_ctl_enable_off (& self) -> bool { * self == CTL_ENABLE_A :: CTL_ENABLE_OFF } # [doc = "ON"] # [inline (always)] pub fn is_ctl_enable_on (& self) -> bool { * self == CTL_ENABLE_A :: CTL_ENABLE_ON } } # [doc = "Field `CTL_ENABLE` writer - OAxn Enable."] pub type CTL_ENABLE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL_ENABLE_A > ; impl < 'a , REG , const O : u8 > CTL_ENABLE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "OFF"] # [inline (always)] pub fn ctl_enable_off (self) -> & 'a mut crate :: W < REG > { self . variant (CTL_ENABLE_A :: CTL_ENABLE_OFF) } # [doc = "ON"] # [inline (always)] pub fn ctl_enable_on (self) -> & 'a mut crate :: W < REG > { self . variant (CTL_ENABLE_A :: CTL_ENABLE_ON) } } impl R { # [doc = "Bit 0 - OAxn Enable."] # [inline (always)] pub fn ctl_enable (& self) -> CTL_ENABLE_R { CTL_ENABLE_R :: new ((self . bits & 1) != 0) } } impl W { # [doc = "Bit 0 - OAxn Enable."] # [inline (always)] # [must_use] pub fn ctl_enable (& mut self) -> CTL_ENABLE_W <'_, CTL_SPEC , 0 > { CTL_ENABLE_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CTL_SPEC ; impl crate :: RegisterSpec for CTL_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`ctl::R`](R) reader structure"] impl crate :: Readable for CTL_SPEC { } # [doc = "`write(|w| ..)` method takes [`ctl::W`](W) writer structure"] impl crate :: Writable for CTL_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets CTL to value 0"] impl crate :: Resettable for CTL_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/i2c1/mfifoctl.rs:1:12308 [INFO] [stdout] | [INFO] [stdout] 1 | ...ub fn mfifoctl_txtrig (& mut self) -> MFIFOCTL_TXTRIG_W < MFIFOCTL_SPEC , 0 > { MFIFOCTL_TXTRIG_W :: new (self) } # [doc = "Bit 7 - TX... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `MFIFOCTL` reader"] pub type R = crate :: R < MFIFOCTL_SPEC > ; # [doc = "Register `MFIFOCTL` writer"] pub type W = crate :: W < MFIFOCTL_SPEC > ; # [doc = "Field `MFIFOCTL_TXTRIG` reader - TX FIFO Trigger Indicates at what fill level in the TX FIFO a trigger will be generated."] pub type MFIFOCTL_TXTRIG_R = crate :: FieldReader < MFIFOCTL_TXTRIG_A > ; # [doc = "TX FIFO Trigger Indicates at what fill level in the TX FIFO a trigger will be generated.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum MFIFOCTL_TXTRIG_A { # [doc = "4: LEVEL_4"] MFIFOCTL_TXTRIG_LEVEL_4 = 4 , # [doc = "5: LEVEL_5"] MFIFOCTL_TXTRIG_LEVEL_5 = 5 , # [doc = "6: LEVEL_6"] MFIFOCTL_TXTRIG_LEVEL_6 = 6 , # [doc = "7: LEVEL_7"] MFIFOCTL_TXTRIG_LEVEL_7 = 7 , } impl From < MFIFOCTL_TXTRIG_A > for u8 { # [inline (always)] fn from (variant : MFIFOCTL_TXTRIG_A) -> Self { variant as _ } } impl crate :: FieldSpec for MFIFOCTL_TXTRIG_A { type Ux = u8 ; } impl MFIFOCTL_TXTRIG_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < MFIFOCTL_TXTRIG_A > { match self . bits { 4 => Some (MFIFOCTL_TXTRIG_A :: MFIFOCTL_TXTRIG_LEVEL_4) , 5 => Some (MFIFOCTL_TXTRIG_A :: MFIFOCTL_TXTRIG_LEVEL_5) , 6 => Some (MFIFOCTL_TXTRIG_A :: MFIFOCTL_TXTRIG_LEVEL_6) , 7 => Some (MFIFOCTL_TXTRIG_A :: MFIFOCTL_TXTRIG_LEVEL_7) , _ => None , } } # [doc = "LEVEL_4"] # [inline (always)] pub fn is_mfifoctl_txtrig_level_4 (& self) -> bool { * self == MFIFOCTL_TXTRIG_A :: MFIFOCTL_TXTRIG_LEVEL_4 } # [doc = "LEVEL_5"] # [inline (always)] pub fn is_mfifoctl_txtrig_level_5 (& self) -> bool { * self == MFIFOCTL_TXTRIG_A :: MFIFOCTL_TXTRIG_LEVEL_5 } # [doc = "LEVEL_6"] # [inline (always)] pub fn is_mfifoctl_txtrig_level_6 (& self) -> bool { * self == MFIFOCTL_TXTRIG_A :: MFIFOCTL_TXTRIG_LEVEL_6 } # [doc = "LEVEL_7"] # [inline (always)] pub fn is_mfifoctl_txtrig_level_7 (& self) -> bool { * self == MFIFOCTL_TXTRIG_A :: MFIFOCTL_TXTRIG_LEVEL_7 } } # [doc = "Field `MFIFOCTL_TXTRIG` writer - TX FIFO Trigger Indicates at what fill level in the TX FIFO a trigger will be generated."] pub type MFIFOCTL_TXTRIG_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 3 , O , MFIFOCTL_TXTRIG_A > ; impl < 'a , REG , const O : u8 > MFIFOCTL_TXTRIG_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "LEVEL_4"] # [inline (always)] pub fn mfifoctl_txtrig_level_4 (self) -> & 'a mut crate :: W < REG > { self . variant (MFIFOCTL_TXTRIG_A :: MFIFOCTL_TXTRIG_LEVEL_4) } # [doc = "LEVEL_5"] # [inline (always)] pub fn mfifoctl_txtrig_level_5 (self) -> & 'a mut crate :: W < REG > { self . variant (MFIFOCTL_TXTRIG_A :: MFIFOCTL_TXTRIG_LEVEL_5) } # [doc = "LEVEL_6"] # [inline (always)] pub fn mfifoctl_txtrig_level_6 (self) -> & 'a mut crate :: W < REG > { self . variant (MFIFOCTL_TXTRIG_A :: MFIFOCTL_TXTRIG_LEVEL_6) } # [doc = "LEVEL_7"] # [inline (always)] pub fn mfifoctl_txtrig_level_7 (self) -> & 'a mut crate :: W < REG > { self . variant (MFIFOCTL_TXTRIG_A :: MFIFOCTL_TXTRIG_LEVEL_7) } } # [doc = "Field `MFIFOCTL_TXFLUSH` reader - TX FIFO Flush Setting this bit will Flush the TX FIFO. Before reseting this bit to stop Flush the TXFIFOCNT should be checked to be 8 and indicating that the Flush has completed."] pub type MFIFOCTL_TXFLUSH_R = crate :: BitReader < MFIFOCTL_TXFLUSH_A > ; # [doc = "TX FIFO Flush Setting this bit will Flush the TX FIFO. Before reseting this bit to stop Flush the TXFIFOCNT should be checked to be 8 and indicating that the Flush has completed.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum MFIFOCTL_TXFLUSH_A { # [doc = "0: NOFLUSH"] MFIFOCTL_TXFLUSH_NOFLUSH = 0 , # [doc = "1: FLUSH"] MFIFOCTL_TXFLUSH_FLUSH = 1 , } impl From < MFIFOCTL_TXFLUSH_A > for bool { # [inline (always)] fn from (variant : MFIFOCTL_TXFLUSH_A) -> Self { variant as u8 != 0 } } impl MFIFOCTL_TXFLUSH_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> MFIFOCTL_TXFLUSH_A { match self . bits { false => MFIFOCTL_TXFLUSH_A :: MFIFOCTL_TXFLUSH_NOFLUSH , true => MFIFOCTL_TXFLUSH_A :: MFIFOCTL_TXFLUSH_FLUSH , } } # [doc = "NOFLUSH"] # [inline (always)] pub fn is_mfifoctl_txflush_noflush (& self) -> bool { * self == MFIFOCTL_TXFLUSH_A :: MFIFOCTL_TXFLUSH_NOFLUSH } # [doc = "FLUSH"] # [inline (always)] pub fn is_mfifoctl_txflush_flush (& self) -> bool { * self == MFIFOCTL_TXFLUSH_A :: MFIFOCTL_TXFLUSH_FLUSH } } # [doc = "Field `MFIFOCTL_TXFLUSH` writer - TX FIFO Flush Setting this bit will Flush the TX FIFO. Before reseting this bit to stop Flush the TXFIFOCNT should be checked to be 8 and indicating that the Flush has completed."] pub type MFIFOCTL_TXFLUSH_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , MFIFOCTL_TXFLUSH_A > ; impl < 'a , REG , const O : u8 > MFIFOCTL_TXFLUSH_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NOFLUSH"] # [inline (always)] pub fn mfifoctl_txflush_noflush (self) -> & 'a mut crate :: W < REG > { self . variant (MFIFOCTL_TXFLUSH_A :: MFIFOCTL_TXFLUSH_NOFLUSH) } # [doc = "FLUSH"] # [inline (always)] pub fn mfifoctl_txflush_flush (self) -> & 'a mut crate :: W < REG > { self . variant (MFIFOCTL_TXFLUSH_A :: MFIFOCTL_TXFLUSH_FLUSH) } } # [doc = "Field `MFIFOCTL_RXTRIG` reader - RX FIFO Trigger Indicates at what fill level in the RX FIFO a trigger will be generated. Note: Programming RXTRIG to 0x0 has no effect since no data is present to transfer out of RX FIFO."] pub type MFIFOCTL_RXTRIG_R = crate :: FieldReader < MFIFOCTL_RXTRIG_A > ; # [doc = "RX FIFO Trigger Indicates at what fill level in the RX FIFO a trigger will be generated. Note: Programming RXTRIG to 0x0 has no effect since no data is present to transfer out of RX FIFO.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum MFIFOCTL_RXTRIG_A { # [doc = "4: LEVEL_5"] MFIFOCTL_RXTRIG_LEVEL_5 = 4 , # [doc = "5: LEVEL_6"] MFIFOCTL_RXTRIG_LEVEL_6 = 5 , # [doc = "6: LEVEL_7"] MFIFOCTL_RXTRIG_LEVEL_7 = 6 , # [doc = "7: LEVEL_8"] MFIFOCTL_RXTRIG_LEVEL_8 = 7 , } impl From < MFIFOCTL_RXTRIG_A > for u8 { # [inline (always)] fn from (variant : MFIFOCTL_RXTRIG_A) -> Self { variant as _ } } impl crate :: FieldSpec for MFIFOCTL_RXTRIG_A { type Ux = u8 ; } impl MFIFOCTL_RXTRIG_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < MFIFOCTL_RXTRIG_A > { match self . bits { 4 => Some (MFIFOCTL_RXTRIG_A :: MFIFOCTL_RXTRIG_LEVEL_5) , 5 => Some (MFIFOCTL_RXTRIG_A :: MFIFOCTL_RXTRIG_LEVEL_6) , 6 => Some (MFIFOCTL_RXTRIG_A :: MFIFOCTL_RXTRIG_LEVEL_7) , 7 => Some (MFIFOCTL_RXTRIG_A :: MFIFOCTL_RXTRIG_LEVEL_8) , _ => None , } } # [doc = "LEVEL_5"] # [inline (always)] pub fn is_mfifoctl_rxtrig_level_5 (& self) -> bool { * self == MFIFOCTL_RXTRIG_A :: MFIFOCTL_RXTRIG_LEVEL_5 } # [doc = "LEVEL_6"] # [inline (always)] pub fn is_mfifoctl_rxtrig_level_6 (& self) -> bool { * self == MFIFOCTL_RXTRIG_A :: MFIFOCTL_RXTRIG_LEVEL_6 } # [doc = "LEVEL_7"] # [inline (always)] pub fn is_mfifoctl_rxtrig_level_7 (& self) -> bool { * self == MFIFOCTL_RXTRIG_A :: MFIFOCTL_RXTRIG_LEVEL_7 } # [doc = "LEVEL_8"] # [inline (always)] pub fn is_mfifoctl_rxtrig_level_8 (& self) -> bool { * self == MFIFOCTL_RXTRIG_A :: MFIFOCTL_RXTRIG_LEVEL_8 } } # [doc = "Field `MFIFOCTL_RXTRIG` writer - RX FIFO Trigger Indicates at what fill level in the RX FIFO a trigger will be generated. Note: Programming RXTRIG to 0x0 has no effect since no data is present to transfer out of RX FIFO."] pub type MFIFOCTL_RXTRIG_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 3 , O , MFIFOCTL_RXTRIG_A > ; impl < 'a , REG , const O : u8 > MFIFOCTL_RXTRIG_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "LEVEL_5"] # [inline (always)] pub fn mfifoctl_rxtrig_level_5 (self) -> & 'a mut crate :: W < REG > { self . variant (MFIFOCTL_RXTRIG_A :: MFIFOCTL_RXTRIG_LEVEL_5) } # [doc = "LEVEL_6"] # [inline (always)] pub fn mfifoctl_rxtrig_level_6 (self) -> & 'a mut crate :: W < REG > { self . variant (MFIFOCTL_RXTRIG_A :: MFIFOCTL_RXTRIG_LEVEL_6) } # [doc = "LEVEL_7"] # [inline (always)] pub fn mfifoctl_rxtrig_level_7 (self) -> & 'a mut crate :: W < REG > { self . variant (MFIFOCTL_RXTRIG_A :: MFIFOCTL_RXTRIG_LEVEL_7) } # [doc = "LEVEL_8"] # [inline (always)] pub fn mfifoctl_rxtrig_level_8 (self) -> & 'a mut crate :: W < REG > { self . variant (MFIFOCTL_RXTRIG_A :: MFIFOCTL_RXTRIG_LEVEL_8) } } # [doc = "Field `MFIFOCTL_RXFLUSH` reader - RX FIFO Flush Setting this bit will Flush the RX FIFO. Before reseting this bit to stop Flush the RXFIFOCNT should be checked to be 0 and indicating that the Flush has completed."] pub type MFIFOCTL_RXFLUSH_R = crate :: BitReader < MFIFOCTL_RXFLUSH_A > ; # [doc = "RX FIFO Flush Setting this bit will Flush the RX FIFO. Before reseting this bit to stop Flush the RXFIFOCNT should be checked to be 0 and indicating that the Flush has completed.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum MFIFOCTL_RXFLUSH_A { # [doc = "0: NOFLUSH"] MFIFOCTL_RXFLUSH_NOFLUSH = 0 , # [doc = "1: FLUSH"] MFIFOCTL_RXFLUSH_FLUSH = 1 , } impl From < MFIFOCTL_RXFLUSH_A > for bool { # [inline (always)] fn from (variant : MFIFOCTL_RXFLUSH_A) -> Self { variant as u8 != 0 } } impl MFIFOCTL_RXFLUSH_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> MFIFOCTL_RXFLUSH_A { match self . bits { false => MFIFOCTL_RXFLUSH_A :: MFIFOCTL_RXFLUSH_NOFLUSH , true => MFIFOCTL_RXFLUSH_A :: MFIFOCTL_RXFLUSH_FLUSH , } } # [doc = "NOFLUSH"] # [inline (always)] pub fn is_mfifoctl_rxflush_noflush (& self) -> bool { * self == MFIFOCTL_RXFLUSH_A :: MFIFOCTL_RXFLUSH_NOFLUSH } # [doc = "FLUSH"] # [inline (always)] pub fn is_mfifoctl_rxflush_flush (& self) -> bool { * self == MFIFOCTL_RXFLUSH_A :: MFIFOCTL_RXFLUSH_FLUSH } } # [doc = "Field `MFIFOCTL_RXFLUSH` writer - RX FIFO Flush Setting this bit will Flush the RX FIFO. Before reseting this bit to stop Flush the RXFIFOCNT should be checked to be 0 and indicating that the Flush has completed."] pub type MFIFOCTL_RXFLUSH_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , MFIFOCTL_RXFLUSH_A > ; impl < 'a , REG , const O : u8 > MFIFOCTL_RXFLUSH_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NOFLUSH"] # [inline (always)] pub fn mfifoctl_rxflush_noflush (self) -> & 'a mut crate :: W < REG > { self . variant (MFIFOCTL_RXFLUSH_A :: MFIFOCTL_RXFLUSH_NOFLUSH) } # [doc = "FLUSH"] # [inline (always)] pub fn mfifoctl_rxflush_flush (self) -> & 'a mut crate :: W < REG > { self . variant (MFIFOCTL_RXFLUSH_A :: MFIFOCTL_RXFLUSH_FLUSH) } } impl R { # [doc = "Bits 0:2 - TX FIFO Trigger Indicates at what fill level in the TX FIFO a trigger will be generated."] # [inline (always)] pub fn mfifoctl_txtrig (& self) -> MFIFOCTL_TXTRIG_R { MFIFOCTL_TXTRIG_R :: new ((self . bits & 7) as u8) } # [doc = "Bit 7 - TX FIFO Flush Setting this bit will Flush the TX FIFO. Before reseting this bit to stop Flush the TXFIFOCNT should be checked to be 8 and indicating that the Flush has completed."] # [inline (always)] pub fn mfifoctl_txflush (& self) -> MFIFOCTL_TXFLUSH_R { MFIFOCTL_TXFLUSH_R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bits 8:10 - RX FIFO Trigger Indicates at what fill level in the RX FIFO a trigger will be generated. Note: Programming RXTRIG to 0x0 has no effect since no data is present to transfer out of RX FIFO."] # [inline (always)] pub fn mfifoctl_rxtrig (& self) -> MFIFOCTL_RXTRIG_R { MFIFOCTL_RXTRIG_R :: new (((self . bits >> 8) & 7) as u8) } # [doc = "Bit 15 - RX FIFO Flush Setting this bit will Flush the RX FIFO. Before reseting this bit to stop Flush the RXFIFOCNT should be checked to be 0 and indicating that the Flush has completed."] # [inline (always)] pub fn mfifoctl_rxflush (& self) -> MFIFOCTL_RXFLUSH_R { MFIFOCTL_RXFLUSH_R :: new (((self . bits >> 15) & 1) != 0) } } impl W { # [doc = "Bits 0:2 - TX FIFO Trigger Indicates at what fill level in the TX FIFO a trigger will be generated."] # [inline (always)] # [must_use] pub fn mfifoctl_txtrig (& mut self) -> MFIFOCTL_TXTRIG_W <'_, MFIFOCTL_SPEC , 0 > { MFIFOCTL_TXTRIG_W :: new (self) } # [doc = "Bit 7 - TX FIFO Flush Setting this bit will Flush the TX FIFO. Before reseting this bit to stop Flush the TXFIFOCNT should be checked to be 8 and indicating that the Flush has completed."] # [inline (always)] # [must_use] pub fn mfifoctl_txflush (& mut self) -> MFIFOCTL_TXFLUSH_W < MFIFOCTL_SPEC , 7 > { MFIFOCTL_TXFLUSH_W :: new (self) } # [doc = "Bits 8:10 - RX FIFO Trigger Indicates at what fill level in the RX FIFO a trigger will be generated. Note: Programming RXTRIG to 0x0 has no effect since no data is present to transfer out of RX FIFO."] # [inline (always)] # [must_use] pub fn mfifoctl_rxtrig (& mut self) -> MFIFOCTL_RXTRIG_W < MFIFOCTL_SPEC , 8 > { MFIFOCTL_RXTRIG_W :: new (self) } # [doc = "Bit 15 - RX FIFO Flush Setting this bit will Flush the RX FIFO. Before reseting this bit to stop Flush the RXFIFOCNT should be checked to be 0 and indicating that the Flush has completed."] # [inline (always)] # [must_use] pub fn mfifoctl_rxflush (& mut self) -> MFIFOCTL_RXFLUSH_W < MFIFOCTL_SPEC , 15 > { MFIFOCTL_RXFLUSH_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "I2C Master FIFO Control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mfifoctl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mfifoctl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct MFIFOCTL_SPEC ; impl crate :: RegisterSpec for MFIFOCTL_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`mfifoctl::R`](R) reader structure"] impl crate :: Readable for MFIFOCTL_SPEC { } # [doc = "`write(|w| ..)` method takes [`mfifoctl::W`](W) writer structure"] impl crate :: Writable for MFIFOCTL_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets MFIFOCTL to value 0"] impl crate :: Resettable for MFIFOCTL_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/sysctl/imask.rs:1:4565 [INFO] [stdout] | [INFO] [stdout] 1 | ... pub fn imask_lfoscgood (& mut self) -> IMASK_LFOSCGOOD_W < IMASK_SPEC , 0 > { IMASK_LFOSCGOOD_W :: new (self) } # [doc = "Bit 1 - Ana... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `IMASK` reader"] pub type R = crate :: R < IMASK_SPEC > ; # [doc = "Register `IMASK` writer"] pub type W = crate :: W < IMASK_SPEC > ; # [doc = "Field `IMASK_LFOSCGOOD` reader - Enable or disable the LFOSCGOOD interrupt. LFOSCGOOD indicates that the LFOSC has started successfully."] pub type IMASK_LFOSCGOOD_R = crate :: BitReader < IMASK_LFOSCGOOD_A > ; # [doc = "Enable or disable the LFOSCGOOD interrupt. LFOSCGOOD indicates that the LFOSC has started successfully.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum IMASK_LFOSCGOOD_A { # [doc = "0: DISABLE"] IMASK_LFOSCGOOD_DISABLE = 0 , # [doc = "1: ENABLE"] IMASK_LFOSCGOOD_ENABLE = 1 , } impl From < IMASK_LFOSCGOOD_A > for bool { # [inline (always)] fn from (variant : IMASK_LFOSCGOOD_A) -> Self { variant as u8 != 0 } } impl IMASK_LFOSCGOOD_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> IMASK_LFOSCGOOD_A { match self . bits { false => IMASK_LFOSCGOOD_A :: IMASK_LFOSCGOOD_DISABLE , true => IMASK_LFOSCGOOD_A :: IMASK_LFOSCGOOD_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_imask_lfoscgood_disable (& self) -> bool { * self == IMASK_LFOSCGOOD_A :: IMASK_LFOSCGOOD_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_imask_lfoscgood_enable (& self) -> bool { * self == IMASK_LFOSCGOOD_A :: IMASK_LFOSCGOOD_ENABLE } } # [doc = "Field `IMASK_LFOSCGOOD` writer - Enable or disable the LFOSCGOOD interrupt. LFOSCGOOD indicates that the LFOSC has started successfully."] pub type IMASK_LFOSCGOOD_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , IMASK_LFOSCGOOD_A > ; impl < 'a , REG , const O : u8 > IMASK_LFOSCGOOD_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn imask_lfoscgood_disable (self) -> & 'a mut crate :: W < REG > { self . variant (IMASK_LFOSCGOOD_A :: IMASK_LFOSCGOOD_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn imask_lfoscgood_enable (self) -> & 'a mut crate :: W < REG > { self . variant (IMASK_LFOSCGOOD_A :: IMASK_LFOSCGOOD_ENABLE) } } # [doc = "Field `IMASK_ANACLKERR` reader - Analog Clocking Consistency Error"] pub type IMASK_ANACLKERR_R = crate :: BitReader < IMASK_ANACLKERR_A > ; # [doc = "Analog Clocking Consistency Error\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum IMASK_ANACLKERR_A { # [doc = "0: DISABLE"] IMASK_ANACLKERR_DISABLE = 0 , # [doc = "1: ENABLE"] IMASK_ANACLKERR_ENABLE = 1 , } impl From < IMASK_ANACLKERR_A > for bool { # [inline (always)] fn from (variant : IMASK_ANACLKERR_A) -> Self { variant as u8 != 0 } } impl IMASK_ANACLKERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> IMASK_ANACLKERR_A { match self . bits { false => IMASK_ANACLKERR_A :: IMASK_ANACLKERR_DISABLE , true => IMASK_ANACLKERR_A :: IMASK_ANACLKERR_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_imask_anaclkerr_disable (& self) -> bool { * self == IMASK_ANACLKERR_A :: IMASK_ANACLKERR_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_imask_anaclkerr_enable (& self) -> bool { * self == IMASK_ANACLKERR_A :: IMASK_ANACLKERR_ENABLE } } # [doc = "Field `IMASK_ANACLKERR` writer - Analog Clocking Consistency Error"] pub type IMASK_ANACLKERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , IMASK_ANACLKERR_A > ; impl < 'a , REG , const O : u8 > IMASK_ANACLKERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn imask_anaclkerr_disable (self) -> & 'a mut crate :: W < REG > { self . variant (IMASK_ANACLKERR_A :: IMASK_ANACLKERR_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn imask_anaclkerr_enable (self) -> & 'a mut crate :: W < REG > { self . variant (IMASK_ANACLKERR_A :: IMASK_ANACLKERR_ENABLE) } } impl R { # [doc = "Bit 0 - Enable or disable the LFOSCGOOD interrupt. LFOSCGOOD indicates that the LFOSC has started successfully."] # [inline (always)] pub fn imask_lfoscgood (& self) -> IMASK_LFOSCGOOD_R { IMASK_LFOSCGOOD_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - Analog Clocking Consistency Error"] # [inline (always)] pub fn imask_anaclkerr (& self) -> IMASK_ANACLKERR_R { IMASK_ANACLKERR_R :: new (((self . bits >> 1) & 1) != 0) } } impl W { # [doc = "Bit 0 - Enable or disable the LFOSCGOOD interrupt. LFOSCGOOD indicates that the LFOSC has started successfully."] # [inline (always)] # [must_use] pub fn imask_lfoscgood (& mut self) -> IMASK_LFOSCGOOD_W <'_, IMASK_SPEC , 0 > { IMASK_LFOSCGOOD_W :: new (self) } # [doc = "Bit 1 - Analog Clocking Consistency Error"] # [inline (always)] # [must_use] pub fn imask_anaclkerr (& mut self) -> IMASK_ANACLKERR_W < IMASK_SPEC , 1 > { IMASK_ANACLKERR_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "SYSCTL interrupt mask\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`imask::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`imask::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct IMASK_SPEC ; impl crate :: RegisterSpec for IMASK_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`imask::R`](R) reader structure"] impl crate :: Readable for IMASK_SPEC { } # [doc = "`write(|w| ..)` method takes [`imask::W`](W) writer structure"] impl crate :: Writable for IMASK_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets IMASK to value 0"] impl crate :: Resettable for IMASK_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/uart0/rstctl.rs:1:3243 [INFO] [stdout] | [INFO] [stdout] 1 | ...fn rstctl_resetassert (& mut self) -> RSTCTL_RESETASSERT_W < RSTCTL_SPEC , 0 > { RSTCTL_RESETASSERT_W :: new (self) } # [doc = "Bit 1 ... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `RSTCTL` writer"] pub type W = crate :: W < RSTCTL_SPEC > ; # [doc = "Assert reset to the peripheral\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum RSTCTL_RESETASSERT_AW { # [doc = "0: NOP"] RSTCTL_RESETASSERT_NOP = 0 , # [doc = "1: ASSERT"] RSTCTL_RESETASSERT_ASSERT = 1 , } impl From < RSTCTL_RESETASSERT_AW > for bool { # [inline (always)] fn from (variant : RSTCTL_RESETASSERT_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `RSTCTL_RESETASSERT` writer - Assert reset to the peripheral"] pub type RSTCTL_RESETASSERT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , RSTCTL_RESETASSERT_AW > ; impl < 'a , REG , const O : u8 > RSTCTL_RESETASSERT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NOP"] # [inline (always)] pub fn rstctl_resetassert_nop (self) -> & 'a mut crate :: W < REG > { self . variant (RSTCTL_RESETASSERT_AW :: RSTCTL_RESETASSERT_NOP) } # [doc = "ASSERT"] # [inline (always)] pub fn rstctl_resetassert_assert (self) -> & 'a mut crate :: W < REG > { self . variant (RSTCTL_RESETASSERT_AW :: RSTCTL_RESETASSERT_ASSERT) } } # [doc = "Clear the RESETSTKY bit in the STAT register\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum RSTCTL_RESETSTKYCLR_AW { # [doc = "0: NOP"] RSTCTL_RESETSTKYCLR_NOP = 0 , # [doc = "1: CLR"] RSTCTL_RESETSTKYCLR_CLR = 1 , } impl From < RSTCTL_RESETSTKYCLR_AW > for bool { # [inline (always)] fn from (variant : RSTCTL_RESETSTKYCLR_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `RSTCTL_RESETSTKYCLR` writer - Clear the RESETSTKY bit in the STAT register"] pub type RSTCTL_RESETSTKYCLR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , RSTCTL_RESETSTKYCLR_AW > ; impl < 'a , REG , const O : u8 > RSTCTL_RESETSTKYCLR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NOP"] # [inline (always)] pub fn rstctl_resetstkyclr_nop (self) -> & 'a mut crate :: W < REG > { self . variant (RSTCTL_RESETSTKYCLR_AW :: RSTCTL_RESETSTKYCLR_NOP) } # [doc = "CLR"] # [inline (always)] pub fn rstctl_resetstkyclr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (RSTCTL_RESETSTKYCLR_AW :: RSTCTL_RESETSTKYCLR_CLR) } } # [doc = "Unlock key\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum RSTCTL_KEY_AW { # [doc = "177: _TO_UNLOCK_W_"] RSTCTL_KEY_UNLOCK_W = 177 , } impl From < RSTCTL_KEY_AW > for u8 { # [inline (always)] fn from (variant : RSTCTL_KEY_AW) -> Self { variant as _ } } impl crate :: FieldSpec for RSTCTL_KEY_AW { type Ux = u8 ; } # [doc = "Field `RSTCTL_KEY` writer - Unlock key"] pub type RSTCTL_KEY_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 8 , O , RSTCTL_KEY_AW > ; impl < 'a , REG , const O : u8 > RSTCTL_KEY_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "_TO_UNLOCK_W_"] # [inline (always)] pub fn rstctl_key_unlock_w (self) -> & 'a mut crate :: W < REG > { self . variant (RSTCTL_KEY_AW :: RSTCTL_KEY_UNLOCK_W) } } impl W { # [doc = "Bit 0 - Assert reset to the peripheral"] # [inline (always)] # [must_use] pub fn rstctl_resetassert (& mut self) -> RSTCTL_RESETASSERT_W <'_, RSTCTL_SPEC , 0 > { RSTCTL_RESETASSERT_W :: new (self) } # [doc = "Bit 1 - Clear the RESETSTKY bit in the STAT register"] # [inline (always)] # [must_use] pub fn rstctl_resetstkyclr (& mut self) -> RSTCTL_RESETSTKYCLR_W < RSTCTL_SPEC , 1 > { RSTCTL_RESETSTKYCLR_W :: new (self) } # [doc = "Bits 24:31 - Unlock key"] # [inline (always)] # [must_use] pub fn rstctl_key (& mut self) -> RSTCTL_KEY_W < RSTCTL_SPEC , 24 > { RSTCTL_KEY_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Reset Control\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rstctl::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct RSTCTL_SPEC ; impl crate :: RegisterSpec for RSTCTL_SPEC { type Ux = u32 ; } # [doc = "`write(|w| ..)` method takes [`rstctl::W`](W) writer structure"] impl crate :: Writable for RSTCTL_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets RSTCTL to value 0"] impl crate :: Resettable for RSTCTL_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/timg4/ccctl_01.rs:1:33975 [INFO] [stdout] | [INFO] [stdout] 1 | ... pub fn ccctl_01_acond (& mut self) -> CCCTL_01_ACOND_W < CCCTL_01_SPEC , 4 > { CCCTL_01_ACOND_W :: new (self) } # [doc = "Bits 8:10 -... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `CCCTL_01[%s]` reader"] pub type R = crate :: R < CCCTL_01_SPEC > ; # [doc = "Register `CCCTL_01[%s]` writer"] pub type W = crate :: W < CCCTL_01_SPEC > ; # [doc = "Field `CCCTL_01_CCOND` reader - Capture Condition. #br# Specifies the condition that generates a capture pulse. 4h-Fh = Reserved"] pub type CCCTL_01_CCOND_R = crate :: FieldReader < CCCTL_01_CCOND_A > ; # [doc = "Capture Condition. #br# Specifies the condition that generates a capture pulse. 4h-Fh = Reserved\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum CCCTL_01_CCOND_A { # [doc = "0: NOCAPTURE"] CCCTL_01_CCOND_NOCAPTURE = 0 , # [doc = "1: CC_TRIG_RISE"] CCCTL_01_CCOND_CC_TRIG_RISE = 1 , # [doc = "2: CC_TRIG_FALL"] CCCTL_01_CCOND_CC_TRIG_FALL = 2 , # [doc = "3: CC_TRIG_EDGE"] CCCTL_01_CCOND_CC_TRIG_EDGE = 3 , } impl From < CCCTL_01_CCOND_A > for u8 { # [inline (always)] fn from (variant : CCCTL_01_CCOND_A) -> Self { variant as _ } } impl crate :: FieldSpec for CCCTL_01_CCOND_A { type Ux = u8 ; } impl CCCTL_01_CCOND_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < CCCTL_01_CCOND_A > { match self . bits { 0 => Some (CCCTL_01_CCOND_A :: CCCTL_01_CCOND_NOCAPTURE) , 1 => Some (CCCTL_01_CCOND_A :: CCCTL_01_CCOND_CC_TRIG_RISE) , 2 => Some (CCCTL_01_CCOND_A :: CCCTL_01_CCOND_CC_TRIG_FALL) , 3 => Some (CCCTL_01_CCOND_A :: CCCTL_01_CCOND_CC_TRIG_EDGE) , _ => None , } } # [doc = "NOCAPTURE"] # [inline (always)] pub fn is_ccctl_01_ccond_nocapture (& self) -> bool { * self == CCCTL_01_CCOND_A :: CCCTL_01_CCOND_NOCAPTURE } # [doc = "CC_TRIG_RISE"] # [inline (always)] pub fn is_ccctl_01_ccond_cc_trig_rise (& self) -> bool { * self == CCCTL_01_CCOND_A :: CCCTL_01_CCOND_CC_TRIG_RISE } # [doc = "CC_TRIG_FALL"] # [inline (always)] pub fn is_ccctl_01_ccond_cc_trig_fall (& self) -> bool { * self == CCCTL_01_CCOND_A :: CCCTL_01_CCOND_CC_TRIG_FALL } # [doc = "CC_TRIG_EDGE"] # [inline (always)] pub fn is_ccctl_01_ccond_cc_trig_edge (& self) -> bool { * self == CCCTL_01_CCOND_A :: CCCTL_01_CCOND_CC_TRIG_EDGE } } # [doc = "Field `CCCTL_01_CCOND` writer - Capture Condition. #br# Specifies the condition that generates a capture pulse. 4h-Fh = Reserved"] pub type CCCTL_01_CCOND_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 3 , O , CCCTL_01_CCOND_A > ; impl < 'a , REG , const O : u8 > CCCTL_01_CCOND_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "NOCAPTURE"] # [inline (always)] pub fn ccctl_01_ccond_nocapture (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CCOND_A :: CCCTL_01_CCOND_NOCAPTURE) } # [doc = "CC_TRIG_RISE"] # [inline (always)] pub fn ccctl_01_ccond_cc_trig_rise (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CCOND_A :: CCCTL_01_CCOND_CC_TRIG_RISE) } # [doc = "CC_TRIG_FALL"] # [inline (always)] pub fn ccctl_01_ccond_cc_trig_fall (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CCOND_A :: CCCTL_01_CCOND_CC_TRIG_FALL) } # [doc = "CC_TRIG_EDGE"] # [inline (always)] pub fn ccctl_01_ccond_cc_trig_edge (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CCOND_A :: CCCTL_01_CCOND_CC_TRIG_EDGE) } } # [doc = "Field `CCCTL_01_ACOND` reader - Advance Condition. #br# Specifies the condition that generates an advance pulse. 6h-Fh = Reserved"] pub type CCCTL_01_ACOND_R = crate :: FieldReader < CCCTL_01_ACOND_A > ; # [doc = "Advance Condition. #br# Specifies the condition that generates an advance pulse. 6h-Fh = Reserved\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum CCCTL_01_ACOND_A { # [doc = "0: TIMCLK"] CCCTL_01_ACOND_TIMCLK = 0 , # [doc = "1: CC_TRIG_RISE"] CCCTL_01_ACOND_CC_TRIG_RISE = 1 , # [doc = "2: CC_TRIG_FALL"] CCCTL_01_ACOND_CC_TRIG_FALL = 2 , # [doc = "3: CC_TRIG_EDGE"] CCCTL_01_ACOND_CC_TRIG_EDGE = 3 , # [doc = "5: CC_TRIG_HIGH"] CCCTL_01_ACOND_CC_TRIG_HIGH = 5 , } impl From < CCCTL_01_ACOND_A > for u8 { # [inline (always)] fn from (variant : CCCTL_01_ACOND_A) -> Self { variant as _ } } impl crate :: FieldSpec for CCCTL_01_ACOND_A { type Ux = u8 ; } impl CCCTL_01_ACOND_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < CCCTL_01_ACOND_A > { match self . bits { 0 => Some (CCCTL_01_ACOND_A :: CCCTL_01_ACOND_TIMCLK) , 1 => Some (CCCTL_01_ACOND_A :: CCCTL_01_ACOND_CC_TRIG_RISE) , 2 => Some (CCCTL_01_ACOND_A :: CCCTL_01_ACOND_CC_TRIG_FALL) , 3 => Some (CCCTL_01_ACOND_A :: CCCTL_01_ACOND_CC_TRIG_EDGE) , 5 => Some (CCCTL_01_ACOND_A :: CCCTL_01_ACOND_CC_TRIG_HIGH) , _ => None , } } # [doc = "TIMCLK"] # [inline (always)] pub fn is_ccctl_01_acond_timclk (& self) -> bool { * self == CCCTL_01_ACOND_A :: CCCTL_01_ACOND_TIMCLK } # [doc = "CC_TRIG_RISE"] # [inline (always)] pub fn is_ccctl_01_acond_cc_trig_rise (& self) -> bool { * self == CCCTL_01_ACOND_A :: CCCTL_01_ACOND_CC_TRIG_RISE } # [doc = "CC_TRIG_FALL"] # [inline (always)] pub fn is_ccctl_01_acond_cc_trig_fall (& self) -> bool { * self == CCCTL_01_ACOND_A :: CCCTL_01_ACOND_CC_TRIG_FALL } # [doc = "CC_TRIG_EDGE"] # [inline (always)] pub fn is_ccctl_01_acond_cc_trig_edge (& self) -> bool { * self == CCCTL_01_ACOND_A :: CCCTL_01_ACOND_CC_TRIG_EDGE } # [doc = "CC_TRIG_HIGH"] # [inline (always)] pub fn is_ccctl_01_acond_cc_trig_high (& self) -> bool { * self == CCCTL_01_ACOND_A :: CCCTL_01_ACOND_CC_TRIG_HIGH } } # [doc = "Field `CCCTL_01_ACOND` writer - Advance Condition. #br# Specifies the condition that generates an advance pulse. 6h-Fh = Reserved"] pub type CCCTL_01_ACOND_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 3 , O , CCCTL_01_ACOND_A > ; impl < 'a , REG , const O : u8 > CCCTL_01_ACOND_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "TIMCLK"] # [inline (always)] pub fn ccctl_01_acond_timclk (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_ACOND_A :: CCCTL_01_ACOND_TIMCLK) } # [doc = "CC_TRIG_RISE"] # [inline (always)] pub fn ccctl_01_acond_cc_trig_rise (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_ACOND_A :: CCCTL_01_ACOND_CC_TRIG_RISE) } # [doc = "CC_TRIG_FALL"] # [inline (always)] pub fn ccctl_01_acond_cc_trig_fall (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_ACOND_A :: CCCTL_01_ACOND_CC_TRIG_FALL) } # [doc = "CC_TRIG_EDGE"] # [inline (always)] pub fn ccctl_01_acond_cc_trig_edge (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_ACOND_A :: CCCTL_01_ACOND_CC_TRIG_EDGE) } # [doc = "CC_TRIG_HIGH"] # [inline (always)] pub fn ccctl_01_acond_cc_trig_high (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_ACOND_A :: CCCTL_01_ACOND_CC_TRIG_HIGH) } } # [doc = "Field `CCCTL_01_LCOND` reader - Load Condition. #br# Specifies the condition that generates a load pulse. 4h-Fh = Reserved"] pub type CCCTL_01_LCOND_R = crate :: FieldReader < CCCTL_01_LCOND_A > ; # [doc = "Load Condition. #br# Specifies the condition that generates a load pulse. 4h-Fh = Reserved\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum CCCTL_01_LCOND_A { # [doc = "1: CC_TRIG_RISE"] CCCTL_01_LCOND_CC_TRIG_RISE = 1 , # [doc = "2: CC_TRIG_FALL"] CCCTL_01_LCOND_CC_TRIG_FALL = 2 , # [doc = "3: CC_TRIG_EDGE"] CCCTL_01_LCOND_CC_TRIG_EDGE = 3 , } impl From < CCCTL_01_LCOND_A > for u8 { # [inline (always)] fn from (variant : CCCTL_01_LCOND_A) -> Self { variant as _ } } impl crate :: FieldSpec for CCCTL_01_LCOND_A { type Ux = u8 ; } impl CCCTL_01_LCOND_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < CCCTL_01_LCOND_A > { match self . bits { 1 => Some (CCCTL_01_LCOND_A :: CCCTL_01_LCOND_CC_TRIG_RISE) , 2 => Some (CCCTL_01_LCOND_A :: CCCTL_01_LCOND_CC_TRIG_FALL) , 3 => Some (CCCTL_01_LCOND_A :: CCCTL_01_LCOND_CC_TRIG_EDGE) , _ => None , } } # [doc = "CC_TRIG_RISE"] # [inline (always)] pub fn is_ccctl_01_lcond_cc_trig_rise (& self) -> bool { * self == CCCTL_01_LCOND_A :: CCCTL_01_LCOND_CC_TRIG_RISE } # [doc = "CC_TRIG_FALL"] # [inline (always)] pub fn is_ccctl_01_lcond_cc_trig_fall (& self) -> bool { * self == CCCTL_01_LCOND_A :: CCCTL_01_LCOND_CC_TRIG_FALL } # [doc = "CC_TRIG_EDGE"] # [inline (always)] pub fn is_ccctl_01_lcond_cc_trig_edge (& self) -> bool { * self == CCCTL_01_LCOND_A :: CCCTL_01_LCOND_CC_TRIG_EDGE } } # [doc = "Field `CCCTL_01_LCOND` writer - Load Condition. #br# Specifies the condition that generates a load pulse. 4h-Fh = Reserved"] pub type CCCTL_01_LCOND_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 3 , O , CCCTL_01_LCOND_A > ; impl < 'a , REG , const O : u8 > CCCTL_01_LCOND_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "CC_TRIG_RISE"] # [inline (always)] pub fn ccctl_01_lcond_cc_trig_rise (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_LCOND_A :: CCCTL_01_LCOND_CC_TRIG_RISE) } # [doc = "CC_TRIG_FALL"] # [inline (always)] pub fn ccctl_01_lcond_cc_trig_fall (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_LCOND_A :: CCCTL_01_LCOND_CC_TRIG_FALL) } # [doc = "CC_TRIG_EDGE"] # [inline (always)] pub fn ccctl_01_lcond_cc_trig_edge (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_LCOND_A :: CCCTL_01_LCOND_CC_TRIG_EDGE) } } # [doc = "Field `CCCTL_01_ZCOND` reader - Zero Condition. #br# This field specifies the condition that generates a zero pulse. 4h-Fh = Reserved"] pub type CCCTL_01_ZCOND_R = crate :: FieldReader < CCCTL_01_ZCOND_A > ; # [doc = "Zero Condition. #br# This field specifies the condition that generates a zero pulse. 4h-Fh = Reserved\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum CCCTL_01_ZCOND_A { # [doc = "1: CC_TRIG_RISE"] CCCTL_01_ZCOND_CC_TRIG_RISE = 1 , # [doc = "2: CC_TRIG_FALL"] CCCTL_01_ZCOND_CC_TRIG_FALL = 2 , # [doc = "3: CC_TRIG_EDGE"] CCCTL_01_ZCOND_CC_TRIG_EDGE = 3 , } impl From < CCCTL_01_ZCOND_A > for u8 { # [inline (always)] fn from (variant : CCCTL_01_ZCOND_A) -> Self { variant as _ } } impl crate :: FieldSpec for CCCTL_01_ZCOND_A { type Ux = u8 ; } impl CCCTL_01_ZCOND_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < CCCTL_01_ZCOND_A > { match self . bits { 1 => Some (CCCTL_01_ZCOND_A :: CCCTL_01_ZCOND_CC_TRIG_RISE) , 2 => Some (CCCTL_01_ZCOND_A :: CCCTL_01_ZCOND_CC_TRIG_FALL) , 3 => Some (CCCTL_01_ZCOND_A :: CCCTL_01_ZCOND_CC_TRIG_EDGE) , _ => None , } } # [doc = "CC_TRIG_RISE"] # [inline (always)] pub fn is_ccctl_01_zcond_cc_trig_rise (& self) -> bool { * self == CCCTL_01_ZCOND_A :: CCCTL_01_ZCOND_CC_TRIG_RISE } # [doc = "CC_TRIG_FALL"] # [inline (always)] pub fn is_ccctl_01_zcond_cc_trig_fall (& self) -> bool { * self == CCCTL_01_ZCOND_A :: CCCTL_01_ZCOND_CC_TRIG_FALL } # [doc = "CC_TRIG_EDGE"] # [inline (always)] pub fn is_ccctl_01_zcond_cc_trig_edge (& self) -> bool { * self == CCCTL_01_ZCOND_A :: CCCTL_01_ZCOND_CC_TRIG_EDGE } } # [doc = "Field `CCCTL_01_ZCOND` writer - Zero Condition. #br# This field specifies the condition that generates a zero pulse. 4h-Fh = Reserved"] pub type CCCTL_01_ZCOND_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 3 , O , CCCTL_01_ZCOND_A > ; impl < 'a , REG , const O : u8 > CCCTL_01_ZCOND_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "CC_TRIG_RISE"] # [inline (always)] pub fn ccctl_01_zcond_cc_trig_rise (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_ZCOND_A :: CCCTL_01_ZCOND_CC_TRIG_RISE) } # [doc = "CC_TRIG_FALL"] # [inline (always)] pub fn ccctl_01_zcond_cc_trig_fall (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_ZCOND_A :: CCCTL_01_ZCOND_CC_TRIG_FALL) } # [doc = "CC_TRIG_EDGE"] # [inline (always)] pub fn ccctl_01_zcond_cc_trig_edge (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_ZCOND_A :: CCCTL_01_ZCOND_CC_TRIG_EDGE) } } # [doc = "Field `CCCTL_01_COC` reader - Capture or Compare. #br# Specifies whether the corresponding CC register is used as a capture register or a compare register (never both)."] pub type CCCTL_01_COC_R = crate :: BitReader < CCCTL_01_COC_A > ; # [doc = "Capture or Compare. #br# Specifies whether the corresponding CC register is used as a capture register or a compare register (never both).\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CCCTL_01_COC_A { # [doc = "0: COMPARE"] CCCTL_01_COC_COMPARE = 0 , # [doc = "1: CAPTURE"] CCCTL_01_COC_CAPTURE = 1 , } impl From < CCCTL_01_COC_A > for bool { # [inline (always)] fn from (variant : CCCTL_01_COC_A) -> Self { variant as u8 != 0 } } impl CCCTL_01_COC_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CCCTL_01_COC_A { match self . bits { false => CCCTL_01_COC_A :: CCCTL_01_COC_COMPARE , true => CCCTL_01_COC_A :: CCCTL_01_COC_CAPTURE , } } # [doc = "COMPARE"] # [inline (always)] pub fn is_ccctl_01_coc_compare (& self) -> bool { * self == CCCTL_01_COC_A :: CCCTL_01_COC_COMPARE } # [doc = "CAPTURE"] # [inline (always)] pub fn is_ccctl_01_coc_capture (& self) -> bool { * self == CCCTL_01_COC_A :: CCCTL_01_COC_CAPTURE } } # [doc = "Field `CCCTL_01_COC` writer - Capture or Compare. #br# Specifies whether the corresponding CC register is used as a capture register or a compare register (never both)."] pub type CCCTL_01_COC_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CCCTL_01_COC_A > ; impl < 'a , REG , const O : u8 > CCCTL_01_COC_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "COMPARE"] # [inline (always)] pub fn ccctl_01_coc_compare (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_COC_A :: CCCTL_01_COC_COMPARE) } # [doc = "CAPTURE"] # [inline (always)] pub fn ccctl_01_coc_capture (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_COC_A :: CCCTL_01_COC_CAPTURE) } } # [doc = "Field `CCCTL_01_CCUPD` reader - Capture and Compare Update Method This field controls how updates to the pipelined capture and compare register are performed (when operating in compare mode, COC=0)."] pub type CCCTL_01_CCUPD_R = crate :: FieldReader < CCCTL_01_CCUPD_A > ; # [doc = "Capture and Compare Update Method This field controls how updates to the pipelined capture and compare register are performed (when operating in compare mode, COC=0).\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum CCCTL_01_CCUPD_A { # [doc = "0: IMMEDIATELY"] CCCTL_01_CCUPD_IMMEDIATELY = 0 , # [doc = "1: ZERO_EVT"] CCCTL_01_CCUPD_ZERO_EVT = 1 , # [doc = "2: COMPARE_DOWN_EVT"] CCCTL_01_CCUPD_COMPARE_DOWN_EVT = 2 , # [doc = "3: COMPARE_UP_EVT"] CCCTL_01_CCUPD_COMPARE_UP_EVT = 3 , # [doc = "4: ZERO_LOAD_EVT"] CCCTL_01_CCUPD_ZERO_LOAD_EVT = 4 , # [doc = "5: ZERO_RC_ZERO_EVT"] CCCTL_01_CCUPD_ZERO_RC_ZERO_EVT = 5 , # [doc = "6: TRIG"] CCCTL_01_CCUPD_TRIG = 6 , } impl From < CCCTL_01_CCUPD_A > for u8 { # [inline (always)] fn from (variant : CCCTL_01_CCUPD_A) -> Self { variant as _ } } impl crate :: FieldSpec for CCCTL_01_CCUPD_A { type Ux = u8 ; } impl CCCTL_01_CCUPD_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < CCCTL_01_CCUPD_A > { match self . bits { 0 => Some (CCCTL_01_CCUPD_A :: CCCTL_01_CCUPD_IMMEDIATELY) , 1 => Some (CCCTL_01_CCUPD_A :: CCCTL_01_CCUPD_ZERO_EVT) , 2 => Some (CCCTL_01_CCUPD_A :: CCCTL_01_CCUPD_COMPARE_DOWN_EVT) , 3 => Some (CCCTL_01_CCUPD_A :: CCCTL_01_CCUPD_COMPARE_UP_EVT) , 4 => Some (CCCTL_01_CCUPD_A :: CCCTL_01_CCUPD_ZERO_LOAD_EVT) , 5 => Some (CCCTL_01_CCUPD_A :: CCCTL_01_CCUPD_ZERO_RC_ZERO_EVT) , 6 => Some (CCCTL_01_CCUPD_A :: CCCTL_01_CCUPD_TRIG) , _ => None , } } # [doc = "IMMEDIATELY"] # [inline (always)] pub fn is_ccctl_01_ccupd_immediately (& self) -> bool { * self == CCCTL_01_CCUPD_A :: CCCTL_01_CCUPD_IMMEDIATELY } # [doc = "ZERO_EVT"] # [inline (always)] pub fn is_ccctl_01_ccupd_zero_evt (& self) -> bool { * self == CCCTL_01_CCUPD_A :: CCCTL_01_CCUPD_ZERO_EVT } # [doc = "COMPARE_DOWN_EVT"] # [inline (always)] pub fn is_ccctl_01_ccupd_compare_down_evt (& self) -> bool { * self == CCCTL_01_CCUPD_A :: CCCTL_01_CCUPD_COMPARE_DOWN_EVT } # [doc = "COMPARE_UP_EVT"] # [inline (always)] pub fn is_ccctl_01_ccupd_compare_up_evt (& self) -> bool { * self == CCCTL_01_CCUPD_A :: CCCTL_01_CCUPD_COMPARE_UP_EVT } # [doc = "ZERO_LOAD_EVT"] # [inline (always)] pub fn is_ccctl_01_ccupd_zero_load_evt (& self) -> bool { * self == CCCTL_01_CCUPD_A :: CCCTL_01_CCUPD_ZERO_LOAD_EVT } # [doc = "ZERO_RC_ZERO_EVT"] # [inline (always)] pub fn is_ccctl_01_ccupd_zero_rc_zero_evt (& self) -> bool { * self == CCCTL_01_CCUPD_A :: CCCTL_01_CCUPD_ZERO_RC_ZERO_EVT } # [doc = "TRIG"] # [inline (always)] pub fn is_ccctl_01_ccupd_trig (& self) -> bool { * self == CCCTL_01_CCUPD_A :: CCCTL_01_CCUPD_TRIG } } # [doc = "Field `CCCTL_01_CCUPD` writer - Capture and Compare Update Method This field controls how updates to the pipelined capture and compare register are performed (when operating in compare mode, COC=0)."] pub type CCCTL_01_CCUPD_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 3 , O , CCCTL_01_CCUPD_A > ; impl < 'a , REG , const O : u8 > CCCTL_01_CCUPD_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "IMMEDIATELY"] # [inline (always)] pub fn ccctl_01_ccupd_immediately (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CCUPD_A :: CCCTL_01_CCUPD_IMMEDIATELY) } # [doc = "ZERO_EVT"] # [inline (always)] pub fn ccctl_01_ccupd_zero_evt (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CCUPD_A :: CCCTL_01_CCUPD_ZERO_EVT) } # [doc = "COMPARE_DOWN_EVT"] # [inline (always)] pub fn ccctl_01_ccupd_compare_down_evt (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CCUPD_A :: CCCTL_01_CCUPD_COMPARE_DOWN_EVT) } # [doc = "COMPARE_UP_EVT"] # [inline (always)] pub fn ccctl_01_ccupd_compare_up_evt (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CCUPD_A :: CCCTL_01_CCUPD_COMPARE_UP_EVT) } # [doc = "ZERO_LOAD_EVT"] # [inline (always)] pub fn ccctl_01_ccupd_zero_load_evt (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CCUPD_A :: CCCTL_01_CCUPD_ZERO_LOAD_EVT) } # [doc = "ZERO_RC_ZERO_EVT"] # [inline (always)] pub fn ccctl_01_ccupd_zero_rc_zero_evt (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CCUPD_A :: CCCTL_01_CCUPD_ZERO_RC_ZERO_EVT) } # [doc = "TRIG"] # [inline (always)] pub fn ccctl_01_ccupd_trig (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CCUPD_A :: CCCTL_01_CCUPD_TRIG) } } # [doc = "Field `CCCTL_01_CC2SELU` reader - Selects the source second CCU event."] pub type CCCTL_01_CC2SELU_R = crate :: FieldReader < CCCTL_01_CC2SELU_A > ; # [doc = "Selects the source second CCU event.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum CCCTL_01_CC2SELU_A { # [doc = "0: SEL_CCU0"] CCCTL_01_CC2SELU_SEL_CCU0 = 0 , # [doc = "1: SEL_CCU1"] CCCTL_01_CC2SELU_SEL_CCU1 = 1 , # [doc = "2: SEL_CCU2"] CCCTL_01_CC2SELU_SEL_CCU2 = 2 , # [doc = "3: SEL_CCU3"] CCCTL_01_CC2SELU_SEL_CCU3 = 3 , # [doc = "4: SEL_CCU4"] CCCTL_01_CC2SELU_SEL_CCU4 = 4 , # [doc = "5: SEL_CCU5"] CCCTL_01_CC2SELU_SEL_CCU5 = 5 , } impl From < CCCTL_01_CC2SELU_A > for u8 { # [inline (always)] fn from (variant : CCCTL_01_CC2SELU_A) -> Self { variant as _ } } impl crate :: FieldSpec for CCCTL_01_CC2SELU_A { type Ux = u8 ; } impl CCCTL_01_CC2SELU_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < CCCTL_01_CC2SELU_A > { match self . bits { 0 => Some (CCCTL_01_CC2SELU_A :: CCCTL_01_CC2SELU_SEL_CCU0) , 1 => Some (CCCTL_01_CC2SELU_A :: CCCTL_01_CC2SELU_SEL_CCU1) , 2 => Some (CCCTL_01_CC2SELU_A :: CCCTL_01_CC2SELU_SEL_CCU2) , 3 => Some (CCCTL_01_CC2SELU_A :: CCCTL_01_CC2SELU_SEL_CCU3) , 4 => Some (CCCTL_01_CC2SELU_A :: CCCTL_01_CC2SELU_SEL_CCU4) , 5 => Some (CCCTL_01_CC2SELU_A :: CCCTL_01_CC2SELU_SEL_CCU5) , _ => None , } } # [doc = "SEL_CCU0"] # [inline (always)] pub fn is_ccctl_01_cc2selu_sel_ccu0 (& self) -> bool { * self == CCCTL_01_CC2SELU_A :: CCCTL_01_CC2SELU_SEL_CCU0 } # [doc = "SEL_CCU1"] # [inline (always)] pub fn is_ccctl_01_cc2selu_sel_ccu1 (& self) -> bool { * self == CCCTL_01_CC2SELU_A :: CCCTL_01_CC2SELU_SEL_CCU1 } # [doc = "SEL_CCU2"] # [inline (always)] pub fn is_ccctl_01_cc2selu_sel_ccu2 (& self) -> bool { * self == CCCTL_01_CC2SELU_A :: CCCTL_01_CC2SELU_SEL_CCU2 } # [doc = "SEL_CCU3"] # [inline (always)] pub fn is_ccctl_01_cc2selu_sel_ccu3 (& self) -> bool { * self == CCCTL_01_CC2SELU_A :: CCCTL_01_CC2SELU_SEL_CCU3 } # [doc = "SEL_CCU4"] # [inline (always)] pub fn is_ccctl_01_cc2selu_sel_ccu4 (& self) -> bool { * self == CCCTL_01_CC2SELU_A :: CCCTL_01_CC2SELU_SEL_CCU4 } # [doc = "SEL_CCU5"] # [inline (always)] pub fn is_ccctl_01_cc2selu_sel_ccu5 (& self) -> bool { * self == CCCTL_01_CC2SELU_A :: CCCTL_01_CC2SELU_SEL_CCU5 } } # [doc = "Field `CCCTL_01_CC2SELU` writer - Selects the source second CCU event."] pub type CCCTL_01_CC2SELU_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 3 , O , CCCTL_01_CC2SELU_A > ; impl < 'a , REG , const O : u8 > CCCTL_01_CC2SELU_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "SEL_CCU0"] # [inline (always)] pub fn ccctl_01_cc2selu_sel_ccu0 (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CC2SELU_A :: CCCTL_01_CC2SELU_SEL_CCU0) } # [doc = "SEL_CCU1"] # [inline (always)] pub fn ccctl_01_cc2selu_sel_ccu1 (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CC2SELU_A :: CCCTL_01_CC2SELU_SEL_CCU1) } # [doc = "SEL_CCU2"] # [inline (always)] pub fn ccctl_01_cc2selu_sel_ccu2 (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CC2SELU_A :: CCCTL_01_CC2SELU_SEL_CCU2) } # [doc = "SEL_CCU3"] # [inline (always)] pub fn ccctl_01_cc2selu_sel_ccu3 (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CC2SELU_A :: CCCTL_01_CC2SELU_SEL_CCU3) } # [doc = "SEL_CCU4"] # [inline (always)] pub fn ccctl_01_cc2selu_sel_ccu4 (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CC2SELU_A :: CCCTL_01_CC2SELU_SEL_CCU4) } # [doc = "SEL_CCU5"] # [inline (always)] pub fn ccctl_01_cc2selu_sel_ccu5 (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CC2SELU_A :: CCCTL_01_CC2SELU_SEL_CCU5) } } # [doc = "Field `CCCTL_01_CCACTUPD` reader - CCACT shadow register Update Method This field controls how updates to the CCCACT shadow register are performed"] pub type CCCTL_01_CCACTUPD_R = crate :: FieldReader < CCCTL_01_CCACTUPD_A > ; # [doc = "CCACT shadow register Update Method This field controls how updates to the CCCACT shadow register are performed\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum CCCTL_01_CCACTUPD_A { # [doc = "0: IMMEDIATELY"] CCCTL_01_CCACTUPD_IMMEDIATELY = 0 , # [doc = "1: ZERO_EVT"] CCCTL_01_CCACTUPD_ZERO_EVT = 1 , # [doc = "2: COMPARE_DOWN_EVT"] CCCTL_01_CCACTUPD_COMPARE_DOWN_EVT = 2 , # [doc = "3: COMPARE_UP_EVT"] CCCTL_01_CCACTUPD_COMPARE_UP_EVT = 3 , # [doc = "4: ZERO_LOAD_EVT"] CCCTL_01_CCACTUPD_ZERO_LOAD_EVT = 4 , # [doc = "5: ZERO_RC_ZERO_EVT"] CCCTL_01_CCACTUPD_ZERO_RC_ZERO_EVT = 5 , # [doc = "6: TRIG"] CCCTL_01_CCACTUPD_TRIG = 6 , } impl From < CCCTL_01_CCACTUPD_A > for u8 { # [inline (always)] fn from (variant : CCCTL_01_CCACTUPD_A) -> Self { variant as _ } } impl crate :: FieldSpec for CCCTL_01_CCACTUPD_A { type Ux = u8 ; } impl CCCTL_01_CCACTUPD_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < CCCTL_01_CCACTUPD_A > { match self . bits { 0 => Some (CCCTL_01_CCACTUPD_A :: CCCTL_01_CCACTUPD_IMMEDIATELY) , 1 => Some (CCCTL_01_CCACTUPD_A :: CCCTL_01_CCACTUPD_ZERO_EVT) , 2 => Some (CCCTL_01_CCACTUPD_A :: CCCTL_01_CCACTUPD_COMPARE_DOWN_EVT) , 3 => Some (CCCTL_01_CCACTUPD_A :: CCCTL_01_CCACTUPD_COMPARE_UP_EVT) , 4 => Some (CCCTL_01_CCACTUPD_A :: CCCTL_01_CCACTUPD_ZERO_LOAD_EVT) , 5 => Some (CCCTL_01_CCACTUPD_A :: CCCTL_01_CCACTUPD_ZERO_RC_ZERO_EVT) , 6 => Some (CCCTL_01_CCACTUPD_A :: CCCTL_01_CCACTUPD_TRIG) , _ => None , } } # [doc = "IMMEDIATELY"] # [inline (always)] pub fn is_ccctl_01_ccactupd_immediately (& self) -> bool { * self == CCCTL_01_CCACTUPD_A :: CCCTL_01_CCACTUPD_IMMEDIATELY } # [doc = "ZERO_EVT"] # [inline (always)] pub fn is_ccctl_01_ccactupd_zero_evt (& self) -> bool { * self == CCCTL_01_CCACTUPD_A :: CCCTL_01_CCACTUPD_ZERO_EVT } # [doc = "COMPARE_DOWN_EVT"] # [inline (always)] pub fn is_ccctl_01_ccactupd_compare_down_evt (& self) -> bool { * self == CCCTL_01_CCACTUPD_A :: CCCTL_01_CCACTUPD_COMPARE_DOWN_EVT } # [doc = "COMPARE_UP_EVT"] # [inline (always)] pub fn is_ccctl_01_ccactupd_compare_up_evt (& self) -> bool { * self == CCCTL_01_CCACTUPD_A :: CCCTL_01_CCACTUPD_COMPARE_UP_EVT } # [doc = "ZERO_LOAD_EVT"] # [inline (always)] pub fn is_ccctl_01_ccactupd_zero_load_evt (& self) -> bool { * self == CCCTL_01_CCACTUPD_A :: CCCTL_01_CCACTUPD_ZERO_LOAD_EVT } # [doc = "ZERO_RC_ZERO_EVT"] # [inline (always)] pub fn is_ccctl_01_ccactupd_zero_rc_zero_evt (& self) -> bool { * self == CCCTL_01_CCACTUPD_A :: CCCTL_01_CCACTUPD_ZERO_RC_ZERO_EVT } # [doc = "TRIG"] # [inline (always)] pub fn is_ccctl_01_ccactupd_trig (& self) -> bool { * self == CCCTL_01_CCACTUPD_A :: CCCTL_01_CCACTUPD_TRIG } } # [doc = "Field `CCCTL_01_CCACTUPD` writer - CCACT shadow register Update Method This field controls how updates to the CCCACT shadow register are performed"] pub type CCCTL_01_CCACTUPD_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 3 , O , CCCTL_01_CCACTUPD_A > ; impl < 'a , REG , const O : u8 > CCCTL_01_CCACTUPD_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "IMMEDIATELY"] # [inline (always)] pub fn ccctl_01_ccactupd_immediately (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CCACTUPD_A :: CCCTL_01_CCACTUPD_IMMEDIATELY) } # [doc = "ZERO_EVT"] # [inline (always)] pub fn ccctl_01_ccactupd_zero_evt (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CCACTUPD_A :: CCCTL_01_CCACTUPD_ZERO_EVT) } # [doc = "COMPARE_DOWN_EVT"] # [inline (always)] pub fn ccctl_01_ccactupd_compare_down_evt (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CCACTUPD_A :: CCCTL_01_CCACTUPD_COMPARE_DOWN_EVT) } # [doc = "COMPARE_UP_EVT"] # [inline (always)] pub fn ccctl_01_ccactupd_compare_up_evt (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CCACTUPD_A :: CCCTL_01_CCACTUPD_COMPARE_UP_EVT) } # [doc = "ZERO_LOAD_EVT"] # [inline (always)] pub fn ccctl_01_ccactupd_zero_load_evt (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CCACTUPD_A :: CCCTL_01_CCACTUPD_ZERO_LOAD_EVT) } # [doc = "ZERO_RC_ZERO_EVT"] # [inline (always)] pub fn ccctl_01_ccactupd_zero_rc_zero_evt (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CCACTUPD_A :: CCCTL_01_CCACTUPD_ZERO_RC_ZERO_EVT) } # [doc = "TRIG"] # [inline (always)] pub fn ccctl_01_ccactupd_trig (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CCACTUPD_A :: CCCTL_01_CCACTUPD_TRIG) } } # [doc = "Field `CCCTL_01_CC2SELD` reader - Selects the source second CCD event."] pub type CCCTL_01_CC2SELD_R = crate :: FieldReader < CCCTL_01_CC2SELD_A > ; # [doc = "Selects the source second CCD event.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum CCCTL_01_CC2SELD_A { # [doc = "0: SEL_CCD0"] CCCTL_01_CC2SELD_SEL_CCD0 = 0 , # [doc = "1: SEL_CCD1"] CCCTL_01_CC2SELD_SEL_CCD1 = 1 , # [doc = "2: SEL_CCD2"] CCCTL_01_CC2SELD_SEL_CCD2 = 2 , # [doc = "3: SEL_CCD3"] CCCTL_01_CC2SELD_SEL_CCD3 = 3 , # [doc = "4: SEL_CCD4"] CCCTL_01_CC2SELD_SEL_CCD4 = 4 , # [doc = "5: SEL_CCD5"] CCCTL_01_CC2SELD_SEL_CCD5 = 5 , } impl From < CCCTL_01_CC2SELD_A > for u8 { # [inline (always)] fn from (variant : CCCTL_01_CC2SELD_A) -> Self { variant as _ } } impl crate :: FieldSpec for CCCTL_01_CC2SELD_A { type Ux = u8 ; } impl CCCTL_01_CC2SELD_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < CCCTL_01_CC2SELD_A > { match self . bits { 0 => Some (CCCTL_01_CC2SELD_A :: CCCTL_01_CC2SELD_SEL_CCD0) , 1 => Some (CCCTL_01_CC2SELD_A :: CCCTL_01_CC2SELD_SEL_CCD1) , 2 => Some (CCCTL_01_CC2SELD_A :: CCCTL_01_CC2SELD_SEL_CCD2) , 3 => Some (CCCTL_01_CC2SELD_A :: CCCTL_01_CC2SELD_SEL_CCD3) , 4 => Some (CCCTL_01_CC2SELD_A :: CCCTL_01_CC2SELD_SEL_CCD4) , 5 => Some (CCCTL_01_CC2SELD_A :: CCCTL_01_CC2SELD_SEL_CCD5) , _ => None , } } # [doc = "SEL_CCD0"] # [inline (always)] pub fn is_ccctl_01_cc2seld_sel_ccd0 (& self) -> bool { * self == CCCTL_01_CC2SELD_A :: CCCTL_01_CC2SELD_SEL_CCD0 } # [doc = "SEL_CCD1"] # [inline (always)] pub fn is_ccctl_01_cc2seld_sel_ccd1 (& self) -> bool { * self == CCCTL_01_CC2SELD_A :: CCCTL_01_CC2SELD_SEL_CCD1 } # [doc = "SEL_CCD2"] # [inline (always)] pub fn is_ccctl_01_cc2seld_sel_ccd2 (& self) -> bool { * self == CCCTL_01_CC2SELD_A :: CCCTL_01_CC2SELD_SEL_CCD2 } # [doc = "SEL_CCD3"] # [inline (always)] pub fn is_ccctl_01_cc2seld_sel_ccd3 (& self) -> bool { * self == CCCTL_01_CC2SELD_A :: CCCTL_01_CC2SELD_SEL_CCD3 } # [doc = "SEL_CCD4"] # [inline (always)] pub fn is_ccctl_01_cc2seld_sel_ccd4 (& self) -> bool { * self == CCCTL_01_CC2SELD_A :: CCCTL_01_CC2SELD_SEL_CCD4 } # [doc = "SEL_CCD5"] # [inline (always)] pub fn is_ccctl_01_cc2seld_sel_ccd5 (& self) -> bool { * self == CCCTL_01_CC2SELD_A :: CCCTL_01_CC2SELD_SEL_CCD5 } } # [doc = "Field `CCCTL_01_CC2SELD` writer - Selects the source second CCD event."] pub type CCCTL_01_CC2SELD_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 3 , O , CCCTL_01_CC2SELD_A > ; impl < 'a , REG , const O : u8 > CCCTL_01_CC2SELD_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "SEL_CCD0"] # [inline (always)] pub fn ccctl_01_cc2seld_sel_ccd0 (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CC2SELD_A :: CCCTL_01_CC2SELD_SEL_CCD0) } # [doc = "SEL_CCD1"] # [inline (always)] pub fn ccctl_01_cc2seld_sel_ccd1 (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CC2SELD_A :: CCCTL_01_CC2SELD_SEL_CCD1) } # [doc = "SEL_CCD2"] # [inline (always)] pub fn ccctl_01_cc2seld_sel_ccd2 (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CC2SELD_A :: CCCTL_01_CC2SELD_SEL_CCD2) } # [doc = "SEL_CCD3"] # [inline (always)] pub fn ccctl_01_cc2seld_sel_ccd3 (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CC2SELD_A :: CCCTL_01_CC2SELD_SEL_CCD3) } # [doc = "SEL_CCD4"] # [inline (always)] pub fn ccctl_01_cc2seld_sel_ccd4 (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CC2SELD_A :: CCCTL_01_CC2SELD_SEL_CCD4) } # [doc = "SEL_CCD5"] # [inline (always)] pub fn ccctl_01_cc2seld_sel_ccd5 (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CC2SELD_A :: CCCTL_01_CC2SELD_SEL_CCD5) } } impl R { # [doc = "Bits 0:2 - Capture Condition. #br# Specifies the condition that generates a capture pulse. 4h-Fh = Reserved"] # [inline (always)] pub fn ccctl_01_ccond (& self) -> CCCTL_01_CCOND_R { CCCTL_01_CCOND_R :: new ((self . bits & 7) as u8) } # [doc = "Bits 4:6 - Advance Condition. #br# Specifies the condition that generates an advance pulse. 6h-Fh = Reserved"] # [inline (always)] pub fn ccctl_01_acond (& self) -> CCCTL_01_ACOND_R { CCCTL_01_ACOND_R :: new (((self . bits >> 4) & 7) as u8) } # [doc = "Bits 8:10 - Load Condition. #br# Specifies the condition that generates a load pulse. 4h-Fh = Reserved"] # [inline (always)] pub fn ccctl_01_lcond (& self) -> CCCTL_01_LCOND_R { CCCTL_01_LCOND_R :: new (((self . bits >> 8) & 7) as u8) } # [doc = "Bits 12:14 - Zero Condition. #br# This field specifies the condition that generates a zero pulse. 4h-Fh = Reserved"] # [inline (always)] pub fn ccctl_01_zcond (& self) -> CCCTL_01_ZCOND_R { CCCTL_01_ZCOND_R :: new (((self . bits >> 12) & 7) as u8) } # [doc = "Bit 17 - Capture or Compare. #br# Specifies whether the corresponding CC register is used as a capture register or a compare register (never both)."] # [inline (always)] pub fn ccctl_01_coc (& self) -> CCCTL_01_COC_R { CCCTL_01_COC_R :: new (((self . bits >> 17) & 1) != 0) } # [doc = "Bits 18:20 - Capture and Compare Update Method This field controls how updates to the pipelined capture and compare register are performed (when operating in compare mode, COC=0)."] # [inline (always)] pub fn ccctl_01_ccupd (& self) -> CCCTL_01_CCUPD_R { CCCTL_01_CCUPD_R :: new (((self . bits >> 18) & 7) as u8) } # [doc = "Bits 22:24 - Selects the source second CCU event."] # [inline (always)] pub fn ccctl_01_cc2selu (& self) -> CCCTL_01_CC2SELU_R { CCCTL_01_CC2SELU_R :: new (((self . bits >> 22) & 7) as u8) } # [doc = "Bits 26:28 - CCACT shadow register Update Method This field controls how updates to the CCCACT shadow register are performed"] # [inline (always)] pub fn ccctl_01_ccactupd (& self) -> CCCTL_01_CCACTUPD_R { CCCTL_01_CCACTUPD_R :: new (((self . bits >> 26) & 7) as u8) } # [doc = "Bits 29:31 - Selects the source second CCD event."] # [inline (always)] pub fn ccctl_01_cc2seld (& self) -> CCCTL_01_CC2SELD_R { CCCTL_01_CC2SELD_R :: new (((self . bits >> 29) & 7) as u8) } } impl W { # [doc = "Bits 0:2 - Capture Condition. #br# Specifies the condition that generates a capture pulse. 4h-Fh = Reserved"] # [inline (always)] # [must_use] pub fn ccctl_01_ccond (& mut self) -> CCCTL_01_CCOND_W < CCCTL_01_SPEC , 0 > { CCCTL_01_CCOND_W :: new (self) } # [doc = "Bits 4:6 - Advance Condition. #br# Specifies the condition that generates an advance pulse. 6h-Fh = Reserved"] # [inline (always)] # [must_use] pub fn ccctl_01_acond (& mut self) -> CCCTL_01_ACOND_W <'_, CCCTL_01_SPEC , 4 > { CCCTL_01_ACOND_W :: new (self) } # [doc = "Bits 8:10 - Load Condition. #br# Specifies the condition that generates a load pulse. 4h-Fh = Reserved"] # [inline (always)] # [must_use] pub fn ccctl_01_lcond (& mut self) -> CCCTL_01_LCOND_W < CCCTL_01_SPEC , 8 > { CCCTL_01_LCOND_W :: new (self) } # [doc = "Bits 12:14 - Zero Condition. #br# This field specifies the condition that generates a zero pulse. 4h-Fh = Reserved"] # [inline (always)] # [must_use] pub fn ccctl_01_zcond (& mut self) -> CCCTL_01_ZCOND_W < CCCTL_01_SPEC , 12 > { CCCTL_01_ZCOND_W :: new (self) } # [doc = "Bit 17 - Capture or Compare. #br# Specifies whether the corresponding CC register is used as a capture register or a compare register (never both)."] # [inline (always)] # [must_use] pub fn ccctl_01_coc (& mut self) -> CCCTL_01_COC_W < CCCTL_01_SPEC , 17 > { CCCTL_01_COC_W :: new (self) } # [doc = "Bits 18:20 - Capture and Compare Update Method This field controls how updates to the pipelined capture and compare register are performed (when operating in compare mode, COC=0)."] # [inline (always)] # [must_use] pub fn ccctl_01_ccupd (& mut self) -> CCCTL_01_CCUPD_W < CCCTL_01_SPEC , 18 > { CCCTL_01_CCUPD_W :: new (self) } # [doc = "Bits 22:24 - Selects the source second CCU event."] # [inline (always)] # [must_use] pub fn ccctl_01_cc2selu (& mut self) -> CCCTL_01_CC2SELU_W < CCCTL_01_SPEC , 22 > { CCCTL_01_CC2SELU_W :: new (self) } # [doc = "Bits 26:28 - CCACT shadow register Update Method This field controls how updates to the CCCACT shadow register are performed"] # [inline (always)] # [must_use] pub fn ccctl_01_ccactupd (& mut self) -> CCCTL_01_CCACTUPD_W < CCCTL_01_SPEC , 26 > { CCCTL_01_CCACTUPD_W :: new (self) } # [doc = "Bits 29:31 - Selects the source second CCD event."] # [inline (always)] # [must_use] pub fn ccctl_01_cc2seld (& mut self) -> CCCTL_01_CC2SELD_W < CCCTL_01_SPEC , 29 > { CCCTL_01_CC2SELD_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Capture or Compare Control Registers\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ccctl_01::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ccctl_01::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CCCTL_01_SPEC ; impl crate :: RegisterSpec for CCCTL_01_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`ccctl_01::R`](R) reader structure"] impl crate :: Readable for CCCTL_01_SPEC { } # [doc = "`write(|w| ..)` method takes [`ccctl_01::W`](W) writer structure"] impl crate :: Writable for CCCTL_01_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets CCCTL_01[%s] [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/spi0/clkdiv.rs:1:4791 [INFO] [stdout] | [INFO] [stdout] 1 | ...use] pub fn clkdiv_ratio (& mut self) -> CLKDIV_RATIO_W < CLKDIV_SPEC , 0 > { CLKDIV_RATIO_W :: new (self) } # [doc = r" Writes raw bi... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `CLKDIV` reader"] pub type R = crate :: R < CLKDIV_SPEC > ; # [doc = "Register `CLKDIV` writer"] pub type W = crate :: W < CLKDIV_SPEC > ; # [doc = "Field `CLKDIV_RATIO` reader - Selects divide ratio of module clock"] pub type CLKDIV_RATIO_R = crate :: FieldReader < CLKDIV_RATIO_A > ; # [doc = "Selects divide ratio of module clock\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum CLKDIV_RATIO_A { # [doc = "0: DIV_BY_1"] CLKDIV_RATIO_DIV_BY_1 = 0 , # [doc = "1: DIV_BY_2"] CLKDIV_RATIO_DIV_BY_2 = 1 , # [doc = "2: DIV_BY_3"] CLKDIV_RATIO_DIV_BY_3 = 2 , # [doc = "3: DIV_BY_4"] CLKDIV_RATIO_DIV_BY_4 = 3 , # [doc = "4: DIV_BY_5"] CLKDIV_RATIO_DIV_BY_5 = 4 , # [doc = "5: DIV_BY_6"] CLKDIV_RATIO_DIV_BY_6 = 5 , # [doc = "6: DIV_BY_7"] CLKDIV_RATIO_DIV_BY_7 = 6 , # [doc = "7: DIV_BY_8"] CLKDIV_RATIO_DIV_BY_8 = 7 , } impl From < CLKDIV_RATIO_A > for u8 { # [inline (always)] fn from (variant : CLKDIV_RATIO_A) -> Self { variant as _ } } impl crate :: FieldSpec for CLKDIV_RATIO_A { type Ux = u8 ; } impl CLKDIV_RATIO_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CLKDIV_RATIO_A { match self . bits { 0 => CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_1 , 1 => CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_2 , 2 => CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_3 , 3 => CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_4 , 4 => CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_5 , 5 => CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_6 , 6 => CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_7 , 7 => CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_8 , _ => unreachable ! () , } } # [doc = "DIV_BY_1"] # [inline (always)] pub fn is_clkdiv_ratio_div_by_1 (& self) -> bool { * self == CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_1 } # [doc = "DIV_BY_2"] # [inline (always)] pub fn is_clkdiv_ratio_div_by_2 (& self) -> bool { * self == CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_2 } # [doc = "DIV_BY_3"] # [inline (always)] pub fn is_clkdiv_ratio_div_by_3 (& self) -> bool { * self == CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_3 } # [doc = "DIV_BY_4"] # [inline (always)] pub fn is_clkdiv_ratio_div_by_4 (& self) -> bool { * self == CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_4 } # [doc = "DIV_BY_5"] # [inline (always)] pub fn is_clkdiv_ratio_div_by_5 (& self) -> bool { * self == CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_5 } # [doc = "DIV_BY_6"] # [inline (always)] pub fn is_clkdiv_ratio_div_by_6 (& self) -> bool { * self == CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_6 } # [doc = "DIV_BY_7"] # [inline (always)] pub fn is_clkdiv_ratio_div_by_7 (& self) -> bool { * self == CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_7 } # [doc = "DIV_BY_8"] # [inline (always)] pub fn is_clkdiv_ratio_div_by_8 (& self) -> bool { * self == CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_8 } } # [doc = "Field `CLKDIV_RATIO` writer - Selects divide ratio of module clock"] pub type CLKDIV_RATIO_W < 'a , REG , const O : u8 > = crate :: FieldWriterSafe < 'a , REG , 3 , O , CLKDIV_RATIO_A > ; impl < 'a , REG , const O : u8 > CLKDIV_RATIO_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "DIV_BY_1"] # [inline (always)] pub fn clkdiv_ratio_div_by_1 (self) -> & 'a mut crate :: W < REG > { self . variant (CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_1) } # [doc = "DIV_BY_2"] # [inline (always)] pub fn clkdiv_ratio_div_by_2 (self) -> & 'a mut crate :: W < REG > { self . variant (CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_2) } # [doc = "DIV_BY_3"] # [inline (always)] pub fn clkdiv_ratio_div_by_3 (self) -> & 'a mut crate :: W < REG > { self . variant (CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_3) } # [doc = "DIV_BY_4"] # [inline (always)] pub fn clkdiv_ratio_div_by_4 (self) -> & 'a mut crate :: W < REG > { self . variant (CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_4) } # [doc = "DIV_BY_5"] # [inline (always)] pub fn clkdiv_ratio_div_by_5 (self) -> & 'a mut crate :: W < REG > { self . variant (CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_5) } # [doc = "DIV_BY_6"] # [inline (always)] pub fn clkdiv_ratio_div_by_6 (self) -> & 'a mut crate :: W < REG > { self . variant (CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_6) } # [doc = "DIV_BY_7"] # [inline (always)] pub fn clkdiv_ratio_div_by_7 (self) -> & 'a mut crate :: W < REG > { self . variant (CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_7) } # [doc = "DIV_BY_8"] # [inline (always)] pub fn clkdiv_ratio_div_by_8 (self) -> & 'a mut crate :: W < REG > { self . variant (CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_8) } } impl R { # [doc = "Bits 0:2 - Selects divide ratio of module clock"] # [inline (always)] pub fn clkdiv_ratio (& self) -> CLKDIV_RATIO_R { CLKDIV_RATIO_R :: new ((self . bits & 7) as u8) } } impl W { # [doc = "Bits 0:2 - Selects divide ratio of module clock"] # [inline (always)] # [must_use] pub fn clkdiv_ratio (& mut self) -> CLKDIV_RATIO_W <'_, CLKDIV_SPEC , 0 > { CLKDIV_RATIO_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Clock Divider\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clkdiv::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clkdiv::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CLKDIV_SPEC ; impl crate :: RegisterSpec for CLKDIV_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`clkdiv::R`](R) reader structure"] impl crate :: Readable for CLKDIV_SPEC { } # [doc = "`write(|w| ..)` method takes [`clkdiv::W`](W) writer structure"] impl crate :: Writable for CLKDIV_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets CLKDIV to value 0"] impl crate :: Resettable for CLKDIV_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/cpuss/int_group0_iclr.rs:1:1318 [INFO] [stdout] | [INFO] [stdout] 1 | ..._group0_iclr_int (& mut self) -> INT_GROUP0_ICLR_INT_W < INT_GROUP0_ICLR_SPEC , 0 > { INT_GROUP0_ICLR_INT_W :: new (self) } # [doc = r... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `INT_GROUP0_ICLR` writer"] pub type W = crate :: W < INT_GROUP0_ICLR_SPEC > ; # [doc = "Clears INT in RIS register\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_GROUP0_ICLR_INT_AW { # [doc = "0: NO_EFFECT"] INT_GROUP0_ICLR_INT_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_GROUP0_ICLR_INT_CLR = 1 , } impl From < INT_GROUP0_ICLR_INT_AW > for bool { # [inline (always)] fn from (variant : INT_GROUP0_ICLR_INT_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_GROUP0_ICLR_INT` writer - Clears INT in RIS register"] pub type INT_GROUP0_ICLR_INT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_GROUP0_ICLR_INT_AW > ; impl < 'a , REG , const O : u8 > INT_GROUP0_ICLR_INT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_group0_iclr_int_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_GROUP0_ICLR_INT_AW :: INT_GROUP0_ICLR_INT_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_group0_iclr_int_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_GROUP0_ICLR_INT_AW :: INT_GROUP0_ICLR_INT_CLR) } } impl W { # [doc = "Bit 0 - Clears INT in RIS register"] # [inline (always)] # [must_use] pub fn int_group0_iclr_int (& mut self) -> INT_GROUP0_ICLR_INT_W <'_, INT_GROUP0_ICLR_SPEC , 0 > { INT_GROUP0_ICLR_INT_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Interrupt clear\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_group0_iclr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct INT_GROUP0_ICLR_SPEC ; impl crate :: RegisterSpec for INT_GROUP0_ICLR_SPEC { type Ux = u32 ; } # [doc = "`write(|w| ..)` method takes [`int_group0_iclr::W`](W) writer structure"] impl crate :: Writable for INT_GROUP0_ICLR_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets INT_GROUP0_ICLR to value 0"] impl crate :: Resettable for INT_GROUP0_ICLR_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/sysctl/imask.rs:1:4764 [INFO] [stdout] | [INFO] [stdout] 1 | ... pub fn imask_anaclkerr (& mut self) -> IMASK_ANACLKERR_W < IMASK_SPEC , 1 > { IMASK_ANACLKERR_W :: new (self) } # [doc = r" Writes ra... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `IMASK` reader"] pub type R = crate :: R < IMASK_SPEC > ; # [doc = "Register `IMASK` writer"] pub type W = crate :: W < IMASK_SPEC > ; # [doc = "Field `IMASK_LFOSCGOOD` reader - Enable or disable the LFOSCGOOD interrupt. LFOSCGOOD indicates that the LFOSC has started successfully."] pub type IMASK_LFOSCGOOD_R = crate :: BitReader < IMASK_LFOSCGOOD_A > ; # [doc = "Enable or disable the LFOSCGOOD interrupt. LFOSCGOOD indicates that the LFOSC has started successfully.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum IMASK_LFOSCGOOD_A { # [doc = "0: DISABLE"] IMASK_LFOSCGOOD_DISABLE = 0 , # [doc = "1: ENABLE"] IMASK_LFOSCGOOD_ENABLE = 1 , } impl From < IMASK_LFOSCGOOD_A > for bool { # [inline (always)] fn from (variant : IMASK_LFOSCGOOD_A) -> Self { variant as u8 != 0 } } impl IMASK_LFOSCGOOD_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> IMASK_LFOSCGOOD_A { match self . bits { false => IMASK_LFOSCGOOD_A :: IMASK_LFOSCGOOD_DISABLE , true => IMASK_LFOSCGOOD_A :: IMASK_LFOSCGOOD_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_imask_lfoscgood_disable (& self) -> bool { * self == IMASK_LFOSCGOOD_A :: IMASK_LFOSCGOOD_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_imask_lfoscgood_enable (& self) -> bool { * self == IMASK_LFOSCGOOD_A :: IMASK_LFOSCGOOD_ENABLE } } # [doc = "Field `IMASK_LFOSCGOOD` writer - Enable or disable the LFOSCGOOD interrupt. LFOSCGOOD indicates that the LFOSC has started successfully."] pub type IMASK_LFOSCGOOD_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , IMASK_LFOSCGOOD_A > ; impl < 'a , REG , const O : u8 > IMASK_LFOSCGOOD_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn imask_lfoscgood_disable (self) -> & 'a mut crate :: W < REG > { self . variant (IMASK_LFOSCGOOD_A :: IMASK_LFOSCGOOD_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn imask_lfoscgood_enable (self) -> & 'a mut crate :: W < REG > { self . variant (IMASK_LFOSCGOOD_A :: IMASK_LFOSCGOOD_ENABLE) } } # [doc = "Field `IMASK_ANACLKERR` reader - Analog Clocking Consistency Error"] pub type IMASK_ANACLKERR_R = crate :: BitReader < IMASK_ANACLKERR_A > ; # [doc = "Analog Clocking Consistency Error\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum IMASK_ANACLKERR_A { # [doc = "0: DISABLE"] IMASK_ANACLKERR_DISABLE = 0 , # [doc = "1: ENABLE"] IMASK_ANACLKERR_ENABLE = 1 , } impl From < IMASK_ANACLKERR_A > for bool { # [inline (always)] fn from (variant : IMASK_ANACLKERR_A) -> Self { variant as u8 != 0 } } impl IMASK_ANACLKERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> IMASK_ANACLKERR_A { match self . bits { false => IMASK_ANACLKERR_A :: IMASK_ANACLKERR_DISABLE , true => IMASK_ANACLKERR_A :: IMASK_ANACLKERR_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_imask_anaclkerr_disable (& self) -> bool { * self == IMASK_ANACLKERR_A :: IMASK_ANACLKERR_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_imask_anaclkerr_enable (& self) -> bool { * self == IMASK_ANACLKERR_A :: IMASK_ANACLKERR_ENABLE } } # [doc = "Field `IMASK_ANACLKERR` writer - Analog Clocking Consistency Error"] pub type IMASK_ANACLKERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , IMASK_ANACLKERR_A > ; impl < 'a , REG , const O : u8 > IMASK_ANACLKERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn imask_anaclkerr_disable (self) -> & 'a mut crate :: W < REG > { self . variant (IMASK_ANACLKERR_A :: IMASK_ANACLKERR_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn imask_anaclkerr_enable (self) -> & 'a mut crate :: W < REG > { self . variant (IMASK_ANACLKERR_A :: IMASK_ANACLKERR_ENABLE) } } impl R { # [doc = "Bit 0 - Enable or disable the LFOSCGOOD interrupt. LFOSCGOOD indicates that the LFOSC has started successfully."] # [inline (always)] pub fn imask_lfoscgood (& self) -> IMASK_LFOSCGOOD_R { IMASK_LFOSCGOOD_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - Analog Clocking Consistency Error"] # [inline (always)] pub fn imask_anaclkerr (& self) -> IMASK_ANACLKERR_R { IMASK_ANACLKERR_R :: new (((self . bits >> 1) & 1) != 0) } } impl W { # [doc = "Bit 0 - Enable or disable the LFOSCGOOD interrupt. LFOSCGOOD indicates that the LFOSC has started successfully."] # [inline (always)] # [must_use] pub fn imask_lfoscgood (& mut self) -> IMASK_LFOSCGOOD_W < IMASK_SPEC , 0 > { IMASK_LFOSCGOOD_W :: new (self) } # [doc = "Bit 1 - Analog Clocking Consistency Error"] # [inline (always)] # [must_use] pub fn imask_anaclkerr (& mut self) -> IMASK_ANACLKERR_W <'_, IMASK_SPEC , 1 > { IMASK_ANACLKERR_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "SYSCTL interrupt mask\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`imask::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`imask::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct IMASK_SPEC ; impl crate :: RegisterSpec for IMASK_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`imask::R`](R) reader structure"] impl crate :: Readable for IMASK_SPEC { } # [doc = "`write(|w| ..)` method takes [`imask::W`](W) writer structure"] impl crate :: Writable for IMASK_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets IMASK to value 0"] impl crate :: Resettable for IMASK_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/i2c1/mfifoctl.rs:1:12656 [INFO] [stdout] | [INFO] [stdout] 1 | ...b fn mfifoctl_txflush (& mut self) -> MFIFOCTL_TXFLUSH_W < MFIFOCTL_SPEC , 7 > { MFIFOCTL_TXFLUSH_W :: new (self) } # [doc = "Bits 8:1... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `MFIFOCTL` reader"] pub type R = crate :: R < MFIFOCTL_SPEC > ; # [doc = "Register `MFIFOCTL` writer"] pub type W = crate :: W < MFIFOCTL_SPEC > ; # [doc = "Field `MFIFOCTL_TXTRIG` reader - TX FIFO Trigger Indicates at what fill level in the TX FIFO a trigger will be generated."] pub type MFIFOCTL_TXTRIG_R = crate :: FieldReader < MFIFOCTL_TXTRIG_A > ; # [doc = "TX FIFO Trigger Indicates at what fill level in the TX FIFO a trigger will be generated.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum MFIFOCTL_TXTRIG_A { # [doc = "4: LEVEL_4"] MFIFOCTL_TXTRIG_LEVEL_4 = 4 , # [doc = "5: LEVEL_5"] MFIFOCTL_TXTRIG_LEVEL_5 = 5 , # [doc = "6: LEVEL_6"] MFIFOCTL_TXTRIG_LEVEL_6 = 6 , # [doc = "7: LEVEL_7"] MFIFOCTL_TXTRIG_LEVEL_7 = 7 , } impl From < MFIFOCTL_TXTRIG_A > for u8 { # [inline (always)] fn from (variant : MFIFOCTL_TXTRIG_A) -> Self { variant as _ } } impl crate :: FieldSpec for MFIFOCTL_TXTRIG_A { type Ux = u8 ; } impl MFIFOCTL_TXTRIG_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < MFIFOCTL_TXTRIG_A > { match self . bits { 4 => Some (MFIFOCTL_TXTRIG_A :: MFIFOCTL_TXTRIG_LEVEL_4) , 5 => Some (MFIFOCTL_TXTRIG_A :: MFIFOCTL_TXTRIG_LEVEL_5) , 6 => Some (MFIFOCTL_TXTRIG_A :: MFIFOCTL_TXTRIG_LEVEL_6) , 7 => Some (MFIFOCTL_TXTRIG_A :: MFIFOCTL_TXTRIG_LEVEL_7) , _ => None , } } # [doc = "LEVEL_4"] # [inline (always)] pub fn is_mfifoctl_txtrig_level_4 (& self) -> bool { * self == MFIFOCTL_TXTRIG_A :: MFIFOCTL_TXTRIG_LEVEL_4 } # [doc = "LEVEL_5"] # [inline (always)] pub fn is_mfifoctl_txtrig_level_5 (& self) -> bool { * self == MFIFOCTL_TXTRIG_A :: MFIFOCTL_TXTRIG_LEVEL_5 } # [doc = "LEVEL_6"] # [inline (always)] pub fn is_mfifoctl_txtrig_level_6 (& self) -> bool { * self == MFIFOCTL_TXTRIG_A :: MFIFOCTL_TXTRIG_LEVEL_6 } # [doc = "LEVEL_7"] # [inline (always)] pub fn is_mfifoctl_txtrig_level_7 (& self) -> bool { * self == MFIFOCTL_TXTRIG_A :: MFIFOCTL_TXTRIG_LEVEL_7 } } # [doc = "Field `MFIFOCTL_TXTRIG` writer - TX FIFO Trigger Indicates at what fill level in the TX FIFO a trigger will be generated."] pub type MFIFOCTL_TXTRIG_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 3 , O , MFIFOCTL_TXTRIG_A > ; impl < 'a , REG , const O : u8 > MFIFOCTL_TXTRIG_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "LEVEL_4"] # [inline (always)] pub fn mfifoctl_txtrig_level_4 (self) -> & 'a mut crate :: W < REG > { self . variant (MFIFOCTL_TXTRIG_A :: MFIFOCTL_TXTRIG_LEVEL_4) } # [doc = "LEVEL_5"] # [inline (always)] pub fn mfifoctl_txtrig_level_5 (self) -> & 'a mut crate :: W < REG > { self . variant (MFIFOCTL_TXTRIG_A :: MFIFOCTL_TXTRIG_LEVEL_5) } # [doc = "LEVEL_6"] # [inline (always)] pub fn mfifoctl_txtrig_level_6 (self) -> & 'a mut crate :: W < REG > { self . variant (MFIFOCTL_TXTRIG_A :: MFIFOCTL_TXTRIG_LEVEL_6) } # [doc = "LEVEL_7"] # [inline (always)] pub fn mfifoctl_txtrig_level_7 (self) -> & 'a mut crate :: W < REG > { self . variant (MFIFOCTL_TXTRIG_A :: MFIFOCTL_TXTRIG_LEVEL_7) } } # [doc = "Field `MFIFOCTL_TXFLUSH` reader - TX FIFO Flush Setting this bit will Flush the TX FIFO. Before reseting this bit to stop Flush the TXFIFOCNT should be checked to be 8 and indicating that the Flush has completed."] pub type MFIFOCTL_TXFLUSH_R = crate :: BitReader < MFIFOCTL_TXFLUSH_A > ; # [doc = "TX FIFO Flush Setting this bit will Flush the TX FIFO. Before reseting this bit to stop Flush the TXFIFOCNT should be checked to be 8 and indicating that the Flush has completed.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum MFIFOCTL_TXFLUSH_A { # [doc = "0: NOFLUSH"] MFIFOCTL_TXFLUSH_NOFLUSH = 0 , # [doc = "1: FLUSH"] MFIFOCTL_TXFLUSH_FLUSH = 1 , } impl From < MFIFOCTL_TXFLUSH_A > for bool { # [inline (always)] fn from (variant : MFIFOCTL_TXFLUSH_A) -> Self { variant as u8 != 0 } } impl MFIFOCTL_TXFLUSH_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> MFIFOCTL_TXFLUSH_A { match self . bits { false => MFIFOCTL_TXFLUSH_A :: MFIFOCTL_TXFLUSH_NOFLUSH , true => MFIFOCTL_TXFLUSH_A :: MFIFOCTL_TXFLUSH_FLUSH , } } # [doc = "NOFLUSH"] # [inline (always)] pub fn is_mfifoctl_txflush_noflush (& self) -> bool { * self == MFIFOCTL_TXFLUSH_A :: MFIFOCTL_TXFLUSH_NOFLUSH } # [doc = "FLUSH"] # [inline (always)] pub fn is_mfifoctl_txflush_flush (& self) -> bool { * self == MFIFOCTL_TXFLUSH_A :: MFIFOCTL_TXFLUSH_FLUSH } } # [doc = "Field `MFIFOCTL_TXFLUSH` writer - TX FIFO Flush Setting this bit will Flush the TX FIFO. Before reseting this bit to stop Flush the TXFIFOCNT should be checked to be 8 and indicating that the Flush has completed."] pub type MFIFOCTL_TXFLUSH_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , MFIFOCTL_TXFLUSH_A > ; impl < 'a , REG , const O : u8 > MFIFOCTL_TXFLUSH_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NOFLUSH"] # [inline (always)] pub fn mfifoctl_txflush_noflush (self) -> & 'a mut crate :: W < REG > { self . variant (MFIFOCTL_TXFLUSH_A :: MFIFOCTL_TXFLUSH_NOFLUSH) } # [doc = "FLUSH"] # [inline (always)] pub fn mfifoctl_txflush_flush (self) -> & 'a mut crate :: W < REG > { self . variant (MFIFOCTL_TXFLUSH_A :: MFIFOCTL_TXFLUSH_FLUSH) } } # [doc = "Field `MFIFOCTL_RXTRIG` reader - RX FIFO Trigger Indicates at what fill level in the RX FIFO a trigger will be generated. Note: Programming RXTRIG to 0x0 has no effect since no data is present to transfer out of RX FIFO."] pub type MFIFOCTL_RXTRIG_R = crate :: FieldReader < MFIFOCTL_RXTRIG_A > ; # [doc = "RX FIFO Trigger Indicates at what fill level in the RX FIFO a trigger will be generated. Note: Programming RXTRIG to 0x0 has no effect since no data is present to transfer out of RX FIFO.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum MFIFOCTL_RXTRIG_A { # [doc = "4: LEVEL_5"] MFIFOCTL_RXTRIG_LEVEL_5 = 4 , # [doc = "5: LEVEL_6"] MFIFOCTL_RXTRIG_LEVEL_6 = 5 , # [doc = "6: LEVEL_7"] MFIFOCTL_RXTRIG_LEVEL_7 = 6 , # [doc = "7: LEVEL_8"] MFIFOCTL_RXTRIG_LEVEL_8 = 7 , } impl From < MFIFOCTL_RXTRIG_A > for u8 { # [inline (always)] fn from (variant : MFIFOCTL_RXTRIG_A) -> Self { variant as _ } } impl crate :: FieldSpec for MFIFOCTL_RXTRIG_A { type Ux = u8 ; } impl MFIFOCTL_RXTRIG_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < MFIFOCTL_RXTRIG_A > { match self . bits { 4 => Some (MFIFOCTL_RXTRIG_A :: MFIFOCTL_RXTRIG_LEVEL_5) , 5 => Some (MFIFOCTL_RXTRIG_A :: MFIFOCTL_RXTRIG_LEVEL_6) , 6 => Some (MFIFOCTL_RXTRIG_A :: MFIFOCTL_RXTRIG_LEVEL_7) , 7 => Some (MFIFOCTL_RXTRIG_A :: MFIFOCTL_RXTRIG_LEVEL_8) , _ => None , } } # [doc = "LEVEL_5"] # [inline (always)] pub fn is_mfifoctl_rxtrig_level_5 (& self) -> bool { * self == MFIFOCTL_RXTRIG_A :: MFIFOCTL_RXTRIG_LEVEL_5 } # [doc = "LEVEL_6"] # [inline (always)] pub fn is_mfifoctl_rxtrig_level_6 (& self) -> bool { * self == MFIFOCTL_RXTRIG_A :: MFIFOCTL_RXTRIG_LEVEL_6 } # [doc = "LEVEL_7"] # [inline (always)] pub fn is_mfifoctl_rxtrig_level_7 (& self) -> bool { * self == MFIFOCTL_RXTRIG_A :: MFIFOCTL_RXTRIG_LEVEL_7 } # [doc = "LEVEL_8"] # [inline (always)] pub fn is_mfifoctl_rxtrig_level_8 (& self) -> bool { * self == MFIFOCTL_RXTRIG_A :: MFIFOCTL_RXTRIG_LEVEL_8 } } # [doc = "Field `MFIFOCTL_RXTRIG` writer - RX FIFO Trigger Indicates at what fill level in the RX FIFO a trigger will be generated. Note: Programming RXTRIG to 0x0 has no effect since no data is present to transfer out of RX FIFO."] pub type MFIFOCTL_RXTRIG_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 3 , O , MFIFOCTL_RXTRIG_A > ; impl < 'a , REG , const O : u8 > MFIFOCTL_RXTRIG_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "LEVEL_5"] # [inline (always)] pub fn mfifoctl_rxtrig_level_5 (self) -> & 'a mut crate :: W < REG > { self . variant (MFIFOCTL_RXTRIG_A :: MFIFOCTL_RXTRIG_LEVEL_5) } # [doc = "LEVEL_6"] # [inline (always)] pub fn mfifoctl_rxtrig_level_6 (self) -> & 'a mut crate :: W < REG > { self . variant (MFIFOCTL_RXTRIG_A :: MFIFOCTL_RXTRIG_LEVEL_6) } # [doc = "LEVEL_7"] # [inline (always)] pub fn mfifoctl_rxtrig_level_7 (self) -> & 'a mut crate :: W < REG > { self . variant (MFIFOCTL_RXTRIG_A :: MFIFOCTL_RXTRIG_LEVEL_7) } # [doc = "LEVEL_8"] # [inline (always)] pub fn mfifoctl_rxtrig_level_8 (self) -> & 'a mut crate :: W < REG > { self . variant (MFIFOCTL_RXTRIG_A :: MFIFOCTL_RXTRIG_LEVEL_8) } } # [doc = "Field `MFIFOCTL_RXFLUSH` reader - RX FIFO Flush Setting this bit will Flush the RX FIFO. Before reseting this bit to stop Flush the RXFIFOCNT should be checked to be 0 and indicating that the Flush has completed."] pub type MFIFOCTL_RXFLUSH_R = crate :: BitReader < MFIFOCTL_RXFLUSH_A > ; # [doc = "RX FIFO Flush Setting this bit will Flush the RX FIFO. Before reseting this bit to stop Flush the RXFIFOCNT should be checked to be 0 and indicating that the Flush has completed.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum MFIFOCTL_RXFLUSH_A { # [doc = "0: NOFLUSH"] MFIFOCTL_RXFLUSH_NOFLUSH = 0 , # [doc = "1: FLUSH"] MFIFOCTL_RXFLUSH_FLUSH = 1 , } impl From < MFIFOCTL_RXFLUSH_A > for bool { # [inline (always)] fn from (variant : MFIFOCTL_RXFLUSH_A) -> Self { variant as u8 != 0 } } impl MFIFOCTL_RXFLUSH_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> MFIFOCTL_RXFLUSH_A { match self . bits { false => MFIFOCTL_RXFLUSH_A :: MFIFOCTL_RXFLUSH_NOFLUSH , true => MFIFOCTL_RXFLUSH_A :: MFIFOCTL_RXFLUSH_FLUSH , } } # [doc = "NOFLUSH"] # [inline (always)] pub fn is_mfifoctl_rxflush_noflush (& self) -> bool { * self == MFIFOCTL_RXFLUSH_A :: MFIFOCTL_RXFLUSH_NOFLUSH } # [doc = "FLUSH"] # [inline (always)] pub fn is_mfifoctl_rxflush_flush (& self) -> bool { * self == MFIFOCTL_RXFLUSH_A :: MFIFOCTL_RXFLUSH_FLUSH } } # [doc = "Field `MFIFOCTL_RXFLUSH` writer - RX FIFO Flush Setting this bit will Flush the RX FIFO. Before reseting this bit to stop Flush the RXFIFOCNT should be checked to be 0 and indicating that the Flush has completed."] pub type MFIFOCTL_RXFLUSH_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , MFIFOCTL_RXFLUSH_A > ; impl < 'a , REG , const O : u8 > MFIFOCTL_RXFLUSH_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NOFLUSH"] # [inline (always)] pub fn mfifoctl_rxflush_noflush (self) -> & 'a mut crate :: W < REG > { self . variant (MFIFOCTL_RXFLUSH_A :: MFIFOCTL_RXFLUSH_NOFLUSH) } # [doc = "FLUSH"] # [inline (always)] pub fn mfifoctl_rxflush_flush (self) -> & 'a mut crate :: W < REG > { self . variant (MFIFOCTL_RXFLUSH_A :: MFIFOCTL_RXFLUSH_FLUSH) } } impl R { # [doc = "Bits 0:2 - TX FIFO Trigger Indicates at what fill level in the TX FIFO a trigger will be generated."] # [inline (always)] pub fn mfifoctl_txtrig (& self) -> MFIFOCTL_TXTRIG_R { MFIFOCTL_TXTRIG_R :: new ((self . bits & 7) as u8) } # [doc = "Bit 7 - TX FIFO Flush Setting this bit will Flush the TX FIFO. Before reseting this bit to stop Flush the TXFIFOCNT should be checked to be 8 and indicating that the Flush has completed."] # [inline (always)] pub fn mfifoctl_txflush (& self) -> MFIFOCTL_TXFLUSH_R { MFIFOCTL_TXFLUSH_R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bits 8:10 - RX FIFO Trigger Indicates at what fill level in the RX FIFO a trigger will be generated. Note: Programming RXTRIG to 0x0 has no effect since no data is present to transfer out of RX FIFO."] # [inline (always)] pub fn mfifoctl_rxtrig (& self) -> MFIFOCTL_RXTRIG_R { MFIFOCTL_RXTRIG_R :: new (((self . bits >> 8) & 7) as u8) } # [doc = "Bit 15 - RX FIFO Flush Setting this bit will Flush the RX FIFO. Before reseting this bit to stop Flush the RXFIFOCNT should be checked to be 0 and indicating that the Flush has completed."] # [inline (always)] pub fn mfifoctl_rxflush (& self) -> MFIFOCTL_RXFLUSH_R { MFIFOCTL_RXFLUSH_R :: new (((self . bits >> 15) & 1) != 0) } } impl W { # [doc = "Bits 0:2 - TX FIFO Trigger Indicates at what fill level in the TX FIFO a trigger will be generated."] # [inline (always)] # [must_use] pub fn mfifoctl_txtrig (& mut self) -> MFIFOCTL_TXTRIG_W < MFIFOCTL_SPEC , 0 > { MFIFOCTL_TXTRIG_W :: new (self) } # [doc = "Bit 7 - TX FIFO Flush Setting this bit will Flush the TX FIFO. Before reseting this bit to stop Flush the TXFIFOCNT should be checked to be 8 and indicating that the Flush has completed."] # [inline (always)] # [must_use] pub fn mfifoctl_txflush (& mut self) -> MFIFOCTL_TXFLUSH_W <'_, MFIFOCTL_SPEC , 7 > { MFIFOCTL_TXFLUSH_W :: new (self) } # [doc = "Bits 8:10 - RX FIFO Trigger Indicates at what fill level in the RX FIFO a trigger will be generated. Note: Programming RXTRIG to 0x0 has no effect since no data is present to transfer out of RX FIFO."] # [inline (always)] # [must_use] pub fn mfifoctl_rxtrig (& mut self) -> MFIFOCTL_RXTRIG_W < MFIFOCTL_SPEC , 8 > { MFIFOCTL_RXTRIG_W :: new (self) } # [doc = "Bit 15 - RX FIFO Flush Setting this bit will Flush the RX FIFO. Before reseting this bit to stop Flush the RXFIFOCNT should be checked to be 0 and indicating that the Flush has completed."] # [inline (always)] # [must_use] pub fn mfifoctl_rxflush (& mut self) -> MFIFOCTL_RXFLUSH_W < MFIFOCTL_SPEC , 15 > { MFIFOCTL_RXFLUSH_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "I2C Master FIFO Control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mfifoctl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mfifoctl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct MFIFOCTL_SPEC ; impl crate :: RegisterSpec for MFIFOCTL_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`mfifoctl::R`](R) reader structure"] impl crate :: Readable for MFIFOCTL_SPEC { } # [doc = "`write(|w| ..)` method takes [`mfifoctl::W`](W) writer structure"] impl crate :: Writable for MFIFOCTL_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets MFIFOCTL to value 0"] impl crate :: Resettable for MFIFOCTL_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/opa0/pwren.rs:1:2941 [INFO] [stdout] | [INFO] [stdout] 1 | ...use] pub fn pwren_enable (& mut self) -> PWREN_ENABLE_W < PWREN_SPEC , 0 > { PWREN_ENABLE_W :: new (self) } # [doc = "Bits 24:31 - KEY... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `PWREN` reader"] pub type R = crate :: R < PWREN_SPEC > ; # [doc = "Register `PWREN` writer"] pub type W = crate :: W < PWREN_SPEC > ; # [doc = "Field `PWREN_ENABLE` reader - Enable the power"] pub type PWREN_ENABLE_R = crate :: BitReader < PWREN_ENABLE_A > ; # [doc = "Enable the power\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum PWREN_ENABLE_A { # [doc = "0: DISABLE"] PWREN_ENABLE_DISABLE = 0 , # [doc = "1: ENABLE"] PWREN_ENABLE_ENABLE = 1 , } impl From < PWREN_ENABLE_A > for bool { # [inline (always)] fn from (variant : PWREN_ENABLE_A) -> Self { variant as u8 != 0 } } impl PWREN_ENABLE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> PWREN_ENABLE_A { match self . bits { false => PWREN_ENABLE_A :: PWREN_ENABLE_DISABLE , true => PWREN_ENABLE_A :: PWREN_ENABLE_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_pwren_enable_disable (& self) -> bool { * self == PWREN_ENABLE_A :: PWREN_ENABLE_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_pwren_enable_enable (& self) -> bool { * self == PWREN_ENABLE_A :: PWREN_ENABLE_ENABLE } } # [doc = "Field `PWREN_ENABLE` writer - Enable the power"] pub type PWREN_ENABLE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , PWREN_ENABLE_A > ; impl < 'a , REG , const O : u8 > PWREN_ENABLE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn pwren_enable_disable (self) -> & 'a mut crate :: W < REG > { self . variant (PWREN_ENABLE_A :: PWREN_ENABLE_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn pwren_enable_enable (self) -> & 'a mut crate :: W < REG > { self . variant (PWREN_ENABLE_A :: PWREN_ENABLE_ENABLE) } } # [doc = "KEY to allow Power State Change\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum PWREN_KEY_AW { # [doc = "38: _TO_UNLOCK_W_"] PWREN_KEY_UNLOCK_W = 38 , } impl From < PWREN_KEY_AW > for u8 { # [inline (always)] fn from (variant : PWREN_KEY_AW) -> Self { variant as _ } } impl crate :: FieldSpec for PWREN_KEY_AW { type Ux = u8 ; } # [doc = "Field `PWREN_KEY` writer - KEY to allow Power State Change"] pub type PWREN_KEY_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 8 , O , PWREN_KEY_AW > ; impl < 'a , REG , const O : u8 > PWREN_KEY_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "_TO_UNLOCK_W_"] # [inline (always)] pub fn pwren_key_unlock_w (self) -> & 'a mut crate :: W < REG > { self . variant (PWREN_KEY_AW :: PWREN_KEY_UNLOCK_W) } } impl R { # [doc = "Bit 0 - Enable the power"] # [inline (always)] pub fn pwren_enable (& self) -> PWREN_ENABLE_R { PWREN_ENABLE_R :: new ((self . bits & 1) != 0) } } impl W { # [doc = "Bit 0 - Enable the power"] # [inline (always)] # [must_use] pub fn pwren_enable (& mut self) -> PWREN_ENABLE_W <'_, PWREN_SPEC , 0 > { PWREN_ENABLE_W :: new (self) } # [doc = "Bits 24:31 - KEY to allow Power State Change"] # [inline (always)] # [must_use] pub fn pwren_key (& mut self) -> PWREN_KEY_W < PWREN_SPEC , 24 > { PWREN_KEY_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Power enable\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pwren::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pwren::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PWREN_SPEC ; impl crate :: RegisterSpec for PWREN_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`pwren::R`](R) reader structure"] impl crate :: Readable for PWREN_SPEC { } # [doc = "`write(|w| ..)` method takes [`pwren::W`](W) writer structure"] impl crate :: Writable for PWREN_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets PWREN to value 0"] impl crate :: Resettable for PWREN_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/i2c1/mctr.rs:1:12287 [INFO] [stdout] | [INFO] [stdout] 1 | ...se] pub fn mctr_burstrun (& mut self) -> MCTR_BURSTRUN_W < MCTR_SPEC , 0 > { MCTR_BURSTRUN_W :: new (self) } # [doc = "Bit 1 - Generat... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `MCTR` reader"] pub type R = crate :: R < MCTR_SPEC > ; # [doc = "Register `MCTR` writer"] pub type W = crate :: W < MCTR_SPEC > ; # [doc = "Field `MCTR_BURSTRUN` reader - I2C Master Enable and start transaction"] pub type MCTR_BURSTRUN_R = crate :: BitReader < MCTR_BURSTRUN_A > ; # [doc = "I2C Master Enable and start transaction\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum MCTR_BURSTRUN_A { # [doc = "0: DISABLE"] MCTR_BURSTRUN_DISABLE = 0 , # [doc = "1: ENABLE"] MCTR_BURSTRUN_ENABLE = 1 , } impl From < MCTR_BURSTRUN_A > for bool { # [inline (always)] fn from (variant : MCTR_BURSTRUN_A) -> Self { variant as u8 != 0 } } impl MCTR_BURSTRUN_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> MCTR_BURSTRUN_A { match self . bits { false => MCTR_BURSTRUN_A :: MCTR_BURSTRUN_DISABLE , true => MCTR_BURSTRUN_A :: MCTR_BURSTRUN_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_mctr_burstrun_disable (& self) -> bool { * self == MCTR_BURSTRUN_A :: MCTR_BURSTRUN_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_mctr_burstrun_enable (& self) -> bool { * self == MCTR_BURSTRUN_A :: MCTR_BURSTRUN_ENABLE } } # [doc = "Field `MCTR_BURSTRUN` writer - I2C Master Enable and start transaction"] pub type MCTR_BURSTRUN_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , MCTR_BURSTRUN_A > ; impl < 'a , REG , const O : u8 > MCTR_BURSTRUN_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn mctr_burstrun_disable (self) -> & 'a mut crate :: W < REG > { self . variant (MCTR_BURSTRUN_A :: MCTR_BURSTRUN_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn mctr_burstrun_enable (self) -> & 'a mut crate :: W < REG > { self . variant (MCTR_BURSTRUN_A :: MCTR_BURSTRUN_ENABLE) } } # [doc = "Field `MCTR_START` reader - Generate START"] pub type MCTR_START_R = crate :: BitReader < MCTR_START_A > ; # [doc = "Generate START\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum MCTR_START_A { # [doc = "0: DISABLE"] MCTR_START_DISABLE = 0 , # [doc = "1: ENABLE"] MCTR_START_ENABLE = 1 , } impl From < MCTR_START_A > for bool { # [inline (always)] fn from (variant : MCTR_START_A) -> Self { variant as u8 != 0 } } impl MCTR_START_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> MCTR_START_A { match self . bits { false => MCTR_START_A :: MCTR_START_DISABLE , true => MCTR_START_A :: MCTR_START_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_mctr_start_disable (& self) -> bool { * self == MCTR_START_A :: MCTR_START_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_mctr_start_enable (& self) -> bool { * self == MCTR_START_A :: MCTR_START_ENABLE } } # [doc = "Field `MCTR_START` writer - Generate START"] pub type MCTR_START_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , MCTR_START_A > ; impl < 'a , REG , const O : u8 > MCTR_START_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn mctr_start_disable (self) -> & 'a mut crate :: W < REG > { self . variant (MCTR_START_A :: MCTR_START_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn mctr_start_enable (self) -> & 'a mut crate :: W < REG > { self . variant (MCTR_START_A :: MCTR_START_ENABLE) } } # [doc = "Field `MCTR_STOP` reader - Generate STOP"] pub type MCTR_STOP_R = crate :: BitReader < MCTR_STOP_A > ; # [doc = "Generate STOP\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum MCTR_STOP_A { # [doc = "0: DISABLE"] MCTR_STOP_DISABLE = 0 , # [doc = "1: ENABLE"] MCTR_STOP_ENABLE = 1 , } impl From < MCTR_STOP_A > for bool { # [inline (always)] fn from (variant : MCTR_STOP_A) -> Self { variant as u8 != 0 } } impl MCTR_STOP_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> MCTR_STOP_A { match self . bits { false => MCTR_STOP_A :: MCTR_STOP_DISABLE , true => MCTR_STOP_A :: MCTR_STOP_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_mctr_stop_disable (& self) -> bool { * self == MCTR_STOP_A :: MCTR_STOP_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_mctr_stop_enable (& self) -> bool { * self == MCTR_STOP_A :: MCTR_STOP_ENABLE } } # [doc = "Field `MCTR_STOP` writer - Generate STOP"] pub type MCTR_STOP_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , MCTR_STOP_A > ; impl < 'a , REG , const O : u8 > MCTR_STOP_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn mctr_stop_disable (self) -> & 'a mut crate :: W < REG > { self . variant (MCTR_STOP_A :: MCTR_STOP_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn mctr_stop_enable (self) -> & 'a mut crate :: W < REG > { self . variant (MCTR_STOP_A :: MCTR_STOP_ENABLE) } } # [doc = "Field `MCTR_ACK` reader - Data Acknowledge Enable. Software needs to configure this bit to send the ACK or NACK. See field decoding in Table: MCTR Field decoding."] pub type MCTR_ACK_R = crate :: BitReader < MCTR_ACK_A > ; # [doc = "Data Acknowledge Enable. Software needs to configure this bit to send the ACK or NACK. See field decoding in Table: MCTR Field decoding.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum MCTR_ACK_A { # [doc = "0: DISABLE"] MCTR_ACK_DISABLE = 0 , # [doc = "1: ENABLE"] MCTR_ACK_ENABLE = 1 , } impl From < MCTR_ACK_A > for bool { # [inline (always)] fn from (variant : MCTR_ACK_A) -> Self { variant as u8 != 0 } } impl MCTR_ACK_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> MCTR_ACK_A { match self . bits { false => MCTR_ACK_A :: MCTR_ACK_DISABLE , true => MCTR_ACK_A :: MCTR_ACK_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_mctr_ack_disable (& self) -> bool { * self == MCTR_ACK_A :: MCTR_ACK_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_mctr_ack_enable (& self) -> bool { * self == MCTR_ACK_A :: MCTR_ACK_ENABLE } } # [doc = "Field `MCTR_ACK` writer - Data Acknowledge Enable. Software needs to configure this bit to send the ACK or NACK. See field decoding in Table: MCTR Field decoding."] pub type MCTR_ACK_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , MCTR_ACK_A > ; impl < 'a , REG , const O : u8 > MCTR_ACK_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn mctr_ack_disable (self) -> & 'a mut crate :: W < REG > { self . variant (MCTR_ACK_A :: MCTR_ACK_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn mctr_ack_enable (self) -> & 'a mut crate :: W < REG > { self . variant (MCTR_ACK_A :: MCTR_ACK_ENABLE) } } # [doc = "Field `MCTR_MACKOEN` reader - Master ACK overrride Enable"] pub type MCTR_MACKOEN_R = crate :: BitReader < MCTR_MACKOEN_A > ; # [doc = "Master ACK overrride Enable\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum MCTR_MACKOEN_A { # [doc = "0: DISABLE"] MCTR_MACKOEN_DISABLE = 0 , # [doc = "1: ENABLE"] MCTR_MACKOEN_ENABLE = 1 , } impl From < MCTR_MACKOEN_A > for bool { # [inline (always)] fn from (variant : MCTR_MACKOEN_A) -> Self { variant as u8 != 0 } } impl MCTR_MACKOEN_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> MCTR_MACKOEN_A { match self . bits { false => MCTR_MACKOEN_A :: MCTR_MACKOEN_DISABLE , true => MCTR_MACKOEN_A :: MCTR_MACKOEN_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_mctr_mackoen_disable (& self) -> bool { * self == MCTR_MACKOEN_A :: MCTR_MACKOEN_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_mctr_mackoen_enable (& self) -> bool { * self == MCTR_MACKOEN_A :: MCTR_MACKOEN_ENABLE } } # [doc = "Field `MCTR_MACKOEN` writer - Master ACK overrride Enable"] pub type MCTR_MACKOEN_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , MCTR_MACKOEN_A > ; impl < 'a , REG , const O : u8 > MCTR_MACKOEN_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn mctr_mackoen_disable (self) -> & 'a mut crate :: W < REG > { self . variant (MCTR_MACKOEN_A :: MCTR_MACKOEN_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn mctr_mackoen_enable (self) -> & 'a mut crate :: W < REG > { self . variant (MCTR_MACKOEN_A :: MCTR_MACKOEN_ENABLE) } } # [doc = "Field `MCTR_RD_ON_TXEMPTY` reader - Read on TX Empty"] pub type MCTR_RD_ON_TXEMPTY_R = crate :: BitReader < MCTR_RD_ON_TXEMPTY_A > ; # [doc = "Read on TX Empty\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum MCTR_RD_ON_TXEMPTY_A { # [doc = "0: DISABLE"] MCTR_RD_ON_TXEMPTY_DISABLE = 0 , # [doc = "1: ENABLE"] MCTR_RD_ON_TXEMPTY_ENABLE = 1 , } impl From < MCTR_RD_ON_TXEMPTY_A > for bool { # [inline (always)] fn from (variant : MCTR_RD_ON_TXEMPTY_A) -> Self { variant as u8 != 0 } } impl MCTR_RD_ON_TXEMPTY_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> MCTR_RD_ON_TXEMPTY_A { match self . bits { false => MCTR_RD_ON_TXEMPTY_A :: MCTR_RD_ON_TXEMPTY_DISABLE , true => MCTR_RD_ON_TXEMPTY_A :: MCTR_RD_ON_TXEMPTY_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_mctr_rd_on_txempty_disable (& self) -> bool { * self == MCTR_RD_ON_TXEMPTY_A :: MCTR_RD_ON_TXEMPTY_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_mctr_rd_on_txempty_enable (& self) -> bool { * self == MCTR_RD_ON_TXEMPTY_A :: MCTR_RD_ON_TXEMPTY_ENABLE } } # [doc = "Field `MCTR_RD_ON_TXEMPTY` writer - Read on TX Empty"] pub type MCTR_RD_ON_TXEMPTY_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , MCTR_RD_ON_TXEMPTY_A > ; impl < 'a , REG , const O : u8 > MCTR_RD_ON_TXEMPTY_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn mctr_rd_on_txempty_disable (self) -> & 'a mut crate :: W < REG > { self . variant (MCTR_RD_ON_TXEMPTY_A :: MCTR_RD_ON_TXEMPTY_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn mctr_rd_on_txempty_enable (self) -> & 'a mut crate :: W < REG > { self . variant (MCTR_RD_ON_TXEMPTY_A :: MCTR_RD_ON_TXEMPTY_ENABLE) } } # [doc = "Field `MCTR_MBLEN` reader - I2C transaction length This field contains the programmed length of bytes of the Transaction."] pub type MCTR_MBLEN_R = crate :: FieldReader < u16 > ; # [doc = "Field `MCTR_MBLEN` writer - I2C transaction length This field contains the programmed length of bytes of the Transaction."] pub type MCTR_MBLEN_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 12 , O , u16 > ; impl R { # [doc = "Bit 0 - I2C Master Enable and start transaction"] # [inline (always)] pub fn mctr_burstrun (& self) -> MCTR_BURSTRUN_R { MCTR_BURSTRUN_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - Generate START"] # [inline (always)] pub fn mctr_start (& self) -> MCTR_START_R { MCTR_START_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - Generate STOP"] # [inline (always)] pub fn mctr_stop (& self) -> MCTR_STOP_R { MCTR_STOP_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - Data Acknowledge Enable. Software needs to configure this bit to send the ACK or NACK. See field decoding in Table: MCTR Field decoding."] # [inline (always)] pub fn mctr_ack (& self) -> MCTR_ACK_R { MCTR_ACK_R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - Master ACK overrride Enable"] # [inline (always)] pub fn mctr_mackoen (& self) -> MCTR_MACKOEN_R { MCTR_MACKOEN_R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - Read on TX Empty"] # [inline (always)] pub fn mctr_rd_on_txempty (& self) -> MCTR_RD_ON_TXEMPTY_R { MCTR_RD_ON_TXEMPTY_R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bits 16:27 - I2C transaction length This field contains the programmed length of bytes of the Transaction."] # [inline (always)] pub fn mctr_mblen (& self) -> MCTR_MBLEN_R { MCTR_MBLEN_R :: new (((self . bits >> 16) & 0x0fff) as u16) } } impl W { # [doc = "Bit 0 - I2C Master Enable and start transaction"] # [inline (always)] # [must_use] pub fn mctr_burstrun (& mut self) -> MCTR_BURSTRUN_W <'_, MCTR_SPEC , 0 > { MCTR_BURSTRUN_W :: new (self) } # [doc = "Bit 1 - Generate START"] # [inline (always)] # [must_use] pub fn mctr_start (& mut self) -> MCTR_START_W < MCTR_SPEC , 1 > { MCTR_START_W :: new (self) } # [doc = "Bit 2 - Generate STOP"] # [inline (always)] # [must_use] pub fn mctr_stop (& mut self) -> MCTR_STOP_W < MCTR_SPEC , 2 > { MCTR_STOP_W :: new (self) } # [doc = "Bit 3 - Data Acknowledge Enable. Software needs to configure this bit to send the ACK or NACK. See field decoding in Table: MCTR Field decoding."] # [inline (always)] # [must_use] pub fn mctr_ack (& mut self) -> MCTR_ACK_W < MCTR_SPEC , 3 > { MCTR_ACK_W :: new (self) } # [doc = "Bit 4 - Master ACK overrride Enable"] # [inline (always)] # [must_use] pub fn mctr_mackoen (& mut self) -> MCTR_MACKOEN_W < MCTR_SPEC , 4 > { MCTR_MACKOEN_W :: new (self) } # [doc = "Bit 5 - Read on TX Empty"] # [inline (always)] # [must_use] pub fn mctr_rd_on_txempty (& mut self) -> MCTR_RD_ON_TXEMPTY_W < MCTR_SPEC , 5 > { MCTR_RD_ON_TXEMPTY_W :: new (self) } # [doc = "Bits 16:27 - I2C transaction length This field contains the programmed length of bytes of the Transaction."] # [inline (always)] # [must_use] pub fn mctr_mblen (& mut self) -> MCTR_MBLEN_W < MCTR_SPEC , 16 > { MCTR_MBLEN_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "I2C Master Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mctr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mctr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct MCTR_SPEC ; impl crate :: RegisterSpec for MCTR_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`mctr::R`](R) reader structure"] impl crate :: Readable for MCTR_SPEC { } # [doc = "`write(|w| ..)` method takes [`mctr::W`](W) writer structure"] impl crate :: Writable for MCTR_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets MCTR to value 0"] impl crate :: Resettable for MCTR_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/i2c0/soar2.rs:1:4071 [INFO] [stdout] | [INFO] [stdout] 1 | ...st_use] pub fn soar2_oar2 (& mut self) -> SOAR2_OAR2_W < SOAR2_SPEC , 0 > { SOAR2_OAR2_W :: new (self) } # [doc = "Bit 7 - I2C Slave O... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `SOAR2` reader"] pub type R = crate :: R < SOAR2_SPEC > ; # [doc = "Register `SOAR2` writer"] pub type W = crate :: W < SOAR2_SPEC > ; # [doc = "Field `SOAR2_OAR2` reader - I2C Slave Own Address 2 This field specifies the alternate OAR2 address."] pub type SOAR2_OAR2_R = crate :: FieldReader ; # [doc = "Field `SOAR2_OAR2` writer - I2C Slave Own Address 2 This field specifies the alternate OAR2 address."] pub type SOAR2_OAR2_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 7 , O > ; # [doc = "Field `SOAR2_OAR2EN` reader - I2C Slave Own Address 2 Enable"] pub type SOAR2_OAR2EN_R = crate :: BitReader < SOAR2_OAR2EN_A > ; # [doc = "I2C Slave Own Address 2 Enable\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum SOAR2_OAR2EN_A { # [doc = "0: DISABLE"] SOAR2_OAR2EN_DISABLE = 0 , # [doc = "1: ENABLE"] SOAR2_OAR2EN_ENABLE = 1 , } impl From < SOAR2_OAR2EN_A > for bool { # [inline (always)] fn from (variant : SOAR2_OAR2EN_A) -> Self { variant as u8 != 0 } } impl SOAR2_OAR2EN_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> SOAR2_OAR2EN_A { match self . bits { false => SOAR2_OAR2EN_A :: SOAR2_OAR2EN_DISABLE , true => SOAR2_OAR2EN_A :: SOAR2_OAR2EN_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_soar2_oar2en_disable (& self) -> bool { * self == SOAR2_OAR2EN_A :: SOAR2_OAR2EN_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_soar2_oar2en_enable (& self) -> bool { * self == SOAR2_OAR2EN_A :: SOAR2_OAR2EN_ENABLE } } # [doc = "Field `SOAR2_OAR2EN` writer - I2C Slave Own Address 2 Enable"] pub type SOAR2_OAR2EN_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , SOAR2_OAR2EN_A > ; impl < 'a , REG , const O : u8 > SOAR2_OAR2EN_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn soar2_oar2en_disable (self) -> & 'a mut crate :: W < REG > { self . variant (SOAR2_OAR2EN_A :: SOAR2_OAR2EN_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn soar2_oar2en_enable (self) -> & 'a mut crate :: W < REG > { self . variant (SOAR2_OAR2EN_A :: SOAR2_OAR2EN_ENABLE) } } # [doc = "Field `SOAR2_OAR2_MASK` reader - I2C Slave Own Address 2 Mask: This field specifies bits A6 through A0 of the slave address. The bits with value 1 in SOAR2.OAR2_MASK field will make the corresponding incoming address bits to match by default regardless of the value inside SOAR2.OAR2 i.e. corresponding SOAR2.OAR2 bit is a dont care."] pub type SOAR2_OAR2_MASK_R = crate :: FieldReader ; # [doc = "Field `SOAR2_OAR2_MASK` writer - I2C Slave Own Address 2 Mask: This field specifies bits A6 through A0 of the slave address. The bits with value 1 in SOAR2.OAR2_MASK field will make the corresponding incoming address bits to match by default regardless of the value inside SOAR2.OAR2 i.e. corresponding SOAR2.OAR2 bit is a dont care."] pub type SOAR2_OAR2_MASK_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 7 , O > ; impl R { # [doc = "Bits 0:6 - I2C Slave Own Address 2 This field specifies the alternate OAR2 address."] # [inline (always)] pub fn soar2_oar2 (& self) -> SOAR2_OAR2_R { SOAR2_OAR2_R :: new ((self . bits & 0x7f) as u8) } # [doc = "Bit 7 - I2C Slave Own Address 2 Enable"] # [inline (always)] pub fn soar2_oar2en (& self) -> SOAR2_OAR2EN_R { SOAR2_OAR2EN_R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bits 16:22 - I2C Slave Own Address 2 Mask: This field specifies bits A6 through A0 of the slave address. The bits with value 1 in SOAR2.OAR2_MASK field will make the corresponding incoming address bits to match by default regardless of the value inside SOAR2.OAR2 i.e. corresponding SOAR2.OAR2 bit is a dont care."] # [inline (always)] pub fn soar2_oar2_mask (& self) -> SOAR2_OAR2_MASK_R { SOAR2_OAR2_MASK_R :: new (((self . bits >> 16) & 0x7f) as u8) } } impl W { # [doc = "Bits 0:6 - I2C Slave Own Address 2 This field specifies the alternate OAR2 address."] # [inline (always)] # [must_use] pub fn soar2_oar2 (& mut self) -> SOAR2_OAR2_W <'_, SOAR2_SPEC , 0 > { SOAR2_OAR2_W :: new (self) } # [doc = "Bit 7 - I2C Slave Own Address 2 Enable"] # [inline (always)] # [must_use] pub fn soar2_oar2en (& mut self) -> SOAR2_OAR2EN_W < SOAR2_SPEC , 7 > { SOAR2_OAR2EN_W :: new (self) } # [doc = "Bits 16:22 - I2C Slave Own Address 2 Mask: This field specifies bits A6 through A0 of the slave address. The bits with value 1 in SOAR2.OAR2_MASK field will make the corresponding incoming address bits to match by default regardless of the value inside SOAR2.OAR2 i.e. corresponding SOAR2.OAR2 bit is a dont care."] # [inline (always)] # [must_use] pub fn soar2_oar2_mask (& mut self) -> SOAR2_OAR2_MASK_W < SOAR2_SPEC , 16 > { SOAR2_OAR2_MASK_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "I2C Slave Own Address 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`soar2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`soar2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct SOAR2_SPEC ; impl crate :: RegisterSpec for SOAR2_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`soar2::R`](R) reader structure"] impl crate :: Readable for SOAR2_SPEC { } # [doc = "`write(|w| ..)` method takes [`soar2::W`](W) writer structure"] impl crate :: Writable for SOAR2_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets SOAR2 to value 0"] impl crate :: Resettable for SOAR2_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/uart0/rstctl.rs:1:3464 [INFO] [stdout] | [INFO] [stdout] 1 | ... rstctl_resetstkyclr (& mut self) -> RSTCTL_RESETSTKYCLR_W < RSTCTL_SPEC , 1 > { RSTCTL_RESETSTKYCLR_W :: new (self) } # [doc = "Bits ... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `RSTCTL` writer"] pub type W = crate :: W < RSTCTL_SPEC > ; # [doc = "Assert reset to the peripheral\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum RSTCTL_RESETASSERT_AW { # [doc = "0: NOP"] RSTCTL_RESETASSERT_NOP = 0 , # [doc = "1: ASSERT"] RSTCTL_RESETASSERT_ASSERT = 1 , } impl From < RSTCTL_RESETASSERT_AW > for bool { # [inline (always)] fn from (variant : RSTCTL_RESETASSERT_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `RSTCTL_RESETASSERT` writer - Assert reset to the peripheral"] pub type RSTCTL_RESETASSERT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , RSTCTL_RESETASSERT_AW > ; impl < 'a , REG , const O : u8 > RSTCTL_RESETASSERT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NOP"] # [inline (always)] pub fn rstctl_resetassert_nop (self) -> & 'a mut crate :: W < REG > { self . variant (RSTCTL_RESETASSERT_AW :: RSTCTL_RESETASSERT_NOP) } # [doc = "ASSERT"] # [inline (always)] pub fn rstctl_resetassert_assert (self) -> & 'a mut crate :: W < REG > { self . variant (RSTCTL_RESETASSERT_AW :: RSTCTL_RESETASSERT_ASSERT) } } # [doc = "Clear the RESETSTKY bit in the STAT register\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum RSTCTL_RESETSTKYCLR_AW { # [doc = "0: NOP"] RSTCTL_RESETSTKYCLR_NOP = 0 , # [doc = "1: CLR"] RSTCTL_RESETSTKYCLR_CLR = 1 , } impl From < RSTCTL_RESETSTKYCLR_AW > for bool { # [inline (always)] fn from (variant : RSTCTL_RESETSTKYCLR_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `RSTCTL_RESETSTKYCLR` writer - Clear the RESETSTKY bit in the STAT register"] pub type RSTCTL_RESETSTKYCLR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , RSTCTL_RESETSTKYCLR_AW > ; impl < 'a , REG , const O : u8 > RSTCTL_RESETSTKYCLR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NOP"] # [inline (always)] pub fn rstctl_resetstkyclr_nop (self) -> & 'a mut crate :: W < REG > { self . variant (RSTCTL_RESETSTKYCLR_AW :: RSTCTL_RESETSTKYCLR_NOP) } # [doc = "CLR"] # [inline (always)] pub fn rstctl_resetstkyclr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (RSTCTL_RESETSTKYCLR_AW :: RSTCTL_RESETSTKYCLR_CLR) } } # [doc = "Unlock key\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum RSTCTL_KEY_AW { # [doc = "177: _TO_UNLOCK_W_"] RSTCTL_KEY_UNLOCK_W = 177 , } impl From < RSTCTL_KEY_AW > for u8 { # [inline (always)] fn from (variant : RSTCTL_KEY_AW) -> Self { variant as _ } } impl crate :: FieldSpec for RSTCTL_KEY_AW { type Ux = u8 ; } # [doc = "Field `RSTCTL_KEY` writer - Unlock key"] pub type RSTCTL_KEY_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 8 , O , RSTCTL_KEY_AW > ; impl < 'a , REG , const O : u8 > RSTCTL_KEY_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "_TO_UNLOCK_W_"] # [inline (always)] pub fn rstctl_key_unlock_w (self) -> & 'a mut crate :: W < REG > { self . variant (RSTCTL_KEY_AW :: RSTCTL_KEY_UNLOCK_W) } } impl W { # [doc = "Bit 0 - Assert reset to the peripheral"] # [inline (always)] # [must_use] pub fn rstctl_resetassert (& mut self) -> RSTCTL_RESETASSERT_W < RSTCTL_SPEC , 0 > { RSTCTL_RESETASSERT_W :: new (self) } # [doc = "Bit 1 - Clear the RESETSTKY bit in the STAT register"] # [inline (always)] # [must_use] pub fn rstctl_resetstkyclr (& mut self) -> RSTCTL_RESETSTKYCLR_W <'_, RSTCTL_SPEC , 1 > { RSTCTL_RESETSTKYCLR_W :: new (self) } # [doc = "Bits 24:31 - Unlock key"] # [inline (always)] # [must_use] pub fn rstctl_key (& mut self) -> RSTCTL_KEY_W < RSTCTL_SPEC , 24 > { RSTCTL_KEY_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Reset Control\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rstctl::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct RSTCTL_SPEC ; impl crate :: RegisterSpec for RSTCTL_SPEC { type Ux = u32 ; } # [doc = "`write(|w| ..)` method takes [`rstctl::W`](W) writer structure"] impl crate :: Writable for RSTCTL_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets RSTCTL to value 0"] impl crate :: Resettable for RSTCTL_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/timg4/ccctl_01.rs:1:34235 [INFO] [stdout] | [INFO] [stdout] 1 | ... pub fn ccctl_01_lcond (& mut self) -> CCCTL_01_LCOND_W < CCCTL_01_SPEC , 8 > { CCCTL_01_LCOND_W :: new (self) } # [doc = "Bits 12:14 ... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `CCCTL_01[%s]` reader"] pub type R = crate :: R < CCCTL_01_SPEC > ; # [doc = "Register `CCCTL_01[%s]` writer"] pub type W = crate :: W < CCCTL_01_SPEC > ; # [doc = "Field `CCCTL_01_CCOND` reader - Capture Condition. #br# Specifies the condition that generates a capture pulse. 4h-Fh = Reserved"] pub type CCCTL_01_CCOND_R = crate :: FieldReader < CCCTL_01_CCOND_A > ; # [doc = "Capture Condition. #br# Specifies the condition that generates a capture pulse. 4h-Fh = Reserved\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum CCCTL_01_CCOND_A { # [doc = "0: NOCAPTURE"] CCCTL_01_CCOND_NOCAPTURE = 0 , # [doc = "1: CC_TRIG_RISE"] CCCTL_01_CCOND_CC_TRIG_RISE = 1 , # [doc = "2: CC_TRIG_FALL"] CCCTL_01_CCOND_CC_TRIG_FALL = 2 , # [doc = "3: CC_TRIG_EDGE"] CCCTL_01_CCOND_CC_TRIG_EDGE = 3 , } impl From < CCCTL_01_CCOND_A > for u8 { # [inline (always)] fn from (variant : CCCTL_01_CCOND_A) -> Self { variant as _ } } impl crate :: FieldSpec for CCCTL_01_CCOND_A { type Ux = u8 ; } impl CCCTL_01_CCOND_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < CCCTL_01_CCOND_A > { match self . bits { 0 => Some (CCCTL_01_CCOND_A :: CCCTL_01_CCOND_NOCAPTURE) , 1 => Some (CCCTL_01_CCOND_A :: CCCTL_01_CCOND_CC_TRIG_RISE) , 2 => Some (CCCTL_01_CCOND_A :: CCCTL_01_CCOND_CC_TRIG_FALL) , 3 => Some (CCCTL_01_CCOND_A :: CCCTL_01_CCOND_CC_TRIG_EDGE) , _ => None , } } # [doc = "NOCAPTURE"] # [inline (always)] pub fn is_ccctl_01_ccond_nocapture (& self) -> bool { * self == CCCTL_01_CCOND_A :: CCCTL_01_CCOND_NOCAPTURE } # [doc = "CC_TRIG_RISE"] # [inline (always)] pub fn is_ccctl_01_ccond_cc_trig_rise (& self) -> bool { * self == CCCTL_01_CCOND_A :: CCCTL_01_CCOND_CC_TRIG_RISE } # [doc = "CC_TRIG_FALL"] # [inline (always)] pub fn is_ccctl_01_ccond_cc_trig_fall (& self) -> bool { * self == CCCTL_01_CCOND_A :: CCCTL_01_CCOND_CC_TRIG_FALL } # [doc = "CC_TRIG_EDGE"] # [inline (always)] pub fn is_ccctl_01_ccond_cc_trig_edge (& self) -> bool { * self == CCCTL_01_CCOND_A :: CCCTL_01_CCOND_CC_TRIG_EDGE } } # [doc = "Field `CCCTL_01_CCOND` writer - Capture Condition. #br# Specifies the condition that generates a capture pulse. 4h-Fh = Reserved"] pub type CCCTL_01_CCOND_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 3 , O , CCCTL_01_CCOND_A > ; impl < 'a , REG , const O : u8 > CCCTL_01_CCOND_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "NOCAPTURE"] # [inline (always)] pub fn ccctl_01_ccond_nocapture (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CCOND_A :: CCCTL_01_CCOND_NOCAPTURE) } # [doc = "CC_TRIG_RISE"] # [inline (always)] pub fn ccctl_01_ccond_cc_trig_rise (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CCOND_A :: CCCTL_01_CCOND_CC_TRIG_RISE) } # [doc = "CC_TRIG_FALL"] # [inline (always)] pub fn ccctl_01_ccond_cc_trig_fall (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CCOND_A :: CCCTL_01_CCOND_CC_TRIG_FALL) } # [doc = "CC_TRIG_EDGE"] # [inline (always)] pub fn ccctl_01_ccond_cc_trig_edge (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CCOND_A :: CCCTL_01_CCOND_CC_TRIG_EDGE) } } # [doc = "Field `CCCTL_01_ACOND` reader - Advance Condition. #br# Specifies the condition that generates an advance pulse. 6h-Fh = Reserved"] pub type CCCTL_01_ACOND_R = crate :: FieldReader < CCCTL_01_ACOND_A > ; # [doc = "Advance Condition. #br# Specifies the condition that generates an advance pulse. 6h-Fh = Reserved\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum CCCTL_01_ACOND_A { # [doc = "0: TIMCLK"] CCCTL_01_ACOND_TIMCLK = 0 , # [doc = "1: CC_TRIG_RISE"] CCCTL_01_ACOND_CC_TRIG_RISE = 1 , # [doc = "2: CC_TRIG_FALL"] CCCTL_01_ACOND_CC_TRIG_FALL = 2 , # [doc = "3: CC_TRIG_EDGE"] CCCTL_01_ACOND_CC_TRIG_EDGE = 3 , # [doc = "5: CC_TRIG_HIGH"] CCCTL_01_ACOND_CC_TRIG_HIGH = 5 , } impl From < CCCTL_01_ACOND_A > for u8 { # [inline (always)] fn from (variant : CCCTL_01_ACOND_A) -> Self { variant as _ } } impl crate :: FieldSpec for CCCTL_01_ACOND_A { type Ux = u8 ; } impl CCCTL_01_ACOND_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < CCCTL_01_ACOND_A > { match self . bits { 0 => Some (CCCTL_01_ACOND_A :: CCCTL_01_ACOND_TIMCLK) , 1 => Some (CCCTL_01_ACOND_A :: CCCTL_01_ACOND_CC_TRIG_RISE) , 2 => Some (CCCTL_01_ACOND_A :: CCCTL_01_ACOND_CC_TRIG_FALL) , 3 => Some (CCCTL_01_ACOND_A :: CCCTL_01_ACOND_CC_TRIG_EDGE) , 5 => Some (CCCTL_01_ACOND_A :: CCCTL_01_ACOND_CC_TRIG_HIGH) , _ => None , } } # [doc = "TIMCLK"] # [inline (always)] pub fn is_ccctl_01_acond_timclk (& self) -> bool { * self == CCCTL_01_ACOND_A :: CCCTL_01_ACOND_TIMCLK } # [doc = "CC_TRIG_RISE"] # [inline (always)] pub fn is_ccctl_01_acond_cc_trig_rise (& self) -> bool { * self == CCCTL_01_ACOND_A :: CCCTL_01_ACOND_CC_TRIG_RISE } # [doc = "CC_TRIG_FALL"] # [inline (always)] pub fn is_ccctl_01_acond_cc_trig_fall (& self) -> bool { * self == CCCTL_01_ACOND_A :: CCCTL_01_ACOND_CC_TRIG_FALL } # [doc = "CC_TRIG_EDGE"] # [inline (always)] pub fn is_ccctl_01_acond_cc_trig_edge (& self) -> bool { * self == CCCTL_01_ACOND_A :: CCCTL_01_ACOND_CC_TRIG_EDGE } # [doc = "CC_TRIG_HIGH"] # [inline (always)] pub fn is_ccctl_01_acond_cc_trig_high (& self) -> bool { * self == CCCTL_01_ACOND_A :: CCCTL_01_ACOND_CC_TRIG_HIGH } } # [doc = "Field `CCCTL_01_ACOND` writer - Advance Condition. #br# Specifies the condition that generates an advance pulse. 6h-Fh = Reserved"] pub type CCCTL_01_ACOND_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 3 , O , CCCTL_01_ACOND_A > ; impl < 'a , REG , const O : u8 > CCCTL_01_ACOND_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "TIMCLK"] # [inline (always)] pub fn ccctl_01_acond_timclk (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_ACOND_A :: CCCTL_01_ACOND_TIMCLK) } # [doc = "CC_TRIG_RISE"] # [inline (always)] pub fn ccctl_01_acond_cc_trig_rise (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_ACOND_A :: CCCTL_01_ACOND_CC_TRIG_RISE) } # [doc = "CC_TRIG_FALL"] # [inline (always)] pub fn ccctl_01_acond_cc_trig_fall (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_ACOND_A :: CCCTL_01_ACOND_CC_TRIG_FALL) } # [doc = "CC_TRIG_EDGE"] # [inline (always)] pub fn ccctl_01_acond_cc_trig_edge (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_ACOND_A :: CCCTL_01_ACOND_CC_TRIG_EDGE) } # [doc = "CC_TRIG_HIGH"] # [inline (always)] pub fn ccctl_01_acond_cc_trig_high (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_ACOND_A :: CCCTL_01_ACOND_CC_TRIG_HIGH) } } # [doc = "Field `CCCTL_01_LCOND` reader - Load Condition. #br# Specifies the condition that generates a load pulse. 4h-Fh = Reserved"] pub type CCCTL_01_LCOND_R = crate :: FieldReader < CCCTL_01_LCOND_A > ; # [doc = "Load Condition. #br# Specifies the condition that generates a load pulse. 4h-Fh = Reserved\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum CCCTL_01_LCOND_A { # [doc = "1: CC_TRIG_RISE"] CCCTL_01_LCOND_CC_TRIG_RISE = 1 , # [doc = "2: CC_TRIG_FALL"] CCCTL_01_LCOND_CC_TRIG_FALL = 2 , # [doc = "3: CC_TRIG_EDGE"] CCCTL_01_LCOND_CC_TRIG_EDGE = 3 , } impl From < CCCTL_01_LCOND_A > for u8 { # [inline (always)] fn from (variant : CCCTL_01_LCOND_A) -> Self { variant as _ } } impl crate :: FieldSpec for CCCTL_01_LCOND_A { type Ux = u8 ; } impl CCCTL_01_LCOND_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < CCCTL_01_LCOND_A > { match self . bits { 1 => Some (CCCTL_01_LCOND_A :: CCCTL_01_LCOND_CC_TRIG_RISE) , 2 => Some (CCCTL_01_LCOND_A :: CCCTL_01_LCOND_CC_TRIG_FALL) , 3 => Some (CCCTL_01_LCOND_A :: CCCTL_01_LCOND_CC_TRIG_EDGE) , _ => None , } } # [doc = "CC_TRIG_RISE"] # [inline (always)] pub fn is_ccctl_01_lcond_cc_trig_rise (& self) -> bool { * self == CCCTL_01_LCOND_A :: CCCTL_01_LCOND_CC_TRIG_RISE } # [doc = "CC_TRIG_FALL"] # [inline (always)] pub fn is_ccctl_01_lcond_cc_trig_fall (& self) -> bool { * self == CCCTL_01_LCOND_A :: CCCTL_01_LCOND_CC_TRIG_FALL } # [doc = "CC_TRIG_EDGE"] # [inline (always)] pub fn is_ccctl_01_lcond_cc_trig_edge (& self) -> bool { * self == CCCTL_01_LCOND_A :: CCCTL_01_LCOND_CC_TRIG_EDGE } } # [doc = "Field `CCCTL_01_LCOND` writer - Load Condition. #br# Specifies the condition that generates a load pulse. 4h-Fh = Reserved"] pub type CCCTL_01_LCOND_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 3 , O , CCCTL_01_LCOND_A > ; impl < 'a , REG , const O : u8 > CCCTL_01_LCOND_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "CC_TRIG_RISE"] # [inline (always)] pub fn ccctl_01_lcond_cc_trig_rise (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_LCOND_A :: CCCTL_01_LCOND_CC_TRIG_RISE) } # [doc = "CC_TRIG_FALL"] # [inline (always)] pub fn ccctl_01_lcond_cc_trig_fall (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_LCOND_A :: CCCTL_01_LCOND_CC_TRIG_FALL) } # [doc = "CC_TRIG_EDGE"] # [inline (always)] pub fn ccctl_01_lcond_cc_trig_edge (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_LCOND_A :: CCCTL_01_LCOND_CC_TRIG_EDGE) } } # [doc = "Field `CCCTL_01_ZCOND` reader - Zero Condition. #br# This field specifies the condition that generates a zero pulse. 4h-Fh = Reserved"] pub type CCCTL_01_ZCOND_R = crate :: FieldReader < CCCTL_01_ZCOND_A > ; # [doc = "Zero Condition. #br# This field specifies the condition that generates a zero pulse. 4h-Fh = Reserved\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum CCCTL_01_ZCOND_A { # [doc = "1: CC_TRIG_RISE"] CCCTL_01_ZCOND_CC_TRIG_RISE = 1 , # [doc = "2: CC_TRIG_FALL"] CCCTL_01_ZCOND_CC_TRIG_FALL = 2 , # [doc = "3: CC_TRIG_EDGE"] CCCTL_01_ZCOND_CC_TRIG_EDGE = 3 , } impl From < CCCTL_01_ZCOND_A > for u8 { # [inline (always)] fn from (variant : CCCTL_01_ZCOND_A) -> Self { variant as _ } } impl crate :: FieldSpec for CCCTL_01_ZCOND_A { type Ux = u8 ; } impl CCCTL_01_ZCOND_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < CCCTL_01_ZCOND_A > { match self . bits { 1 => Some (CCCTL_01_ZCOND_A :: CCCTL_01_ZCOND_CC_TRIG_RISE) , 2 => Some (CCCTL_01_ZCOND_A :: CCCTL_01_ZCOND_CC_TRIG_FALL) , 3 => Some (CCCTL_01_ZCOND_A :: CCCTL_01_ZCOND_CC_TRIG_EDGE) , _ => None , } } # [doc = "CC_TRIG_RISE"] # [inline (always)] pub fn is_ccctl_01_zcond_cc_trig_rise (& self) -> bool { * self == CCCTL_01_ZCOND_A :: CCCTL_01_ZCOND_CC_TRIG_RISE } # [doc = "CC_TRIG_FALL"] # [inline (always)] pub fn is_ccctl_01_zcond_cc_trig_fall (& self) -> bool { * self == CCCTL_01_ZCOND_A :: CCCTL_01_ZCOND_CC_TRIG_FALL } # [doc = "CC_TRIG_EDGE"] # [inline (always)] pub fn is_ccctl_01_zcond_cc_trig_edge (& self) -> bool { * self == CCCTL_01_ZCOND_A :: CCCTL_01_ZCOND_CC_TRIG_EDGE } } # [doc = "Field `CCCTL_01_ZCOND` writer - Zero Condition. #br# This field specifies the condition that generates a zero pulse. 4h-Fh = Reserved"] pub type CCCTL_01_ZCOND_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 3 , O , CCCTL_01_ZCOND_A > ; impl < 'a , REG , const O : u8 > CCCTL_01_ZCOND_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "CC_TRIG_RISE"] # [inline (always)] pub fn ccctl_01_zcond_cc_trig_rise (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_ZCOND_A :: CCCTL_01_ZCOND_CC_TRIG_RISE) } # [doc = "CC_TRIG_FALL"] # [inline (always)] pub fn ccctl_01_zcond_cc_trig_fall (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_ZCOND_A :: CCCTL_01_ZCOND_CC_TRIG_FALL) } # [doc = "CC_TRIG_EDGE"] # [inline (always)] pub fn ccctl_01_zcond_cc_trig_edge (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_ZCOND_A :: CCCTL_01_ZCOND_CC_TRIG_EDGE) } } # [doc = "Field `CCCTL_01_COC` reader - Capture or Compare. #br# Specifies whether the corresponding CC register is used as a capture register or a compare register (never both)."] pub type CCCTL_01_COC_R = crate :: BitReader < CCCTL_01_COC_A > ; # [doc = "Capture or Compare. #br# Specifies whether the corresponding CC register is used as a capture register or a compare register (never both).\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CCCTL_01_COC_A { # [doc = "0: COMPARE"] CCCTL_01_COC_COMPARE = 0 , # [doc = "1: CAPTURE"] CCCTL_01_COC_CAPTURE = 1 , } impl From < CCCTL_01_COC_A > for bool { # [inline (always)] fn from (variant : CCCTL_01_COC_A) -> Self { variant as u8 != 0 } } impl CCCTL_01_COC_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CCCTL_01_COC_A { match self . bits { false => CCCTL_01_COC_A :: CCCTL_01_COC_COMPARE , true => CCCTL_01_COC_A :: CCCTL_01_COC_CAPTURE , } } # [doc = "COMPARE"] # [inline (always)] pub fn is_ccctl_01_coc_compare (& self) -> bool { * self == CCCTL_01_COC_A :: CCCTL_01_COC_COMPARE } # [doc = "CAPTURE"] # [inline (always)] pub fn is_ccctl_01_coc_capture (& self) -> bool { * self == CCCTL_01_COC_A :: CCCTL_01_COC_CAPTURE } } # [doc = "Field `CCCTL_01_COC` writer - Capture or Compare. #br# Specifies whether the corresponding CC register is used as a capture register or a compare register (never both)."] pub type CCCTL_01_COC_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CCCTL_01_COC_A > ; impl < 'a , REG , const O : u8 > CCCTL_01_COC_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "COMPARE"] # [inline (always)] pub fn ccctl_01_coc_compare (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_COC_A :: CCCTL_01_COC_COMPARE) } # [doc = "CAPTURE"] # [inline (always)] pub fn ccctl_01_coc_capture (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_COC_A :: CCCTL_01_COC_CAPTURE) } } # [doc = "Field `CCCTL_01_CCUPD` reader - Capture and Compare Update Method This field controls how updates to the pipelined capture and compare register are performed (when operating in compare mode, COC=0)."] pub type CCCTL_01_CCUPD_R = crate :: FieldReader < CCCTL_01_CCUPD_A > ; # [doc = "Capture and Compare Update Method This field controls how updates to the pipelined capture and compare register are performed (when operating in compare mode, COC=0).\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum CCCTL_01_CCUPD_A { # [doc = "0: IMMEDIATELY"] CCCTL_01_CCUPD_IMMEDIATELY = 0 , # [doc = "1: ZERO_EVT"] CCCTL_01_CCUPD_ZERO_EVT = 1 , # [doc = "2: COMPARE_DOWN_EVT"] CCCTL_01_CCUPD_COMPARE_DOWN_EVT = 2 , # [doc = "3: COMPARE_UP_EVT"] CCCTL_01_CCUPD_COMPARE_UP_EVT = 3 , # [doc = "4: ZERO_LOAD_EVT"] CCCTL_01_CCUPD_ZERO_LOAD_EVT = 4 , # [doc = "5: ZERO_RC_ZERO_EVT"] CCCTL_01_CCUPD_ZERO_RC_ZERO_EVT = 5 , # [doc = "6: TRIG"] CCCTL_01_CCUPD_TRIG = 6 , } impl From < CCCTL_01_CCUPD_A > for u8 { # [inline (always)] fn from (variant : CCCTL_01_CCUPD_A) -> Self { variant as _ } } impl crate :: FieldSpec for CCCTL_01_CCUPD_A { type Ux = u8 ; } impl CCCTL_01_CCUPD_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < CCCTL_01_CCUPD_A > { match self . bits { 0 => Some (CCCTL_01_CCUPD_A :: CCCTL_01_CCUPD_IMMEDIATELY) , 1 => Some (CCCTL_01_CCUPD_A :: CCCTL_01_CCUPD_ZERO_EVT) , 2 => Some (CCCTL_01_CCUPD_A :: CCCTL_01_CCUPD_COMPARE_DOWN_EVT) , 3 => Some (CCCTL_01_CCUPD_A :: CCCTL_01_CCUPD_COMPARE_UP_EVT) , 4 => Some (CCCTL_01_CCUPD_A :: CCCTL_01_CCUPD_ZERO_LOAD_EVT) , 5 => Some (CCCTL_01_CCUPD_A :: CCCTL_01_CCUPD_ZERO_RC_ZERO_EVT) , 6 => Some (CCCTL_01_CCUPD_A :: CCCTL_01_CCUPD_TRIG) , _ => None , } } # [doc = "IMMEDIATELY"] # [inline (always)] pub fn is_ccctl_01_ccupd_immediately (& self) -> bool { * self == CCCTL_01_CCUPD_A :: CCCTL_01_CCUPD_IMMEDIATELY } # [doc = "ZERO_EVT"] # [inline (always)] pub fn is_ccctl_01_ccupd_zero_evt (& self) -> bool { * self == CCCTL_01_CCUPD_A :: CCCTL_01_CCUPD_ZERO_EVT } # [doc = "COMPARE_DOWN_EVT"] # [inline (always)] pub fn is_ccctl_01_ccupd_compare_down_evt (& self) -> bool { * self == CCCTL_01_CCUPD_A :: CCCTL_01_CCUPD_COMPARE_DOWN_EVT } # [doc = "COMPARE_UP_EVT"] # [inline (always)] pub fn is_ccctl_01_ccupd_compare_up_evt (& self) -> bool { * self == CCCTL_01_CCUPD_A :: CCCTL_01_CCUPD_COMPARE_UP_EVT } # [doc = "ZERO_LOAD_EVT"] # [inline (always)] pub fn is_ccctl_01_ccupd_zero_load_evt (& self) -> bool { * self == CCCTL_01_CCUPD_A :: CCCTL_01_CCUPD_ZERO_LOAD_EVT } # [doc = "ZERO_RC_ZERO_EVT"] # [inline (always)] pub fn is_ccctl_01_ccupd_zero_rc_zero_evt (& self) -> bool { * self == CCCTL_01_CCUPD_A :: CCCTL_01_CCUPD_ZERO_RC_ZERO_EVT } # [doc = "TRIG"] # [inline (always)] pub fn is_ccctl_01_ccupd_trig (& self) -> bool { * self == CCCTL_01_CCUPD_A :: CCCTL_01_CCUPD_TRIG } } # [doc = "Field `CCCTL_01_CCUPD` writer - Capture and Compare Update Method This field controls how updates to the pipelined capture and compare register are performed (when operating in compare mode, COC=0)."] pub type CCCTL_01_CCUPD_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 3 , O , CCCTL_01_CCUPD_A > ; impl < 'a , REG , const O : u8 > CCCTL_01_CCUPD_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "IMMEDIATELY"] # [inline (always)] pub fn ccctl_01_ccupd_immediately (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CCUPD_A :: CCCTL_01_CCUPD_IMMEDIATELY) } # [doc = "ZERO_EVT"] # [inline (always)] pub fn ccctl_01_ccupd_zero_evt (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CCUPD_A :: CCCTL_01_CCUPD_ZERO_EVT) } # [doc = "COMPARE_DOWN_EVT"] # [inline (always)] pub fn ccctl_01_ccupd_compare_down_evt (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CCUPD_A :: CCCTL_01_CCUPD_COMPARE_DOWN_EVT) } # [doc = "COMPARE_UP_EVT"] # [inline (always)] pub fn ccctl_01_ccupd_compare_up_evt (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CCUPD_A :: CCCTL_01_CCUPD_COMPARE_UP_EVT) } # [doc = "ZERO_LOAD_EVT"] # [inline (always)] pub fn ccctl_01_ccupd_zero_load_evt (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CCUPD_A :: CCCTL_01_CCUPD_ZERO_LOAD_EVT) } # [doc = "ZERO_RC_ZERO_EVT"] # [inline (always)] pub fn ccctl_01_ccupd_zero_rc_zero_evt (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CCUPD_A :: CCCTL_01_CCUPD_ZERO_RC_ZERO_EVT) } # [doc = "TRIG"] # [inline (always)] pub fn ccctl_01_ccupd_trig (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CCUPD_A :: CCCTL_01_CCUPD_TRIG) } } # [doc = "Field `CCCTL_01_CC2SELU` reader - Selects the source second CCU event."] pub type CCCTL_01_CC2SELU_R = crate :: FieldReader < CCCTL_01_CC2SELU_A > ; # [doc = "Selects the source second CCU event.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum CCCTL_01_CC2SELU_A { # [doc = "0: SEL_CCU0"] CCCTL_01_CC2SELU_SEL_CCU0 = 0 , # [doc = "1: SEL_CCU1"] CCCTL_01_CC2SELU_SEL_CCU1 = 1 , # [doc = "2: SEL_CCU2"] CCCTL_01_CC2SELU_SEL_CCU2 = 2 , # [doc = "3: SEL_CCU3"] CCCTL_01_CC2SELU_SEL_CCU3 = 3 , # [doc = "4: SEL_CCU4"] CCCTL_01_CC2SELU_SEL_CCU4 = 4 , # [doc = "5: SEL_CCU5"] CCCTL_01_CC2SELU_SEL_CCU5 = 5 , } impl From < CCCTL_01_CC2SELU_A > for u8 { # [inline (always)] fn from (variant : CCCTL_01_CC2SELU_A) -> Self { variant as _ } } impl crate :: FieldSpec for CCCTL_01_CC2SELU_A { type Ux = u8 ; } impl CCCTL_01_CC2SELU_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < CCCTL_01_CC2SELU_A > { match self . bits { 0 => Some (CCCTL_01_CC2SELU_A :: CCCTL_01_CC2SELU_SEL_CCU0) , 1 => Some (CCCTL_01_CC2SELU_A :: CCCTL_01_CC2SELU_SEL_CCU1) , 2 => Some (CCCTL_01_CC2SELU_A :: CCCTL_01_CC2SELU_SEL_CCU2) , 3 => Some (CCCTL_01_CC2SELU_A :: CCCTL_01_CC2SELU_SEL_CCU3) , 4 => Some (CCCTL_01_CC2SELU_A :: CCCTL_01_CC2SELU_SEL_CCU4) , 5 => Some (CCCTL_01_CC2SELU_A :: CCCTL_01_CC2SELU_SEL_CCU5) , _ => None , } } # [doc = "SEL_CCU0"] # [inline (always)] pub fn is_ccctl_01_cc2selu_sel_ccu0 (& self) -> bool { * self == CCCTL_01_CC2SELU_A :: CCCTL_01_CC2SELU_SEL_CCU0 } # [doc = "SEL_CCU1"] # [inline (always)] pub fn is_ccctl_01_cc2selu_sel_ccu1 (& self) -> bool { * self == CCCTL_01_CC2SELU_A :: CCCTL_01_CC2SELU_SEL_CCU1 } # [doc = "SEL_CCU2"] # [inline (always)] pub fn is_ccctl_01_cc2selu_sel_ccu2 (& self) -> bool { * self == CCCTL_01_CC2SELU_A :: CCCTL_01_CC2SELU_SEL_CCU2 } # [doc = "SEL_CCU3"] # [inline (always)] pub fn is_ccctl_01_cc2selu_sel_ccu3 (& self) -> bool { * self == CCCTL_01_CC2SELU_A :: CCCTL_01_CC2SELU_SEL_CCU3 } # [doc = "SEL_CCU4"] # [inline (always)] pub fn is_ccctl_01_cc2selu_sel_ccu4 (& self) -> bool { * self == CCCTL_01_CC2SELU_A :: CCCTL_01_CC2SELU_SEL_CCU4 } # [doc = "SEL_CCU5"] # [inline (always)] pub fn is_ccctl_01_cc2selu_sel_ccu5 (& self) -> bool { * self == CCCTL_01_CC2SELU_A :: CCCTL_01_CC2SELU_SEL_CCU5 } } # [doc = "Field `CCCTL_01_CC2SELU` writer - Selects the source second CCU event."] pub type CCCTL_01_CC2SELU_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 3 , O , CCCTL_01_CC2SELU_A > ; impl < 'a , REG , const O : u8 > CCCTL_01_CC2SELU_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "SEL_CCU0"] # [inline (always)] pub fn ccctl_01_cc2selu_sel_ccu0 (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CC2SELU_A :: CCCTL_01_CC2SELU_SEL_CCU0) } # [doc = "SEL_CCU1"] # [inline (always)] pub fn ccctl_01_cc2selu_sel_ccu1 (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CC2SELU_A :: CCCTL_01_CC2SELU_SEL_CCU1) } # [doc = "SEL_CCU2"] # [inline (always)] pub fn ccctl_01_cc2selu_sel_ccu2 (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CC2SELU_A :: CCCTL_01_CC2SELU_SEL_CCU2) } # [doc = "SEL_CCU3"] # [inline (always)] pub fn ccctl_01_cc2selu_sel_ccu3 (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CC2SELU_A :: CCCTL_01_CC2SELU_SEL_CCU3) } # [doc = "SEL_CCU4"] # [inline (always)] pub fn ccctl_01_cc2selu_sel_ccu4 (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CC2SELU_A :: CCCTL_01_CC2SELU_SEL_CCU4) } # [doc = "SEL_CCU5"] # [inline (always)] pub fn ccctl_01_cc2selu_sel_ccu5 (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CC2SELU_A :: CCCTL_01_CC2SELU_SEL_CCU5) } } # [doc = "Field `CCCTL_01_CCACTUPD` reader - CCACT shadow register Update Method This field controls how updates to the CCCACT shadow register are performed"] pub type CCCTL_01_CCACTUPD_R = crate :: FieldReader < CCCTL_01_CCACTUPD_A > ; # [doc = "CCACT shadow register Update Method This field controls how updates to the CCCACT shadow register are performed\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum CCCTL_01_CCACTUPD_A { # [doc = "0: IMMEDIATELY"] CCCTL_01_CCACTUPD_IMMEDIATELY = 0 , # [doc = "1: ZERO_EVT"] CCCTL_01_CCACTUPD_ZERO_EVT = 1 , # [doc = "2: COMPARE_DOWN_EVT"] CCCTL_01_CCACTUPD_COMPARE_DOWN_EVT = 2 , # [doc = "3: COMPARE_UP_EVT"] CCCTL_01_CCACTUPD_COMPARE_UP_EVT = 3 , # [doc = "4: ZERO_LOAD_EVT"] CCCTL_01_CCACTUPD_ZERO_LOAD_EVT = 4 , # [doc = "5: ZERO_RC_ZERO_EVT"] CCCTL_01_CCACTUPD_ZERO_RC_ZERO_EVT = 5 , # [doc = "6: TRIG"] CCCTL_01_CCACTUPD_TRIG = 6 , } impl From < CCCTL_01_CCACTUPD_A > for u8 { # [inline (always)] fn from (variant : CCCTL_01_CCACTUPD_A) -> Self { variant as _ } } impl crate :: FieldSpec for CCCTL_01_CCACTUPD_A { type Ux = u8 ; } impl CCCTL_01_CCACTUPD_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < CCCTL_01_CCACTUPD_A > { match self . bits { 0 => Some (CCCTL_01_CCACTUPD_A :: CCCTL_01_CCACTUPD_IMMEDIATELY) , 1 => Some (CCCTL_01_CCACTUPD_A :: CCCTL_01_CCACTUPD_ZERO_EVT) , 2 => Some (CCCTL_01_CCACTUPD_A :: CCCTL_01_CCACTUPD_COMPARE_DOWN_EVT) , 3 => Some (CCCTL_01_CCACTUPD_A :: CCCTL_01_CCACTUPD_COMPARE_UP_EVT) , 4 => Some (CCCTL_01_CCACTUPD_A :: CCCTL_01_CCACTUPD_ZERO_LOAD_EVT) , 5 => Some (CCCTL_01_CCACTUPD_A :: CCCTL_01_CCACTUPD_ZERO_RC_ZERO_EVT) , 6 => Some (CCCTL_01_CCACTUPD_A :: CCCTL_01_CCACTUPD_TRIG) , _ => None , } } # [doc = "IMMEDIATELY"] # [inline (always)] pub fn is_ccctl_01_ccactupd_immediately (& self) -> bool { * self == CCCTL_01_CCACTUPD_A :: CCCTL_01_CCACTUPD_IMMEDIATELY } # [doc = "ZERO_EVT"] # [inline (always)] pub fn is_ccctl_01_ccactupd_zero_evt (& self) -> bool { * self == CCCTL_01_CCACTUPD_A :: CCCTL_01_CCACTUPD_ZERO_EVT } # [doc = "COMPARE_DOWN_EVT"] # [inline (always)] pub fn is_ccctl_01_ccactupd_compare_down_evt (& self) -> bool { * self == CCCTL_01_CCACTUPD_A :: CCCTL_01_CCACTUPD_COMPARE_DOWN_EVT } # [doc = "COMPARE_UP_EVT"] # [inline (always)] pub fn is_ccctl_01_ccactupd_compare_up_evt (& self) -> bool { * self == CCCTL_01_CCACTUPD_A :: CCCTL_01_CCACTUPD_COMPARE_UP_EVT } # [doc = "ZERO_LOAD_EVT"] # [inline (always)] pub fn is_ccctl_01_ccactupd_zero_load_evt (& self) -> bool { * self == CCCTL_01_CCACTUPD_A :: CCCTL_01_CCACTUPD_ZERO_LOAD_EVT } # [doc = "ZERO_RC_ZERO_EVT"] # [inline (always)] pub fn is_ccctl_01_ccactupd_zero_rc_zero_evt (& self) -> bool { * self == CCCTL_01_CCACTUPD_A :: CCCTL_01_CCACTUPD_ZERO_RC_ZERO_EVT } # [doc = "TRIG"] # [inline (always)] pub fn is_ccctl_01_ccactupd_trig (& self) -> bool { * self == CCCTL_01_CCACTUPD_A :: CCCTL_01_CCACTUPD_TRIG } } # [doc = "Field `CCCTL_01_CCACTUPD` writer - CCACT shadow register Update Method This field controls how updates to the CCCACT shadow register are performed"] pub type CCCTL_01_CCACTUPD_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 3 , O , CCCTL_01_CCACTUPD_A > ; impl < 'a , REG , const O : u8 > CCCTL_01_CCACTUPD_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "IMMEDIATELY"] # [inline (always)] pub fn ccctl_01_ccactupd_immediately (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CCACTUPD_A :: CCCTL_01_CCACTUPD_IMMEDIATELY) } # [doc = "ZERO_EVT"] # [inline (always)] pub fn ccctl_01_ccactupd_zero_evt (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CCACTUPD_A :: CCCTL_01_CCACTUPD_ZERO_EVT) } # [doc = "COMPARE_DOWN_EVT"] # [inline (always)] pub fn ccctl_01_ccactupd_compare_down_evt (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CCACTUPD_A :: CCCTL_01_CCACTUPD_COMPARE_DOWN_EVT) } # [doc = "COMPARE_UP_EVT"] # [inline (always)] pub fn ccctl_01_ccactupd_compare_up_evt (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CCACTUPD_A :: CCCTL_01_CCACTUPD_COMPARE_UP_EVT) } # [doc = "ZERO_LOAD_EVT"] # [inline (always)] pub fn ccctl_01_ccactupd_zero_load_evt (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CCACTUPD_A :: CCCTL_01_CCACTUPD_ZERO_LOAD_EVT) } # [doc = "ZERO_RC_ZERO_EVT"] # [inline (always)] pub fn ccctl_01_ccactupd_zero_rc_zero_evt (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CCACTUPD_A :: CCCTL_01_CCACTUPD_ZERO_RC_ZERO_EVT) } # [doc = "TRIG"] # [inline (always)] pub fn ccctl_01_ccactupd_trig (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CCACTUPD_A :: CCCTL_01_CCACTUPD_TRIG) } } # [doc = "Field `CCCTL_01_CC2SELD` reader - Selects the source second CCD event."] pub type CCCTL_01_CC2SELD_R = crate :: FieldReader < CCCTL_01_CC2SELD_A > ; # [doc = "Selects the source second CCD event.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum CCCTL_01_CC2SELD_A { # [doc = "0: SEL_CCD0"] CCCTL_01_CC2SELD_SEL_CCD0 = 0 , # [doc = "1: SEL_CCD1"] CCCTL_01_CC2SELD_SEL_CCD1 = 1 , # [doc = "2: SEL_CCD2"] CCCTL_01_CC2SELD_SEL_CCD2 = 2 , # [doc = "3: SEL_CCD3"] CCCTL_01_CC2SELD_SEL_CCD3 = 3 , # [doc = "4: SEL_CCD4"] CCCTL_01_CC2SELD_SEL_CCD4 = 4 , # [doc = "5: SEL_CCD5"] CCCTL_01_CC2SELD_SEL_CCD5 = 5 , } impl From < CCCTL_01_CC2SELD_A > for u8 { # [inline (always)] fn from (variant : CCCTL_01_CC2SELD_A) -> Self { variant as _ } } impl crate :: FieldSpec for CCCTL_01_CC2SELD_A { type Ux = u8 ; } impl CCCTL_01_CC2SELD_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < CCCTL_01_CC2SELD_A > { match self . bits { 0 => Some (CCCTL_01_CC2SELD_A :: CCCTL_01_CC2SELD_SEL_CCD0) , 1 => Some (CCCTL_01_CC2SELD_A :: CCCTL_01_CC2SELD_SEL_CCD1) , 2 => Some (CCCTL_01_CC2SELD_A :: CCCTL_01_CC2SELD_SEL_CCD2) , 3 => Some (CCCTL_01_CC2SELD_A :: CCCTL_01_CC2SELD_SEL_CCD3) , 4 => Some (CCCTL_01_CC2SELD_A :: CCCTL_01_CC2SELD_SEL_CCD4) , 5 => Some (CCCTL_01_CC2SELD_A :: CCCTL_01_CC2SELD_SEL_CCD5) , _ => None , } } # [doc = "SEL_CCD0"] # [inline (always)] pub fn is_ccctl_01_cc2seld_sel_ccd0 (& self) -> bool { * self == CCCTL_01_CC2SELD_A :: CCCTL_01_CC2SELD_SEL_CCD0 } # [doc = "SEL_CCD1"] # [inline (always)] pub fn is_ccctl_01_cc2seld_sel_ccd1 (& self) -> bool { * self == CCCTL_01_CC2SELD_A :: CCCTL_01_CC2SELD_SEL_CCD1 } # [doc = "SEL_CCD2"] # [inline (always)] pub fn is_ccctl_01_cc2seld_sel_ccd2 (& self) -> bool { * self == CCCTL_01_CC2SELD_A :: CCCTL_01_CC2SELD_SEL_CCD2 } # [doc = "SEL_CCD3"] # [inline (always)] pub fn is_ccctl_01_cc2seld_sel_ccd3 (& self) -> bool { * self == CCCTL_01_CC2SELD_A :: CCCTL_01_CC2SELD_SEL_CCD3 } # [doc = "SEL_CCD4"] # [inline (always)] pub fn is_ccctl_01_cc2seld_sel_ccd4 (& self) -> bool { * self == CCCTL_01_CC2SELD_A :: CCCTL_01_CC2SELD_SEL_CCD4 } # [doc = "SEL_CCD5"] # [inline (always)] pub fn is_ccctl_01_cc2seld_sel_ccd5 (& self) -> bool { * self == CCCTL_01_CC2SELD_A :: CCCTL_01_CC2SELD_SEL_CCD5 } } # [doc = "Field `CCCTL_01_CC2SELD` writer - Selects the source second CCD event."] pub type CCCTL_01_CC2SELD_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 3 , O , CCCTL_01_CC2SELD_A > ; impl < 'a , REG , const O : u8 > CCCTL_01_CC2SELD_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "SEL_CCD0"] # [inline (always)] pub fn ccctl_01_cc2seld_sel_ccd0 (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CC2SELD_A :: CCCTL_01_CC2SELD_SEL_CCD0) } # [doc = "SEL_CCD1"] # [inline (always)] pub fn ccctl_01_cc2seld_sel_ccd1 (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CC2SELD_A :: CCCTL_01_CC2SELD_SEL_CCD1) } # [doc = "SEL_CCD2"] # [inline (always)] pub fn ccctl_01_cc2seld_sel_ccd2 (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CC2SELD_A :: CCCTL_01_CC2SELD_SEL_CCD2) } # [doc = "SEL_CCD3"] # [inline (always)] pub fn ccctl_01_cc2seld_sel_ccd3 (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CC2SELD_A :: CCCTL_01_CC2SELD_SEL_CCD3) } # [doc = "SEL_CCD4"] # [inline (always)] pub fn ccctl_01_cc2seld_sel_ccd4 (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CC2SELD_A :: CCCTL_01_CC2SELD_SEL_CCD4) } # [doc = "SEL_CCD5"] # [inline (always)] pub fn ccctl_01_cc2seld_sel_ccd5 (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CC2SELD_A :: CCCTL_01_CC2SELD_SEL_CCD5) } } impl R { # [doc = "Bits 0:2 - Capture Condition. #br# Specifies the condition that generates a capture pulse. 4h-Fh = Reserved"] # [inline (always)] pub fn ccctl_01_ccond (& self) -> CCCTL_01_CCOND_R { CCCTL_01_CCOND_R :: new ((self . bits & 7) as u8) } # [doc = "Bits 4:6 - Advance Condition. #br# Specifies the condition that generates an advance pulse. 6h-Fh = Reserved"] # [inline (always)] pub fn ccctl_01_acond (& self) -> CCCTL_01_ACOND_R { CCCTL_01_ACOND_R :: new (((self . bits >> 4) & 7) as u8) } # [doc = "Bits 8:10 - Load Condition. #br# Specifies the condition that generates a load pulse. 4h-Fh = Reserved"] # [inline (always)] pub fn ccctl_01_lcond (& self) -> CCCTL_01_LCOND_R { CCCTL_01_LCOND_R :: new (((self . bits >> 8) & 7) as u8) } # [doc = "Bits 12:14 - Zero Condition. #br# This field specifies the condition that generates a zero pulse. 4h-Fh = Reserved"] # [inline (always)] pub fn ccctl_01_zcond (& self) -> CCCTL_01_ZCOND_R { CCCTL_01_ZCOND_R :: new (((self . bits >> 12) & 7) as u8) } # [doc = "Bit 17 - Capture or Compare. #br# Specifies whether the corresponding CC register is used as a capture register or a compare register (never both)."] # [inline (always)] pub fn ccctl_01_coc (& self) -> CCCTL_01_COC_R { CCCTL_01_COC_R :: new (((self . bits >> 17) & 1) != 0) } # [doc = "Bits 18:20 - Capture and Compare Update Method This field controls how updates to the pipelined capture and compare register are performed (when operating in compare mode, COC=0)."] # [inline (always)] pub fn ccctl_01_ccupd (& self) -> CCCTL_01_CCUPD_R { CCCTL_01_CCUPD_R :: new (((self . bits >> 18) & 7) as u8) } # [doc = "Bits 22:24 - Selects the source second CCU event."] # [inline (always)] pub fn ccctl_01_cc2selu (& self) -> CCCTL_01_CC2SELU_R { CCCTL_01_CC2SELU_R :: new (((self . bits >> 22) & 7) as u8) } # [doc = "Bits 26:28 - CCACT shadow register Update Method This field controls how updates to the CCCACT shadow register are performed"] # [inline (always)] pub fn ccctl_01_ccactupd (& self) -> CCCTL_01_CCACTUPD_R { CCCTL_01_CCACTUPD_R :: new (((self . bits >> 26) & 7) as u8) } # [doc = "Bits 29:31 - Selects the source second CCD event."] # [inline (always)] pub fn ccctl_01_cc2seld (& self) -> CCCTL_01_CC2SELD_R { CCCTL_01_CC2SELD_R :: new (((self . bits >> 29) & 7) as u8) } } impl W { # [doc = "Bits 0:2 - Capture Condition. #br# Specifies the condition that generates a capture pulse. 4h-Fh = Reserved"] # [inline (always)] # [must_use] pub fn ccctl_01_ccond (& mut self) -> CCCTL_01_CCOND_W < CCCTL_01_SPEC , 0 > { CCCTL_01_CCOND_W :: new (self) } # [doc = "Bits 4:6 - Advance Condition. #br# Specifies the condition that generates an advance pulse. 6h-Fh = Reserved"] # [inline (always)] # [must_use] pub fn ccctl_01_acond (& mut self) -> CCCTL_01_ACOND_W < CCCTL_01_SPEC , 4 > { CCCTL_01_ACOND_W :: new (self) } # [doc = "Bits 8:10 - Load Condition. #br# Specifies the condition that generates a load pulse. 4h-Fh = Reserved"] # [inline (always)] # [must_use] pub fn ccctl_01_lcond (& mut self) -> CCCTL_01_LCOND_W <'_, CCCTL_01_SPEC , 8 > { CCCTL_01_LCOND_W :: new (self) } # [doc = "Bits 12:14 - Zero Condition. #br# This field specifies the condition that generates a zero pulse. 4h-Fh = Reserved"] # [inline (always)] # [must_use] pub fn ccctl_01_zcond (& mut self) -> CCCTL_01_ZCOND_W < CCCTL_01_SPEC , 12 > { CCCTL_01_ZCOND_W :: new (self) } # [doc = "Bit 17 - Capture or Compare. #br# Specifies whether the corresponding CC register is used as a capture register or a compare register (never both)."] # [inline (always)] # [must_use] pub fn ccctl_01_coc (& mut self) -> CCCTL_01_COC_W < CCCTL_01_SPEC , 17 > { CCCTL_01_COC_W :: new (self) } # [doc = "Bits 18:20 - Capture and Compare Update Method This field controls how updates to the pipelined capture and compare register are performed (when operating in compare mode, COC=0)."] # [inline (always)] # [must_use] pub fn ccctl_01_ccupd (& mut self) -> CCCTL_01_CCUPD_W < CCCTL_01_SPEC , 18 > { CCCTL_01_CCUPD_W :: new (self) } # [doc = "Bits 22:24 - Selects the source second CCU event."] # [inline (always)] # [must_use] pub fn ccctl_01_cc2selu (& mut self) -> CCCTL_01_CC2SELU_W < CCCTL_01_SPEC , 22 > { CCCTL_01_CC2SELU_W :: new (self) } # [doc = "Bits 26:28 - CCACT shadow register Update Method This field controls how updates to the CCCACT shadow register are performed"] # [inline (always)] # [must_use] pub fn ccctl_01_ccactupd (& mut self) -> CCCTL_01_CCACTUPD_W < CCCTL_01_SPEC , 26 > { CCCTL_01_CCACTUPD_W :: new (self) } # [doc = "Bits 29:31 - Selects the source second CCD event."] # [inline (always)] # [must_use] pub fn ccctl_01_cc2seld (& mut self) -> CCCTL_01_CC2SELD_W < CCCTL_01_SPEC , 29 > { CCCTL_01_CC2SELD_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Capture or Compare Control Registers\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ccctl_01::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ccctl_01::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CCCTL_01_SPEC ; impl crate :: RegisterSpec for CCCTL_01_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`ccctl_01::R`](R) reader structure"] impl crate :: Readable for CCCTL_01_SPEC { } # [doc = "`write(|w| ..)` method takes [`ccctl_01::W`](W) writer structure"] impl crate :: Writable for CCCTL_01_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets CCCTL_01[%s] [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/spi0/clksel.rs:1:6422 [INFO] [stdout] | [INFO] [stdout] 1 | ...ub fn clksel_lfclk_sel (& mut self) -> CLKSEL_LFCLK_SEL_W < CLKSEL_SPEC , 1 > { CLKSEL_LFCLK_SEL_W :: new (self) } # [doc = "Bit 2 - S... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `CLKSEL` reader"] pub type R = crate :: R < CLKSEL_SPEC > ; # [doc = "Register `CLKSEL` writer"] pub type W = crate :: W < CLKSEL_SPEC > ; # [doc = "Field `CLKSEL_LFCLK_SEL` reader - Selects LFCLK as clock source if enabled"] pub type CLKSEL_LFCLK_SEL_R = crate :: BitReader < CLKSEL_LFCLK_SEL_A > ; # [doc = "Selects LFCLK as clock source if enabled\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CLKSEL_LFCLK_SEL_A { # [doc = "0: DISABLE"] CLKSEL_LFCLK_SEL_DISABLE = 0 , # [doc = "1: ENABLE"] CLKSEL_LFCLK_SEL_ENABLE = 1 , } impl From < CLKSEL_LFCLK_SEL_A > for bool { # [inline (always)] fn from (variant : CLKSEL_LFCLK_SEL_A) -> Self { variant as u8 != 0 } } impl CLKSEL_LFCLK_SEL_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CLKSEL_LFCLK_SEL_A { match self . bits { false => CLKSEL_LFCLK_SEL_A :: CLKSEL_LFCLK_SEL_DISABLE , true => CLKSEL_LFCLK_SEL_A :: CLKSEL_LFCLK_SEL_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_clksel_lfclk_sel_disable (& self) -> bool { * self == CLKSEL_LFCLK_SEL_A :: CLKSEL_LFCLK_SEL_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_clksel_lfclk_sel_enable (& self) -> bool { * self == CLKSEL_LFCLK_SEL_A :: CLKSEL_LFCLK_SEL_ENABLE } } # [doc = "Field `CLKSEL_LFCLK_SEL` writer - Selects LFCLK as clock source if enabled"] pub type CLKSEL_LFCLK_SEL_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CLKSEL_LFCLK_SEL_A > ; impl < 'a , REG , const O : u8 > CLKSEL_LFCLK_SEL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn clksel_lfclk_sel_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CLKSEL_LFCLK_SEL_A :: CLKSEL_LFCLK_SEL_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn clksel_lfclk_sel_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CLKSEL_LFCLK_SEL_A :: CLKSEL_LFCLK_SEL_ENABLE) } } # [doc = "Field `CLKSEL_MFCLK_SEL` reader - Selects MFCLK as clock source if enabled"] pub type CLKSEL_MFCLK_SEL_R = crate :: BitReader < CLKSEL_MFCLK_SEL_A > ; # [doc = "Selects MFCLK as clock source if enabled\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CLKSEL_MFCLK_SEL_A { # [doc = "0: DISABLE"] CLKSEL_MFCLK_SEL_DISABLE = 0 , # [doc = "1: ENABLE"] CLKSEL_MFCLK_SEL_ENABLE = 1 , } impl From < CLKSEL_MFCLK_SEL_A > for bool { # [inline (always)] fn from (variant : CLKSEL_MFCLK_SEL_A) -> Self { variant as u8 != 0 } } impl CLKSEL_MFCLK_SEL_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CLKSEL_MFCLK_SEL_A { match self . bits { false => CLKSEL_MFCLK_SEL_A :: CLKSEL_MFCLK_SEL_DISABLE , true => CLKSEL_MFCLK_SEL_A :: CLKSEL_MFCLK_SEL_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_clksel_mfclk_sel_disable (& self) -> bool { * self == CLKSEL_MFCLK_SEL_A :: CLKSEL_MFCLK_SEL_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_clksel_mfclk_sel_enable (& self) -> bool { * self == CLKSEL_MFCLK_SEL_A :: CLKSEL_MFCLK_SEL_ENABLE } } # [doc = "Field `CLKSEL_MFCLK_SEL` writer - Selects MFCLK as clock source if enabled"] pub type CLKSEL_MFCLK_SEL_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CLKSEL_MFCLK_SEL_A > ; impl < 'a , REG , const O : u8 > CLKSEL_MFCLK_SEL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn clksel_mfclk_sel_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CLKSEL_MFCLK_SEL_A :: CLKSEL_MFCLK_SEL_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn clksel_mfclk_sel_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CLKSEL_MFCLK_SEL_A :: CLKSEL_MFCLK_SEL_ENABLE) } } # [doc = "Field `CLKSEL_SYSCLK_SEL` reader - Selects SYSCLK as clock source if enabled"] pub type CLKSEL_SYSCLK_SEL_R = crate :: BitReader < CLKSEL_SYSCLK_SEL_A > ; # [doc = "Selects SYSCLK as clock source if enabled\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CLKSEL_SYSCLK_SEL_A { # [doc = "0: DISABLE"] CLKSEL_SYSCLK_SEL_DISABLE = 0 , # [doc = "1: ENABLE"] CLKSEL_SYSCLK_SEL_ENABLE = 1 , } impl From < CLKSEL_SYSCLK_SEL_A > for bool { # [inline (always)] fn from (variant : CLKSEL_SYSCLK_SEL_A) -> Self { variant as u8 != 0 } } impl CLKSEL_SYSCLK_SEL_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CLKSEL_SYSCLK_SEL_A { match self . bits { false => CLKSEL_SYSCLK_SEL_A :: CLKSEL_SYSCLK_SEL_DISABLE , true => CLKSEL_SYSCLK_SEL_A :: CLKSEL_SYSCLK_SEL_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_clksel_sysclk_sel_disable (& self) -> bool { * self == CLKSEL_SYSCLK_SEL_A :: CLKSEL_SYSCLK_SEL_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_clksel_sysclk_sel_enable (& self) -> bool { * self == CLKSEL_SYSCLK_SEL_A :: CLKSEL_SYSCLK_SEL_ENABLE } } # [doc = "Field `CLKSEL_SYSCLK_SEL` writer - Selects SYSCLK as clock source if enabled"] pub type CLKSEL_SYSCLK_SEL_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CLKSEL_SYSCLK_SEL_A > ; impl < 'a , REG , const O : u8 > CLKSEL_SYSCLK_SEL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn clksel_sysclk_sel_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CLKSEL_SYSCLK_SEL_A :: CLKSEL_SYSCLK_SEL_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn clksel_sysclk_sel_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CLKSEL_SYSCLK_SEL_A :: CLKSEL_SYSCLK_SEL_ENABLE) } } impl R { # [doc = "Bit 1 - Selects LFCLK as clock source if enabled"] # [inline (always)] pub fn clksel_lfclk_sel (& self) -> CLKSEL_LFCLK_SEL_R { CLKSEL_LFCLK_SEL_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - Selects MFCLK as clock source if enabled"] # [inline (always)] pub fn clksel_mfclk_sel (& self) -> CLKSEL_MFCLK_SEL_R { CLKSEL_MFCLK_SEL_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - Selects SYSCLK as clock source if enabled"] # [inline (always)] pub fn clksel_sysclk_sel (& self) -> CLKSEL_SYSCLK_SEL_R { CLKSEL_SYSCLK_SEL_R :: new (((self . bits >> 3) & 1) != 0) } } impl W { # [doc = "Bit 1 - Selects LFCLK as clock source if enabled"] # [inline (always)] # [must_use] pub fn clksel_lfclk_sel (& mut self) -> CLKSEL_LFCLK_SEL_W <'_, CLKSEL_SPEC , 1 > { CLKSEL_LFCLK_SEL_W :: new (self) } # [doc = "Bit 2 - Selects MFCLK as clock source if enabled"] # [inline (always)] # [must_use] pub fn clksel_mfclk_sel (& mut self) -> CLKSEL_MFCLK_SEL_W < CLKSEL_SPEC , 2 > { CLKSEL_MFCLK_SEL_W :: new (self) } # [doc = "Bit 3 - Selects SYSCLK as clock source if enabled"] # [inline (always)] # [must_use] pub fn clksel_sysclk_sel (& mut self) -> CLKSEL_SYSCLK_SEL_W < CLKSEL_SPEC , 3 > { CLKSEL_SYSCLK_SEL_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Clock Select for Ultra Low Power peripherals\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clksel::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clksel::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CLKSEL_SPEC ; impl crate :: RegisterSpec for CLKSEL_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`clksel::R`](R) reader structure"] impl crate :: Readable for CLKSEL_SPEC { } # [doc = "`write(|w| ..)` method takes [`clksel::W`](W) writer structure"] impl crate :: Writable for CLKSEL_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets CLKSEL to value 0"] impl crate :: Resettable for CLKSEL_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/i2c1/int_event1_iset.rs:1:5345 [INFO] [stdout] | [INFO] [stdout] 1 | ...t_mrxfifotrg (& mut self) -> INT_EVENT1_ISET_MRXFIFOTRG_W < INT_EVENT1_ISET_SPEC , 0 > { INT_EVENT1_ISET_MRXFIFOTRG_W :: new (self) } ... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `INT_EVENT1_ISET` writer"] pub type W = crate :: W < INT_EVENT1_ISET_SPEC > ; # [doc = "Master Receive FIFO Trigger Trigger when RX FIFO contains &gt;= defined bytes\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT1_ISET_MRXFIFOTRG_AW { # [doc = "0: NO_EFFECT"] INT_EVENT1_ISET_MRXFIFOTRG_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT1_ISET_MRXFIFOTRG_SET = 1 , } impl From < INT_EVENT1_ISET_MRXFIFOTRG_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT1_ISET_MRXFIFOTRG_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT1_ISET_MRXFIFOTRG` writer - Master Receive FIFO Trigger Trigger when RX FIFO contains &gt;= defined bytes"] pub type INT_EVENT1_ISET_MRXFIFOTRG_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT1_ISET_MRXFIFOTRG_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT1_ISET_MRXFIFOTRG_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event1_iset_mrxfifotrg_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_ISET_MRXFIFOTRG_AW :: INT_EVENT1_ISET_MRXFIFOTRG_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event1_iset_mrxfifotrg_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_ISET_MRXFIFOTRG_AW :: INT_EVENT1_ISET_MRXFIFOTRG_SET) } } # [doc = "Master Transmit FIFO Trigger Trigger when Transmit FIFO contains &lt;= defined bytes\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT1_ISET_MTXFIFOTRG_AW { # [doc = "0: NO_EFFECT"] INT_EVENT1_ISET_MTXFIFOTRG_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT1_ISET_MTXFIFOTRG_SET = 1 , } impl From < INT_EVENT1_ISET_MTXFIFOTRG_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT1_ISET_MTXFIFOTRG_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT1_ISET_MTXFIFOTRG` writer - Master Transmit FIFO Trigger Trigger when Transmit FIFO contains &lt;= defined bytes"] pub type INT_EVENT1_ISET_MTXFIFOTRG_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT1_ISET_MTXFIFOTRG_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT1_ISET_MTXFIFOTRG_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event1_iset_mtxfifotrg_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_ISET_MTXFIFOTRG_AW :: INT_EVENT1_ISET_MTXFIFOTRG_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event1_iset_mtxfifotrg_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_ISET_MTXFIFOTRG_AW :: INT_EVENT1_ISET_MTXFIFOTRG_SET) } } # [doc = "Slave Receive FIFO Trigger\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT1_ISET_SRXFIFOTRG_AW { # [doc = "0: NO_EFFECT"] INT_EVENT1_ISET_SRXFIFOTRG_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT1_ISET_SRXFIFOTRG_SET = 1 , } impl From < INT_EVENT1_ISET_SRXFIFOTRG_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT1_ISET_SRXFIFOTRG_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT1_ISET_SRXFIFOTRG` writer - Slave Receive FIFO Trigger"] pub type INT_EVENT1_ISET_SRXFIFOTRG_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT1_ISET_SRXFIFOTRG_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT1_ISET_SRXFIFOTRG_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event1_iset_srxfifotrg_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_ISET_SRXFIFOTRG_AW :: INT_EVENT1_ISET_SRXFIFOTRG_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event1_iset_srxfifotrg_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_ISET_SRXFIFOTRG_AW :: INT_EVENT1_ISET_SRXFIFOTRG_SET) } } # [doc = "Slave Transmit FIFO Trigger\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT1_ISET_STXFIFOTRG_AW { # [doc = "0: NO_EFFECT"] INT_EVENT1_ISET_STXFIFOTRG_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT1_ISET_STXFIFOTRG_SET = 1 , } impl From < INT_EVENT1_ISET_STXFIFOTRG_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT1_ISET_STXFIFOTRG_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT1_ISET_STXFIFOTRG` writer - Slave Transmit FIFO Trigger"] pub type INT_EVENT1_ISET_STXFIFOTRG_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT1_ISET_STXFIFOTRG_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT1_ISET_STXFIFOTRG_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event1_iset_stxfifotrg_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_ISET_STXFIFOTRG_AW :: INT_EVENT1_ISET_STXFIFOTRG_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event1_iset_stxfifotrg_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_ISET_STXFIFOTRG_AW :: INT_EVENT1_ISET_STXFIFOTRG_SET) } } impl W { # [doc = "Bit 0 - Master Receive FIFO Trigger Trigger when RX FIFO contains &gt;= defined bytes"] # [inline (always)] # [must_use] pub fn int_event1_iset_mrxfifotrg (& mut self) -> INT_EVENT1_ISET_MRXFIFOTRG_W <'_, INT_EVENT1_ISET_SPEC , 0 > { INT_EVENT1_ISET_MRXFIFOTRG_W :: new (self) } # [doc = "Bit 1 - Master Transmit FIFO Trigger Trigger when Transmit FIFO contains &lt;= defined bytes"] # [inline (always)] # [must_use] pub fn int_event1_iset_mtxfifotrg (& mut self) -> INT_EVENT1_ISET_MTXFIFOTRG_W < INT_EVENT1_ISET_SPEC , 1 > { INT_EVENT1_ISET_MTXFIFOTRG_W :: new (self) } # [doc = "Bit 2 - Slave Receive FIFO Trigger"] # [inline (always)] # [must_use] pub fn int_event1_iset_srxfifotrg (& mut self) -> INT_EVENT1_ISET_SRXFIFOTRG_W < INT_EVENT1_ISET_SPEC , 2 > { INT_EVENT1_ISET_SRXFIFOTRG_W :: new (self) } # [doc = "Bit 3 - Slave Transmit FIFO Trigger"] # [inline (always)] # [must_use] pub fn int_event1_iset_stxfifotrg (& mut self) -> INT_EVENT1_ISET_STXFIFOTRG_W < INT_EVENT1_ISET_SPEC , 3 > { INT_EVENT1_ISET_STXFIFOTRG_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Interrupt set\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_event1_iset::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct INT_EVENT1_ISET_SPEC ; impl crate :: RegisterSpec for INT_EVENT1_ISET_SPEC { type Ux = u32 ; } # [doc = "`write(|w| ..)` method takes [`int_event1_iset::W`](W) writer structure"] impl crate :: Writable for INT_EVENT1_ISET_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets INT_EVENT1_ISET to value 0"] impl crate :: Resettable for INT_EVENT1_ISET_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/opa1/cfgbase.rs:1:4840 [INFO] [stdout] | [INFO] [stdout] 1 | ..._use] pub fn cfgbase_gbw (& mut self) -> CFGBASE_GBW_W < CFGBASE_SPEC , 0 > { CFGBASE_GBW_W :: new (self) } # [doc = "Bit 2 - Rail-to-... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `CFGBASE` reader"] pub type R = crate :: R < CFGBASE_SPEC > ; # [doc = "Register `CFGBASE` writer"] pub type W = crate :: W < CFGBASE_SPEC > ; # [doc = "Field `CFGBASE_GBW` reader - Select gain bandwidth which affects current as well the gain bandwidth. The lower gain bandwidth has lower current. See device specific datasheet for values. Can only be modified when STAT.BUSY=0."] pub type CFGBASE_GBW_R = crate :: BitReader < CFGBASE_GBW_A > ; # [doc = "Select gain bandwidth which affects current as well the gain bandwidth. The lower gain bandwidth has lower current. See device specific datasheet for values. Can only be modified when STAT.BUSY=0.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CFGBASE_GBW_A { # [doc = "0: LOWGAIN"] CFGBASE_GBW_LOWGAIN = 0 , # [doc = "1: HIGHGAIN"] CFGBASE_GBW_HIGHGAIN = 1 , } impl From < CFGBASE_GBW_A > for bool { # [inline (always)] fn from (variant : CFGBASE_GBW_A) -> Self { variant as u8 != 0 } } impl CFGBASE_GBW_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CFGBASE_GBW_A { match self . bits { false => CFGBASE_GBW_A :: CFGBASE_GBW_LOWGAIN , true => CFGBASE_GBW_A :: CFGBASE_GBW_HIGHGAIN , } } # [doc = "LOWGAIN"] # [inline (always)] pub fn is_cfgbase_gbw_lowgain (& self) -> bool { * self == CFGBASE_GBW_A :: CFGBASE_GBW_LOWGAIN } # [doc = "HIGHGAIN"] # [inline (always)] pub fn is_cfgbase_gbw_highgain (& self) -> bool { * self == CFGBASE_GBW_A :: CFGBASE_GBW_HIGHGAIN } } # [doc = "Field `CFGBASE_GBW` writer - Select gain bandwidth which affects current as well the gain bandwidth. The lower gain bandwidth has lower current. See device specific datasheet for values. Can only be modified when STAT.BUSY=0."] pub type CFGBASE_GBW_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CFGBASE_GBW_A > ; impl < 'a , REG , const O : u8 > CFGBASE_GBW_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "LOWGAIN"] # [inline (always)] pub fn cfgbase_gbw_lowgain (self) -> & 'a mut crate :: W < REG > { self . variant (CFGBASE_GBW_A :: CFGBASE_GBW_LOWGAIN) } # [doc = "HIGHGAIN"] # [inline (always)] pub fn cfgbase_gbw_highgain (self) -> & 'a mut crate :: W < REG > { self . variant (CFGBASE_GBW_A :: CFGBASE_GBW_HIGHGAIN) } } # [doc = "Field `CFGBASE_RRI` reader - Rail-to-rail input enable. Can only be modified when STAT.BUSY=0"] pub type CFGBASE_RRI_R = crate :: BitReader < CFGBASE_RRI_A > ; # [doc = "Rail-to-rail input enable. Can only be modified when STAT.BUSY=0\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CFGBASE_RRI_A { # [doc = "0: OFF"] CFGBASE_RRI_OFF = 0 , # [doc = "1: ON"] CFGBASE_RRI_ON = 1 , } impl From < CFGBASE_RRI_A > for bool { # [inline (always)] fn from (variant : CFGBASE_RRI_A) -> Self { variant as u8 != 0 } } impl CFGBASE_RRI_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CFGBASE_RRI_A { match self . bits { false => CFGBASE_RRI_A :: CFGBASE_RRI_OFF , true => CFGBASE_RRI_A :: CFGBASE_RRI_ON , } } # [doc = "OFF"] # [inline (always)] pub fn is_cfgbase_rri_off (& self) -> bool { * self == CFGBASE_RRI_A :: CFGBASE_RRI_OFF } # [doc = "ON"] # [inline (always)] pub fn is_cfgbase_rri_on (& self) -> bool { * self == CFGBASE_RRI_A :: CFGBASE_RRI_ON } } # [doc = "Field `CFGBASE_RRI` writer - Rail-to-rail input enable. Can only be modified when STAT.BUSY=0"] pub type CFGBASE_RRI_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CFGBASE_RRI_A > ; impl < 'a , REG , const O : u8 > CFGBASE_RRI_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "OFF"] # [inline (always)] pub fn cfgbase_rri_off (self) -> & 'a mut crate :: W < REG > { self . variant (CFGBASE_RRI_A :: CFGBASE_RRI_OFF) } # [doc = "ON"] # [inline (always)] pub fn cfgbase_rri_on (self) -> & 'a mut crate :: W < REG > { self . variant (CFGBASE_RRI_A :: CFGBASE_RRI_ON) } } impl R { # [doc = "Bit 0 - Select gain bandwidth which affects current as well the gain bandwidth. The lower gain bandwidth has lower current. See device specific datasheet for values. Can only be modified when STAT.BUSY=0."] # [inline (always)] pub fn cfgbase_gbw (& self) -> CFGBASE_GBW_R { CFGBASE_GBW_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 2 - Rail-to-rail input enable. Can only be modified when STAT.BUSY=0"] # [inline (always)] pub fn cfgbase_rri (& self) -> CFGBASE_RRI_R { CFGBASE_RRI_R :: new (((self . bits >> 2) & 1) != 0) } } impl W { # [doc = "Bit 0 - Select gain bandwidth which affects current as well the gain bandwidth. The lower gain bandwidth has lower current. See device specific datasheet for values. Can only be modified when STAT.BUSY=0."] # [inline (always)] # [must_use] pub fn cfgbase_gbw (& mut self) -> CFGBASE_GBW_W <'_, CFGBASE_SPEC , 0 > { CFGBASE_GBW_W :: new (self) } # [doc = "Bit 2 - Rail-to-rail input enable. Can only be modified when STAT.BUSY=0"] # [inline (always)] # [must_use] pub fn cfgbase_rri (& mut self) -> CFGBASE_RRI_W < CFGBASE_SPEC , 2 > { CFGBASE_RRI_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Configuration Base Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cfgbase::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cfgbase::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CFGBASE_SPEC ; impl crate :: RegisterSpec for CFGBASE_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`cfgbase::R`](R) reader structure"] impl crate :: Readable for CFGBASE_SPEC { } # [doc = "`write(|w| ..)` method takes [`cfgbase::W`](W) writer structure"] impl crate :: Writable for CFGBASE_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets CFGBASE to value 0"] impl crate :: Resettable for CFGBASE_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/opa0/pwren.rs:1:3131 [INFO] [stdout] | [INFO] [stdout] 1 | ...ust_use] pub fn pwren_key (& mut self) -> PWREN_KEY_W < PWREN_SPEC , 24 > { PWREN_KEY_W :: new (self) } # [doc = r" Writes raw bits to... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `PWREN` reader"] pub type R = crate :: R < PWREN_SPEC > ; # [doc = "Register `PWREN` writer"] pub type W = crate :: W < PWREN_SPEC > ; # [doc = "Field `PWREN_ENABLE` reader - Enable the power"] pub type PWREN_ENABLE_R = crate :: BitReader < PWREN_ENABLE_A > ; # [doc = "Enable the power\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum PWREN_ENABLE_A { # [doc = "0: DISABLE"] PWREN_ENABLE_DISABLE = 0 , # [doc = "1: ENABLE"] PWREN_ENABLE_ENABLE = 1 , } impl From < PWREN_ENABLE_A > for bool { # [inline (always)] fn from (variant : PWREN_ENABLE_A) -> Self { variant as u8 != 0 } } impl PWREN_ENABLE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> PWREN_ENABLE_A { match self . bits { false => PWREN_ENABLE_A :: PWREN_ENABLE_DISABLE , true => PWREN_ENABLE_A :: PWREN_ENABLE_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_pwren_enable_disable (& self) -> bool { * self == PWREN_ENABLE_A :: PWREN_ENABLE_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_pwren_enable_enable (& self) -> bool { * self == PWREN_ENABLE_A :: PWREN_ENABLE_ENABLE } } # [doc = "Field `PWREN_ENABLE` writer - Enable the power"] pub type PWREN_ENABLE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , PWREN_ENABLE_A > ; impl < 'a , REG , const O : u8 > PWREN_ENABLE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn pwren_enable_disable (self) -> & 'a mut crate :: W < REG > { self . variant (PWREN_ENABLE_A :: PWREN_ENABLE_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn pwren_enable_enable (self) -> & 'a mut crate :: W < REG > { self . variant (PWREN_ENABLE_A :: PWREN_ENABLE_ENABLE) } } # [doc = "KEY to allow Power State Change\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum PWREN_KEY_AW { # [doc = "38: _TO_UNLOCK_W_"] PWREN_KEY_UNLOCK_W = 38 , } impl From < PWREN_KEY_AW > for u8 { # [inline (always)] fn from (variant : PWREN_KEY_AW) -> Self { variant as _ } } impl crate :: FieldSpec for PWREN_KEY_AW { type Ux = u8 ; } # [doc = "Field `PWREN_KEY` writer - KEY to allow Power State Change"] pub type PWREN_KEY_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 8 , O , PWREN_KEY_AW > ; impl < 'a , REG , const O : u8 > PWREN_KEY_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "_TO_UNLOCK_W_"] # [inline (always)] pub fn pwren_key_unlock_w (self) -> & 'a mut crate :: W < REG > { self . variant (PWREN_KEY_AW :: PWREN_KEY_UNLOCK_W) } } impl R { # [doc = "Bit 0 - Enable the power"] # [inline (always)] pub fn pwren_enable (& self) -> PWREN_ENABLE_R { PWREN_ENABLE_R :: new ((self . bits & 1) != 0) } } impl W { # [doc = "Bit 0 - Enable the power"] # [inline (always)] # [must_use] pub fn pwren_enable (& mut self) -> PWREN_ENABLE_W < PWREN_SPEC , 0 > { PWREN_ENABLE_W :: new (self) } # [doc = "Bits 24:31 - KEY to allow Power State Change"] # [inline (always)] # [must_use] pub fn pwren_key (& mut self) -> PWREN_KEY_W <'_, PWREN_SPEC , 24 > { PWREN_KEY_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Power enable\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pwren::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pwren::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PWREN_SPEC ; impl crate :: RegisterSpec for PWREN_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`pwren::R`](R) reader structure"] impl crate :: Readable for PWREN_SPEC { } # [doc = "`write(|w| ..)` method takes [`pwren::W`](W) writer structure"] impl crate :: Writable for PWREN_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets PWREN to value 0"] impl crate :: Resettable for PWREN_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/i2c0/mtxdata.rs:1:1000 [INFO] [stdout] | [INFO] [stdout] 1 | ...e] pub fn mtxdata_value (& mut self) -> MTXDATA_VALUE_W < MTXDATA_SPEC , 0 > { MTXDATA_VALUE_W :: new (self) } # [doc = r" Writes raw ... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `MTXDATA` reader"] pub type R = crate :: R < MTXDATA_SPEC > ; # [doc = "Register `MTXDATA` writer"] pub type W = crate :: W < MTXDATA_SPEC > ; # [doc = "Field `MTXDATA_VALUE` reader - Transmit Data This byte contains the data to be transferred during the next transaction."] pub type MTXDATA_VALUE_R = crate :: FieldReader ; # [doc = "Field `MTXDATA_VALUE` writer - Transmit Data This byte contains the data to be transferred during the next transaction."] pub type MTXDATA_VALUE_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 8 , O > ; impl R { # [doc = "Bits 0:7 - Transmit Data This byte contains the data to be transferred during the next transaction."] # [inline (always)] pub fn mtxdata_value (& self) -> MTXDATA_VALUE_R { MTXDATA_VALUE_R :: new ((self . bits & 0xff) as u8) } } impl W { # [doc = "Bits 0:7 - Transmit Data This byte contains the data to be transferred during the next transaction."] # [inline (always)] # [must_use] pub fn mtxdata_value (& mut self) -> MTXDATA_VALUE_W <'_, MTXDATA_SPEC , 0 > { MTXDATA_VALUE_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "I2C Master TXData\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mtxdata::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mtxdata::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct MTXDATA_SPEC ; impl crate :: RegisterSpec for MTXDATA_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`mtxdata::R`](R) reader structure"] impl crate :: Readable for MTXDATA_SPEC { } # [doc = "`write(|w| ..)` method takes [`mtxdata::W`](W) writer structure"] impl crate :: Writable for MTXDATA_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets MTXDATA to value 0"] impl crate :: Resettable for MTXDATA_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/sysctl/iset.rs:1:2264 [INFO] [stdout] | [INFO] [stdout] 1 | ...e] pub fn iset_lfoscgood (& mut self) -> ISET_LFOSCGOOD_W < ISET_SPEC , 0 > { ISET_LFOSCGOOD_W :: new (self) } # [doc = "Bit 1 - Analo... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `ISET` writer"] pub type W = crate :: W < ISET_SPEC > ; # [doc = "Set the LFOSCGOOD interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum ISET_LFOSCGOOD_AW { # [doc = "0: NO_EFFECT"] ISET_LFOSCGOOD_NO_EFFECT = 0 , # [doc = "1: SET"] ISET_LFOSCGOOD_SET = 1 , } impl From < ISET_LFOSCGOOD_AW > for bool { # [inline (always)] fn from (variant : ISET_LFOSCGOOD_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `ISET_LFOSCGOOD` writer - Set the LFOSCGOOD interrupt."] pub type ISET_LFOSCGOOD_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , ISET_LFOSCGOOD_AW > ; impl < 'a , REG , const O : u8 > ISET_LFOSCGOOD_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn iset_lfoscgood_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (ISET_LFOSCGOOD_AW :: ISET_LFOSCGOOD_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn iset_lfoscgood_set (self) -> & 'a mut crate :: W < REG > { self . variant (ISET_LFOSCGOOD_AW :: ISET_LFOSCGOOD_SET) } } # [doc = "Analog Clocking Consistency Error\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum ISET_ANACLKERR_AW { # [doc = "0: NO_EFFECT"] ISET_ANACLKERR_NO_EFFECT = 0 , # [doc = "1: SET"] ISET_ANACLKERR_SET = 1 , } impl From < ISET_ANACLKERR_AW > for bool { # [inline (always)] fn from (variant : ISET_ANACLKERR_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `ISET_ANACLKERR` writer - Analog Clocking Consistency Error"] pub type ISET_ANACLKERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , ISET_ANACLKERR_AW > ; impl < 'a , REG , const O : u8 > ISET_ANACLKERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn iset_anaclkerr_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (ISET_ANACLKERR_AW :: ISET_ANACLKERR_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn iset_anaclkerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (ISET_ANACLKERR_AW :: ISET_ANACLKERR_SET) } } impl W { # [doc = "Bit 0 - Set the LFOSCGOOD interrupt."] # [inline (always)] # [must_use] pub fn iset_lfoscgood (& mut self) -> ISET_LFOSCGOOD_W <'_, ISET_SPEC , 0 > { ISET_LFOSCGOOD_W :: new (self) } # [doc = "Bit 1 - Analog Clocking Consistency Error"] # [inline (always)] # [must_use] pub fn iset_anaclkerr (& mut self) -> ISET_ANACLKERR_W < ISET_SPEC , 1 > { ISET_ANACLKERR_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "SYSCTL interrupt set\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`iset::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct ISET_SPEC ; impl crate :: RegisterSpec for ISET_SPEC { type Ux = u32 ; } # [doc = "`write(|w| ..)` method takes [`iset::W`](W) writer structure"] impl crate :: Writable for ISET_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets ISET to value 0"] impl crate :: Resettable for ISET_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/i2c1/mfifoctl.rs:1:13018 [INFO] [stdout] | [INFO] [stdout] 1 | ...ub fn mfifoctl_rxtrig (& mut self) -> MFIFOCTL_RXTRIG_W < MFIFOCTL_SPEC , 8 > { MFIFOCTL_RXTRIG_W :: new (self) } # [doc = "Bit 15 - R... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `MFIFOCTL` reader"] pub type R = crate :: R < MFIFOCTL_SPEC > ; # [doc = "Register `MFIFOCTL` writer"] pub type W = crate :: W < MFIFOCTL_SPEC > ; # [doc = "Field `MFIFOCTL_TXTRIG` reader - TX FIFO Trigger Indicates at what fill level in the TX FIFO a trigger will be generated."] pub type MFIFOCTL_TXTRIG_R = crate :: FieldReader < MFIFOCTL_TXTRIG_A > ; # [doc = "TX FIFO Trigger Indicates at what fill level in the TX FIFO a trigger will be generated.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum MFIFOCTL_TXTRIG_A { # [doc = "4: LEVEL_4"] MFIFOCTL_TXTRIG_LEVEL_4 = 4 , # [doc = "5: LEVEL_5"] MFIFOCTL_TXTRIG_LEVEL_5 = 5 , # [doc = "6: LEVEL_6"] MFIFOCTL_TXTRIG_LEVEL_6 = 6 , # [doc = "7: LEVEL_7"] MFIFOCTL_TXTRIG_LEVEL_7 = 7 , } impl From < MFIFOCTL_TXTRIG_A > for u8 { # [inline (always)] fn from (variant : MFIFOCTL_TXTRIG_A) -> Self { variant as _ } } impl crate :: FieldSpec for MFIFOCTL_TXTRIG_A { type Ux = u8 ; } impl MFIFOCTL_TXTRIG_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < MFIFOCTL_TXTRIG_A > { match self . bits { 4 => Some (MFIFOCTL_TXTRIG_A :: MFIFOCTL_TXTRIG_LEVEL_4) , 5 => Some (MFIFOCTL_TXTRIG_A :: MFIFOCTL_TXTRIG_LEVEL_5) , 6 => Some (MFIFOCTL_TXTRIG_A :: MFIFOCTL_TXTRIG_LEVEL_6) , 7 => Some (MFIFOCTL_TXTRIG_A :: MFIFOCTL_TXTRIG_LEVEL_7) , _ => None , } } # [doc = "LEVEL_4"] # [inline (always)] pub fn is_mfifoctl_txtrig_level_4 (& self) -> bool { * self == MFIFOCTL_TXTRIG_A :: MFIFOCTL_TXTRIG_LEVEL_4 } # [doc = "LEVEL_5"] # [inline (always)] pub fn is_mfifoctl_txtrig_level_5 (& self) -> bool { * self == MFIFOCTL_TXTRIG_A :: MFIFOCTL_TXTRIG_LEVEL_5 } # [doc = "LEVEL_6"] # [inline (always)] pub fn is_mfifoctl_txtrig_level_6 (& self) -> bool { * self == MFIFOCTL_TXTRIG_A :: MFIFOCTL_TXTRIG_LEVEL_6 } # [doc = "LEVEL_7"] # [inline (always)] pub fn is_mfifoctl_txtrig_level_7 (& self) -> bool { * self == MFIFOCTL_TXTRIG_A :: MFIFOCTL_TXTRIG_LEVEL_7 } } # [doc = "Field `MFIFOCTL_TXTRIG` writer - TX FIFO Trigger Indicates at what fill level in the TX FIFO a trigger will be generated."] pub type MFIFOCTL_TXTRIG_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 3 , O , MFIFOCTL_TXTRIG_A > ; impl < 'a , REG , const O : u8 > MFIFOCTL_TXTRIG_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "LEVEL_4"] # [inline (always)] pub fn mfifoctl_txtrig_level_4 (self) -> & 'a mut crate :: W < REG > { self . variant (MFIFOCTL_TXTRIG_A :: MFIFOCTL_TXTRIG_LEVEL_4) } # [doc = "LEVEL_5"] # [inline (always)] pub fn mfifoctl_txtrig_level_5 (self) -> & 'a mut crate :: W < REG > { self . variant (MFIFOCTL_TXTRIG_A :: MFIFOCTL_TXTRIG_LEVEL_5) } # [doc = "LEVEL_6"] # [inline (always)] pub fn mfifoctl_txtrig_level_6 (self) -> & 'a mut crate :: W < REG > { self . variant (MFIFOCTL_TXTRIG_A :: MFIFOCTL_TXTRIG_LEVEL_6) } # [doc = "LEVEL_7"] # [inline (always)] pub fn mfifoctl_txtrig_level_7 (self) -> & 'a mut crate :: W < REG > { self . variant (MFIFOCTL_TXTRIG_A :: MFIFOCTL_TXTRIG_LEVEL_7) } } # [doc = "Field `MFIFOCTL_TXFLUSH` reader - TX FIFO Flush Setting this bit will Flush the TX FIFO. Before reseting this bit to stop Flush the TXFIFOCNT should be checked to be 8 and indicating that the Flush has completed."] pub type MFIFOCTL_TXFLUSH_R = crate :: BitReader < MFIFOCTL_TXFLUSH_A > ; # [doc = "TX FIFO Flush Setting this bit will Flush the TX FIFO. Before reseting this bit to stop Flush the TXFIFOCNT should be checked to be 8 and indicating that the Flush has completed.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum MFIFOCTL_TXFLUSH_A { # [doc = "0: NOFLUSH"] MFIFOCTL_TXFLUSH_NOFLUSH = 0 , # [doc = "1: FLUSH"] MFIFOCTL_TXFLUSH_FLUSH = 1 , } impl From < MFIFOCTL_TXFLUSH_A > for bool { # [inline (always)] fn from (variant : MFIFOCTL_TXFLUSH_A) -> Self { variant as u8 != 0 } } impl MFIFOCTL_TXFLUSH_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> MFIFOCTL_TXFLUSH_A { match self . bits { false => MFIFOCTL_TXFLUSH_A :: MFIFOCTL_TXFLUSH_NOFLUSH , true => MFIFOCTL_TXFLUSH_A :: MFIFOCTL_TXFLUSH_FLUSH , } } # [doc = "NOFLUSH"] # [inline (always)] pub fn is_mfifoctl_txflush_noflush (& self) -> bool { * self == MFIFOCTL_TXFLUSH_A :: MFIFOCTL_TXFLUSH_NOFLUSH } # [doc = "FLUSH"] # [inline (always)] pub fn is_mfifoctl_txflush_flush (& self) -> bool { * self == MFIFOCTL_TXFLUSH_A :: MFIFOCTL_TXFLUSH_FLUSH } } # [doc = "Field `MFIFOCTL_TXFLUSH` writer - TX FIFO Flush Setting this bit will Flush the TX FIFO. Before reseting this bit to stop Flush the TXFIFOCNT should be checked to be 8 and indicating that the Flush has completed."] pub type MFIFOCTL_TXFLUSH_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , MFIFOCTL_TXFLUSH_A > ; impl < 'a , REG , const O : u8 > MFIFOCTL_TXFLUSH_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NOFLUSH"] # [inline (always)] pub fn mfifoctl_txflush_noflush (self) -> & 'a mut crate :: W < REG > { self . variant (MFIFOCTL_TXFLUSH_A :: MFIFOCTL_TXFLUSH_NOFLUSH) } # [doc = "FLUSH"] # [inline (always)] pub fn mfifoctl_txflush_flush (self) -> & 'a mut crate :: W < REG > { self . variant (MFIFOCTL_TXFLUSH_A :: MFIFOCTL_TXFLUSH_FLUSH) } } # [doc = "Field `MFIFOCTL_RXTRIG` reader - RX FIFO Trigger Indicates at what fill level in the RX FIFO a trigger will be generated. Note: Programming RXTRIG to 0x0 has no effect since no data is present to transfer out of RX FIFO."] pub type MFIFOCTL_RXTRIG_R = crate :: FieldReader < MFIFOCTL_RXTRIG_A > ; # [doc = "RX FIFO Trigger Indicates at what fill level in the RX FIFO a trigger will be generated. Note: Programming RXTRIG to 0x0 has no effect since no data is present to transfer out of RX FIFO.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum MFIFOCTL_RXTRIG_A { # [doc = "4: LEVEL_5"] MFIFOCTL_RXTRIG_LEVEL_5 = 4 , # [doc = "5: LEVEL_6"] MFIFOCTL_RXTRIG_LEVEL_6 = 5 , # [doc = "6: LEVEL_7"] MFIFOCTL_RXTRIG_LEVEL_7 = 6 , # [doc = "7: LEVEL_8"] MFIFOCTL_RXTRIG_LEVEL_8 = 7 , } impl From < MFIFOCTL_RXTRIG_A > for u8 { # [inline (always)] fn from (variant : MFIFOCTL_RXTRIG_A) -> Self { variant as _ } } impl crate :: FieldSpec for MFIFOCTL_RXTRIG_A { type Ux = u8 ; } impl MFIFOCTL_RXTRIG_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < MFIFOCTL_RXTRIG_A > { match self . bits { 4 => Some (MFIFOCTL_RXTRIG_A :: MFIFOCTL_RXTRIG_LEVEL_5) , 5 => Some (MFIFOCTL_RXTRIG_A :: MFIFOCTL_RXTRIG_LEVEL_6) , 6 => Some (MFIFOCTL_RXTRIG_A :: MFIFOCTL_RXTRIG_LEVEL_7) , 7 => Some (MFIFOCTL_RXTRIG_A :: MFIFOCTL_RXTRIG_LEVEL_8) , _ => None , } } # [doc = "LEVEL_5"] # [inline (always)] pub fn is_mfifoctl_rxtrig_level_5 (& self) -> bool { * self == MFIFOCTL_RXTRIG_A :: MFIFOCTL_RXTRIG_LEVEL_5 } # [doc = "LEVEL_6"] # [inline (always)] pub fn is_mfifoctl_rxtrig_level_6 (& self) -> bool { * self == MFIFOCTL_RXTRIG_A :: MFIFOCTL_RXTRIG_LEVEL_6 } # [doc = "LEVEL_7"] # [inline (always)] pub fn is_mfifoctl_rxtrig_level_7 (& self) -> bool { * self == MFIFOCTL_RXTRIG_A :: MFIFOCTL_RXTRIG_LEVEL_7 } # [doc = "LEVEL_8"] # [inline (always)] pub fn is_mfifoctl_rxtrig_level_8 (& self) -> bool { * self == MFIFOCTL_RXTRIG_A :: MFIFOCTL_RXTRIG_LEVEL_8 } } # [doc = "Field `MFIFOCTL_RXTRIG` writer - RX FIFO Trigger Indicates at what fill level in the RX FIFO a trigger will be generated. Note: Programming RXTRIG to 0x0 has no effect since no data is present to transfer out of RX FIFO."] pub type MFIFOCTL_RXTRIG_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 3 , O , MFIFOCTL_RXTRIG_A > ; impl < 'a , REG , const O : u8 > MFIFOCTL_RXTRIG_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "LEVEL_5"] # [inline (always)] pub fn mfifoctl_rxtrig_level_5 (self) -> & 'a mut crate :: W < REG > { self . variant (MFIFOCTL_RXTRIG_A :: MFIFOCTL_RXTRIG_LEVEL_5) } # [doc = "LEVEL_6"] # [inline (always)] pub fn mfifoctl_rxtrig_level_6 (self) -> & 'a mut crate :: W < REG > { self . variant (MFIFOCTL_RXTRIG_A :: MFIFOCTL_RXTRIG_LEVEL_6) } # [doc = "LEVEL_7"] # [inline (always)] pub fn mfifoctl_rxtrig_level_7 (self) -> & 'a mut crate :: W < REG > { self . variant (MFIFOCTL_RXTRIG_A :: MFIFOCTL_RXTRIG_LEVEL_7) } # [doc = "LEVEL_8"] # [inline (always)] pub fn mfifoctl_rxtrig_level_8 (self) -> & 'a mut crate :: W < REG > { self . variant (MFIFOCTL_RXTRIG_A :: MFIFOCTL_RXTRIG_LEVEL_8) } } # [doc = "Field `MFIFOCTL_RXFLUSH` reader - RX FIFO Flush Setting this bit will Flush the RX FIFO. Before reseting this bit to stop Flush the RXFIFOCNT should be checked to be 0 and indicating that the Flush has completed."] pub type MFIFOCTL_RXFLUSH_R = crate :: BitReader < MFIFOCTL_RXFLUSH_A > ; # [doc = "RX FIFO Flush Setting this bit will Flush the RX FIFO. Before reseting this bit to stop Flush the RXFIFOCNT should be checked to be 0 and indicating that the Flush has completed.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum MFIFOCTL_RXFLUSH_A { # [doc = "0: NOFLUSH"] MFIFOCTL_RXFLUSH_NOFLUSH = 0 , # [doc = "1: FLUSH"] MFIFOCTL_RXFLUSH_FLUSH = 1 , } impl From < MFIFOCTL_RXFLUSH_A > for bool { # [inline (always)] fn from (variant : MFIFOCTL_RXFLUSH_A) -> Self { variant as u8 != 0 } } impl MFIFOCTL_RXFLUSH_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> MFIFOCTL_RXFLUSH_A { match self . bits { false => MFIFOCTL_RXFLUSH_A :: MFIFOCTL_RXFLUSH_NOFLUSH , true => MFIFOCTL_RXFLUSH_A :: MFIFOCTL_RXFLUSH_FLUSH , } } # [doc = "NOFLUSH"] # [inline (always)] pub fn is_mfifoctl_rxflush_noflush (& self) -> bool { * self == MFIFOCTL_RXFLUSH_A :: MFIFOCTL_RXFLUSH_NOFLUSH } # [doc = "FLUSH"] # [inline (always)] pub fn is_mfifoctl_rxflush_flush (& self) -> bool { * self == MFIFOCTL_RXFLUSH_A :: MFIFOCTL_RXFLUSH_FLUSH } } # [doc = "Field `MFIFOCTL_RXFLUSH` writer - RX FIFO Flush Setting this bit will Flush the RX FIFO. Before reseting this bit to stop Flush the RXFIFOCNT should be checked to be 0 and indicating that the Flush has completed."] pub type MFIFOCTL_RXFLUSH_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , MFIFOCTL_RXFLUSH_A > ; impl < 'a , REG , const O : u8 > MFIFOCTL_RXFLUSH_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NOFLUSH"] # [inline (always)] pub fn mfifoctl_rxflush_noflush (self) -> & 'a mut crate :: W < REG > { self . variant (MFIFOCTL_RXFLUSH_A :: MFIFOCTL_RXFLUSH_NOFLUSH) } # [doc = "FLUSH"] # [inline (always)] pub fn mfifoctl_rxflush_flush (self) -> & 'a mut crate :: W < REG > { self . variant (MFIFOCTL_RXFLUSH_A :: MFIFOCTL_RXFLUSH_FLUSH) } } impl R { # [doc = "Bits 0:2 - TX FIFO Trigger Indicates at what fill level in the TX FIFO a trigger will be generated."] # [inline (always)] pub fn mfifoctl_txtrig (& self) -> MFIFOCTL_TXTRIG_R { MFIFOCTL_TXTRIG_R :: new ((self . bits & 7) as u8) } # [doc = "Bit 7 - TX FIFO Flush Setting this bit will Flush the TX FIFO. Before reseting this bit to stop Flush the TXFIFOCNT should be checked to be 8 and indicating that the Flush has completed."] # [inline (always)] pub fn mfifoctl_txflush (& self) -> MFIFOCTL_TXFLUSH_R { MFIFOCTL_TXFLUSH_R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bits 8:10 - RX FIFO Trigger Indicates at what fill level in the RX FIFO a trigger will be generated. Note: Programming RXTRIG to 0x0 has no effect since no data is present to transfer out of RX FIFO."] # [inline (always)] pub fn mfifoctl_rxtrig (& self) -> MFIFOCTL_RXTRIG_R { MFIFOCTL_RXTRIG_R :: new (((self . bits >> 8) & 7) as u8) } # [doc = "Bit 15 - RX FIFO Flush Setting this bit will Flush the RX FIFO. Before reseting this bit to stop Flush the RXFIFOCNT should be checked to be 0 and indicating that the Flush has completed."] # [inline (always)] pub fn mfifoctl_rxflush (& self) -> MFIFOCTL_RXFLUSH_R { MFIFOCTL_RXFLUSH_R :: new (((self . bits >> 15) & 1) != 0) } } impl W { # [doc = "Bits 0:2 - TX FIFO Trigger Indicates at what fill level in the TX FIFO a trigger will be generated."] # [inline (always)] # [must_use] pub fn mfifoctl_txtrig (& mut self) -> MFIFOCTL_TXTRIG_W < MFIFOCTL_SPEC , 0 > { MFIFOCTL_TXTRIG_W :: new (self) } # [doc = "Bit 7 - TX FIFO Flush Setting this bit will Flush the TX FIFO. Before reseting this bit to stop Flush the TXFIFOCNT should be checked to be 8 and indicating that the Flush has completed."] # [inline (always)] # [must_use] pub fn mfifoctl_txflush (& mut self) -> MFIFOCTL_TXFLUSH_W < MFIFOCTL_SPEC , 7 > { MFIFOCTL_TXFLUSH_W :: new (self) } # [doc = "Bits 8:10 - RX FIFO Trigger Indicates at what fill level in the RX FIFO a trigger will be generated. Note: Programming RXTRIG to 0x0 has no effect since no data is present to transfer out of RX FIFO."] # [inline (always)] # [must_use] pub fn mfifoctl_rxtrig (& mut self) -> MFIFOCTL_RXTRIG_W <'_, MFIFOCTL_SPEC , 8 > { MFIFOCTL_RXTRIG_W :: new (self) } # [doc = "Bit 15 - RX FIFO Flush Setting this bit will Flush the RX FIFO. Before reseting this bit to stop Flush the RXFIFOCNT should be checked to be 0 and indicating that the Flush has completed."] # [inline (always)] # [must_use] pub fn mfifoctl_rxflush (& mut self) -> MFIFOCTL_RXFLUSH_W < MFIFOCTL_SPEC , 15 > { MFIFOCTL_RXFLUSH_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "I2C Master FIFO Control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mfifoctl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mfifoctl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct MFIFOCTL_SPEC ; impl crate :: RegisterSpec for MFIFOCTL_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`mfifoctl::R`](R) reader structure"] impl crate :: Readable for MFIFOCTL_SPEC { } # [doc = "`write(|w| ..)` method takes [`mfifoctl::W`](W) writer structure"] impl crate :: Writable for MFIFOCTL_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets MFIFOCTL to value 0"] impl crate :: Resettable for MFIFOCTL_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/i2c0/soar2.rs:1:4254 [INFO] [stdout] | [INFO] [stdout] 1 | ...use] pub fn soar2_oar2en (& mut self) -> SOAR2_OAR2EN_W < SOAR2_SPEC , 7 > { SOAR2_OAR2EN_W :: new (self) } # [doc = "Bits 16:22 - I2C... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `SOAR2` reader"] pub type R = crate :: R < SOAR2_SPEC > ; # [doc = "Register `SOAR2` writer"] pub type W = crate :: W < SOAR2_SPEC > ; # [doc = "Field `SOAR2_OAR2` reader - I2C Slave Own Address 2 This field specifies the alternate OAR2 address."] pub type SOAR2_OAR2_R = crate :: FieldReader ; # [doc = "Field `SOAR2_OAR2` writer - I2C Slave Own Address 2 This field specifies the alternate OAR2 address."] pub type SOAR2_OAR2_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 7 , O > ; # [doc = "Field `SOAR2_OAR2EN` reader - I2C Slave Own Address 2 Enable"] pub type SOAR2_OAR2EN_R = crate :: BitReader < SOAR2_OAR2EN_A > ; # [doc = "I2C Slave Own Address 2 Enable\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum SOAR2_OAR2EN_A { # [doc = "0: DISABLE"] SOAR2_OAR2EN_DISABLE = 0 , # [doc = "1: ENABLE"] SOAR2_OAR2EN_ENABLE = 1 , } impl From < SOAR2_OAR2EN_A > for bool { # [inline (always)] fn from (variant : SOAR2_OAR2EN_A) -> Self { variant as u8 != 0 } } impl SOAR2_OAR2EN_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> SOAR2_OAR2EN_A { match self . bits { false => SOAR2_OAR2EN_A :: SOAR2_OAR2EN_DISABLE , true => SOAR2_OAR2EN_A :: SOAR2_OAR2EN_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_soar2_oar2en_disable (& self) -> bool { * self == SOAR2_OAR2EN_A :: SOAR2_OAR2EN_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_soar2_oar2en_enable (& self) -> bool { * self == SOAR2_OAR2EN_A :: SOAR2_OAR2EN_ENABLE } } # [doc = "Field `SOAR2_OAR2EN` writer - I2C Slave Own Address 2 Enable"] pub type SOAR2_OAR2EN_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , SOAR2_OAR2EN_A > ; impl < 'a , REG , const O : u8 > SOAR2_OAR2EN_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn soar2_oar2en_disable (self) -> & 'a mut crate :: W < REG > { self . variant (SOAR2_OAR2EN_A :: SOAR2_OAR2EN_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn soar2_oar2en_enable (self) -> & 'a mut crate :: W < REG > { self . variant (SOAR2_OAR2EN_A :: SOAR2_OAR2EN_ENABLE) } } # [doc = "Field `SOAR2_OAR2_MASK` reader - I2C Slave Own Address 2 Mask: This field specifies bits A6 through A0 of the slave address. The bits with value 1 in SOAR2.OAR2_MASK field will make the corresponding incoming address bits to match by default regardless of the value inside SOAR2.OAR2 i.e. corresponding SOAR2.OAR2 bit is a dont care."] pub type SOAR2_OAR2_MASK_R = crate :: FieldReader ; # [doc = "Field `SOAR2_OAR2_MASK` writer - I2C Slave Own Address 2 Mask: This field specifies bits A6 through A0 of the slave address. The bits with value 1 in SOAR2.OAR2_MASK field will make the corresponding incoming address bits to match by default regardless of the value inside SOAR2.OAR2 i.e. corresponding SOAR2.OAR2 bit is a dont care."] pub type SOAR2_OAR2_MASK_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 7 , O > ; impl R { # [doc = "Bits 0:6 - I2C Slave Own Address 2 This field specifies the alternate OAR2 address."] # [inline (always)] pub fn soar2_oar2 (& self) -> SOAR2_OAR2_R { SOAR2_OAR2_R :: new ((self . bits & 0x7f) as u8) } # [doc = "Bit 7 - I2C Slave Own Address 2 Enable"] # [inline (always)] pub fn soar2_oar2en (& self) -> SOAR2_OAR2EN_R { SOAR2_OAR2EN_R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bits 16:22 - I2C Slave Own Address 2 Mask: This field specifies bits A6 through A0 of the slave address. The bits with value 1 in SOAR2.OAR2_MASK field will make the corresponding incoming address bits to match by default regardless of the value inside SOAR2.OAR2 i.e. corresponding SOAR2.OAR2 bit is a dont care."] # [inline (always)] pub fn soar2_oar2_mask (& self) -> SOAR2_OAR2_MASK_R { SOAR2_OAR2_MASK_R :: new (((self . bits >> 16) & 0x7f) as u8) } } impl W { # [doc = "Bits 0:6 - I2C Slave Own Address 2 This field specifies the alternate OAR2 address."] # [inline (always)] # [must_use] pub fn soar2_oar2 (& mut self) -> SOAR2_OAR2_W < SOAR2_SPEC , 0 > { SOAR2_OAR2_W :: new (self) } # [doc = "Bit 7 - I2C Slave Own Address 2 Enable"] # [inline (always)] # [must_use] pub fn soar2_oar2en (& mut self) -> SOAR2_OAR2EN_W <'_, SOAR2_SPEC , 7 > { SOAR2_OAR2EN_W :: new (self) } # [doc = "Bits 16:22 - I2C Slave Own Address 2 Mask: This field specifies bits A6 through A0 of the slave address. The bits with value 1 in SOAR2.OAR2_MASK field will make the corresponding incoming address bits to match by default regardless of the value inside SOAR2.OAR2 i.e. corresponding SOAR2.OAR2 bit is a dont care."] # [inline (always)] # [must_use] pub fn soar2_oar2_mask (& mut self) -> SOAR2_OAR2_MASK_W < SOAR2_SPEC , 16 > { SOAR2_OAR2_MASK_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "I2C Slave Own Address 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`soar2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`soar2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct SOAR2_SPEC ; impl crate :: RegisterSpec for SOAR2_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`soar2::R`](R) reader structure"] impl crate :: Readable for SOAR2_SPEC { } # [doc = "`write(|w| ..)` method takes [`soar2::W`](W) writer structure"] impl crate :: Writable for SOAR2_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets SOAR2 to value 0"] impl crate :: Resettable for SOAR2_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/cpuss/int_group1_iset.rs:1:1312 [INFO] [stdout] | [INFO] [stdout] 1 | ..._group1_iset_int (& mut self) -> INT_GROUP1_ISET_INT_W < INT_GROUP1_ISET_SPEC , 0 > { INT_GROUP1_ISET_INT_W :: new (self) } # [doc = r... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `INT_GROUP1_ISET` writer"] pub type W = crate :: W < INT_GROUP1_ISET_SPEC > ; # [doc = "Sets INT in RIS register\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_GROUP1_ISET_INT_AW { # [doc = "0: NO_EFFECT"] INT_GROUP1_ISET_INT_NO_EFFECT = 0 , # [doc = "1: SET"] INT_GROUP1_ISET_INT_SET = 1 , } impl From < INT_GROUP1_ISET_INT_AW > for bool { # [inline (always)] fn from (variant : INT_GROUP1_ISET_INT_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_GROUP1_ISET_INT` writer - Sets INT in RIS register"] pub type INT_GROUP1_ISET_INT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_GROUP1_ISET_INT_AW > ; impl < 'a , REG , const O : u8 > INT_GROUP1_ISET_INT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_group1_iset_int_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_GROUP1_ISET_INT_AW :: INT_GROUP1_ISET_INT_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_group1_iset_int_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_GROUP1_ISET_INT_AW :: INT_GROUP1_ISET_INT_SET) } } impl W { # [doc = "Bit 0 - Sets INT in RIS register"] # [inline (always)] # [must_use] pub fn int_group1_iset_int (& mut self) -> INT_GROUP1_ISET_INT_W <'_, INT_GROUP1_ISET_SPEC , 0 > { INT_GROUP1_ISET_INT_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Interrupt set\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_group1_iset::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct INT_GROUP1_ISET_SPEC ; impl crate :: RegisterSpec for INT_GROUP1_ISET_SPEC { type Ux = u32 ; } # [doc = "`write(|w| ..)` method takes [`int_group1_iset::W`](W) writer structure"] impl crate :: Writable for INT_GROUP1_ISET_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets INT_GROUP1_ISET to value 0"] impl crate :: Resettable for INT_GROUP1_ISET_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/spi0/clksel.rs:1:6632 [INFO] [stdout] | [INFO] [stdout] 1 | ...ub fn clksel_mfclk_sel (& mut self) -> CLKSEL_MFCLK_SEL_W < CLKSEL_SPEC , 2 > { CLKSEL_MFCLK_SEL_W :: new (self) } # [doc = "Bit 3 - S... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `CLKSEL` reader"] pub type R = crate :: R < CLKSEL_SPEC > ; # [doc = "Register `CLKSEL` writer"] pub type W = crate :: W < CLKSEL_SPEC > ; # [doc = "Field `CLKSEL_LFCLK_SEL` reader - Selects LFCLK as clock source if enabled"] pub type CLKSEL_LFCLK_SEL_R = crate :: BitReader < CLKSEL_LFCLK_SEL_A > ; # [doc = "Selects LFCLK as clock source if enabled\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CLKSEL_LFCLK_SEL_A { # [doc = "0: DISABLE"] CLKSEL_LFCLK_SEL_DISABLE = 0 , # [doc = "1: ENABLE"] CLKSEL_LFCLK_SEL_ENABLE = 1 , } impl From < CLKSEL_LFCLK_SEL_A > for bool { # [inline (always)] fn from (variant : CLKSEL_LFCLK_SEL_A) -> Self { variant as u8 != 0 } } impl CLKSEL_LFCLK_SEL_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CLKSEL_LFCLK_SEL_A { match self . bits { false => CLKSEL_LFCLK_SEL_A :: CLKSEL_LFCLK_SEL_DISABLE , true => CLKSEL_LFCLK_SEL_A :: CLKSEL_LFCLK_SEL_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_clksel_lfclk_sel_disable (& self) -> bool { * self == CLKSEL_LFCLK_SEL_A :: CLKSEL_LFCLK_SEL_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_clksel_lfclk_sel_enable (& self) -> bool { * self == CLKSEL_LFCLK_SEL_A :: CLKSEL_LFCLK_SEL_ENABLE } } # [doc = "Field `CLKSEL_LFCLK_SEL` writer - Selects LFCLK as clock source if enabled"] pub type CLKSEL_LFCLK_SEL_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CLKSEL_LFCLK_SEL_A > ; impl < 'a , REG , const O : u8 > CLKSEL_LFCLK_SEL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn clksel_lfclk_sel_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CLKSEL_LFCLK_SEL_A :: CLKSEL_LFCLK_SEL_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn clksel_lfclk_sel_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CLKSEL_LFCLK_SEL_A :: CLKSEL_LFCLK_SEL_ENABLE) } } # [doc = "Field `CLKSEL_MFCLK_SEL` reader - Selects MFCLK as clock source if enabled"] pub type CLKSEL_MFCLK_SEL_R = crate :: BitReader < CLKSEL_MFCLK_SEL_A > ; # [doc = "Selects MFCLK as clock source if enabled\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CLKSEL_MFCLK_SEL_A { # [doc = "0: DISABLE"] CLKSEL_MFCLK_SEL_DISABLE = 0 , # [doc = "1: ENABLE"] CLKSEL_MFCLK_SEL_ENABLE = 1 , } impl From < CLKSEL_MFCLK_SEL_A > for bool { # [inline (always)] fn from (variant : CLKSEL_MFCLK_SEL_A) -> Self { variant as u8 != 0 } } impl CLKSEL_MFCLK_SEL_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CLKSEL_MFCLK_SEL_A { match self . bits { false => CLKSEL_MFCLK_SEL_A :: CLKSEL_MFCLK_SEL_DISABLE , true => CLKSEL_MFCLK_SEL_A :: CLKSEL_MFCLK_SEL_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_clksel_mfclk_sel_disable (& self) -> bool { * self == CLKSEL_MFCLK_SEL_A :: CLKSEL_MFCLK_SEL_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_clksel_mfclk_sel_enable (& self) -> bool { * self == CLKSEL_MFCLK_SEL_A :: CLKSEL_MFCLK_SEL_ENABLE } } # [doc = "Field `CLKSEL_MFCLK_SEL` writer - Selects MFCLK as clock source if enabled"] pub type CLKSEL_MFCLK_SEL_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CLKSEL_MFCLK_SEL_A > ; impl < 'a , REG , const O : u8 > CLKSEL_MFCLK_SEL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn clksel_mfclk_sel_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CLKSEL_MFCLK_SEL_A :: CLKSEL_MFCLK_SEL_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn clksel_mfclk_sel_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CLKSEL_MFCLK_SEL_A :: CLKSEL_MFCLK_SEL_ENABLE) } } # [doc = "Field `CLKSEL_SYSCLK_SEL` reader - Selects SYSCLK as clock source if enabled"] pub type CLKSEL_SYSCLK_SEL_R = crate :: BitReader < CLKSEL_SYSCLK_SEL_A > ; # [doc = "Selects SYSCLK as clock source if enabled\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CLKSEL_SYSCLK_SEL_A { # [doc = "0: DISABLE"] CLKSEL_SYSCLK_SEL_DISABLE = 0 , # [doc = "1: ENABLE"] CLKSEL_SYSCLK_SEL_ENABLE = 1 , } impl From < CLKSEL_SYSCLK_SEL_A > for bool { # [inline (always)] fn from (variant : CLKSEL_SYSCLK_SEL_A) -> Self { variant as u8 != 0 } } impl CLKSEL_SYSCLK_SEL_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CLKSEL_SYSCLK_SEL_A { match self . bits { false => CLKSEL_SYSCLK_SEL_A :: CLKSEL_SYSCLK_SEL_DISABLE , true => CLKSEL_SYSCLK_SEL_A :: CLKSEL_SYSCLK_SEL_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_clksel_sysclk_sel_disable (& self) -> bool { * self == CLKSEL_SYSCLK_SEL_A :: CLKSEL_SYSCLK_SEL_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_clksel_sysclk_sel_enable (& self) -> bool { * self == CLKSEL_SYSCLK_SEL_A :: CLKSEL_SYSCLK_SEL_ENABLE } } # [doc = "Field `CLKSEL_SYSCLK_SEL` writer - Selects SYSCLK as clock source if enabled"] pub type CLKSEL_SYSCLK_SEL_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CLKSEL_SYSCLK_SEL_A > ; impl < 'a , REG , const O : u8 > CLKSEL_SYSCLK_SEL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn clksel_sysclk_sel_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CLKSEL_SYSCLK_SEL_A :: CLKSEL_SYSCLK_SEL_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn clksel_sysclk_sel_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CLKSEL_SYSCLK_SEL_A :: CLKSEL_SYSCLK_SEL_ENABLE) } } impl R { # [doc = "Bit 1 - Selects LFCLK as clock source if enabled"] # [inline (always)] pub fn clksel_lfclk_sel (& self) -> CLKSEL_LFCLK_SEL_R { CLKSEL_LFCLK_SEL_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - Selects MFCLK as clock source if enabled"] # [inline (always)] pub fn clksel_mfclk_sel (& self) -> CLKSEL_MFCLK_SEL_R { CLKSEL_MFCLK_SEL_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - Selects SYSCLK as clock source if enabled"] # [inline (always)] pub fn clksel_sysclk_sel (& self) -> CLKSEL_SYSCLK_SEL_R { CLKSEL_SYSCLK_SEL_R :: new (((self . bits >> 3) & 1) != 0) } } impl W { # [doc = "Bit 1 - Selects LFCLK as clock source if enabled"] # [inline (always)] # [must_use] pub fn clksel_lfclk_sel (& mut self) -> CLKSEL_LFCLK_SEL_W < CLKSEL_SPEC , 1 > { CLKSEL_LFCLK_SEL_W :: new (self) } # [doc = "Bit 2 - Selects MFCLK as clock source if enabled"] # [inline (always)] # [must_use] pub fn clksel_mfclk_sel (& mut self) -> CLKSEL_MFCLK_SEL_W <'_, CLKSEL_SPEC , 2 > { CLKSEL_MFCLK_SEL_W :: new (self) } # [doc = "Bit 3 - Selects SYSCLK as clock source if enabled"] # [inline (always)] # [must_use] pub fn clksel_sysclk_sel (& mut self) -> CLKSEL_SYSCLK_SEL_W < CLKSEL_SPEC , 3 > { CLKSEL_SYSCLK_SEL_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Clock Select for Ultra Low Power peripherals\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clksel::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clksel::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CLKSEL_SPEC ; impl crate :: RegisterSpec for CLKSEL_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`clksel::R`](R) reader structure"] impl crate :: Readable for CLKSEL_SPEC { } # [doc = "`write(|w| ..)` method takes [`clksel::W`](W) writer structure"] impl crate :: Writable for CLKSEL_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets CLKSEL to value 0"] impl crate :: Resettable for CLKSEL_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/i2c0/mtpr.rs:1:2100 [INFO] [stdout] | [INFO] [stdout] 1 | ... [must_use] pub fn mtpr_tpr (& mut self) -> MTPR_TPR_W < MTPR_SPEC , 0 > { MTPR_TPR_W :: new (self) } # [doc = r" Writes raw bits to t... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `MTPR` reader"] pub type R = crate :: R < MTPR_SPEC > ; # [doc = "Register `MTPR` writer"] pub type W = crate :: W < MTPR_SPEC > ; # [doc = "Field `MTPR_TPR` reader - Timer Period This field is used in the equation to configure SCL_PERIOD : SCL_PERIOD = (1 + TPR ) * (SCL_LP + SCL_HP ) * INT_CLK_PRD where: SCL_PRD is the SCL line period (I2C clock). TPR is the Timer Period register value (range of 1 to 127). SCL_LP is the SCL Low period (fixed at 6). SCL_HP is the SCL High period (fixed at 4). CLK_PRD is the functional clock period in ns."] pub type MTPR_TPR_R = crate :: FieldReader ; # [doc = "Field `MTPR_TPR` writer - Timer Period This field is used in the equation to configure SCL_PERIOD : SCL_PERIOD = (1 + TPR ) * (SCL_LP + SCL_HP ) * INT_CLK_PRD where: SCL_PRD is the SCL line period (I2C clock). TPR is the Timer Period register value (range of 1 to 127). SCL_LP is the SCL Low period (fixed at 6). SCL_HP is the SCL High period (fixed at 4). CLK_PRD is the functional clock period in ns."] pub type MTPR_TPR_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 7 , O > ; impl R { # [doc = "Bits 0:6 - Timer Period This field is used in the equation to configure SCL_PERIOD : SCL_PERIOD = (1 + TPR ) * (SCL_LP + SCL_HP ) * INT_CLK_PRD where: SCL_PRD is the SCL line period (I2C clock). TPR is the Timer Period register value (range of 1 to 127). SCL_LP is the SCL Low period (fixed at 6). SCL_HP is the SCL High period (fixed at 4). CLK_PRD is the functional clock period in ns."] # [inline (always)] pub fn mtpr_tpr (& self) -> MTPR_TPR_R { MTPR_TPR_R :: new ((self . bits & 0x7f) as u8) } } impl W { # [doc = "Bits 0:6 - Timer Period This field is used in the equation to configure SCL_PERIOD : SCL_PERIOD = (1 + TPR ) * (SCL_LP + SCL_HP ) * INT_CLK_PRD where: SCL_PRD is the SCL line period (I2C clock). TPR is the Timer Period register value (range of 1 to 127). SCL_LP is the SCL Low period (fixed at 6). SCL_HP is the SCL High period (fixed at 4). CLK_PRD is the functional clock period in ns."] # [inline (always)] # [must_use] pub fn mtpr_tpr (& mut self) -> MTPR_TPR_W <'_, MTPR_SPEC , 0 > { MTPR_TPR_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "I2C Master Timer Period\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mtpr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mtpr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct MTPR_SPEC ; impl crate :: RegisterSpec for MTPR_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`mtpr::R`](R) reader structure"] impl crate :: Readable for MTPR_SPEC { } # [doc = "`write(|w| ..)` method takes [`mtpr::W`](W) writer structure"] impl crate :: Writable for MTPR_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets MTPR to value 0x01"] impl crate :: Resettable for MTPR_SPEC { const RESET_VALUE : Self :: Ux = 0x01 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/i2c1/int_event1_iset.rs:1:5642 [INFO] [stdout] | [INFO] [stdout] 1 | ...t_mtxfifotrg (& mut self) -> INT_EVENT1_ISET_MTXFIFOTRG_W < INT_EVENT1_ISET_SPEC , 1 > { INT_EVENT1_ISET_MTXFIFOTRG_W :: new (self) } ... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `INT_EVENT1_ISET` writer"] pub type W = crate :: W < INT_EVENT1_ISET_SPEC > ; # [doc = "Master Receive FIFO Trigger Trigger when RX FIFO contains &gt;= defined bytes\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT1_ISET_MRXFIFOTRG_AW { # [doc = "0: NO_EFFECT"] INT_EVENT1_ISET_MRXFIFOTRG_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT1_ISET_MRXFIFOTRG_SET = 1 , } impl From < INT_EVENT1_ISET_MRXFIFOTRG_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT1_ISET_MRXFIFOTRG_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT1_ISET_MRXFIFOTRG` writer - Master Receive FIFO Trigger Trigger when RX FIFO contains &gt;= defined bytes"] pub type INT_EVENT1_ISET_MRXFIFOTRG_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT1_ISET_MRXFIFOTRG_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT1_ISET_MRXFIFOTRG_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event1_iset_mrxfifotrg_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_ISET_MRXFIFOTRG_AW :: INT_EVENT1_ISET_MRXFIFOTRG_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event1_iset_mrxfifotrg_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_ISET_MRXFIFOTRG_AW :: INT_EVENT1_ISET_MRXFIFOTRG_SET) } } # [doc = "Master Transmit FIFO Trigger Trigger when Transmit FIFO contains &lt;= defined bytes\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT1_ISET_MTXFIFOTRG_AW { # [doc = "0: NO_EFFECT"] INT_EVENT1_ISET_MTXFIFOTRG_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT1_ISET_MTXFIFOTRG_SET = 1 , } impl From < INT_EVENT1_ISET_MTXFIFOTRG_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT1_ISET_MTXFIFOTRG_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT1_ISET_MTXFIFOTRG` writer - Master Transmit FIFO Trigger Trigger when Transmit FIFO contains &lt;= defined bytes"] pub type INT_EVENT1_ISET_MTXFIFOTRG_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT1_ISET_MTXFIFOTRG_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT1_ISET_MTXFIFOTRG_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event1_iset_mtxfifotrg_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_ISET_MTXFIFOTRG_AW :: INT_EVENT1_ISET_MTXFIFOTRG_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event1_iset_mtxfifotrg_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_ISET_MTXFIFOTRG_AW :: INT_EVENT1_ISET_MTXFIFOTRG_SET) } } # [doc = "Slave Receive FIFO Trigger\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT1_ISET_SRXFIFOTRG_AW { # [doc = "0: NO_EFFECT"] INT_EVENT1_ISET_SRXFIFOTRG_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT1_ISET_SRXFIFOTRG_SET = 1 , } impl From < INT_EVENT1_ISET_SRXFIFOTRG_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT1_ISET_SRXFIFOTRG_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT1_ISET_SRXFIFOTRG` writer - Slave Receive FIFO Trigger"] pub type INT_EVENT1_ISET_SRXFIFOTRG_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT1_ISET_SRXFIFOTRG_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT1_ISET_SRXFIFOTRG_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event1_iset_srxfifotrg_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_ISET_SRXFIFOTRG_AW :: INT_EVENT1_ISET_SRXFIFOTRG_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event1_iset_srxfifotrg_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_ISET_SRXFIFOTRG_AW :: INT_EVENT1_ISET_SRXFIFOTRG_SET) } } # [doc = "Slave Transmit FIFO Trigger\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT1_ISET_STXFIFOTRG_AW { # [doc = "0: NO_EFFECT"] INT_EVENT1_ISET_STXFIFOTRG_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT1_ISET_STXFIFOTRG_SET = 1 , } impl From < INT_EVENT1_ISET_STXFIFOTRG_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT1_ISET_STXFIFOTRG_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT1_ISET_STXFIFOTRG` writer - Slave Transmit FIFO Trigger"] pub type INT_EVENT1_ISET_STXFIFOTRG_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT1_ISET_STXFIFOTRG_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT1_ISET_STXFIFOTRG_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event1_iset_stxfifotrg_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_ISET_STXFIFOTRG_AW :: INT_EVENT1_ISET_STXFIFOTRG_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event1_iset_stxfifotrg_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_ISET_STXFIFOTRG_AW :: INT_EVENT1_ISET_STXFIFOTRG_SET) } } impl W { # [doc = "Bit 0 - Master Receive FIFO Trigger Trigger when RX FIFO contains &gt;= defined bytes"] # [inline (always)] # [must_use] pub fn int_event1_iset_mrxfifotrg (& mut self) -> INT_EVENT1_ISET_MRXFIFOTRG_W < INT_EVENT1_ISET_SPEC , 0 > { INT_EVENT1_ISET_MRXFIFOTRG_W :: new (self) } # [doc = "Bit 1 - Master Transmit FIFO Trigger Trigger when Transmit FIFO contains &lt;= defined bytes"] # [inline (always)] # [must_use] pub fn int_event1_iset_mtxfifotrg (& mut self) -> INT_EVENT1_ISET_MTXFIFOTRG_W <'_, INT_EVENT1_ISET_SPEC , 1 > { INT_EVENT1_ISET_MTXFIFOTRG_W :: new (self) } # [doc = "Bit 2 - Slave Receive FIFO Trigger"] # [inline (always)] # [must_use] pub fn int_event1_iset_srxfifotrg (& mut self) -> INT_EVENT1_ISET_SRXFIFOTRG_W < INT_EVENT1_ISET_SPEC , 2 > { INT_EVENT1_ISET_SRXFIFOTRG_W :: new (self) } # [doc = "Bit 3 - Slave Transmit FIFO Trigger"] # [inline (always)] # [must_use] pub fn int_event1_iset_stxfifotrg (& mut self) -> INT_EVENT1_ISET_STXFIFOTRG_W < INT_EVENT1_ISET_SPEC , 3 > { INT_EVENT1_ISET_STXFIFOTRG_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Interrupt set\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_event1_iset::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct INT_EVENT1_ISET_SPEC ; impl crate :: RegisterSpec for INT_EVENT1_ISET_SPEC { type Ux = u32 ; } # [doc = "`write(|w| ..)` method takes [`int_event1_iset::W`](W) writer structure"] impl crate :: Writable for INT_EVENT1_ISET_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets INT_EVENT1_ISET to value 0"] impl crate :: Resettable for INT_EVENT1_ISET_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/i2c1/gfctl.rs:1:12770 [INFO] [stdout] | [INFO] [stdout] 1 | ...use] pub fn gfctl_dgfsel (& mut self) -> GFCTL_DGFSEL_W < GFCTL_SPEC , 0 > { GFCTL_DGFSEL_W :: new (self) } # [doc = "Bit 8 - Analog G... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `GFCTL` reader"] pub type R = crate :: R < GFCTL_SPEC > ; # [doc = "Register `GFCTL` writer"] pub type W = crate :: W < GFCTL_SPEC > ; # [doc = "Field `GFCTL_DGFSEL` reader - Glitch Suppression Pulse Width This field controls the pulse width select for glitch suppression on the SCL and SDA lines. The following values are the glitch suppression values in terms of functional clocks. (Core Domain only)"] pub type GFCTL_DGFSEL_R = crate :: FieldReader < GFCTL_DGFSEL_A > ; # [doc = "Glitch Suppression Pulse Width This field controls the pulse width select for glitch suppression on the SCL and SDA lines. The following values are the glitch suppression values in terms of functional clocks. (Core Domain only)\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum GFCTL_DGFSEL_A { # [doc = "0: DISABLED"] GFCTL_DGFSEL_DISABLED = 0 , # [doc = "1: CLK_1"] GFCTL_DGFSEL_CLK_1 = 1 , # [doc = "2: CLK_2"] GFCTL_DGFSEL_CLK_2 = 2 , # [doc = "3: CLK_3"] GFCTL_DGFSEL_CLK_3 = 3 , # [doc = "4: CLK_4"] GFCTL_DGFSEL_CLK_4 = 4 , # [doc = "5: CLK_8"] GFCTL_DGFSEL_CLK_8 = 5 , # [doc = "6: CLK_16"] GFCTL_DGFSEL_CLK_16 = 6 , # [doc = "7: CLK_31"] GFCTL_DGFSEL_CLK_31 = 7 , } impl From < GFCTL_DGFSEL_A > for u8 { # [inline (always)] fn from (variant : GFCTL_DGFSEL_A) -> Self { variant as _ } } impl crate :: FieldSpec for GFCTL_DGFSEL_A { type Ux = u8 ; } impl GFCTL_DGFSEL_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> GFCTL_DGFSEL_A { match self . bits { 0 => GFCTL_DGFSEL_A :: GFCTL_DGFSEL_DISABLED , 1 => GFCTL_DGFSEL_A :: GFCTL_DGFSEL_CLK_1 , 2 => GFCTL_DGFSEL_A :: GFCTL_DGFSEL_CLK_2 , 3 => GFCTL_DGFSEL_A :: GFCTL_DGFSEL_CLK_3 , 4 => GFCTL_DGFSEL_A :: GFCTL_DGFSEL_CLK_4 , 5 => GFCTL_DGFSEL_A :: GFCTL_DGFSEL_CLK_8 , 6 => GFCTL_DGFSEL_A :: GFCTL_DGFSEL_CLK_16 , 7 => GFCTL_DGFSEL_A :: GFCTL_DGFSEL_CLK_31 , _ => unreachable ! () , } } # [doc = "DISABLED"] # [inline (always)] pub fn is_gfctl_dgfsel_disabled (& self) -> bool { * self == GFCTL_DGFSEL_A :: GFCTL_DGFSEL_DISABLED } # [doc = "CLK_1"] # [inline (always)] pub fn is_gfctl_dgfsel_clk_1 (& self) -> bool { * self == GFCTL_DGFSEL_A :: GFCTL_DGFSEL_CLK_1 } # [doc = "CLK_2"] # [inline (always)] pub fn is_gfctl_dgfsel_clk_2 (& self) -> bool { * self == GFCTL_DGFSEL_A :: GFCTL_DGFSEL_CLK_2 } # [doc = "CLK_3"] # [inline (always)] pub fn is_gfctl_dgfsel_clk_3 (& self) -> bool { * self == GFCTL_DGFSEL_A :: GFCTL_DGFSEL_CLK_3 } # [doc = "CLK_4"] # [inline (always)] pub fn is_gfctl_dgfsel_clk_4 (& self) -> bool { * self == GFCTL_DGFSEL_A :: GFCTL_DGFSEL_CLK_4 } # [doc = "CLK_8"] # [inline (always)] pub fn is_gfctl_dgfsel_clk_8 (& self) -> bool { * self == GFCTL_DGFSEL_A :: GFCTL_DGFSEL_CLK_8 } # [doc = "CLK_16"] # [inline (always)] pub fn is_gfctl_dgfsel_clk_16 (& self) -> bool { * self == GFCTL_DGFSEL_A :: GFCTL_DGFSEL_CLK_16 } # [doc = "CLK_31"] # [inline (always)] pub fn is_gfctl_dgfsel_clk_31 (& self) -> bool { * self == GFCTL_DGFSEL_A :: GFCTL_DGFSEL_CLK_31 } } # [doc = "Field `GFCTL_DGFSEL` writer - Glitch Suppression Pulse Width This field controls the pulse width select for glitch suppression on the SCL and SDA lines. The following values are the glitch suppression values in terms of functional clocks. (Core Domain only)"] pub type GFCTL_DGFSEL_W < 'a , REG , const O : u8 > = crate :: FieldWriterSafe < 'a , REG , 3 , O , GFCTL_DGFSEL_A > ; impl < 'a , REG , const O : u8 > GFCTL_DGFSEL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "DISABLED"] # [inline (always)] pub fn gfctl_dgfsel_disabled (self) -> & 'a mut crate :: W < REG > { self . variant (GFCTL_DGFSEL_A :: GFCTL_DGFSEL_DISABLED) } # [doc = "CLK_1"] # [inline (always)] pub fn gfctl_dgfsel_clk_1 (self) -> & 'a mut crate :: W < REG > { self . variant (GFCTL_DGFSEL_A :: GFCTL_DGFSEL_CLK_1) } # [doc = "CLK_2"] # [inline (always)] pub fn gfctl_dgfsel_clk_2 (self) -> & 'a mut crate :: W < REG > { self . variant (GFCTL_DGFSEL_A :: GFCTL_DGFSEL_CLK_2) } # [doc = "CLK_3"] # [inline (always)] pub fn gfctl_dgfsel_clk_3 (self) -> & 'a mut crate :: W < REG > { self . variant (GFCTL_DGFSEL_A :: GFCTL_DGFSEL_CLK_3) } # [doc = "CLK_4"] # [inline (always)] pub fn gfctl_dgfsel_clk_4 (self) -> & 'a mut crate :: W < REG > { self . variant (GFCTL_DGFSEL_A :: GFCTL_DGFSEL_CLK_4) } # [doc = "CLK_8"] # [inline (always)] pub fn gfctl_dgfsel_clk_8 (self) -> & 'a mut crate :: W < REG > { self . variant (GFCTL_DGFSEL_A :: GFCTL_DGFSEL_CLK_8) } # [doc = "CLK_16"] # [inline (always)] pub fn gfctl_dgfsel_clk_16 (self) -> & 'a mut crate :: W < REG > { self . variant (GFCTL_DGFSEL_A :: GFCTL_DGFSEL_CLK_16) } # [doc = "CLK_31"] # [inline (always)] pub fn gfctl_dgfsel_clk_31 (self) -> & 'a mut crate :: W < REG > { self . variant (GFCTL_DGFSEL_A :: GFCTL_DGFSEL_CLK_31) } } # [doc = "Field `GFCTL_AGFEN` reader - Analog Glitch Suppression Enable"] pub type GFCTL_AGFEN_R = crate :: BitReader < GFCTL_AGFEN_A > ; # [doc = "Analog Glitch Suppression Enable\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum GFCTL_AGFEN_A { # [doc = "0: DISABLE"] GFCTL_AGFEN_DISABLE = 0 , # [doc = "1: ENABLE"] GFCTL_AGFEN_ENABLE = 1 , } impl From < GFCTL_AGFEN_A > for bool { # [inline (always)] fn from (variant : GFCTL_AGFEN_A) -> Self { variant as u8 != 0 } } impl GFCTL_AGFEN_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> GFCTL_AGFEN_A { match self . bits { false => GFCTL_AGFEN_A :: GFCTL_AGFEN_DISABLE , true => GFCTL_AGFEN_A :: GFCTL_AGFEN_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_gfctl_agfen_disable (& self) -> bool { * self == GFCTL_AGFEN_A :: GFCTL_AGFEN_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_gfctl_agfen_enable (& self) -> bool { * self == GFCTL_AGFEN_A :: GFCTL_AGFEN_ENABLE } } # [doc = "Field `GFCTL_AGFEN` writer - Analog Glitch Suppression Enable"] pub type GFCTL_AGFEN_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , GFCTL_AGFEN_A > ; impl < 'a , REG , const O : u8 > GFCTL_AGFEN_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn gfctl_agfen_disable (self) -> & 'a mut crate :: W < REG > { self . variant (GFCTL_AGFEN_A :: GFCTL_AGFEN_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn gfctl_agfen_enable (self) -> & 'a mut crate :: W < REG > { self . variant (GFCTL_AGFEN_A :: GFCTL_AGFEN_ENABLE) } } # [doc = "Field `GFCTL_AGFSEL` reader - Analog Glitch Suppression Pulse Width This field controls the pulse width select for the analog glitch suppression on SCL and SDA lines. See device datasheet for exact values. (ULP I2C only)"] pub type GFCTL_AGFSEL_R = crate :: FieldReader < GFCTL_AGFSEL_A > ; # [doc = "Analog Glitch Suppression Pulse Width This field controls the pulse width select for the analog glitch suppression on SCL and SDA lines. See device datasheet for exact values. (ULP I2C only)\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum GFCTL_AGFSEL_A { # [doc = "0: AGLIT_5"] GFCTL_AGFSEL_AGLIT_5 = 0 , # [doc = "1: AGLIT_10"] GFCTL_AGFSEL_AGLIT_10 = 1 , # [doc = "2: AGLIT_25"] GFCTL_AGFSEL_AGLIT_25 = 2 , # [doc = "3: AGLIT_50"] GFCTL_AGFSEL_AGLIT_50 = 3 , } impl From < GFCTL_AGFSEL_A > for u8 { # [inline (always)] fn from (variant : GFCTL_AGFSEL_A) -> Self { variant as _ } } impl crate :: FieldSpec for GFCTL_AGFSEL_A { type Ux = u8 ; } impl GFCTL_AGFSEL_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> GFCTL_AGFSEL_A { match self . bits { 0 => GFCTL_AGFSEL_A :: GFCTL_AGFSEL_AGLIT_5 , 1 => GFCTL_AGFSEL_A :: GFCTL_AGFSEL_AGLIT_10 , 2 => GFCTL_AGFSEL_A :: GFCTL_AGFSEL_AGLIT_25 , 3 => GFCTL_AGFSEL_A :: GFCTL_AGFSEL_AGLIT_50 , _ => unreachable ! () , } } # [doc = "AGLIT_5"] # [inline (always)] pub fn is_gfctl_agfsel_aglit_5 (& self) -> bool { * self == GFCTL_AGFSEL_A :: GFCTL_AGFSEL_AGLIT_5 } # [doc = "AGLIT_10"] # [inline (always)] pub fn is_gfctl_agfsel_aglit_10 (& self) -> bool { * self == GFCTL_AGFSEL_A :: GFCTL_AGFSEL_AGLIT_10 } # [doc = "AGLIT_25"] # [inline (always)] pub fn is_gfctl_agfsel_aglit_25 (& self) -> bool { * self == GFCTL_AGFSEL_A :: GFCTL_AGFSEL_AGLIT_25 } # [doc = "AGLIT_50"] # [inline (always)] pub fn is_gfctl_agfsel_aglit_50 (& self) -> bool { * self == GFCTL_AGFSEL_A :: GFCTL_AGFSEL_AGLIT_50 } } # [doc = "Field `GFCTL_AGFSEL` writer - Analog Glitch Suppression Pulse Width This field controls the pulse width select for the analog glitch suppression on SCL and SDA lines. See device datasheet for exact values. (ULP I2C only)"] pub type GFCTL_AGFSEL_W < 'a , REG , const O : u8 > = crate :: FieldWriterSafe < 'a , REG , 2 , O , GFCTL_AGFSEL_A > ; impl < 'a , REG , const O : u8 > GFCTL_AGFSEL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "AGLIT_5"] # [inline (always)] pub fn gfctl_agfsel_aglit_5 (self) -> & 'a mut crate :: W < REG > { self . variant (GFCTL_AGFSEL_A :: GFCTL_AGFSEL_AGLIT_5) } # [doc = "AGLIT_10"] # [inline (always)] pub fn gfctl_agfsel_aglit_10 (self) -> & 'a mut crate :: W < REG > { self . variant (GFCTL_AGFSEL_A :: GFCTL_AGFSEL_AGLIT_10) } # [doc = "AGLIT_25"] # [inline (always)] pub fn gfctl_agfsel_aglit_25 (self) -> & 'a mut crate :: W < REG > { self . variant (GFCTL_AGFSEL_A :: GFCTL_AGFSEL_AGLIT_25) } # [doc = "AGLIT_50"] # [inline (always)] pub fn gfctl_agfsel_aglit_50 (self) -> & 'a mut crate :: W < REG > { self . variant (GFCTL_AGFSEL_A :: GFCTL_AGFSEL_AGLIT_50) } } # [doc = "Field `GFCTL_CHAIN` reader - Analog and digital noise filters chaining enable."] pub type GFCTL_CHAIN_R = crate :: BitReader < GFCTL_CHAIN_A > ; # [doc = "Analog and digital noise filters chaining enable.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum GFCTL_CHAIN_A { # [doc = "0: DISABLE"] GFCTL_CHAIN_DISABLE = 0 , # [doc = "1: ENABLE"] GFCTL_CHAIN_ENABLE = 1 , } impl From < GFCTL_CHAIN_A > for bool { # [inline (always)] fn from (variant : GFCTL_CHAIN_A) -> Self { variant as u8 != 0 } } impl GFCTL_CHAIN_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> GFCTL_CHAIN_A { match self . bits { false => GFCTL_CHAIN_A :: GFCTL_CHAIN_DISABLE , true => GFCTL_CHAIN_A :: GFCTL_CHAIN_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_gfctl_chain_disable (& self) -> bool { * self == GFCTL_CHAIN_A :: GFCTL_CHAIN_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_gfctl_chain_enable (& self) -> bool { * self == GFCTL_CHAIN_A :: GFCTL_CHAIN_ENABLE } } # [doc = "Field `GFCTL_CHAIN` writer - Analog and digital noise filters chaining enable."] pub type GFCTL_CHAIN_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , GFCTL_CHAIN_A > ; impl < 'a , REG , const O : u8 > GFCTL_CHAIN_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn gfctl_chain_disable (self) -> & 'a mut crate :: W < REG > { self . variant (GFCTL_CHAIN_A :: GFCTL_CHAIN_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn gfctl_chain_enable (self) -> & 'a mut crate :: W < REG > { self . variant (GFCTL_CHAIN_A :: GFCTL_CHAIN_ENABLE) } } impl R { # [doc = "Bits 0:2 - Glitch Suppression Pulse Width This field controls the pulse width select for glitch suppression on the SCL and SDA lines. The following values are the glitch suppression values in terms of functional clocks. (Core Domain only)"] # [inline (always)] pub fn gfctl_dgfsel (& self) -> GFCTL_DGFSEL_R { GFCTL_DGFSEL_R :: new ((self . bits & 7) as u8) } # [doc = "Bit 8 - Analog Glitch Suppression Enable"] # [inline (always)] pub fn gfctl_agfen (& self) -> GFCTL_AGFEN_R { GFCTL_AGFEN_R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bits 9:10 - Analog Glitch Suppression Pulse Width This field controls the pulse width select for the analog glitch suppression on SCL and SDA lines. See device datasheet for exact values. (ULP I2C only)"] # [inline (always)] pub fn gfctl_agfsel (& self) -> GFCTL_AGFSEL_R { GFCTL_AGFSEL_R :: new (((self . bits >> 9) & 3) as u8) } # [doc = "Bit 11 - Analog and digital noise filters chaining enable."] # [inline (always)] pub fn gfctl_chain (& self) -> GFCTL_CHAIN_R { GFCTL_CHAIN_R :: new (((self . bits >> 11) & 1) != 0) } } impl W { # [doc = "Bits 0:2 - Glitch Suppression Pulse Width This field controls the pulse width select for glitch suppression on the SCL and SDA lines. The following values are the glitch suppression values in terms of functional clocks. (Core Domain only)"] # [inline (always)] # [must_use] pub fn gfctl_dgfsel (& mut self) -> GFCTL_DGFSEL_W <'_, GFCTL_SPEC , 0 > { GFCTL_DGFSEL_W :: new (self) } # [doc = "Bit 8 - Analog Glitch Suppression Enable"] # [inline (always)] # [must_use] pub fn gfctl_agfen (& mut self) -> GFCTL_AGFEN_W < GFCTL_SPEC , 8 > { GFCTL_AGFEN_W :: new (self) } # [doc = "Bits 9:10 - Analog Glitch Suppression Pulse Width This field controls the pulse width select for the analog glitch suppression on SCL and SDA lines. See device datasheet for exact values. (ULP I2C only)"] # [inline (always)] # [must_use] pub fn gfctl_agfsel (& mut self) -> GFCTL_AGFSEL_W < GFCTL_SPEC , 9 > { GFCTL_AGFSEL_W :: new (self) } # [doc = "Bit 11 - Analog and digital noise filters chaining enable."] # [inline (always)] # [must_use] pub fn gfctl_chain (& mut self) -> GFCTL_CHAIN_W < GFCTL_SPEC , 11 > { GFCTL_CHAIN_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "I2C Glitch Filter Control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gfctl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gfctl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GFCTL_SPEC ; impl crate :: RegisterSpec for GFCTL_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`gfctl::R`](R) reader structure"] impl crate :: Readable for GFCTL_SPEC { } # [doc = "`write(|w| ..)` method takes [`gfctl::W`](W) writer structure"] impl crate :: Writable for GFCTL_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets GFCTL to value 0"] impl crate :: Resettable for GFCTL_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/timg4/ccctl_01.rs:1:34507 [INFO] [stdout] | [INFO] [stdout] 1 | ...pub fn ccctl_01_zcond (& mut self) -> CCCTL_01_ZCOND_W < CCCTL_01_SPEC , 12 > { CCCTL_01_ZCOND_W :: new (self) } # [doc = "Bit 17 - Ca... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `CCCTL_01[%s]` reader"] pub type R = crate :: R < CCCTL_01_SPEC > ; # [doc = "Register `CCCTL_01[%s]` writer"] pub type W = crate :: W < CCCTL_01_SPEC > ; # [doc = "Field `CCCTL_01_CCOND` reader - Capture Condition. #br# Specifies the condition that generates a capture pulse. 4h-Fh = Reserved"] pub type CCCTL_01_CCOND_R = crate :: FieldReader < CCCTL_01_CCOND_A > ; # [doc = "Capture Condition. #br# Specifies the condition that generates a capture pulse. 4h-Fh = Reserved\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum CCCTL_01_CCOND_A { # [doc = "0: NOCAPTURE"] CCCTL_01_CCOND_NOCAPTURE = 0 , # [doc = "1: CC_TRIG_RISE"] CCCTL_01_CCOND_CC_TRIG_RISE = 1 , # [doc = "2: CC_TRIG_FALL"] CCCTL_01_CCOND_CC_TRIG_FALL = 2 , # [doc = "3: CC_TRIG_EDGE"] CCCTL_01_CCOND_CC_TRIG_EDGE = 3 , } impl From < CCCTL_01_CCOND_A > for u8 { # [inline (always)] fn from (variant : CCCTL_01_CCOND_A) -> Self { variant as _ } } impl crate :: FieldSpec for CCCTL_01_CCOND_A { type Ux = u8 ; } impl CCCTL_01_CCOND_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < CCCTL_01_CCOND_A > { match self . bits { 0 => Some (CCCTL_01_CCOND_A :: CCCTL_01_CCOND_NOCAPTURE) , 1 => Some (CCCTL_01_CCOND_A :: CCCTL_01_CCOND_CC_TRIG_RISE) , 2 => Some (CCCTL_01_CCOND_A :: CCCTL_01_CCOND_CC_TRIG_FALL) , 3 => Some (CCCTL_01_CCOND_A :: CCCTL_01_CCOND_CC_TRIG_EDGE) , _ => None , } } # [doc = "NOCAPTURE"] # [inline (always)] pub fn is_ccctl_01_ccond_nocapture (& self) -> bool { * self == CCCTL_01_CCOND_A :: CCCTL_01_CCOND_NOCAPTURE } # [doc = "CC_TRIG_RISE"] # [inline (always)] pub fn is_ccctl_01_ccond_cc_trig_rise (& self) -> bool { * self == CCCTL_01_CCOND_A :: CCCTL_01_CCOND_CC_TRIG_RISE } # [doc = "CC_TRIG_FALL"] # [inline (always)] pub fn is_ccctl_01_ccond_cc_trig_fall (& self) -> bool { * self == CCCTL_01_CCOND_A :: CCCTL_01_CCOND_CC_TRIG_FALL } # [doc = "CC_TRIG_EDGE"] # [inline (always)] pub fn is_ccctl_01_ccond_cc_trig_edge (& self) -> bool { * self == CCCTL_01_CCOND_A :: CCCTL_01_CCOND_CC_TRIG_EDGE } } # [doc = "Field `CCCTL_01_CCOND` writer - Capture Condition. #br# Specifies the condition that generates a capture pulse. 4h-Fh = Reserved"] pub type CCCTL_01_CCOND_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 3 , O , CCCTL_01_CCOND_A > ; impl < 'a , REG , const O : u8 > CCCTL_01_CCOND_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "NOCAPTURE"] # [inline (always)] pub fn ccctl_01_ccond_nocapture (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CCOND_A :: CCCTL_01_CCOND_NOCAPTURE) } # [doc = "CC_TRIG_RISE"] # [inline (always)] pub fn ccctl_01_ccond_cc_trig_rise (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CCOND_A :: CCCTL_01_CCOND_CC_TRIG_RISE) } # [doc = "CC_TRIG_FALL"] # [inline (always)] pub fn ccctl_01_ccond_cc_trig_fall (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CCOND_A :: CCCTL_01_CCOND_CC_TRIG_FALL) } # [doc = "CC_TRIG_EDGE"] # [inline (always)] pub fn ccctl_01_ccond_cc_trig_edge (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CCOND_A :: CCCTL_01_CCOND_CC_TRIG_EDGE) } } # [doc = "Field `CCCTL_01_ACOND` reader - Advance Condition. #br# Specifies the condition that generates an advance pulse. 6h-Fh = Reserved"] pub type CCCTL_01_ACOND_R = crate :: FieldReader < CCCTL_01_ACOND_A > ; # [doc = "Advance Condition. #br# Specifies the condition that generates an advance pulse. 6h-Fh = Reserved\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum CCCTL_01_ACOND_A { # [doc = "0: TIMCLK"] CCCTL_01_ACOND_TIMCLK = 0 , # [doc = "1: CC_TRIG_RISE"] CCCTL_01_ACOND_CC_TRIG_RISE = 1 , # [doc = "2: CC_TRIG_FALL"] CCCTL_01_ACOND_CC_TRIG_FALL = 2 , # [doc = "3: CC_TRIG_EDGE"] CCCTL_01_ACOND_CC_TRIG_EDGE = 3 , # [doc = "5: CC_TRIG_HIGH"] CCCTL_01_ACOND_CC_TRIG_HIGH = 5 , } impl From < CCCTL_01_ACOND_A > for u8 { # [inline (always)] fn from (variant : CCCTL_01_ACOND_A) -> Self { variant as _ } } impl crate :: FieldSpec for CCCTL_01_ACOND_A { type Ux = u8 ; } impl CCCTL_01_ACOND_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < CCCTL_01_ACOND_A > { match self . bits { 0 => Some (CCCTL_01_ACOND_A :: CCCTL_01_ACOND_TIMCLK) , 1 => Some (CCCTL_01_ACOND_A :: CCCTL_01_ACOND_CC_TRIG_RISE) , 2 => Some (CCCTL_01_ACOND_A :: CCCTL_01_ACOND_CC_TRIG_FALL) , 3 => Some (CCCTL_01_ACOND_A :: CCCTL_01_ACOND_CC_TRIG_EDGE) , 5 => Some (CCCTL_01_ACOND_A :: CCCTL_01_ACOND_CC_TRIG_HIGH) , _ => None , } } # [doc = "TIMCLK"] # [inline (always)] pub fn is_ccctl_01_acond_timclk (& self) -> bool { * self == CCCTL_01_ACOND_A :: CCCTL_01_ACOND_TIMCLK } # [doc = "CC_TRIG_RISE"] # [inline (always)] pub fn is_ccctl_01_acond_cc_trig_rise (& self) -> bool { * self == CCCTL_01_ACOND_A :: CCCTL_01_ACOND_CC_TRIG_RISE } # [doc = "CC_TRIG_FALL"] # [inline (always)] pub fn is_ccctl_01_acond_cc_trig_fall (& self) -> bool { * self == CCCTL_01_ACOND_A :: CCCTL_01_ACOND_CC_TRIG_FALL } # [doc = "CC_TRIG_EDGE"] # [inline (always)] pub fn is_ccctl_01_acond_cc_trig_edge (& self) -> bool { * self == CCCTL_01_ACOND_A :: CCCTL_01_ACOND_CC_TRIG_EDGE } # [doc = "CC_TRIG_HIGH"] # [inline (always)] pub fn is_ccctl_01_acond_cc_trig_high (& self) -> bool { * self == CCCTL_01_ACOND_A :: CCCTL_01_ACOND_CC_TRIG_HIGH } } # [doc = "Field `CCCTL_01_ACOND` writer - Advance Condition. #br# Specifies the condition that generates an advance pulse. 6h-Fh = Reserved"] pub type CCCTL_01_ACOND_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 3 , O , CCCTL_01_ACOND_A > ; impl < 'a , REG , const O : u8 > CCCTL_01_ACOND_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "TIMCLK"] # [inline (always)] pub fn ccctl_01_acond_timclk (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_ACOND_A :: CCCTL_01_ACOND_TIMCLK) } # [doc = "CC_TRIG_RISE"] # [inline (always)] pub fn ccctl_01_acond_cc_trig_rise (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_ACOND_A :: CCCTL_01_ACOND_CC_TRIG_RISE) } # [doc = "CC_TRIG_FALL"] # [inline (always)] pub fn ccctl_01_acond_cc_trig_fall (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_ACOND_A :: CCCTL_01_ACOND_CC_TRIG_FALL) } # [doc = "CC_TRIG_EDGE"] # [inline (always)] pub fn ccctl_01_acond_cc_trig_edge (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_ACOND_A :: CCCTL_01_ACOND_CC_TRIG_EDGE) } # [doc = "CC_TRIG_HIGH"] # [inline (always)] pub fn ccctl_01_acond_cc_trig_high (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_ACOND_A :: CCCTL_01_ACOND_CC_TRIG_HIGH) } } # [doc = "Field `CCCTL_01_LCOND` reader - Load Condition. #br# Specifies the condition that generates a load pulse. 4h-Fh = Reserved"] pub type CCCTL_01_LCOND_R = crate :: FieldReader < CCCTL_01_LCOND_A > ; # [doc = "Load Condition. #br# Specifies the condition that generates a load pulse. 4h-Fh = Reserved\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum CCCTL_01_LCOND_A { # [doc = "1: CC_TRIG_RISE"] CCCTL_01_LCOND_CC_TRIG_RISE = 1 , # [doc = "2: CC_TRIG_FALL"] CCCTL_01_LCOND_CC_TRIG_FALL = 2 , # [doc = "3: CC_TRIG_EDGE"] CCCTL_01_LCOND_CC_TRIG_EDGE = 3 , } impl From < CCCTL_01_LCOND_A > for u8 { # [inline (always)] fn from (variant : CCCTL_01_LCOND_A) -> Self { variant as _ } } impl crate :: FieldSpec for CCCTL_01_LCOND_A { type Ux = u8 ; } impl CCCTL_01_LCOND_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < CCCTL_01_LCOND_A > { match self . bits { 1 => Some (CCCTL_01_LCOND_A :: CCCTL_01_LCOND_CC_TRIG_RISE) , 2 => Some (CCCTL_01_LCOND_A :: CCCTL_01_LCOND_CC_TRIG_FALL) , 3 => Some (CCCTL_01_LCOND_A :: CCCTL_01_LCOND_CC_TRIG_EDGE) , _ => None , } } # [doc = "CC_TRIG_RISE"] # [inline (always)] pub fn is_ccctl_01_lcond_cc_trig_rise (& self) -> bool { * self == CCCTL_01_LCOND_A :: CCCTL_01_LCOND_CC_TRIG_RISE } # [doc = "CC_TRIG_FALL"] # [inline (always)] pub fn is_ccctl_01_lcond_cc_trig_fall (& self) -> bool { * self == CCCTL_01_LCOND_A :: CCCTL_01_LCOND_CC_TRIG_FALL } # [doc = "CC_TRIG_EDGE"] # [inline (always)] pub fn is_ccctl_01_lcond_cc_trig_edge (& self) -> bool { * self == CCCTL_01_LCOND_A :: CCCTL_01_LCOND_CC_TRIG_EDGE } } # [doc = "Field `CCCTL_01_LCOND` writer - Load Condition. #br# Specifies the condition that generates a load pulse. 4h-Fh = Reserved"] pub type CCCTL_01_LCOND_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 3 , O , CCCTL_01_LCOND_A > ; impl < 'a , REG , const O : u8 > CCCTL_01_LCOND_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "CC_TRIG_RISE"] # [inline (always)] pub fn ccctl_01_lcond_cc_trig_rise (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_LCOND_A :: CCCTL_01_LCOND_CC_TRIG_RISE) } # [doc = "CC_TRIG_FALL"] # [inline (always)] pub fn ccctl_01_lcond_cc_trig_fall (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_LCOND_A :: CCCTL_01_LCOND_CC_TRIG_FALL) } # [doc = "CC_TRIG_EDGE"] # [inline (always)] pub fn ccctl_01_lcond_cc_trig_edge (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_LCOND_A :: CCCTL_01_LCOND_CC_TRIG_EDGE) } } # [doc = "Field `CCCTL_01_ZCOND` reader - Zero Condition. #br# This field specifies the condition that generates a zero pulse. 4h-Fh = Reserved"] pub type CCCTL_01_ZCOND_R = crate :: FieldReader < CCCTL_01_ZCOND_A > ; # [doc = "Zero Condition. #br# This field specifies the condition that generates a zero pulse. 4h-Fh = Reserved\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum CCCTL_01_ZCOND_A { # [doc = "1: CC_TRIG_RISE"] CCCTL_01_ZCOND_CC_TRIG_RISE = 1 , # [doc = "2: CC_TRIG_FALL"] CCCTL_01_ZCOND_CC_TRIG_FALL = 2 , # [doc = "3: CC_TRIG_EDGE"] CCCTL_01_ZCOND_CC_TRIG_EDGE = 3 , } impl From < CCCTL_01_ZCOND_A > for u8 { # [inline (always)] fn from (variant : CCCTL_01_ZCOND_A) -> Self { variant as _ } } impl crate :: FieldSpec for CCCTL_01_ZCOND_A { type Ux = u8 ; } impl CCCTL_01_ZCOND_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < CCCTL_01_ZCOND_A > { match self . bits { 1 => Some (CCCTL_01_ZCOND_A :: CCCTL_01_ZCOND_CC_TRIG_RISE) , 2 => Some (CCCTL_01_ZCOND_A :: CCCTL_01_ZCOND_CC_TRIG_FALL) , 3 => Some (CCCTL_01_ZCOND_A :: CCCTL_01_ZCOND_CC_TRIG_EDGE) , _ => None , } } # [doc = "CC_TRIG_RISE"] # [inline (always)] pub fn is_ccctl_01_zcond_cc_trig_rise (& self) -> bool { * self == CCCTL_01_ZCOND_A :: CCCTL_01_ZCOND_CC_TRIG_RISE } # [doc = "CC_TRIG_FALL"] # [inline (always)] pub fn is_ccctl_01_zcond_cc_trig_fall (& self) -> bool { * self == CCCTL_01_ZCOND_A :: CCCTL_01_ZCOND_CC_TRIG_FALL } # [doc = "CC_TRIG_EDGE"] # [inline (always)] pub fn is_ccctl_01_zcond_cc_trig_edge (& self) -> bool { * self == CCCTL_01_ZCOND_A :: CCCTL_01_ZCOND_CC_TRIG_EDGE } } # [doc = "Field `CCCTL_01_ZCOND` writer - Zero Condition. #br# This field specifies the condition that generates a zero pulse. 4h-Fh = Reserved"] pub type CCCTL_01_ZCOND_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 3 , O , CCCTL_01_ZCOND_A > ; impl < 'a , REG , const O : u8 > CCCTL_01_ZCOND_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "CC_TRIG_RISE"] # [inline (always)] pub fn ccctl_01_zcond_cc_trig_rise (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_ZCOND_A :: CCCTL_01_ZCOND_CC_TRIG_RISE) } # [doc = "CC_TRIG_FALL"] # [inline (always)] pub fn ccctl_01_zcond_cc_trig_fall (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_ZCOND_A :: CCCTL_01_ZCOND_CC_TRIG_FALL) } # [doc = "CC_TRIG_EDGE"] # [inline (always)] pub fn ccctl_01_zcond_cc_trig_edge (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_ZCOND_A :: CCCTL_01_ZCOND_CC_TRIG_EDGE) } } # [doc = "Field `CCCTL_01_COC` reader - Capture or Compare. #br# Specifies whether the corresponding CC register is used as a capture register or a compare register (never both)."] pub type CCCTL_01_COC_R = crate :: BitReader < CCCTL_01_COC_A > ; # [doc = "Capture or Compare. #br# Specifies whether the corresponding CC register is used as a capture register or a compare register (never both).\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CCCTL_01_COC_A { # [doc = "0: COMPARE"] CCCTL_01_COC_COMPARE = 0 , # [doc = "1: CAPTURE"] CCCTL_01_COC_CAPTURE = 1 , } impl From < CCCTL_01_COC_A > for bool { # [inline (always)] fn from (variant : CCCTL_01_COC_A) -> Self { variant as u8 != 0 } } impl CCCTL_01_COC_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CCCTL_01_COC_A { match self . bits { false => CCCTL_01_COC_A :: CCCTL_01_COC_COMPARE , true => CCCTL_01_COC_A :: CCCTL_01_COC_CAPTURE , } } # [doc = "COMPARE"] # [inline (always)] pub fn is_ccctl_01_coc_compare (& self) -> bool { * self == CCCTL_01_COC_A :: CCCTL_01_COC_COMPARE } # [doc = "CAPTURE"] # [inline (always)] pub fn is_ccctl_01_coc_capture (& self) -> bool { * self == CCCTL_01_COC_A :: CCCTL_01_COC_CAPTURE } } # [doc = "Field `CCCTL_01_COC` writer - Capture or Compare. #br# Specifies whether the corresponding CC register is used as a capture register or a compare register (never both)."] pub type CCCTL_01_COC_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CCCTL_01_COC_A > ; impl < 'a , REG , const O : u8 > CCCTL_01_COC_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "COMPARE"] # [inline (always)] pub fn ccctl_01_coc_compare (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_COC_A :: CCCTL_01_COC_COMPARE) } # [doc = "CAPTURE"] # [inline (always)] pub fn ccctl_01_coc_capture (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_COC_A :: CCCTL_01_COC_CAPTURE) } } # [doc = "Field `CCCTL_01_CCUPD` reader - Capture and Compare Update Method This field controls how updates to the pipelined capture and compare register are performed (when operating in compare mode, COC=0)."] pub type CCCTL_01_CCUPD_R = crate :: FieldReader < CCCTL_01_CCUPD_A > ; # [doc = "Capture and Compare Update Method This field controls how updates to the pipelined capture and compare register are performed (when operating in compare mode, COC=0).\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum CCCTL_01_CCUPD_A { # [doc = "0: IMMEDIATELY"] CCCTL_01_CCUPD_IMMEDIATELY = 0 , # [doc = "1: ZERO_EVT"] CCCTL_01_CCUPD_ZERO_EVT = 1 , # [doc = "2: COMPARE_DOWN_EVT"] CCCTL_01_CCUPD_COMPARE_DOWN_EVT = 2 , # [doc = "3: COMPARE_UP_EVT"] CCCTL_01_CCUPD_COMPARE_UP_EVT = 3 , # [doc = "4: ZERO_LOAD_EVT"] CCCTL_01_CCUPD_ZERO_LOAD_EVT = 4 , # [doc = "5: ZERO_RC_ZERO_EVT"] CCCTL_01_CCUPD_ZERO_RC_ZERO_EVT = 5 , # [doc = "6: TRIG"] CCCTL_01_CCUPD_TRIG = 6 , } impl From < CCCTL_01_CCUPD_A > for u8 { # [inline (always)] fn from (variant : CCCTL_01_CCUPD_A) -> Self { variant as _ } } impl crate :: FieldSpec for CCCTL_01_CCUPD_A { type Ux = u8 ; } impl CCCTL_01_CCUPD_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < CCCTL_01_CCUPD_A > { match self . bits { 0 => Some (CCCTL_01_CCUPD_A :: CCCTL_01_CCUPD_IMMEDIATELY) , 1 => Some (CCCTL_01_CCUPD_A :: CCCTL_01_CCUPD_ZERO_EVT) , 2 => Some (CCCTL_01_CCUPD_A :: CCCTL_01_CCUPD_COMPARE_DOWN_EVT) , 3 => Some (CCCTL_01_CCUPD_A :: CCCTL_01_CCUPD_COMPARE_UP_EVT) , 4 => Some (CCCTL_01_CCUPD_A :: CCCTL_01_CCUPD_ZERO_LOAD_EVT) , 5 => Some (CCCTL_01_CCUPD_A :: CCCTL_01_CCUPD_ZERO_RC_ZERO_EVT) , 6 => Some (CCCTL_01_CCUPD_A :: CCCTL_01_CCUPD_TRIG) , _ => None , } } # [doc = "IMMEDIATELY"] # [inline (always)] pub fn is_ccctl_01_ccupd_immediately (& self) -> bool { * self == CCCTL_01_CCUPD_A :: CCCTL_01_CCUPD_IMMEDIATELY } # [doc = "ZERO_EVT"] # [inline (always)] pub fn is_ccctl_01_ccupd_zero_evt (& self) -> bool { * self == CCCTL_01_CCUPD_A :: CCCTL_01_CCUPD_ZERO_EVT } # [doc = "COMPARE_DOWN_EVT"] # [inline (always)] pub fn is_ccctl_01_ccupd_compare_down_evt (& self) -> bool { * self == CCCTL_01_CCUPD_A :: CCCTL_01_CCUPD_COMPARE_DOWN_EVT } # [doc = "COMPARE_UP_EVT"] # [inline (always)] pub fn is_ccctl_01_ccupd_compare_up_evt (& self) -> bool { * self == CCCTL_01_CCUPD_A :: CCCTL_01_CCUPD_COMPARE_UP_EVT } # [doc = "ZERO_LOAD_EVT"] # [inline (always)] pub fn is_ccctl_01_ccupd_zero_load_evt (& self) -> bool { * self == CCCTL_01_CCUPD_A :: CCCTL_01_CCUPD_ZERO_LOAD_EVT } # [doc = "ZERO_RC_ZERO_EVT"] # [inline (always)] pub fn is_ccctl_01_ccupd_zero_rc_zero_evt (& self) -> bool { * self == CCCTL_01_CCUPD_A :: CCCTL_01_CCUPD_ZERO_RC_ZERO_EVT } # [doc = "TRIG"] # [inline (always)] pub fn is_ccctl_01_ccupd_trig (& self) -> bool { * self == CCCTL_01_CCUPD_A :: CCCTL_01_CCUPD_TRIG } } # [doc = "Field `CCCTL_01_CCUPD` writer - Capture and Compare Update Method This field controls how updates to the pipelined capture and compare register are performed (when operating in compare mode, COC=0)."] pub type CCCTL_01_CCUPD_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 3 , O , CCCTL_01_CCUPD_A > ; impl < 'a , REG , const O : u8 > CCCTL_01_CCUPD_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "IMMEDIATELY"] # [inline (always)] pub fn ccctl_01_ccupd_immediately (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CCUPD_A :: CCCTL_01_CCUPD_IMMEDIATELY) } # [doc = "ZERO_EVT"] # [inline (always)] pub fn ccctl_01_ccupd_zero_evt (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CCUPD_A :: CCCTL_01_CCUPD_ZERO_EVT) } # [doc = "COMPARE_DOWN_EVT"] # [inline (always)] pub fn ccctl_01_ccupd_compare_down_evt (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CCUPD_A :: CCCTL_01_CCUPD_COMPARE_DOWN_EVT) } # [doc = "COMPARE_UP_EVT"] # [inline (always)] pub fn ccctl_01_ccupd_compare_up_evt (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CCUPD_A :: CCCTL_01_CCUPD_COMPARE_UP_EVT) } # [doc = "ZERO_LOAD_EVT"] # [inline (always)] pub fn ccctl_01_ccupd_zero_load_evt (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CCUPD_A :: CCCTL_01_CCUPD_ZERO_LOAD_EVT) } # [doc = "ZERO_RC_ZERO_EVT"] # [inline (always)] pub fn ccctl_01_ccupd_zero_rc_zero_evt (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CCUPD_A :: CCCTL_01_CCUPD_ZERO_RC_ZERO_EVT) } # [doc = "TRIG"] # [inline (always)] pub fn ccctl_01_ccupd_trig (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CCUPD_A :: CCCTL_01_CCUPD_TRIG) } } # [doc = "Field `CCCTL_01_CC2SELU` reader - Selects the source second CCU event."] pub type CCCTL_01_CC2SELU_R = crate :: FieldReader < CCCTL_01_CC2SELU_A > ; # [doc = "Selects the source second CCU event.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum CCCTL_01_CC2SELU_A { # [doc = "0: SEL_CCU0"] CCCTL_01_CC2SELU_SEL_CCU0 = 0 , # [doc = "1: SEL_CCU1"] CCCTL_01_CC2SELU_SEL_CCU1 = 1 , # [doc = "2: SEL_CCU2"] CCCTL_01_CC2SELU_SEL_CCU2 = 2 , # [doc = "3: SEL_CCU3"] CCCTL_01_CC2SELU_SEL_CCU3 = 3 , # [doc = "4: SEL_CCU4"] CCCTL_01_CC2SELU_SEL_CCU4 = 4 , # [doc = "5: SEL_CCU5"] CCCTL_01_CC2SELU_SEL_CCU5 = 5 , } impl From < CCCTL_01_CC2SELU_A > for u8 { # [inline (always)] fn from (variant : CCCTL_01_CC2SELU_A) -> Self { variant as _ } } impl crate :: FieldSpec for CCCTL_01_CC2SELU_A { type Ux = u8 ; } impl CCCTL_01_CC2SELU_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < CCCTL_01_CC2SELU_A > { match self . bits { 0 => Some (CCCTL_01_CC2SELU_A :: CCCTL_01_CC2SELU_SEL_CCU0) , 1 => Some (CCCTL_01_CC2SELU_A :: CCCTL_01_CC2SELU_SEL_CCU1) , 2 => Some (CCCTL_01_CC2SELU_A :: CCCTL_01_CC2SELU_SEL_CCU2) , 3 => Some (CCCTL_01_CC2SELU_A :: CCCTL_01_CC2SELU_SEL_CCU3) , 4 => Some (CCCTL_01_CC2SELU_A :: CCCTL_01_CC2SELU_SEL_CCU4) , 5 => Some (CCCTL_01_CC2SELU_A :: CCCTL_01_CC2SELU_SEL_CCU5) , _ => None , } } # [doc = "SEL_CCU0"] # [inline (always)] pub fn is_ccctl_01_cc2selu_sel_ccu0 (& self) -> bool { * self == CCCTL_01_CC2SELU_A :: CCCTL_01_CC2SELU_SEL_CCU0 } # [doc = "SEL_CCU1"] # [inline (always)] pub fn is_ccctl_01_cc2selu_sel_ccu1 (& self) -> bool { * self == CCCTL_01_CC2SELU_A :: CCCTL_01_CC2SELU_SEL_CCU1 } # [doc = "SEL_CCU2"] # [inline (always)] pub fn is_ccctl_01_cc2selu_sel_ccu2 (& self) -> bool { * self == CCCTL_01_CC2SELU_A :: CCCTL_01_CC2SELU_SEL_CCU2 } # [doc = "SEL_CCU3"] # [inline (always)] pub fn is_ccctl_01_cc2selu_sel_ccu3 (& self) -> bool { * self == CCCTL_01_CC2SELU_A :: CCCTL_01_CC2SELU_SEL_CCU3 } # [doc = "SEL_CCU4"] # [inline (always)] pub fn is_ccctl_01_cc2selu_sel_ccu4 (& self) -> bool { * self == CCCTL_01_CC2SELU_A :: CCCTL_01_CC2SELU_SEL_CCU4 } # [doc = "SEL_CCU5"] # [inline (always)] pub fn is_ccctl_01_cc2selu_sel_ccu5 (& self) -> bool { * self == CCCTL_01_CC2SELU_A :: CCCTL_01_CC2SELU_SEL_CCU5 } } # [doc = "Field `CCCTL_01_CC2SELU` writer - Selects the source second CCU event."] pub type CCCTL_01_CC2SELU_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 3 , O , CCCTL_01_CC2SELU_A > ; impl < 'a , REG , const O : u8 > CCCTL_01_CC2SELU_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "SEL_CCU0"] # [inline (always)] pub fn ccctl_01_cc2selu_sel_ccu0 (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CC2SELU_A :: CCCTL_01_CC2SELU_SEL_CCU0) } # [doc = "SEL_CCU1"] # [inline (always)] pub fn ccctl_01_cc2selu_sel_ccu1 (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CC2SELU_A :: CCCTL_01_CC2SELU_SEL_CCU1) } # [doc = "SEL_CCU2"] # [inline (always)] pub fn ccctl_01_cc2selu_sel_ccu2 (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CC2SELU_A :: CCCTL_01_CC2SELU_SEL_CCU2) } # [doc = "SEL_CCU3"] # [inline (always)] pub fn ccctl_01_cc2selu_sel_ccu3 (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CC2SELU_A :: CCCTL_01_CC2SELU_SEL_CCU3) } # [doc = "SEL_CCU4"] # [inline (always)] pub fn ccctl_01_cc2selu_sel_ccu4 (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CC2SELU_A :: CCCTL_01_CC2SELU_SEL_CCU4) } # [doc = "SEL_CCU5"] # [inline (always)] pub fn ccctl_01_cc2selu_sel_ccu5 (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CC2SELU_A :: CCCTL_01_CC2SELU_SEL_CCU5) } } # [doc = "Field `CCCTL_01_CCACTUPD` reader - CCACT shadow register Update Method This field controls how updates to the CCCACT shadow register are performed"] pub type CCCTL_01_CCACTUPD_R = crate :: FieldReader < CCCTL_01_CCACTUPD_A > ; # [doc = "CCACT shadow register Update Method This field controls how updates to the CCCACT shadow register are performed\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum CCCTL_01_CCACTUPD_A { # [doc = "0: IMMEDIATELY"] CCCTL_01_CCACTUPD_IMMEDIATELY = 0 , # [doc = "1: ZERO_EVT"] CCCTL_01_CCACTUPD_ZERO_EVT = 1 , # [doc = "2: COMPARE_DOWN_EVT"] CCCTL_01_CCACTUPD_COMPARE_DOWN_EVT = 2 , # [doc = "3: COMPARE_UP_EVT"] CCCTL_01_CCACTUPD_COMPARE_UP_EVT = 3 , # [doc = "4: ZERO_LOAD_EVT"] CCCTL_01_CCACTUPD_ZERO_LOAD_EVT = 4 , # [doc = "5: ZERO_RC_ZERO_EVT"] CCCTL_01_CCACTUPD_ZERO_RC_ZERO_EVT = 5 , # [doc = "6: TRIG"] CCCTL_01_CCACTUPD_TRIG = 6 , } impl From < CCCTL_01_CCACTUPD_A > for u8 { # [inline (always)] fn from (variant : CCCTL_01_CCACTUPD_A) -> Self { variant as _ } } impl crate :: FieldSpec for CCCTL_01_CCACTUPD_A { type Ux = u8 ; } impl CCCTL_01_CCACTUPD_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < CCCTL_01_CCACTUPD_A > { match self . bits { 0 => Some (CCCTL_01_CCACTUPD_A :: CCCTL_01_CCACTUPD_IMMEDIATELY) , 1 => Some (CCCTL_01_CCACTUPD_A :: CCCTL_01_CCACTUPD_ZERO_EVT) , 2 => Some (CCCTL_01_CCACTUPD_A :: CCCTL_01_CCACTUPD_COMPARE_DOWN_EVT) , 3 => Some (CCCTL_01_CCACTUPD_A :: CCCTL_01_CCACTUPD_COMPARE_UP_EVT) , 4 => Some (CCCTL_01_CCACTUPD_A :: CCCTL_01_CCACTUPD_ZERO_LOAD_EVT) , 5 => Some (CCCTL_01_CCACTUPD_A :: CCCTL_01_CCACTUPD_ZERO_RC_ZERO_EVT) , 6 => Some (CCCTL_01_CCACTUPD_A :: CCCTL_01_CCACTUPD_TRIG) , _ => None , } } # [doc = "IMMEDIATELY"] # [inline (always)] pub fn is_ccctl_01_ccactupd_immediately (& self) -> bool { * self == CCCTL_01_CCACTUPD_A :: CCCTL_01_CCACTUPD_IMMEDIATELY } # [doc = "ZERO_EVT"] # [inline (always)] pub fn is_ccctl_01_ccactupd_zero_evt (& self) -> bool { * self == CCCTL_01_CCACTUPD_A :: CCCTL_01_CCACTUPD_ZERO_EVT } # [doc = "COMPARE_DOWN_EVT"] # [inline (always)] pub fn is_ccctl_01_ccactupd_compare_down_evt (& self) -> bool { * self == CCCTL_01_CCACTUPD_A :: CCCTL_01_CCACTUPD_COMPARE_DOWN_EVT } # [doc = "COMPARE_UP_EVT"] # [inline (always)] pub fn is_ccctl_01_ccactupd_compare_up_evt (& self) -> bool { * self == CCCTL_01_CCACTUPD_A :: CCCTL_01_CCACTUPD_COMPARE_UP_EVT } # [doc = "ZERO_LOAD_EVT"] # [inline (always)] pub fn is_ccctl_01_ccactupd_zero_load_evt (& self) -> bool { * self == CCCTL_01_CCACTUPD_A :: CCCTL_01_CCACTUPD_ZERO_LOAD_EVT } # [doc = "ZERO_RC_ZERO_EVT"] # [inline (always)] pub fn is_ccctl_01_ccactupd_zero_rc_zero_evt (& self) -> bool { * self == CCCTL_01_CCACTUPD_A :: CCCTL_01_CCACTUPD_ZERO_RC_ZERO_EVT } # [doc = "TRIG"] # [inline (always)] pub fn is_ccctl_01_ccactupd_trig (& self) -> bool { * self == CCCTL_01_CCACTUPD_A :: CCCTL_01_CCACTUPD_TRIG } } # [doc = "Field `CCCTL_01_CCACTUPD` writer - CCACT shadow register Update Method This field controls how updates to the CCCACT shadow register are performed"] pub type CCCTL_01_CCACTUPD_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 3 , O , CCCTL_01_CCACTUPD_A > ; impl < 'a , REG , const O : u8 > CCCTL_01_CCACTUPD_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "IMMEDIATELY"] # [inline (always)] pub fn ccctl_01_ccactupd_immediately (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CCACTUPD_A :: CCCTL_01_CCACTUPD_IMMEDIATELY) } # [doc = "ZERO_EVT"] # [inline (always)] pub fn ccctl_01_ccactupd_zero_evt (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CCACTUPD_A :: CCCTL_01_CCACTUPD_ZERO_EVT) } # [doc = "COMPARE_DOWN_EVT"] # [inline (always)] pub fn ccctl_01_ccactupd_compare_down_evt (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CCACTUPD_A :: CCCTL_01_CCACTUPD_COMPARE_DOWN_EVT) } # [doc = "COMPARE_UP_EVT"] # [inline (always)] pub fn ccctl_01_ccactupd_compare_up_evt (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CCACTUPD_A :: CCCTL_01_CCACTUPD_COMPARE_UP_EVT) } # [doc = "ZERO_LOAD_EVT"] # [inline (always)] pub fn ccctl_01_ccactupd_zero_load_evt (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CCACTUPD_A :: CCCTL_01_CCACTUPD_ZERO_LOAD_EVT) } # [doc = "ZERO_RC_ZERO_EVT"] # [inline (always)] pub fn ccctl_01_ccactupd_zero_rc_zero_evt (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CCACTUPD_A :: CCCTL_01_CCACTUPD_ZERO_RC_ZERO_EVT) } # [doc = "TRIG"] # [inline (always)] pub fn ccctl_01_ccactupd_trig (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CCACTUPD_A :: CCCTL_01_CCACTUPD_TRIG) } } # [doc = "Field `CCCTL_01_CC2SELD` reader - Selects the source second CCD event."] pub type CCCTL_01_CC2SELD_R = crate :: FieldReader < CCCTL_01_CC2SELD_A > ; # [doc = "Selects the source second CCD event.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum CCCTL_01_CC2SELD_A { # [doc = "0: SEL_CCD0"] CCCTL_01_CC2SELD_SEL_CCD0 = 0 , # [doc = "1: SEL_CCD1"] CCCTL_01_CC2SELD_SEL_CCD1 = 1 , # [doc = "2: SEL_CCD2"] CCCTL_01_CC2SELD_SEL_CCD2 = 2 , # [doc = "3: SEL_CCD3"] CCCTL_01_CC2SELD_SEL_CCD3 = 3 , # [doc = "4: SEL_CCD4"] CCCTL_01_CC2SELD_SEL_CCD4 = 4 , # [doc = "5: SEL_CCD5"] CCCTL_01_CC2SELD_SEL_CCD5 = 5 , } impl From < CCCTL_01_CC2SELD_A > for u8 { # [inline (always)] fn from (variant : CCCTL_01_CC2SELD_A) -> Self { variant as _ } } impl crate :: FieldSpec for CCCTL_01_CC2SELD_A { type Ux = u8 ; } impl CCCTL_01_CC2SELD_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < CCCTL_01_CC2SELD_A > { match self . bits { 0 => Some (CCCTL_01_CC2SELD_A :: CCCTL_01_CC2SELD_SEL_CCD0) , 1 => Some (CCCTL_01_CC2SELD_A :: CCCTL_01_CC2SELD_SEL_CCD1) , 2 => Some (CCCTL_01_CC2SELD_A :: CCCTL_01_CC2SELD_SEL_CCD2) , 3 => Some (CCCTL_01_CC2SELD_A :: CCCTL_01_CC2SELD_SEL_CCD3) , 4 => Some (CCCTL_01_CC2SELD_A :: CCCTL_01_CC2SELD_SEL_CCD4) , 5 => Some (CCCTL_01_CC2SELD_A :: CCCTL_01_CC2SELD_SEL_CCD5) , _ => None , } } # [doc = "SEL_CCD0"] # [inline (always)] pub fn is_ccctl_01_cc2seld_sel_ccd0 (& self) -> bool { * self == CCCTL_01_CC2SELD_A :: CCCTL_01_CC2SELD_SEL_CCD0 } # [doc = "SEL_CCD1"] # [inline (always)] pub fn is_ccctl_01_cc2seld_sel_ccd1 (& self) -> bool { * self == CCCTL_01_CC2SELD_A :: CCCTL_01_CC2SELD_SEL_CCD1 } # [doc = "SEL_CCD2"] # [inline (always)] pub fn is_ccctl_01_cc2seld_sel_ccd2 (& self) -> bool { * self == CCCTL_01_CC2SELD_A :: CCCTL_01_CC2SELD_SEL_CCD2 } # [doc = "SEL_CCD3"] # [inline (always)] pub fn is_ccctl_01_cc2seld_sel_ccd3 (& self) -> bool { * self == CCCTL_01_CC2SELD_A :: CCCTL_01_CC2SELD_SEL_CCD3 } # [doc = "SEL_CCD4"] # [inline (always)] pub fn is_ccctl_01_cc2seld_sel_ccd4 (& self) -> bool { * self == CCCTL_01_CC2SELD_A :: CCCTL_01_CC2SELD_SEL_CCD4 } # [doc = "SEL_CCD5"] # [inline (always)] pub fn is_ccctl_01_cc2seld_sel_ccd5 (& self) -> bool { * self == CCCTL_01_CC2SELD_A :: CCCTL_01_CC2SELD_SEL_CCD5 } } # [doc = "Field `CCCTL_01_CC2SELD` writer - Selects the source second CCD event."] pub type CCCTL_01_CC2SELD_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 3 , O , CCCTL_01_CC2SELD_A > ; impl < 'a , REG , const O : u8 > CCCTL_01_CC2SELD_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "SEL_CCD0"] # [inline (always)] pub fn ccctl_01_cc2seld_sel_ccd0 (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CC2SELD_A :: CCCTL_01_CC2SELD_SEL_CCD0) } # [doc = "SEL_CCD1"] # [inline (always)] pub fn ccctl_01_cc2seld_sel_ccd1 (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CC2SELD_A :: CCCTL_01_CC2SELD_SEL_CCD1) } # [doc = "SEL_CCD2"] # [inline (always)] pub fn ccctl_01_cc2seld_sel_ccd2 (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CC2SELD_A :: CCCTL_01_CC2SELD_SEL_CCD2) } # [doc = "SEL_CCD3"] # [inline (always)] pub fn ccctl_01_cc2seld_sel_ccd3 (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CC2SELD_A :: CCCTL_01_CC2SELD_SEL_CCD3) } # [doc = "SEL_CCD4"] # [inline (always)] pub fn ccctl_01_cc2seld_sel_ccd4 (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CC2SELD_A :: CCCTL_01_CC2SELD_SEL_CCD4) } # [doc = "SEL_CCD5"] # [inline (always)] pub fn ccctl_01_cc2seld_sel_ccd5 (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CC2SELD_A :: CCCTL_01_CC2SELD_SEL_CCD5) } } impl R { # [doc = "Bits 0:2 - Capture Condition. #br# Specifies the condition that generates a capture pulse. 4h-Fh = Reserved"] # [inline (always)] pub fn ccctl_01_ccond (& self) -> CCCTL_01_CCOND_R { CCCTL_01_CCOND_R :: new ((self . bits & 7) as u8) } # [doc = "Bits 4:6 - Advance Condition. #br# Specifies the condition that generates an advance pulse. 6h-Fh = Reserved"] # [inline (always)] pub fn ccctl_01_acond (& self) -> CCCTL_01_ACOND_R { CCCTL_01_ACOND_R :: new (((self . bits >> 4) & 7) as u8) } # [doc = "Bits 8:10 - Load Condition. #br# Specifies the condition that generates a load pulse. 4h-Fh = Reserved"] # [inline (always)] pub fn ccctl_01_lcond (& self) -> CCCTL_01_LCOND_R { CCCTL_01_LCOND_R :: new (((self . bits >> 8) & 7) as u8) } # [doc = "Bits 12:14 - Zero Condition. #br# This field specifies the condition that generates a zero pulse. 4h-Fh = Reserved"] # [inline (always)] pub fn ccctl_01_zcond (& self) -> CCCTL_01_ZCOND_R { CCCTL_01_ZCOND_R :: new (((self . bits >> 12) & 7) as u8) } # [doc = "Bit 17 - Capture or Compare. #br# Specifies whether the corresponding CC register is used as a capture register or a compare register (never both)."] # [inline (always)] pub fn ccctl_01_coc (& self) -> CCCTL_01_COC_R { CCCTL_01_COC_R :: new (((self . bits >> 17) & 1) != 0) } # [doc = "Bits 18:20 - Capture and Compare Update Method This field controls how updates to the pipelined capture and compare register are performed (when operating in compare mode, COC=0)."] # [inline (always)] pub fn ccctl_01_ccupd (& self) -> CCCTL_01_CCUPD_R { CCCTL_01_CCUPD_R :: new (((self . bits >> 18) & 7) as u8) } # [doc = "Bits 22:24 - Selects the source second CCU event."] # [inline (always)] pub fn ccctl_01_cc2selu (& self) -> CCCTL_01_CC2SELU_R { CCCTL_01_CC2SELU_R :: new (((self . bits >> 22) & 7) as u8) } # [doc = "Bits 26:28 - CCACT shadow register Update Method This field controls how updates to the CCCACT shadow register are performed"] # [inline (always)] pub fn ccctl_01_ccactupd (& self) -> CCCTL_01_CCACTUPD_R { CCCTL_01_CCACTUPD_R :: new (((self . bits >> 26) & 7) as u8) } # [doc = "Bits 29:31 - Selects the source second CCD event."] # [inline (always)] pub fn ccctl_01_cc2seld (& self) -> CCCTL_01_CC2SELD_R { CCCTL_01_CC2SELD_R :: new (((self . bits >> 29) & 7) as u8) } } impl W { # [doc = "Bits 0:2 - Capture Condition. #br# Specifies the condition that generates a capture pulse. 4h-Fh = Reserved"] # [inline (always)] # [must_use] pub fn ccctl_01_ccond (& mut self) -> CCCTL_01_CCOND_W < CCCTL_01_SPEC , 0 > { CCCTL_01_CCOND_W :: new (self) } # [doc = "Bits 4:6 - Advance Condition. #br# Specifies the condition that generates an advance pulse. 6h-Fh = Reserved"] # [inline (always)] # [must_use] pub fn ccctl_01_acond (& mut self) -> CCCTL_01_ACOND_W < CCCTL_01_SPEC , 4 > { CCCTL_01_ACOND_W :: new (self) } # [doc = "Bits 8:10 - Load Condition. #br# Specifies the condition that generates a load pulse. 4h-Fh = Reserved"] # [inline (always)] # [must_use] pub fn ccctl_01_lcond (& mut self) -> CCCTL_01_LCOND_W < CCCTL_01_SPEC , 8 > { CCCTL_01_LCOND_W :: new (self) } # [doc = "Bits 12:14 - Zero Condition. #br# This field specifies the condition that generates a zero pulse. 4h-Fh = Reserved"] # [inline (always)] # [must_use] pub fn ccctl_01_zcond (& mut self) -> CCCTL_01_ZCOND_W <'_, CCCTL_01_SPEC , 12 > { CCCTL_01_ZCOND_W :: new (self) } # [doc = "Bit 17 - Capture or Compare. #br# Specifies whether the corresponding CC register is used as a capture register or a compare register (never both)."] # [inline (always)] # [must_use] pub fn ccctl_01_coc (& mut self) -> CCCTL_01_COC_W < CCCTL_01_SPEC , 17 > { CCCTL_01_COC_W :: new (self) } # [doc = "Bits 18:20 - Capture and Compare Update Method This field controls how updates to the pipelined capture and compare register are performed (when operating in compare mode, COC=0)."] # [inline (always)] # [must_use] pub fn ccctl_01_ccupd (& mut self) -> CCCTL_01_CCUPD_W < CCCTL_01_SPEC , 18 > { CCCTL_01_CCUPD_W :: new (self) } # [doc = "Bits 22:24 - Selects the source second CCU event."] # [inline (always)] # [must_use] pub fn ccctl_01_cc2selu (& mut self) -> CCCTL_01_CC2SELU_W < CCCTL_01_SPEC , 22 > { CCCTL_01_CC2SELU_W :: new (self) } # [doc = "Bits 26:28 - CCACT shadow register Update Method This field controls how updates to the CCCACT shadow register are performed"] # [inline (always)] # [must_use] pub fn ccctl_01_ccactupd (& mut self) -> CCCTL_01_CCACTUPD_W < CCCTL_01_SPEC , 26 > { CCCTL_01_CCACTUPD_W :: new (self) } # [doc = "Bits 29:31 - Selects the source second CCD event."] # [inline (always)] # [must_use] pub fn ccctl_01_cc2seld (& mut self) -> CCCTL_01_CC2SELD_W < CCCTL_01_SPEC , 29 > { CCCTL_01_CC2SELD_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Capture or Compare Control Registers\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ccctl_01::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ccctl_01::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CCCTL_01_SPEC ; impl crate :: RegisterSpec for CCCTL_01_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`ccctl_01::R`](R) reader structure"] impl crate :: Readable for CCCTL_01_SPEC { } # [doc = "`write(|w| ..)` method takes [`ccctl_01::W`](W) writer structure"] impl crate :: Writable for CCCTL_01_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets CCCTL_01[%s] [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/uart0/rstctl.rs:1:3649 [INFO] [stdout] | [INFO] [stdout] 1 | ...t_use] pub fn rstctl_key (& mut self) -> RSTCTL_KEY_W < RSTCTL_SPEC , 24 > { RSTCTL_KEY_W :: new (self) } # [doc = r" Writes raw bits ... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `RSTCTL` writer"] pub type W = crate :: W < RSTCTL_SPEC > ; # [doc = "Assert reset to the peripheral\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum RSTCTL_RESETASSERT_AW { # [doc = "0: NOP"] RSTCTL_RESETASSERT_NOP = 0 , # [doc = "1: ASSERT"] RSTCTL_RESETASSERT_ASSERT = 1 , } impl From < RSTCTL_RESETASSERT_AW > for bool { # [inline (always)] fn from (variant : RSTCTL_RESETASSERT_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `RSTCTL_RESETASSERT` writer - Assert reset to the peripheral"] pub type RSTCTL_RESETASSERT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , RSTCTL_RESETASSERT_AW > ; impl < 'a , REG , const O : u8 > RSTCTL_RESETASSERT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NOP"] # [inline (always)] pub fn rstctl_resetassert_nop (self) -> & 'a mut crate :: W < REG > { self . variant (RSTCTL_RESETASSERT_AW :: RSTCTL_RESETASSERT_NOP) } # [doc = "ASSERT"] # [inline (always)] pub fn rstctl_resetassert_assert (self) -> & 'a mut crate :: W < REG > { self . variant (RSTCTL_RESETASSERT_AW :: RSTCTL_RESETASSERT_ASSERT) } } # [doc = "Clear the RESETSTKY bit in the STAT register\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum RSTCTL_RESETSTKYCLR_AW { # [doc = "0: NOP"] RSTCTL_RESETSTKYCLR_NOP = 0 , # [doc = "1: CLR"] RSTCTL_RESETSTKYCLR_CLR = 1 , } impl From < RSTCTL_RESETSTKYCLR_AW > for bool { # [inline (always)] fn from (variant : RSTCTL_RESETSTKYCLR_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `RSTCTL_RESETSTKYCLR` writer - Clear the RESETSTKY bit in the STAT register"] pub type RSTCTL_RESETSTKYCLR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , RSTCTL_RESETSTKYCLR_AW > ; impl < 'a , REG , const O : u8 > RSTCTL_RESETSTKYCLR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NOP"] # [inline (always)] pub fn rstctl_resetstkyclr_nop (self) -> & 'a mut crate :: W < REG > { self . variant (RSTCTL_RESETSTKYCLR_AW :: RSTCTL_RESETSTKYCLR_NOP) } # [doc = "CLR"] # [inline (always)] pub fn rstctl_resetstkyclr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (RSTCTL_RESETSTKYCLR_AW :: RSTCTL_RESETSTKYCLR_CLR) } } # [doc = "Unlock key\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum RSTCTL_KEY_AW { # [doc = "177: _TO_UNLOCK_W_"] RSTCTL_KEY_UNLOCK_W = 177 , } impl From < RSTCTL_KEY_AW > for u8 { # [inline (always)] fn from (variant : RSTCTL_KEY_AW) -> Self { variant as _ } } impl crate :: FieldSpec for RSTCTL_KEY_AW { type Ux = u8 ; } # [doc = "Field `RSTCTL_KEY` writer - Unlock key"] pub type RSTCTL_KEY_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 8 , O , RSTCTL_KEY_AW > ; impl < 'a , REG , const O : u8 > RSTCTL_KEY_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "_TO_UNLOCK_W_"] # [inline (always)] pub fn rstctl_key_unlock_w (self) -> & 'a mut crate :: W < REG > { self . variant (RSTCTL_KEY_AW :: RSTCTL_KEY_UNLOCK_W) } } impl W { # [doc = "Bit 0 - Assert reset to the peripheral"] # [inline (always)] # [must_use] pub fn rstctl_resetassert (& mut self) -> RSTCTL_RESETASSERT_W < RSTCTL_SPEC , 0 > { RSTCTL_RESETASSERT_W :: new (self) } # [doc = "Bit 1 - Clear the RESETSTKY bit in the STAT register"] # [inline (always)] # [must_use] pub fn rstctl_resetstkyclr (& mut self) -> RSTCTL_RESETSTKYCLR_W < RSTCTL_SPEC , 1 > { RSTCTL_RESETSTKYCLR_W :: new (self) } # [doc = "Bits 24:31 - Unlock key"] # [inline (always)] # [must_use] pub fn rstctl_key (& mut self) -> RSTCTL_KEY_W <'_, RSTCTL_SPEC , 24 > { RSTCTL_KEY_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Reset Control\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rstctl::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct RSTCTL_SPEC ; impl crate :: RegisterSpec for RSTCTL_SPEC { type Ux = u32 ; } # [doc = "`write(|w| ..)` method takes [`rstctl::W`](W) writer structure"] impl crate :: Writable for RSTCTL_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets RSTCTL to value 0"] impl crate :: Resettable for RSTCTL_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/opa0/rstctl.rs:1:3243 [INFO] [stdout] | [INFO] [stdout] 1 | ...fn rstctl_resetassert (& mut self) -> RSTCTL_RESETASSERT_W < RSTCTL_SPEC , 0 > { RSTCTL_RESETASSERT_W :: new (self) } # [doc = "Bit 1 ... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `RSTCTL` writer"] pub type W = crate :: W < RSTCTL_SPEC > ; # [doc = "Assert reset to the peripheral\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum RSTCTL_RESETASSERT_AW { # [doc = "0: NOP"] RSTCTL_RESETASSERT_NOP = 0 , # [doc = "1: ASSERT"] RSTCTL_RESETASSERT_ASSERT = 1 , } impl From < RSTCTL_RESETASSERT_AW > for bool { # [inline (always)] fn from (variant : RSTCTL_RESETASSERT_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `RSTCTL_RESETASSERT` writer - Assert reset to the peripheral"] pub type RSTCTL_RESETASSERT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , RSTCTL_RESETASSERT_AW > ; impl < 'a , REG , const O : u8 > RSTCTL_RESETASSERT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NOP"] # [inline (always)] pub fn rstctl_resetassert_nop (self) -> & 'a mut crate :: W < REG > { self . variant (RSTCTL_RESETASSERT_AW :: RSTCTL_RESETASSERT_NOP) } # [doc = "ASSERT"] # [inline (always)] pub fn rstctl_resetassert_assert (self) -> & 'a mut crate :: W < REG > { self . variant (RSTCTL_RESETASSERT_AW :: RSTCTL_RESETASSERT_ASSERT) } } # [doc = "Clear the RESETSTKY bit in the STAT register\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum RSTCTL_RESETSTKYCLR_AW { # [doc = "0: NOP"] RSTCTL_RESETSTKYCLR_NOP = 0 , # [doc = "1: CLR"] RSTCTL_RESETSTKYCLR_CLR = 1 , } impl From < RSTCTL_RESETSTKYCLR_AW > for bool { # [inline (always)] fn from (variant : RSTCTL_RESETSTKYCLR_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `RSTCTL_RESETSTKYCLR` writer - Clear the RESETSTKY bit in the STAT register"] pub type RSTCTL_RESETSTKYCLR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , RSTCTL_RESETSTKYCLR_AW > ; impl < 'a , REG , const O : u8 > RSTCTL_RESETSTKYCLR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NOP"] # [inline (always)] pub fn rstctl_resetstkyclr_nop (self) -> & 'a mut crate :: W < REG > { self . variant (RSTCTL_RESETSTKYCLR_AW :: RSTCTL_RESETSTKYCLR_NOP) } # [doc = "CLR"] # [inline (always)] pub fn rstctl_resetstkyclr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (RSTCTL_RESETSTKYCLR_AW :: RSTCTL_RESETSTKYCLR_CLR) } } # [doc = "Unlock key\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum RSTCTL_KEY_AW { # [doc = "177: _TO_UNLOCK_W_"] RSTCTL_KEY_UNLOCK_W = 177 , } impl From < RSTCTL_KEY_AW > for u8 { # [inline (always)] fn from (variant : RSTCTL_KEY_AW) -> Self { variant as _ } } impl crate :: FieldSpec for RSTCTL_KEY_AW { type Ux = u8 ; } # [doc = "Field `RSTCTL_KEY` writer - Unlock key"] pub type RSTCTL_KEY_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 8 , O , RSTCTL_KEY_AW > ; impl < 'a , REG , const O : u8 > RSTCTL_KEY_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "_TO_UNLOCK_W_"] # [inline (always)] pub fn rstctl_key_unlock_w (self) -> & 'a mut crate :: W < REG > { self . variant (RSTCTL_KEY_AW :: RSTCTL_KEY_UNLOCK_W) } } impl W { # [doc = "Bit 0 - Assert reset to the peripheral"] # [inline (always)] # [must_use] pub fn rstctl_resetassert (& mut self) -> RSTCTL_RESETASSERT_W <'_, RSTCTL_SPEC , 0 > { RSTCTL_RESETASSERT_W :: new (self) } # [doc = "Bit 1 - Clear the RESETSTKY bit in the STAT register"] # [inline (always)] # [must_use] pub fn rstctl_resetstkyclr (& mut self) -> RSTCTL_RESETSTKYCLR_W < RSTCTL_SPEC , 1 > { RSTCTL_RESETSTKYCLR_W :: new (self) } # [doc = "Bits 24:31 - Unlock key"] # [inline (always)] # [must_use] pub fn rstctl_key (& mut self) -> RSTCTL_KEY_W < RSTCTL_SPEC , 24 > { RSTCTL_KEY_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Reset Control\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rstctl::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct RSTCTL_SPEC ; impl crate :: RegisterSpec for RSTCTL_SPEC { type Ux = u32 ; } # [doc = "`write(|w| ..)` method takes [`rstctl::W`](W) writer structure"] impl crate :: Writable for RSTCTL_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets RSTCTL to value 0"] impl crate :: Resettable for RSTCTL_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/sysctl/iset.rs:1:2459 [INFO] [stdout] | [INFO] [stdout] 1 | ...e] pub fn iset_anaclkerr (& mut self) -> ISET_ANACLKERR_W < ISET_SPEC , 1 > { ISET_ANACLKERR_W :: new (self) } # [doc = r" Writes raw ... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `ISET` writer"] pub type W = crate :: W < ISET_SPEC > ; # [doc = "Set the LFOSCGOOD interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum ISET_LFOSCGOOD_AW { # [doc = "0: NO_EFFECT"] ISET_LFOSCGOOD_NO_EFFECT = 0 , # [doc = "1: SET"] ISET_LFOSCGOOD_SET = 1 , } impl From < ISET_LFOSCGOOD_AW > for bool { # [inline (always)] fn from (variant : ISET_LFOSCGOOD_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `ISET_LFOSCGOOD` writer - Set the LFOSCGOOD interrupt."] pub type ISET_LFOSCGOOD_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , ISET_LFOSCGOOD_AW > ; impl < 'a , REG , const O : u8 > ISET_LFOSCGOOD_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn iset_lfoscgood_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (ISET_LFOSCGOOD_AW :: ISET_LFOSCGOOD_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn iset_lfoscgood_set (self) -> & 'a mut crate :: W < REG > { self . variant (ISET_LFOSCGOOD_AW :: ISET_LFOSCGOOD_SET) } } # [doc = "Analog Clocking Consistency Error\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum ISET_ANACLKERR_AW { # [doc = "0: NO_EFFECT"] ISET_ANACLKERR_NO_EFFECT = 0 , # [doc = "1: SET"] ISET_ANACLKERR_SET = 1 , } impl From < ISET_ANACLKERR_AW > for bool { # [inline (always)] fn from (variant : ISET_ANACLKERR_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `ISET_ANACLKERR` writer - Analog Clocking Consistency Error"] pub type ISET_ANACLKERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , ISET_ANACLKERR_AW > ; impl < 'a , REG , const O : u8 > ISET_ANACLKERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn iset_anaclkerr_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (ISET_ANACLKERR_AW :: ISET_ANACLKERR_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn iset_anaclkerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (ISET_ANACLKERR_AW :: ISET_ANACLKERR_SET) } } impl W { # [doc = "Bit 0 - Set the LFOSCGOOD interrupt."] # [inline (always)] # [must_use] pub fn iset_lfoscgood (& mut self) -> ISET_LFOSCGOOD_W < ISET_SPEC , 0 > { ISET_LFOSCGOOD_W :: new (self) } # [doc = "Bit 1 - Analog Clocking Consistency Error"] # [inline (always)] # [must_use] pub fn iset_anaclkerr (& mut self) -> ISET_ANACLKERR_W <'_, ISET_SPEC , 1 > { ISET_ANACLKERR_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "SYSCTL interrupt set\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`iset::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct ISET_SPEC ; impl crate :: RegisterSpec for ISET_SPEC { type Ux = u32 ; } # [doc = "`write(|w| ..)` method takes [`iset::W`](W) writer structure"] impl crate :: Writable for ISET_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets ISET to value 0"] impl crate :: Resettable for ISET_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/i2c1/gfctl.rs:1:12958 [INFO] [stdout] | [INFO] [stdout] 1 | ...t_use] pub fn gfctl_agfen (& mut self) -> GFCTL_AGFEN_W < GFCTL_SPEC , 8 > { GFCTL_AGFEN_W :: new (self) } # [doc = "Bits 9:10 - Analo... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `GFCTL` reader"] pub type R = crate :: R < GFCTL_SPEC > ; # [doc = "Register `GFCTL` writer"] pub type W = crate :: W < GFCTL_SPEC > ; # [doc = "Field `GFCTL_DGFSEL` reader - Glitch Suppression Pulse Width This field controls the pulse width select for glitch suppression on the SCL and SDA lines. The following values are the glitch suppression values in terms of functional clocks. (Core Domain only)"] pub type GFCTL_DGFSEL_R = crate :: FieldReader < GFCTL_DGFSEL_A > ; # [doc = "Glitch Suppression Pulse Width This field controls the pulse width select for glitch suppression on the SCL and SDA lines. The following values are the glitch suppression values in terms of functional clocks. (Core Domain only)\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum GFCTL_DGFSEL_A { # [doc = "0: DISABLED"] GFCTL_DGFSEL_DISABLED = 0 , # [doc = "1: CLK_1"] GFCTL_DGFSEL_CLK_1 = 1 , # [doc = "2: CLK_2"] GFCTL_DGFSEL_CLK_2 = 2 , # [doc = "3: CLK_3"] GFCTL_DGFSEL_CLK_3 = 3 , # [doc = "4: CLK_4"] GFCTL_DGFSEL_CLK_4 = 4 , # [doc = "5: CLK_8"] GFCTL_DGFSEL_CLK_8 = 5 , # [doc = "6: CLK_16"] GFCTL_DGFSEL_CLK_16 = 6 , # [doc = "7: CLK_31"] GFCTL_DGFSEL_CLK_31 = 7 , } impl From < GFCTL_DGFSEL_A > for u8 { # [inline (always)] fn from (variant : GFCTL_DGFSEL_A) -> Self { variant as _ } } impl crate :: FieldSpec for GFCTL_DGFSEL_A { type Ux = u8 ; } impl GFCTL_DGFSEL_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> GFCTL_DGFSEL_A { match self . bits { 0 => GFCTL_DGFSEL_A :: GFCTL_DGFSEL_DISABLED , 1 => GFCTL_DGFSEL_A :: GFCTL_DGFSEL_CLK_1 , 2 => GFCTL_DGFSEL_A :: GFCTL_DGFSEL_CLK_2 , 3 => GFCTL_DGFSEL_A :: GFCTL_DGFSEL_CLK_3 , 4 => GFCTL_DGFSEL_A :: GFCTL_DGFSEL_CLK_4 , 5 => GFCTL_DGFSEL_A :: GFCTL_DGFSEL_CLK_8 , 6 => GFCTL_DGFSEL_A :: GFCTL_DGFSEL_CLK_16 , 7 => GFCTL_DGFSEL_A :: GFCTL_DGFSEL_CLK_31 , _ => unreachable ! () , } } # [doc = "DISABLED"] # [inline (always)] pub fn is_gfctl_dgfsel_disabled (& self) -> bool { * self == GFCTL_DGFSEL_A :: GFCTL_DGFSEL_DISABLED } # [doc = "CLK_1"] # [inline (always)] pub fn is_gfctl_dgfsel_clk_1 (& self) -> bool { * self == GFCTL_DGFSEL_A :: GFCTL_DGFSEL_CLK_1 } # [doc = "CLK_2"] # [inline (always)] pub fn is_gfctl_dgfsel_clk_2 (& self) -> bool { * self == GFCTL_DGFSEL_A :: GFCTL_DGFSEL_CLK_2 } # [doc = "CLK_3"] # [inline (always)] pub fn is_gfctl_dgfsel_clk_3 (& self) -> bool { * self == GFCTL_DGFSEL_A :: GFCTL_DGFSEL_CLK_3 } # [doc = "CLK_4"] # [inline (always)] pub fn is_gfctl_dgfsel_clk_4 (& self) -> bool { * self == GFCTL_DGFSEL_A :: GFCTL_DGFSEL_CLK_4 } # [doc = "CLK_8"] # [inline (always)] pub fn is_gfctl_dgfsel_clk_8 (& self) -> bool { * self == GFCTL_DGFSEL_A :: GFCTL_DGFSEL_CLK_8 } # [doc = "CLK_16"] # [inline (always)] pub fn is_gfctl_dgfsel_clk_16 (& self) -> bool { * self == GFCTL_DGFSEL_A :: GFCTL_DGFSEL_CLK_16 } # [doc = "CLK_31"] # [inline (always)] pub fn is_gfctl_dgfsel_clk_31 (& self) -> bool { * self == GFCTL_DGFSEL_A :: GFCTL_DGFSEL_CLK_31 } } # [doc = "Field `GFCTL_DGFSEL` writer - Glitch Suppression Pulse Width This field controls the pulse width select for glitch suppression on the SCL and SDA lines. The following values are the glitch suppression values in terms of functional clocks. (Core Domain only)"] pub type GFCTL_DGFSEL_W < 'a , REG , const O : u8 > = crate :: FieldWriterSafe < 'a , REG , 3 , O , GFCTL_DGFSEL_A > ; impl < 'a , REG , const O : u8 > GFCTL_DGFSEL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "DISABLED"] # [inline (always)] pub fn gfctl_dgfsel_disabled (self) -> & 'a mut crate :: W < REG > { self . variant (GFCTL_DGFSEL_A :: GFCTL_DGFSEL_DISABLED) } # [doc = "CLK_1"] # [inline (always)] pub fn gfctl_dgfsel_clk_1 (self) -> & 'a mut crate :: W < REG > { self . variant (GFCTL_DGFSEL_A :: GFCTL_DGFSEL_CLK_1) } # [doc = "CLK_2"] # [inline (always)] pub fn gfctl_dgfsel_clk_2 (self) -> & 'a mut crate :: W < REG > { self . variant (GFCTL_DGFSEL_A :: GFCTL_DGFSEL_CLK_2) } # [doc = "CLK_3"] # [inline (always)] pub fn gfctl_dgfsel_clk_3 (self) -> & 'a mut crate :: W < REG > { self . variant (GFCTL_DGFSEL_A :: GFCTL_DGFSEL_CLK_3) } # [doc = "CLK_4"] # [inline (always)] pub fn gfctl_dgfsel_clk_4 (self) -> & 'a mut crate :: W < REG > { self . variant (GFCTL_DGFSEL_A :: GFCTL_DGFSEL_CLK_4) } # [doc = "CLK_8"] # [inline (always)] pub fn gfctl_dgfsel_clk_8 (self) -> & 'a mut crate :: W < REG > { self . variant (GFCTL_DGFSEL_A :: GFCTL_DGFSEL_CLK_8) } # [doc = "CLK_16"] # [inline (always)] pub fn gfctl_dgfsel_clk_16 (self) -> & 'a mut crate :: W < REG > { self . variant (GFCTL_DGFSEL_A :: GFCTL_DGFSEL_CLK_16) } # [doc = "CLK_31"] # [inline (always)] pub fn gfctl_dgfsel_clk_31 (self) -> & 'a mut crate :: W < REG > { self . variant (GFCTL_DGFSEL_A :: GFCTL_DGFSEL_CLK_31) } } # [doc = "Field `GFCTL_AGFEN` reader - Analog Glitch Suppression Enable"] pub type GFCTL_AGFEN_R = crate :: BitReader < GFCTL_AGFEN_A > ; # [doc = "Analog Glitch Suppression Enable\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum GFCTL_AGFEN_A { # [doc = "0: DISABLE"] GFCTL_AGFEN_DISABLE = 0 , # [doc = "1: ENABLE"] GFCTL_AGFEN_ENABLE = 1 , } impl From < GFCTL_AGFEN_A > for bool { # [inline (always)] fn from (variant : GFCTL_AGFEN_A) -> Self { variant as u8 != 0 } } impl GFCTL_AGFEN_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> GFCTL_AGFEN_A { match self . bits { false => GFCTL_AGFEN_A :: GFCTL_AGFEN_DISABLE , true => GFCTL_AGFEN_A :: GFCTL_AGFEN_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_gfctl_agfen_disable (& self) -> bool { * self == GFCTL_AGFEN_A :: GFCTL_AGFEN_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_gfctl_agfen_enable (& self) -> bool { * self == GFCTL_AGFEN_A :: GFCTL_AGFEN_ENABLE } } # [doc = "Field `GFCTL_AGFEN` writer - Analog Glitch Suppression Enable"] pub type GFCTL_AGFEN_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , GFCTL_AGFEN_A > ; impl < 'a , REG , const O : u8 > GFCTL_AGFEN_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn gfctl_agfen_disable (self) -> & 'a mut crate :: W < REG > { self . variant (GFCTL_AGFEN_A :: GFCTL_AGFEN_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn gfctl_agfen_enable (self) -> & 'a mut crate :: W < REG > { self . variant (GFCTL_AGFEN_A :: GFCTL_AGFEN_ENABLE) } } # [doc = "Field `GFCTL_AGFSEL` reader - Analog Glitch Suppression Pulse Width This field controls the pulse width select for the analog glitch suppression on SCL and SDA lines. See device datasheet for exact values. (ULP I2C only)"] pub type GFCTL_AGFSEL_R = crate :: FieldReader < GFCTL_AGFSEL_A > ; # [doc = "Analog Glitch Suppression Pulse Width This field controls the pulse width select for the analog glitch suppression on SCL and SDA lines. See device datasheet for exact values. (ULP I2C only)\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum GFCTL_AGFSEL_A { # [doc = "0: AGLIT_5"] GFCTL_AGFSEL_AGLIT_5 = 0 , # [doc = "1: AGLIT_10"] GFCTL_AGFSEL_AGLIT_10 = 1 , # [doc = "2: AGLIT_25"] GFCTL_AGFSEL_AGLIT_25 = 2 , # [doc = "3: AGLIT_50"] GFCTL_AGFSEL_AGLIT_50 = 3 , } impl From < GFCTL_AGFSEL_A > for u8 { # [inline (always)] fn from (variant : GFCTL_AGFSEL_A) -> Self { variant as _ } } impl crate :: FieldSpec for GFCTL_AGFSEL_A { type Ux = u8 ; } impl GFCTL_AGFSEL_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> GFCTL_AGFSEL_A { match self . bits { 0 => GFCTL_AGFSEL_A :: GFCTL_AGFSEL_AGLIT_5 , 1 => GFCTL_AGFSEL_A :: GFCTL_AGFSEL_AGLIT_10 , 2 => GFCTL_AGFSEL_A :: GFCTL_AGFSEL_AGLIT_25 , 3 => GFCTL_AGFSEL_A :: GFCTL_AGFSEL_AGLIT_50 , _ => unreachable ! () , } } # [doc = "AGLIT_5"] # [inline (always)] pub fn is_gfctl_agfsel_aglit_5 (& self) -> bool { * self == GFCTL_AGFSEL_A :: GFCTL_AGFSEL_AGLIT_5 } # [doc = "AGLIT_10"] # [inline (always)] pub fn is_gfctl_agfsel_aglit_10 (& self) -> bool { * self == GFCTL_AGFSEL_A :: GFCTL_AGFSEL_AGLIT_10 } # [doc = "AGLIT_25"] # [inline (always)] pub fn is_gfctl_agfsel_aglit_25 (& self) -> bool { * self == GFCTL_AGFSEL_A :: GFCTL_AGFSEL_AGLIT_25 } # [doc = "AGLIT_50"] # [inline (always)] pub fn is_gfctl_agfsel_aglit_50 (& self) -> bool { * self == GFCTL_AGFSEL_A :: GFCTL_AGFSEL_AGLIT_50 } } # [doc = "Field `GFCTL_AGFSEL` writer - Analog Glitch Suppression Pulse Width This field controls the pulse width select for the analog glitch suppression on SCL and SDA lines. See device datasheet for exact values. (ULP I2C only)"] pub type GFCTL_AGFSEL_W < 'a , REG , const O : u8 > = crate :: FieldWriterSafe < 'a , REG , 2 , O , GFCTL_AGFSEL_A > ; impl < 'a , REG , const O : u8 > GFCTL_AGFSEL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "AGLIT_5"] # [inline (always)] pub fn gfctl_agfsel_aglit_5 (self) -> & 'a mut crate :: W < REG > { self . variant (GFCTL_AGFSEL_A :: GFCTL_AGFSEL_AGLIT_5) } # [doc = "AGLIT_10"] # [inline (always)] pub fn gfctl_agfsel_aglit_10 (self) -> & 'a mut crate :: W < REG > { self . variant (GFCTL_AGFSEL_A :: GFCTL_AGFSEL_AGLIT_10) } # [doc = "AGLIT_25"] # [inline (always)] pub fn gfctl_agfsel_aglit_25 (self) -> & 'a mut crate :: W < REG > { self . variant (GFCTL_AGFSEL_A :: GFCTL_AGFSEL_AGLIT_25) } # [doc = "AGLIT_50"] # [inline (always)] pub fn gfctl_agfsel_aglit_50 (self) -> & 'a mut crate :: W < REG > { self . variant (GFCTL_AGFSEL_A :: GFCTL_AGFSEL_AGLIT_50) } } # [doc = "Field `GFCTL_CHAIN` reader - Analog and digital noise filters chaining enable."] pub type GFCTL_CHAIN_R = crate :: BitReader < GFCTL_CHAIN_A > ; # [doc = "Analog and digital noise filters chaining enable.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum GFCTL_CHAIN_A { # [doc = "0: DISABLE"] GFCTL_CHAIN_DISABLE = 0 , # [doc = "1: ENABLE"] GFCTL_CHAIN_ENABLE = 1 , } impl From < GFCTL_CHAIN_A > for bool { # [inline (always)] fn from (variant : GFCTL_CHAIN_A) -> Self { variant as u8 != 0 } } impl GFCTL_CHAIN_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> GFCTL_CHAIN_A { match self . bits { false => GFCTL_CHAIN_A :: GFCTL_CHAIN_DISABLE , true => GFCTL_CHAIN_A :: GFCTL_CHAIN_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_gfctl_chain_disable (& self) -> bool { * self == GFCTL_CHAIN_A :: GFCTL_CHAIN_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_gfctl_chain_enable (& self) -> bool { * self == GFCTL_CHAIN_A :: GFCTL_CHAIN_ENABLE } } # [doc = "Field `GFCTL_CHAIN` writer - Analog and digital noise filters chaining enable."] pub type GFCTL_CHAIN_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , GFCTL_CHAIN_A > ; impl < 'a , REG , const O : u8 > GFCTL_CHAIN_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn gfctl_chain_disable (self) -> & 'a mut crate :: W < REG > { self . variant (GFCTL_CHAIN_A :: GFCTL_CHAIN_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn gfctl_chain_enable (self) -> & 'a mut crate :: W < REG > { self . variant (GFCTL_CHAIN_A :: GFCTL_CHAIN_ENABLE) } } impl R { # [doc = "Bits 0:2 - Glitch Suppression Pulse Width This field controls the pulse width select for glitch suppression on the SCL and SDA lines. The following values are the glitch suppression values in terms of functional clocks. (Core Domain only)"] # [inline (always)] pub fn gfctl_dgfsel (& self) -> GFCTL_DGFSEL_R { GFCTL_DGFSEL_R :: new ((self . bits & 7) as u8) } # [doc = "Bit 8 - Analog Glitch Suppression Enable"] # [inline (always)] pub fn gfctl_agfen (& self) -> GFCTL_AGFEN_R { GFCTL_AGFEN_R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bits 9:10 - Analog Glitch Suppression Pulse Width This field controls the pulse width select for the analog glitch suppression on SCL and SDA lines. See device datasheet for exact values. (ULP I2C only)"] # [inline (always)] pub fn gfctl_agfsel (& self) -> GFCTL_AGFSEL_R { GFCTL_AGFSEL_R :: new (((self . bits >> 9) & 3) as u8) } # [doc = "Bit 11 - Analog and digital noise filters chaining enable."] # [inline (always)] pub fn gfctl_chain (& self) -> GFCTL_CHAIN_R { GFCTL_CHAIN_R :: new (((self . bits >> 11) & 1) != 0) } } impl W { # [doc = "Bits 0:2 - Glitch Suppression Pulse Width This field controls the pulse width select for glitch suppression on the SCL and SDA lines. The following values are the glitch suppression values in terms of functional clocks. (Core Domain only)"] # [inline (always)] # [must_use] pub fn gfctl_dgfsel (& mut self) -> GFCTL_DGFSEL_W < GFCTL_SPEC , 0 > { GFCTL_DGFSEL_W :: new (self) } # [doc = "Bit 8 - Analog Glitch Suppression Enable"] # [inline (always)] # [must_use] pub fn gfctl_agfen (& mut self) -> GFCTL_AGFEN_W <'_, GFCTL_SPEC , 8 > { GFCTL_AGFEN_W :: new (self) } # [doc = "Bits 9:10 - Analog Glitch Suppression Pulse Width This field controls the pulse width select for the analog glitch suppression on SCL and SDA lines. See device datasheet for exact values. (ULP I2C only)"] # [inline (always)] # [must_use] pub fn gfctl_agfsel (& mut self) -> GFCTL_AGFSEL_W < GFCTL_SPEC , 9 > { GFCTL_AGFSEL_W :: new (self) } # [doc = "Bit 11 - Analog and digital noise filters chaining enable."] # [inline (always)] # [must_use] pub fn gfctl_chain (& mut self) -> GFCTL_CHAIN_W < GFCTL_SPEC , 11 > { GFCTL_CHAIN_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "I2C Glitch Filter Control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gfctl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gfctl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GFCTL_SPEC ; impl crate :: RegisterSpec for GFCTL_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`gfctl::R`](R) reader structure"] impl crate :: Readable for GFCTL_SPEC { } # [doc = "`write(|w| ..)` method takes [`gfctl::W`](W) writer structure"] impl crate :: Writable for GFCTL_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets GFCTL to value 0"] impl crate :: Resettable for GFCTL_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/uart0/clkcfg.rs:1:3453 [INFO] [stdout] | [INFO] [stdout] 1 | ... fn clkcfg_blockasync (& mut self) -> CLKCFG_BLOCKASYNC_W < CLKCFG_SPEC , 8 > { CLKCFG_BLOCKASYNC_W :: new (self) } # [doc = "Bits 24:... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `CLKCFG` reader"] pub type R = crate :: R < CLKCFG_SPEC > ; # [doc = "Register `CLKCFG` writer"] pub type W = crate :: W < CLKCFG_SPEC > ; # [doc = "Field `CLKCFG_BLOCKASYNC` reader - Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz"] pub type CLKCFG_BLOCKASYNC_R = crate :: BitReader < CLKCFG_BLOCKASYNC_A > ; # [doc = "Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CLKCFG_BLOCKASYNC_A { # [doc = "0: DISABLE"] CLKCFG_BLOCKASYNC_DISABLE = 0 , # [doc = "1: ENABLE"] CLKCFG_BLOCKASYNC_ENABLE = 1 , } impl From < CLKCFG_BLOCKASYNC_A > for bool { # [inline (always)] fn from (variant : CLKCFG_BLOCKASYNC_A) -> Self { variant as u8 != 0 } } impl CLKCFG_BLOCKASYNC_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CLKCFG_BLOCKASYNC_A { match self . bits { false => CLKCFG_BLOCKASYNC_A :: CLKCFG_BLOCKASYNC_DISABLE , true => CLKCFG_BLOCKASYNC_A :: CLKCFG_BLOCKASYNC_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_clkcfg_blockasync_disable (& self) -> bool { * self == CLKCFG_BLOCKASYNC_A :: CLKCFG_BLOCKASYNC_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_clkcfg_blockasync_enable (& self) -> bool { * self == CLKCFG_BLOCKASYNC_A :: CLKCFG_BLOCKASYNC_ENABLE } } # [doc = "Field `CLKCFG_BLOCKASYNC` writer - Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz"] pub type CLKCFG_BLOCKASYNC_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CLKCFG_BLOCKASYNC_A > ; impl < 'a , REG , const O : u8 > CLKCFG_BLOCKASYNC_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn clkcfg_blockasync_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CLKCFG_BLOCKASYNC_A :: CLKCFG_BLOCKASYNC_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn clkcfg_blockasync_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CLKCFG_BLOCKASYNC_A :: CLKCFG_BLOCKASYNC_ENABLE) } } # [doc = "KEY to Allow State Change -- 0xA9\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum CLKCFG_KEY_AW { # [doc = "169: _UNLOCK_W_"] CLKCFG_KEY_UNLOCK = 169 , } impl From < CLKCFG_KEY_AW > for u8 { # [inline (always)] fn from (variant : CLKCFG_KEY_AW) -> Self { variant as _ } } impl crate :: FieldSpec for CLKCFG_KEY_AW { type Ux = u8 ; } # [doc = "Field `CLKCFG_KEY` writer - KEY to Allow State Change -- 0xA9"] pub type CLKCFG_KEY_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 8 , O , CLKCFG_KEY_AW > ; impl < 'a , REG , const O : u8 > CLKCFG_KEY_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "_UNLOCK_W_"] # [inline (always)] pub fn clkcfg_key_unlock (self) -> & 'a mut crate :: W < REG > { self . variant (CLKCFG_KEY_AW :: CLKCFG_KEY_UNLOCK) } } impl R { # [doc = "Bit 8 - Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz"] # [inline (always)] pub fn clkcfg_blockasync (& self) -> CLKCFG_BLOCKASYNC_R { CLKCFG_BLOCKASYNC_R :: new (((self . bits >> 8) & 1) != 0) } } impl W { # [doc = "Bit 8 - Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz"] # [inline (always)] # [must_use] pub fn clkcfg_blockasync (& mut self) -> CLKCFG_BLOCKASYNC_W <'_, CLKCFG_SPEC , 8 > { CLKCFG_BLOCKASYNC_W :: new (self) } # [doc = "Bits 24:31 - KEY to Allow State Change -- 0xA9"] # [inline (always)] # [must_use] pub fn clkcfg_key (& mut self) -> CLKCFG_KEY_W < CLKCFG_SPEC , 24 > { CLKCFG_KEY_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Peripheral Clock Configuration Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clkcfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clkcfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CLKCFG_SPEC ; impl crate :: RegisterSpec for CLKCFG_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`clkcfg::R`](R) reader structure"] impl crate :: Readable for CLKCFG_SPEC { } # [doc = "`write(|w| ..)` method takes [`clkcfg::W`](W) writer structure"] impl crate :: Writable for CLKCFG_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets CLKCFG to value 0"] impl crate :: Resettable for CLKCFG_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/i2c0/int_event0_iset.rs:1:38062 [INFO] [stdout] | [INFO] [stdout] 1 | ...0_iset_mrxdone (& mut self) -> INT_EVENT0_ISET_MRXDONE_W < INT_EVENT0_ISET_SPEC , 0 > { INT_EVENT0_ISET_MRXDONE_W :: new (self) } # [d... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `INT_EVENT0_ISET` writer"] pub type W = crate :: W < INT_EVENT0_ISET_SPEC > ; # [doc = "Master Receive Data Interrupt Signals that a byte has been received\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_MRXDONE_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_MRXDONE_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_MRXDONE_SET = 1 , } impl From < INT_EVENT0_ISET_MRXDONE_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_MRXDONE_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_MRXDONE` writer - Master Receive Data Interrupt Signals that a byte has been received"] pub type INT_EVENT0_ISET_MRXDONE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_MRXDONE_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_MRXDONE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_mrxdone_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MRXDONE_AW :: INT_EVENT0_ISET_MRXDONE_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_mrxdone_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MRXDONE_AW :: INT_EVENT0_ISET_MRXDONE_SET) } } # [doc = "Master Transmit Transaction completed Interrupt\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_MTXDONE_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_MTXDONE_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_MTXDONE_SET = 1 , } impl From < INT_EVENT0_ISET_MTXDONE_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_MTXDONE_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_MTXDONE` writer - Master Transmit Transaction completed Interrupt"] pub type INT_EVENT0_ISET_MTXDONE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_MTXDONE_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_MTXDONE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_mtxdone_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MTXDONE_AW :: INT_EVENT0_ISET_MTXDONE_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_mtxdone_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MTXDONE_AW :: INT_EVENT0_ISET_MTXDONE_SET) } } # [doc = "Master Receive FIFO Trigger Trigger when RX FIFO contains &gt;= defined bytes\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_MRXFIFOTRG_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_MRXFIFOTRG_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_MRXFIFOTRG_SET = 1 , } impl From < INT_EVENT0_ISET_MRXFIFOTRG_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_MRXFIFOTRG_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_MRXFIFOTRG` writer - Master Receive FIFO Trigger Trigger when RX FIFO contains &gt;= defined bytes"] pub type INT_EVENT0_ISET_MRXFIFOTRG_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_MRXFIFOTRG_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_MRXFIFOTRG_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_mrxfifotrg_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MRXFIFOTRG_AW :: INT_EVENT0_ISET_MRXFIFOTRG_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_mrxfifotrg_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MRXFIFOTRG_AW :: INT_EVENT0_ISET_MRXFIFOTRG_SET) } } # [doc = "Master Transmit FIFO Trigger Trigger when Transmit FIFO contains &lt;= defined bytes\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_MTXFIFOTRG_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_MTXFIFOTRG_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_MTXFIFOTRG_SET = 1 , } impl From < INT_EVENT0_ISET_MTXFIFOTRG_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_MTXFIFOTRG_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_MTXFIFOTRG` writer - Master Transmit FIFO Trigger Trigger when Transmit FIFO contains &lt;= defined bytes"] pub type INT_EVENT0_ISET_MTXFIFOTRG_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_MTXFIFOTRG_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_MTXFIFOTRG_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_mtxfifotrg_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MTXFIFOTRG_AW :: INT_EVENT0_ISET_MTXFIFOTRG_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_mtxfifotrg_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MTXFIFOTRG_AW :: INT_EVENT0_ISET_MTXFIFOTRG_SET) } } # [doc = "RXFIFO full event.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_MRXFIFOFULL_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_MRXFIFOFULL_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_MRXFIFOFULL_SET = 1 , } impl From < INT_EVENT0_ISET_MRXFIFOFULL_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_MRXFIFOFULL_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_MRXFIFOFULL` writer - RXFIFO full event."] pub type INT_EVENT0_ISET_MRXFIFOFULL_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_MRXFIFOFULL_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_MRXFIFOFULL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_mrxfifofull_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MRXFIFOFULL_AW :: INT_EVENT0_ISET_MRXFIFOFULL_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_mrxfifofull_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MRXFIFOFULL_AW :: INT_EVENT0_ISET_MRXFIFOFULL_SET) } } # [doc = "Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_MTXEMPTY_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_MTXEMPTY_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_MTXEMPTY_SET = 1 , } impl From < INT_EVENT0_ISET_MTXEMPTY_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_MTXEMPTY_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_MTXEMPTY` writer - Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode."] pub type INT_EVENT0_ISET_MTXEMPTY_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_MTXEMPTY_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_MTXEMPTY_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_mtxempty_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MTXEMPTY_AW :: INT_EVENT0_ISET_MTXEMPTY_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_mtxempty_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MTXEMPTY_AW :: INT_EVENT0_ISET_MTXEMPTY_SET) } } # [doc = "Address/Data NACK Interrupt\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_MNACK_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_MNACK_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_MNACK_SET = 1 , } impl From < INT_EVENT0_ISET_MNACK_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_MNACK_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_MNACK` writer - Address/Data NACK Interrupt"] pub type INT_EVENT0_ISET_MNACK_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_MNACK_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_MNACK_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_mnack_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MNACK_AW :: INT_EVENT0_ISET_MNACK_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_mnack_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MNACK_AW :: INT_EVENT0_ISET_MNACK_SET) } } # [doc = "START Detection Interrupt\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_MSTART_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_MSTART_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_MSTART_SET = 1 , } impl From < INT_EVENT0_ISET_MSTART_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_MSTART_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_MSTART` writer - START Detection Interrupt"] pub type INT_EVENT0_ISET_MSTART_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_MSTART_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_MSTART_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_mstart_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MSTART_AW :: INT_EVENT0_ISET_MSTART_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_mstart_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MSTART_AW :: INT_EVENT0_ISET_MSTART_SET) } } # [doc = "STOP Detection Interrupt\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_MSTOP_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_MSTOP_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_MSTOP_SET = 1 , } impl From < INT_EVENT0_ISET_MSTOP_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_MSTOP_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_MSTOP` writer - STOP Detection Interrupt"] pub type INT_EVENT0_ISET_MSTOP_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_MSTOP_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_MSTOP_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_mstop_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MSTOP_AW :: INT_EVENT0_ISET_MSTOP_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_mstop_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MSTOP_AW :: INT_EVENT0_ISET_MSTOP_SET) } } # [doc = "Arbitration Lost Interrupt\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_MARBLOST_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_MARBLOST_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_MARBLOST_SET = 1 , } impl From < INT_EVENT0_ISET_MARBLOST_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_MARBLOST_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_MARBLOST` writer - Arbitration Lost Interrupt"] pub type INT_EVENT0_ISET_MARBLOST_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_MARBLOST_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_MARBLOST_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_marblost_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MARBLOST_AW :: INT_EVENT0_ISET_MARBLOST_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_marblost_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MARBLOST_AW :: INT_EVENT0_ISET_MARBLOST_SET) } } # [doc = "DMA Done 1 on Event Channel 2\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_MDMA_DONE1_2_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_MDMA_DONE1_2_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_MDMA_DONE1_2_SET = 1 , } impl From < INT_EVENT0_ISET_MDMA_DONE1_2_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_MDMA_DONE1_2_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_MDMA_DONE1_2` writer - DMA Done 1 on Event Channel 2"] pub type INT_EVENT0_ISET_MDMA_DONE1_2_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_MDMA_DONE1_2_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_MDMA_DONE1_2_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_mdma_done1_2_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MDMA_DONE1_2_AW :: INT_EVENT0_ISET_MDMA_DONE1_2_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_mdma_done1_2_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MDMA_DONE1_2_AW :: INT_EVENT0_ISET_MDMA_DONE1_2_SET) } } # [doc = "DMA Done 1 on Event Channel 3\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_MDMA_DONE1_3_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_MDMA_DONE1_3_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_MDMA_DONE1_3_SET = 1 , } impl From < INT_EVENT0_ISET_MDMA_DONE1_3_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_MDMA_DONE1_3_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_MDMA_DONE1_3` writer - DMA Done 1 on Event Channel 3"] pub type INT_EVENT0_ISET_MDMA_DONE1_3_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_MDMA_DONE1_3_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_MDMA_DONE1_3_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_mdma_done1_3_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MDMA_DONE1_3_AW :: INT_EVENT0_ISET_MDMA_DONE1_3_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_mdma_done1_3_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MDMA_DONE1_3_AW :: INT_EVENT0_ISET_MDMA_DONE1_3_SET) } } # [doc = "Master RX Pec Error Interrupt\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_MPEC_RX_ERR_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_MPEC_RX_ERR_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_MPEC_RX_ERR_SET = 1 , } impl From < INT_EVENT0_ISET_MPEC_RX_ERR_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_MPEC_RX_ERR_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_MPEC_RX_ERR` writer - Master RX Pec Error Interrupt"] pub type INT_EVENT0_ISET_MPEC_RX_ERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_MPEC_RX_ERR_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_MPEC_RX_ERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_mpec_rx_err_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MPEC_RX_ERR_AW :: INT_EVENT0_ISET_MPEC_RX_ERR_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_mpec_rx_err_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MPEC_RX_ERR_AW :: INT_EVENT0_ISET_MPEC_RX_ERR_SET) } } # [doc = "Timeout A interrupt\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_TIMEOUTA_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_TIMEOUTA_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_TIMEOUTA_SET = 1 , } impl From < INT_EVENT0_ISET_TIMEOUTA_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_TIMEOUTA_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_TIMEOUTA` writer - Timeout A interrupt"] pub type INT_EVENT0_ISET_TIMEOUTA_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_TIMEOUTA_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_TIMEOUTA_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_timeouta_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_TIMEOUTA_AW :: INT_EVENT0_ISET_TIMEOUTA_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_timeouta_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_TIMEOUTA_AW :: INT_EVENT0_ISET_TIMEOUTA_SET) } } # [doc = "Timeout B Interrupt\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_TIMEOUTB_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_TIMEOUTB_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_TIMEOUTB_SET = 1 , } impl From < INT_EVENT0_ISET_TIMEOUTB_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_TIMEOUTB_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_TIMEOUTB` writer - Timeout B Interrupt"] pub type INT_EVENT0_ISET_TIMEOUTB_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_TIMEOUTB_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_TIMEOUTB_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_timeoutb_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_TIMEOUTB_AW :: INT_EVENT0_ISET_TIMEOUTB_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_timeoutb_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_TIMEOUTB_AW :: INT_EVENT0_ISET_TIMEOUTB_SET) } } # [doc = "Slave Receive Data Interrupt Signals that a byte has been received\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_SRXDONE_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_SRXDONE_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_SRXDONE_SET = 1 , } impl From < INT_EVENT0_ISET_SRXDONE_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_SRXDONE_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_SRXDONE` writer - Slave Receive Data Interrupt Signals that a byte has been received"] pub type INT_EVENT0_ISET_SRXDONE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_SRXDONE_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_SRXDONE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_srxdone_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_SRXDONE_AW :: INT_EVENT0_ISET_SRXDONE_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_srxdone_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_SRXDONE_AW :: INT_EVENT0_ISET_SRXDONE_SET) } } # [doc = "Slave Transmit Transaction completed Interrupt\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_STXDONE_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_STXDONE_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_STXDONE_SET = 1 , } impl From < INT_EVENT0_ISET_STXDONE_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_STXDONE_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_STXDONE` writer - Slave Transmit Transaction completed Interrupt"] pub type INT_EVENT0_ISET_STXDONE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_STXDONE_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_STXDONE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_stxdone_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_STXDONE_AW :: INT_EVENT0_ISET_STXDONE_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_stxdone_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_STXDONE_AW :: INT_EVENT0_ISET_STXDONE_SET) } } # [doc = "Slave Receive FIFO Trigger\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_SRXFIFOTRG_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_SRXFIFOTRG_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_SRXFIFOTRG_SET = 1 , } impl From < INT_EVENT0_ISET_SRXFIFOTRG_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_SRXFIFOTRG_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_SRXFIFOTRG` writer - Slave Receive FIFO Trigger"] pub type INT_EVENT0_ISET_SRXFIFOTRG_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_SRXFIFOTRG_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_SRXFIFOTRG_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_srxfifotrg_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_SRXFIFOTRG_AW :: INT_EVENT0_ISET_SRXFIFOTRG_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_srxfifotrg_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_SRXFIFOTRG_AW :: INT_EVENT0_ISET_SRXFIFOTRG_SET) } } # [doc = "Slave Transmit FIFO Trigger\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_STXFIFOTRG_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_STXFIFOTRG_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_STXFIFOTRG_SET = 1 , } impl From < INT_EVENT0_ISET_STXFIFOTRG_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_STXFIFOTRG_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_STXFIFOTRG` writer - Slave Transmit FIFO Trigger"] pub type INT_EVENT0_ISET_STXFIFOTRG_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_STXFIFOTRG_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_STXFIFOTRG_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_stxfifotrg_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_STXFIFOTRG_AW :: INT_EVENT0_ISET_STXFIFOTRG_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_stxfifotrg_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_STXFIFOTRG_AW :: INT_EVENT0_ISET_STXFIFOTRG_SET) } } # [doc = "RXFIFO full event. This interrupt is set if an RX FIFO is full.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_SRXFIFOFULL_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_SRXFIFOFULL_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_SRXFIFOFULL_SET = 1 , } impl From < INT_EVENT0_ISET_SRXFIFOFULL_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_SRXFIFOFULL_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_SRXFIFOFULL` writer - RXFIFO full event. This interrupt is set if an RX FIFO is full."] pub type INT_EVENT0_ISET_SRXFIFOFULL_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_SRXFIFOFULL_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_SRXFIFOFULL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_srxfifofull_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_SRXFIFOFULL_AW :: INT_EVENT0_ISET_SRXFIFOFULL_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_srxfifofull_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_SRXFIFOFULL_AW :: INT_EVENT0_ISET_SRXFIFOFULL_SET) } } # [doc = "Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_STXEMPTY_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_STXEMPTY_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_STXEMPTY_SET = 1 , } impl From < INT_EVENT0_ISET_STXEMPTY_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_STXEMPTY_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_STXEMPTY` writer - Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode."] pub type INT_EVENT0_ISET_STXEMPTY_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_STXEMPTY_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_STXEMPTY_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_stxempty_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_STXEMPTY_AW :: INT_EVENT0_ISET_STXEMPTY_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_stxempty_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_STXEMPTY_AW :: INT_EVENT0_ISET_STXEMPTY_SET) } } # [doc = "Start Condition Interrupt\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_SSTART_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_SSTART_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_SSTART_SET = 1 , } impl From < INT_EVENT0_ISET_SSTART_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_SSTART_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_SSTART` writer - Start Condition Interrupt"] pub type INT_EVENT0_ISET_SSTART_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_SSTART_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_SSTART_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_sstart_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_SSTART_AW :: INT_EVENT0_ISET_SSTART_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_sstart_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_SSTART_AW :: INT_EVENT0_ISET_SSTART_SET) } } # [doc = "Stop Condition Interrupt\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_SSTOP_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_SSTOP_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_SSTOP_SET = 1 , } impl From < INT_EVENT0_ISET_SSTOP_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_SSTOP_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_SSTOP` writer - Stop Condition Interrupt"] pub type INT_EVENT0_ISET_SSTOP_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_SSTOP_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_SSTOP_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_sstop_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_SSTOP_AW :: INT_EVENT0_ISET_SSTOP_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_sstop_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_SSTOP_AW :: INT_EVENT0_ISET_SSTOP_SET) } } # [doc = "General Call Interrupt\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_SGENCALL_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_SGENCALL_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_SGENCALL_SET = 1 , } impl From < INT_EVENT0_ISET_SGENCALL_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_SGENCALL_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_SGENCALL` writer - General Call Interrupt"] pub type INT_EVENT0_ISET_SGENCALL_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_SGENCALL_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_SGENCALL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_sgencall_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_SGENCALL_AW :: INT_EVENT0_ISET_SGENCALL_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_sgencall_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_SGENCALL_AW :: INT_EVENT0_ISET_SGENCALL_SET) } } # [doc = "DMA Done 1 on Event Channel 2\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_SDMA_DONE1_2_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_SDMA_DONE1_2_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_SDMA_DONE1_2_SET = 1 , } impl From < INT_EVENT0_ISET_SDMA_DONE1_2_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_SDMA_DONE1_2_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_SDMA_DONE1_2` writer - DMA Done 1 on Event Channel 2"] pub type INT_EVENT0_ISET_SDMA_DONE1_2_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_SDMA_DONE1_2_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_SDMA_DONE1_2_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_sdma_done1_2_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_SDMA_DONE1_2_AW :: INT_EVENT0_ISET_SDMA_DONE1_2_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_sdma_done1_2_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_SDMA_DONE1_2_AW :: INT_EVENT0_ISET_SDMA_DONE1_2_SET) } } # [doc = "DMA Done 1 on Event Channel 3\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_SDMA_DONE1_3_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_SDMA_DONE1_3_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_SDMA_DONE1_3_SET = 1 , } impl From < INT_EVENT0_ISET_SDMA_DONE1_3_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_SDMA_DONE1_3_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_SDMA_DONE1_3` writer - DMA Done 1 on Event Channel 3"] pub type INT_EVENT0_ISET_SDMA_DONE1_3_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_SDMA_DONE1_3_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_SDMA_DONE1_3_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_sdma_done1_3_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_SDMA_DONE1_3_AW :: INT_EVENT0_ISET_SDMA_DONE1_3_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_sdma_done1_3_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_SDMA_DONE1_3_AW :: INT_EVENT0_ISET_SDMA_DONE1_3_SET) } } # [doc = "Slave RX Pec Error Interrupt\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_SPEC_RX_ERR_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_SPEC_RX_ERR_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_SPEC_RX_ERR_SET = 1 , } impl From < INT_EVENT0_ISET_SPEC_RX_ERR_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_SPEC_RX_ERR_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_SPEC_RX_ERR` writer - Slave RX Pec Error Interrupt"] pub type INT_EVENT0_ISET_SPEC_RX_ERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_SPEC_RX_ERR_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_SPEC_RX_ERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_spec_rx_err_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_SPEC_RX_ERR_AW :: INT_EVENT0_ISET_SPEC_RX_ERR_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_spec_rx_err_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_SPEC_RX_ERR_AW :: INT_EVENT0_ISET_SPEC_RX_ERR_SET) } } # [doc = "Slave TX FIFO underflow\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_STX_UNFL_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_STX_UNFL_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_STX_UNFL_SET = 1 , } impl From < INT_EVENT0_ISET_STX_UNFL_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_STX_UNFL_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_STX_UNFL` writer - Slave TX FIFO underflow"] pub type INT_EVENT0_ISET_STX_UNFL_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_STX_UNFL_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_STX_UNFL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_stx_unfl_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_STX_UNFL_AW :: INT_EVENT0_ISET_STX_UNFL_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_stx_unfl_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_STX_UNFL_AW :: INT_EVENT0_ISET_STX_UNFL_SET) } } # [doc = "Slave RX FIFO overflow\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_SRX_OVFL_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_SRX_OVFL_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_SRX_OVFL_SET = 1 , } impl From < INT_EVENT0_ISET_SRX_OVFL_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_SRX_OVFL_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_SRX_OVFL` writer - Slave RX FIFO overflow"] pub type INT_EVENT0_ISET_SRX_OVFL_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_SRX_OVFL_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_SRX_OVFL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_srx_ovfl_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_SRX_OVFL_AW :: INT_EVENT0_ISET_SRX_OVFL_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_srx_ovfl_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_SRX_OVFL_AW :: INT_EVENT0_ISET_SRX_OVFL_SET) } } # [doc = "Slave Arbitration Lost\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_SARBLOST_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_SARBLOST_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_SARBLOST_SET = 1 , } impl From < INT_EVENT0_ISET_SARBLOST_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_SARBLOST_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_SARBLOST` writer - Slave Arbitration Lost"] pub type INT_EVENT0_ISET_SARBLOST_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_SARBLOST_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_SARBLOST_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_sarblost_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_SARBLOST_AW :: INT_EVENT0_ISET_SARBLOST_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_sarblost_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_SARBLOST_AW :: INT_EVENT0_ISET_SARBLOST_SET) } } # [doc = "Interrupt overflow\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_INTR_OVFL_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_INTR_OVFL_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_INTR_OVFL_SET = 1 , } impl From < INT_EVENT0_ISET_INTR_OVFL_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_INTR_OVFL_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_INTR_OVFL` writer - Interrupt overflow"] pub type INT_EVENT0_ISET_INTR_OVFL_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_INTR_OVFL_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_INTR_OVFL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_intr_ovfl_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_INTR_OVFL_AW :: INT_EVENT0_ISET_INTR_OVFL_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_intr_ovfl_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_INTR_OVFL_AW :: INT_EVENT0_ISET_INTR_OVFL_SET) } } impl W { # [doc = "Bit 0 - Master Receive Data Interrupt Signals that a byte has been received"] # [inline (always)] # [must_use] pub fn int_event0_iset_mrxdone (& mut self) -> INT_EVENT0_ISET_MRXDONE_W <'_, INT_EVENT0_ISET_SPEC , 0 > { INT_EVENT0_ISET_MRXDONE_W :: new (self) } # [doc = "Bit 1 - Master Transmit Transaction completed Interrupt"] # [inline (always)] # [must_use] pub fn int_event0_iset_mtxdone (& mut self) -> INT_EVENT0_ISET_MTXDONE_W < INT_EVENT0_ISET_SPEC , 1 > { INT_EVENT0_ISET_MTXDONE_W :: new (self) } # [doc = "Bit 2 - Master Receive FIFO Trigger Trigger when RX FIFO contains &gt;= defined bytes"] # [inline (always)] # [must_use] pub fn int_event0_iset_mrxfifotrg (& mut self) -> INT_EVENT0_ISET_MRXFIFOTRG_W < INT_EVENT0_ISET_SPEC , 2 > { INT_EVENT0_ISET_MRXFIFOTRG_W :: new (self) } # [doc = "Bit 3 - Master Transmit FIFO Trigger Trigger when Transmit FIFO contains &lt;= defined bytes"] # [inline (always)] # [must_use] pub fn int_event0_iset_mtxfifotrg (& mut self) -> INT_EVENT0_ISET_MTXFIFOTRG_W < INT_EVENT0_ISET_SPEC , 3 > { INT_EVENT0_ISET_MTXFIFOTRG_W :: new (self) } # [doc = "Bit 4 - RXFIFO full event."] # [inline (always)] # [must_use] pub fn int_event0_iset_mrxfifofull (& mut self) -> INT_EVENT0_ISET_MRXFIFOFULL_W < INT_EVENT0_ISET_SPEC , 4 > { INT_EVENT0_ISET_MRXFIFOFULL_W :: new (self) } # [doc = "Bit 5 - Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode."] # [inline (always)] # [must_use] pub fn int_event0_iset_mtxempty (& mut self) -> INT_EVENT0_ISET_MTXEMPTY_W < INT_EVENT0_ISET_SPEC , 5 > { INT_EVENT0_ISET_MTXEMPTY_W :: new (self) } # [doc = "Bit 7 - Address/Data NACK Interrupt"] # [inline (always)] # [must_use] pub fn int_event0_iset_mnack (& mut self) -> INT_EVENT0_ISET_MNACK_W < INT_EVENT0_ISET_SPEC , 7 > { INT_EVENT0_ISET_MNACK_W :: new (self) } # [doc = "Bit 8 - START Detection Interrupt"] # [inline (always)] # [must_use] pub fn int_event0_iset_mstart (& mut self) -> INT_EVENT0_ISET_MSTART_W < INT_EVENT0_ISET_SPEC , 8 > { INT_EVENT0_ISET_MSTART_W :: new (self) } # [doc = "Bit 9 - STOP Detection Interrupt"] # [inline (always)] # [must_use] pub fn int_event0_iset_mstop (& mut self) -> INT_EVENT0_ISET_MSTOP_W < INT_EVENT0_ISET_SPEC , 9 > { INT_EVENT0_ISET_MSTOP_W :: new (self) } # [doc = "Bit 10 - Arbitration Lost Interrupt"] # [inline (always)] # [must_use] pub fn int_event0_iset_marblost (& mut self) -> INT_EVENT0_ISET_MARBLOST_W < INT_EVENT0_ISET_SPEC , 10 > { INT_EVENT0_ISET_MARBLOST_W :: new (self) } # [doc = "Bit 11 - DMA Done 1 on Event Channel 2"] # [inline (always)] # [must_use] pub fn int_event0_iset_mdma_done1_2 (& mut self) -> INT_EVENT0_ISET_MDMA_DONE1_2_W < INT_EVENT0_ISET_SPEC , 11 > { INT_EVENT0_ISET_MDMA_DONE1_2_W :: new (self) } # [doc = "Bit 12 - DMA Done 1 on Event Channel 3"] # [inline (always)] # [must_use] pub fn int_event0_iset_mdma_done1_3 (& mut self) -> INT_EVENT0_ISET_MDMA_DONE1_3_W < INT_EVENT0_ISET_SPEC , 12 > { INT_EVENT0_ISET_MDMA_DONE1_3_W :: new (self) } # [doc = "Bit 13 - Master RX Pec Error Interrupt"] # [inline (always)] # [must_use] pub fn int_event0_iset_mpec_rx_err (& mut self) -> INT_EVENT0_ISET_MPEC_RX_ERR_W < INT_EVENT0_ISET_SPEC , 13 > { INT_EVENT0_ISET_MPEC_RX_ERR_W :: new (self) } # [doc = "Bit 14 - Timeout A interrupt"] # [inline (always)] # [must_use] pub fn int_event0_iset_timeouta (& mut self) -> INT_EVENT0_ISET_TIMEOUTA_W < INT_EVENT0_ISET_SPEC , 14 > { INT_EVENT0_ISET_TIMEOUTA_W :: new (self) } # [doc = "Bit 15 - Timeout B Interrupt"] # [inline (always)] # [must_use] pub fn int_event0_iset_timeoutb (& mut self) -> INT_EVENT0_ISET_TIMEOUTB_W < INT_EVENT0_ISET_SPEC , 15 > { INT_EVENT0_ISET_TIMEOUTB_W :: new (self) } # [doc = "Bit 16 - Slave Receive Data Interrupt Signals that a byte has been received"] # [inline (always)] # [must_use] pub fn int_event0_iset_srxdone (& mut self) -> INT_EVENT0_ISET_SRXDONE_W < INT_EVENT0_ISET_SPEC , 16 > { INT_EVENT0_ISET_SRXDONE_W :: new (self) } # [doc = "Bit 17 - Slave Transmit Transaction completed Interrupt"] # [inline (always)] # [must_use] pub fn int_event0_iset_stxdone (& mut self) -> INT_EVENT0_ISET_STXDONE_W < INT_EVENT0_ISET_SPEC , 17 > { INT_EVENT0_ISET_STXDONE_W :: new (self) } # [doc = "Bit 18 - Slave Receive FIFO Trigger"] # [inline (always)] # [must_use] pub fn int_event0_iset_srxfifotrg (& mut self) -> INT_EVENT0_ISET_SRXFIFOTRG_W < INT_EVENT0_ISET_SPEC , 18 > { INT_EVENT0_ISET_SRXFIFOTRG_W :: new (self) } # [doc = "Bit 19 - Slave Transmit FIFO Trigger"] # [inline (always)] # [must_use] pub fn int_event0_iset_stxfifotrg (& mut self) -> INT_EVENT0_ISET_STXFIFOTRG_W < INT_EVENT0_ISET_SPEC , 19 > { INT_EVENT0_ISET_STXFIFOTRG_W :: new (self) } # [doc = "Bit 20 - RXFIFO full event. This interrupt is set if an RX FIFO is full."] # [inline (always)] # [must_use] pub fn int_event0_iset_srxfifofull (& mut self) -> INT_EVENT0_ISET_SRXFIFOFULL_W < INT_EVENT0_ISET_SPEC , 20 > { INT_EVENT0_ISET_SRXFIFOFULL_W :: new (self) } # [doc = "Bit 21 - Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode."] # [inline (always)] # [must_use] pub fn int_event0_iset_stxempty (& mut self) -> INT_EVENT0_ISET_STXEMPTY_W < INT_EVENT0_ISET_SPEC , 21 > { INT_EVENT0_ISET_STXEMPTY_W :: new (self) } # [doc = "Bit 22 - Start Condition Interrupt"] # [inline (always)] # [must_use] pub fn int_event0_iset_sstart (& mut self) -> INT_EVENT0_ISET_SSTART_W < INT_EVENT0_ISET_SPEC , 22 > { INT_EVENT0_ISET_SSTART_W :: new (self) } # [doc = "Bit 23 - Stop Condition Interrupt"] # [inline (always)] # [must_use] pub fn int_event0_iset_sstop (& mut self) -> INT_EVENT0_ISET_SSTOP_W < INT_EVENT0_ISET_SPEC , 23 > { INT_EVENT0_ISET_SSTOP_W :: new (self) } # [doc = "Bit 24 - General Call Interrupt"] # [inline (always)] # [must_use] pub fn int_event0_iset_sgencall (& mut self) -> INT_EVENT0_ISET_SGENCALL_W < INT_EVENT0_ISET_SPEC , 24 > { INT_EVENT0_ISET_SGENCALL_W :: new (self) } # [doc = "Bit 25 - DMA Done 1 on Event Channel 2"] # [inline (always)] # [must_use] pub fn int_event0_iset_sdma_done1_2 (& mut self) -> INT_EVENT0_ISET_SDMA_DONE1_2_W < INT_EVENT0_ISET_SPEC , 25 > { INT_EVENT0_ISET_SDMA_DONE1_2_W :: new (self) } # [doc = "Bit 26 - DMA Done 1 on Event Channel 3"] # [inline (always)] # [must_use] pub fn int_event0_iset_sdma_done1_3 (& mut self) -> INT_EVENT0_ISET_SDMA_DONE1_3_W < INT_EVENT0_ISET_SPEC , 26 > { INT_EVENT0_ISET_SDMA_DONE1_3_W :: new (self) } # [doc = "Bit 27 - Slave RX Pec Error Interrupt"] # [inline (always)] # [must_use] pub fn int_event0_iset_spec_rx_err (& mut self) -> INT_EVENT0_ISET_SPEC_RX_ERR_W < INT_EVENT0_ISET_SPEC , 27 > { INT_EVENT0_ISET_SPEC_RX_ERR_W :: new (self) } # [doc = "Bit 28 - Slave TX FIFO underflow"] # [inline (always)] # [must_use] pub fn int_event0_iset_stx_unfl (& mut self) -> INT_EVENT0_ISET_STX_UNFL_W < INT_EVENT0_ISET_SPEC , 28 > { INT_EVENT0_ISET_STX_UNFL_W :: new (self) } # [doc = "Bit 29 - Slave RX FIFO overflow"] # [inline (always)] # [must_use] pub fn int_event0_iset_srx_ovfl (& mut self) -> INT_EVENT0_ISET_SRX_OVFL_W < INT_EVENT0_ISET_SPEC , 29 > { INT_EVENT0_ISET_SRX_OVFL_W :: new (self) } # [doc = "Bit 30 - Slave Arbitration Lost"] # [inline (always)] # [must_use] pub fn int_event0_iset_sarblost (& mut self) -> INT_EVENT0_ISET_SARBLOST_W < INT_EVENT0_ISET_SPEC , 30 > { INT_EVENT0_ISET_SARBLOST_W :: new (self) } # [doc = "Bit 31 - Interrupt overflow"] # [inline (always)] # [must_use] pub fn int_event0_iset_intr_ovfl (& mut self) -> INT_EVENT0_ISET_INTR_OVFL_W < INT_EVENT0_ISET_SPEC , 31 > { INT_EVENT0_ISET_INTR_OVFL_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Interrupt set\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_event0_iset::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct INT_EVENT0_ISET_SPEC ; impl crate :: RegisterSpec for INT_EVENT0_ISET_SPEC { type Ux = u32 ; } # [doc = "`write(|w| ..)` method takes [`int_event0_iset::W`](W) writer structure"] impl crate :: Writable for INT_EVENT0_ISET_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets INT_EVENT0_ISET to value 0"] impl crate :: Resettable for INT_EVENT0_ISET_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/cpuss/int_group1_iclr.rs:1:1318 [INFO] [stdout] | [INFO] [stdout] 1 | ..._group1_iclr_int (& mut self) -> INT_GROUP1_ICLR_INT_W < INT_GROUP1_ICLR_SPEC , 0 > { INT_GROUP1_ICLR_INT_W :: new (self) } # [doc = r... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `INT_GROUP1_ICLR` writer"] pub type W = crate :: W < INT_GROUP1_ICLR_SPEC > ; # [doc = "Clears INT in RIS register\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_GROUP1_ICLR_INT_AW { # [doc = "0: NO_EFFECT"] INT_GROUP1_ICLR_INT_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_GROUP1_ICLR_INT_CLR = 1 , } impl From < INT_GROUP1_ICLR_INT_AW > for bool { # [inline (always)] fn from (variant : INT_GROUP1_ICLR_INT_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_GROUP1_ICLR_INT` writer - Clears INT in RIS register"] pub type INT_GROUP1_ICLR_INT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_GROUP1_ICLR_INT_AW > ; impl < 'a , REG , const O : u8 > INT_GROUP1_ICLR_INT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_group1_iclr_int_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_GROUP1_ICLR_INT_AW :: INT_GROUP1_ICLR_INT_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_group1_iclr_int_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_GROUP1_ICLR_INT_AW :: INT_GROUP1_ICLR_INT_CLR) } } impl W { # [doc = "Bit 0 - Clears INT in RIS register"] # [inline (always)] # [must_use] pub fn int_group1_iclr_int (& mut self) -> INT_GROUP1_ICLR_INT_W <'_, INT_GROUP1_ICLR_SPEC , 0 > { INT_GROUP1_ICLR_INT_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Interrupt clear\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_group1_iclr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct INT_GROUP1_ICLR_SPEC ; impl crate :: RegisterSpec for INT_GROUP1_ICLR_SPEC { type Ux = u32 ; } # [doc = "`write(|w| ..)` method takes [`int_group1_iclr::W`](W) writer structure"] impl crate :: Writable for INT_GROUP1_ICLR_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets INT_GROUP1_ICLR to value 0"] impl crate :: Resettable for INT_GROUP1_ICLR_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/opa1/cfgbase.rs:1:5060 [INFO] [stdout] | [INFO] [stdout] 1 | ..._use] pub fn cfgbase_rri (& mut self) -> CFGBASE_RRI_W < CFGBASE_SPEC , 2 > { CFGBASE_RRI_W :: new (self) } # [doc = r" Writes raw bit... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `CFGBASE` reader"] pub type R = crate :: R < CFGBASE_SPEC > ; # [doc = "Register `CFGBASE` writer"] pub type W = crate :: W < CFGBASE_SPEC > ; # [doc = "Field `CFGBASE_GBW` reader - Select gain bandwidth which affects current as well the gain bandwidth. The lower gain bandwidth has lower current. See device specific datasheet for values. Can only be modified when STAT.BUSY=0."] pub type CFGBASE_GBW_R = crate :: BitReader < CFGBASE_GBW_A > ; # [doc = "Select gain bandwidth which affects current as well the gain bandwidth. The lower gain bandwidth has lower current. See device specific datasheet for values. Can only be modified when STAT.BUSY=0.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CFGBASE_GBW_A { # [doc = "0: LOWGAIN"] CFGBASE_GBW_LOWGAIN = 0 , # [doc = "1: HIGHGAIN"] CFGBASE_GBW_HIGHGAIN = 1 , } impl From < CFGBASE_GBW_A > for bool { # [inline (always)] fn from (variant : CFGBASE_GBW_A) -> Self { variant as u8 != 0 } } impl CFGBASE_GBW_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CFGBASE_GBW_A { match self . bits { false => CFGBASE_GBW_A :: CFGBASE_GBW_LOWGAIN , true => CFGBASE_GBW_A :: CFGBASE_GBW_HIGHGAIN , } } # [doc = "LOWGAIN"] # [inline (always)] pub fn is_cfgbase_gbw_lowgain (& self) -> bool { * self == CFGBASE_GBW_A :: CFGBASE_GBW_LOWGAIN } # [doc = "HIGHGAIN"] # [inline (always)] pub fn is_cfgbase_gbw_highgain (& self) -> bool { * self == CFGBASE_GBW_A :: CFGBASE_GBW_HIGHGAIN } } # [doc = "Field `CFGBASE_GBW` writer - Select gain bandwidth which affects current as well the gain bandwidth. The lower gain bandwidth has lower current. See device specific datasheet for values. Can only be modified when STAT.BUSY=0."] pub type CFGBASE_GBW_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CFGBASE_GBW_A > ; impl < 'a , REG , const O : u8 > CFGBASE_GBW_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "LOWGAIN"] # [inline (always)] pub fn cfgbase_gbw_lowgain (self) -> & 'a mut crate :: W < REG > { self . variant (CFGBASE_GBW_A :: CFGBASE_GBW_LOWGAIN) } # [doc = "HIGHGAIN"] # [inline (always)] pub fn cfgbase_gbw_highgain (self) -> & 'a mut crate :: W < REG > { self . variant (CFGBASE_GBW_A :: CFGBASE_GBW_HIGHGAIN) } } # [doc = "Field `CFGBASE_RRI` reader - Rail-to-rail input enable. Can only be modified when STAT.BUSY=0"] pub type CFGBASE_RRI_R = crate :: BitReader < CFGBASE_RRI_A > ; # [doc = "Rail-to-rail input enable. Can only be modified when STAT.BUSY=0\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CFGBASE_RRI_A { # [doc = "0: OFF"] CFGBASE_RRI_OFF = 0 , # [doc = "1: ON"] CFGBASE_RRI_ON = 1 , } impl From < CFGBASE_RRI_A > for bool { # [inline (always)] fn from (variant : CFGBASE_RRI_A) -> Self { variant as u8 != 0 } } impl CFGBASE_RRI_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CFGBASE_RRI_A { match self . bits { false => CFGBASE_RRI_A :: CFGBASE_RRI_OFF , true => CFGBASE_RRI_A :: CFGBASE_RRI_ON , } } # [doc = "OFF"] # [inline (always)] pub fn is_cfgbase_rri_off (& self) -> bool { * self == CFGBASE_RRI_A :: CFGBASE_RRI_OFF } # [doc = "ON"] # [inline (always)] pub fn is_cfgbase_rri_on (& self) -> bool { * self == CFGBASE_RRI_A :: CFGBASE_RRI_ON } } # [doc = "Field `CFGBASE_RRI` writer - Rail-to-rail input enable. Can only be modified when STAT.BUSY=0"] pub type CFGBASE_RRI_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CFGBASE_RRI_A > ; impl < 'a , REG , const O : u8 > CFGBASE_RRI_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "OFF"] # [inline (always)] pub fn cfgbase_rri_off (self) -> & 'a mut crate :: W < REG > { self . variant (CFGBASE_RRI_A :: CFGBASE_RRI_OFF) } # [doc = "ON"] # [inline (always)] pub fn cfgbase_rri_on (self) -> & 'a mut crate :: W < REG > { self . variant (CFGBASE_RRI_A :: CFGBASE_RRI_ON) } } impl R { # [doc = "Bit 0 - Select gain bandwidth which affects current as well the gain bandwidth. The lower gain bandwidth has lower current. See device specific datasheet for values. Can only be modified when STAT.BUSY=0."] # [inline (always)] pub fn cfgbase_gbw (& self) -> CFGBASE_GBW_R { CFGBASE_GBW_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 2 - Rail-to-rail input enable. Can only be modified when STAT.BUSY=0"] # [inline (always)] pub fn cfgbase_rri (& self) -> CFGBASE_RRI_R { CFGBASE_RRI_R :: new (((self . bits >> 2) & 1) != 0) } } impl W { # [doc = "Bit 0 - Select gain bandwidth which affects current as well the gain bandwidth. The lower gain bandwidth has lower current. See device specific datasheet for values. Can only be modified when STAT.BUSY=0."] # [inline (always)] # [must_use] pub fn cfgbase_gbw (& mut self) -> CFGBASE_GBW_W < CFGBASE_SPEC , 0 > { CFGBASE_GBW_W :: new (self) } # [doc = "Bit 2 - Rail-to-rail input enable. Can only be modified when STAT.BUSY=0"] # [inline (always)] # [must_use] pub fn cfgbase_rri (& mut self) -> CFGBASE_RRI_W <'_, CFGBASE_SPEC , 2 > { CFGBASE_RRI_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Configuration Base Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cfgbase::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cfgbase::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CFGBASE_SPEC ; impl crate :: RegisterSpec for CFGBASE_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`cfgbase::R`](R) reader structure"] impl crate :: Readable for CFGBASE_SPEC { } # [doc = "`write(|w| ..)` method takes [`cfgbase::W`](W) writer structure"] impl crate :: Writable for CFGBASE_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets CFGBASE to value 0"] impl crate :: Resettable for CFGBASE_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/i2c0/soar2.rs:1:4719 [INFO] [stdout] | [INFO] [stdout] 1 | ...pub fn soar2_oar2_mask (& mut self) -> SOAR2_OAR2_MASK_W < SOAR2_SPEC , 16 > { SOAR2_OAR2_MASK_W :: new (self) } # [doc = r" Writes ra... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `SOAR2` reader"] pub type R = crate :: R < SOAR2_SPEC > ; # [doc = "Register `SOAR2` writer"] pub type W = crate :: W < SOAR2_SPEC > ; # [doc = "Field `SOAR2_OAR2` reader - I2C Slave Own Address 2 This field specifies the alternate OAR2 address."] pub type SOAR2_OAR2_R = crate :: FieldReader ; # [doc = "Field `SOAR2_OAR2` writer - I2C Slave Own Address 2 This field specifies the alternate OAR2 address."] pub type SOAR2_OAR2_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 7 , O > ; # [doc = "Field `SOAR2_OAR2EN` reader - I2C Slave Own Address 2 Enable"] pub type SOAR2_OAR2EN_R = crate :: BitReader < SOAR2_OAR2EN_A > ; # [doc = "I2C Slave Own Address 2 Enable\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum SOAR2_OAR2EN_A { # [doc = "0: DISABLE"] SOAR2_OAR2EN_DISABLE = 0 , # [doc = "1: ENABLE"] SOAR2_OAR2EN_ENABLE = 1 , } impl From < SOAR2_OAR2EN_A > for bool { # [inline (always)] fn from (variant : SOAR2_OAR2EN_A) -> Self { variant as u8 != 0 } } impl SOAR2_OAR2EN_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> SOAR2_OAR2EN_A { match self . bits { false => SOAR2_OAR2EN_A :: SOAR2_OAR2EN_DISABLE , true => SOAR2_OAR2EN_A :: SOAR2_OAR2EN_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_soar2_oar2en_disable (& self) -> bool { * self == SOAR2_OAR2EN_A :: SOAR2_OAR2EN_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_soar2_oar2en_enable (& self) -> bool { * self == SOAR2_OAR2EN_A :: SOAR2_OAR2EN_ENABLE } } # [doc = "Field `SOAR2_OAR2EN` writer - I2C Slave Own Address 2 Enable"] pub type SOAR2_OAR2EN_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , SOAR2_OAR2EN_A > ; impl < 'a , REG , const O : u8 > SOAR2_OAR2EN_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn soar2_oar2en_disable (self) -> & 'a mut crate :: W < REG > { self . variant (SOAR2_OAR2EN_A :: SOAR2_OAR2EN_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn soar2_oar2en_enable (self) -> & 'a mut crate :: W < REG > { self . variant (SOAR2_OAR2EN_A :: SOAR2_OAR2EN_ENABLE) } } # [doc = "Field `SOAR2_OAR2_MASK` reader - I2C Slave Own Address 2 Mask: This field specifies bits A6 through A0 of the slave address. The bits with value 1 in SOAR2.OAR2_MASK field will make the corresponding incoming address bits to match by default regardless of the value inside SOAR2.OAR2 i.e. corresponding SOAR2.OAR2 bit is a dont care."] pub type SOAR2_OAR2_MASK_R = crate :: FieldReader ; # [doc = "Field `SOAR2_OAR2_MASK` writer - I2C Slave Own Address 2 Mask: This field specifies bits A6 through A0 of the slave address. The bits with value 1 in SOAR2.OAR2_MASK field will make the corresponding incoming address bits to match by default regardless of the value inside SOAR2.OAR2 i.e. corresponding SOAR2.OAR2 bit is a dont care."] pub type SOAR2_OAR2_MASK_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 7 , O > ; impl R { # [doc = "Bits 0:6 - I2C Slave Own Address 2 This field specifies the alternate OAR2 address."] # [inline (always)] pub fn soar2_oar2 (& self) -> SOAR2_OAR2_R { SOAR2_OAR2_R :: new ((self . bits & 0x7f) as u8) } # [doc = "Bit 7 - I2C Slave Own Address 2 Enable"] # [inline (always)] pub fn soar2_oar2en (& self) -> SOAR2_OAR2EN_R { SOAR2_OAR2EN_R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bits 16:22 - I2C Slave Own Address 2 Mask: This field specifies bits A6 through A0 of the slave address. The bits with value 1 in SOAR2.OAR2_MASK field will make the corresponding incoming address bits to match by default regardless of the value inside SOAR2.OAR2 i.e. corresponding SOAR2.OAR2 bit is a dont care."] # [inline (always)] pub fn soar2_oar2_mask (& self) -> SOAR2_OAR2_MASK_R { SOAR2_OAR2_MASK_R :: new (((self . bits >> 16) & 0x7f) as u8) } } impl W { # [doc = "Bits 0:6 - I2C Slave Own Address 2 This field specifies the alternate OAR2 address."] # [inline (always)] # [must_use] pub fn soar2_oar2 (& mut self) -> SOAR2_OAR2_W < SOAR2_SPEC , 0 > { SOAR2_OAR2_W :: new (self) } # [doc = "Bit 7 - I2C Slave Own Address 2 Enable"] # [inline (always)] # [must_use] pub fn soar2_oar2en (& mut self) -> SOAR2_OAR2EN_W < SOAR2_SPEC , 7 > { SOAR2_OAR2EN_W :: new (self) } # [doc = "Bits 16:22 - I2C Slave Own Address 2 Mask: This field specifies bits A6 through A0 of the slave address. The bits with value 1 in SOAR2.OAR2_MASK field will make the corresponding incoming address bits to match by default regardless of the value inside SOAR2.OAR2 i.e. corresponding SOAR2.OAR2 bit is a dont care."] # [inline (always)] # [must_use] pub fn soar2_oar2_mask (& mut self) -> SOAR2_OAR2_MASK_W <'_, SOAR2_SPEC , 16 > { SOAR2_OAR2_MASK_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "I2C Slave Own Address 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`soar2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`soar2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct SOAR2_SPEC ; impl crate :: RegisterSpec for SOAR2_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`soar2::R`](R) reader structure"] impl crate :: Readable for SOAR2_SPEC { } # [doc = "`write(|w| ..)` method takes [`soar2::W`](W) writer structure"] impl crate :: Writable for SOAR2_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets SOAR2 to value 0"] impl crate :: Resettable for SOAR2_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/uart0/clkcfg.rs:1:3657 [INFO] [stdout] | [INFO] [stdout] 1 | ...t_use] pub fn clkcfg_key (& mut self) -> CLKCFG_KEY_W < CLKCFG_SPEC , 24 > { CLKCFG_KEY_W :: new (self) } # [doc = r" Writes raw bits ... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `CLKCFG` reader"] pub type R = crate :: R < CLKCFG_SPEC > ; # [doc = "Register `CLKCFG` writer"] pub type W = crate :: W < CLKCFG_SPEC > ; # [doc = "Field `CLKCFG_BLOCKASYNC` reader - Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz"] pub type CLKCFG_BLOCKASYNC_R = crate :: BitReader < CLKCFG_BLOCKASYNC_A > ; # [doc = "Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CLKCFG_BLOCKASYNC_A { # [doc = "0: DISABLE"] CLKCFG_BLOCKASYNC_DISABLE = 0 , # [doc = "1: ENABLE"] CLKCFG_BLOCKASYNC_ENABLE = 1 , } impl From < CLKCFG_BLOCKASYNC_A > for bool { # [inline (always)] fn from (variant : CLKCFG_BLOCKASYNC_A) -> Self { variant as u8 != 0 } } impl CLKCFG_BLOCKASYNC_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CLKCFG_BLOCKASYNC_A { match self . bits { false => CLKCFG_BLOCKASYNC_A :: CLKCFG_BLOCKASYNC_DISABLE , true => CLKCFG_BLOCKASYNC_A :: CLKCFG_BLOCKASYNC_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_clkcfg_blockasync_disable (& self) -> bool { * self == CLKCFG_BLOCKASYNC_A :: CLKCFG_BLOCKASYNC_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_clkcfg_blockasync_enable (& self) -> bool { * self == CLKCFG_BLOCKASYNC_A :: CLKCFG_BLOCKASYNC_ENABLE } } # [doc = "Field `CLKCFG_BLOCKASYNC` writer - Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz"] pub type CLKCFG_BLOCKASYNC_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CLKCFG_BLOCKASYNC_A > ; impl < 'a , REG , const O : u8 > CLKCFG_BLOCKASYNC_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn clkcfg_blockasync_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CLKCFG_BLOCKASYNC_A :: CLKCFG_BLOCKASYNC_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn clkcfg_blockasync_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CLKCFG_BLOCKASYNC_A :: CLKCFG_BLOCKASYNC_ENABLE) } } # [doc = "KEY to Allow State Change -- 0xA9\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum CLKCFG_KEY_AW { # [doc = "169: _UNLOCK_W_"] CLKCFG_KEY_UNLOCK = 169 , } impl From < CLKCFG_KEY_AW > for u8 { # [inline (always)] fn from (variant : CLKCFG_KEY_AW) -> Self { variant as _ } } impl crate :: FieldSpec for CLKCFG_KEY_AW { type Ux = u8 ; } # [doc = "Field `CLKCFG_KEY` writer - KEY to Allow State Change -- 0xA9"] pub type CLKCFG_KEY_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 8 , O , CLKCFG_KEY_AW > ; impl < 'a , REG , const O : u8 > CLKCFG_KEY_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "_UNLOCK_W_"] # [inline (always)] pub fn clkcfg_key_unlock (self) -> & 'a mut crate :: W < REG > { self . variant (CLKCFG_KEY_AW :: CLKCFG_KEY_UNLOCK) } } impl R { # [doc = "Bit 8 - Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz"] # [inline (always)] pub fn clkcfg_blockasync (& self) -> CLKCFG_BLOCKASYNC_R { CLKCFG_BLOCKASYNC_R :: new (((self . bits >> 8) & 1) != 0) } } impl W { # [doc = "Bit 8 - Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz"] # [inline (always)] # [must_use] pub fn clkcfg_blockasync (& mut self) -> CLKCFG_BLOCKASYNC_W < CLKCFG_SPEC , 8 > { CLKCFG_BLOCKASYNC_W :: new (self) } # [doc = "Bits 24:31 - KEY to Allow State Change -- 0xA9"] # [inline (always)] # [must_use] pub fn clkcfg_key (& mut self) -> CLKCFG_KEY_W <'_, CLKCFG_SPEC , 24 > { CLKCFG_KEY_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Peripheral Clock Configuration Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clkcfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clkcfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CLKCFG_SPEC ; impl crate :: RegisterSpec for CLKCFG_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`clkcfg::R`](R) reader structure"] impl crate :: Readable for CLKCFG_SPEC { } # [doc = "`write(|w| ..)` method takes [`clkcfg::W`](W) writer structure"] impl crate :: Writable for CLKCFG_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets CLKCFG to value 0"] impl crate :: Resettable for CLKCFG_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/i2c1/mfifoctl.rs:1:13367 [INFO] [stdout] | [INFO] [stdout] 1 | ... fn mfifoctl_rxflush (& mut self) -> MFIFOCTL_RXFLUSH_W < MFIFOCTL_SPEC , 15 > { MFIFOCTL_RXFLUSH_W :: new (self) } # [doc = r" Writes... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `MFIFOCTL` reader"] pub type R = crate :: R < MFIFOCTL_SPEC > ; # [doc = "Register `MFIFOCTL` writer"] pub type W = crate :: W < MFIFOCTL_SPEC > ; # [doc = "Field `MFIFOCTL_TXTRIG` reader - TX FIFO Trigger Indicates at what fill level in the TX FIFO a trigger will be generated."] pub type MFIFOCTL_TXTRIG_R = crate :: FieldReader < MFIFOCTL_TXTRIG_A > ; # [doc = "TX FIFO Trigger Indicates at what fill level in the TX FIFO a trigger will be generated.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum MFIFOCTL_TXTRIG_A { # [doc = "4: LEVEL_4"] MFIFOCTL_TXTRIG_LEVEL_4 = 4 , # [doc = "5: LEVEL_5"] MFIFOCTL_TXTRIG_LEVEL_5 = 5 , # [doc = "6: LEVEL_6"] MFIFOCTL_TXTRIG_LEVEL_6 = 6 , # [doc = "7: LEVEL_7"] MFIFOCTL_TXTRIG_LEVEL_7 = 7 , } impl From < MFIFOCTL_TXTRIG_A > for u8 { # [inline (always)] fn from (variant : MFIFOCTL_TXTRIG_A) -> Self { variant as _ } } impl crate :: FieldSpec for MFIFOCTL_TXTRIG_A { type Ux = u8 ; } impl MFIFOCTL_TXTRIG_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < MFIFOCTL_TXTRIG_A > { match self . bits { 4 => Some (MFIFOCTL_TXTRIG_A :: MFIFOCTL_TXTRIG_LEVEL_4) , 5 => Some (MFIFOCTL_TXTRIG_A :: MFIFOCTL_TXTRIG_LEVEL_5) , 6 => Some (MFIFOCTL_TXTRIG_A :: MFIFOCTL_TXTRIG_LEVEL_6) , 7 => Some (MFIFOCTL_TXTRIG_A :: MFIFOCTL_TXTRIG_LEVEL_7) , _ => None , } } # [doc = "LEVEL_4"] # [inline (always)] pub fn is_mfifoctl_txtrig_level_4 (& self) -> bool { * self == MFIFOCTL_TXTRIG_A :: MFIFOCTL_TXTRIG_LEVEL_4 } # [doc = "LEVEL_5"] # [inline (always)] pub fn is_mfifoctl_txtrig_level_5 (& self) -> bool { * self == MFIFOCTL_TXTRIG_A :: MFIFOCTL_TXTRIG_LEVEL_5 } # [doc = "LEVEL_6"] # [inline (always)] pub fn is_mfifoctl_txtrig_level_6 (& self) -> bool { * self == MFIFOCTL_TXTRIG_A :: MFIFOCTL_TXTRIG_LEVEL_6 } # [doc = "LEVEL_7"] # [inline (always)] pub fn is_mfifoctl_txtrig_level_7 (& self) -> bool { * self == MFIFOCTL_TXTRIG_A :: MFIFOCTL_TXTRIG_LEVEL_7 } } # [doc = "Field `MFIFOCTL_TXTRIG` writer - TX FIFO Trigger Indicates at what fill level in the TX FIFO a trigger will be generated."] pub type MFIFOCTL_TXTRIG_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 3 , O , MFIFOCTL_TXTRIG_A > ; impl < 'a , REG , const O : u8 > MFIFOCTL_TXTRIG_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "LEVEL_4"] # [inline (always)] pub fn mfifoctl_txtrig_level_4 (self) -> & 'a mut crate :: W < REG > { self . variant (MFIFOCTL_TXTRIG_A :: MFIFOCTL_TXTRIG_LEVEL_4) } # [doc = "LEVEL_5"] # [inline (always)] pub fn mfifoctl_txtrig_level_5 (self) -> & 'a mut crate :: W < REG > { self . variant (MFIFOCTL_TXTRIG_A :: MFIFOCTL_TXTRIG_LEVEL_5) } # [doc = "LEVEL_6"] # [inline (always)] pub fn mfifoctl_txtrig_level_6 (self) -> & 'a mut crate :: W < REG > { self . variant (MFIFOCTL_TXTRIG_A :: MFIFOCTL_TXTRIG_LEVEL_6) } # [doc = "LEVEL_7"] # [inline (always)] pub fn mfifoctl_txtrig_level_7 (self) -> & 'a mut crate :: W < REG > { self . variant (MFIFOCTL_TXTRIG_A :: MFIFOCTL_TXTRIG_LEVEL_7) } } # [doc = "Field `MFIFOCTL_TXFLUSH` reader - TX FIFO Flush Setting this bit will Flush the TX FIFO. Before reseting this bit to stop Flush the TXFIFOCNT should be checked to be 8 and indicating that the Flush has completed."] pub type MFIFOCTL_TXFLUSH_R = crate :: BitReader < MFIFOCTL_TXFLUSH_A > ; # [doc = "TX FIFO Flush Setting this bit will Flush the TX FIFO. Before reseting this bit to stop Flush the TXFIFOCNT should be checked to be 8 and indicating that the Flush has completed.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum MFIFOCTL_TXFLUSH_A { # [doc = "0: NOFLUSH"] MFIFOCTL_TXFLUSH_NOFLUSH = 0 , # [doc = "1: FLUSH"] MFIFOCTL_TXFLUSH_FLUSH = 1 , } impl From < MFIFOCTL_TXFLUSH_A > for bool { # [inline (always)] fn from (variant : MFIFOCTL_TXFLUSH_A) -> Self { variant as u8 != 0 } } impl MFIFOCTL_TXFLUSH_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> MFIFOCTL_TXFLUSH_A { match self . bits { false => MFIFOCTL_TXFLUSH_A :: MFIFOCTL_TXFLUSH_NOFLUSH , true => MFIFOCTL_TXFLUSH_A :: MFIFOCTL_TXFLUSH_FLUSH , } } # [doc = "NOFLUSH"] # [inline (always)] pub fn is_mfifoctl_txflush_noflush (& self) -> bool { * self == MFIFOCTL_TXFLUSH_A :: MFIFOCTL_TXFLUSH_NOFLUSH } # [doc = "FLUSH"] # [inline (always)] pub fn is_mfifoctl_txflush_flush (& self) -> bool { * self == MFIFOCTL_TXFLUSH_A :: MFIFOCTL_TXFLUSH_FLUSH } } # [doc = "Field `MFIFOCTL_TXFLUSH` writer - TX FIFO Flush Setting this bit will Flush the TX FIFO. Before reseting this bit to stop Flush the TXFIFOCNT should be checked to be 8 and indicating that the Flush has completed."] pub type MFIFOCTL_TXFLUSH_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , MFIFOCTL_TXFLUSH_A > ; impl < 'a , REG , const O : u8 > MFIFOCTL_TXFLUSH_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NOFLUSH"] # [inline (always)] pub fn mfifoctl_txflush_noflush (self) -> & 'a mut crate :: W < REG > { self . variant (MFIFOCTL_TXFLUSH_A :: MFIFOCTL_TXFLUSH_NOFLUSH) } # [doc = "FLUSH"] # [inline (always)] pub fn mfifoctl_txflush_flush (self) -> & 'a mut crate :: W < REG > { self . variant (MFIFOCTL_TXFLUSH_A :: MFIFOCTL_TXFLUSH_FLUSH) } } # [doc = "Field `MFIFOCTL_RXTRIG` reader - RX FIFO Trigger Indicates at what fill level in the RX FIFO a trigger will be generated. Note: Programming RXTRIG to 0x0 has no effect since no data is present to transfer out of RX FIFO."] pub type MFIFOCTL_RXTRIG_R = crate :: FieldReader < MFIFOCTL_RXTRIG_A > ; # [doc = "RX FIFO Trigger Indicates at what fill level in the RX FIFO a trigger will be generated. Note: Programming RXTRIG to 0x0 has no effect since no data is present to transfer out of RX FIFO.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum MFIFOCTL_RXTRIG_A { # [doc = "4: LEVEL_5"] MFIFOCTL_RXTRIG_LEVEL_5 = 4 , # [doc = "5: LEVEL_6"] MFIFOCTL_RXTRIG_LEVEL_6 = 5 , # [doc = "6: LEVEL_7"] MFIFOCTL_RXTRIG_LEVEL_7 = 6 , # [doc = "7: LEVEL_8"] MFIFOCTL_RXTRIG_LEVEL_8 = 7 , } impl From < MFIFOCTL_RXTRIG_A > for u8 { # [inline (always)] fn from (variant : MFIFOCTL_RXTRIG_A) -> Self { variant as _ } } impl crate :: FieldSpec for MFIFOCTL_RXTRIG_A { type Ux = u8 ; } impl MFIFOCTL_RXTRIG_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < MFIFOCTL_RXTRIG_A > { match self . bits { 4 => Some (MFIFOCTL_RXTRIG_A :: MFIFOCTL_RXTRIG_LEVEL_5) , 5 => Some (MFIFOCTL_RXTRIG_A :: MFIFOCTL_RXTRIG_LEVEL_6) , 6 => Some (MFIFOCTL_RXTRIG_A :: MFIFOCTL_RXTRIG_LEVEL_7) , 7 => Some (MFIFOCTL_RXTRIG_A :: MFIFOCTL_RXTRIG_LEVEL_8) , _ => None , } } # [doc = "LEVEL_5"] # [inline (always)] pub fn is_mfifoctl_rxtrig_level_5 (& self) -> bool { * self == MFIFOCTL_RXTRIG_A :: MFIFOCTL_RXTRIG_LEVEL_5 } # [doc = "LEVEL_6"] # [inline (always)] pub fn is_mfifoctl_rxtrig_level_6 (& self) -> bool { * self == MFIFOCTL_RXTRIG_A :: MFIFOCTL_RXTRIG_LEVEL_6 } # [doc = "LEVEL_7"] # [inline (always)] pub fn is_mfifoctl_rxtrig_level_7 (& self) -> bool { * self == MFIFOCTL_RXTRIG_A :: MFIFOCTL_RXTRIG_LEVEL_7 } # [doc = "LEVEL_8"] # [inline (always)] pub fn is_mfifoctl_rxtrig_level_8 (& self) -> bool { * self == MFIFOCTL_RXTRIG_A :: MFIFOCTL_RXTRIG_LEVEL_8 } } # [doc = "Field `MFIFOCTL_RXTRIG` writer - RX FIFO Trigger Indicates at what fill level in the RX FIFO a trigger will be generated. Note: Programming RXTRIG to 0x0 has no effect since no data is present to transfer out of RX FIFO."] pub type MFIFOCTL_RXTRIG_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 3 , O , MFIFOCTL_RXTRIG_A > ; impl < 'a , REG , const O : u8 > MFIFOCTL_RXTRIG_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "LEVEL_5"] # [inline (always)] pub fn mfifoctl_rxtrig_level_5 (self) -> & 'a mut crate :: W < REG > { self . variant (MFIFOCTL_RXTRIG_A :: MFIFOCTL_RXTRIG_LEVEL_5) } # [doc = "LEVEL_6"] # [inline (always)] pub fn mfifoctl_rxtrig_level_6 (self) -> & 'a mut crate :: W < REG > { self . variant (MFIFOCTL_RXTRIG_A :: MFIFOCTL_RXTRIG_LEVEL_6) } # [doc = "LEVEL_7"] # [inline (always)] pub fn mfifoctl_rxtrig_level_7 (self) -> & 'a mut crate :: W < REG > { self . variant (MFIFOCTL_RXTRIG_A :: MFIFOCTL_RXTRIG_LEVEL_7) } # [doc = "LEVEL_8"] # [inline (always)] pub fn mfifoctl_rxtrig_level_8 (self) -> & 'a mut crate :: W < REG > { self . variant (MFIFOCTL_RXTRIG_A :: MFIFOCTL_RXTRIG_LEVEL_8) } } # [doc = "Field `MFIFOCTL_RXFLUSH` reader - RX FIFO Flush Setting this bit will Flush the RX FIFO. Before reseting this bit to stop Flush the RXFIFOCNT should be checked to be 0 and indicating that the Flush has completed."] pub type MFIFOCTL_RXFLUSH_R = crate :: BitReader < MFIFOCTL_RXFLUSH_A > ; # [doc = "RX FIFO Flush Setting this bit will Flush the RX FIFO. Before reseting this bit to stop Flush the RXFIFOCNT should be checked to be 0 and indicating that the Flush has completed.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum MFIFOCTL_RXFLUSH_A { # [doc = "0: NOFLUSH"] MFIFOCTL_RXFLUSH_NOFLUSH = 0 , # [doc = "1: FLUSH"] MFIFOCTL_RXFLUSH_FLUSH = 1 , } impl From < MFIFOCTL_RXFLUSH_A > for bool { # [inline (always)] fn from (variant : MFIFOCTL_RXFLUSH_A) -> Self { variant as u8 != 0 } } impl MFIFOCTL_RXFLUSH_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> MFIFOCTL_RXFLUSH_A { match self . bits { false => MFIFOCTL_RXFLUSH_A :: MFIFOCTL_RXFLUSH_NOFLUSH , true => MFIFOCTL_RXFLUSH_A :: MFIFOCTL_RXFLUSH_FLUSH , } } # [doc = "NOFLUSH"] # [inline (always)] pub fn is_mfifoctl_rxflush_noflush (& self) -> bool { * self == MFIFOCTL_RXFLUSH_A :: MFIFOCTL_RXFLUSH_NOFLUSH } # [doc = "FLUSH"] # [inline (always)] pub fn is_mfifoctl_rxflush_flush (& self) -> bool { * self == MFIFOCTL_RXFLUSH_A :: MFIFOCTL_RXFLUSH_FLUSH } } # [doc = "Field `MFIFOCTL_RXFLUSH` writer - RX FIFO Flush Setting this bit will Flush the RX FIFO. Before reseting this bit to stop Flush the RXFIFOCNT should be checked to be 0 and indicating that the Flush has completed."] pub type MFIFOCTL_RXFLUSH_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , MFIFOCTL_RXFLUSH_A > ; impl < 'a , REG , const O : u8 > MFIFOCTL_RXFLUSH_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NOFLUSH"] # [inline (always)] pub fn mfifoctl_rxflush_noflush (self) -> & 'a mut crate :: W < REG > { self . variant (MFIFOCTL_RXFLUSH_A :: MFIFOCTL_RXFLUSH_NOFLUSH) } # [doc = "FLUSH"] # [inline (always)] pub fn mfifoctl_rxflush_flush (self) -> & 'a mut crate :: W < REG > { self . variant (MFIFOCTL_RXFLUSH_A :: MFIFOCTL_RXFLUSH_FLUSH) } } impl R { # [doc = "Bits 0:2 - TX FIFO Trigger Indicates at what fill level in the TX FIFO a trigger will be generated."] # [inline (always)] pub fn mfifoctl_txtrig (& self) -> MFIFOCTL_TXTRIG_R { MFIFOCTL_TXTRIG_R :: new ((self . bits & 7) as u8) } # [doc = "Bit 7 - TX FIFO Flush Setting this bit will Flush the TX FIFO. Before reseting this bit to stop Flush the TXFIFOCNT should be checked to be 8 and indicating that the Flush has completed."] # [inline (always)] pub fn mfifoctl_txflush (& self) -> MFIFOCTL_TXFLUSH_R { MFIFOCTL_TXFLUSH_R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bits 8:10 - RX FIFO Trigger Indicates at what fill level in the RX FIFO a trigger will be generated. Note: Programming RXTRIG to 0x0 has no effect since no data is present to transfer out of RX FIFO."] # [inline (always)] pub fn mfifoctl_rxtrig (& self) -> MFIFOCTL_RXTRIG_R { MFIFOCTL_RXTRIG_R :: new (((self . bits >> 8) & 7) as u8) } # [doc = "Bit 15 - RX FIFO Flush Setting this bit will Flush the RX FIFO. Before reseting this bit to stop Flush the RXFIFOCNT should be checked to be 0 and indicating that the Flush has completed."] # [inline (always)] pub fn mfifoctl_rxflush (& self) -> MFIFOCTL_RXFLUSH_R { MFIFOCTL_RXFLUSH_R :: new (((self . bits >> 15) & 1) != 0) } } impl W { # [doc = "Bits 0:2 - TX FIFO Trigger Indicates at what fill level in the TX FIFO a trigger will be generated."] # [inline (always)] # [must_use] pub fn mfifoctl_txtrig (& mut self) -> MFIFOCTL_TXTRIG_W < MFIFOCTL_SPEC , 0 > { MFIFOCTL_TXTRIG_W :: new (self) } # [doc = "Bit 7 - TX FIFO Flush Setting this bit will Flush the TX FIFO. Before reseting this bit to stop Flush the TXFIFOCNT should be checked to be 8 and indicating that the Flush has completed."] # [inline (always)] # [must_use] pub fn mfifoctl_txflush (& mut self) -> MFIFOCTL_TXFLUSH_W < MFIFOCTL_SPEC , 7 > { MFIFOCTL_TXFLUSH_W :: new (self) } # [doc = "Bits 8:10 - RX FIFO Trigger Indicates at what fill level in the RX FIFO a trigger will be generated. Note: Programming RXTRIG to 0x0 has no effect since no data is present to transfer out of RX FIFO."] # [inline (always)] # [must_use] pub fn mfifoctl_rxtrig (& mut self) -> MFIFOCTL_RXTRIG_W < MFIFOCTL_SPEC , 8 > { MFIFOCTL_RXTRIG_W :: new (self) } # [doc = "Bit 15 - RX FIFO Flush Setting this bit will Flush the RX FIFO. Before reseting this bit to stop Flush the RXFIFOCNT should be checked to be 0 and indicating that the Flush has completed."] # [inline (always)] # [must_use] pub fn mfifoctl_rxflush (& mut self) -> MFIFOCTL_RXFLUSH_W <'_, MFIFOCTL_SPEC , 15 > { MFIFOCTL_RXFLUSH_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "I2C Master FIFO Control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mfifoctl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mfifoctl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct MFIFOCTL_SPEC ; impl crate :: RegisterSpec for MFIFOCTL_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`mfifoctl::R`](R) reader structure"] impl crate :: Readable for MFIFOCTL_SPEC { } # [doc = "`write(|w| ..)` method takes [`mfifoctl::W`](W) writer structure"] impl crate :: Writable for MFIFOCTL_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets MFIFOCTL to value 0"] impl crate :: Resettable for MFIFOCTL_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/i2c1/mctr.rs:1:12457 [INFO] [stdout] | [INFO] [stdout] 1 | ...ust_use] pub fn mctr_start (& mut self) -> MCTR_START_W < MCTR_SPEC , 1 > { MCTR_START_W :: new (self) } # [doc = "Bit 2 - Generate ST... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `MCTR` reader"] pub type R = crate :: R < MCTR_SPEC > ; # [doc = "Register `MCTR` writer"] pub type W = crate :: W < MCTR_SPEC > ; # [doc = "Field `MCTR_BURSTRUN` reader - I2C Master Enable and start transaction"] pub type MCTR_BURSTRUN_R = crate :: BitReader < MCTR_BURSTRUN_A > ; # [doc = "I2C Master Enable and start transaction\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum MCTR_BURSTRUN_A { # [doc = "0: DISABLE"] MCTR_BURSTRUN_DISABLE = 0 , # [doc = "1: ENABLE"] MCTR_BURSTRUN_ENABLE = 1 , } impl From < MCTR_BURSTRUN_A > for bool { # [inline (always)] fn from (variant : MCTR_BURSTRUN_A) -> Self { variant as u8 != 0 } } impl MCTR_BURSTRUN_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> MCTR_BURSTRUN_A { match self . bits { false => MCTR_BURSTRUN_A :: MCTR_BURSTRUN_DISABLE , true => MCTR_BURSTRUN_A :: MCTR_BURSTRUN_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_mctr_burstrun_disable (& self) -> bool { * self == MCTR_BURSTRUN_A :: MCTR_BURSTRUN_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_mctr_burstrun_enable (& self) -> bool { * self == MCTR_BURSTRUN_A :: MCTR_BURSTRUN_ENABLE } } # [doc = "Field `MCTR_BURSTRUN` writer - I2C Master Enable and start transaction"] pub type MCTR_BURSTRUN_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , MCTR_BURSTRUN_A > ; impl < 'a , REG , const O : u8 > MCTR_BURSTRUN_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn mctr_burstrun_disable (self) -> & 'a mut crate :: W < REG > { self . variant (MCTR_BURSTRUN_A :: MCTR_BURSTRUN_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn mctr_burstrun_enable (self) -> & 'a mut crate :: W < REG > { self . variant (MCTR_BURSTRUN_A :: MCTR_BURSTRUN_ENABLE) } } # [doc = "Field `MCTR_START` reader - Generate START"] pub type MCTR_START_R = crate :: BitReader < MCTR_START_A > ; # [doc = "Generate START\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum MCTR_START_A { # [doc = "0: DISABLE"] MCTR_START_DISABLE = 0 , # [doc = "1: ENABLE"] MCTR_START_ENABLE = 1 , } impl From < MCTR_START_A > for bool { # [inline (always)] fn from (variant : MCTR_START_A) -> Self { variant as u8 != 0 } } impl MCTR_START_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> MCTR_START_A { match self . bits { false => MCTR_START_A :: MCTR_START_DISABLE , true => MCTR_START_A :: MCTR_START_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_mctr_start_disable (& self) -> bool { * self == MCTR_START_A :: MCTR_START_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_mctr_start_enable (& self) -> bool { * self == MCTR_START_A :: MCTR_START_ENABLE } } # [doc = "Field `MCTR_START` writer - Generate START"] pub type MCTR_START_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , MCTR_START_A > ; impl < 'a , REG , const O : u8 > MCTR_START_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn mctr_start_disable (self) -> & 'a mut crate :: W < REG > { self . variant (MCTR_START_A :: MCTR_START_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn mctr_start_enable (self) -> & 'a mut crate :: W < REG > { self . variant (MCTR_START_A :: MCTR_START_ENABLE) } } # [doc = "Field `MCTR_STOP` reader - Generate STOP"] pub type MCTR_STOP_R = crate :: BitReader < MCTR_STOP_A > ; # [doc = "Generate STOP\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum MCTR_STOP_A { # [doc = "0: DISABLE"] MCTR_STOP_DISABLE = 0 , # [doc = "1: ENABLE"] MCTR_STOP_ENABLE = 1 , } impl From < MCTR_STOP_A > for bool { # [inline (always)] fn from (variant : MCTR_STOP_A) -> Self { variant as u8 != 0 } } impl MCTR_STOP_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> MCTR_STOP_A { match self . bits { false => MCTR_STOP_A :: MCTR_STOP_DISABLE , true => MCTR_STOP_A :: MCTR_STOP_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_mctr_stop_disable (& self) -> bool { * self == MCTR_STOP_A :: MCTR_STOP_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_mctr_stop_enable (& self) -> bool { * self == MCTR_STOP_A :: MCTR_STOP_ENABLE } } # [doc = "Field `MCTR_STOP` writer - Generate STOP"] pub type MCTR_STOP_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , MCTR_STOP_A > ; impl < 'a , REG , const O : u8 > MCTR_STOP_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn mctr_stop_disable (self) -> & 'a mut crate :: W < REG > { self . variant (MCTR_STOP_A :: MCTR_STOP_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn mctr_stop_enable (self) -> & 'a mut crate :: W < REG > { self . variant (MCTR_STOP_A :: MCTR_STOP_ENABLE) } } # [doc = "Field `MCTR_ACK` reader - Data Acknowledge Enable. Software needs to configure this bit to send the ACK or NACK. See field decoding in Table: MCTR Field decoding."] pub type MCTR_ACK_R = crate :: BitReader < MCTR_ACK_A > ; # [doc = "Data Acknowledge Enable. Software needs to configure this bit to send the ACK or NACK. See field decoding in Table: MCTR Field decoding.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum MCTR_ACK_A { # [doc = "0: DISABLE"] MCTR_ACK_DISABLE = 0 , # [doc = "1: ENABLE"] MCTR_ACK_ENABLE = 1 , } impl From < MCTR_ACK_A > for bool { # [inline (always)] fn from (variant : MCTR_ACK_A) -> Self { variant as u8 != 0 } } impl MCTR_ACK_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> MCTR_ACK_A { match self . bits { false => MCTR_ACK_A :: MCTR_ACK_DISABLE , true => MCTR_ACK_A :: MCTR_ACK_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_mctr_ack_disable (& self) -> bool { * self == MCTR_ACK_A :: MCTR_ACK_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_mctr_ack_enable (& self) -> bool { * self == MCTR_ACK_A :: MCTR_ACK_ENABLE } } # [doc = "Field `MCTR_ACK` writer - Data Acknowledge Enable. Software needs to configure this bit to send the ACK or NACK. See field decoding in Table: MCTR Field decoding."] pub type MCTR_ACK_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , MCTR_ACK_A > ; impl < 'a , REG , const O : u8 > MCTR_ACK_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn mctr_ack_disable (self) -> & 'a mut crate :: W < REG > { self . variant (MCTR_ACK_A :: MCTR_ACK_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn mctr_ack_enable (self) -> & 'a mut crate :: W < REG > { self . variant (MCTR_ACK_A :: MCTR_ACK_ENABLE) } } # [doc = "Field `MCTR_MACKOEN` reader - Master ACK overrride Enable"] pub type MCTR_MACKOEN_R = crate :: BitReader < MCTR_MACKOEN_A > ; # [doc = "Master ACK overrride Enable\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum MCTR_MACKOEN_A { # [doc = "0: DISABLE"] MCTR_MACKOEN_DISABLE = 0 , # [doc = "1: ENABLE"] MCTR_MACKOEN_ENABLE = 1 , } impl From < MCTR_MACKOEN_A > for bool { # [inline (always)] fn from (variant : MCTR_MACKOEN_A) -> Self { variant as u8 != 0 } } impl MCTR_MACKOEN_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> MCTR_MACKOEN_A { match self . bits { false => MCTR_MACKOEN_A :: MCTR_MACKOEN_DISABLE , true => MCTR_MACKOEN_A :: MCTR_MACKOEN_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_mctr_mackoen_disable (& self) -> bool { * self == MCTR_MACKOEN_A :: MCTR_MACKOEN_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_mctr_mackoen_enable (& self) -> bool { * self == MCTR_MACKOEN_A :: MCTR_MACKOEN_ENABLE } } # [doc = "Field `MCTR_MACKOEN` writer - Master ACK overrride Enable"] pub type MCTR_MACKOEN_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , MCTR_MACKOEN_A > ; impl < 'a , REG , const O : u8 > MCTR_MACKOEN_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn mctr_mackoen_disable (self) -> & 'a mut crate :: W < REG > { self . variant (MCTR_MACKOEN_A :: MCTR_MACKOEN_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn mctr_mackoen_enable (self) -> & 'a mut crate :: W < REG > { self . variant (MCTR_MACKOEN_A :: MCTR_MACKOEN_ENABLE) } } # [doc = "Field `MCTR_RD_ON_TXEMPTY` reader - Read on TX Empty"] pub type MCTR_RD_ON_TXEMPTY_R = crate :: BitReader < MCTR_RD_ON_TXEMPTY_A > ; # [doc = "Read on TX Empty\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum MCTR_RD_ON_TXEMPTY_A { # [doc = "0: DISABLE"] MCTR_RD_ON_TXEMPTY_DISABLE = 0 , # [doc = "1: ENABLE"] MCTR_RD_ON_TXEMPTY_ENABLE = 1 , } impl From < MCTR_RD_ON_TXEMPTY_A > for bool { # [inline (always)] fn from (variant : MCTR_RD_ON_TXEMPTY_A) -> Self { variant as u8 != 0 } } impl MCTR_RD_ON_TXEMPTY_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> MCTR_RD_ON_TXEMPTY_A { match self . bits { false => MCTR_RD_ON_TXEMPTY_A :: MCTR_RD_ON_TXEMPTY_DISABLE , true => MCTR_RD_ON_TXEMPTY_A :: MCTR_RD_ON_TXEMPTY_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_mctr_rd_on_txempty_disable (& self) -> bool { * self == MCTR_RD_ON_TXEMPTY_A :: MCTR_RD_ON_TXEMPTY_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_mctr_rd_on_txempty_enable (& self) -> bool { * self == MCTR_RD_ON_TXEMPTY_A :: MCTR_RD_ON_TXEMPTY_ENABLE } } # [doc = "Field `MCTR_RD_ON_TXEMPTY` writer - Read on TX Empty"] pub type MCTR_RD_ON_TXEMPTY_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , MCTR_RD_ON_TXEMPTY_A > ; impl < 'a , REG , const O : u8 > MCTR_RD_ON_TXEMPTY_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn mctr_rd_on_txempty_disable (self) -> & 'a mut crate :: W < REG > { self . variant (MCTR_RD_ON_TXEMPTY_A :: MCTR_RD_ON_TXEMPTY_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn mctr_rd_on_txempty_enable (self) -> & 'a mut crate :: W < REG > { self . variant (MCTR_RD_ON_TXEMPTY_A :: MCTR_RD_ON_TXEMPTY_ENABLE) } } # [doc = "Field `MCTR_MBLEN` reader - I2C transaction length This field contains the programmed length of bytes of the Transaction."] pub type MCTR_MBLEN_R = crate :: FieldReader < u16 > ; # [doc = "Field `MCTR_MBLEN` writer - I2C transaction length This field contains the programmed length of bytes of the Transaction."] pub type MCTR_MBLEN_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 12 , O , u16 > ; impl R { # [doc = "Bit 0 - I2C Master Enable and start transaction"] # [inline (always)] pub fn mctr_burstrun (& self) -> MCTR_BURSTRUN_R { MCTR_BURSTRUN_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - Generate START"] # [inline (always)] pub fn mctr_start (& self) -> MCTR_START_R { MCTR_START_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - Generate STOP"] # [inline (always)] pub fn mctr_stop (& self) -> MCTR_STOP_R { MCTR_STOP_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - Data Acknowledge Enable. Software needs to configure this bit to send the ACK or NACK. See field decoding in Table: MCTR Field decoding."] # [inline (always)] pub fn mctr_ack (& self) -> MCTR_ACK_R { MCTR_ACK_R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - Master ACK overrride Enable"] # [inline (always)] pub fn mctr_mackoen (& self) -> MCTR_MACKOEN_R { MCTR_MACKOEN_R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - Read on TX Empty"] # [inline (always)] pub fn mctr_rd_on_txempty (& self) -> MCTR_RD_ON_TXEMPTY_R { MCTR_RD_ON_TXEMPTY_R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bits 16:27 - I2C transaction length This field contains the programmed length of bytes of the Transaction."] # [inline (always)] pub fn mctr_mblen (& self) -> MCTR_MBLEN_R { MCTR_MBLEN_R :: new (((self . bits >> 16) & 0x0fff) as u16) } } impl W { # [doc = "Bit 0 - I2C Master Enable and start transaction"] # [inline (always)] # [must_use] pub fn mctr_burstrun (& mut self) -> MCTR_BURSTRUN_W < MCTR_SPEC , 0 > { MCTR_BURSTRUN_W :: new (self) } # [doc = "Bit 1 - Generate START"] # [inline (always)] # [must_use] pub fn mctr_start (& mut self) -> MCTR_START_W <'_, MCTR_SPEC , 1 > { MCTR_START_W :: new (self) } # [doc = "Bit 2 - Generate STOP"] # [inline (always)] # [must_use] pub fn mctr_stop (& mut self) -> MCTR_STOP_W < MCTR_SPEC , 2 > { MCTR_STOP_W :: new (self) } # [doc = "Bit 3 - Data Acknowledge Enable. Software needs to configure this bit to send the ACK or NACK. See field decoding in Table: MCTR Field decoding."] # [inline (always)] # [must_use] pub fn mctr_ack (& mut self) -> MCTR_ACK_W < MCTR_SPEC , 3 > { MCTR_ACK_W :: new (self) } # [doc = "Bit 4 - Master ACK overrride Enable"] # [inline (always)] # [must_use] pub fn mctr_mackoen (& mut self) -> MCTR_MACKOEN_W < MCTR_SPEC , 4 > { MCTR_MACKOEN_W :: new (self) } # [doc = "Bit 5 - Read on TX Empty"] # [inline (always)] # [must_use] pub fn mctr_rd_on_txempty (& mut self) -> MCTR_RD_ON_TXEMPTY_W < MCTR_SPEC , 5 > { MCTR_RD_ON_TXEMPTY_W :: new (self) } # [doc = "Bits 16:27 - I2C transaction length This field contains the programmed length of bytes of the Transaction."] # [inline (always)] # [must_use] pub fn mctr_mblen (& mut self) -> MCTR_MBLEN_W < MCTR_SPEC , 16 > { MCTR_MBLEN_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "I2C Master Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mctr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mctr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct MCTR_SPEC ; impl crate :: RegisterSpec for MCTR_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`mctr::R`](R) reader structure"] impl crate :: Readable for MCTR_SPEC { } # [doc = "`write(|w| ..)` method takes [`mctr::W`](W) writer structure"] impl crate :: Writable for MCTR_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets MCTR to value 0"] impl crate :: Resettable for MCTR_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/i2c1/int_event1_iset.rs:1:5877 [INFO] [stdout] | [INFO] [stdout] 1 | ...t_srxfifotrg (& mut self) -> INT_EVENT1_ISET_SRXFIFOTRG_W < INT_EVENT1_ISET_SPEC , 2 > { INT_EVENT1_ISET_SRXFIFOTRG_W :: new (self) } ... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `INT_EVENT1_ISET` writer"] pub type W = crate :: W < INT_EVENT1_ISET_SPEC > ; # [doc = "Master Receive FIFO Trigger Trigger when RX FIFO contains &gt;= defined bytes\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT1_ISET_MRXFIFOTRG_AW { # [doc = "0: NO_EFFECT"] INT_EVENT1_ISET_MRXFIFOTRG_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT1_ISET_MRXFIFOTRG_SET = 1 , } impl From < INT_EVENT1_ISET_MRXFIFOTRG_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT1_ISET_MRXFIFOTRG_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT1_ISET_MRXFIFOTRG` writer - Master Receive FIFO Trigger Trigger when RX FIFO contains &gt;= defined bytes"] pub type INT_EVENT1_ISET_MRXFIFOTRG_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT1_ISET_MRXFIFOTRG_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT1_ISET_MRXFIFOTRG_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event1_iset_mrxfifotrg_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_ISET_MRXFIFOTRG_AW :: INT_EVENT1_ISET_MRXFIFOTRG_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event1_iset_mrxfifotrg_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_ISET_MRXFIFOTRG_AW :: INT_EVENT1_ISET_MRXFIFOTRG_SET) } } # [doc = "Master Transmit FIFO Trigger Trigger when Transmit FIFO contains &lt;= defined bytes\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT1_ISET_MTXFIFOTRG_AW { # [doc = "0: NO_EFFECT"] INT_EVENT1_ISET_MTXFIFOTRG_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT1_ISET_MTXFIFOTRG_SET = 1 , } impl From < INT_EVENT1_ISET_MTXFIFOTRG_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT1_ISET_MTXFIFOTRG_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT1_ISET_MTXFIFOTRG` writer - Master Transmit FIFO Trigger Trigger when Transmit FIFO contains &lt;= defined bytes"] pub type INT_EVENT1_ISET_MTXFIFOTRG_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT1_ISET_MTXFIFOTRG_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT1_ISET_MTXFIFOTRG_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event1_iset_mtxfifotrg_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_ISET_MTXFIFOTRG_AW :: INT_EVENT1_ISET_MTXFIFOTRG_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event1_iset_mtxfifotrg_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_ISET_MTXFIFOTRG_AW :: INT_EVENT1_ISET_MTXFIFOTRG_SET) } } # [doc = "Slave Receive FIFO Trigger\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT1_ISET_SRXFIFOTRG_AW { # [doc = "0: NO_EFFECT"] INT_EVENT1_ISET_SRXFIFOTRG_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT1_ISET_SRXFIFOTRG_SET = 1 , } impl From < INT_EVENT1_ISET_SRXFIFOTRG_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT1_ISET_SRXFIFOTRG_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT1_ISET_SRXFIFOTRG` writer - Slave Receive FIFO Trigger"] pub type INT_EVENT1_ISET_SRXFIFOTRG_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT1_ISET_SRXFIFOTRG_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT1_ISET_SRXFIFOTRG_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event1_iset_srxfifotrg_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_ISET_SRXFIFOTRG_AW :: INT_EVENT1_ISET_SRXFIFOTRG_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event1_iset_srxfifotrg_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_ISET_SRXFIFOTRG_AW :: INT_EVENT1_ISET_SRXFIFOTRG_SET) } } # [doc = "Slave Transmit FIFO Trigger\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT1_ISET_STXFIFOTRG_AW { # [doc = "0: NO_EFFECT"] INT_EVENT1_ISET_STXFIFOTRG_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT1_ISET_STXFIFOTRG_SET = 1 , } impl From < INT_EVENT1_ISET_STXFIFOTRG_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT1_ISET_STXFIFOTRG_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT1_ISET_STXFIFOTRG` writer - Slave Transmit FIFO Trigger"] pub type INT_EVENT1_ISET_STXFIFOTRG_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT1_ISET_STXFIFOTRG_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT1_ISET_STXFIFOTRG_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event1_iset_stxfifotrg_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_ISET_STXFIFOTRG_AW :: INT_EVENT1_ISET_STXFIFOTRG_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event1_iset_stxfifotrg_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_ISET_STXFIFOTRG_AW :: INT_EVENT1_ISET_STXFIFOTRG_SET) } } impl W { # [doc = "Bit 0 - Master Receive FIFO Trigger Trigger when RX FIFO contains &gt;= defined bytes"] # [inline (always)] # [must_use] pub fn int_event1_iset_mrxfifotrg (& mut self) -> INT_EVENT1_ISET_MRXFIFOTRG_W < INT_EVENT1_ISET_SPEC , 0 > { INT_EVENT1_ISET_MRXFIFOTRG_W :: new (self) } # [doc = "Bit 1 - Master Transmit FIFO Trigger Trigger when Transmit FIFO contains &lt;= defined bytes"] # [inline (always)] # [must_use] pub fn int_event1_iset_mtxfifotrg (& mut self) -> INT_EVENT1_ISET_MTXFIFOTRG_W < INT_EVENT1_ISET_SPEC , 1 > { INT_EVENT1_ISET_MTXFIFOTRG_W :: new (self) } # [doc = "Bit 2 - Slave Receive FIFO Trigger"] # [inline (always)] # [must_use] pub fn int_event1_iset_srxfifotrg (& mut self) -> INT_EVENT1_ISET_SRXFIFOTRG_W <'_, INT_EVENT1_ISET_SPEC , 2 > { INT_EVENT1_ISET_SRXFIFOTRG_W :: new (self) } # [doc = "Bit 3 - Slave Transmit FIFO Trigger"] # [inline (always)] # [must_use] pub fn int_event1_iset_stxfifotrg (& mut self) -> INT_EVENT1_ISET_STXFIFOTRG_W < INT_EVENT1_ISET_SPEC , 3 > { INT_EVENT1_ISET_STXFIFOTRG_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Interrupt set\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_event1_iset::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct INT_EVENT1_ISET_SPEC ; impl crate :: RegisterSpec for INT_EVENT1_ISET_SPEC { type Ux = u32 ; } # [doc = "`write(|w| ..)` method takes [`int_event1_iset::W`](W) writer structure"] impl crate :: Writable for INT_EVENT1_ISET_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets INT_EVENT1_ISET to value 0"] impl crate :: Resettable for INT_EVENT1_ISET_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/opa1/cfg.rs:1:16556 [INFO] [stdout] | [INFO] [stdout] 1 | ... [must_use] pub fn cfg_chop (& mut self) -> CFG_CHOP_W < CFG_SPEC , 0 > { CFG_CHOP_W :: new (self) } # [doc = "Bit 2 - Enable output p... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `CFG` reader"] pub type R = crate :: R < CFG_SPEC > ; # [doc = "Register `CFG` writer"] pub type W = crate :: W < CFG_SPEC > ; # [doc = "Field `CFG_CHOP` reader - Chopping enable."] pub type CFG_CHOP_R = crate :: FieldReader < CFG_CHOP_A > ; # [doc = "Chopping enable.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum CFG_CHOP_A { # [doc = "0: OFF"] CFG_CHOP_OFF = 0 , # [doc = "1: ON"] CFG_CHOP_ON = 1 , # [doc = "2: AVGON"] CFG_CHOP_AVGON = 2 , } impl From < CFG_CHOP_A > for u8 { # [inline (always)] fn from (variant : CFG_CHOP_A) -> Self { variant as _ } } impl crate :: FieldSpec for CFG_CHOP_A { type Ux = u8 ; } impl CFG_CHOP_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < CFG_CHOP_A > { match self . bits { 0 => Some (CFG_CHOP_A :: CFG_CHOP_OFF) , 1 => Some (CFG_CHOP_A :: CFG_CHOP_ON) , 2 => Some (CFG_CHOP_A :: CFG_CHOP_AVGON) , _ => None , } } # [doc = "OFF"] # [inline (always)] pub fn is_cfg_chop_off (& self) -> bool { * self == CFG_CHOP_A :: CFG_CHOP_OFF } # [doc = "ON"] # [inline (always)] pub fn is_cfg_chop_on (& self) -> bool { * self == CFG_CHOP_A :: CFG_CHOP_ON } # [doc = "AVGON"] # [inline (always)] pub fn is_cfg_chop_avgon (& self) -> bool { * self == CFG_CHOP_A :: CFG_CHOP_AVGON } } # [doc = "Field `CFG_CHOP` writer - Chopping enable."] pub type CFG_CHOP_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 2 , O , CFG_CHOP_A > ; impl < 'a , REG , const O : u8 > CFG_CHOP_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "OFF"] # [inline (always)] pub fn cfg_chop_off (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_CHOP_A :: CFG_CHOP_OFF) } # [doc = "ON"] # [inline (always)] pub fn cfg_chop_on (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_CHOP_A :: CFG_CHOP_ON) } # [doc = "AVGON"] # [inline (always)] pub fn cfg_chop_avgon (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_CHOP_A :: CFG_CHOP_AVGON) } } # [doc = "Field `CFG_OUTPIN` reader - Enable output pin"] pub type CFG_OUTPIN_R = crate :: BitReader < CFG_OUTPIN_A > ; # [doc = "Enable output pin\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CFG_OUTPIN_A { # [doc = "0: DISABLED"] CFG_OUTPIN_DISABLED = 0 , # [doc = "1: ENABLED"] CFG_OUTPIN_ENABLED = 1 , } impl From < CFG_OUTPIN_A > for bool { # [inline (always)] fn from (variant : CFG_OUTPIN_A) -> Self { variant as u8 != 0 } } impl CFG_OUTPIN_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CFG_OUTPIN_A { match self . bits { false => CFG_OUTPIN_A :: CFG_OUTPIN_DISABLED , true => CFG_OUTPIN_A :: CFG_OUTPIN_ENABLED , } } # [doc = "DISABLED"] # [inline (always)] pub fn is_cfg_outpin_disabled (& self) -> bool { * self == CFG_OUTPIN_A :: CFG_OUTPIN_DISABLED } # [doc = "ENABLED"] # [inline (always)] pub fn is_cfg_outpin_enabled (& self) -> bool { * self == CFG_OUTPIN_A :: CFG_OUTPIN_ENABLED } } # [doc = "Field `CFG_OUTPIN` writer - Enable output pin"] pub type CFG_OUTPIN_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CFG_OUTPIN_A > ; impl < 'a , REG , const O : u8 > CFG_OUTPIN_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLED"] # [inline (always)] pub fn cfg_outpin_disabled (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_OUTPIN_A :: CFG_OUTPIN_DISABLED) } # [doc = "ENABLED"] # [inline (always)] pub fn cfg_outpin_enabled (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_OUTPIN_A :: CFG_OUTPIN_ENABLED) } } # [doc = "Field `CFG_PSEL` reader - Positive OA input selection. Please refer to the device specific datasheet for exact channels available."] pub type CFG_PSEL_R = crate :: FieldReader < CFG_PSEL_A > ; # [doc = "Positive OA input selection. Please refer to the device specific datasheet for exact channels available.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum CFG_PSEL_A { # [doc = "0: NC"] CFG_PSEL_NC = 0 , # [doc = "1: EXTPIN0"] CFG_PSEL_EXTPIN0 = 1 , # [doc = "2: EXTPIN1"] CFG_PSEL_EXTPIN1 = 2 , # [doc = "3: DAC12OUT"] CFG_PSEL_DAC12OUT = 3 , # [doc = "4: DAC8OUT"] CFG_PSEL_DAC8OUT = 4 , # [doc = "5: VREF"] CFG_PSEL_VREF = 5 , # [doc = "6: OANM1RTOP"] CFG_PSEL_OANM1RTOP = 6 , # [doc = "7: GPAMP_OUT_INT"] CFG_PSEL_GPAMP_OUT_INT = 7 , # [doc = "8: VSS"] CFG_PSEL_VSS = 8 , } impl From < CFG_PSEL_A > for u8 { # [inline (always)] fn from (variant : CFG_PSEL_A) -> Self { variant as _ } } impl crate :: FieldSpec for CFG_PSEL_A { type Ux = u8 ; } impl CFG_PSEL_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < CFG_PSEL_A > { match self . bits { 0 => Some (CFG_PSEL_A :: CFG_PSEL_NC) , 1 => Some (CFG_PSEL_A :: CFG_PSEL_EXTPIN0) , 2 => Some (CFG_PSEL_A :: CFG_PSEL_EXTPIN1) , 3 => Some (CFG_PSEL_A :: CFG_PSEL_DAC12OUT) , 4 => Some (CFG_PSEL_A :: CFG_PSEL_DAC8OUT) , 5 => Some (CFG_PSEL_A :: CFG_PSEL_VREF) , 6 => Some (CFG_PSEL_A :: CFG_PSEL_OANM1RTOP) , 7 => Some (CFG_PSEL_A :: CFG_PSEL_GPAMP_OUT_INT) , 8 => Some (CFG_PSEL_A :: CFG_PSEL_VSS) , _ => None , } } # [doc = "NC"] # [inline (always)] pub fn is_cfg_psel_nc (& self) -> bool { * self == CFG_PSEL_A :: CFG_PSEL_NC } # [doc = "EXTPIN0"] # [inline (always)] pub fn is_cfg_psel_extpin0 (& self) -> bool { * self == CFG_PSEL_A :: CFG_PSEL_EXTPIN0 } # [doc = "EXTPIN1"] # [inline (always)] pub fn is_cfg_psel_extpin1 (& self) -> bool { * self == CFG_PSEL_A :: CFG_PSEL_EXTPIN1 } # [doc = "DAC12OUT"] # [inline (always)] pub fn is_cfg_psel_dac12out (& self) -> bool { * self == CFG_PSEL_A :: CFG_PSEL_DAC12OUT } # [doc = "DAC8OUT"] # [inline (always)] pub fn is_cfg_psel_dac8out (& self) -> bool { * self == CFG_PSEL_A :: CFG_PSEL_DAC8OUT } # [doc = "VREF"] # [inline (always)] pub fn is_cfg_psel_vref (& self) -> bool { * self == CFG_PSEL_A :: CFG_PSEL_VREF } # [doc = "OANM1RTOP"] # [inline (always)] pub fn is_cfg_psel_oanm1rtop (& self) -> bool { * self == CFG_PSEL_A :: CFG_PSEL_OANM1RTOP } # [doc = "GPAMP_OUT_INT"] # [inline (always)] pub fn is_cfg_psel_gpamp_out_int (& self) -> bool { * self == CFG_PSEL_A :: CFG_PSEL_GPAMP_OUT_INT } # [doc = "VSS"] # [inline (always)] pub fn is_cfg_psel_vss (& self) -> bool { * self == CFG_PSEL_A :: CFG_PSEL_VSS } } # [doc = "Field `CFG_PSEL` writer - Positive OA input selection. Please refer to the device specific datasheet for exact channels available."] pub type CFG_PSEL_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 4 , O , CFG_PSEL_A > ; impl < 'a , REG , const O : u8 > CFG_PSEL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "NC"] # [inline (always)] pub fn cfg_psel_nc (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_PSEL_A :: CFG_PSEL_NC) } # [doc = "EXTPIN0"] # [inline (always)] pub fn cfg_psel_extpin0 (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_PSEL_A :: CFG_PSEL_EXTPIN0) } # [doc = "EXTPIN1"] # [inline (always)] pub fn cfg_psel_extpin1 (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_PSEL_A :: CFG_PSEL_EXTPIN1) } # [doc = "DAC12OUT"] # [inline (always)] pub fn cfg_psel_dac12out (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_PSEL_A :: CFG_PSEL_DAC12OUT) } # [doc = "DAC8OUT"] # [inline (always)] pub fn cfg_psel_dac8out (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_PSEL_A :: CFG_PSEL_DAC8OUT) } # [doc = "VREF"] # [inline (always)] pub fn cfg_psel_vref (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_PSEL_A :: CFG_PSEL_VREF) } # [doc = "OANM1RTOP"] # [inline (always)] pub fn cfg_psel_oanm1rtop (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_PSEL_A :: CFG_PSEL_OANM1RTOP) } # [doc = "GPAMP_OUT_INT"] # [inline (always)] pub fn cfg_psel_gpamp_out_int (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_PSEL_A :: CFG_PSEL_GPAMP_OUT_INT) } # [doc = "VSS"] # [inline (always)] pub fn cfg_psel_vss (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_PSEL_A :: CFG_PSEL_VSS) } } # [doc = "Field `CFG_NSEL` reader - Negative OA input selection. Please refer to the device specific datasheet for exact channels available."] pub type CFG_NSEL_R = crate :: FieldReader < CFG_NSEL_A > ; # [doc = "Negative OA input selection. Please refer to the device specific datasheet for exact channels available.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum CFG_NSEL_A { # [doc = "0: NC"] CFG_NSEL_NC = 0 , # [doc = "1: EXTPIN0"] CFG_NSEL_EXTPIN0 = 1 , # [doc = "2: EXTPIN1"] CFG_NSEL_EXTPIN1 = 2 , # [doc = "3: OANP1RBOT"] CFG_NSEL_OANP1RBOT = 3 , # [doc = "4: OANRTAP"] CFG_NSEL_OANRTAP = 4 , # [doc = "5: OANRTOP"] CFG_NSEL_OANRTOP = 5 , # [doc = "6: SPARE"] CFG_NSEL_SPARE = 6 , } impl From < CFG_NSEL_A > for u8 { # [inline (always)] fn from (variant : CFG_NSEL_A) -> Self { variant as _ } } impl crate :: FieldSpec for CFG_NSEL_A { type Ux = u8 ; } impl CFG_NSEL_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < CFG_NSEL_A > { match self . bits { 0 => Some (CFG_NSEL_A :: CFG_NSEL_NC) , 1 => Some (CFG_NSEL_A :: CFG_NSEL_EXTPIN0) , 2 => Some (CFG_NSEL_A :: CFG_NSEL_EXTPIN1) , 3 => Some (CFG_NSEL_A :: CFG_NSEL_OANP1RBOT) , 4 => Some (CFG_NSEL_A :: CFG_NSEL_OANRTAP) , 5 => Some (CFG_NSEL_A :: CFG_NSEL_OANRTOP) , 6 => Some (CFG_NSEL_A :: CFG_NSEL_SPARE) , _ => None , } } # [doc = "NC"] # [inline (always)] pub fn is_cfg_nsel_nc (& self) -> bool { * self == CFG_NSEL_A :: CFG_NSEL_NC } # [doc = "EXTPIN0"] # [inline (always)] pub fn is_cfg_nsel_extpin0 (& self) -> bool { * self == CFG_NSEL_A :: CFG_NSEL_EXTPIN0 } # [doc = "EXTPIN1"] # [inline (always)] pub fn is_cfg_nsel_extpin1 (& self) -> bool { * self == CFG_NSEL_A :: CFG_NSEL_EXTPIN1 } # [doc = "OANP1RBOT"] # [inline (always)] pub fn is_cfg_nsel_oanp1rbot (& self) -> bool { * self == CFG_NSEL_A :: CFG_NSEL_OANP1RBOT } # [doc = "OANRTAP"] # [inline (always)] pub fn is_cfg_nsel_oanrtap (& self) -> bool { * self == CFG_NSEL_A :: CFG_NSEL_OANRTAP } # [doc = "OANRTOP"] # [inline (always)] pub fn is_cfg_nsel_oanrtop (& self) -> bool { * self == CFG_NSEL_A :: CFG_NSEL_OANRTOP } # [doc = "SPARE"] # [inline (always)] pub fn is_cfg_nsel_spare (& self) -> bool { * self == CFG_NSEL_A :: CFG_NSEL_SPARE } } # [doc = "Field `CFG_NSEL` writer - Negative OA input selection. Please refer to the device specific datasheet for exact channels available."] pub type CFG_NSEL_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 3 , O , CFG_NSEL_A > ; impl < 'a , REG , const O : u8 > CFG_NSEL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "NC"] # [inline (always)] pub fn cfg_nsel_nc (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_NSEL_A :: CFG_NSEL_NC) } # [doc = "EXTPIN0"] # [inline (always)] pub fn cfg_nsel_extpin0 (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_NSEL_A :: CFG_NSEL_EXTPIN0) } # [doc = "EXTPIN1"] # [inline (always)] pub fn cfg_nsel_extpin1 (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_NSEL_A :: CFG_NSEL_EXTPIN1) } # [doc = "OANP1RBOT"] # [inline (always)] pub fn cfg_nsel_oanp1rbot (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_NSEL_A :: CFG_NSEL_OANP1RBOT) } # [doc = "OANRTAP"] # [inline (always)] pub fn cfg_nsel_oanrtap (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_NSEL_A :: CFG_NSEL_OANRTAP) } # [doc = "OANRTOP"] # [inline (always)] pub fn cfg_nsel_oanrtop (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_NSEL_A :: CFG_NSEL_OANRTOP) } # [doc = "SPARE"] # [inline (always)] pub fn cfg_nsel_spare (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_NSEL_A :: CFG_NSEL_SPARE) } } # [doc = "Field `CFG_MSEL` reader - MSEL Mux selection. Please refer to the device specific datasheet for exact channels available."] pub type CFG_MSEL_R = crate :: FieldReader < CFG_MSEL_A > ; # [doc = "MSEL Mux selection. Please refer to the device specific datasheet for exact channels available.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum CFG_MSEL_A { # [doc = "0: NC"] CFG_MSEL_NC = 0 , # [doc = "1: EXTNPIN1"] CFG_MSEL_EXTNPIN1 = 1 , # [doc = "2: VSS"] CFG_MSEL_VSS = 2 , # [doc = "3: DAC12OUT"] CFG_MSEL_DAC12OUT = 3 , # [doc = "4: OANM1RTOP"] CFG_MSEL_OANM1RTOP = 4 , } impl From < CFG_MSEL_A > for u8 { # [inline (always)] fn from (variant : CFG_MSEL_A) -> Self { variant as _ } } impl crate :: FieldSpec for CFG_MSEL_A { type Ux = u8 ; } impl CFG_MSEL_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < CFG_MSEL_A > { match self . bits { 0 => Some (CFG_MSEL_A :: CFG_MSEL_NC) , 1 => Some (CFG_MSEL_A :: CFG_MSEL_EXTNPIN1) , 2 => Some (CFG_MSEL_A :: CFG_MSEL_VSS) , 3 => Some (CFG_MSEL_A :: CFG_MSEL_DAC12OUT) , 4 => Some (CFG_MSEL_A :: CFG_MSEL_OANM1RTOP) , _ => None , } } # [doc = "NC"] # [inline (always)] pub fn is_cfg_msel_nc (& self) -> bool { * self == CFG_MSEL_A :: CFG_MSEL_NC } # [doc = "EXTNPIN1"] # [inline (always)] pub fn is_cfg_msel_extnpin1 (& self) -> bool { * self == CFG_MSEL_A :: CFG_MSEL_EXTNPIN1 } # [doc = "VSS"] # [inline (always)] pub fn is_cfg_msel_vss (& self) -> bool { * self == CFG_MSEL_A :: CFG_MSEL_VSS } # [doc = "DAC12OUT"] # [inline (always)] pub fn is_cfg_msel_dac12out (& self) -> bool { * self == CFG_MSEL_A :: CFG_MSEL_DAC12OUT } # [doc = "OANM1RTOP"] # [inline (always)] pub fn is_cfg_msel_oanm1rtop (& self) -> bool { * self == CFG_MSEL_A :: CFG_MSEL_OANM1RTOP } } # [doc = "Field `CFG_MSEL` writer - MSEL Mux selection. Please refer to the device specific datasheet for exact channels available."] pub type CFG_MSEL_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 3 , O , CFG_MSEL_A > ; impl < 'a , REG , const O : u8 > CFG_MSEL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "NC"] # [inline (always)] pub fn cfg_msel_nc (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_MSEL_A :: CFG_MSEL_NC) } # [doc = "EXTNPIN1"] # [inline (always)] pub fn cfg_msel_extnpin1 (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_MSEL_A :: CFG_MSEL_EXTNPIN1) } # [doc = "VSS"] # [inline (always)] pub fn cfg_msel_vss (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_MSEL_A :: CFG_MSEL_VSS) } # [doc = "DAC12OUT"] # [inline (always)] pub fn cfg_msel_dac12out (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_MSEL_A :: CFG_MSEL_DAC12OUT) } # [doc = "OANM1RTOP"] # [inline (always)] pub fn cfg_msel_oanm1rtop (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_MSEL_A :: CFG_MSEL_OANM1RTOP) } } # [doc = "Field `CFG_GAIN` reader - Gain setting. Refer to TRM for enumeration information."] pub type CFG_GAIN_R = crate :: FieldReader ; # [doc = "Field `CFG_GAIN` writer - Gain setting. Refer to TRM for enumeration information."] pub type CFG_GAIN_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 3 , O > ; impl R { # [doc = "Bits 0:1 - Chopping enable."] # [inline (always)] pub fn cfg_chop (& self) -> CFG_CHOP_R { CFG_CHOP_R :: new ((self . bits & 3) as u8) } # [doc = "Bit 2 - Enable output pin"] # [inline (always)] pub fn cfg_outpin (& self) -> CFG_OUTPIN_R { CFG_OUTPIN_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bits 3:6 - Positive OA input selection. Please refer to the device specific datasheet for exact channels available."] # [inline (always)] pub fn cfg_psel (& self) -> CFG_PSEL_R { CFG_PSEL_R :: new (((self . bits >> 3) & 0x0f) as u8) } # [doc = "Bits 7:9 - Negative OA input selection. Please refer to the device specific datasheet for exact channels available."] # [inline (always)] pub fn cfg_nsel (& self) -> CFG_NSEL_R { CFG_NSEL_R :: new (((self . bits >> 7) & 7) as u8) } # [doc = "Bits 10:12 - MSEL Mux selection. Please refer to the device specific datasheet for exact channels available."] # [inline (always)] pub fn cfg_msel (& self) -> CFG_MSEL_R { CFG_MSEL_R :: new (((self . bits >> 10) & 7) as u8) } # [doc = "Bits 13:15 - Gain setting. Refer to TRM for enumeration information."] # [inline (always)] pub fn cfg_gain (& self) -> CFG_GAIN_R { CFG_GAIN_R :: new (((self . bits >> 13) & 7) as u8) } } impl W { # [doc = "Bits 0:1 - Chopping enable."] # [inline (always)] # [must_use] pub fn cfg_chop (& mut self) -> CFG_CHOP_W <'_, CFG_SPEC , 0 > { CFG_CHOP_W :: new (self) } # [doc = "Bit 2 - Enable output pin"] # [inline (always)] # [must_use] pub fn cfg_outpin (& mut self) -> CFG_OUTPIN_W < CFG_SPEC , 2 > { CFG_OUTPIN_W :: new (self) } # [doc = "Bits 3:6 - Positive OA input selection. Please refer to the device specific datasheet for exact channels available."] # [inline (always)] # [must_use] pub fn cfg_psel (& mut self) -> CFG_PSEL_W < CFG_SPEC , 3 > { CFG_PSEL_W :: new (self) } # [doc = "Bits 7:9 - Negative OA input selection. Please refer to the device specific datasheet for exact channels available."] # [inline (always)] # [must_use] pub fn cfg_nsel (& mut self) -> CFG_NSEL_W < CFG_SPEC , 7 > { CFG_NSEL_W :: new (self) } # [doc = "Bits 10:12 - MSEL Mux selection. Please refer to the device specific datasheet for exact channels available."] # [inline (always)] # [must_use] pub fn cfg_msel (& mut self) -> CFG_MSEL_W < CFG_SPEC , 10 > { CFG_MSEL_W :: new (self) } # [doc = "Bits 13:15 - Gain setting. Refer to TRM for enumeration information."] # [inline (always)] # [must_use] pub fn cfg_gain (& mut self) -> CFG_GAIN_W < CFG_SPEC , 13 > { CFG_GAIN_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Configuration Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CFG_SPEC ; impl crate :: RegisterSpec for CFG_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`cfg::R`](R) reader structure"] impl crate :: Readable for CFG_SPEC { } # [doc = "`write(|w| ..)` method takes [`cfg::W`](W) writer structure"] impl crate :: Writable for CFG_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets CFG to value 0"] impl crate :: Resettable for CFG_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/i2c0/sackctl.rs:1:13033 [INFO] [stdout] | [INFO] [stdout] 1 | ... pub fn sackctl_ackoen (& mut self) -> SACKCTL_ACKOEN_W < SACKCTL_SPEC , 0 > { SACKCTL_ACKOEN_W :: new (self) } # [doc = "Bit 1 - I2C ... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `SACKCTL` reader"] pub type R = crate :: R < SACKCTL_SPEC > ; # [doc = "Register `SACKCTL` writer"] pub type W = crate :: W < SACKCTL_SPEC > ; # [doc = "Field `SACKCTL_ACKOEN` reader - I2C Slave ACK Override Enable"] pub type SACKCTL_ACKOEN_R = crate :: BitReader < SACKCTL_ACKOEN_A > ; # [doc = "I2C Slave ACK Override Enable\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum SACKCTL_ACKOEN_A { # [doc = "0: DISABLE"] SACKCTL_ACKOEN_DISABLE = 0 , # [doc = "1: ENABLE"] SACKCTL_ACKOEN_ENABLE = 1 , } impl From < SACKCTL_ACKOEN_A > for bool { # [inline (always)] fn from (variant : SACKCTL_ACKOEN_A) -> Self { variant as u8 != 0 } } impl SACKCTL_ACKOEN_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> SACKCTL_ACKOEN_A { match self . bits { false => SACKCTL_ACKOEN_A :: SACKCTL_ACKOEN_DISABLE , true => SACKCTL_ACKOEN_A :: SACKCTL_ACKOEN_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_sackctl_ackoen_disable (& self) -> bool { * self == SACKCTL_ACKOEN_A :: SACKCTL_ACKOEN_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_sackctl_ackoen_enable (& self) -> bool { * self == SACKCTL_ACKOEN_A :: SACKCTL_ACKOEN_ENABLE } } # [doc = "Field `SACKCTL_ACKOEN` writer - I2C Slave ACK Override Enable"] pub type SACKCTL_ACKOEN_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , SACKCTL_ACKOEN_A > ; impl < 'a , REG , const O : u8 > SACKCTL_ACKOEN_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn sackctl_ackoen_disable (self) -> & 'a mut crate :: W < REG > { self . variant (SACKCTL_ACKOEN_A :: SACKCTL_ACKOEN_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn sackctl_ackoen_enable (self) -> & 'a mut crate :: W < REG > { self . variant (SACKCTL_ACKOEN_A :: SACKCTL_ACKOEN_ENABLE) } } # [doc = "Field `SACKCTL_ACKOVAL` reader - I2C Slave ACK Override Value Note: for General Call this bit will be ignored if set to NACK and slave continues to receive data."] pub type SACKCTL_ACKOVAL_R = crate :: BitReader < SACKCTL_ACKOVAL_A > ; # [doc = "I2C Slave ACK Override Value Note: for General Call this bit will be ignored if set to NACK and slave continues to receive data.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum SACKCTL_ACKOVAL_A { # [doc = "0: DISABLE"] SACKCTL_ACKOVAL_DISABLE = 0 , # [doc = "1: ENABLE"] SACKCTL_ACKOVAL_ENABLE = 1 , } impl From < SACKCTL_ACKOVAL_A > for bool { # [inline (always)] fn from (variant : SACKCTL_ACKOVAL_A) -> Self { variant as u8 != 0 } } impl SACKCTL_ACKOVAL_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> SACKCTL_ACKOVAL_A { match self . bits { false => SACKCTL_ACKOVAL_A :: SACKCTL_ACKOVAL_DISABLE , true => SACKCTL_ACKOVAL_A :: SACKCTL_ACKOVAL_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_sackctl_ackoval_disable (& self) -> bool { * self == SACKCTL_ACKOVAL_A :: SACKCTL_ACKOVAL_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_sackctl_ackoval_enable (& self) -> bool { * self == SACKCTL_ACKOVAL_A :: SACKCTL_ACKOVAL_ENABLE } } # [doc = "Field `SACKCTL_ACKOVAL` writer - I2C Slave ACK Override Value Note: for General Call this bit will be ignored if set to NACK and slave continues to receive data."] pub type SACKCTL_ACKOVAL_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , SACKCTL_ACKOVAL_A > ; impl < 'a , REG , const O : u8 > SACKCTL_ACKOVAL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn sackctl_ackoval_disable (self) -> & 'a mut crate :: W < REG > { self . variant (SACKCTL_ACKOVAL_A :: SACKCTL_ACKOVAL_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn sackctl_ackoval_enable (self) -> & 'a mut crate :: W < REG > { self . variant (SACKCTL_ACKOVAL_A :: SACKCTL_ACKOVAL_ENABLE) } } # [doc = "Field `SACKCTL_ACKOEN_ON_START` reader - When set this bit will automatically turn on the Slave ACKOEN field following a Start Condition."] pub type SACKCTL_ACKOEN_ON_START_R = crate :: BitReader < SACKCTL_ACKOEN_ON_START_A > ; # [doc = "When set this bit will automatically turn on the Slave ACKOEN field following a Start Condition.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum SACKCTL_ACKOEN_ON_START_A { # [doc = "0: DISABLE"] SACKCTL_ACKOEN_ON_START_DISABLE = 0 , # [doc = "1: ENABLE"] SACKCTL_ACKOEN_ON_START_ENABLE = 1 , } impl From < SACKCTL_ACKOEN_ON_START_A > for bool { # [inline (always)] fn from (variant : SACKCTL_ACKOEN_ON_START_A) -> Self { variant as u8 != 0 } } impl SACKCTL_ACKOEN_ON_START_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> SACKCTL_ACKOEN_ON_START_A { match self . bits { false => SACKCTL_ACKOEN_ON_START_A :: SACKCTL_ACKOEN_ON_START_DISABLE , true => SACKCTL_ACKOEN_ON_START_A :: SACKCTL_ACKOEN_ON_START_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_sackctl_ackoen_on_start_disable (& self) -> bool { * self == SACKCTL_ACKOEN_ON_START_A :: SACKCTL_ACKOEN_ON_START_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_sackctl_ackoen_on_start_enable (& self) -> bool { * self == SACKCTL_ACKOEN_ON_START_A :: SACKCTL_ACKOEN_ON_START_ENABLE } } # [doc = "Field `SACKCTL_ACKOEN_ON_START` writer - When set this bit will automatically turn on the Slave ACKOEN field following a Start Condition."] pub type SACKCTL_ACKOEN_ON_START_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , SACKCTL_ACKOEN_ON_START_A > ; impl < 'a , REG , const O : u8 > SACKCTL_ACKOEN_ON_START_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn sackctl_ackoen_on_start_disable (self) -> & 'a mut crate :: W < REG > { self . variant (SACKCTL_ACKOEN_ON_START_A :: SACKCTL_ACKOEN_ON_START_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn sackctl_ackoen_on_start_enable (self) -> & 'a mut crate :: W < REG > { self . variant (SACKCTL_ACKOEN_ON_START_A :: SACKCTL_ACKOEN_ON_START_ENABLE) } } # [doc = "Field `SACKCTL_ACKOEN_ON_PECNEXT` reader - When set this bit will automatically turn on the Slave ACKOEN field following the ACK/NACK of the byte received just prior to the PEC byte. Note that when ACKOEN is set the PEC byte will not automatically be ACKed/NACKed by the State Machine and FW must perform this function by writing SLAVE_SACKCTL."] pub type SACKCTL_ACKOEN_ON_PECNEXT_R = crate :: BitReader < SACKCTL_ACKOEN_ON_PECNEXT_A > ; # [doc = "When set this bit will automatically turn on the Slave ACKOEN field following the ACK/NACK of the byte received just prior to the PEC byte. Note that when ACKOEN is set the PEC byte will not automatically be ACKed/NACKed by the State Machine and FW must perform this function by writing SLAVE_SACKCTL.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum SACKCTL_ACKOEN_ON_PECNEXT_A { # [doc = "0: DISABLE"] SACKCTL_ACKOEN_ON_PECNEXT_DISABLE = 0 , # [doc = "1: ENABLE"] SACKCTL_ACKOEN_ON_PECNEXT_ENABLE = 1 , } impl From < SACKCTL_ACKOEN_ON_PECNEXT_A > for bool { # [inline (always)] fn from (variant : SACKCTL_ACKOEN_ON_PECNEXT_A) -> Self { variant as u8 != 0 } } impl SACKCTL_ACKOEN_ON_PECNEXT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> SACKCTL_ACKOEN_ON_PECNEXT_A { match self . bits { false => SACKCTL_ACKOEN_ON_PECNEXT_A :: SACKCTL_ACKOEN_ON_PECNEXT_DISABLE , true => SACKCTL_ACKOEN_ON_PECNEXT_A :: SACKCTL_ACKOEN_ON_PECNEXT_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_sackctl_ackoen_on_pecnext_disable (& self) -> bool { * self == SACKCTL_ACKOEN_ON_PECNEXT_A :: SACKCTL_ACKOEN_ON_PECNEXT_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_sackctl_ackoen_on_pecnext_enable (& self) -> bool { * self == SACKCTL_ACKOEN_ON_PECNEXT_A :: SACKCTL_ACKOEN_ON_PECNEXT_ENABLE } } # [doc = "Field `SACKCTL_ACKOEN_ON_PECNEXT` writer - When set this bit will automatically turn on the Slave ACKOEN field following the ACK/NACK of the byte received just prior to the PEC byte. Note that when ACKOEN is set the PEC byte will not automatically be ACKed/NACKed by the State Machine and FW must perform this function by writing SLAVE_SACKCTL."] pub type SACKCTL_ACKOEN_ON_PECNEXT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , SACKCTL_ACKOEN_ON_PECNEXT_A > ; impl < 'a , REG , const O : u8 > SACKCTL_ACKOEN_ON_PECNEXT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn sackctl_ackoen_on_pecnext_disable (self) -> & 'a mut crate :: W < REG > { self . variant (SACKCTL_ACKOEN_ON_PECNEXT_A :: SACKCTL_ACKOEN_ON_PECNEXT_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn sackctl_ackoen_on_pecnext_enable (self) -> & 'a mut crate :: W < REG > { self . variant (SACKCTL_ACKOEN_ON_PECNEXT_A :: SACKCTL_ACKOEN_ON_PECNEXT_ENABLE) } } # [doc = "Field `SACKCTL_ACKOEN_ON_PECDONE` reader - When set this bit will automatically turn on the Slave ACKOEN field following the ACK/NACK of the received PEC byte."] pub type SACKCTL_ACKOEN_ON_PECDONE_R = crate :: BitReader < SACKCTL_ACKOEN_ON_PECDONE_A > ; # [doc = "When set this bit will automatically turn on the Slave ACKOEN field following the ACK/NACK of the received PEC byte.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum SACKCTL_ACKOEN_ON_PECDONE_A { # [doc = "0: DISABLE"] SACKCTL_ACKOEN_ON_PECDONE_DISABLE = 0 , # [doc = "1: ENABLE"] SACKCTL_ACKOEN_ON_PECDONE_ENABLE = 1 , } impl From < SACKCTL_ACKOEN_ON_PECDONE_A > for bool { # [inline (always)] fn from (variant : SACKCTL_ACKOEN_ON_PECDONE_A) -> Self { variant as u8 != 0 } } impl SACKCTL_ACKOEN_ON_PECDONE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> SACKCTL_ACKOEN_ON_PECDONE_A { match self . bits { false => SACKCTL_ACKOEN_ON_PECDONE_A :: SACKCTL_ACKOEN_ON_PECDONE_DISABLE , true => SACKCTL_ACKOEN_ON_PECDONE_A :: SACKCTL_ACKOEN_ON_PECDONE_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_sackctl_ackoen_on_pecdone_disable (& self) -> bool { * self == SACKCTL_ACKOEN_ON_PECDONE_A :: SACKCTL_ACKOEN_ON_PECDONE_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_sackctl_ackoen_on_pecdone_enable (& self) -> bool { * self == SACKCTL_ACKOEN_ON_PECDONE_A :: SACKCTL_ACKOEN_ON_PECDONE_ENABLE } } # [doc = "Field `SACKCTL_ACKOEN_ON_PECDONE` writer - When set this bit will automatically turn on the Slave ACKOEN field following the ACK/NACK of the received PEC byte."] pub type SACKCTL_ACKOEN_ON_PECDONE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , SACKCTL_ACKOEN_ON_PECDONE_A > ; impl < 'a , REG , const O : u8 > SACKCTL_ACKOEN_ON_PECDONE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn sackctl_ackoen_on_pecdone_disable (self) -> & 'a mut crate :: W < REG > { self . variant (SACKCTL_ACKOEN_ON_PECDONE_A :: SACKCTL_ACKOEN_ON_PECDONE_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn sackctl_ackoen_on_pecdone_enable (self) -> & 'a mut crate :: W < REG > { self . variant (SACKCTL_ACKOEN_ON_PECDONE_A :: SACKCTL_ACKOEN_ON_PECDONE_ENABLE) } } impl R { # [doc = "Bit 0 - I2C Slave ACK Override Enable"] # [inline (always)] pub fn sackctl_ackoen (& self) -> SACKCTL_ACKOEN_R { SACKCTL_ACKOEN_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - I2C Slave ACK Override Value Note: for General Call this bit will be ignored if set to NACK and slave continues to receive data."] # [inline (always)] pub fn sackctl_ackoval (& self) -> SACKCTL_ACKOVAL_R { SACKCTL_ACKOVAL_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - When set this bit will automatically turn on the Slave ACKOEN field following a Start Condition."] # [inline (always)] pub fn sackctl_ackoen_on_start (& self) -> SACKCTL_ACKOEN_ON_START_R { SACKCTL_ACKOEN_ON_START_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - When set this bit will automatically turn on the Slave ACKOEN field following the ACK/NACK of the byte received just prior to the PEC byte. Note that when ACKOEN is set the PEC byte will not automatically be ACKed/NACKed by the State Machine and FW must perform this function by writing SLAVE_SACKCTL."] # [inline (always)] pub fn sackctl_ackoen_on_pecnext (& self) -> SACKCTL_ACKOEN_ON_PECNEXT_R { SACKCTL_ACKOEN_ON_PECNEXT_R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - When set this bit will automatically turn on the Slave ACKOEN field following the ACK/NACK of the received PEC byte."] # [inline (always)] pub fn sackctl_ackoen_on_pecdone (& self) -> SACKCTL_ACKOEN_ON_PECDONE_R { SACKCTL_ACKOEN_ON_PECDONE_R :: new (((self . bits >> 4) & 1) != 0) } } impl W { # [doc = "Bit 0 - I2C Slave ACK Override Enable"] # [inline (always)] # [must_use] pub fn sackctl_ackoen (& mut self) -> SACKCTL_ACKOEN_W <'_, SACKCTL_SPEC , 0 > { SACKCTL_ACKOEN_W :: new (self) } # [doc = "Bit 1 - I2C Slave ACK Override Value Note: for General Call this bit will be ignored if set to NACK and slave continues to receive data."] # [inline (always)] # [must_use] pub fn sackctl_ackoval (& mut self) -> SACKCTL_ACKOVAL_W < SACKCTL_SPEC , 1 > { SACKCTL_ACKOVAL_W :: new (self) } # [doc = "Bit 2 - When set this bit will automatically turn on the Slave ACKOEN field following a Start Condition."] # [inline (always)] # [must_use] pub fn sackctl_ackoen_on_start (& mut self) -> SACKCTL_ACKOEN_ON_START_W < SACKCTL_SPEC , 2 > { SACKCTL_ACKOEN_ON_START_W :: new (self) } # [doc = "Bit 3 - When set this bit will automatically turn on the Slave ACKOEN field following the ACK/NACK of the byte received just prior to the PEC byte. Note that when ACKOEN is set the PEC byte will not automatically be ACKed/NACKed by the State Machine and FW must perform this function by writing SLAVE_SACKCTL."] # [inline (always)] # [must_use] pub fn sackctl_ackoen_on_pecnext (& mut self) -> SACKCTL_ACKOEN_ON_PECNEXT_W < SACKCTL_SPEC , 3 > { SACKCTL_ACKOEN_ON_PECNEXT_W :: new (self) } # [doc = "Bit 4 - When set this bit will automatically turn on the Slave ACKOEN field following the ACK/NACK of the received PEC byte."] # [inline (always)] # [must_use] pub fn sackctl_ackoen_on_pecdone (& mut self) -> SACKCTL_ACKOEN_ON_PECDONE_W < SACKCTL_SPEC , 4 > { SACKCTL_ACKOEN_ON_PECDONE_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "I2C Slave ACK Control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sackctl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sackctl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct SACKCTL_SPEC ; impl crate :: RegisterSpec for SACKCTL_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`sackctl::R`](R) reader structure"] impl crate :: Readable for SACKCTL_SPEC { } # [doc = "`write(|w| ..)` method takes [`sackctl::W`](W) writer structure"] impl crate :: Writable for SACKCTL_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets SACKCTL to value 0"] impl crate :: Resettable for SACKCTL_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/cpuss/ctl.rs:1:7350 [INFO] [stdout] | [INFO] [stdout] 1 | ..._use] pub fn ctl_prefetch (& mut self) -> CTL_PREFETCH_W < CTL_SPEC , 0 > { CTL_PREFETCH_W :: new (self) } # [doc = "Bit 1 - Used to e... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `CTL` reader"] pub type R = crate :: R < CTL_SPEC > ; # [doc = "Register `CTL` writer"] pub type W = crate :: W < CTL_SPEC > ; # [doc = "Field `CTL_PREFETCH` reader - Used to enable/disable instruction prefetch to Flash."] pub type CTL_PREFETCH_R = crate :: BitReader < CTL_PREFETCH_A > ; # [doc = "Used to enable/disable instruction prefetch to Flash.\n\nValue on reset: 1"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CTL_PREFETCH_A { # [doc = "0: DISABLE"] CTL_PREFETCH_DISABLE = 0 , # [doc = "1: ENABLE"] CTL_PREFETCH_ENABLE = 1 , } impl From < CTL_PREFETCH_A > for bool { # [inline (always)] fn from (variant : CTL_PREFETCH_A) -> Self { variant as u8 != 0 } } impl CTL_PREFETCH_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CTL_PREFETCH_A { match self . bits { false => CTL_PREFETCH_A :: CTL_PREFETCH_DISABLE , true => CTL_PREFETCH_A :: CTL_PREFETCH_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_ctl_prefetch_disable (& self) -> bool { * self == CTL_PREFETCH_A :: CTL_PREFETCH_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_ctl_prefetch_enable (& self) -> bool { * self == CTL_PREFETCH_A :: CTL_PREFETCH_ENABLE } } # [doc = "Field `CTL_PREFETCH` writer - Used to enable/disable instruction prefetch to Flash."] pub type CTL_PREFETCH_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL_PREFETCH_A > ; impl < 'a , REG , const O : u8 > CTL_PREFETCH_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn ctl_prefetch_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL_PREFETCH_A :: CTL_PREFETCH_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn ctl_prefetch_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL_PREFETCH_A :: CTL_PREFETCH_ENABLE) } } # [doc = "Field `CTL_ICACHE` reader - Used to enable/disable Instruction caching on flash access."] pub type CTL_ICACHE_R = crate :: BitReader < CTL_ICACHE_A > ; # [doc = "Used to enable/disable Instruction caching on flash access.\n\nValue on reset: 1"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CTL_ICACHE_A { # [doc = "0: DISABLE"] CTL_ICACHE_DISABLE = 0 , # [doc = "1: ENABLE"] CTL_ICACHE_ENABLE = 1 , } impl From < CTL_ICACHE_A > for bool { # [inline (always)] fn from (variant : CTL_ICACHE_A) -> Self { variant as u8 != 0 } } impl CTL_ICACHE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CTL_ICACHE_A { match self . bits { false => CTL_ICACHE_A :: CTL_ICACHE_DISABLE , true => CTL_ICACHE_A :: CTL_ICACHE_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_ctl_icache_disable (& self) -> bool { * self == CTL_ICACHE_A :: CTL_ICACHE_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_ctl_icache_enable (& self) -> bool { * self == CTL_ICACHE_A :: CTL_ICACHE_ENABLE } } # [doc = "Field `CTL_ICACHE` writer - Used to enable/disable Instruction caching on flash access."] pub type CTL_ICACHE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL_ICACHE_A > ; impl < 'a , REG , const O : u8 > CTL_ICACHE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn ctl_icache_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL_ICACHE_A :: CTL_ICACHE_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn ctl_icache_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL_ICACHE_A :: CTL_ICACHE_ENABLE) } } # [doc = "Field `CTL_LITEN` reader - Literal caching and prefetch enable. This bit is a subset of ICACHE/PREFETCH bit i.e. literal caching or literal prefetching will only happen if ICACHE or PREFETCH bits have been set respectively When enabled, the cache and prefetcher structures inside CPUSS will cache and prefetch literals When disabled, the cache and prefetcher structures inside CPUSS will not cache and prefetch literals"] pub type CTL_LITEN_R = crate :: BitReader < CTL_LITEN_A > ; # [doc = "Literal caching and prefetch enable. This bit is a subset of ICACHE/PREFETCH bit i.e. literal caching or literal prefetching will only happen if ICACHE or PREFETCH bits have been set respectively When enabled, the cache and prefetcher structures inside CPUSS will cache and prefetch literals When disabled, the cache and prefetcher structures inside CPUSS will not cache and prefetch literals\n\nValue on reset: 1"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CTL_LITEN_A { # [doc = "0: DISABLE"] CTL_LITEN_DISABLE = 0 , # [doc = "1: ENABLE"] CTL_LITEN_ENABLE = 1 , } impl From < CTL_LITEN_A > for bool { # [inline (always)] fn from (variant : CTL_LITEN_A) -> Self { variant as u8 != 0 } } impl CTL_LITEN_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CTL_LITEN_A { match self . bits { false => CTL_LITEN_A :: CTL_LITEN_DISABLE , true => CTL_LITEN_A :: CTL_LITEN_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_ctl_liten_disable (& self) -> bool { * self == CTL_LITEN_A :: CTL_LITEN_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_ctl_liten_enable (& self) -> bool { * self == CTL_LITEN_A :: CTL_LITEN_ENABLE } } # [doc = "Field `CTL_LITEN` writer - Literal caching and prefetch enable. This bit is a subset of ICACHE/PREFETCH bit i.e. literal caching or literal prefetching will only happen if ICACHE or PREFETCH bits have been set respectively When enabled, the cache and prefetcher structures inside CPUSS will cache and prefetch literals When disabled, the cache and prefetcher structures inside CPUSS will not cache and prefetch literals"] pub type CTL_LITEN_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL_LITEN_A > ; impl < 'a , REG , const O : u8 > CTL_LITEN_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn ctl_liten_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL_LITEN_A :: CTL_LITEN_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn ctl_liten_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL_LITEN_A :: CTL_LITEN_ENABLE) } } impl R { # [doc = "Bit 0 - Used to enable/disable instruction prefetch to Flash."] # [inline (always)] pub fn ctl_prefetch (& self) -> CTL_PREFETCH_R { CTL_PREFETCH_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - Used to enable/disable Instruction caching on flash access."] # [inline (always)] pub fn ctl_icache (& self) -> CTL_ICACHE_R { CTL_ICACHE_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - Literal caching and prefetch enable. This bit is a subset of ICACHE/PREFETCH bit i.e. literal caching or literal prefetching will only happen if ICACHE or PREFETCH bits have been set respectively When enabled, the cache and prefetcher structures inside CPUSS will cache and prefetch literals When disabled, the cache and prefetcher structures inside CPUSS will not cache and prefetch literals"] # [inline (always)] pub fn ctl_liten (& self) -> CTL_LITEN_R { CTL_LITEN_R :: new (((self . bits >> 2) & 1) != 0) } } impl W { # [doc = "Bit 0 - Used to enable/disable instruction prefetch to Flash."] # [inline (always)] # [must_use] pub fn ctl_prefetch (& mut self) -> CTL_PREFETCH_W <'_, CTL_SPEC , 0 > { CTL_PREFETCH_W :: new (self) } # [doc = "Bit 1 - Used to enable/disable Instruction caching on flash access."] # [inline (always)] # [must_use] pub fn ctl_icache (& mut self) -> CTL_ICACHE_W < CTL_SPEC , 1 > { CTL_ICACHE_W :: new (self) } # [doc = "Bit 2 - Literal caching and prefetch enable. This bit is a subset of ICACHE/PREFETCH bit i.e. literal caching or literal prefetching will only happen if ICACHE or PREFETCH bits have been set respectively When enabled, the cache and prefetcher structures inside CPUSS will cache and prefetch literals When disabled, the cache and prefetcher structures inside CPUSS will not cache and prefetch literals"] # [inline (always)] # [must_use] pub fn ctl_liten (& mut self) -> CTL_LITEN_W < CTL_SPEC , 2 > { CTL_LITEN_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Prefetch/Cache control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CTL_SPEC ; impl crate :: RegisterSpec for CTL_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`ctl::R`](R) reader structure"] impl crate :: Readable for CTL_SPEC { } # [doc = "`write(|w| ..)` method takes [`ctl::W`](W) writer structure"] impl crate :: Writable for CTL_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets CTL to value 0x07"] impl crate :: Resettable for CTL_SPEC { const RESET_VALUE : Self :: Ux = 0x07 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/timg4/ccctl_01.rs:1:34811 [INFO] [stdout] | [INFO] [stdout] 1 | ...e] pub fn ccctl_01_coc (& mut self) -> CCCTL_01_COC_W < CCCTL_01_SPEC , 17 > { CCCTL_01_COC_W :: new (self) } # [doc = "Bits 18:20 - C... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `CCCTL_01[%s]` reader"] pub type R = crate :: R < CCCTL_01_SPEC > ; # [doc = "Register `CCCTL_01[%s]` writer"] pub type W = crate :: W < CCCTL_01_SPEC > ; # [doc = "Field `CCCTL_01_CCOND` reader - Capture Condition. #br# Specifies the condition that generates a capture pulse. 4h-Fh = Reserved"] pub type CCCTL_01_CCOND_R = crate :: FieldReader < CCCTL_01_CCOND_A > ; # [doc = "Capture Condition. #br# Specifies the condition that generates a capture pulse. 4h-Fh = Reserved\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum CCCTL_01_CCOND_A { # [doc = "0: NOCAPTURE"] CCCTL_01_CCOND_NOCAPTURE = 0 , # [doc = "1: CC_TRIG_RISE"] CCCTL_01_CCOND_CC_TRIG_RISE = 1 , # [doc = "2: CC_TRIG_FALL"] CCCTL_01_CCOND_CC_TRIG_FALL = 2 , # [doc = "3: CC_TRIG_EDGE"] CCCTL_01_CCOND_CC_TRIG_EDGE = 3 , } impl From < CCCTL_01_CCOND_A > for u8 { # [inline (always)] fn from (variant : CCCTL_01_CCOND_A) -> Self { variant as _ } } impl crate :: FieldSpec for CCCTL_01_CCOND_A { type Ux = u8 ; } impl CCCTL_01_CCOND_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < CCCTL_01_CCOND_A > { match self . bits { 0 => Some (CCCTL_01_CCOND_A :: CCCTL_01_CCOND_NOCAPTURE) , 1 => Some (CCCTL_01_CCOND_A :: CCCTL_01_CCOND_CC_TRIG_RISE) , 2 => Some (CCCTL_01_CCOND_A :: CCCTL_01_CCOND_CC_TRIG_FALL) , 3 => Some (CCCTL_01_CCOND_A :: CCCTL_01_CCOND_CC_TRIG_EDGE) , _ => None , } } # [doc = "NOCAPTURE"] # [inline (always)] pub fn is_ccctl_01_ccond_nocapture (& self) -> bool { * self == CCCTL_01_CCOND_A :: CCCTL_01_CCOND_NOCAPTURE } # [doc = "CC_TRIG_RISE"] # [inline (always)] pub fn is_ccctl_01_ccond_cc_trig_rise (& self) -> bool { * self == CCCTL_01_CCOND_A :: CCCTL_01_CCOND_CC_TRIG_RISE } # [doc = "CC_TRIG_FALL"] # [inline (always)] pub fn is_ccctl_01_ccond_cc_trig_fall (& self) -> bool { * self == CCCTL_01_CCOND_A :: CCCTL_01_CCOND_CC_TRIG_FALL } # [doc = "CC_TRIG_EDGE"] # [inline (always)] pub fn is_ccctl_01_ccond_cc_trig_edge (& self) -> bool { * self == CCCTL_01_CCOND_A :: CCCTL_01_CCOND_CC_TRIG_EDGE } } # [doc = "Field `CCCTL_01_CCOND` writer - Capture Condition. #br# Specifies the condition that generates a capture pulse. 4h-Fh = Reserved"] pub type CCCTL_01_CCOND_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 3 , O , CCCTL_01_CCOND_A > ; impl < 'a , REG , const O : u8 > CCCTL_01_CCOND_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "NOCAPTURE"] # [inline (always)] pub fn ccctl_01_ccond_nocapture (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CCOND_A :: CCCTL_01_CCOND_NOCAPTURE) } # [doc = "CC_TRIG_RISE"] # [inline (always)] pub fn ccctl_01_ccond_cc_trig_rise (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CCOND_A :: CCCTL_01_CCOND_CC_TRIG_RISE) } # [doc = "CC_TRIG_FALL"] # [inline (always)] pub fn ccctl_01_ccond_cc_trig_fall (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CCOND_A :: CCCTL_01_CCOND_CC_TRIG_FALL) } # [doc = "CC_TRIG_EDGE"] # [inline (always)] pub fn ccctl_01_ccond_cc_trig_edge (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CCOND_A :: CCCTL_01_CCOND_CC_TRIG_EDGE) } } # [doc = "Field `CCCTL_01_ACOND` reader - Advance Condition. #br# Specifies the condition that generates an advance pulse. 6h-Fh = Reserved"] pub type CCCTL_01_ACOND_R = crate :: FieldReader < CCCTL_01_ACOND_A > ; # [doc = "Advance Condition. #br# Specifies the condition that generates an advance pulse. 6h-Fh = Reserved\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum CCCTL_01_ACOND_A { # [doc = "0: TIMCLK"] CCCTL_01_ACOND_TIMCLK = 0 , # [doc = "1: CC_TRIG_RISE"] CCCTL_01_ACOND_CC_TRIG_RISE = 1 , # [doc = "2: CC_TRIG_FALL"] CCCTL_01_ACOND_CC_TRIG_FALL = 2 , # [doc = "3: CC_TRIG_EDGE"] CCCTL_01_ACOND_CC_TRIG_EDGE = 3 , # [doc = "5: CC_TRIG_HIGH"] CCCTL_01_ACOND_CC_TRIG_HIGH = 5 , } impl From < CCCTL_01_ACOND_A > for u8 { # [inline (always)] fn from (variant : CCCTL_01_ACOND_A) -> Self { variant as _ } } impl crate :: FieldSpec for CCCTL_01_ACOND_A { type Ux = u8 ; } impl CCCTL_01_ACOND_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < CCCTL_01_ACOND_A > { match self . bits { 0 => Some (CCCTL_01_ACOND_A :: CCCTL_01_ACOND_TIMCLK) , 1 => Some (CCCTL_01_ACOND_A :: CCCTL_01_ACOND_CC_TRIG_RISE) , 2 => Some (CCCTL_01_ACOND_A :: CCCTL_01_ACOND_CC_TRIG_FALL) , 3 => Some (CCCTL_01_ACOND_A :: CCCTL_01_ACOND_CC_TRIG_EDGE) , 5 => Some (CCCTL_01_ACOND_A :: CCCTL_01_ACOND_CC_TRIG_HIGH) , _ => None , } } # [doc = "TIMCLK"] # [inline (always)] pub fn is_ccctl_01_acond_timclk (& self) -> bool { * self == CCCTL_01_ACOND_A :: CCCTL_01_ACOND_TIMCLK } # [doc = "CC_TRIG_RISE"] # [inline (always)] pub fn is_ccctl_01_acond_cc_trig_rise (& self) -> bool { * self == CCCTL_01_ACOND_A :: CCCTL_01_ACOND_CC_TRIG_RISE } # [doc = "CC_TRIG_FALL"] # [inline (always)] pub fn is_ccctl_01_acond_cc_trig_fall (& self) -> bool { * self == CCCTL_01_ACOND_A :: CCCTL_01_ACOND_CC_TRIG_FALL } # [doc = "CC_TRIG_EDGE"] # [inline (always)] pub fn is_ccctl_01_acond_cc_trig_edge (& self) -> bool { * self == CCCTL_01_ACOND_A :: CCCTL_01_ACOND_CC_TRIG_EDGE } # [doc = "CC_TRIG_HIGH"] # [inline (always)] pub fn is_ccctl_01_acond_cc_trig_high (& self) -> bool { * self == CCCTL_01_ACOND_A :: CCCTL_01_ACOND_CC_TRIG_HIGH } } # [doc = "Field `CCCTL_01_ACOND` writer - Advance Condition. #br# Specifies the condition that generates an advance pulse. 6h-Fh = Reserved"] pub type CCCTL_01_ACOND_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 3 , O , CCCTL_01_ACOND_A > ; impl < 'a , REG , const O : u8 > CCCTL_01_ACOND_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "TIMCLK"] # [inline (always)] pub fn ccctl_01_acond_timclk (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_ACOND_A :: CCCTL_01_ACOND_TIMCLK) } # [doc = "CC_TRIG_RISE"] # [inline (always)] pub fn ccctl_01_acond_cc_trig_rise (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_ACOND_A :: CCCTL_01_ACOND_CC_TRIG_RISE) } # [doc = "CC_TRIG_FALL"] # [inline (always)] pub fn ccctl_01_acond_cc_trig_fall (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_ACOND_A :: CCCTL_01_ACOND_CC_TRIG_FALL) } # [doc = "CC_TRIG_EDGE"] # [inline (always)] pub fn ccctl_01_acond_cc_trig_edge (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_ACOND_A :: CCCTL_01_ACOND_CC_TRIG_EDGE) } # [doc = "CC_TRIG_HIGH"] # [inline (always)] pub fn ccctl_01_acond_cc_trig_high (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_ACOND_A :: CCCTL_01_ACOND_CC_TRIG_HIGH) } } # [doc = "Field `CCCTL_01_LCOND` reader - Load Condition. #br# Specifies the condition that generates a load pulse. 4h-Fh = Reserved"] pub type CCCTL_01_LCOND_R = crate :: FieldReader < CCCTL_01_LCOND_A > ; # [doc = "Load Condition. #br# Specifies the condition that generates a load pulse. 4h-Fh = Reserved\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum CCCTL_01_LCOND_A { # [doc = "1: CC_TRIG_RISE"] CCCTL_01_LCOND_CC_TRIG_RISE = 1 , # [doc = "2: CC_TRIG_FALL"] CCCTL_01_LCOND_CC_TRIG_FALL = 2 , # [doc = "3: CC_TRIG_EDGE"] CCCTL_01_LCOND_CC_TRIG_EDGE = 3 , } impl From < CCCTL_01_LCOND_A > for u8 { # [inline (always)] fn from (variant : CCCTL_01_LCOND_A) -> Self { variant as _ } } impl crate :: FieldSpec for CCCTL_01_LCOND_A { type Ux = u8 ; } impl CCCTL_01_LCOND_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < CCCTL_01_LCOND_A > { match self . bits { 1 => Some (CCCTL_01_LCOND_A :: CCCTL_01_LCOND_CC_TRIG_RISE) , 2 => Some (CCCTL_01_LCOND_A :: CCCTL_01_LCOND_CC_TRIG_FALL) , 3 => Some (CCCTL_01_LCOND_A :: CCCTL_01_LCOND_CC_TRIG_EDGE) , _ => None , } } # [doc = "CC_TRIG_RISE"] # [inline (always)] pub fn is_ccctl_01_lcond_cc_trig_rise (& self) -> bool { * self == CCCTL_01_LCOND_A :: CCCTL_01_LCOND_CC_TRIG_RISE } # [doc = "CC_TRIG_FALL"] # [inline (always)] pub fn is_ccctl_01_lcond_cc_trig_fall (& self) -> bool { * self == CCCTL_01_LCOND_A :: CCCTL_01_LCOND_CC_TRIG_FALL } # [doc = "CC_TRIG_EDGE"] # [inline (always)] pub fn is_ccctl_01_lcond_cc_trig_edge (& self) -> bool { * self == CCCTL_01_LCOND_A :: CCCTL_01_LCOND_CC_TRIG_EDGE } } # [doc = "Field `CCCTL_01_LCOND` writer - Load Condition. #br# Specifies the condition that generates a load pulse. 4h-Fh = Reserved"] pub type CCCTL_01_LCOND_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 3 , O , CCCTL_01_LCOND_A > ; impl < 'a , REG , const O : u8 > CCCTL_01_LCOND_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "CC_TRIG_RISE"] # [inline (always)] pub fn ccctl_01_lcond_cc_trig_rise (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_LCOND_A :: CCCTL_01_LCOND_CC_TRIG_RISE) } # [doc = "CC_TRIG_FALL"] # [inline (always)] pub fn ccctl_01_lcond_cc_trig_fall (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_LCOND_A :: CCCTL_01_LCOND_CC_TRIG_FALL) } # [doc = "CC_TRIG_EDGE"] # [inline (always)] pub fn ccctl_01_lcond_cc_trig_edge (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_LCOND_A :: CCCTL_01_LCOND_CC_TRIG_EDGE) } } # [doc = "Field `CCCTL_01_ZCOND` reader - Zero Condition. #br# This field specifies the condition that generates a zero pulse. 4h-Fh = Reserved"] pub type CCCTL_01_ZCOND_R = crate :: FieldReader < CCCTL_01_ZCOND_A > ; # [doc = "Zero Condition. #br# This field specifies the condition that generates a zero pulse. 4h-Fh = Reserved\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum CCCTL_01_ZCOND_A { # [doc = "1: CC_TRIG_RISE"] CCCTL_01_ZCOND_CC_TRIG_RISE = 1 , # [doc = "2: CC_TRIG_FALL"] CCCTL_01_ZCOND_CC_TRIG_FALL = 2 , # [doc = "3: CC_TRIG_EDGE"] CCCTL_01_ZCOND_CC_TRIG_EDGE = 3 , } impl From < CCCTL_01_ZCOND_A > for u8 { # [inline (always)] fn from (variant : CCCTL_01_ZCOND_A) -> Self { variant as _ } } impl crate :: FieldSpec for CCCTL_01_ZCOND_A { type Ux = u8 ; } impl CCCTL_01_ZCOND_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < CCCTL_01_ZCOND_A > { match self . bits { 1 => Some (CCCTL_01_ZCOND_A :: CCCTL_01_ZCOND_CC_TRIG_RISE) , 2 => Some (CCCTL_01_ZCOND_A :: CCCTL_01_ZCOND_CC_TRIG_FALL) , 3 => Some (CCCTL_01_ZCOND_A :: CCCTL_01_ZCOND_CC_TRIG_EDGE) , _ => None , } } # [doc = "CC_TRIG_RISE"] # [inline (always)] pub fn is_ccctl_01_zcond_cc_trig_rise (& self) -> bool { * self == CCCTL_01_ZCOND_A :: CCCTL_01_ZCOND_CC_TRIG_RISE } # [doc = "CC_TRIG_FALL"] # [inline (always)] pub fn is_ccctl_01_zcond_cc_trig_fall (& self) -> bool { * self == CCCTL_01_ZCOND_A :: CCCTL_01_ZCOND_CC_TRIG_FALL } # [doc = "CC_TRIG_EDGE"] # [inline (always)] pub fn is_ccctl_01_zcond_cc_trig_edge (& self) -> bool { * self == CCCTL_01_ZCOND_A :: CCCTL_01_ZCOND_CC_TRIG_EDGE } } # [doc = "Field `CCCTL_01_ZCOND` writer - Zero Condition. #br# This field specifies the condition that generates a zero pulse. 4h-Fh = Reserved"] pub type CCCTL_01_ZCOND_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 3 , O , CCCTL_01_ZCOND_A > ; impl < 'a , REG , const O : u8 > CCCTL_01_ZCOND_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "CC_TRIG_RISE"] # [inline (always)] pub fn ccctl_01_zcond_cc_trig_rise (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_ZCOND_A :: CCCTL_01_ZCOND_CC_TRIG_RISE) } # [doc = "CC_TRIG_FALL"] # [inline (always)] pub fn ccctl_01_zcond_cc_trig_fall (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_ZCOND_A :: CCCTL_01_ZCOND_CC_TRIG_FALL) } # [doc = "CC_TRIG_EDGE"] # [inline (always)] pub fn ccctl_01_zcond_cc_trig_edge (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_ZCOND_A :: CCCTL_01_ZCOND_CC_TRIG_EDGE) } } # [doc = "Field `CCCTL_01_COC` reader - Capture or Compare. #br# Specifies whether the corresponding CC register is used as a capture register or a compare register (never both)."] pub type CCCTL_01_COC_R = crate :: BitReader < CCCTL_01_COC_A > ; # [doc = "Capture or Compare. #br# Specifies whether the corresponding CC register is used as a capture register or a compare register (never both).\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CCCTL_01_COC_A { # [doc = "0: COMPARE"] CCCTL_01_COC_COMPARE = 0 , # [doc = "1: CAPTURE"] CCCTL_01_COC_CAPTURE = 1 , } impl From < CCCTL_01_COC_A > for bool { # [inline (always)] fn from (variant : CCCTL_01_COC_A) -> Self { variant as u8 != 0 } } impl CCCTL_01_COC_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CCCTL_01_COC_A { match self . bits { false => CCCTL_01_COC_A :: CCCTL_01_COC_COMPARE , true => CCCTL_01_COC_A :: CCCTL_01_COC_CAPTURE , } } # [doc = "COMPARE"] # [inline (always)] pub fn is_ccctl_01_coc_compare (& self) -> bool { * self == CCCTL_01_COC_A :: CCCTL_01_COC_COMPARE } # [doc = "CAPTURE"] # [inline (always)] pub fn is_ccctl_01_coc_capture (& self) -> bool { * self == CCCTL_01_COC_A :: CCCTL_01_COC_CAPTURE } } # [doc = "Field `CCCTL_01_COC` writer - Capture or Compare. #br# Specifies whether the corresponding CC register is used as a capture register or a compare register (never both)."] pub type CCCTL_01_COC_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CCCTL_01_COC_A > ; impl < 'a , REG , const O : u8 > CCCTL_01_COC_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "COMPARE"] # [inline (always)] pub fn ccctl_01_coc_compare (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_COC_A :: CCCTL_01_COC_COMPARE) } # [doc = "CAPTURE"] # [inline (always)] pub fn ccctl_01_coc_capture (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_COC_A :: CCCTL_01_COC_CAPTURE) } } # [doc = "Field `CCCTL_01_CCUPD` reader - Capture and Compare Update Method This field controls how updates to the pipelined capture and compare register are performed (when operating in compare mode, COC=0)."] pub type CCCTL_01_CCUPD_R = crate :: FieldReader < CCCTL_01_CCUPD_A > ; # [doc = "Capture and Compare Update Method This field controls how updates to the pipelined capture and compare register are performed (when operating in compare mode, COC=0).\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum CCCTL_01_CCUPD_A { # [doc = "0: IMMEDIATELY"] CCCTL_01_CCUPD_IMMEDIATELY = 0 , # [doc = "1: ZERO_EVT"] CCCTL_01_CCUPD_ZERO_EVT = 1 , # [doc = "2: COMPARE_DOWN_EVT"] CCCTL_01_CCUPD_COMPARE_DOWN_EVT = 2 , # [doc = "3: COMPARE_UP_EVT"] CCCTL_01_CCUPD_COMPARE_UP_EVT = 3 , # [doc = "4: ZERO_LOAD_EVT"] CCCTL_01_CCUPD_ZERO_LOAD_EVT = 4 , # [doc = "5: ZERO_RC_ZERO_EVT"] CCCTL_01_CCUPD_ZERO_RC_ZERO_EVT = 5 , # [doc = "6: TRIG"] CCCTL_01_CCUPD_TRIG = 6 , } impl From < CCCTL_01_CCUPD_A > for u8 { # [inline (always)] fn from (variant : CCCTL_01_CCUPD_A) -> Self { variant as _ } } impl crate :: FieldSpec for CCCTL_01_CCUPD_A { type Ux = u8 ; } impl CCCTL_01_CCUPD_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < CCCTL_01_CCUPD_A > { match self . bits { 0 => Some (CCCTL_01_CCUPD_A :: CCCTL_01_CCUPD_IMMEDIATELY) , 1 => Some (CCCTL_01_CCUPD_A :: CCCTL_01_CCUPD_ZERO_EVT) , 2 => Some (CCCTL_01_CCUPD_A :: CCCTL_01_CCUPD_COMPARE_DOWN_EVT) , 3 => Some (CCCTL_01_CCUPD_A :: CCCTL_01_CCUPD_COMPARE_UP_EVT) , 4 => Some (CCCTL_01_CCUPD_A :: CCCTL_01_CCUPD_ZERO_LOAD_EVT) , 5 => Some (CCCTL_01_CCUPD_A :: CCCTL_01_CCUPD_ZERO_RC_ZERO_EVT) , 6 => Some (CCCTL_01_CCUPD_A :: CCCTL_01_CCUPD_TRIG) , _ => None , } } # [doc = "IMMEDIATELY"] # [inline (always)] pub fn is_ccctl_01_ccupd_immediately (& self) -> bool { * self == CCCTL_01_CCUPD_A :: CCCTL_01_CCUPD_IMMEDIATELY } # [doc = "ZERO_EVT"] # [inline (always)] pub fn is_ccctl_01_ccupd_zero_evt (& self) -> bool { * self == CCCTL_01_CCUPD_A :: CCCTL_01_CCUPD_ZERO_EVT } # [doc = "COMPARE_DOWN_EVT"] # [inline (always)] pub fn is_ccctl_01_ccupd_compare_down_evt (& self) -> bool { * self == CCCTL_01_CCUPD_A :: CCCTL_01_CCUPD_COMPARE_DOWN_EVT } # [doc = "COMPARE_UP_EVT"] # [inline (always)] pub fn is_ccctl_01_ccupd_compare_up_evt (& self) -> bool { * self == CCCTL_01_CCUPD_A :: CCCTL_01_CCUPD_COMPARE_UP_EVT } # [doc = "ZERO_LOAD_EVT"] # [inline (always)] pub fn is_ccctl_01_ccupd_zero_load_evt (& self) -> bool { * self == CCCTL_01_CCUPD_A :: CCCTL_01_CCUPD_ZERO_LOAD_EVT } # [doc = "ZERO_RC_ZERO_EVT"] # [inline (always)] pub fn is_ccctl_01_ccupd_zero_rc_zero_evt (& self) -> bool { * self == CCCTL_01_CCUPD_A :: CCCTL_01_CCUPD_ZERO_RC_ZERO_EVT } # [doc = "TRIG"] # [inline (always)] pub fn is_ccctl_01_ccupd_trig (& self) -> bool { * self == CCCTL_01_CCUPD_A :: CCCTL_01_CCUPD_TRIG } } # [doc = "Field `CCCTL_01_CCUPD` writer - Capture and Compare Update Method This field controls how updates to the pipelined capture and compare register are performed (when operating in compare mode, COC=0)."] pub type CCCTL_01_CCUPD_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 3 , O , CCCTL_01_CCUPD_A > ; impl < 'a , REG , const O : u8 > CCCTL_01_CCUPD_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "IMMEDIATELY"] # [inline (always)] pub fn ccctl_01_ccupd_immediately (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CCUPD_A :: CCCTL_01_CCUPD_IMMEDIATELY) } # [doc = "ZERO_EVT"] # [inline (always)] pub fn ccctl_01_ccupd_zero_evt (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CCUPD_A :: CCCTL_01_CCUPD_ZERO_EVT) } # [doc = "COMPARE_DOWN_EVT"] # [inline (always)] pub fn ccctl_01_ccupd_compare_down_evt (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CCUPD_A :: CCCTL_01_CCUPD_COMPARE_DOWN_EVT) } # [doc = "COMPARE_UP_EVT"] # [inline (always)] pub fn ccctl_01_ccupd_compare_up_evt (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CCUPD_A :: CCCTL_01_CCUPD_COMPARE_UP_EVT) } # [doc = "ZERO_LOAD_EVT"] # [inline (always)] pub fn ccctl_01_ccupd_zero_load_evt (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CCUPD_A :: CCCTL_01_CCUPD_ZERO_LOAD_EVT) } # [doc = "ZERO_RC_ZERO_EVT"] # [inline (always)] pub fn ccctl_01_ccupd_zero_rc_zero_evt (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CCUPD_A :: CCCTL_01_CCUPD_ZERO_RC_ZERO_EVT) } # [doc = "TRIG"] # [inline (always)] pub fn ccctl_01_ccupd_trig (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CCUPD_A :: CCCTL_01_CCUPD_TRIG) } } # [doc = "Field `CCCTL_01_CC2SELU` reader - Selects the source second CCU event."] pub type CCCTL_01_CC2SELU_R = crate :: FieldReader < CCCTL_01_CC2SELU_A > ; # [doc = "Selects the source second CCU event.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum CCCTL_01_CC2SELU_A { # [doc = "0: SEL_CCU0"] CCCTL_01_CC2SELU_SEL_CCU0 = 0 , # [doc = "1: SEL_CCU1"] CCCTL_01_CC2SELU_SEL_CCU1 = 1 , # [doc = "2: SEL_CCU2"] CCCTL_01_CC2SELU_SEL_CCU2 = 2 , # [doc = "3: SEL_CCU3"] CCCTL_01_CC2SELU_SEL_CCU3 = 3 , # [doc = "4: SEL_CCU4"] CCCTL_01_CC2SELU_SEL_CCU4 = 4 , # [doc = "5: SEL_CCU5"] CCCTL_01_CC2SELU_SEL_CCU5 = 5 , } impl From < CCCTL_01_CC2SELU_A > for u8 { # [inline (always)] fn from (variant : CCCTL_01_CC2SELU_A) -> Self { variant as _ } } impl crate :: FieldSpec for CCCTL_01_CC2SELU_A { type Ux = u8 ; } impl CCCTL_01_CC2SELU_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < CCCTL_01_CC2SELU_A > { match self . bits { 0 => Some (CCCTL_01_CC2SELU_A :: CCCTL_01_CC2SELU_SEL_CCU0) , 1 => Some (CCCTL_01_CC2SELU_A :: CCCTL_01_CC2SELU_SEL_CCU1) , 2 => Some (CCCTL_01_CC2SELU_A :: CCCTL_01_CC2SELU_SEL_CCU2) , 3 => Some (CCCTL_01_CC2SELU_A :: CCCTL_01_CC2SELU_SEL_CCU3) , 4 => Some (CCCTL_01_CC2SELU_A :: CCCTL_01_CC2SELU_SEL_CCU4) , 5 => Some (CCCTL_01_CC2SELU_A :: CCCTL_01_CC2SELU_SEL_CCU5) , _ => None , } } # [doc = "SEL_CCU0"] # [inline (always)] pub fn is_ccctl_01_cc2selu_sel_ccu0 (& self) -> bool { * self == CCCTL_01_CC2SELU_A :: CCCTL_01_CC2SELU_SEL_CCU0 } # [doc = "SEL_CCU1"] # [inline (always)] pub fn is_ccctl_01_cc2selu_sel_ccu1 (& self) -> bool { * self == CCCTL_01_CC2SELU_A :: CCCTL_01_CC2SELU_SEL_CCU1 } # [doc = "SEL_CCU2"] # [inline (always)] pub fn is_ccctl_01_cc2selu_sel_ccu2 (& self) -> bool { * self == CCCTL_01_CC2SELU_A :: CCCTL_01_CC2SELU_SEL_CCU2 } # [doc = "SEL_CCU3"] # [inline (always)] pub fn is_ccctl_01_cc2selu_sel_ccu3 (& self) -> bool { * self == CCCTL_01_CC2SELU_A :: CCCTL_01_CC2SELU_SEL_CCU3 } # [doc = "SEL_CCU4"] # [inline (always)] pub fn is_ccctl_01_cc2selu_sel_ccu4 (& self) -> bool { * self == CCCTL_01_CC2SELU_A :: CCCTL_01_CC2SELU_SEL_CCU4 } # [doc = "SEL_CCU5"] # [inline (always)] pub fn is_ccctl_01_cc2selu_sel_ccu5 (& self) -> bool { * self == CCCTL_01_CC2SELU_A :: CCCTL_01_CC2SELU_SEL_CCU5 } } # [doc = "Field `CCCTL_01_CC2SELU` writer - Selects the source second CCU event."] pub type CCCTL_01_CC2SELU_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 3 , O , CCCTL_01_CC2SELU_A > ; impl < 'a , REG , const O : u8 > CCCTL_01_CC2SELU_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "SEL_CCU0"] # [inline (always)] pub fn ccctl_01_cc2selu_sel_ccu0 (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CC2SELU_A :: CCCTL_01_CC2SELU_SEL_CCU0) } # [doc = "SEL_CCU1"] # [inline (always)] pub fn ccctl_01_cc2selu_sel_ccu1 (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CC2SELU_A :: CCCTL_01_CC2SELU_SEL_CCU1) } # [doc = "SEL_CCU2"] # [inline (always)] pub fn ccctl_01_cc2selu_sel_ccu2 (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CC2SELU_A :: CCCTL_01_CC2SELU_SEL_CCU2) } # [doc = "SEL_CCU3"] # [inline (always)] pub fn ccctl_01_cc2selu_sel_ccu3 (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CC2SELU_A :: CCCTL_01_CC2SELU_SEL_CCU3) } # [doc = "SEL_CCU4"] # [inline (always)] pub fn ccctl_01_cc2selu_sel_ccu4 (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CC2SELU_A :: CCCTL_01_CC2SELU_SEL_CCU4) } # [doc = "SEL_CCU5"] # [inline (always)] pub fn ccctl_01_cc2selu_sel_ccu5 (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CC2SELU_A :: CCCTL_01_CC2SELU_SEL_CCU5) } } # [doc = "Field `CCCTL_01_CCACTUPD` reader - CCACT shadow register Update Method This field controls how updates to the CCCACT shadow register are performed"] pub type CCCTL_01_CCACTUPD_R = crate :: FieldReader < CCCTL_01_CCACTUPD_A > ; # [doc = "CCACT shadow register Update Method This field controls how updates to the CCCACT shadow register are performed\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum CCCTL_01_CCACTUPD_A { # [doc = "0: IMMEDIATELY"] CCCTL_01_CCACTUPD_IMMEDIATELY = 0 , # [doc = "1: ZERO_EVT"] CCCTL_01_CCACTUPD_ZERO_EVT = 1 , # [doc = "2: COMPARE_DOWN_EVT"] CCCTL_01_CCACTUPD_COMPARE_DOWN_EVT = 2 , # [doc = "3: COMPARE_UP_EVT"] CCCTL_01_CCACTUPD_COMPARE_UP_EVT = 3 , # [doc = "4: ZERO_LOAD_EVT"] CCCTL_01_CCACTUPD_ZERO_LOAD_EVT = 4 , # [doc = "5: ZERO_RC_ZERO_EVT"] CCCTL_01_CCACTUPD_ZERO_RC_ZERO_EVT = 5 , # [doc = "6: TRIG"] CCCTL_01_CCACTUPD_TRIG = 6 , } impl From < CCCTL_01_CCACTUPD_A > for u8 { # [inline (always)] fn from (variant : CCCTL_01_CCACTUPD_A) -> Self { variant as _ } } impl crate :: FieldSpec for CCCTL_01_CCACTUPD_A { type Ux = u8 ; } impl CCCTL_01_CCACTUPD_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < CCCTL_01_CCACTUPD_A > { match self . bits { 0 => Some (CCCTL_01_CCACTUPD_A :: CCCTL_01_CCACTUPD_IMMEDIATELY) , 1 => Some (CCCTL_01_CCACTUPD_A :: CCCTL_01_CCACTUPD_ZERO_EVT) , 2 => Some (CCCTL_01_CCACTUPD_A :: CCCTL_01_CCACTUPD_COMPARE_DOWN_EVT) , 3 => Some (CCCTL_01_CCACTUPD_A :: CCCTL_01_CCACTUPD_COMPARE_UP_EVT) , 4 => Some (CCCTL_01_CCACTUPD_A :: CCCTL_01_CCACTUPD_ZERO_LOAD_EVT) , 5 => Some (CCCTL_01_CCACTUPD_A :: CCCTL_01_CCACTUPD_ZERO_RC_ZERO_EVT) , 6 => Some (CCCTL_01_CCACTUPD_A :: CCCTL_01_CCACTUPD_TRIG) , _ => None , } } # [doc = "IMMEDIATELY"] # [inline (always)] pub fn is_ccctl_01_ccactupd_immediately (& self) -> bool { * self == CCCTL_01_CCACTUPD_A :: CCCTL_01_CCACTUPD_IMMEDIATELY } # [doc = "ZERO_EVT"] # [inline (always)] pub fn is_ccctl_01_ccactupd_zero_evt (& self) -> bool { * self == CCCTL_01_CCACTUPD_A :: CCCTL_01_CCACTUPD_ZERO_EVT } # [doc = "COMPARE_DOWN_EVT"] # [inline (always)] pub fn is_ccctl_01_ccactupd_compare_down_evt (& self) -> bool { * self == CCCTL_01_CCACTUPD_A :: CCCTL_01_CCACTUPD_COMPARE_DOWN_EVT } # [doc = "COMPARE_UP_EVT"] # [inline (always)] pub fn is_ccctl_01_ccactupd_compare_up_evt (& self) -> bool { * self == CCCTL_01_CCACTUPD_A :: CCCTL_01_CCACTUPD_COMPARE_UP_EVT } # [doc = "ZERO_LOAD_EVT"] # [inline (always)] pub fn is_ccctl_01_ccactupd_zero_load_evt (& self) -> bool { * self == CCCTL_01_CCACTUPD_A :: CCCTL_01_CCACTUPD_ZERO_LOAD_EVT } # [doc = "ZERO_RC_ZERO_EVT"] # [inline (always)] pub fn is_ccctl_01_ccactupd_zero_rc_zero_evt (& self) -> bool { * self == CCCTL_01_CCACTUPD_A :: CCCTL_01_CCACTUPD_ZERO_RC_ZERO_EVT } # [doc = "TRIG"] # [inline (always)] pub fn is_ccctl_01_ccactupd_trig (& self) -> bool { * self == CCCTL_01_CCACTUPD_A :: CCCTL_01_CCACTUPD_TRIG } } # [doc = "Field `CCCTL_01_CCACTUPD` writer - CCACT shadow register Update Method This field controls how updates to the CCCACT shadow register are performed"] pub type CCCTL_01_CCACTUPD_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 3 , O , CCCTL_01_CCACTUPD_A > ; impl < 'a , REG , const O : u8 > CCCTL_01_CCACTUPD_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "IMMEDIATELY"] # [inline (always)] pub fn ccctl_01_ccactupd_immediately (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CCACTUPD_A :: CCCTL_01_CCACTUPD_IMMEDIATELY) } # [doc = "ZERO_EVT"] # [inline (always)] pub fn ccctl_01_ccactupd_zero_evt (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CCACTUPD_A :: CCCTL_01_CCACTUPD_ZERO_EVT) } # [doc = "COMPARE_DOWN_EVT"] # [inline (always)] pub fn ccctl_01_ccactupd_compare_down_evt (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CCACTUPD_A :: CCCTL_01_CCACTUPD_COMPARE_DOWN_EVT) } # [doc = "COMPARE_UP_EVT"] # [inline (always)] pub fn ccctl_01_ccactupd_compare_up_evt (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CCACTUPD_A :: CCCTL_01_CCACTUPD_COMPARE_UP_EVT) } # [doc = "ZERO_LOAD_EVT"] # [inline (always)] pub fn ccctl_01_ccactupd_zero_load_evt (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CCACTUPD_A :: CCCTL_01_CCACTUPD_ZERO_LOAD_EVT) } # [doc = "ZERO_RC_ZERO_EVT"] # [inline (always)] pub fn ccctl_01_ccactupd_zero_rc_zero_evt (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CCACTUPD_A :: CCCTL_01_CCACTUPD_ZERO_RC_ZERO_EVT) } # [doc = "TRIG"] # [inline (always)] pub fn ccctl_01_ccactupd_trig (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CCACTUPD_A :: CCCTL_01_CCACTUPD_TRIG) } } # [doc = "Field `CCCTL_01_CC2SELD` reader - Selects the source second CCD event."] pub type CCCTL_01_CC2SELD_R = crate :: FieldReader < CCCTL_01_CC2SELD_A > ; # [doc = "Selects the source second CCD event.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum CCCTL_01_CC2SELD_A { # [doc = "0: SEL_CCD0"] CCCTL_01_CC2SELD_SEL_CCD0 = 0 , # [doc = "1: SEL_CCD1"] CCCTL_01_CC2SELD_SEL_CCD1 = 1 , # [doc = "2: SEL_CCD2"] CCCTL_01_CC2SELD_SEL_CCD2 = 2 , # [doc = "3: SEL_CCD3"] CCCTL_01_CC2SELD_SEL_CCD3 = 3 , # [doc = "4: SEL_CCD4"] CCCTL_01_CC2SELD_SEL_CCD4 = 4 , # [doc = "5: SEL_CCD5"] CCCTL_01_CC2SELD_SEL_CCD5 = 5 , } impl From < CCCTL_01_CC2SELD_A > for u8 { # [inline (always)] fn from (variant : CCCTL_01_CC2SELD_A) -> Self { variant as _ } } impl crate :: FieldSpec for CCCTL_01_CC2SELD_A { type Ux = u8 ; } impl CCCTL_01_CC2SELD_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < CCCTL_01_CC2SELD_A > { match self . bits { 0 => Some (CCCTL_01_CC2SELD_A :: CCCTL_01_CC2SELD_SEL_CCD0) , 1 => Some (CCCTL_01_CC2SELD_A :: CCCTL_01_CC2SELD_SEL_CCD1) , 2 => Some (CCCTL_01_CC2SELD_A :: CCCTL_01_CC2SELD_SEL_CCD2) , 3 => Some (CCCTL_01_CC2SELD_A :: CCCTL_01_CC2SELD_SEL_CCD3) , 4 => Some (CCCTL_01_CC2SELD_A :: CCCTL_01_CC2SELD_SEL_CCD4) , 5 => Some (CCCTL_01_CC2SELD_A :: CCCTL_01_CC2SELD_SEL_CCD5) , _ => None , } } # [doc = "SEL_CCD0"] # [inline (always)] pub fn is_ccctl_01_cc2seld_sel_ccd0 (& self) -> bool { * self == CCCTL_01_CC2SELD_A :: CCCTL_01_CC2SELD_SEL_CCD0 } # [doc = "SEL_CCD1"] # [inline (always)] pub fn is_ccctl_01_cc2seld_sel_ccd1 (& self) -> bool { * self == CCCTL_01_CC2SELD_A :: CCCTL_01_CC2SELD_SEL_CCD1 } # [doc = "SEL_CCD2"] # [inline (always)] pub fn is_ccctl_01_cc2seld_sel_ccd2 (& self) -> bool { * self == CCCTL_01_CC2SELD_A :: CCCTL_01_CC2SELD_SEL_CCD2 } # [doc = "SEL_CCD3"] # [inline (always)] pub fn is_ccctl_01_cc2seld_sel_ccd3 (& self) -> bool { * self == CCCTL_01_CC2SELD_A :: CCCTL_01_CC2SELD_SEL_CCD3 } # [doc = "SEL_CCD4"] # [inline (always)] pub fn is_ccctl_01_cc2seld_sel_ccd4 (& self) -> bool { * self == CCCTL_01_CC2SELD_A :: CCCTL_01_CC2SELD_SEL_CCD4 } # [doc = "SEL_CCD5"] # [inline (always)] pub fn is_ccctl_01_cc2seld_sel_ccd5 (& self) -> bool { * self == CCCTL_01_CC2SELD_A :: CCCTL_01_CC2SELD_SEL_CCD5 } } # [doc = "Field `CCCTL_01_CC2SELD` writer - Selects the source second CCD event."] pub type CCCTL_01_CC2SELD_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 3 , O , CCCTL_01_CC2SELD_A > ; impl < 'a , REG , const O : u8 > CCCTL_01_CC2SELD_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "SEL_CCD0"] # [inline (always)] pub fn ccctl_01_cc2seld_sel_ccd0 (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CC2SELD_A :: CCCTL_01_CC2SELD_SEL_CCD0) } # [doc = "SEL_CCD1"] # [inline (always)] pub fn ccctl_01_cc2seld_sel_ccd1 (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CC2SELD_A :: CCCTL_01_CC2SELD_SEL_CCD1) } # [doc = "SEL_CCD2"] # [inline (always)] pub fn ccctl_01_cc2seld_sel_ccd2 (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CC2SELD_A :: CCCTL_01_CC2SELD_SEL_CCD2) } # [doc = "SEL_CCD3"] # [inline (always)] pub fn ccctl_01_cc2seld_sel_ccd3 (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CC2SELD_A :: CCCTL_01_CC2SELD_SEL_CCD3) } # [doc = "SEL_CCD4"] # [inline (always)] pub fn ccctl_01_cc2seld_sel_ccd4 (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CC2SELD_A :: CCCTL_01_CC2SELD_SEL_CCD4) } # [doc = "SEL_CCD5"] # [inline (always)] pub fn ccctl_01_cc2seld_sel_ccd5 (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CC2SELD_A :: CCCTL_01_CC2SELD_SEL_CCD5) } } impl R { # [doc = "Bits 0:2 - Capture Condition. #br# Specifies the condition that generates a capture pulse. 4h-Fh = Reserved"] # [inline (always)] pub fn ccctl_01_ccond (& self) -> CCCTL_01_CCOND_R { CCCTL_01_CCOND_R :: new ((self . bits & 7) as u8) } # [doc = "Bits 4:6 - Advance Condition. #br# Specifies the condition that generates an advance pulse. 6h-Fh = Reserved"] # [inline (always)] pub fn ccctl_01_acond (& self) -> CCCTL_01_ACOND_R { CCCTL_01_ACOND_R :: new (((self . bits >> 4) & 7) as u8) } # [doc = "Bits 8:10 - Load Condition. #br# Specifies the condition that generates a load pulse. 4h-Fh = Reserved"] # [inline (always)] pub fn ccctl_01_lcond (& self) -> CCCTL_01_LCOND_R { CCCTL_01_LCOND_R :: new (((self . bits >> 8) & 7) as u8) } # [doc = "Bits 12:14 - Zero Condition. #br# This field specifies the condition that generates a zero pulse. 4h-Fh = Reserved"] # [inline (always)] pub fn ccctl_01_zcond (& self) -> CCCTL_01_ZCOND_R { CCCTL_01_ZCOND_R :: new (((self . bits >> 12) & 7) as u8) } # [doc = "Bit 17 - Capture or Compare. #br# Specifies whether the corresponding CC register is used as a capture register or a compare register (never both)."] # [inline (always)] pub fn ccctl_01_coc (& self) -> CCCTL_01_COC_R { CCCTL_01_COC_R :: new (((self . bits >> 17) & 1) != 0) } # [doc = "Bits 18:20 - Capture and Compare Update Method This field controls how updates to the pipelined capture and compare register are performed (when operating in compare mode, COC=0)."] # [inline (always)] pub fn ccctl_01_ccupd (& self) -> CCCTL_01_CCUPD_R { CCCTL_01_CCUPD_R :: new (((self . bits >> 18) & 7) as u8) } # [doc = "Bits 22:24 - Selects the source second CCU event."] # [inline (always)] pub fn ccctl_01_cc2selu (& self) -> CCCTL_01_CC2SELU_R { CCCTL_01_CC2SELU_R :: new (((self . bits >> 22) & 7) as u8) } # [doc = "Bits 26:28 - CCACT shadow register Update Method This field controls how updates to the CCCACT shadow register are performed"] # [inline (always)] pub fn ccctl_01_ccactupd (& self) -> CCCTL_01_CCACTUPD_R { CCCTL_01_CCACTUPD_R :: new (((self . bits >> 26) & 7) as u8) } # [doc = "Bits 29:31 - Selects the source second CCD event."] # [inline (always)] pub fn ccctl_01_cc2seld (& self) -> CCCTL_01_CC2SELD_R { CCCTL_01_CC2SELD_R :: new (((self . bits >> 29) & 7) as u8) } } impl W { # [doc = "Bits 0:2 - Capture Condition. #br# Specifies the condition that generates a capture pulse. 4h-Fh = Reserved"] # [inline (always)] # [must_use] pub fn ccctl_01_ccond (& mut self) -> CCCTL_01_CCOND_W < CCCTL_01_SPEC , 0 > { CCCTL_01_CCOND_W :: new (self) } # [doc = "Bits 4:6 - Advance Condition. #br# Specifies the condition that generates an advance pulse. 6h-Fh = Reserved"] # [inline (always)] # [must_use] pub fn ccctl_01_acond (& mut self) -> CCCTL_01_ACOND_W < CCCTL_01_SPEC , 4 > { CCCTL_01_ACOND_W :: new (self) } # [doc = "Bits 8:10 - Load Condition. #br# Specifies the condition that generates a load pulse. 4h-Fh = Reserved"] # [inline (always)] # [must_use] pub fn ccctl_01_lcond (& mut self) -> CCCTL_01_LCOND_W < CCCTL_01_SPEC , 8 > { CCCTL_01_LCOND_W :: new (self) } # [doc = "Bits 12:14 - Zero Condition. #br# This field specifies the condition that generates a zero pulse. 4h-Fh = Reserved"] # [inline (always)] # [must_use] pub fn ccctl_01_zcond (& mut self) -> CCCTL_01_ZCOND_W < CCCTL_01_SPEC , 12 > { CCCTL_01_ZCOND_W :: new (self) } # [doc = "Bit 17 - Capture or Compare. #br# Specifies whether the corresponding CC register is used as a capture register or a compare register (never both)."] # [inline (always)] # [must_use] pub fn ccctl_01_coc (& mut self) -> CCCTL_01_COC_W <'_, CCCTL_01_SPEC , 17 > { CCCTL_01_COC_W :: new (self) } # [doc = "Bits 18:20 - Capture and Compare Update Method This field controls how updates to the pipelined capture and compare register are performed (when operating in compare mode, COC=0)."] # [inline (always)] # [must_use] pub fn ccctl_01_ccupd (& mut self) -> CCCTL_01_CCUPD_W < CCCTL_01_SPEC , 18 > { CCCTL_01_CCUPD_W :: new (self) } # [doc = "Bits 22:24 - Selects the source second CCU event."] # [inline (always)] # [must_use] pub fn ccctl_01_cc2selu (& mut self) -> CCCTL_01_CC2SELU_W < CCCTL_01_SPEC , 22 > { CCCTL_01_CC2SELU_W :: new (self) } # [doc = "Bits 26:28 - CCACT shadow register Update Method This field controls how updates to the CCCACT shadow register are performed"] # [inline (always)] # [must_use] pub fn ccctl_01_ccactupd (& mut self) -> CCCTL_01_CCACTUPD_W < CCCTL_01_SPEC , 26 > { CCCTL_01_CCACTUPD_W :: new (self) } # [doc = "Bits 29:31 - Selects the source second CCD event."] # [inline (always)] # [must_use] pub fn ccctl_01_cc2seld (& mut self) -> CCCTL_01_CC2SELD_W < CCCTL_01_SPEC , 29 > { CCCTL_01_CC2SELD_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Capture or Compare Control Registers\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ccctl_01::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ccctl_01::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CCCTL_01_SPEC ; impl crate :: RegisterSpec for CCCTL_01_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`ccctl_01::R`](R) reader structure"] impl crate :: Readable for CCCTL_01_SPEC { } # [doc = "`write(|w| ..)` method takes [`ccctl_01::W`](W) writer structure"] impl crate :: Writable for CCCTL_01_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets CCCTL_01[%s] [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/spi0/clksel.rs:1:6844 [INFO] [stdout] | [INFO] [stdout] 1 | ... fn clksel_sysclk_sel (& mut self) -> CLKSEL_SYSCLK_SEL_W < CLKSEL_SPEC , 3 > { CLKSEL_SYSCLK_SEL_W :: new (self) } # [doc = r" Writes... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `CLKSEL` reader"] pub type R = crate :: R < CLKSEL_SPEC > ; # [doc = "Register `CLKSEL` writer"] pub type W = crate :: W < CLKSEL_SPEC > ; # [doc = "Field `CLKSEL_LFCLK_SEL` reader - Selects LFCLK as clock source if enabled"] pub type CLKSEL_LFCLK_SEL_R = crate :: BitReader < CLKSEL_LFCLK_SEL_A > ; # [doc = "Selects LFCLK as clock source if enabled\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CLKSEL_LFCLK_SEL_A { # [doc = "0: DISABLE"] CLKSEL_LFCLK_SEL_DISABLE = 0 , # [doc = "1: ENABLE"] CLKSEL_LFCLK_SEL_ENABLE = 1 , } impl From < CLKSEL_LFCLK_SEL_A > for bool { # [inline (always)] fn from (variant : CLKSEL_LFCLK_SEL_A) -> Self { variant as u8 != 0 } } impl CLKSEL_LFCLK_SEL_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CLKSEL_LFCLK_SEL_A { match self . bits { false => CLKSEL_LFCLK_SEL_A :: CLKSEL_LFCLK_SEL_DISABLE , true => CLKSEL_LFCLK_SEL_A :: CLKSEL_LFCLK_SEL_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_clksel_lfclk_sel_disable (& self) -> bool { * self == CLKSEL_LFCLK_SEL_A :: CLKSEL_LFCLK_SEL_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_clksel_lfclk_sel_enable (& self) -> bool { * self == CLKSEL_LFCLK_SEL_A :: CLKSEL_LFCLK_SEL_ENABLE } } # [doc = "Field `CLKSEL_LFCLK_SEL` writer - Selects LFCLK as clock source if enabled"] pub type CLKSEL_LFCLK_SEL_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CLKSEL_LFCLK_SEL_A > ; impl < 'a , REG , const O : u8 > CLKSEL_LFCLK_SEL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn clksel_lfclk_sel_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CLKSEL_LFCLK_SEL_A :: CLKSEL_LFCLK_SEL_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn clksel_lfclk_sel_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CLKSEL_LFCLK_SEL_A :: CLKSEL_LFCLK_SEL_ENABLE) } } # [doc = "Field `CLKSEL_MFCLK_SEL` reader - Selects MFCLK as clock source if enabled"] pub type CLKSEL_MFCLK_SEL_R = crate :: BitReader < CLKSEL_MFCLK_SEL_A > ; # [doc = "Selects MFCLK as clock source if enabled\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CLKSEL_MFCLK_SEL_A { # [doc = "0: DISABLE"] CLKSEL_MFCLK_SEL_DISABLE = 0 , # [doc = "1: ENABLE"] CLKSEL_MFCLK_SEL_ENABLE = 1 , } impl From < CLKSEL_MFCLK_SEL_A > for bool { # [inline (always)] fn from (variant : CLKSEL_MFCLK_SEL_A) -> Self { variant as u8 != 0 } } impl CLKSEL_MFCLK_SEL_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CLKSEL_MFCLK_SEL_A { match self . bits { false => CLKSEL_MFCLK_SEL_A :: CLKSEL_MFCLK_SEL_DISABLE , true => CLKSEL_MFCLK_SEL_A :: CLKSEL_MFCLK_SEL_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_clksel_mfclk_sel_disable (& self) -> bool { * self == CLKSEL_MFCLK_SEL_A :: CLKSEL_MFCLK_SEL_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_clksel_mfclk_sel_enable (& self) -> bool { * self == CLKSEL_MFCLK_SEL_A :: CLKSEL_MFCLK_SEL_ENABLE } } # [doc = "Field `CLKSEL_MFCLK_SEL` writer - Selects MFCLK as clock source if enabled"] pub type CLKSEL_MFCLK_SEL_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CLKSEL_MFCLK_SEL_A > ; impl < 'a , REG , const O : u8 > CLKSEL_MFCLK_SEL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn clksel_mfclk_sel_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CLKSEL_MFCLK_SEL_A :: CLKSEL_MFCLK_SEL_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn clksel_mfclk_sel_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CLKSEL_MFCLK_SEL_A :: CLKSEL_MFCLK_SEL_ENABLE) } } # [doc = "Field `CLKSEL_SYSCLK_SEL` reader - Selects SYSCLK as clock source if enabled"] pub type CLKSEL_SYSCLK_SEL_R = crate :: BitReader < CLKSEL_SYSCLK_SEL_A > ; # [doc = "Selects SYSCLK as clock source if enabled\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CLKSEL_SYSCLK_SEL_A { # [doc = "0: DISABLE"] CLKSEL_SYSCLK_SEL_DISABLE = 0 , # [doc = "1: ENABLE"] CLKSEL_SYSCLK_SEL_ENABLE = 1 , } impl From < CLKSEL_SYSCLK_SEL_A > for bool { # [inline (always)] fn from (variant : CLKSEL_SYSCLK_SEL_A) -> Self { variant as u8 != 0 } } impl CLKSEL_SYSCLK_SEL_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CLKSEL_SYSCLK_SEL_A { match self . bits { false => CLKSEL_SYSCLK_SEL_A :: CLKSEL_SYSCLK_SEL_DISABLE , true => CLKSEL_SYSCLK_SEL_A :: CLKSEL_SYSCLK_SEL_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_clksel_sysclk_sel_disable (& self) -> bool { * self == CLKSEL_SYSCLK_SEL_A :: CLKSEL_SYSCLK_SEL_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_clksel_sysclk_sel_enable (& self) -> bool { * self == CLKSEL_SYSCLK_SEL_A :: CLKSEL_SYSCLK_SEL_ENABLE } } # [doc = "Field `CLKSEL_SYSCLK_SEL` writer - Selects SYSCLK as clock source if enabled"] pub type CLKSEL_SYSCLK_SEL_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CLKSEL_SYSCLK_SEL_A > ; impl < 'a , REG , const O : u8 > CLKSEL_SYSCLK_SEL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn clksel_sysclk_sel_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CLKSEL_SYSCLK_SEL_A :: CLKSEL_SYSCLK_SEL_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn clksel_sysclk_sel_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CLKSEL_SYSCLK_SEL_A :: CLKSEL_SYSCLK_SEL_ENABLE) } } impl R { # [doc = "Bit 1 - Selects LFCLK as clock source if enabled"] # [inline (always)] pub fn clksel_lfclk_sel (& self) -> CLKSEL_LFCLK_SEL_R { CLKSEL_LFCLK_SEL_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - Selects MFCLK as clock source if enabled"] # [inline (always)] pub fn clksel_mfclk_sel (& self) -> CLKSEL_MFCLK_SEL_R { CLKSEL_MFCLK_SEL_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - Selects SYSCLK as clock source if enabled"] # [inline (always)] pub fn clksel_sysclk_sel (& self) -> CLKSEL_SYSCLK_SEL_R { CLKSEL_SYSCLK_SEL_R :: new (((self . bits >> 3) & 1) != 0) } } impl W { # [doc = "Bit 1 - Selects LFCLK as clock source if enabled"] # [inline (always)] # [must_use] pub fn clksel_lfclk_sel (& mut self) -> CLKSEL_LFCLK_SEL_W < CLKSEL_SPEC , 1 > { CLKSEL_LFCLK_SEL_W :: new (self) } # [doc = "Bit 2 - Selects MFCLK as clock source if enabled"] # [inline (always)] # [must_use] pub fn clksel_mfclk_sel (& mut self) -> CLKSEL_MFCLK_SEL_W < CLKSEL_SPEC , 2 > { CLKSEL_MFCLK_SEL_W :: new (self) } # [doc = "Bit 3 - Selects SYSCLK as clock source if enabled"] # [inline (always)] # [must_use] pub fn clksel_sysclk_sel (& mut self) -> CLKSEL_SYSCLK_SEL_W <'_, CLKSEL_SPEC , 3 > { CLKSEL_SYSCLK_SEL_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Clock Select for Ultra Low Power peripherals\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clksel::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clksel::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CLKSEL_SPEC ; impl crate :: RegisterSpec for CLKSEL_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`clksel::R`](R) reader structure"] impl crate :: Readable for CLKSEL_SPEC { } # [doc = "`write(|w| ..)` method takes [`clksel::W`](W) writer structure"] impl crate :: Writable for CLKSEL_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets CLKSEL to value 0"] impl crate :: Resettable for CLKSEL_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/opa1/cfg.rs:1:16718 [INFO] [stdout] | [INFO] [stdout] 1 | ...ust_use] pub fn cfg_outpin (& mut self) -> CFG_OUTPIN_W < CFG_SPEC , 2 > { CFG_OUTPIN_W :: new (self) } # [doc = "Bits 3:6 - Positive ... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `CFG` reader"] pub type R = crate :: R < CFG_SPEC > ; # [doc = "Register `CFG` writer"] pub type W = crate :: W < CFG_SPEC > ; # [doc = "Field `CFG_CHOP` reader - Chopping enable."] pub type CFG_CHOP_R = crate :: FieldReader < CFG_CHOP_A > ; # [doc = "Chopping enable.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum CFG_CHOP_A { # [doc = "0: OFF"] CFG_CHOP_OFF = 0 , # [doc = "1: ON"] CFG_CHOP_ON = 1 , # [doc = "2: AVGON"] CFG_CHOP_AVGON = 2 , } impl From < CFG_CHOP_A > for u8 { # [inline (always)] fn from (variant : CFG_CHOP_A) -> Self { variant as _ } } impl crate :: FieldSpec for CFG_CHOP_A { type Ux = u8 ; } impl CFG_CHOP_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < CFG_CHOP_A > { match self . bits { 0 => Some (CFG_CHOP_A :: CFG_CHOP_OFF) , 1 => Some (CFG_CHOP_A :: CFG_CHOP_ON) , 2 => Some (CFG_CHOP_A :: CFG_CHOP_AVGON) , _ => None , } } # [doc = "OFF"] # [inline (always)] pub fn is_cfg_chop_off (& self) -> bool { * self == CFG_CHOP_A :: CFG_CHOP_OFF } # [doc = "ON"] # [inline (always)] pub fn is_cfg_chop_on (& self) -> bool { * self == CFG_CHOP_A :: CFG_CHOP_ON } # [doc = "AVGON"] # [inline (always)] pub fn is_cfg_chop_avgon (& self) -> bool { * self == CFG_CHOP_A :: CFG_CHOP_AVGON } } # [doc = "Field `CFG_CHOP` writer - Chopping enable."] pub type CFG_CHOP_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 2 , O , CFG_CHOP_A > ; impl < 'a , REG , const O : u8 > CFG_CHOP_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "OFF"] # [inline (always)] pub fn cfg_chop_off (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_CHOP_A :: CFG_CHOP_OFF) } # [doc = "ON"] # [inline (always)] pub fn cfg_chop_on (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_CHOP_A :: CFG_CHOP_ON) } # [doc = "AVGON"] # [inline (always)] pub fn cfg_chop_avgon (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_CHOP_A :: CFG_CHOP_AVGON) } } # [doc = "Field `CFG_OUTPIN` reader - Enable output pin"] pub type CFG_OUTPIN_R = crate :: BitReader < CFG_OUTPIN_A > ; # [doc = "Enable output pin\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CFG_OUTPIN_A { # [doc = "0: DISABLED"] CFG_OUTPIN_DISABLED = 0 , # [doc = "1: ENABLED"] CFG_OUTPIN_ENABLED = 1 , } impl From < CFG_OUTPIN_A > for bool { # [inline (always)] fn from (variant : CFG_OUTPIN_A) -> Self { variant as u8 != 0 } } impl CFG_OUTPIN_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CFG_OUTPIN_A { match self . bits { false => CFG_OUTPIN_A :: CFG_OUTPIN_DISABLED , true => CFG_OUTPIN_A :: CFG_OUTPIN_ENABLED , } } # [doc = "DISABLED"] # [inline (always)] pub fn is_cfg_outpin_disabled (& self) -> bool { * self == CFG_OUTPIN_A :: CFG_OUTPIN_DISABLED } # [doc = "ENABLED"] # [inline (always)] pub fn is_cfg_outpin_enabled (& self) -> bool { * self == CFG_OUTPIN_A :: CFG_OUTPIN_ENABLED } } # [doc = "Field `CFG_OUTPIN` writer - Enable output pin"] pub type CFG_OUTPIN_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CFG_OUTPIN_A > ; impl < 'a , REG , const O : u8 > CFG_OUTPIN_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLED"] # [inline (always)] pub fn cfg_outpin_disabled (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_OUTPIN_A :: CFG_OUTPIN_DISABLED) } # [doc = "ENABLED"] # [inline (always)] pub fn cfg_outpin_enabled (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_OUTPIN_A :: CFG_OUTPIN_ENABLED) } } # [doc = "Field `CFG_PSEL` reader - Positive OA input selection. Please refer to the device specific datasheet for exact channels available."] pub type CFG_PSEL_R = crate :: FieldReader < CFG_PSEL_A > ; # [doc = "Positive OA input selection. Please refer to the device specific datasheet for exact channels available.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum CFG_PSEL_A { # [doc = "0: NC"] CFG_PSEL_NC = 0 , # [doc = "1: EXTPIN0"] CFG_PSEL_EXTPIN0 = 1 , # [doc = "2: EXTPIN1"] CFG_PSEL_EXTPIN1 = 2 , # [doc = "3: DAC12OUT"] CFG_PSEL_DAC12OUT = 3 , # [doc = "4: DAC8OUT"] CFG_PSEL_DAC8OUT = 4 , # [doc = "5: VREF"] CFG_PSEL_VREF = 5 , # [doc = "6: OANM1RTOP"] CFG_PSEL_OANM1RTOP = 6 , # [doc = "7: GPAMP_OUT_INT"] CFG_PSEL_GPAMP_OUT_INT = 7 , # [doc = "8: VSS"] CFG_PSEL_VSS = 8 , } impl From < CFG_PSEL_A > for u8 { # [inline (always)] fn from (variant : CFG_PSEL_A) -> Self { variant as _ } } impl crate :: FieldSpec for CFG_PSEL_A { type Ux = u8 ; } impl CFG_PSEL_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < CFG_PSEL_A > { match self . bits { 0 => Some (CFG_PSEL_A :: CFG_PSEL_NC) , 1 => Some (CFG_PSEL_A :: CFG_PSEL_EXTPIN0) , 2 => Some (CFG_PSEL_A :: CFG_PSEL_EXTPIN1) , 3 => Some (CFG_PSEL_A :: CFG_PSEL_DAC12OUT) , 4 => Some (CFG_PSEL_A :: CFG_PSEL_DAC8OUT) , 5 => Some (CFG_PSEL_A :: CFG_PSEL_VREF) , 6 => Some (CFG_PSEL_A :: CFG_PSEL_OANM1RTOP) , 7 => Some (CFG_PSEL_A :: CFG_PSEL_GPAMP_OUT_INT) , 8 => Some (CFG_PSEL_A :: CFG_PSEL_VSS) , _ => None , } } # [doc = "NC"] # [inline (always)] pub fn is_cfg_psel_nc (& self) -> bool { * self == CFG_PSEL_A :: CFG_PSEL_NC } # [doc = "EXTPIN0"] # [inline (always)] pub fn is_cfg_psel_extpin0 (& self) -> bool { * self == CFG_PSEL_A :: CFG_PSEL_EXTPIN0 } # [doc = "EXTPIN1"] # [inline (always)] pub fn is_cfg_psel_extpin1 (& self) -> bool { * self == CFG_PSEL_A :: CFG_PSEL_EXTPIN1 } # [doc = "DAC12OUT"] # [inline (always)] pub fn is_cfg_psel_dac12out (& self) -> bool { * self == CFG_PSEL_A :: CFG_PSEL_DAC12OUT } # [doc = "DAC8OUT"] # [inline (always)] pub fn is_cfg_psel_dac8out (& self) -> bool { * self == CFG_PSEL_A :: CFG_PSEL_DAC8OUT } # [doc = "VREF"] # [inline (always)] pub fn is_cfg_psel_vref (& self) -> bool { * self == CFG_PSEL_A :: CFG_PSEL_VREF } # [doc = "OANM1RTOP"] # [inline (always)] pub fn is_cfg_psel_oanm1rtop (& self) -> bool { * self == CFG_PSEL_A :: CFG_PSEL_OANM1RTOP } # [doc = "GPAMP_OUT_INT"] # [inline (always)] pub fn is_cfg_psel_gpamp_out_int (& self) -> bool { * self == CFG_PSEL_A :: CFG_PSEL_GPAMP_OUT_INT } # [doc = "VSS"] # [inline (always)] pub fn is_cfg_psel_vss (& self) -> bool { * self == CFG_PSEL_A :: CFG_PSEL_VSS } } # [doc = "Field `CFG_PSEL` writer - Positive OA input selection. Please refer to the device specific datasheet for exact channels available."] pub type CFG_PSEL_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 4 , O , CFG_PSEL_A > ; impl < 'a , REG , const O : u8 > CFG_PSEL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "NC"] # [inline (always)] pub fn cfg_psel_nc (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_PSEL_A :: CFG_PSEL_NC) } # [doc = "EXTPIN0"] # [inline (always)] pub fn cfg_psel_extpin0 (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_PSEL_A :: CFG_PSEL_EXTPIN0) } # [doc = "EXTPIN1"] # [inline (always)] pub fn cfg_psel_extpin1 (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_PSEL_A :: CFG_PSEL_EXTPIN1) } # [doc = "DAC12OUT"] # [inline (always)] pub fn cfg_psel_dac12out (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_PSEL_A :: CFG_PSEL_DAC12OUT) } # [doc = "DAC8OUT"] # [inline (always)] pub fn cfg_psel_dac8out (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_PSEL_A :: CFG_PSEL_DAC8OUT) } # [doc = "VREF"] # [inline (always)] pub fn cfg_psel_vref (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_PSEL_A :: CFG_PSEL_VREF) } # [doc = "OANM1RTOP"] # [inline (always)] pub fn cfg_psel_oanm1rtop (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_PSEL_A :: CFG_PSEL_OANM1RTOP) } # [doc = "GPAMP_OUT_INT"] # [inline (always)] pub fn cfg_psel_gpamp_out_int (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_PSEL_A :: CFG_PSEL_GPAMP_OUT_INT) } # [doc = "VSS"] # [inline (always)] pub fn cfg_psel_vss (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_PSEL_A :: CFG_PSEL_VSS) } } # [doc = "Field `CFG_NSEL` reader - Negative OA input selection. Please refer to the device specific datasheet for exact channels available."] pub type CFG_NSEL_R = crate :: FieldReader < CFG_NSEL_A > ; # [doc = "Negative OA input selection. Please refer to the device specific datasheet for exact channels available.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum CFG_NSEL_A { # [doc = "0: NC"] CFG_NSEL_NC = 0 , # [doc = "1: EXTPIN0"] CFG_NSEL_EXTPIN0 = 1 , # [doc = "2: EXTPIN1"] CFG_NSEL_EXTPIN1 = 2 , # [doc = "3: OANP1RBOT"] CFG_NSEL_OANP1RBOT = 3 , # [doc = "4: OANRTAP"] CFG_NSEL_OANRTAP = 4 , # [doc = "5: OANRTOP"] CFG_NSEL_OANRTOP = 5 , # [doc = "6: SPARE"] CFG_NSEL_SPARE = 6 , } impl From < CFG_NSEL_A > for u8 { # [inline (always)] fn from (variant : CFG_NSEL_A) -> Self { variant as _ } } impl crate :: FieldSpec for CFG_NSEL_A { type Ux = u8 ; } impl CFG_NSEL_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < CFG_NSEL_A > { match self . bits { 0 => Some (CFG_NSEL_A :: CFG_NSEL_NC) , 1 => Some (CFG_NSEL_A :: CFG_NSEL_EXTPIN0) , 2 => Some (CFG_NSEL_A :: CFG_NSEL_EXTPIN1) , 3 => Some (CFG_NSEL_A :: CFG_NSEL_OANP1RBOT) , 4 => Some (CFG_NSEL_A :: CFG_NSEL_OANRTAP) , 5 => Some (CFG_NSEL_A :: CFG_NSEL_OANRTOP) , 6 => Some (CFG_NSEL_A :: CFG_NSEL_SPARE) , _ => None , } } # [doc = "NC"] # [inline (always)] pub fn is_cfg_nsel_nc (& self) -> bool { * self == CFG_NSEL_A :: CFG_NSEL_NC } # [doc = "EXTPIN0"] # [inline (always)] pub fn is_cfg_nsel_extpin0 (& self) -> bool { * self == CFG_NSEL_A :: CFG_NSEL_EXTPIN0 } # [doc = "EXTPIN1"] # [inline (always)] pub fn is_cfg_nsel_extpin1 (& self) -> bool { * self == CFG_NSEL_A :: CFG_NSEL_EXTPIN1 } # [doc = "OANP1RBOT"] # [inline (always)] pub fn is_cfg_nsel_oanp1rbot (& self) -> bool { * self == CFG_NSEL_A :: CFG_NSEL_OANP1RBOT } # [doc = "OANRTAP"] # [inline (always)] pub fn is_cfg_nsel_oanrtap (& self) -> bool { * self == CFG_NSEL_A :: CFG_NSEL_OANRTAP } # [doc = "OANRTOP"] # [inline (always)] pub fn is_cfg_nsel_oanrtop (& self) -> bool { * self == CFG_NSEL_A :: CFG_NSEL_OANRTOP } # [doc = "SPARE"] # [inline (always)] pub fn is_cfg_nsel_spare (& self) -> bool { * self == CFG_NSEL_A :: CFG_NSEL_SPARE } } # [doc = "Field `CFG_NSEL` writer - Negative OA input selection. Please refer to the device specific datasheet for exact channels available."] pub type CFG_NSEL_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 3 , O , CFG_NSEL_A > ; impl < 'a , REG , const O : u8 > CFG_NSEL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "NC"] # [inline (always)] pub fn cfg_nsel_nc (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_NSEL_A :: CFG_NSEL_NC) } # [doc = "EXTPIN0"] # [inline (always)] pub fn cfg_nsel_extpin0 (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_NSEL_A :: CFG_NSEL_EXTPIN0) } # [doc = "EXTPIN1"] # [inline (always)] pub fn cfg_nsel_extpin1 (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_NSEL_A :: CFG_NSEL_EXTPIN1) } # [doc = "OANP1RBOT"] # [inline (always)] pub fn cfg_nsel_oanp1rbot (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_NSEL_A :: CFG_NSEL_OANP1RBOT) } # [doc = "OANRTAP"] # [inline (always)] pub fn cfg_nsel_oanrtap (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_NSEL_A :: CFG_NSEL_OANRTAP) } # [doc = "OANRTOP"] # [inline (always)] pub fn cfg_nsel_oanrtop (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_NSEL_A :: CFG_NSEL_OANRTOP) } # [doc = "SPARE"] # [inline (always)] pub fn cfg_nsel_spare (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_NSEL_A :: CFG_NSEL_SPARE) } } # [doc = "Field `CFG_MSEL` reader - MSEL Mux selection. Please refer to the device specific datasheet for exact channels available."] pub type CFG_MSEL_R = crate :: FieldReader < CFG_MSEL_A > ; # [doc = "MSEL Mux selection. Please refer to the device specific datasheet for exact channels available.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum CFG_MSEL_A { # [doc = "0: NC"] CFG_MSEL_NC = 0 , # [doc = "1: EXTNPIN1"] CFG_MSEL_EXTNPIN1 = 1 , # [doc = "2: VSS"] CFG_MSEL_VSS = 2 , # [doc = "3: DAC12OUT"] CFG_MSEL_DAC12OUT = 3 , # [doc = "4: OANM1RTOP"] CFG_MSEL_OANM1RTOP = 4 , } impl From < CFG_MSEL_A > for u8 { # [inline (always)] fn from (variant : CFG_MSEL_A) -> Self { variant as _ } } impl crate :: FieldSpec for CFG_MSEL_A { type Ux = u8 ; } impl CFG_MSEL_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < CFG_MSEL_A > { match self . bits { 0 => Some (CFG_MSEL_A :: CFG_MSEL_NC) , 1 => Some (CFG_MSEL_A :: CFG_MSEL_EXTNPIN1) , 2 => Some (CFG_MSEL_A :: CFG_MSEL_VSS) , 3 => Some (CFG_MSEL_A :: CFG_MSEL_DAC12OUT) , 4 => Some (CFG_MSEL_A :: CFG_MSEL_OANM1RTOP) , _ => None , } } # [doc = "NC"] # [inline (always)] pub fn is_cfg_msel_nc (& self) -> bool { * self == CFG_MSEL_A :: CFG_MSEL_NC } # [doc = "EXTNPIN1"] # [inline (always)] pub fn is_cfg_msel_extnpin1 (& self) -> bool { * self == CFG_MSEL_A :: CFG_MSEL_EXTNPIN1 } # [doc = "VSS"] # [inline (always)] pub fn is_cfg_msel_vss (& self) -> bool { * self == CFG_MSEL_A :: CFG_MSEL_VSS } # [doc = "DAC12OUT"] # [inline (always)] pub fn is_cfg_msel_dac12out (& self) -> bool { * self == CFG_MSEL_A :: CFG_MSEL_DAC12OUT } # [doc = "OANM1RTOP"] # [inline (always)] pub fn is_cfg_msel_oanm1rtop (& self) -> bool { * self == CFG_MSEL_A :: CFG_MSEL_OANM1RTOP } } # [doc = "Field `CFG_MSEL` writer - MSEL Mux selection. Please refer to the device specific datasheet for exact channels available."] pub type CFG_MSEL_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 3 , O , CFG_MSEL_A > ; impl < 'a , REG , const O : u8 > CFG_MSEL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "NC"] # [inline (always)] pub fn cfg_msel_nc (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_MSEL_A :: CFG_MSEL_NC) } # [doc = "EXTNPIN1"] # [inline (always)] pub fn cfg_msel_extnpin1 (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_MSEL_A :: CFG_MSEL_EXTNPIN1) } # [doc = "VSS"] # [inline (always)] pub fn cfg_msel_vss (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_MSEL_A :: CFG_MSEL_VSS) } # [doc = "DAC12OUT"] # [inline (always)] pub fn cfg_msel_dac12out (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_MSEL_A :: CFG_MSEL_DAC12OUT) } # [doc = "OANM1RTOP"] # [inline (always)] pub fn cfg_msel_oanm1rtop (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_MSEL_A :: CFG_MSEL_OANM1RTOP) } } # [doc = "Field `CFG_GAIN` reader - Gain setting. Refer to TRM for enumeration information."] pub type CFG_GAIN_R = crate :: FieldReader ; # [doc = "Field `CFG_GAIN` writer - Gain setting. Refer to TRM for enumeration information."] pub type CFG_GAIN_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 3 , O > ; impl R { # [doc = "Bits 0:1 - Chopping enable."] # [inline (always)] pub fn cfg_chop (& self) -> CFG_CHOP_R { CFG_CHOP_R :: new ((self . bits & 3) as u8) } # [doc = "Bit 2 - Enable output pin"] # [inline (always)] pub fn cfg_outpin (& self) -> CFG_OUTPIN_R { CFG_OUTPIN_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bits 3:6 - Positive OA input selection. Please refer to the device specific datasheet for exact channels available."] # [inline (always)] pub fn cfg_psel (& self) -> CFG_PSEL_R { CFG_PSEL_R :: new (((self . bits >> 3) & 0x0f) as u8) } # [doc = "Bits 7:9 - Negative OA input selection. Please refer to the device specific datasheet for exact channels available."] # [inline (always)] pub fn cfg_nsel (& self) -> CFG_NSEL_R { CFG_NSEL_R :: new (((self . bits >> 7) & 7) as u8) } # [doc = "Bits 10:12 - MSEL Mux selection. Please refer to the device specific datasheet for exact channels available."] # [inline (always)] pub fn cfg_msel (& self) -> CFG_MSEL_R { CFG_MSEL_R :: new (((self . bits >> 10) & 7) as u8) } # [doc = "Bits 13:15 - Gain setting. Refer to TRM for enumeration information."] # [inline (always)] pub fn cfg_gain (& self) -> CFG_GAIN_R { CFG_GAIN_R :: new (((self . bits >> 13) & 7) as u8) } } impl W { # [doc = "Bits 0:1 - Chopping enable."] # [inline (always)] # [must_use] pub fn cfg_chop (& mut self) -> CFG_CHOP_W < CFG_SPEC , 0 > { CFG_CHOP_W :: new (self) } # [doc = "Bit 2 - Enable output pin"] # [inline (always)] # [must_use] pub fn cfg_outpin (& mut self) -> CFG_OUTPIN_W <'_, CFG_SPEC , 2 > { CFG_OUTPIN_W :: new (self) } # [doc = "Bits 3:6 - Positive OA input selection. Please refer to the device specific datasheet for exact channels available."] # [inline (always)] # [must_use] pub fn cfg_psel (& mut self) -> CFG_PSEL_W < CFG_SPEC , 3 > { CFG_PSEL_W :: new (self) } # [doc = "Bits 7:9 - Negative OA input selection. Please refer to the device specific datasheet for exact channels available."] # [inline (always)] # [must_use] pub fn cfg_nsel (& mut self) -> CFG_NSEL_W < CFG_SPEC , 7 > { CFG_NSEL_W :: new (self) } # [doc = "Bits 10:12 - MSEL Mux selection. Please refer to the device specific datasheet for exact channels available."] # [inline (always)] # [must_use] pub fn cfg_msel (& mut self) -> CFG_MSEL_W < CFG_SPEC , 10 > { CFG_MSEL_W :: new (self) } # [doc = "Bits 13:15 - Gain setting. Refer to TRM for enumeration information."] # [inline (always)] # [must_use] pub fn cfg_gain (& mut self) -> CFG_GAIN_W < CFG_SPEC , 13 > { CFG_GAIN_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Configuration Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CFG_SPEC ; impl crate :: RegisterSpec for CFG_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`cfg::R`](R) reader structure"] impl crate :: Readable for CFG_SPEC { } # [doc = "`write(|w| ..)` method takes [`cfg::W`](W) writer structure"] impl crate :: Writable for CFG_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets CFG to value 0"] impl crate :: Resettable for CFG_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/i2c0/sctr.rs:1:24329 [INFO] [stdout] | [INFO] [stdout] 1 | ...t_use] pub fn sctr_active (& mut self) -> SCTR_ACTIVE_W < SCTR_SPEC , 0 > { SCTR_ACTIVE_W :: new (self) } # [doc = "Bit 1 - General ca... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `SCTR` reader"] pub type R = crate :: R < SCTR_SPEC > ; # [doc = "Register `SCTR` writer"] pub type W = crate :: W < SCTR_SPEC > ; # [doc = "Field `SCTR_ACTIVE` reader - Device Active. Setting this bit enables the slave functionality."] pub type SCTR_ACTIVE_R = crate :: BitReader < SCTR_ACTIVE_A > ; # [doc = "Device Active. Setting this bit enables the slave functionality.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum SCTR_ACTIVE_A { # [doc = "0: DISABLE"] SCTR_ACTIVE_DISABLE = 0 , # [doc = "1: ENABLE"] SCTR_ACTIVE_ENABLE = 1 , } impl From < SCTR_ACTIVE_A > for bool { # [inline (always)] fn from (variant : SCTR_ACTIVE_A) -> Self { variant as u8 != 0 } } impl SCTR_ACTIVE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> SCTR_ACTIVE_A { match self . bits { false => SCTR_ACTIVE_A :: SCTR_ACTIVE_DISABLE , true => SCTR_ACTIVE_A :: SCTR_ACTIVE_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_sctr_active_disable (& self) -> bool { * self == SCTR_ACTIVE_A :: SCTR_ACTIVE_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_sctr_active_enable (& self) -> bool { * self == SCTR_ACTIVE_A :: SCTR_ACTIVE_ENABLE } } # [doc = "Field `SCTR_ACTIVE` writer - Device Active. Setting this bit enables the slave functionality."] pub type SCTR_ACTIVE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , SCTR_ACTIVE_A > ; impl < 'a , REG , const O : u8 > SCTR_ACTIVE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn sctr_active_disable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_ACTIVE_A :: SCTR_ACTIVE_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn sctr_active_enable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_ACTIVE_A :: SCTR_ACTIVE_ENABLE) } } # [doc = "Field `SCTR_GENCALL` reader - General call response enable. This bit is only available in UCBxI2COA0. Modify only when UCSWRST = 1. 0b = Do not respond to a general call 1b = Respond to a general call"] pub type SCTR_GENCALL_R = crate :: BitReader < SCTR_GENCALL_A > ; # [doc = "General call response enable. This bit is only available in UCBxI2COA0. Modify only when UCSWRST = 1. 0b = Do not respond to a general call 1b = Respond to a general call\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum SCTR_GENCALL_A { # [doc = "0: DISABLE"] SCTR_GENCALL_DISABLE = 0 , # [doc = "1: ENABLE"] SCTR_GENCALL_ENABLE = 1 , } impl From < SCTR_GENCALL_A > for bool { # [inline (always)] fn from (variant : SCTR_GENCALL_A) -> Self { variant as u8 != 0 } } impl SCTR_GENCALL_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> SCTR_GENCALL_A { match self . bits { false => SCTR_GENCALL_A :: SCTR_GENCALL_DISABLE , true => SCTR_GENCALL_A :: SCTR_GENCALL_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_sctr_gencall_disable (& self) -> bool { * self == SCTR_GENCALL_A :: SCTR_GENCALL_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_sctr_gencall_enable (& self) -> bool { * self == SCTR_GENCALL_A :: SCTR_GENCALL_ENABLE } } # [doc = "Field `SCTR_GENCALL` writer - General call response enable. This bit is only available in UCBxI2COA0. Modify only when UCSWRST = 1. 0b = Do not respond to a general call 1b = Respond to a general call"] pub type SCTR_GENCALL_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , SCTR_GENCALL_A > ; impl < 'a , REG , const O : u8 > SCTR_GENCALL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn sctr_gencall_disable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_GENCALL_A :: SCTR_GENCALL_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn sctr_gencall_enable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_GENCALL_A :: SCTR_GENCALL_ENABLE) } } # [doc = "Field `SCTR_SCLKSTRETCH` reader - Slave Clock Stretch Enable"] pub type SCTR_SCLKSTRETCH_R = crate :: BitReader < SCTR_SCLKSTRETCH_A > ; # [doc = "Slave Clock Stretch Enable\n\nValue on reset: 1"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum SCTR_SCLKSTRETCH_A { # [doc = "0: DISABLE"] SCTR_SCLKSTRETCH_DISABLE = 0 , # [doc = "1: ENABLE"] SCTR_SCLKSTRETCH_ENABLE = 1 , } impl From < SCTR_SCLKSTRETCH_A > for bool { # [inline (always)] fn from (variant : SCTR_SCLKSTRETCH_A) -> Self { variant as u8 != 0 } } impl SCTR_SCLKSTRETCH_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> SCTR_SCLKSTRETCH_A { match self . bits { false => SCTR_SCLKSTRETCH_A :: SCTR_SCLKSTRETCH_DISABLE , true => SCTR_SCLKSTRETCH_A :: SCTR_SCLKSTRETCH_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_sctr_sclkstretch_disable (& self) -> bool { * self == SCTR_SCLKSTRETCH_A :: SCTR_SCLKSTRETCH_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_sctr_sclkstretch_enable (& self) -> bool { * self == SCTR_SCLKSTRETCH_A :: SCTR_SCLKSTRETCH_ENABLE } } # [doc = "Field `SCTR_SCLKSTRETCH` writer - Slave Clock Stretch Enable"] pub type SCTR_SCLKSTRETCH_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , SCTR_SCLKSTRETCH_A > ; impl < 'a , REG , const O : u8 > SCTR_SCLKSTRETCH_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn sctr_sclkstretch_disable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_SCLKSTRETCH_A :: SCTR_SCLKSTRETCH_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn sctr_sclkstretch_enable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_SCLKSTRETCH_A :: SCTR_SCLKSTRETCH_ENABLE) } } # [doc = "Field `SCTR_TXEMPTY_ON_TREQ` reader - Tx Empty Interrupt on TREQ"] pub type SCTR_TXEMPTY_ON_TREQ_R = crate :: BitReader < SCTR_TXEMPTY_ON_TREQ_A > ; # [doc = "Tx Empty Interrupt on TREQ\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum SCTR_TXEMPTY_ON_TREQ_A { # [doc = "0: DISABLE"] SCTR_TXEMPTY_ON_TREQ_DISABLE = 0 , # [doc = "1: ENABLE"] SCTR_TXEMPTY_ON_TREQ_ENABLE = 1 , } impl From < SCTR_TXEMPTY_ON_TREQ_A > for bool { # [inline (always)] fn from (variant : SCTR_TXEMPTY_ON_TREQ_A) -> Self { variant as u8 != 0 } } impl SCTR_TXEMPTY_ON_TREQ_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> SCTR_TXEMPTY_ON_TREQ_A { match self . bits { false => SCTR_TXEMPTY_ON_TREQ_A :: SCTR_TXEMPTY_ON_TREQ_DISABLE , true => SCTR_TXEMPTY_ON_TREQ_A :: SCTR_TXEMPTY_ON_TREQ_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_sctr_txempty_on_treq_disable (& self) -> bool { * self == SCTR_TXEMPTY_ON_TREQ_A :: SCTR_TXEMPTY_ON_TREQ_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_sctr_txempty_on_treq_enable (& self) -> bool { * self == SCTR_TXEMPTY_ON_TREQ_A :: SCTR_TXEMPTY_ON_TREQ_ENABLE } } # [doc = "Field `SCTR_TXEMPTY_ON_TREQ` writer - Tx Empty Interrupt on TREQ"] pub type SCTR_TXEMPTY_ON_TREQ_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , SCTR_TXEMPTY_ON_TREQ_A > ; impl < 'a , REG , const O : u8 > SCTR_TXEMPTY_ON_TREQ_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn sctr_txempty_on_treq_disable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_TXEMPTY_ON_TREQ_A :: SCTR_TXEMPTY_ON_TREQ_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn sctr_txempty_on_treq_enable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_TXEMPTY_ON_TREQ_A :: SCTR_TXEMPTY_ON_TREQ_ENABLE) } } # [doc = "Field `SCTR_TXTRIG_TXMODE` reader - Tx Trigger when slave FSM is in Tx Mode"] pub type SCTR_TXTRIG_TXMODE_R = crate :: BitReader < SCTR_TXTRIG_TXMODE_A > ; # [doc = "Tx Trigger when slave FSM is in Tx Mode\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum SCTR_TXTRIG_TXMODE_A { # [doc = "0: DISABLE"] SCTR_TXTRIG_TXMODE_DISABLE = 0 , # [doc = "1: ENABLE"] SCTR_TXTRIG_TXMODE_ENABLE = 1 , } impl From < SCTR_TXTRIG_TXMODE_A > for bool { # [inline (always)] fn from (variant : SCTR_TXTRIG_TXMODE_A) -> Self { variant as u8 != 0 } } impl SCTR_TXTRIG_TXMODE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> SCTR_TXTRIG_TXMODE_A { match self . bits { false => SCTR_TXTRIG_TXMODE_A :: SCTR_TXTRIG_TXMODE_DISABLE , true => SCTR_TXTRIG_TXMODE_A :: SCTR_TXTRIG_TXMODE_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_sctr_txtrig_txmode_disable (& self) -> bool { * self == SCTR_TXTRIG_TXMODE_A :: SCTR_TXTRIG_TXMODE_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_sctr_txtrig_txmode_enable (& self) -> bool { * self == SCTR_TXTRIG_TXMODE_A :: SCTR_TXTRIG_TXMODE_ENABLE } } # [doc = "Field `SCTR_TXTRIG_TXMODE` writer - Tx Trigger when slave FSM is in Tx Mode"] pub type SCTR_TXTRIG_TXMODE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , SCTR_TXTRIG_TXMODE_A > ; impl < 'a , REG , const O : u8 > SCTR_TXTRIG_TXMODE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn sctr_txtrig_txmode_disable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_TXTRIG_TXMODE_A :: SCTR_TXTRIG_TXMODE_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn sctr_txtrig_txmode_enable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_TXTRIG_TXMODE_A :: SCTR_TXTRIG_TXMODE_ENABLE) } } # [doc = "Field `SCTR_TXWAIT_STALE_TXFIFO` reader - Tx transfer waits when stale data in Tx FIFO. This prevents stale bytes left in the TX FIFO from automatically being sent on the next I2C packet. Note: this should be used with TXEMPTY_ON_TREQ set to prevent the Slave State Machine from waiting for TX FIFO data without an interrupt notification when the FIFO data is stale."] pub type SCTR_TXWAIT_STALE_TXFIFO_R = crate :: BitReader < SCTR_TXWAIT_STALE_TXFIFO_A > ; # [doc = "Tx transfer waits when stale data in Tx FIFO. This prevents stale bytes left in the TX FIFO from automatically being sent on the next I2C packet. Note: this should be used with TXEMPTY_ON_TREQ set to prevent the Slave State Machine from waiting for TX FIFO data without an interrupt notification when the FIFO data is stale.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum SCTR_TXWAIT_STALE_TXFIFO_A { # [doc = "0: DISABLE"] SCTR_TXWAIT_STALE_TXFIFO_DISABLE = 0 , # [doc = "1: ENABLE"] SCTR_TXWAIT_STALE_TXFIFO_ENABLE = 1 , } impl From < SCTR_TXWAIT_STALE_TXFIFO_A > for bool { # [inline (always)] fn from (variant : SCTR_TXWAIT_STALE_TXFIFO_A) -> Self { variant as u8 != 0 } } impl SCTR_TXWAIT_STALE_TXFIFO_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> SCTR_TXWAIT_STALE_TXFIFO_A { match self . bits { false => SCTR_TXWAIT_STALE_TXFIFO_A :: SCTR_TXWAIT_STALE_TXFIFO_DISABLE , true => SCTR_TXWAIT_STALE_TXFIFO_A :: SCTR_TXWAIT_STALE_TXFIFO_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_sctr_txwait_stale_txfifo_disable (& self) -> bool { * self == SCTR_TXWAIT_STALE_TXFIFO_A :: SCTR_TXWAIT_STALE_TXFIFO_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_sctr_txwait_stale_txfifo_enable (& self) -> bool { * self == SCTR_TXWAIT_STALE_TXFIFO_A :: SCTR_TXWAIT_STALE_TXFIFO_ENABLE } } # [doc = "Field `SCTR_TXWAIT_STALE_TXFIFO` writer - Tx transfer waits when stale data in Tx FIFO. This prevents stale bytes left in the TX FIFO from automatically being sent on the next I2C packet. Note: this should be used with TXEMPTY_ON_TREQ set to prevent the Slave State Machine from waiting for TX FIFO data without an interrupt notification when the FIFO data is stale."] pub type SCTR_TXWAIT_STALE_TXFIFO_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , SCTR_TXWAIT_STALE_TXFIFO_A > ; impl < 'a , REG , const O : u8 > SCTR_TXWAIT_STALE_TXFIFO_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn sctr_txwait_stale_txfifo_disable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_TXWAIT_STALE_TXFIFO_A :: SCTR_TXWAIT_STALE_TXFIFO_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn sctr_txwait_stale_txfifo_enable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_TXWAIT_STALE_TXFIFO_A :: SCTR_TXWAIT_STALE_TXFIFO_ENABLE) } } # [doc = "Field `SCTR_RXFULL_ON_RREQ` reader - Rx full interrupt generated on RREQ condition as indicated in SSR"] pub type SCTR_RXFULL_ON_RREQ_R = crate :: BitReader < SCTR_RXFULL_ON_RREQ_A > ; # [doc = "Rx full interrupt generated on RREQ condition as indicated in SSR\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum SCTR_RXFULL_ON_RREQ_A { # [doc = "0: DISABLE"] SCTR_RXFULL_ON_RREQ_DISABLE = 0 , # [doc = "1: ENABLE"] SCTR_RXFULL_ON_RREQ_ENABLE = 1 , } impl From < SCTR_RXFULL_ON_RREQ_A > for bool { # [inline (always)] fn from (variant : SCTR_RXFULL_ON_RREQ_A) -> Self { variant as u8 != 0 } } impl SCTR_RXFULL_ON_RREQ_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> SCTR_RXFULL_ON_RREQ_A { match self . bits { false => SCTR_RXFULL_ON_RREQ_A :: SCTR_RXFULL_ON_RREQ_DISABLE , true => SCTR_RXFULL_ON_RREQ_A :: SCTR_RXFULL_ON_RREQ_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_sctr_rxfull_on_rreq_disable (& self) -> bool { * self == SCTR_RXFULL_ON_RREQ_A :: SCTR_RXFULL_ON_RREQ_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_sctr_rxfull_on_rreq_enable (& self) -> bool { * self == SCTR_RXFULL_ON_RREQ_A :: SCTR_RXFULL_ON_RREQ_ENABLE } } # [doc = "Field `SCTR_RXFULL_ON_RREQ` writer - Rx full interrupt generated on RREQ condition as indicated in SSR"] pub type SCTR_RXFULL_ON_RREQ_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , SCTR_RXFULL_ON_RREQ_A > ; impl < 'a , REG , const O : u8 > SCTR_RXFULL_ON_RREQ_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn sctr_rxfull_on_rreq_disable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_RXFULL_ON_RREQ_A :: SCTR_RXFULL_ON_RREQ_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn sctr_rxfull_on_rreq_enable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_RXFULL_ON_RREQ_A :: SCTR_RXFULL_ON_RREQ_ENABLE) } } # [doc = "Field `SCTR_EN_DEFHOSTADR` reader - Enable Default Host Address"] pub type SCTR_EN_DEFHOSTADR_R = crate :: BitReader < SCTR_EN_DEFHOSTADR_A > ; # [doc = "Enable Default Host Address\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum SCTR_EN_DEFHOSTADR_A { # [doc = "0: DISABLE"] SCTR_EN_DEFHOSTADR_DISABLE = 0 , # [doc = "1: ENABLE"] SCTR_EN_DEFHOSTADR_ENABLE = 1 , } impl From < SCTR_EN_DEFHOSTADR_A > for bool { # [inline (always)] fn from (variant : SCTR_EN_DEFHOSTADR_A) -> Self { variant as u8 != 0 } } impl SCTR_EN_DEFHOSTADR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> SCTR_EN_DEFHOSTADR_A { match self . bits { false => SCTR_EN_DEFHOSTADR_A :: SCTR_EN_DEFHOSTADR_DISABLE , true => SCTR_EN_DEFHOSTADR_A :: SCTR_EN_DEFHOSTADR_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_sctr_en_defhostadr_disable (& self) -> bool { * self == SCTR_EN_DEFHOSTADR_A :: SCTR_EN_DEFHOSTADR_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_sctr_en_defhostadr_enable (& self) -> bool { * self == SCTR_EN_DEFHOSTADR_A :: SCTR_EN_DEFHOSTADR_ENABLE } } # [doc = "Field `SCTR_EN_DEFHOSTADR` writer - Enable Default Host Address"] pub type SCTR_EN_DEFHOSTADR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , SCTR_EN_DEFHOSTADR_A > ; impl < 'a , REG , const O : u8 > SCTR_EN_DEFHOSTADR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn sctr_en_defhostadr_disable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_EN_DEFHOSTADR_A :: SCTR_EN_DEFHOSTADR_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn sctr_en_defhostadr_enable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_EN_DEFHOSTADR_A :: SCTR_EN_DEFHOSTADR_ENABLE) } } # [doc = "Field `SCTR_EN_ALRESPADR` reader - Enable Alert Response Address"] pub type SCTR_EN_ALRESPADR_R = crate :: BitReader < SCTR_EN_ALRESPADR_A > ; # [doc = "Enable Alert Response Address\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum SCTR_EN_ALRESPADR_A { # [doc = "0: DISABLE"] SCTR_EN_ALRESPADR_DISABLE = 0 , # [doc = "1: ENABLE"] SCTR_EN_ALRESPADR_ENABLE = 1 , } impl From < SCTR_EN_ALRESPADR_A > for bool { # [inline (always)] fn from (variant : SCTR_EN_ALRESPADR_A) -> Self { variant as u8 != 0 } } impl SCTR_EN_ALRESPADR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> SCTR_EN_ALRESPADR_A { match self . bits { false => SCTR_EN_ALRESPADR_A :: SCTR_EN_ALRESPADR_DISABLE , true => SCTR_EN_ALRESPADR_A :: SCTR_EN_ALRESPADR_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_sctr_en_alrespadr_disable (& self) -> bool { * self == SCTR_EN_ALRESPADR_A :: SCTR_EN_ALRESPADR_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_sctr_en_alrespadr_enable (& self) -> bool { * self == SCTR_EN_ALRESPADR_A :: SCTR_EN_ALRESPADR_ENABLE } } # [doc = "Field `SCTR_EN_ALRESPADR` writer - Enable Alert Response Address"] pub type SCTR_EN_ALRESPADR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , SCTR_EN_ALRESPADR_A > ; impl < 'a , REG , const O : u8 > SCTR_EN_ALRESPADR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn sctr_en_alrespadr_disable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_EN_ALRESPADR_A :: SCTR_EN_ALRESPADR_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn sctr_en_alrespadr_enable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_EN_ALRESPADR_A :: SCTR_EN_ALRESPADR_ENABLE) } } # [doc = "Field `SCTR_EN_DEFDEVADR` reader - Enable Deault device address"] pub type SCTR_EN_DEFDEVADR_R = crate :: BitReader < SCTR_EN_DEFDEVADR_A > ; # [doc = "Enable Deault device address\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum SCTR_EN_DEFDEVADR_A { # [doc = "0: DISABLE"] SCTR_EN_DEFDEVADR_DISABLE = 0 , # [doc = "1: ENABLE"] SCTR_EN_DEFDEVADR_ENABLE = 1 , } impl From < SCTR_EN_DEFDEVADR_A > for bool { # [inline (always)] fn from (variant : SCTR_EN_DEFDEVADR_A) -> Self { variant as u8 != 0 } } impl SCTR_EN_DEFDEVADR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> SCTR_EN_DEFDEVADR_A { match self . bits { false => SCTR_EN_DEFDEVADR_A :: SCTR_EN_DEFDEVADR_DISABLE , true => SCTR_EN_DEFDEVADR_A :: SCTR_EN_DEFDEVADR_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_sctr_en_defdevadr_disable (& self) -> bool { * self == SCTR_EN_DEFDEVADR_A :: SCTR_EN_DEFDEVADR_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_sctr_en_defdevadr_enable (& self) -> bool { * self == SCTR_EN_DEFDEVADR_A :: SCTR_EN_DEFDEVADR_ENABLE } } # [doc = "Field `SCTR_EN_DEFDEVADR` writer - Enable Deault device address"] pub type SCTR_EN_DEFDEVADR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , SCTR_EN_DEFDEVADR_A > ; impl < 'a , REG , const O : u8 > SCTR_EN_DEFDEVADR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn sctr_en_defdevadr_disable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_EN_DEFDEVADR_A :: SCTR_EN_DEFDEVADR_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn sctr_en_defdevadr_enable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_EN_DEFDEVADR_A :: SCTR_EN_DEFDEVADR_ENABLE) } } # [doc = "Field `SCTR_SWUEN` reader - Slave Wakeup Enable"] pub type SCTR_SWUEN_R = crate :: BitReader < SCTR_SWUEN_A > ; # [doc = "Slave Wakeup Enable\n\nValue on reset: 1"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum SCTR_SWUEN_A { # [doc = "0: DISABLE"] SCTR_SWUEN_DISABLE = 0 , # [doc = "1: ENABLE"] SCTR_SWUEN_ENABLE = 1 , } impl From < SCTR_SWUEN_A > for bool { # [inline (always)] fn from (variant : SCTR_SWUEN_A) -> Self { variant as u8 != 0 } } impl SCTR_SWUEN_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> SCTR_SWUEN_A { match self . bits { false => SCTR_SWUEN_A :: SCTR_SWUEN_DISABLE , true => SCTR_SWUEN_A :: SCTR_SWUEN_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_sctr_swuen_disable (& self) -> bool { * self == SCTR_SWUEN_A :: SCTR_SWUEN_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_sctr_swuen_enable (& self) -> bool { * self == SCTR_SWUEN_A :: SCTR_SWUEN_ENABLE } } # [doc = "Field `SCTR_SWUEN` writer - Slave Wakeup Enable"] pub type SCTR_SWUEN_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , SCTR_SWUEN_A > ; impl < 'a , REG , const O : u8 > SCTR_SWUEN_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn sctr_swuen_disable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_SWUEN_A :: SCTR_SWUEN_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn sctr_swuen_enable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_SWUEN_A :: SCTR_SWUEN_ENABLE) } } impl R { # [doc = "Bit 0 - Device Active. Setting this bit enables the slave functionality."] # [inline (always)] pub fn sctr_active (& self) -> SCTR_ACTIVE_R { SCTR_ACTIVE_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - General call response enable. This bit is only available in UCBxI2COA0. Modify only when UCSWRST = 1. 0b = Do not respond to a general call 1b = Respond to a general call"] # [inline (always)] pub fn sctr_gencall (& self) -> SCTR_GENCALL_R { SCTR_GENCALL_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - Slave Clock Stretch Enable"] # [inline (always)] pub fn sctr_sclkstretch (& self) -> SCTR_SCLKSTRETCH_R { SCTR_SCLKSTRETCH_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - Tx Empty Interrupt on TREQ"] # [inline (always)] pub fn sctr_txempty_on_treq (& self) -> SCTR_TXEMPTY_ON_TREQ_R { SCTR_TXEMPTY_ON_TREQ_R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - Tx Trigger when slave FSM is in Tx Mode"] # [inline (always)] pub fn sctr_txtrig_txmode (& self) -> SCTR_TXTRIG_TXMODE_R { SCTR_TXTRIG_TXMODE_R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - Tx transfer waits when stale data in Tx FIFO. This prevents stale bytes left in the TX FIFO from automatically being sent on the next I2C packet. Note: this should be used with TXEMPTY_ON_TREQ set to prevent the Slave State Machine from waiting for TX FIFO data without an interrupt notification when the FIFO data is stale."] # [inline (always)] pub fn sctr_txwait_stale_txfifo (& self) -> SCTR_TXWAIT_STALE_TXFIFO_R { SCTR_TXWAIT_STALE_TXFIFO_R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - Rx full interrupt generated on RREQ condition as indicated in SSR"] # [inline (always)] pub fn sctr_rxfull_on_rreq (& self) -> SCTR_RXFULL_ON_RREQ_R { SCTR_RXFULL_ON_RREQ_R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - Enable Default Host Address"] # [inline (always)] pub fn sctr_en_defhostadr (& self) -> SCTR_EN_DEFHOSTADR_R { SCTR_EN_DEFHOSTADR_R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - Enable Alert Response Address"] # [inline (always)] pub fn sctr_en_alrespadr (& self) -> SCTR_EN_ALRESPADR_R { SCTR_EN_ALRESPADR_R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - Enable Deault device address"] # [inline (always)] pub fn sctr_en_defdevadr (& self) -> SCTR_EN_DEFDEVADR_R { SCTR_EN_DEFDEVADR_R :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - Slave Wakeup Enable"] # [inline (always)] pub fn sctr_swuen (& self) -> SCTR_SWUEN_R { SCTR_SWUEN_R :: new (((self . bits >> 10) & 1) != 0) } } impl W { # [doc = "Bit 0 - Device Active. Setting this bit enables the slave functionality."] # [inline (always)] # [must_use] pub fn sctr_active (& mut self) -> SCTR_ACTIVE_W <'_, SCTR_SPEC , 0 > { SCTR_ACTIVE_W :: new (self) } # [doc = "Bit 1 - General call response enable. This bit is only available in UCBxI2COA0. Modify only when UCSWRST = 1. 0b = Do not respond to a general call 1b = Respond to a general call"] # [inline (always)] # [must_use] pub fn sctr_gencall (& mut self) -> SCTR_GENCALL_W < SCTR_SPEC , 1 > { SCTR_GENCALL_W :: new (self) } # [doc = "Bit 2 - Slave Clock Stretch Enable"] # [inline (always)] # [must_use] pub fn sctr_sclkstretch (& mut self) -> SCTR_SCLKSTRETCH_W < SCTR_SPEC , 2 > { SCTR_SCLKSTRETCH_W :: new (self) } # [doc = "Bit 3 - Tx Empty Interrupt on TREQ"] # [inline (always)] # [must_use] pub fn sctr_txempty_on_treq (& mut self) -> SCTR_TXEMPTY_ON_TREQ_W < SCTR_SPEC , 3 > { SCTR_TXEMPTY_ON_TREQ_W :: new (self) } # [doc = "Bit 4 - Tx Trigger when slave FSM is in Tx Mode"] # [inline (always)] # [must_use] pub fn sctr_txtrig_txmode (& mut self) -> SCTR_TXTRIG_TXMODE_W < SCTR_SPEC , 4 > { SCTR_TXTRIG_TXMODE_W :: new (self) } # [doc = "Bit 5 - Tx transfer waits when stale data in Tx FIFO. This prevents stale bytes left in the TX FIFO from automatically being sent on the next I2C packet. Note: this should be used with TXEMPTY_ON_TREQ set to prevent the Slave State Machine from waiting for TX FIFO data without an interrupt notification when the FIFO data is stale."] # [inline (always)] # [must_use] pub fn sctr_txwait_stale_txfifo (& mut self) -> SCTR_TXWAIT_STALE_TXFIFO_W < SCTR_SPEC , 5 > { SCTR_TXWAIT_STALE_TXFIFO_W :: new (self) } # [doc = "Bit 6 - Rx full interrupt generated on RREQ condition as indicated in SSR"] # [inline (always)] # [must_use] pub fn sctr_rxfull_on_rreq (& mut self) -> SCTR_RXFULL_ON_RREQ_W < SCTR_SPEC , 6 > { SCTR_RXFULL_ON_RREQ_W :: new (self) } # [doc = "Bit 7 - Enable Default Host Address"] # [inline (always)] # [must_use] pub fn sctr_en_defhostadr (& mut self) -> SCTR_EN_DEFHOSTADR_W < SCTR_SPEC , 7 > { SCTR_EN_DEFHOSTADR_W :: new (self) } # [doc = "Bit 8 - Enable Alert Response Address"] # [inline (always)] # [must_use] pub fn sctr_en_alrespadr (& mut self) -> SCTR_EN_ALRESPADR_W < SCTR_SPEC , 8 > { SCTR_EN_ALRESPADR_W :: new (self) } # [doc = "Bit 9 - Enable Deault device address"] # [inline (always)] # [must_use] pub fn sctr_en_defdevadr (& mut self) -> SCTR_EN_DEFDEVADR_W < SCTR_SPEC , 9 > { SCTR_EN_DEFDEVADR_W :: new (self) } # [doc = "Bit 10 - Slave Wakeup Enable"] # [inline (always)] # [must_use] pub fn sctr_swuen (& mut self) -> SCTR_SWUEN_W < SCTR_SPEC , 10 > { SCTR_SWUEN_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "I2C Slave Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sctr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sctr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct SCTR_SPEC ; impl crate :: RegisterSpec for SCTR_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`sctr::R`](R) reader structure"] impl crate :: Readable for SCTR_SPEC { } # [doc = "`write(|w| ..)` method takes [`sctr::W`](W) writer structure"] impl crate :: Writable for SCTR_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets SCTR to value 0x0404"] impl crate :: Resettable for SCTR_SPEC { const RESET_VALUE : Self :: Ux = 0x0404 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/i2c0/int_event0_iset.rs:1:38309 [INFO] [stdout] | [INFO] [stdout] 1 | ...0_iset_mtxdone (& mut self) -> INT_EVENT0_ISET_MTXDONE_W < INT_EVENT0_ISET_SPEC , 1 > { INT_EVENT0_ISET_MTXDONE_W :: new (self) } # [d... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `INT_EVENT0_ISET` writer"] pub type W = crate :: W < INT_EVENT0_ISET_SPEC > ; # [doc = "Master Receive Data Interrupt Signals that a byte has been received\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_MRXDONE_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_MRXDONE_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_MRXDONE_SET = 1 , } impl From < INT_EVENT0_ISET_MRXDONE_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_MRXDONE_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_MRXDONE` writer - Master Receive Data Interrupt Signals that a byte has been received"] pub type INT_EVENT0_ISET_MRXDONE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_MRXDONE_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_MRXDONE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_mrxdone_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MRXDONE_AW :: INT_EVENT0_ISET_MRXDONE_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_mrxdone_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MRXDONE_AW :: INT_EVENT0_ISET_MRXDONE_SET) } } # [doc = "Master Transmit Transaction completed Interrupt\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_MTXDONE_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_MTXDONE_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_MTXDONE_SET = 1 , } impl From < INT_EVENT0_ISET_MTXDONE_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_MTXDONE_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_MTXDONE` writer - Master Transmit Transaction completed Interrupt"] pub type INT_EVENT0_ISET_MTXDONE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_MTXDONE_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_MTXDONE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_mtxdone_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MTXDONE_AW :: INT_EVENT0_ISET_MTXDONE_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_mtxdone_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MTXDONE_AW :: INT_EVENT0_ISET_MTXDONE_SET) } } # [doc = "Master Receive FIFO Trigger Trigger when RX FIFO contains &gt;= defined bytes\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_MRXFIFOTRG_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_MRXFIFOTRG_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_MRXFIFOTRG_SET = 1 , } impl From < INT_EVENT0_ISET_MRXFIFOTRG_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_MRXFIFOTRG_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_MRXFIFOTRG` writer - Master Receive FIFO Trigger Trigger when RX FIFO contains &gt;= defined bytes"] pub type INT_EVENT0_ISET_MRXFIFOTRG_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_MRXFIFOTRG_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_MRXFIFOTRG_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_mrxfifotrg_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MRXFIFOTRG_AW :: INT_EVENT0_ISET_MRXFIFOTRG_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_mrxfifotrg_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MRXFIFOTRG_AW :: INT_EVENT0_ISET_MRXFIFOTRG_SET) } } # [doc = "Master Transmit FIFO Trigger Trigger when Transmit FIFO contains &lt;= defined bytes\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_MTXFIFOTRG_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_MTXFIFOTRG_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_MTXFIFOTRG_SET = 1 , } impl From < INT_EVENT0_ISET_MTXFIFOTRG_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_MTXFIFOTRG_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_MTXFIFOTRG` writer - Master Transmit FIFO Trigger Trigger when Transmit FIFO contains &lt;= defined bytes"] pub type INT_EVENT0_ISET_MTXFIFOTRG_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_MTXFIFOTRG_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_MTXFIFOTRG_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_mtxfifotrg_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MTXFIFOTRG_AW :: INT_EVENT0_ISET_MTXFIFOTRG_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_mtxfifotrg_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MTXFIFOTRG_AW :: INT_EVENT0_ISET_MTXFIFOTRG_SET) } } # [doc = "RXFIFO full event.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_MRXFIFOFULL_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_MRXFIFOFULL_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_MRXFIFOFULL_SET = 1 , } impl From < INT_EVENT0_ISET_MRXFIFOFULL_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_MRXFIFOFULL_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_MRXFIFOFULL` writer - RXFIFO full event."] pub type INT_EVENT0_ISET_MRXFIFOFULL_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_MRXFIFOFULL_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_MRXFIFOFULL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_mrxfifofull_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MRXFIFOFULL_AW :: INT_EVENT0_ISET_MRXFIFOFULL_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_mrxfifofull_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MRXFIFOFULL_AW :: INT_EVENT0_ISET_MRXFIFOFULL_SET) } } # [doc = "Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_MTXEMPTY_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_MTXEMPTY_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_MTXEMPTY_SET = 1 , } impl From < INT_EVENT0_ISET_MTXEMPTY_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_MTXEMPTY_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_MTXEMPTY` writer - Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode."] pub type INT_EVENT0_ISET_MTXEMPTY_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_MTXEMPTY_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_MTXEMPTY_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_mtxempty_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MTXEMPTY_AW :: INT_EVENT0_ISET_MTXEMPTY_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_mtxempty_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MTXEMPTY_AW :: INT_EVENT0_ISET_MTXEMPTY_SET) } } # [doc = "Address/Data NACK Interrupt\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_MNACK_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_MNACK_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_MNACK_SET = 1 , } impl From < INT_EVENT0_ISET_MNACK_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_MNACK_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_MNACK` writer - Address/Data NACK Interrupt"] pub type INT_EVENT0_ISET_MNACK_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_MNACK_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_MNACK_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_mnack_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MNACK_AW :: INT_EVENT0_ISET_MNACK_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_mnack_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MNACK_AW :: INT_EVENT0_ISET_MNACK_SET) } } # [doc = "START Detection Interrupt\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_MSTART_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_MSTART_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_MSTART_SET = 1 , } impl From < INT_EVENT0_ISET_MSTART_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_MSTART_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_MSTART` writer - START Detection Interrupt"] pub type INT_EVENT0_ISET_MSTART_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_MSTART_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_MSTART_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_mstart_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MSTART_AW :: INT_EVENT0_ISET_MSTART_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_mstart_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MSTART_AW :: INT_EVENT0_ISET_MSTART_SET) } } # [doc = "STOP Detection Interrupt\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_MSTOP_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_MSTOP_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_MSTOP_SET = 1 , } impl From < INT_EVENT0_ISET_MSTOP_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_MSTOP_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_MSTOP` writer - STOP Detection Interrupt"] pub type INT_EVENT0_ISET_MSTOP_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_MSTOP_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_MSTOP_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_mstop_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MSTOP_AW :: INT_EVENT0_ISET_MSTOP_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_mstop_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MSTOP_AW :: INT_EVENT0_ISET_MSTOP_SET) } } # [doc = "Arbitration Lost Interrupt\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_MARBLOST_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_MARBLOST_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_MARBLOST_SET = 1 , } impl From < INT_EVENT0_ISET_MARBLOST_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_MARBLOST_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_MARBLOST` writer - Arbitration Lost Interrupt"] pub type INT_EVENT0_ISET_MARBLOST_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_MARBLOST_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_MARBLOST_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_marblost_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MARBLOST_AW :: INT_EVENT0_ISET_MARBLOST_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_marblost_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MARBLOST_AW :: INT_EVENT0_ISET_MARBLOST_SET) } } # [doc = "DMA Done 1 on Event Channel 2\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_MDMA_DONE1_2_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_MDMA_DONE1_2_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_MDMA_DONE1_2_SET = 1 , } impl From < INT_EVENT0_ISET_MDMA_DONE1_2_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_MDMA_DONE1_2_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_MDMA_DONE1_2` writer - DMA Done 1 on Event Channel 2"] pub type INT_EVENT0_ISET_MDMA_DONE1_2_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_MDMA_DONE1_2_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_MDMA_DONE1_2_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_mdma_done1_2_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MDMA_DONE1_2_AW :: INT_EVENT0_ISET_MDMA_DONE1_2_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_mdma_done1_2_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MDMA_DONE1_2_AW :: INT_EVENT0_ISET_MDMA_DONE1_2_SET) } } # [doc = "DMA Done 1 on Event Channel 3\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_MDMA_DONE1_3_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_MDMA_DONE1_3_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_MDMA_DONE1_3_SET = 1 , } impl From < INT_EVENT0_ISET_MDMA_DONE1_3_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_MDMA_DONE1_3_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_MDMA_DONE1_3` writer - DMA Done 1 on Event Channel 3"] pub type INT_EVENT0_ISET_MDMA_DONE1_3_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_MDMA_DONE1_3_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_MDMA_DONE1_3_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_mdma_done1_3_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MDMA_DONE1_3_AW :: INT_EVENT0_ISET_MDMA_DONE1_3_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_mdma_done1_3_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MDMA_DONE1_3_AW :: INT_EVENT0_ISET_MDMA_DONE1_3_SET) } } # [doc = "Master RX Pec Error Interrupt\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_MPEC_RX_ERR_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_MPEC_RX_ERR_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_MPEC_RX_ERR_SET = 1 , } impl From < INT_EVENT0_ISET_MPEC_RX_ERR_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_MPEC_RX_ERR_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_MPEC_RX_ERR` writer - Master RX Pec Error Interrupt"] pub type INT_EVENT0_ISET_MPEC_RX_ERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_MPEC_RX_ERR_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_MPEC_RX_ERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_mpec_rx_err_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MPEC_RX_ERR_AW :: INT_EVENT0_ISET_MPEC_RX_ERR_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_mpec_rx_err_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MPEC_RX_ERR_AW :: INT_EVENT0_ISET_MPEC_RX_ERR_SET) } } # [doc = "Timeout A interrupt\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_TIMEOUTA_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_TIMEOUTA_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_TIMEOUTA_SET = 1 , } impl From < INT_EVENT0_ISET_TIMEOUTA_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_TIMEOUTA_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_TIMEOUTA` writer - Timeout A interrupt"] pub type INT_EVENT0_ISET_TIMEOUTA_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_TIMEOUTA_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_TIMEOUTA_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_timeouta_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_TIMEOUTA_AW :: INT_EVENT0_ISET_TIMEOUTA_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_timeouta_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_TIMEOUTA_AW :: INT_EVENT0_ISET_TIMEOUTA_SET) } } # [doc = "Timeout B Interrupt\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_TIMEOUTB_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_TIMEOUTB_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_TIMEOUTB_SET = 1 , } impl From < INT_EVENT0_ISET_TIMEOUTB_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_TIMEOUTB_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_TIMEOUTB` writer - Timeout B Interrupt"] pub type INT_EVENT0_ISET_TIMEOUTB_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_TIMEOUTB_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_TIMEOUTB_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_timeoutb_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_TIMEOUTB_AW :: INT_EVENT0_ISET_TIMEOUTB_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_timeoutb_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_TIMEOUTB_AW :: INT_EVENT0_ISET_TIMEOUTB_SET) } } # [doc = "Slave Receive Data Interrupt Signals that a byte has been received\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_SRXDONE_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_SRXDONE_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_SRXDONE_SET = 1 , } impl From < INT_EVENT0_ISET_SRXDONE_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_SRXDONE_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_SRXDONE` writer - Slave Receive Data Interrupt Signals that a byte has been received"] pub type INT_EVENT0_ISET_SRXDONE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_SRXDONE_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_SRXDONE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_srxdone_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_SRXDONE_AW :: INT_EVENT0_ISET_SRXDONE_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_srxdone_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_SRXDONE_AW :: INT_EVENT0_ISET_SRXDONE_SET) } } # [doc = "Slave Transmit Transaction completed Interrupt\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_STXDONE_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_STXDONE_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_STXDONE_SET = 1 , } impl From < INT_EVENT0_ISET_STXDONE_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_STXDONE_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_STXDONE` writer - Slave Transmit Transaction completed Interrupt"] pub type INT_EVENT0_ISET_STXDONE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_STXDONE_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_STXDONE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_stxdone_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_STXDONE_AW :: INT_EVENT0_ISET_STXDONE_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_stxdone_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_STXDONE_AW :: INT_EVENT0_ISET_STXDONE_SET) } } # [doc = "Slave Receive FIFO Trigger\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_SRXFIFOTRG_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_SRXFIFOTRG_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_SRXFIFOTRG_SET = 1 , } impl From < INT_EVENT0_ISET_SRXFIFOTRG_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_SRXFIFOTRG_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_SRXFIFOTRG` writer - Slave Receive FIFO Trigger"] pub type INT_EVENT0_ISET_SRXFIFOTRG_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_SRXFIFOTRG_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_SRXFIFOTRG_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_srxfifotrg_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_SRXFIFOTRG_AW :: INT_EVENT0_ISET_SRXFIFOTRG_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_srxfifotrg_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_SRXFIFOTRG_AW :: INT_EVENT0_ISET_SRXFIFOTRG_SET) } } # [doc = "Slave Transmit FIFO Trigger\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_STXFIFOTRG_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_STXFIFOTRG_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_STXFIFOTRG_SET = 1 , } impl From < INT_EVENT0_ISET_STXFIFOTRG_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_STXFIFOTRG_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_STXFIFOTRG` writer - Slave Transmit FIFO Trigger"] pub type INT_EVENT0_ISET_STXFIFOTRG_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_STXFIFOTRG_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_STXFIFOTRG_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_stxfifotrg_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_STXFIFOTRG_AW :: INT_EVENT0_ISET_STXFIFOTRG_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_stxfifotrg_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_STXFIFOTRG_AW :: INT_EVENT0_ISET_STXFIFOTRG_SET) } } # [doc = "RXFIFO full event. This interrupt is set if an RX FIFO is full.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_SRXFIFOFULL_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_SRXFIFOFULL_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_SRXFIFOFULL_SET = 1 , } impl From < INT_EVENT0_ISET_SRXFIFOFULL_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_SRXFIFOFULL_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_SRXFIFOFULL` writer - RXFIFO full event. This interrupt is set if an RX FIFO is full."] pub type INT_EVENT0_ISET_SRXFIFOFULL_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_SRXFIFOFULL_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_SRXFIFOFULL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_srxfifofull_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_SRXFIFOFULL_AW :: INT_EVENT0_ISET_SRXFIFOFULL_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_srxfifofull_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_SRXFIFOFULL_AW :: INT_EVENT0_ISET_SRXFIFOFULL_SET) } } # [doc = "Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_STXEMPTY_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_STXEMPTY_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_STXEMPTY_SET = 1 , } impl From < INT_EVENT0_ISET_STXEMPTY_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_STXEMPTY_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_STXEMPTY` writer - Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode."] pub type INT_EVENT0_ISET_STXEMPTY_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_STXEMPTY_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_STXEMPTY_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_stxempty_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_STXEMPTY_AW :: INT_EVENT0_ISET_STXEMPTY_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_stxempty_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_STXEMPTY_AW :: INT_EVENT0_ISET_STXEMPTY_SET) } } # [doc = "Start Condition Interrupt\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_SSTART_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_SSTART_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_SSTART_SET = 1 , } impl From < INT_EVENT0_ISET_SSTART_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_SSTART_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_SSTART` writer - Start Condition Interrupt"] pub type INT_EVENT0_ISET_SSTART_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_SSTART_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_SSTART_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_sstart_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_SSTART_AW :: INT_EVENT0_ISET_SSTART_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_sstart_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_SSTART_AW :: INT_EVENT0_ISET_SSTART_SET) } } # [doc = "Stop Condition Interrupt\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_SSTOP_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_SSTOP_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_SSTOP_SET = 1 , } impl From < INT_EVENT0_ISET_SSTOP_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_SSTOP_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_SSTOP` writer - Stop Condition Interrupt"] pub type INT_EVENT0_ISET_SSTOP_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_SSTOP_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_SSTOP_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_sstop_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_SSTOP_AW :: INT_EVENT0_ISET_SSTOP_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_sstop_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_SSTOP_AW :: INT_EVENT0_ISET_SSTOP_SET) } } # [doc = "General Call Interrupt\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_SGENCALL_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_SGENCALL_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_SGENCALL_SET = 1 , } impl From < INT_EVENT0_ISET_SGENCALL_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_SGENCALL_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_SGENCALL` writer - General Call Interrupt"] pub type INT_EVENT0_ISET_SGENCALL_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_SGENCALL_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_SGENCALL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_sgencall_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_SGENCALL_AW :: INT_EVENT0_ISET_SGENCALL_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_sgencall_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_SGENCALL_AW :: INT_EVENT0_ISET_SGENCALL_SET) } } # [doc = "DMA Done 1 on Event Channel 2\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_SDMA_DONE1_2_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_SDMA_DONE1_2_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_SDMA_DONE1_2_SET = 1 , } impl From < INT_EVENT0_ISET_SDMA_DONE1_2_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_SDMA_DONE1_2_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_SDMA_DONE1_2` writer - DMA Done 1 on Event Channel 2"] pub type INT_EVENT0_ISET_SDMA_DONE1_2_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_SDMA_DONE1_2_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_SDMA_DONE1_2_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_sdma_done1_2_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_SDMA_DONE1_2_AW :: INT_EVENT0_ISET_SDMA_DONE1_2_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_sdma_done1_2_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_SDMA_DONE1_2_AW :: INT_EVENT0_ISET_SDMA_DONE1_2_SET) } } # [doc = "DMA Done 1 on Event Channel 3\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_SDMA_DONE1_3_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_SDMA_DONE1_3_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_SDMA_DONE1_3_SET = 1 , } impl From < INT_EVENT0_ISET_SDMA_DONE1_3_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_SDMA_DONE1_3_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_SDMA_DONE1_3` writer - DMA Done 1 on Event Channel 3"] pub type INT_EVENT0_ISET_SDMA_DONE1_3_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_SDMA_DONE1_3_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_SDMA_DONE1_3_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_sdma_done1_3_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_SDMA_DONE1_3_AW :: INT_EVENT0_ISET_SDMA_DONE1_3_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_sdma_done1_3_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_SDMA_DONE1_3_AW :: INT_EVENT0_ISET_SDMA_DONE1_3_SET) } } # [doc = "Slave RX Pec Error Interrupt\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_SPEC_RX_ERR_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_SPEC_RX_ERR_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_SPEC_RX_ERR_SET = 1 , } impl From < INT_EVENT0_ISET_SPEC_RX_ERR_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_SPEC_RX_ERR_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_SPEC_RX_ERR` writer - Slave RX Pec Error Interrupt"] pub type INT_EVENT0_ISET_SPEC_RX_ERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_SPEC_RX_ERR_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_SPEC_RX_ERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_spec_rx_err_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_SPEC_RX_ERR_AW :: INT_EVENT0_ISET_SPEC_RX_ERR_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_spec_rx_err_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_SPEC_RX_ERR_AW :: INT_EVENT0_ISET_SPEC_RX_ERR_SET) } } # [doc = "Slave TX FIFO underflow\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_STX_UNFL_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_STX_UNFL_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_STX_UNFL_SET = 1 , } impl From < INT_EVENT0_ISET_STX_UNFL_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_STX_UNFL_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_STX_UNFL` writer - Slave TX FIFO underflow"] pub type INT_EVENT0_ISET_STX_UNFL_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_STX_UNFL_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_STX_UNFL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_stx_unfl_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_STX_UNFL_AW :: INT_EVENT0_ISET_STX_UNFL_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_stx_unfl_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_STX_UNFL_AW :: INT_EVENT0_ISET_STX_UNFL_SET) } } # [doc = "Slave RX FIFO overflow\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_SRX_OVFL_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_SRX_OVFL_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_SRX_OVFL_SET = 1 , } impl From < INT_EVENT0_ISET_SRX_OVFL_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_SRX_OVFL_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_SRX_OVFL` writer - Slave RX FIFO overflow"] pub type INT_EVENT0_ISET_SRX_OVFL_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_SRX_OVFL_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_SRX_OVFL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_srx_ovfl_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_SRX_OVFL_AW :: INT_EVENT0_ISET_SRX_OVFL_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_srx_ovfl_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_SRX_OVFL_AW :: INT_EVENT0_ISET_SRX_OVFL_SET) } } # [doc = "Slave Arbitration Lost\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_SARBLOST_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_SARBLOST_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_SARBLOST_SET = 1 , } impl From < INT_EVENT0_ISET_SARBLOST_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_SARBLOST_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_SARBLOST` writer - Slave Arbitration Lost"] pub type INT_EVENT0_ISET_SARBLOST_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_SARBLOST_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_SARBLOST_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_sarblost_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_SARBLOST_AW :: INT_EVENT0_ISET_SARBLOST_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_sarblost_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_SARBLOST_AW :: INT_EVENT0_ISET_SARBLOST_SET) } } # [doc = "Interrupt overflow\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_INTR_OVFL_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_INTR_OVFL_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_INTR_OVFL_SET = 1 , } impl From < INT_EVENT0_ISET_INTR_OVFL_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_INTR_OVFL_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_INTR_OVFL` writer - Interrupt overflow"] pub type INT_EVENT0_ISET_INTR_OVFL_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_INTR_OVFL_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_INTR_OVFL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_intr_ovfl_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_INTR_OVFL_AW :: INT_EVENT0_ISET_INTR_OVFL_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_intr_ovfl_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_INTR_OVFL_AW :: INT_EVENT0_ISET_INTR_OVFL_SET) } } impl W { # [doc = "Bit 0 - Master Receive Data Interrupt Signals that a byte has been received"] # [inline (always)] # [must_use] pub fn int_event0_iset_mrxdone (& mut self) -> INT_EVENT0_ISET_MRXDONE_W < INT_EVENT0_ISET_SPEC , 0 > { INT_EVENT0_ISET_MRXDONE_W :: new (self) } # [doc = "Bit 1 - Master Transmit Transaction completed Interrupt"] # [inline (always)] # [must_use] pub fn int_event0_iset_mtxdone (& mut self) -> INT_EVENT0_ISET_MTXDONE_W <'_, INT_EVENT0_ISET_SPEC , 1 > { INT_EVENT0_ISET_MTXDONE_W :: new (self) } # [doc = "Bit 2 - Master Receive FIFO Trigger Trigger when RX FIFO contains &gt;= defined bytes"] # [inline (always)] # [must_use] pub fn int_event0_iset_mrxfifotrg (& mut self) -> INT_EVENT0_ISET_MRXFIFOTRG_W < INT_EVENT0_ISET_SPEC , 2 > { INT_EVENT0_ISET_MRXFIFOTRG_W :: new (self) } # [doc = "Bit 3 - Master Transmit FIFO Trigger Trigger when Transmit FIFO contains &lt;= defined bytes"] # [inline (always)] # [must_use] pub fn int_event0_iset_mtxfifotrg (& mut self) -> INT_EVENT0_ISET_MTXFIFOTRG_W < INT_EVENT0_ISET_SPEC , 3 > { INT_EVENT0_ISET_MTXFIFOTRG_W :: new (self) } # [doc = "Bit 4 - RXFIFO full event."] # [inline (always)] # [must_use] pub fn int_event0_iset_mrxfifofull (& mut self) -> INT_EVENT0_ISET_MRXFIFOFULL_W < INT_EVENT0_ISET_SPEC , 4 > { INT_EVENT0_ISET_MRXFIFOFULL_W :: new (self) } # [doc = "Bit 5 - Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode."] # [inline (always)] # [must_use] pub fn int_event0_iset_mtxempty (& mut self) -> INT_EVENT0_ISET_MTXEMPTY_W < INT_EVENT0_ISET_SPEC , 5 > { INT_EVENT0_ISET_MTXEMPTY_W :: new (self) } # [doc = "Bit 7 - Address/Data NACK Interrupt"] # [inline (always)] # [must_use] pub fn int_event0_iset_mnack (& mut self) -> INT_EVENT0_ISET_MNACK_W < INT_EVENT0_ISET_SPEC , 7 > { INT_EVENT0_ISET_MNACK_W :: new (self) } # [doc = "Bit 8 - START Detection Interrupt"] # [inline (always)] # [must_use] pub fn int_event0_iset_mstart (& mut self) -> INT_EVENT0_ISET_MSTART_W < INT_EVENT0_ISET_SPEC , 8 > { INT_EVENT0_ISET_MSTART_W :: new (self) } # [doc = "Bit 9 - STOP Detection Interrupt"] # [inline (always)] # [must_use] pub fn int_event0_iset_mstop (& mut self) -> INT_EVENT0_ISET_MSTOP_W < INT_EVENT0_ISET_SPEC , 9 > { INT_EVENT0_ISET_MSTOP_W :: new (self) } # [doc = "Bit 10 - Arbitration Lost Interrupt"] # [inline (always)] # [must_use] pub fn int_event0_iset_marblost (& mut self) -> INT_EVENT0_ISET_MARBLOST_W < INT_EVENT0_ISET_SPEC , 10 > { INT_EVENT0_ISET_MARBLOST_W :: new (self) } # [doc = "Bit 11 - DMA Done 1 on Event Channel 2"] # [inline (always)] # [must_use] pub fn int_event0_iset_mdma_done1_2 (& mut self) -> INT_EVENT0_ISET_MDMA_DONE1_2_W < INT_EVENT0_ISET_SPEC , 11 > { INT_EVENT0_ISET_MDMA_DONE1_2_W :: new (self) } # [doc = "Bit 12 - DMA Done 1 on Event Channel 3"] # [inline (always)] # [must_use] pub fn int_event0_iset_mdma_done1_3 (& mut self) -> INT_EVENT0_ISET_MDMA_DONE1_3_W < INT_EVENT0_ISET_SPEC , 12 > { INT_EVENT0_ISET_MDMA_DONE1_3_W :: new (self) } # [doc = "Bit 13 - Master RX Pec Error Interrupt"] # [inline (always)] # [must_use] pub fn int_event0_iset_mpec_rx_err (& mut self) -> INT_EVENT0_ISET_MPEC_RX_ERR_W < INT_EVENT0_ISET_SPEC , 13 > { INT_EVENT0_ISET_MPEC_RX_ERR_W :: new (self) } # [doc = "Bit 14 - Timeout A interrupt"] # [inline (always)] # [must_use] pub fn int_event0_iset_timeouta (& mut self) -> INT_EVENT0_ISET_TIMEOUTA_W < INT_EVENT0_ISET_SPEC , 14 > { INT_EVENT0_ISET_TIMEOUTA_W :: new (self) } # [doc = "Bit 15 - Timeout B Interrupt"] # [inline (always)] # [must_use] pub fn int_event0_iset_timeoutb (& mut self) -> INT_EVENT0_ISET_TIMEOUTB_W < INT_EVENT0_ISET_SPEC , 15 > { INT_EVENT0_ISET_TIMEOUTB_W :: new (self) } # [doc = "Bit 16 - Slave Receive Data Interrupt Signals that a byte has been received"] # [inline (always)] # [must_use] pub fn int_event0_iset_srxdone (& mut self) -> INT_EVENT0_ISET_SRXDONE_W < INT_EVENT0_ISET_SPEC , 16 > { INT_EVENT0_ISET_SRXDONE_W :: new (self) } # [doc = "Bit 17 - Slave Transmit Transaction completed Interrupt"] # [inline (always)] # [must_use] pub fn int_event0_iset_stxdone (& mut self) -> INT_EVENT0_ISET_STXDONE_W < INT_EVENT0_ISET_SPEC , 17 > { INT_EVENT0_ISET_STXDONE_W :: new (self) } # [doc = "Bit 18 - Slave Receive FIFO Trigger"] # [inline (always)] # [must_use] pub fn int_event0_iset_srxfifotrg (& mut self) -> INT_EVENT0_ISET_SRXFIFOTRG_W < INT_EVENT0_ISET_SPEC , 18 > { INT_EVENT0_ISET_SRXFIFOTRG_W :: new (self) } # [doc = "Bit 19 - Slave Transmit FIFO Trigger"] # [inline (always)] # [must_use] pub fn int_event0_iset_stxfifotrg (& mut self) -> INT_EVENT0_ISET_STXFIFOTRG_W < INT_EVENT0_ISET_SPEC , 19 > { INT_EVENT0_ISET_STXFIFOTRG_W :: new (self) } # [doc = "Bit 20 - RXFIFO full event. This interrupt is set if an RX FIFO is full."] # [inline (always)] # [must_use] pub fn int_event0_iset_srxfifofull (& mut self) -> INT_EVENT0_ISET_SRXFIFOFULL_W < INT_EVENT0_ISET_SPEC , 20 > { INT_EVENT0_ISET_SRXFIFOFULL_W :: new (self) } # [doc = "Bit 21 - Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode."] # [inline (always)] # [must_use] pub fn int_event0_iset_stxempty (& mut self) -> INT_EVENT0_ISET_STXEMPTY_W < INT_EVENT0_ISET_SPEC , 21 > { INT_EVENT0_ISET_STXEMPTY_W :: new (self) } # [doc = "Bit 22 - Start Condition Interrupt"] # [inline (always)] # [must_use] pub fn int_event0_iset_sstart (& mut self) -> INT_EVENT0_ISET_SSTART_W < INT_EVENT0_ISET_SPEC , 22 > { INT_EVENT0_ISET_SSTART_W :: new (self) } # [doc = "Bit 23 - Stop Condition Interrupt"] # [inline (always)] # [must_use] pub fn int_event0_iset_sstop (& mut self) -> INT_EVENT0_ISET_SSTOP_W < INT_EVENT0_ISET_SPEC , 23 > { INT_EVENT0_ISET_SSTOP_W :: new (self) } # [doc = "Bit 24 - General Call Interrupt"] # [inline (always)] # [must_use] pub fn int_event0_iset_sgencall (& mut self) -> INT_EVENT0_ISET_SGENCALL_W < INT_EVENT0_ISET_SPEC , 24 > { INT_EVENT0_ISET_SGENCALL_W :: new (self) } # [doc = "Bit 25 - DMA Done 1 on Event Channel 2"] # [inline (always)] # [must_use] pub fn int_event0_iset_sdma_done1_2 (& mut self) -> INT_EVENT0_ISET_SDMA_DONE1_2_W < INT_EVENT0_ISET_SPEC , 25 > { INT_EVENT0_ISET_SDMA_DONE1_2_W :: new (self) } # [doc = "Bit 26 - DMA Done 1 on Event Channel 3"] # [inline (always)] # [must_use] pub fn int_event0_iset_sdma_done1_3 (& mut self) -> INT_EVENT0_ISET_SDMA_DONE1_3_W < INT_EVENT0_ISET_SPEC , 26 > { INT_EVENT0_ISET_SDMA_DONE1_3_W :: new (self) } # [doc = "Bit 27 - Slave RX Pec Error Interrupt"] # [inline (always)] # [must_use] pub fn int_event0_iset_spec_rx_err (& mut self) -> INT_EVENT0_ISET_SPEC_RX_ERR_W < INT_EVENT0_ISET_SPEC , 27 > { INT_EVENT0_ISET_SPEC_RX_ERR_W :: new (self) } # [doc = "Bit 28 - Slave TX FIFO underflow"] # [inline (always)] # [must_use] pub fn int_event0_iset_stx_unfl (& mut self) -> INT_EVENT0_ISET_STX_UNFL_W < INT_EVENT0_ISET_SPEC , 28 > { INT_EVENT0_ISET_STX_UNFL_W :: new (self) } # [doc = "Bit 29 - Slave RX FIFO overflow"] # [inline (always)] # [must_use] pub fn int_event0_iset_srx_ovfl (& mut self) -> INT_EVENT0_ISET_SRX_OVFL_W < INT_EVENT0_ISET_SPEC , 29 > { INT_EVENT0_ISET_SRX_OVFL_W :: new (self) } # [doc = "Bit 30 - Slave Arbitration Lost"] # [inline (always)] # [must_use] pub fn int_event0_iset_sarblost (& mut self) -> INT_EVENT0_ISET_SARBLOST_W < INT_EVENT0_ISET_SPEC , 30 > { INT_EVENT0_ISET_SARBLOST_W :: new (self) } # [doc = "Bit 31 - Interrupt overflow"] # [inline (always)] # [must_use] pub fn int_event0_iset_intr_ovfl (& mut self) -> INT_EVENT0_ISET_INTR_OVFL_W < INT_EVENT0_ISET_SPEC , 31 > { INT_EVENT0_ISET_INTR_OVFL_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Interrupt set\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_event0_iset::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct INT_EVENT0_ISET_SPEC ; impl crate :: RegisterSpec for INT_EVENT0_ISET_SPEC { type Ux = u32 ; } # [doc = "`write(|w| ..)` method takes [`int_event0_iset::W`](W) writer structure"] impl crate :: Writable for INT_EVENT0_ISET_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets INT_EVENT0_ISET to value 0"] impl crate :: Resettable for INT_EVENT0_ISET_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/timg4/ccctl_01.rs:1:35145 [INFO] [stdout] | [INFO] [stdout] 1 | ...pub fn ccctl_01_ccupd (& mut self) -> CCCTL_01_CCUPD_W < CCCTL_01_SPEC , 18 > { CCCTL_01_CCUPD_W :: new (self) } # [doc = "Bits 22:24 ... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `CCCTL_01[%s]` reader"] pub type R = crate :: R < CCCTL_01_SPEC > ; # [doc = "Register `CCCTL_01[%s]` writer"] pub type W = crate :: W < CCCTL_01_SPEC > ; # [doc = "Field `CCCTL_01_CCOND` reader - Capture Condition. #br# Specifies the condition that generates a capture pulse. 4h-Fh = Reserved"] pub type CCCTL_01_CCOND_R = crate :: FieldReader < CCCTL_01_CCOND_A > ; # [doc = "Capture Condition. #br# Specifies the condition that generates a capture pulse. 4h-Fh = Reserved\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum CCCTL_01_CCOND_A { # [doc = "0: NOCAPTURE"] CCCTL_01_CCOND_NOCAPTURE = 0 , # [doc = "1: CC_TRIG_RISE"] CCCTL_01_CCOND_CC_TRIG_RISE = 1 , # [doc = "2: CC_TRIG_FALL"] CCCTL_01_CCOND_CC_TRIG_FALL = 2 , # [doc = "3: CC_TRIG_EDGE"] CCCTL_01_CCOND_CC_TRIG_EDGE = 3 , } impl From < CCCTL_01_CCOND_A > for u8 { # [inline (always)] fn from (variant : CCCTL_01_CCOND_A) -> Self { variant as _ } } impl crate :: FieldSpec for CCCTL_01_CCOND_A { type Ux = u8 ; } impl CCCTL_01_CCOND_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < CCCTL_01_CCOND_A > { match self . bits { 0 => Some (CCCTL_01_CCOND_A :: CCCTL_01_CCOND_NOCAPTURE) , 1 => Some (CCCTL_01_CCOND_A :: CCCTL_01_CCOND_CC_TRIG_RISE) , 2 => Some (CCCTL_01_CCOND_A :: CCCTL_01_CCOND_CC_TRIG_FALL) , 3 => Some (CCCTL_01_CCOND_A :: CCCTL_01_CCOND_CC_TRIG_EDGE) , _ => None , } } # [doc = "NOCAPTURE"] # [inline (always)] pub fn is_ccctl_01_ccond_nocapture (& self) -> bool { * self == CCCTL_01_CCOND_A :: CCCTL_01_CCOND_NOCAPTURE } # [doc = "CC_TRIG_RISE"] # [inline (always)] pub fn is_ccctl_01_ccond_cc_trig_rise (& self) -> bool { * self == CCCTL_01_CCOND_A :: CCCTL_01_CCOND_CC_TRIG_RISE } # [doc = "CC_TRIG_FALL"] # [inline (always)] pub fn is_ccctl_01_ccond_cc_trig_fall (& self) -> bool { * self == CCCTL_01_CCOND_A :: CCCTL_01_CCOND_CC_TRIG_FALL } # [doc = "CC_TRIG_EDGE"] # [inline (always)] pub fn is_ccctl_01_ccond_cc_trig_edge (& self) -> bool { * self == CCCTL_01_CCOND_A :: CCCTL_01_CCOND_CC_TRIG_EDGE } } # [doc = "Field `CCCTL_01_CCOND` writer - Capture Condition. #br# Specifies the condition that generates a capture pulse. 4h-Fh = Reserved"] pub type CCCTL_01_CCOND_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 3 , O , CCCTL_01_CCOND_A > ; impl < 'a , REG , const O : u8 > CCCTL_01_CCOND_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "NOCAPTURE"] # [inline (always)] pub fn ccctl_01_ccond_nocapture (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CCOND_A :: CCCTL_01_CCOND_NOCAPTURE) } # [doc = "CC_TRIG_RISE"] # [inline (always)] pub fn ccctl_01_ccond_cc_trig_rise (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CCOND_A :: CCCTL_01_CCOND_CC_TRIG_RISE) } # [doc = "CC_TRIG_FALL"] # [inline (always)] pub fn ccctl_01_ccond_cc_trig_fall (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CCOND_A :: CCCTL_01_CCOND_CC_TRIG_FALL) } # [doc = "CC_TRIG_EDGE"] # [inline (always)] pub fn ccctl_01_ccond_cc_trig_edge (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CCOND_A :: CCCTL_01_CCOND_CC_TRIG_EDGE) } } # [doc = "Field `CCCTL_01_ACOND` reader - Advance Condition. #br# Specifies the condition that generates an advance pulse. 6h-Fh = Reserved"] pub type CCCTL_01_ACOND_R = crate :: FieldReader < CCCTL_01_ACOND_A > ; # [doc = "Advance Condition. #br# Specifies the condition that generates an advance pulse. 6h-Fh = Reserved\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum CCCTL_01_ACOND_A { # [doc = "0: TIMCLK"] CCCTL_01_ACOND_TIMCLK = 0 , # [doc = "1: CC_TRIG_RISE"] CCCTL_01_ACOND_CC_TRIG_RISE = 1 , # [doc = "2: CC_TRIG_FALL"] CCCTL_01_ACOND_CC_TRIG_FALL = 2 , # [doc = "3: CC_TRIG_EDGE"] CCCTL_01_ACOND_CC_TRIG_EDGE = 3 , # [doc = "5: CC_TRIG_HIGH"] CCCTL_01_ACOND_CC_TRIG_HIGH = 5 , } impl From < CCCTL_01_ACOND_A > for u8 { # [inline (always)] fn from (variant : CCCTL_01_ACOND_A) -> Self { variant as _ } } impl crate :: FieldSpec for CCCTL_01_ACOND_A { type Ux = u8 ; } impl CCCTL_01_ACOND_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < CCCTL_01_ACOND_A > { match self . bits { 0 => Some (CCCTL_01_ACOND_A :: CCCTL_01_ACOND_TIMCLK) , 1 => Some (CCCTL_01_ACOND_A :: CCCTL_01_ACOND_CC_TRIG_RISE) , 2 => Some (CCCTL_01_ACOND_A :: CCCTL_01_ACOND_CC_TRIG_FALL) , 3 => Some (CCCTL_01_ACOND_A :: CCCTL_01_ACOND_CC_TRIG_EDGE) , 5 => Some (CCCTL_01_ACOND_A :: CCCTL_01_ACOND_CC_TRIG_HIGH) , _ => None , } } # [doc = "TIMCLK"] # [inline (always)] pub fn is_ccctl_01_acond_timclk (& self) -> bool { * self == CCCTL_01_ACOND_A :: CCCTL_01_ACOND_TIMCLK } # [doc = "CC_TRIG_RISE"] # [inline (always)] pub fn is_ccctl_01_acond_cc_trig_rise (& self) -> bool { * self == CCCTL_01_ACOND_A :: CCCTL_01_ACOND_CC_TRIG_RISE } # [doc = "CC_TRIG_FALL"] # [inline (always)] pub fn is_ccctl_01_acond_cc_trig_fall (& self) -> bool { * self == CCCTL_01_ACOND_A :: CCCTL_01_ACOND_CC_TRIG_FALL } # [doc = "CC_TRIG_EDGE"] # [inline (always)] pub fn is_ccctl_01_acond_cc_trig_edge (& self) -> bool { * self == CCCTL_01_ACOND_A :: CCCTL_01_ACOND_CC_TRIG_EDGE } # [doc = "CC_TRIG_HIGH"] # [inline (always)] pub fn is_ccctl_01_acond_cc_trig_high (& self) -> bool { * self == CCCTL_01_ACOND_A :: CCCTL_01_ACOND_CC_TRIG_HIGH } } # [doc = "Field `CCCTL_01_ACOND` writer - Advance Condition. #br# Specifies the condition that generates an advance pulse. 6h-Fh = Reserved"] pub type CCCTL_01_ACOND_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 3 , O , CCCTL_01_ACOND_A > ; impl < 'a , REG , const O : u8 > CCCTL_01_ACOND_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "TIMCLK"] # [inline (always)] pub fn ccctl_01_acond_timclk (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_ACOND_A :: CCCTL_01_ACOND_TIMCLK) } # [doc = "CC_TRIG_RISE"] # [inline (always)] pub fn ccctl_01_acond_cc_trig_rise (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_ACOND_A :: CCCTL_01_ACOND_CC_TRIG_RISE) } # [doc = "CC_TRIG_FALL"] # [inline (always)] pub fn ccctl_01_acond_cc_trig_fall (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_ACOND_A :: CCCTL_01_ACOND_CC_TRIG_FALL) } # [doc = "CC_TRIG_EDGE"] # [inline (always)] pub fn ccctl_01_acond_cc_trig_edge (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_ACOND_A :: CCCTL_01_ACOND_CC_TRIG_EDGE) } # [doc = "CC_TRIG_HIGH"] # [inline (always)] pub fn ccctl_01_acond_cc_trig_high (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_ACOND_A :: CCCTL_01_ACOND_CC_TRIG_HIGH) } } # [doc = "Field `CCCTL_01_LCOND` reader - Load Condition. #br# Specifies the condition that generates a load pulse. 4h-Fh = Reserved"] pub type CCCTL_01_LCOND_R = crate :: FieldReader < CCCTL_01_LCOND_A > ; # [doc = "Load Condition. #br# Specifies the condition that generates a load pulse. 4h-Fh = Reserved\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum CCCTL_01_LCOND_A { # [doc = "1: CC_TRIG_RISE"] CCCTL_01_LCOND_CC_TRIG_RISE = 1 , # [doc = "2: CC_TRIG_FALL"] CCCTL_01_LCOND_CC_TRIG_FALL = 2 , # [doc = "3: CC_TRIG_EDGE"] CCCTL_01_LCOND_CC_TRIG_EDGE = 3 , } impl From < CCCTL_01_LCOND_A > for u8 { # [inline (always)] fn from (variant : CCCTL_01_LCOND_A) -> Self { variant as _ } } impl crate :: FieldSpec for CCCTL_01_LCOND_A { type Ux = u8 ; } impl CCCTL_01_LCOND_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < CCCTL_01_LCOND_A > { match self . bits { 1 => Some (CCCTL_01_LCOND_A :: CCCTL_01_LCOND_CC_TRIG_RISE) , 2 => Some (CCCTL_01_LCOND_A :: CCCTL_01_LCOND_CC_TRIG_FALL) , 3 => Some (CCCTL_01_LCOND_A :: CCCTL_01_LCOND_CC_TRIG_EDGE) , _ => None , } } # [doc = "CC_TRIG_RISE"] # [inline (always)] pub fn is_ccctl_01_lcond_cc_trig_rise (& self) -> bool { * self == CCCTL_01_LCOND_A :: CCCTL_01_LCOND_CC_TRIG_RISE } # [doc = "CC_TRIG_FALL"] # [inline (always)] pub fn is_ccctl_01_lcond_cc_trig_fall (& self) -> bool { * self == CCCTL_01_LCOND_A :: CCCTL_01_LCOND_CC_TRIG_FALL } # [doc = "CC_TRIG_EDGE"] # [inline (always)] pub fn is_ccctl_01_lcond_cc_trig_edge (& self) -> bool { * self == CCCTL_01_LCOND_A :: CCCTL_01_LCOND_CC_TRIG_EDGE } } # [doc = "Field `CCCTL_01_LCOND` writer - Load Condition. #br# Specifies the condition that generates a load pulse. 4h-Fh = Reserved"] pub type CCCTL_01_LCOND_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 3 , O , CCCTL_01_LCOND_A > ; impl < 'a , REG , const O : u8 > CCCTL_01_LCOND_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "CC_TRIG_RISE"] # [inline (always)] pub fn ccctl_01_lcond_cc_trig_rise (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_LCOND_A :: CCCTL_01_LCOND_CC_TRIG_RISE) } # [doc = "CC_TRIG_FALL"] # [inline (always)] pub fn ccctl_01_lcond_cc_trig_fall (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_LCOND_A :: CCCTL_01_LCOND_CC_TRIG_FALL) } # [doc = "CC_TRIG_EDGE"] # [inline (always)] pub fn ccctl_01_lcond_cc_trig_edge (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_LCOND_A :: CCCTL_01_LCOND_CC_TRIG_EDGE) } } # [doc = "Field `CCCTL_01_ZCOND` reader - Zero Condition. #br# This field specifies the condition that generates a zero pulse. 4h-Fh = Reserved"] pub type CCCTL_01_ZCOND_R = crate :: FieldReader < CCCTL_01_ZCOND_A > ; # [doc = "Zero Condition. #br# This field specifies the condition that generates a zero pulse. 4h-Fh = Reserved\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum CCCTL_01_ZCOND_A { # [doc = "1: CC_TRIG_RISE"] CCCTL_01_ZCOND_CC_TRIG_RISE = 1 , # [doc = "2: CC_TRIG_FALL"] CCCTL_01_ZCOND_CC_TRIG_FALL = 2 , # [doc = "3: CC_TRIG_EDGE"] CCCTL_01_ZCOND_CC_TRIG_EDGE = 3 , } impl From < CCCTL_01_ZCOND_A > for u8 { # [inline (always)] fn from (variant : CCCTL_01_ZCOND_A) -> Self { variant as _ } } impl crate :: FieldSpec for CCCTL_01_ZCOND_A { type Ux = u8 ; } impl CCCTL_01_ZCOND_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < CCCTL_01_ZCOND_A > { match self . bits { 1 => Some (CCCTL_01_ZCOND_A :: CCCTL_01_ZCOND_CC_TRIG_RISE) , 2 => Some (CCCTL_01_ZCOND_A :: CCCTL_01_ZCOND_CC_TRIG_FALL) , 3 => Some (CCCTL_01_ZCOND_A :: CCCTL_01_ZCOND_CC_TRIG_EDGE) , _ => None , } } # [doc = "CC_TRIG_RISE"] # [inline (always)] pub fn is_ccctl_01_zcond_cc_trig_rise (& self) -> bool { * self == CCCTL_01_ZCOND_A :: CCCTL_01_ZCOND_CC_TRIG_RISE } # [doc = "CC_TRIG_FALL"] # [inline (always)] pub fn is_ccctl_01_zcond_cc_trig_fall (& self) -> bool { * self == CCCTL_01_ZCOND_A :: CCCTL_01_ZCOND_CC_TRIG_FALL } # [doc = "CC_TRIG_EDGE"] # [inline (always)] pub fn is_ccctl_01_zcond_cc_trig_edge (& self) -> bool { * self == CCCTL_01_ZCOND_A :: CCCTL_01_ZCOND_CC_TRIG_EDGE } } # [doc = "Field `CCCTL_01_ZCOND` writer - Zero Condition. #br# This field specifies the condition that generates a zero pulse. 4h-Fh = Reserved"] pub type CCCTL_01_ZCOND_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 3 , O , CCCTL_01_ZCOND_A > ; impl < 'a , REG , const O : u8 > CCCTL_01_ZCOND_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "CC_TRIG_RISE"] # [inline (always)] pub fn ccctl_01_zcond_cc_trig_rise (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_ZCOND_A :: CCCTL_01_ZCOND_CC_TRIG_RISE) } # [doc = "CC_TRIG_FALL"] # [inline (always)] pub fn ccctl_01_zcond_cc_trig_fall (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_ZCOND_A :: CCCTL_01_ZCOND_CC_TRIG_FALL) } # [doc = "CC_TRIG_EDGE"] # [inline (always)] pub fn ccctl_01_zcond_cc_trig_edge (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_ZCOND_A :: CCCTL_01_ZCOND_CC_TRIG_EDGE) } } # [doc = "Field `CCCTL_01_COC` reader - Capture or Compare. #br# Specifies whether the corresponding CC register is used as a capture register or a compare register (never both)."] pub type CCCTL_01_COC_R = crate :: BitReader < CCCTL_01_COC_A > ; # [doc = "Capture or Compare. #br# Specifies whether the corresponding CC register is used as a capture register or a compare register (never both).\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CCCTL_01_COC_A { # [doc = "0: COMPARE"] CCCTL_01_COC_COMPARE = 0 , # [doc = "1: CAPTURE"] CCCTL_01_COC_CAPTURE = 1 , } impl From < CCCTL_01_COC_A > for bool { # [inline (always)] fn from (variant : CCCTL_01_COC_A) -> Self { variant as u8 != 0 } } impl CCCTL_01_COC_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CCCTL_01_COC_A { match self . bits { false => CCCTL_01_COC_A :: CCCTL_01_COC_COMPARE , true => CCCTL_01_COC_A :: CCCTL_01_COC_CAPTURE , } } # [doc = "COMPARE"] # [inline (always)] pub fn is_ccctl_01_coc_compare (& self) -> bool { * self == CCCTL_01_COC_A :: CCCTL_01_COC_COMPARE } # [doc = "CAPTURE"] # [inline (always)] pub fn is_ccctl_01_coc_capture (& self) -> bool { * self == CCCTL_01_COC_A :: CCCTL_01_COC_CAPTURE } } # [doc = "Field `CCCTL_01_COC` writer - Capture or Compare. #br# Specifies whether the corresponding CC register is used as a capture register or a compare register (never both)."] pub type CCCTL_01_COC_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CCCTL_01_COC_A > ; impl < 'a , REG , const O : u8 > CCCTL_01_COC_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "COMPARE"] # [inline (always)] pub fn ccctl_01_coc_compare (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_COC_A :: CCCTL_01_COC_COMPARE) } # [doc = "CAPTURE"] # [inline (always)] pub fn ccctl_01_coc_capture (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_COC_A :: CCCTL_01_COC_CAPTURE) } } # [doc = "Field `CCCTL_01_CCUPD` reader - Capture and Compare Update Method This field controls how updates to the pipelined capture and compare register are performed (when operating in compare mode, COC=0)."] pub type CCCTL_01_CCUPD_R = crate :: FieldReader < CCCTL_01_CCUPD_A > ; # [doc = "Capture and Compare Update Method This field controls how updates to the pipelined capture and compare register are performed (when operating in compare mode, COC=0).\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum CCCTL_01_CCUPD_A { # [doc = "0: IMMEDIATELY"] CCCTL_01_CCUPD_IMMEDIATELY = 0 , # [doc = "1: ZERO_EVT"] CCCTL_01_CCUPD_ZERO_EVT = 1 , # [doc = "2: COMPARE_DOWN_EVT"] CCCTL_01_CCUPD_COMPARE_DOWN_EVT = 2 , # [doc = "3: COMPARE_UP_EVT"] CCCTL_01_CCUPD_COMPARE_UP_EVT = 3 , # [doc = "4: ZERO_LOAD_EVT"] CCCTL_01_CCUPD_ZERO_LOAD_EVT = 4 , # [doc = "5: ZERO_RC_ZERO_EVT"] CCCTL_01_CCUPD_ZERO_RC_ZERO_EVT = 5 , # [doc = "6: TRIG"] CCCTL_01_CCUPD_TRIG = 6 , } impl From < CCCTL_01_CCUPD_A > for u8 { # [inline (always)] fn from (variant : CCCTL_01_CCUPD_A) -> Self { variant as _ } } impl crate :: FieldSpec for CCCTL_01_CCUPD_A { type Ux = u8 ; } impl CCCTL_01_CCUPD_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < CCCTL_01_CCUPD_A > { match self . bits { 0 => Some (CCCTL_01_CCUPD_A :: CCCTL_01_CCUPD_IMMEDIATELY) , 1 => Some (CCCTL_01_CCUPD_A :: CCCTL_01_CCUPD_ZERO_EVT) , 2 => Some (CCCTL_01_CCUPD_A :: CCCTL_01_CCUPD_COMPARE_DOWN_EVT) , 3 => Some (CCCTL_01_CCUPD_A :: CCCTL_01_CCUPD_COMPARE_UP_EVT) , 4 => Some (CCCTL_01_CCUPD_A :: CCCTL_01_CCUPD_ZERO_LOAD_EVT) , 5 => Some (CCCTL_01_CCUPD_A :: CCCTL_01_CCUPD_ZERO_RC_ZERO_EVT) , 6 => Some (CCCTL_01_CCUPD_A :: CCCTL_01_CCUPD_TRIG) , _ => None , } } # [doc = "IMMEDIATELY"] # [inline (always)] pub fn is_ccctl_01_ccupd_immediately (& self) -> bool { * self == CCCTL_01_CCUPD_A :: CCCTL_01_CCUPD_IMMEDIATELY } # [doc = "ZERO_EVT"] # [inline (always)] pub fn is_ccctl_01_ccupd_zero_evt (& self) -> bool { * self == CCCTL_01_CCUPD_A :: CCCTL_01_CCUPD_ZERO_EVT } # [doc = "COMPARE_DOWN_EVT"] # [inline (always)] pub fn is_ccctl_01_ccupd_compare_down_evt (& self) -> bool { * self == CCCTL_01_CCUPD_A :: CCCTL_01_CCUPD_COMPARE_DOWN_EVT } # [doc = "COMPARE_UP_EVT"] # [inline (always)] pub fn is_ccctl_01_ccupd_compare_up_evt (& self) -> bool { * self == CCCTL_01_CCUPD_A :: CCCTL_01_CCUPD_COMPARE_UP_EVT } # [doc = "ZERO_LOAD_EVT"] # [inline (always)] pub fn is_ccctl_01_ccupd_zero_load_evt (& self) -> bool { * self == CCCTL_01_CCUPD_A :: CCCTL_01_CCUPD_ZERO_LOAD_EVT } # [doc = "ZERO_RC_ZERO_EVT"] # [inline (always)] pub fn is_ccctl_01_ccupd_zero_rc_zero_evt (& self) -> bool { * self == CCCTL_01_CCUPD_A :: CCCTL_01_CCUPD_ZERO_RC_ZERO_EVT } # [doc = "TRIG"] # [inline (always)] pub fn is_ccctl_01_ccupd_trig (& self) -> bool { * self == CCCTL_01_CCUPD_A :: CCCTL_01_CCUPD_TRIG } } # [doc = "Field `CCCTL_01_CCUPD` writer - Capture and Compare Update Method This field controls how updates to the pipelined capture and compare register are performed (when operating in compare mode, COC=0)."] pub type CCCTL_01_CCUPD_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 3 , O , CCCTL_01_CCUPD_A > ; impl < 'a , REG , const O : u8 > CCCTL_01_CCUPD_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "IMMEDIATELY"] # [inline (always)] pub fn ccctl_01_ccupd_immediately (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CCUPD_A :: CCCTL_01_CCUPD_IMMEDIATELY) } # [doc = "ZERO_EVT"] # [inline (always)] pub fn ccctl_01_ccupd_zero_evt (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CCUPD_A :: CCCTL_01_CCUPD_ZERO_EVT) } # [doc = "COMPARE_DOWN_EVT"] # [inline (always)] pub fn ccctl_01_ccupd_compare_down_evt (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CCUPD_A :: CCCTL_01_CCUPD_COMPARE_DOWN_EVT) } # [doc = "COMPARE_UP_EVT"] # [inline (always)] pub fn ccctl_01_ccupd_compare_up_evt (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CCUPD_A :: CCCTL_01_CCUPD_COMPARE_UP_EVT) } # [doc = "ZERO_LOAD_EVT"] # [inline (always)] pub fn ccctl_01_ccupd_zero_load_evt (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CCUPD_A :: CCCTL_01_CCUPD_ZERO_LOAD_EVT) } # [doc = "ZERO_RC_ZERO_EVT"] # [inline (always)] pub fn ccctl_01_ccupd_zero_rc_zero_evt (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CCUPD_A :: CCCTL_01_CCUPD_ZERO_RC_ZERO_EVT) } # [doc = "TRIG"] # [inline (always)] pub fn ccctl_01_ccupd_trig (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CCUPD_A :: CCCTL_01_CCUPD_TRIG) } } # [doc = "Field `CCCTL_01_CC2SELU` reader - Selects the source second CCU event."] pub type CCCTL_01_CC2SELU_R = crate :: FieldReader < CCCTL_01_CC2SELU_A > ; # [doc = "Selects the source second CCU event.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum CCCTL_01_CC2SELU_A { # [doc = "0: SEL_CCU0"] CCCTL_01_CC2SELU_SEL_CCU0 = 0 , # [doc = "1: SEL_CCU1"] CCCTL_01_CC2SELU_SEL_CCU1 = 1 , # [doc = "2: SEL_CCU2"] CCCTL_01_CC2SELU_SEL_CCU2 = 2 , # [doc = "3: SEL_CCU3"] CCCTL_01_CC2SELU_SEL_CCU3 = 3 , # [doc = "4: SEL_CCU4"] CCCTL_01_CC2SELU_SEL_CCU4 = 4 , # [doc = "5: SEL_CCU5"] CCCTL_01_CC2SELU_SEL_CCU5 = 5 , } impl From < CCCTL_01_CC2SELU_A > for u8 { # [inline (always)] fn from (variant : CCCTL_01_CC2SELU_A) -> Self { variant as _ } } impl crate :: FieldSpec for CCCTL_01_CC2SELU_A { type Ux = u8 ; } impl CCCTL_01_CC2SELU_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < CCCTL_01_CC2SELU_A > { match self . bits { 0 => Some (CCCTL_01_CC2SELU_A :: CCCTL_01_CC2SELU_SEL_CCU0) , 1 => Some (CCCTL_01_CC2SELU_A :: CCCTL_01_CC2SELU_SEL_CCU1) , 2 => Some (CCCTL_01_CC2SELU_A :: CCCTL_01_CC2SELU_SEL_CCU2) , 3 => Some (CCCTL_01_CC2SELU_A :: CCCTL_01_CC2SELU_SEL_CCU3) , 4 => Some (CCCTL_01_CC2SELU_A :: CCCTL_01_CC2SELU_SEL_CCU4) , 5 => Some (CCCTL_01_CC2SELU_A :: CCCTL_01_CC2SELU_SEL_CCU5) , _ => None , } } # [doc = "SEL_CCU0"] # [inline (always)] pub fn is_ccctl_01_cc2selu_sel_ccu0 (& self) -> bool { * self == CCCTL_01_CC2SELU_A :: CCCTL_01_CC2SELU_SEL_CCU0 } # [doc = "SEL_CCU1"] # [inline (always)] pub fn is_ccctl_01_cc2selu_sel_ccu1 (& self) -> bool { * self == CCCTL_01_CC2SELU_A :: CCCTL_01_CC2SELU_SEL_CCU1 } # [doc = "SEL_CCU2"] # [inline (always)] pub fn is_ccctl_01_cc2selu_sel_ccu2 (& self) -> bool { * self == CCCTL_01_CC2SELU_A :: CCCTL_01_CC2SELU_SEL_CCU2 } # [doc = "SEL_CCU3"] # [inline (always)] pub fn is_ccctl_01_cc2selu_sel_ccu3 (& self) -> bool { * self == CCCTL_01_CC2SELU_A :: CCCTL_01_CC2SELU_SEL_CCU3 } # [doc = "SEL_CCU4"] # [inline (always)] pub fn is_ccctl_01_cc2selu_sel_ccu4 (& self) -> bool { * self == CCCTL_01_CC2SELU_A :: CCCTL_01_CC2SELU_SEL_CCU4 } # [doc = "SEL_CCU5"] # [inline (always)] pub fn is_ccctl_01_cc2selu_sel_ccu5 (& self) -> bool { * self == CCCTL_01_CC2SELU_A :: CCCTL_01_CC2SELU_SEL_CCU5 } } # [doc = "Field `CCCTL_01_CC2SELU` writer - Selects the source second CCU event."] pub type CCCTL_01_CC2SELU_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 3 , O , CCCTL_01_CC2SELU_A > ; impl < 'a , REG , const O : u8 > CCCTL_01_CC2SELU_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "SEL_CCU0"] # [inline (always)] pub fn ccctl_01_cc2selu_sel_ccu0 (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CC2SELU_A :: CCCTL_01_CC2SELU_SEL_CCU0) } # [doc = "SEL_CCU1"] # [inline (always)] pub fn ccctl_01_cc2selu_sel_ccu1 (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CC2SELU_A :: CCCTL_01_CC2SELU_SEL_CCU1) } # [doc = "SEL_CCU2"] # [inline (always)] pub fn ccctl_01_cc2selu_sel_ccu2 (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CC2SELU_A :: CCCTL_01_CC2SELU_SEL_CCU2) } # [doc = "SEL_CCU3"] # [inline (always)] pub fn ccctl_01_cc2selu_sel_ccu3 (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CC2SELU_A :: CCCTL_01_CC2SELU_SEL_CCU3) } # [doc = "SEL_CCU4"] # [inline (always)] pub fn ccctl_01_cc2selu_sel_ccu4 (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CC2SELU_A :: CCCTL_01_CC2SELU_SEL_CCU4) } # [doc = "SEL_CCU5"] # [inline (always)] pub fn ccctl_01_cc2selu_sel_ccu5 (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CC2SELU_A :: CCCTL_01_CC2SELU_SEL_CCU5) } } # [doc = "Field `CCCTL_01_CCACTUPD` reader - CCACT shadow register Update Method This field controls how updates to the CCCACT shadow register are performed"] pub type CCCTL_01_CCACTUPD_R = crate :: FieldReader < CCCTL_01_CCACTUPD_A > ; # [doc = "CCACT shadow register Update Method This field controls how updates to the CCCACT shadow register are performed\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum CCCTL_01_CCACTUPD_A { # [doc = "0: IMMEDIATELY"] CCCTL_01_CCACTUPD_IMMEDIATELY = 0 , # [doc = "1: ZERO_EVT"] CCCTL_01_CCACTUPD_ZERO_EVT = 1 , # [doc = "2: COMPARE_DOWN_EVT"] CCCTL_01_CCACTUPD_COMPARE_DOWN_EVT = 2 , # [doc = "3: COMPARE_UP_EVT"] CCCTL_01_CCACTUPD_COMPARE_UP_EVT = 3 , # [doc = "4: ZERO_LOAD_EVT"] CCCTL_01_CCACTUPD_ZERO_LOAD_EVT = 4 , # [doc = "5: ZERO_RC_ZERO_EVT"] CCCTL_01_CCACTUPD_ZERO_RC_ZERO_EVT = 5 , # [doc = "6: TRIG"] CCCTL_01_CCACTUPD_TRIG = 6 , } impl From < CCCTL_01_CCACTUPD_A > for u8 { # [inline (always)] fn from (variant : CCCTL_01_CCACTUPD_A) -> Self { variant as _ } } impl crate :: FieldSpec for CCCTL_01_CCACTUPD_A { type Ux = u8 ; } impl CCCTL_01_CCACTUPD_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < CCCTL_01_CCACTUPD_A > { match self . bits { 0 => Some (CCCTL_01_CCACTUPD_A :: CCCTL_01_CCACTUPD_IMMEDIATELY) , 1 => Some (CCCTL_01_CCACTUPD_A :: CCCTL_01_CCACTUPD_ZERO_EVT) , 2 => Some (CCCTL_01_CCACTUPD_A :: CCCTL_01_CCACTUPD_COMPARE_DOWN_EVT) , 3 => Some (CCCTL_01_CCACTUPD_A :: CCCTL_01_CCACTUPD_COMPARE_UP_EVT) , 4 => Some (CCCTL_01_CCACTUPD_A :: CCCTL_01_CCACTUPD_ZERO_LOAD_EVT) , 5 => Some (CCCTL_01_CCACTUPD_A :: CCCTL_01_CCACTUPD_ZERO_RC_ZERO_EVT) , 6 => Some (CCCTL_01_CCACTUPD_A :: CCCTL_01_CCACTUPD_TRIG) , _ => None , } } # [doc = "IMMEDIATELY"] # [inline (always)] pub fn is_ccctl_01_ccactupd_immediately (& self) -> bool { * self == CCCTL_01_CCACTUPD_A :: CCCTL_01_CCACTUPD_IMMEDIATELY } # [doc = "ZERO_EVT"] # [inline (always)] pub fn is_ccctl_01_ccactupd_zero_evt (& self) -> bool { * self == CCCTL_01_CCACTUPD_A :: CCCTL_01_CCACTUPD_ZERO_EVT } # [doc = "COMPARE_DOWN_EVT"] # [inline (always)] pub fn is_ccctl_01_ccactupd_compare_down_evt (& self) -> bool { * self == CCCTL_01_CCACTUPD_A :: CCCTL_01_CCACTUPD_COMPARE_DOWN_EVT } # [doc = "COMPARE_UP_EVT"] # [inline (always)] pub fn is_ccctl_01_ccactupd_compare_up_evt (& self) -> bool { * self == CCCTL_01_CCACTUPD_A :: CCCTL_01_CCACTUPD_COMPARE_UP_EVT } # [doc = "ZERO_LOAD_EVT"] # [inline (always)] pub fn is_ccctl_01_ccactupd_zero_load_evt (& self) -> bool { * self == CCCTL_01_CCACTUPD_A :: CCCTL_01_CCACTUPD_ZERO_LOAD_EVT } # [doc = "ZERO_RC_ZERO_EVT"] # [inline (always)] pub fn is_ccctl_01_ccactupd_zero_rc_zero_evt (& self) -> bool { * self == CCCTL_01_CCACTUPD_A :: CCCTL_01_CCACTUPD_ZERO_RC_ZERO_EVT } # [doc = "TRIG"] # [inline (always)] pub fn is_ccctl_01_ccactupd_trig (& self) -> bool { * self == CCCTL_01_CCACTUPD_A :: CCCTL_01_CCACTUPD_TRIG } } # [doc = "Field `CCCTL_01_CCACTUPD` writer - CCACT shadow register Update Method This field controls how updates to the CCCACT shadow register are performed"] pub type CCCTL_01_CCACTUPD_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 3 , O , CCCTL_01_CCACTUPD_A > ; impl < 'a , REG , const O : u8 > CCCTL_01_CCACTUPD_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "IMMEDIATELY"] # [inline (always)] pub fn ccctl_01_ccactupd_immediately (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CCACTUPD_A :: CCCTL_01_CCACTUPD_IMMEDIATELY) } # [doc = "ZERO_EVT"] # [inline (always)] pub fn ccctl_01_ccactupd_zero_evt (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CCACTUPD_A :: CCCTL_01_CCACTUPD_ZERO_EVT) } # [doc = "COMPARE_DOWN_EVT"] # [inline (always)] pub fn ccctl_01_ccactupd_compare_down_evt (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CCACTUPD_A :: CCCTL_01_CCACTUPD_COMPARE_DOWN_EVT) } # [doc = "COMPARE_UP_EVT"] # [inline (always)] pub fn ccctl_01_ccactupd_compare_up_evt (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CCACTUPD_A :: CCCTL_01_CCACTUPD_COMPARE_UP_EVT) } # [doc = "ZERO_LOAD_EVT"] # [inline (always)] pub fn ccctl_01_ccactupd_zero_load_evt (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CCACTUPD_A :: CCCTL_01_CCACTUPD_ZERO_LOAD_EVT) } # [doc = "ZERO_RC_ZERO_EVT"] # [inline (always)] pub fn ccctl_01_ccactupd_zero_rc_zero_evt (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CCACTUPD_A :: CCCTL_01_CCACTUPD_ZERO_RC_ZERO_EVT) } # [doc = "TRIG"] # [inline (always)] pub fn ccctl_01_ccactupd_trig (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CCACTUPD_A :: CCCTL_01_CCACTUPD_TRIG) } } # [doc = "Field `CCCTL_01_CC2SELD` reader - Selects the source second CCD event."] pub type CCCTL_01_CC2SELD_R = crate :: FieldReader < CCCTL_01_CC2SELD_A > ; # [doc = "Selects the source second CCD event.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum CCCTL_01_CC2SELD_A { # [doc = "0: SEL_CCD0"] CCCTL_01_CC2SELD_SEL_CCD0 = 0 , # [doc = "1: SEL_CCD1"] CCCTL_01_CC2SELD_SEL_CCD1 = 1 , # [doc = "2: SEL_CCD2"] CCCTL_01_CC2SELD_SEL_CCD2 = 2 , # [doc = "3: SEL_CCD3"] CCCTL_01_CC2SELD_SEL_CCD3 = 3 , # [doc = "4: SEL_CCD4"] CCCTL_01_CC2SELD_SEL_CCD4 = 4 , # [doc = "5: SEL_CCD5"] CCCTL_01_CC2SELD_SEL_CCD5 = 5 , } impl From < CCCTL_01_CC2SELD_A > for u8 { # [inline (always)] fn from (variant : CCCTL_01_CC2SELD_A) -> Self { variant as _ } } impl crate :: FieldSpec for CCCTL_01_CC2SELD_A { type Ux = u8 ; } impl CCCTL_01_CC2SELD_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < CCCTL_01_CC2SELD_A > { match self . bits { 0 => Some (CCCTL_01_CC2SELD_A :: CCCTL_01_CC2SELD_SEL_CCD0) , 1 => Some (CCCTL_01_CC2SELD_A :: CCCTL_01_CC2SELD_SEL_CCD1) , 2 => Some (CCCTL_01_CC2SELD_A :: CCCTL_01_CC2SELD_SEL_CCD2) , 3 => Some (CCCTL_01_CC2SELD_A :: CCCTL_01_CC2SELD_SEL_CCD3) , 4 => Some (CCCTL_01_CC2SELD_A :: CCCTL_01_CC2SELD_SEL_CCD4) , 5 => Some (CCCTL_01_CC2SELD_A :: CCCTL_01_CC2SELD_SEL_CCD5) , _ => None , } } # [doc = "SEL_CCD0"] # [inline (always)] pub fn is_ccctl_01_cc2seld_sel_ccd0 (& self) -> bool { * self == CCCTL_01_CC2SELD_A :: CCCTL_01_CC2SELD_SEL_CCD0 } # [doc = "SEL_CCD1"] # [inline (always)] pub fn is_ccctl_01_cc2seld_sel_ccd1 (& self) -> bool { * self == CCCTL_01_CC2SELD_A :: CCCTL_01_CC2SELD_SEL_CCD1 } # [doc = "SEL_CCD2"] # [inline (always)] pub fn is_ccctl_01_cc2seld_sel_ccd2 (& self) -> bool { * self == CCCTL_01_CC2SELD_A :: CCCTL_01_CC2SELD_SEL_CCD2 } # [doc = "SEL_CCD3"] # [inline (always)] pub fn is_ccctl_01_cc2seld_sel_ccd3 (& self) -> bool { * self == CCCTL_01_CC2SELD_A :: CCCTL_01_CC2SELD_SEL_CCD3 } # [doc = "SEL_CCD4"] # [inline (always)] pub fn is_ccctl_01_cc2seld_sel_ccd4 (& self) -> bool { * self == CCCTL_01_CC2SELD_A :: CCCTL_01_CC2SELD_SEL_CCD4 } # [doc = "SEL_CCD5"] # [inline (always)] pub fn is_ccctl_01_cc2seld_sel_ccd5 (& self) -> bool { * self == CCCTL_01_CC2SELD_A :: CCCTL_01_CC2SELD_SEL_CCD5 } } # [doc = "Field `CCCTL_01_CC2SELD` writer - Selects the source second CCD event."] pub type CCCTL_01_CC2SELD_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 3 , O , CCCTL_01_CC2SELD_A > ; impl < 'a , REG , const O : u8 > CCCTL_01_CC2SELD_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "SEL_CCD0"] # [inline (always)] pub fn ccctl_01_cc2seld_sel_ccd0 (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CC2SELD_A :: CCCTL_01_CC2SELD_SEL_CCD0) } # [doc = "SEL_CCD1"] # [inline (always)] pub fn ccctl_01_cc2seld_sel_ccd1 (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CC2SELD_A :: CCCTL_01_CC2SELD_SEL_CCD1) } # [doc = "SEL_CCD2"] # [inline (always)] pub fn ccctl_01_cc2seld_sel_ccd2 (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CC2SELD_A :: CCCTL_01_CC2SELD_SEL_CCD2) } # [doc = "SEL_CCD3"] # [inline (always)] pub fn ccctl_01_cc2seld_sel_ccd3 (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CC2SELD_A :: CCCTL_01_CC2SELD_SEL_CCD3) } # [doc = "SEL_CCD4"] # [inline (always)] pub fn ccctl_01_cc2seld_sel_ccd4 (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CC2SELD_A :: CCCTL_01_CC2SELD_SEL_CCD4) } # [doc = "SEL_CCD5"] # [inline (always)] pub fn ccctl_01_cc2seld_sel_ccd5 (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CC2SELD_A :: CCCTL_01_CC2SELD_SEL_CCD5) } } impl R { # [doc = "Bits 0:2 - Capture Condition. #br# Specifies the condition that generates a capture pulse. 4h-Fh = Reserved"] # [inline (always)] pub fn ccctl_01_ccond (& self) -> CCCTL_01_CCOND_R { CCCTL_01_CCOND_R :: new ((self . bits & 7) as u8) } # [doc = "Bits 4:6 - Advance Condition. #br# Specifies the condition that generates an advance pulse. 6h-Fh = Reserved"] # [inline (always)] pub fn ccctl_01_acond (& self) -> CCCTL_01_ACOND_R { CCCTL_01_ACOND_R :: new (((self . bits >> 4) & 7) as u8) } # [doc = "Bits 8:10 - Load Condition. #br# Specifies the condition that generates a load pulse. 4h-Fh = Reserved"] # [inline (always)] pub fn ccctl_01_lcond (& self) -> CCCTL_01_LCOND_R { CCCTL_01_LCOND_R :: new (((self . bits >> 8) & 7) as u8) } # [doc = "Bits 12:14 - Zero Condition. #br# This field specifies the condition that generates a zero pulse. 4h-Fh = Reserved"] # [inline (always)] pub fn ccctl_01_zcond (& self) -> CCCTL_01_ZCOND_R { CCCTL_01_ZCOND_R :: new (((self . bits >> 12) & 7) as u8) } # [doc = "Bit 17 - Capture or Compare. #br# Specifies whether the corresponding CC register is used as a capture register or a compare register (never both)."] # [inline (always)] pub fn ccctl_01_coc (& self) -> CCCTL_01_COC_R { CCCTL_01_COC_R :: new (((self . bits >> 17) & 1) != 0) } # [doc = "Bits 18:20 - Capture and Compare Update Method This field controls how updates to the pipelined capture and compare register are performed (when operating in compare mode, COC=0)."] # [inline (always)] pub fn ccctl_01_ccupd (& self) -> CCCTL_01_CCUPD_R { CCCTL_01_CCUPD_R :: new (((self . bits >> 18) & 7) as u8) } # [doc = "Bits 22:24 - Selects the source second CCU event."] # [inline (always)] pub fn ccctl_01_cc2selu (& self) -> CCCTL_01_CC2SELU_R { CCCTL_01_CC2SELU_R :: new (((self . bits >> 22) & 7) as u8) } # [doc = "Bits 26:28 - CCACT shadow register Update Method This field controls how updates to the CCCACT shadow register are performed"] # [inline (always)] pub fn ccctl_01_ccactupd (& self) -> CCCTL_01_CCACTUPD_R { CCCTL_01_CCACTUPD_R :: new (((self . bits >> 26) & 7) as u8) } # [doc = "Bits 29:31 - Selects the source second CCD event."] # [inline (always)] pub fn ccctl_01_cc2seld (& self) -> CCCTL_01_CC2SELD_R { CCCTL_01_CC2SELD_R :: new (((self . bits >> 29) & 7) as u8) } } impl W { # [doc = "Bits 0:2 - Capture Condition. #br# Specifies the condition that generates a capture pulse. 4h-Fh = Reserved"] # [inline (always)] # [must_use] pub fn ccctl_01_ccond (& mut self) -> CCCTL_01_CCOND_W < CCCTL_01_SPEC , 0 > { CCCTL_01_CCOND_W :: new (self) } # [doc = "Bits 4:6 - Advance Condition. #br# Specifies the condition that generates an advance pulse. 6h-Fh = Reserved"] # [inline (always)] # [must_use] pub fn ccctl_01_acond (& mut self) -> CCCTL_01_ACOND_W < CCCTL_01_SPEC , 4 > { CCCTL_01_ACOND_W :: new (self) } # [doc = "Bits 8:10 - Load Condition. #br# Specifies the condition that generates a load pulse. 4h-Fh = Reserved"] # [inline (always)] # [must_use] pub fn ccctl_01_lcond (& mut self) -> CCCTL_01_LCOND_W < CCCTL_01_SPEC , 8 > { CCCTL_01_LCOND_W :: new (self) } # [doc = "Bits 12:14 - Zero Condition. #br# This field specifies the condition that generates a zero pulse. 4h-Fh = Reserved"] # [inline (always)] # [must_use] pub fn ccctl_01_zcond (& mut self) -> CCCTL_01_ZCOND_W < CCCTL_01_SPEC , 12 > { CCCTL_01_ZCOND_W :: new (self) } # [doc = "Bit 17 - Capture or Compare. #br# Specifies whether the corresponding CC register is used as a capture register or a compare register (never both)."] # [inline (always)] # [must_use] pub fn ccctl_01_coc (& mut self) -> CCCTL_01_COC_W < CCCTL_01_SPEC , 17 > { CCCTL_01_COC_W :: new (self) } # [doc = "Bits 18:20 - Capture and Compare Update Method This field controls how updates to the pipelined capture and compare register are performed (when operating in compare mode, COC=0)."] # [inline (always)] # [must_use] pub fn ccctl_01_ccupd (& mut self) -> CCCTL_01_CCUPD_W <'_, CCCTL_01_SPEC , 18 > { CCCTL_01_CCUPD_W :: new (self) } # [doc = "Bits 22:24 - Selects the source second CCU event."] # [inline (always)] # [must_use] pub fn ccctl_01_cc2selu (& mut self) -> CCCTL_01_CC2SELU_W < CCCTL_01_SPEC , 22 > { CCCTL_01_CC2SELU_W :: new (self) } # [doc = "Bits 26:28 - CCACT shadow register Update Method This field controls how updates to the CCCACT shadow register are performed"] # [inline (always)] # [must_use] pub fn ccctl_01_ccactupd (& mut self) -> CCCTL_01_CCACTUPD_W < CCCTL_01_SPEC , 26 > { CCCTL_01_CCACTUPD_W :: new (self) } # [doc = "Bits 29:31 - Selects the source second CCD event."] # [inline (always)] # [must_use] pub fn ccctl_01_cc2seld (& mut self) -> CCCTL_01_CC2SELD_W < CCCTL_01_SPEC , 29 > { CCCTL_01_CC2SELD_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Capture or Compare Control Registers\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ccctl_01::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ccctl_01::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CCCTL_01_SPEC ; impl crate :: RegisterSpec for CCCTL_01_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`ccctl_01::R`](R) reader structure"] impl crate :: Readable for CCCTL_01_SPEC { } # [doc = "`write(|w| ..)` method takes [`ccctl_01::W`](W) writer structure"] impl crate :: Writable for CCCTL_01_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets CCCTL_01[%s] [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/i2c1/int_event1_iset.rs:1:6113 [INFO] [stdout] | [INFO] [stdout] 1 | ...t_stxfifotrg (& mut self) -> INT_EVENT1_ISET_STXFIFOTRG_W < INT_EVENT1_ISET_SPEC , 3 > { INT_EVENT1_ISET_STXFIFOTRG_W :: new (self) } ... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `INT_EVENT1_ISET` writer"] pub type W = crate :: W < INT_EVENT1_ISET_SPEC > ; # [doc = "Master Receive FIFO Trigger Trigger when RX FIFO contains &gt;= defined bytes\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT1_ISET_MRXFIFOTRG_AW { # [doc = "0: NO_EFFECT"] INT_EVENT1_ISET_MRXFIFOTRG_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT1_ISET_MRXFIFOTRG_SET = 1 , } impl From < INT_EVENT1_ISET_MRXFIFOTRG_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT1_ISET_MRXFIFOTRG_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT1_ISET_MRXFIFOTRG` writer - Master Receive FIFO Trigger Trigger when RX FIFO contains &gt;= defined bytes"] pub type INT_EVENT1_ISET_MRXFIFOTRG_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT1_ISET_MRXFIFOTRG_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT1_ISET_MRXFIFOTRG_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event1_iset_mrxfifotrg_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_ISET_MRXFIFOTRG_AW :: INT_EVENT1_ISET_MRXFIFOTRG_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event1_iset_mrxfifotrg_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_ISET_MRXFIFOTRG_AW :: INT_EVENT1_ISET_MRXFIFOTRG_SET) } } # [doc = "Master Transmit FIFO Trigger Trigger when Transmit FIFO contains &lt;= defined bytes\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT1_ISET_MTXFIFOTRG_AW { # [doc = "0: NO_EFFECT"] INT_EVENT1_ISET_MTXFIFOTRG_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT1_ISET_MTXFIFOTRG_SET = 1 , } impl From < INT_EVENT1_ISET_MTXFIFOTRG_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT1_ISET_MTXFIFOTRG_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT1_ISET_MTXFIFOTRG` writer - Master Transmit FIFO Trigger Trigger when Transmit FIFO contains &lt;= defined bytes"] pub type INT_EVENT1_ISET_MTXFIFOTRG_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT1_ISET_MTXFIFOTRG_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT1_ISET_MTXFIFOTRG_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event1_iset_mtxfifotrg_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_ISET_MTXFIFOTRG_AW :: INT_EVENT1_ISET_MTXFIFOTRG_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event1_iset_mtxfifotrg_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_ISET_MTXFIFOTRG_AW :: INT_EVENT1_ISET_MTXFIFOTRG_SET) } } # [doc = "Slave Receive FIFO Trigger\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT1_ISET_SRXFIFOTRG_AW { # [doc = "0: NO_EFFECT"] INT_EVENT1_ISET_SRXFIFOTRG_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT1_ISET_SRXFIFOTRG_SET = 1 , } impl From < INT_EVENT1_ISET_SRXFIFOTRG_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT1_ISET_SRXFIFOTRG_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT1_ISET_SRXFIFOTRG` writer - Slave Receive FIFO Trigger"] pub type INT_EVENT1_ISET_SRXFIFOTRG_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT1_ISET_SRXFIFOTRG_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT1_ISET_SRXFIFOTRG_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event1_iset_srxfifotrg_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_ISET_SRXFIFOTRG_AW :: INT_EVENT1_ISET_SRXFIFOTRG_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event1_iset_srxfifotrg_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_ISET_SRXFIFOTRG_AW :: INT_EVENT1_ISET_SRXFIFOTRG_SET) } } # [doc = "Slave Transmit FIFO Trigger\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT1_ISET_STXFIFOTRG_AW { # [doc = "0: NO_EFFECT"] INT_EVENT1_ISET_STXFIFOTRG_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT1_ISET_STXFIFOTRG_SET = 1 , } impl From < INT_EVENT1_ISET_STXFIFOTRG_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT1_ISET_STXFIFOTRG_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT1_ISET_STXFIFOTRG` writer - Slave Transmit FIFO Trigger"] pub type INT_EVENT1_ISET_STXFIFOTRG_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT1_ISET_STXFIFOTRG_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT1_ISET_STXFIFOTRG_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event1_iset_stxfifotrg_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_ISET_STXFIFOTRG_AW :: INT_EVENT1_ISET_STXFIFOTRG_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event1_iset_stxfifotrg_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_ISET_STXFIFOTRG_AW :: INT_EVENT1_ISET_STXFIFOTRG_SET) } } impl W { # [doc = "Bit 0 - Master Receive FIFO Trigger Trigger when RX FIFO contains &gt;= defined bytes"] # [inline (always)] # [must_use] pub fn int_event1_iset_mrxfifotrg (& mut self) -> INT_EVENT1_ISET_MRXFIFOTRG_W < INT_EVENT1_ISET_SPEC , 0 > { INT_EVENT1_ISET_MRXFIFOTRG_W :: new (self) } # [doc = "Bit 1 - Master Transmit FIFO Trigger Trigger when Transmit FIFO contains &lt;= defined bytes"] # [inline (always)] # [must_use] pub fn int_event1_iset_mtxfifotrg (& mut self) -> INT_EVENT1_ISET_MTXFIFOTRG_W < INT_EVENT1_ISET_SPEC , 1 > { INT_EVENT1_ISET_MTXFIFOTRG_W :: new (self) } # [doc = "Bit 2 - Slave Receive FIFO Trigger"] # [inline (always)] # [must_use] pub fn int_event1_iset_srxfifotrg (& mut self) -> INT_EVENT1_ISET_SRXFIFOTRG_W < INT_EVENT1_ISET_SPEC , 2 > { INT_EVENT1_ISET_SRXFIFOTRG_W :: new (self) } # [doc = "Bit 3 - Slave Transmit FIFO Trigger"] # [inline (always)] # [must_use] pub fn int_event1_iset_stxfifotrg (& mut self) -> INT_EVENT1_ISET_STXFIFOTRG_W <'_, INT_EVENT1_ISET_SPEC , 3 > { INT_EVENT1_ISET_STXFIFOTRG_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Interrupt set\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_event1_iset::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct INT_EVENT1_ISET_SPEC ; impl crate :: RegisterSpec for INT_EVENT1_ISET_SPEC { type Ux = u32 ; } # [doc = "`write(|w| ..)` method takes [`int_event1_iset::W`](W) writer structure"] impl crate :: Writable for INT_EVENT1_ISET_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets INT_EVENT1_ISET to value 0"] impl crate :: Resettable for INT_EVENT1_ISET_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/i2c0/mcr.rs:1:8978 [INFO] [stdout] | [INFO] [stdout] 1 | ...ust_use] pub fn mcr_active (& mut self) -> MCR_ACTIVE_W < MCR_SPEC , 0 > { MCR_ACTIVE_W :: new (self) } # [doc = "Bit 1 - Multimaster ... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `MCR` reader"] pub type R = crate :: R < MCR_SPEC > ; # [doc = "Register `MCR` writer"] pub type W = crate :: W < MCR_SPEC > ; # [doc = "Field `MCR_ACTIVE` reader - Device Active After this bit has been set, it should not be set again unless it has been cleared by writing a 0 or by a reset, otherwise transfer failures may occur."] pub type MCR_ACTIVE_R = crate :: BitReader < MCR_ACTIVE_A > ; # [doc = "Device Active After this bit has been set, it should not be set again unless it has been cleared by writing a 0 or by a reset, otherwise transfer failures may occur.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum MCR_ACTIVE_A { # [doc = "0: DISABLE"] MCR_ACTIVE_DISABLE = 0 , # [doc = "1: ENABLE"] MCR_ACTIVE_ENABLE = 1 , } impl From < MCR_ACTIVE_A > for bool { # [inline (always)] fn from (variant : MCR_ACTIVE_A) -> Self { variant as u8 != 0 } } impl MCR_ACTIVE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> MCR_ACTIVE_A { match self . bits { false => MCR_ACTIVE_A :: MCR_ACTIVE_DISABLE , true => MCR_ACTIVE_A :: MCR_ACTIVE_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_mcr_active_disable (& self) -> bool { * self == MCR_ACTIVE_A :: MCR_ACTIVE_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_mcr_active_enable (& self) -> bool { * self == MCR_ACTIVE_A :: MCR_ACTIVE_ENABLE } } # [doc = "Field `MCR_ACTIVE` writer - Device Active After this bit has been set, it should not be set again unless it has been cleared by writing a 0 or by a reset, otherwise transfer failures may occur."] pub type MCR_ACTIVE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , MCR_ACTIVE_A > ; impl < 'a , REG , const O : u8 > MCR_ACTIVE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn mcr_active_disable (self) -> & 'a mut crate :: W < REG > { self . variant (MCR_ACTIVE_A :: MCR_ACTIVE_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn mcr_active_enable (self) -> & 'a mut crate :: W < REG > { self . variant (MCR_ACTIVE_A :: MCR_ACTIVE_ENABLE) } } # [doc = "Field `MCR_MMST` reader - Multimaster mode. In Multimaster mode the SCL high time counts once the SCL line has been detected high. If this is not enabled the high time counts as soon as the SCL line has been set high by the I2C controller."] pub type MCR_MMST_R = crate :: BitReader < MCR_MMST_A > ; # [doc = "Multimaster mode. In Multimaster mode the SCL high time counts once the SCL line has been detected high. If this is not enabled the high time counts as soon as the SCL line has been set high by the I2C controller.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum MCR_MMST_A { # [doc = "0: DISABLE"] MCR_MMST_DISABLE = 0 , # [doc = "1: ENABLE"] MCR_MMST_ENABLE = 1 , } impl From < MCR_MMST_A > for bool { # [inline (always)] fn from (variant : MCR_MMST_A) -> Self { variant as u8 != 0 } } impl MCR_MMST_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> MCR_MMST_A { match self . bits { false => MCR_MMST_A :: MCR_MMST_DISABLE , true => MCR_MMST_A :: MCR_MMST_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_mcr_mmst_disable (& self) -> bool { * self == MCR_MMST_A :: MCR_MMST_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_mcr_mmst_enable (& self) -> bool { * self == MCR_MMST_A :: MCR_MMST_ENABLE } } # [doc = "Field `MCR_MMST` writer - Multimaster mode. In Multimaster mode the SCL high time counts once the SCL line has been detected high. If this is not enabled the high time counts as soon as the SCL line has been set high by the I2C controller."] pub type MCR_MMST_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , MCR_MMST_A > ; impl < 'a , REG , const O : u8 > MCR_MMST_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn mcr_mmst_disable (self) -> & 'a mut crate :: W < REG > { self . variant (MCR_MMST_A :: MCR_MMST_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn mcr_mmst_enable (self) -> & 'a mut crate :: W < REG > { self . variant (MCR_MMST_A :: MCR_MMST_ENABLE) } } # [doc = "Field `MCR_CLKSTRETCH` reader - Clock Stretching. This bit controls the support for clock stretching of the I2C bus."] pub type MCR_CLKSTRETCH_R = crate :: BitReader < MCR_CLKSTRETCH_A > ; # [doc = "Clock Stretching. This bit controls the support for clock stretching of the I2C bus.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum MCR_CLKSTRETCH_A { # [doc = "0: DISABLE"] MCR_CLKSTRETCH_DISABLE = 0 , # [doc = "1: ENABLE"] MCR_CLKSTRETCH_ENABLE = 1 , } impl From < MCR_CLKSTRETCH_A > for bool { # [inline (always)] fn from (variant : MCR_CLKSTRETCH_A) -> Self { variant as u8 != 0 } } impl MCR_CLKSTRETCH_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> MCR_CLKSTRETCH_A { match self . bits { false => MCR_CLKSTRETCH_A :: MCR_CLKSTRETCH_DISABLE , true => MCR_CLKSTRETCH_A :: MCR_CLKSTRETCH_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_mcr_clkstretch_disable (& self) -> bool { * self == MCR_CLKSTRETCH_A :: MCR_CLKSTRETCH_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_mcr_clkstretch_enable (& self) -> bool { * self == MCR_CLKSTRETCH_A :: MCR_CLKSTRETCH_ENABLE } } # [doc = "Field `MCR_CLKSTRETCH` writer - Clock Stretching. This bit controls the support for clock stretching of the I2C bus."] pub type MCR_CLKSTRETCH_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , MCR_CLKSTRETCH_A > ; impl < 'a , REG , const O : u8 > MCR_CLKSTRETCH_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn mcr_clkstretch_disable (self) -> & 'a mut crate :: W < REG > { self . variant (MCR_CLKSTRETCH_A :: MCR_CLKSTRETCH_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn mcr_clkstretch_enable (self) -> & 'a mut crate :: W < REG > { self . variant (MCR_CLKSTRETCH_A :: MCR_CLKSTRETCH_ENABLE) } } # [doc = "Field `MCR_LPBK` reader - I2C Loopback"] pub type MCR_LPBK_R = crate :: BitReader < MCR_LPBK_A > ; # [doc = "I2C Loopback\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum MCR_LPBK_A { # [doc = "0: DISABLE"] MCR_LPBK_DISABLE = 0 , # [doc = "1: ENABLE"] MCR_LPBK_ENABLE = 1 , } impl From < MCR_LPBK_A > for bool { # [inline (always)] fn from (variant : MCR_LPBK_A) -> Self { variant as u8 != 0 } } impl MCR_LPBK_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> MCR_LPBK_A { match self . bits { false => MCR_LPBK_A :: MCR_LPBK_DISABLE , true => MCR_LPBK_A :: MCR_LPBK_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_mcr_lpbk_disable (& self) -> bool { * self == MCR_LPBK_A :: MCR_LPBK_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_mcr_lpbk_enable (& self) -> bool { * self == MCR_LPBK_A :: MCR_LPBK_ENABLE } } # [doc = "Field `MCR_LPBK` writer - I2C Loopback"] pub type MCR_LPBK_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , MCR_LPBK_A > ; impl < 'a , REG , const O : u8 > MCR_LPBK_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn mcr_lpbk_disable (self) -> & 'a mut crate :: W < REG > { self . variant (MCR_LPBK_A :: MCR_LPBK_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn mcr_lpbk_enable (self) -> & 'a mut crate :: W < REG > { self . variant (MCR_LPBK_A :: MCR_LPBK_ENABLE) } } impl R { # [doc = "Bit 0 - Device Active After this bit has been set, it should not be set again unless it has been cleared by writing a 0 or by a reset, otherwise transfer failures may occur."] # [inline (always)] pub fn mcr_active (& self) -> MCR_ACTIVE_R { MCR_ACTIVE_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - Multimaster mode. In Multimaster mode the SCL high time counts once the SCL line has been detected high. If this is not enabled the high time counts as soon as the SCL line has been set high by the I2C controller."] # [inline (always)] pub fn mcr_mmst (& self) -> MCR_MMST_R { MCR_MMST_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - Clock Stretching. This bit controls the support for clock stretching of the I2C bus."] # [inline (always)] pub fn mcr_clkstretch (& self) -> MCR_CLKSTRETCH_R { MCR_CLKSTRETCH_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 8 - I2C Loopback"] # [inline (always)] pub fn mcr_lpbk (& self) -> MCR_LPBK_R { MCR_LPBK_R :: new (((self . bits >> 8) & 1) != 0) } } impl W { # [doc = "Bit 0 - Device Active After this bit has been set, it should not be set again unless it has been cleared by writing a 0 or by a reset, otherwise transfer failures may occur."] # [inline (always)] # [must_use] pub fn mcr_active (& mut self) -> MCR_ACTIVE_W <'_, MCR_SPEC , 0 > { MCR_ACTIVE_W :: new (self) } # [doc = "Bit 1 - Multimaster mode. In Multimaster mode the SCL high time counts once the SCL line has been detected high. If this is not enabled the high time counts as soon as the SCL line has been set high by the I2C controller."] # [inline (always)] # [must_use] pub fn mcr_mmst (& mut self) -> MCR_MMST_W < MCR_SPEC , 1 > { MCR_MMST_W :: new (self) } # [doc = "Bit 2 - Clock Stretching. This bit controls the support for clock stretching of the I2C bus."] # [inline (always)] # [must_use] pub fn mcr_clkstretch (& mut self) -> MCR_CLKSTRETCH_W < MCR_SPEC , 2 > { MCR_CLKSTRETCH_W :: new (self) } # [doc = "Bit 8 - I2C Loopback"] # [inline (always)] # [must_use] pub fn mcr_lpbk (& mut self) -> MCR_LPBK_W < MCR_SPEC , 8 > { MCR_LPBK_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "I2C Master Configuration\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mcr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mcr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct MCR_SPEC ; impl crate :: RegisterSpec for MCR_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`mcr::R`](R) reader structure"] impl crate :: Readable for MCR_SPEC { } # [doc = "`write(|w| ..)` method takes [`mcr::W`](W) writer structure"] impl crate :: Writable for MCR_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets MCR to value 0"] impl crate :: Resettable for MCR_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/opa0/rstctl.rs:1:3464 [INFO] [stdout] | [INFO] [stdout] 1 | ... rstctl_resetstkyclr (& mut self) -> RSTCTL_RESETSTKYCLR_W < RSTCTL_SPEC , 1 > { RSTCTL_RESETSTKYCLR_W :: new (self) } # [doc = "Bits ... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `RSTCTL` writer"] pub type W = crate :: W < RSTCTL_SPEC > ; # [doc = "Assert reset to the peripheral\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum RSTCTL_RESETASSERT_AW { # [doc = "0: NOP"] RSTCTL_RESETASSERT_NOP = 0 , # [doc = "1: ASSERT"] RSTCTL_RESETASSERT_ASSERT = 1 , } impl From < RSTCTL_RESETASSERT_AW > for bool { # [inline (always)] fn from (variant : RSTCTL_RESETASSERT_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `RSTCTL_RESETASSERT` writer - Assert reset to the peripheral"] pub type RSTCTL_RESETASSERT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , RSTCTL_RESETASSERT_AW > ; impl < 'a , REG , const O : u8 > RSTCTL_RESETASSERT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NOP"] # [inline (always)] pub fn rstctl_resetassert_nop (self) -> & 'a mut crate :: W < REG > { self . variant (RSTCTL_RESETASSERT_AW :: RSTCTL_RESETASSERT_NOP) } # [doc = "ASSERT"] # [inline (always)] pub fn rstctl_resetassert_assert (self) -> & 'a mut crate :: W < REG > { self . variant (RSTCTL_RESETASSERT_AW :: RSTCTL_RESETASSERT_ASSERT) } } # [doc = "Clear the RESETSTKY bit in the STAT register\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum RSTCTL_RESETSTKYCLR_AW { # [doc = "0: NOP"] RSTCTL_RESETSTKYCLR_NOP = 0 , # [doc = "1: CLR"] RSTCTL_RESETSTKYCLR_CLR = 1 , } impl From < RSTCTL_RESETSTKYCLR_AW > for bool { # [inline (always)] fn from (variant : RSTCTL_RESETSTKYCLR_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `RSTCTL_RESETSTKYCLR` writer - Clear the RESETSTKY bit in the STAT register"] pub type RSTCTL_RESETSTKYCLR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , RSTCTL_RESETSTKYCLR_AW > ; impl < 'a , REG , const O : u8 > RSTCTL_RESETSTKYCLR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NOP"] # [inline (always)] pub fn rstctl_resetstkyclr_nop (self) -> & 'a mut crate :: W < REG > { self . variant (RSTCTL_RESETSTKYCLR_AW :: RSTCTL_RESETSTKYCLR_NOP) } # [doc = "CLR"] # [inline (always)] pub fn rstctl_resetstkyclr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (RSTCTL_RESETSTKYCLR_AW :: RSTCTL_RESETSTKYCLR_CLR) } } # [doc = "Unlock key\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum RSTCTL_KEY_AW { # [doc = "177: _TO_UNLOCK_W_"] RSTCTL_KEY_UNLOCK_W = 177 , } impl From < RSTCTL_KEY_AW > for u8 { # [inline (always)] fn from (variant : RSTCTL_KEY_AW) -> Self { variant as _ } } impl crate :: FieldSpec for RSTCTL_KEY_AW { type Ux = u8 ; } # [doc = "Field `RSTCTL_KEY` writer - Unlock key"] pub type RSTCTL_KEY_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 8 , O , RSTCTL_KEY_AW > ; impl < 'a , REG , const O : u8 > RSTCTL_KEY_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "_TO_UNLOCK_W_"] # [inline (always)] pub fn rstctl_key_unlock_w (self) -> & 'a mut crate :: W < REG > { self . variant (RSTCTL_KEY_AW :: RSTCTL_KEY_UNLOCK_W) } } impl W { # [doc = "Bit 0 - Assert reset to the peripheral"] # [inline (always)] # [must_use] pub fn rstctl_resetassert (& mut self) -> RSTCTL_RESETASSERT_W < RSTCTL_SPEC , 0 > { RSTCTL_RESETASSERT_W :: new (self) } # [doc = "Bit 1 - Clear the RESETSTKY bit in the STAT register"] # [inline (always)] # [must_use] pub fn rstctl_resetstkyclr (& mut self) -> RSTCTL_RESETSTKYCLR_W <'_, RSTCTL_SPEC , 1 > { RSTCTL_RESETSTKYCLR_W :: new (self) } # [doc = "Bits 24:31 - Unlock key"] # [inline (always)] # [must_use] pub fn rstctl_key (& mut self) -> RSTCTL_KEY_W < RSTCTL_SPEC , 24 > { RSTCTL_KEY_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Reset Control\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rstctl::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct RSTCTL_SPEC ; impl crate :: RegisterSpec for RSTCTL_SPEC { type Ux = u32 ; } # [doc = "`write(|w| ..)` method takes [`rstctl::W`](W) writer structure"] impl crate :: Writable for RSTCTL_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets RSTCTL to value 0"] impl crate :: Resettable for RSTCTL_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/i2c0/sctr.rs:1:24653 [INFO] [stdout] | [INFO] [stdout] 1 | ..._use] pub fn sctr_gencall (& mut self) -> SCTR_GENCALL_W < SCTR_SPEC , 1 > { SCTR_GENCALL_W :: new (self) } # [doc = "Bit 2 - Slave Cl... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `SCTR` reader"] pub type R = crate :: R < SCTR_SPEC > ; # [doc = "Register `SCTR` writer"] pub type W = crate :: W < SCTR_SPEC > ; # [doc = "Field `SCTR_ACTIVE` reader - Device Active. Setting this bit enables the slave functionality."] pub type SCTR_ACTIVE_R = crate :: BitReader < SCTR_ACTIVE_A > ; # [doc = "Device Active. Setting this bit enables the slave functionality.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum SCTR_ACTIVE_A { # [doc = "0: DISABLE"] SCTR_ACTIVE_DISABLE = 0 , # [doc = "1: ENABLE"] SCTR_ACTIVE_ENABLE = 1 , } impl From < SCTR_ACTIVE_A > for bool { # [inline (always)] fn from (variant : SCTR_ACTIVE_A) -> Self { variant as u8 != 0 } } impl SCTR_ACTIVE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> SCTR_ACTIVE_A { match self . bits { false => SCTR_ACTIVE_A :: SCTR_ACTIVE_DISABLE , true => SCTR_ACTIVE_A :: SCTR_ACTIVE_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_sctr_active_disable (& self) -> bool { * self == SCTR_ACTIVE_A :: SCTR_ACTIVE_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_sctr_active_enable (& self) -> bool { * self == SCTR_ACTIVE_A :: SCTR_ACTIVE_ENABLE } } # [doc = "Field `SCTR_ACTIVE` writer - Device Active. Setting this bit enables the slave functionality."] pub type SCTR_ACTIVE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , SCTR_ACTIVE_A > ; impl < 'a , REG , const O : u8 > SCTR_ACTIVE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn sctr_active_disable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_ACTIVE_A :: SCTR_ACTIVE_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn sctr_active_enable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_ACTIVE_A :: SCTR_ACTIVE_ENABLE) } } # [doc = "Field `SCTR_GENCALL` reader - General call response enable. This bit is only available in UCBxI2COA0. Modify only when UCSWRST = 1. 0b = Do not respond to a general call 1b = Respond to a general call"] pub type SCTR_GENCALL_R = crate :: BitReader < SCTR_GENCALL_A > ; # [doc = "General call response enable. This bit is only available in UCBxI2COA0. Modify only when UCSWRST = 1. 0b = Do not respond to a general call 1b = Respond to a general call\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum SCTR_GENCALL_A { # [doc = "0: DISABLE"] SCTR_GENCALL_DISABLE = 0 , # [doc = "1: ENABLE"] SCTR_GENCALL_ENABLE = 1 , } impl From < SCTR_GENCALL_A > for bool { # [inline (always)] fn from (variant : SCTR_GENCALL_A) -> Self { variant as u8 != 0 } } impl SCTR_GENCALL_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> SCTR_GENCALL_A { match self . bits { false => SCTR_GENCALL_A :: SCTR_GENCALL_DISABLE , true => SCTR_GENCALL_A :: SCTR_GENCALL_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_sctr_gencall_disable (& self) -> bool { * self == SCTR_GENCALL_A :: SCTR_GENCALL_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_sctr_gencall_enable (& self) -> bool { * self == SCTR_GENCALL_A :: SCTR_GENCALL_ENABLE } } # [doc = "Field `SCTR_GENCALL` writer - General call response enable. This bit is only available in UCBxI2COA0. Modify only when UCSWRST = 1. 0b = Do not respond to a general call 1b = Respond to a general call"] pub type SCTR_GENCALL_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , SCTR_GENCALL_A > ; impl < 'a , REG , const O : u8 > SCTR_GENCALL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn sctr_gencall_disable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_GENCALL_A :: SCTR_GENCALL_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn sctr_gencall_enable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_GENCALL_A :: SCTR_GENCALL_ENABLE) } } # [doc = "Field `SCTR_SCLKSTRETCH` reader - Slave Clock Stretch Enable"] pub type SCTR_SCLKSTRETCH_R = crate :: BitReader < SCTR_SCLKSTRETCH_A > ; # [doc = "Slave Clock Stretch Enable\n\nValue on reset: 1"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum SCTR_SCLKSTRETCH_A { # [doc = "0: DISABLE"] SCTR_SCLKSTRETCH_DISABLE = 0 , # [doc = "1: ENABLE"] SCTR_SCLKSTRETCH_ENABLE = 1 , } impl From < SCTR_SCLKSTRETCH_A > for bool { # [inline (always)] fn from (variant : SCTR_SCLKSTRETCH_A) -> Self { variant as u8 != 0 } } impl SCTR_SCLKSTRETCH_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> SCTR_SCLKSTRETCH_A { match self . bits { false => SCTR_SCLKSTRETCH_A :: SCTR_SCLKSTRETCH_DISABLE , true => SCTR_SCLKSTRETCH_A :: SCTR_SCLKSTRETCH_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_sctr_sclkstretch_disable (& self) -> bool { * self == SCTR_SCLKSTRETCH_A :: SCTR_SCLKSTRETCH_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_sctr_sclkstretch_enable (& self) -> bool { * self == SCTR_SCLKSTRETCH_A :: SCTR_SCLKSTRETCH_ENABLE } } # [doc = "Field `SCTR_SCLKSTRETCH` writer - Slave Clock Stretch Enable"] pub type SCTR_SCLKSTRETCH_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , SCTR_SCLKSTRETCH_A > ; impl < 'a , REG , const O : u8 > SCTR_SCLKSTRETCH_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn sctr_sclkstretch_disable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_SCLKSTRETCH_A :: SCTR_SCLKSTRETCH_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn sctr_sclkstretch_enable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_SCLKSTRETCH_A :: SCTR_SCLKSTRETCH_ENABLE) } } # [doc = "Field `SCTR_TXEMPTY_ON_TREQ` reader - Tx Empty Interrupt on TREQ"] pub type SCTR_TXEMPTY_ON_TREQ_R = crate :: BitReader < SCTR_TXEMPTY_ON_TREQ_A > ; # [doc = "Tx Empty Interrupt on TREQ\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum SCTR_TXEMPTY_ON_TREQ_A { # [doc = "0: DISABLE"] SCTR_TXEMPTY_ON_TREQ_DISABLE = 0 , # [doc = "1: ENABLE"] SCTR_TXEMPTY_ON_TREQ_ENABLE = 1 , } impl From < SCTR_TXEMPTY_ON_TREQ_A > for bool { # [inline (always)] fn from (variant : SCTR_TXEMPTY_ON_TREQ_A) -> Self { variant as u8 != 0 } } impl SCTR_TXEMPTY_ON_TREQ_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> SCTR_TXEMPTY_ON_TREQ_A { match self . bits { false => SCTR_TXEMPTY_ON_TREQ_A :: SCTR_TXEMPTY_ON_TREQ_DISABLE , true => SCTR_TXEMPTY_ON_TREQ_A :: SCTR_TXEMPTY_ON_TREQ_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_sctr_txempty_on_treq_disable (& self) -> bool { * self == SCTR_TXEMPTY_ON_TREQ_A :: SCTR_TXEMPTY_ON_TREQ_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_sctr_txempty_on_treq_enable (& self) -> bool { * self == SCTR_TXEMPTY_ON_TREQ_A :: SCTR_TXEMPTY_ON_TREQ_ENABLE } } # [doc = "Field `SCTR_TXEMPTY_ON_TREQ` writer - Tx Empty Interrupt on TREQ"] pub type SCTR_TXEMPTY_ON_TREQ_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , SCTR_TXEMPTY_ON_TREQ_A > ; impl < 'a , REG , const O : u8 > SCTR_TXEMPTY_ON_TREQ_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn sctr_txempty_on_treq_disable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_TXEMPTY_ON_TREQ_A :: SCTR_TXEMPTY_ON_TREQ_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn sctr_txempty_on_treq_enable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_TXEMPTY_ON_TREQ_A :: SCTR_TXEMPTY_ON_TREQ_ENABLE) } } # [doc = "Field `SCTR_TXTRIG_TXMODE` reader - Tx Trigger when slave FSM is in Tx Mode"] pub type SCTR_TXTRIG_TXMODE_R = crate :: BitReader < SCTR_TXTRIG_TXMODE_A > ; # [doc = "Tx Trigger when slave FSM is in Tx Mode\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum SCTR_TXTRIG_TXMODE_A { # [doc = "0: DISABLE"] SCTR_TXTRIG_TXMODE_DISABLE = 0 , # [doc = "1: ENABLE"] SCTR_TXTRIG_TXMODE_ENABLE = 1 , } impl From < SCTR_TXTRIG_TXMODE_A > for bool { # [inline (always)] fn from (variant : SCTR_TXTRIG_TXMODE_A) -> Self { variant as u8 != 0 } } impl SCTR_TXTRIG_TXMODE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> SCTR_TXTRIG_TXMODE_A { match self . bits { false => SCTR_TXTRIG_TXMODE_A :: SCTR_TXTRIG_TXMODE_DISABLE , true => SCTR_TXTRIG_TXMODE_A :: SCTR_TXTRIG_TXMODE_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_sctr_txtrig_txmode_disable (& self) -> bool { * self == SCTR_TXTRIG_TXMODE_A :: SCTR_TXTRIG_TXMODE_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_sctr_txtrig_txmode_enable (& self) -> bool { * self == SCTR_TXTRIG_TXMODE_A :: SCTR_TXTRIG_TXMODE_ENABLE } } # [doc = "Field `SCTR_TXTRIG_TXMODE` writer - Tx Trigger when slave FSM is in Tx Mode"] pub type SCTR_TXTRIG_TXMODE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , SCTR_TXTRIG_TXMODE_A > ; impl < 'a , REG , const O : u8 > SCTR_TXTRIG_TXMODE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn sctr_txtrig_txmode_disable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_TXTRIG_TXMODE_A :: SCTR_TXTRIG_TXMODE_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn sctr_txtrig_txmode_enable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_TXTRIG_TXMODE_A :: SCTR_TXTRIG_TXMODE_ENABLE) } } # [doc = "Field `SCTR_TXWAIT_STALE_TXFIFO` reader - Tx transfer waits when stale data in Tx FIFO. This prevents stale bytes left in the TX FIFO from automatically being sent on the next I2C packet. Note: this should be used with TXEMPTY_ON_TREQ set to prevent the Slave State Machine from waiting for TX FIFO data without an interrupt notification when the FIFO data is stale."] pub type SCTR_TXWAIT_STALE_TXFIFO_R = crate :: BitReader < SCTR_TXWAIT_STALE_TXFIFO_A > ; # [doc = "Tx transfer waits when stale data in Tx FIFO. This prevents stale bytes left in the TX FIFO from automatically being sent on the next I2C packet. Note: this should be used with TXEMPTY_ON_TREQ set to prevent the Slave State Machine from waiting for TX FIFO data without an interrupt notification when the FIFO data is stale.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum SCTR_TXWAIT_STALE_TXFIFO_A { # [doc = "0: DISABLE"] SCTR_TXWAIT_STALE_TXFIFO_DISABLE = 0 , # [doc = "1: ENABLE"] SCTR_TXWAIT_STALE_TXFIFO_ENABLE = 1 , } impl From < SCTR_TXWAIT_STALE_TXFIFO_A > for bool { # [inline (always)] fn from (variant : SCTR_TXWAIT_STALE_TXFIFO_A) -> Self { variant as u8 != 0 } } impl SCTR_TXWAIT_STALE_TXFIFO_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> SCTR_TXWAIT_STALE_TXFIFO_A { match self . bits { false => SCTR_TXWAIT_STALE_TXFIFO_A :: SCTR_TXWAIT_STALE_TXFIFO_DISABLE , true => SCTR_TXWAIT_STALE_TXFIFO_A :: SCTR_TXWAIT_STALE_TXFIFO_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_sctr_txwait_stale_txfifo_disable (& self) -> bool { * self == SCTR_TXWAIT_STALE_TXFIFO_A :: SCTR_TXWAIT_STALE_TXFIFO_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_sctr_txwait_stale_txfifo_enable (& self) -> bool { * self == SCTR_TXWAIT_STALE_TXFIFO_A :: SCTR_TXWAIT_STALE_TXFIFO_ENABLE } } # [doc = "Field `SCTR_TXWAIT_STALE_TXFIFO` writer - Tx transfer waits when stale data in Tx FIFO. This prevents stale bytes left in the TX FIFO from automatically being sent on the next I2C packet. Note: this should be used with TXEMPTY_ON_TREQ set to prevent the Slave State Machine from waiting for TX FIFO data without an interrupt notification when the FIFO data is stale."] pub type SCTR_TXWAIT_STALE_TXFIFO_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , SCTR_TXWAIT_STALE_TXFIFO_A > ; impl < 'a , REG , const O : u8 > SCTR_TXWAIT_STALE_TXFIFO_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn sctr_txwait_stale_txfifo_disable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_TXWAIT_STALE_TXFIFO_A :: SCTR_TXWAIT_STALE_TXFIFO_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn sctr_txwait_stale_txfifo_enable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_TXWAIT_STALE_TXFIFO_A :: SCTR_TXWAIT_STALE_TXFIFO_ENABLE) } } # [doc = "Field `SCTR_RXFULL_ON_RREQ` reader - Rx full interrupt generated on RREQ condition as indicated in SSR"] pub type SCTR_RXFULL_ON_RREQ_R = crate :: BitReader < SCTR_RXFULL_ON_RREQ_A > ; # [doc = "Rx full interrupt generated on RREQ condition as indicated in SSR\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum SCTR_RXFULL_ON_RREQ_A { # [doc = "0: DISABLE"] SCTR_RXFULL_ON_RREQ_DISABLE = 0 , # [doc = "1: ENABLE"] SCTR_RXFULL_ON_RREQ_ENABLE = 1 , } impl From < SCTR_RXFULL_ON_RREQ_A > for bool { # [inline (always)] fn from (variant : SCTR_RXFULL_ON_RREQ_A) -> Self { variant as u8 != 0 } } impl SCTR_RXFULL_ON_RREQ_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> SCTR_RXFULL_ON_RREQ_A { match self . bits { false => SCTR_RXFULL_ON_RREQ_A :: SCTR_RXFULL_ON_RREQ_DISABLE , true => SCTR_RXFULL_ON_RREQ_A :: SCTR_RXFULL_ON_RREQ_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_sctr_rxfull_on_rreq_disable (& self) -> bool { * self == SCTR_RXFULL_ON_RREQ_A :: SCTR_RXFULL_ON_RREQ_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_sctr_rxfull_on_rreq_enable (& self) -> bool { * self == SCTR_RXFULL_ON_RREQ_A :: SCTR_RXFULL_ON_RREQ_ENABLE } } # [doc = "Field `SCTR_RXFULL_ON_RREQ` writer - Rx full interrupt generated on RREQ condition as indicated in SSR"] pub type SCTR_RXFULL_ON_RREQ_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , SCTR_RXFULL_ON_RREQ_A > ; impl < 'a , REG , const O : u8 > SCTR_RXFULL_ON_RREQ_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn sctr_rxfull_on_rreq_disable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_RXFULL_ON_RREQ_A :: SCTR_RXFULL_ON_RREQ_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn sctr_rxfull_on_rreq_enable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_RXFULL_ON_RREQ_A :: SCTR_RXFULL_ON_RREQ_ENABLE) } } # [doc = "Field `SCTR_EN_DEFHOSTADR` reader - Enable Default Host Address"] pub type SCTR_EN_DEFHOSTADR_R = crate :: BitReader < SCTR_EN_DEFHOSTADR_A > ; # [doc = "Enable Default Host Address\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum SCTR_EN_DEFHOSTADR_A { # [doc = "0: DISABLE"] SCTR_EN_DEFHOSTADR_DISABLE = 0 , # [doc = "1: ENABLE"] SCTR_EN_DEFHOSTADR_ENABLE = 1 , } impl From < SCTR_EN_DEFHOSTADR_A > for bool { # [inline (always)] fn from (variant : SCTR_EN_DEFHOSTADR_A) -> Self { variant as u8 != 0 } } impl SCTR_EN_DEFHOSTADR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> SCTR_EN_DEFHOSTADR_A { match self . bits { false => SCTR_EN_DEFHOSTADR_A :: SCTR_EN_DEFHOSTADR_DISABLE , true => SCTR_EN_DEFHOSTADR_A :: SCTR_EN_DEFHOSTADR_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_sctr_en_defhostadr_disable (& self) -> bool { * self == SCTR_EN_DEFHOSTADR_A :: SCTR_EN_DEFHOSTADR_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_sctr_en_defhostadr_enable (& self) -> bool { * self == SCTR_EN_DEFHOSTADR_A :: SCTR_EN_DEFHOSTADR_ENABLE } } # [doc = "Field `SCTR_EN_DEFHOSTADR` writer - Enable Default Host Address"] pub type SCTR_EN_DEFHOSTADR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , SCTR_EN_DEFHOSTADR_A > ; impl < 'a , REG , const O : u8 > SCTR_EN_DEFHOSTADR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn sctr_en_defhostadr_disable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_EN_DEFHOSTADR_A :: SCTR_EN_DEFHOSTADR_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn sctr_en_defhostadr_enable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_EN_DEFHOSTADR_A :: SCTR_EN_DEFHOSTADR_ENABLE) } } # [doc = "Field `SCTR_EN_ALRESPADR` reader - Enable Alert Response Address"] pub type SCTR_EN_ALRESPADR_R = crate :: BitReader < SCTR_EN_ALRESPADR_A > ; # [doc = "Enable Alert Response Address\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum SCTR_EN_ALRESPADR_A { # [doc = "0: DISABLE"] SCTR_EN_ALRESPADR_DISABLE = 0 , # [doc = "1: ENABLE"] SCTR_EN_ALRESPADR_ENABLE = 1 , } impl From < SCTR_EN_ALRESPADR_A > for bool { # [inline (always)] fn from (variant : SCTR_EN_ALRESPADR_A) -> Self { variant as u8 != 0 } } impl SCTR_EN_ALRESPADR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> SCTR_EN_ALRESPADR_A { match self . bits { false => SCTR_EN_ALRESPADR_A :: SCTR_EN_ALRESPADR_DISABLE , true => SCTR_EN_ALRESPADR_A :: SCTR_EN_ALRESPADR_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_sctr_en_alrespadr_disable (& self) -> bool { * self == SCTR_EN_ALRESPADR_A :: SCTR_EN_ALRESPADR_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_sctr_en_alrespadr_enable (& self) -> bool { * self == SCTR_EN_ALRESPADR_A :: SCTR_EN_ALRESPADR_ENABLE } } # [doc = "Field `SCTR_EN_ALRESPADR` writer - Enable Alert Response Address"] pub type SCTR_EN_ALRESPADR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , SCTR_EN_ALRESPADR_A > ; impl < 'a , REG , const O : u8 > SCTR_EN_ALRESPADR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn sctr_en_alrespadr_disable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_EN_ALRESPADR_A :: SCTR_EN_ALRESPADR_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn sctr_en_alrespadr_enable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_EN_ALRESPADR_A :: SCTR_EN_ALRESPADR_ENABLE) } } # [doc = "Field `SCTR_EN_DEFDEVADR` reader - Enable Deault device address"] pub type SCTR_EN_DEFDEVADR_R = crate :: BitReader < SCTR_EN_DEFDEVADR_A > ; # [doc = "Enable Deault device address\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum SCTR_EN_DEFDEVADR_A { # [doc = "0: DISABLE"] SCTR_EN_DEFDEVADR_DISABLE = 0 , # [doc = "1: ENABLE"] SCTR_EN_DEFDEVADR_ENABLE = 1 , } impl From < SCTR_EN_DEFDEVADR_A > for bool { # [inline (always)] fn from (variant : SCTR_EN_DEFDEVADR_A) -> Self { variant as u8 != 0 } } impl SCTR_EN_DEFDEVADR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> SCTR_EN_DEFDEVADR_A { match self . bits { false => SCTR_EN_DEFDEVADR_A :: SCTR_EN_DEFDEVADR_DISABLE , true => SCTR_EN_DEFDEVADR_A :: SCTR_EN_DEFDEVADR_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_sctr_en_defdevadr_disable (& self) -> bool { * self == SCTR_EN_DEFDEVADR_A :: SCTR_EN_DEFDEVADR_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_sctr_en_defdevadr_enable (& self) -> bool { * self == SCTR_EN_DEFDEVADR_A :: SCTR_EN_DEFDEVADR_ENABLE } } # [doc = "Field `SCTR_EN_DEFDEVADR` writer - Enable Deault device address"] pub type SCTR_EN_DEFDEVADR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , SCTR_EN_DEFDEVADR_A > ; impl < 'a , REG , const O : u8 > SCTR_EN_DEFDEVADR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn sctr_en_defdevadr_disable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_EN_DEFDEVADR_A :: SCTR_EN_DEFDEVADR_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn sctr_en_defdevadr_enable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_EN_DEFDEVADR_A :: SCTR_EN_DEFDEVADR_ENABLE) } } # [doc = "Field `SCTR_SWUEN` reader - Slave Wakeup Enable"] pub type SCTR_SWUEN_R = crate :: BitReader < SCTR_SWUEN_A > ; # [doc = "Slave Wakeup Enable\n\nValue on reset: 1"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum SCTR_SWUEN_A { # [doc = "0: DISABLE"] SCTR_SWUEN_DISABLE = 0 , # [doc = "1: ENABLE"] SCTR_SWUEN_ENABLE = 1 , } impl From < SCTR_SWUEN_A > for bool { # [inline (always)] fn from (variant : SCTR_SWUEN_A) -> Self { variant as u8 != 0 } } impl SCTR_SWUEN_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> SCTR_SWUEN_A { match self . bits { false => SCTR_SWUEN_A :: SCTR_SWUEN_DISABLE , true => SCTR_SWUEN_A :: SCTR_SWUEN_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_sctr_swuen_disable (& self) -> bool { * self == SCTR_SWUEN_A :: SCTR_SWUEN_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_sctr_swuen_enable (& self) -> bool { * self == SCTR_SWUEN_A :: SCTR_SWUEN_ENABLE } } # [doc = "Field `SCTR_SWUEN` writer - Slave Wakeup Enable"] pub type SCTR_SWUEN_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , SCTR_SWUEN_A > ; impl < 'a , REG , const O : u8 > SCTR_SWUEN_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn sctr_swuen_disable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_SWUEN_A :: SCTR_SWUEN_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn sctr_swuen_enable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_SWUEN_A :: SCTR_SWUEN_ENABLE) } } impl R { # [doc = "Bit 0 - Device Active. Setting this bit enables the slave functionality."] # [inline (always)] pub fn sctr_active (& self) -> SCTR_ACTIVE_R { SCTR_ACTIVE_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - General call response enable. This bit is only available in UCBxI2COA0. Modify only when UCSWRST = 1. 0b = Do not respond to a general call 1b = Respond to a general call"] # [inline (always)] pub fn sctr_gencall (& self) -> SCTR_GENCALL_R { SCTR_GENCALL_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - Slave Clock Stretch Enable"] # [inline (always)] pub fn sctr_sclkstretch (& self) -> SCTR_SCLKSTRETCH_R { SCTR_SCLKSTRETCH_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - Tx Empty Interrupt on TREQ"] # [inline (always)] pub fn sctr_txempty_on_treq (& self) -> SCTR_TXEMPTY_ON_TREQ_R { SCTR_TXEMPTY_ON_TREQ_R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - Tx Trigger when slave FSM is in Tx Mode"] # [inline (always)] pub fn sctr_txtrig_txmode (& self) -> SCTR_TXTRIG_TXMODE_R { SCTR_TXTRIG_TXMODE_R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - Tx transfer waits when stale data in Tx FIFO. This prevents stale bytes left in the TX FIFO from automatically being sent on the next I2C packet. Note: this should be used with TXEMPTY_ON_TREQ set to prevent the Slave State Machine from waiting for TX FIFO data without an interrupt notification when the FIFO data is stale."] # [inline (always)] pub fn sctr_txwait_stale_txfifo (& self) -> SCTR_TXWAIT_STALE_TXFIFO_R { SCTR_TXWAIT_STALE_TXFIFO_R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - Rx full interrupt generated on RREQ condition as indicated in SSR"] # [inline (always)] pub fn sctr_rxfull_on_rreq (& self) -> SCTR_RXFULL_ON_RREQ_R { SCTR_RXFULL_ON_RREQ_R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - Enable Default Host Address"] # [inline (always)] pub fn sctr_en_defhostadr (& self) -> SCTR_EN_DEFHOSTADR_R { SCTR_EN_DEFHOSTADR_R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - Enable Alert Response Address"] # [inline (always)] pub fn sctr_en_alrespadr (& self) -> SCTR_EN_ALRESPADR_R { SCTR_EN_ALRESPADR_R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - Enable Deault device address"] # [inline (always)] pub fn sctr_en_defdevadr (& self) -> SCTR_EN_DEFDEVADR_R { SCTR_EN_DEFDEVADR_R :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - Slave Wakeup Enable"] # [inline (always)] pub fn sctr_swuen (& self) -> SCTR_SWUEN_R { SCTR_SWUEN_R :: new (((self . bits >> 10) & 1) != 0) } } impl W { # [doc = "Bit 0 - Device Active. Setting this bit enables the slave functionality."] # [inline (always)] # [must_use] pub fn sctr_active (& mut self) -> SCTR_ACTIVE_W < SCTR_SPEC , 0 > { SCTR_ACTIVE_W :: new (self) } # [doc = "Bit 1 - General call response enable. This bit is only available in UCBxI2COA0. Modify only when UCSWRST = 1. 0b = Do not respond to a general call 1b = Respond to a general call"] # [inline (always)] # [must_use] pub fn sctr_gencall (& mut self) -> SCTR_GENCALL_W <'_, SCTR_SPEC , 1 > { SCTR_GENCALL_W :: new (self) } # [doc = "Bit 2 - Slave Clock Stretch Enable"] # [inline (always)] # [must_use] pub fn sctr_sclkstretch (& mut self) -> SCTR_SCLKSTRETCH_W < SCTR_SPEC , 2 > { SCTR_SCLKSTRETCH_W :: new (self) } # [doc = "Bit 3 - Tx Empty Interrupt on TREQ"] # [inline (always)] # [must_use] pub fn sctr_txempty_on_treq (& mut self) -> SCTR_TXEMPTY_ON_TREQ_W < SCTR_SPEC , 3 > { SCTR_TXEMPTY_ON_TREQ_W :: new (self) } # [doc = "Bit 4 - Tx Trigger when slave FSM is in Tx Mode"] # [inline (always)] # [must_use] pub fn sctr_txtrig_txmode (& mut self) -> SCTR_TXTRIG_TXMODE_W < SCTR_SPEC , 4 > { SCTR_TXTRIG_TXMODE_W :: new (self) } # [doc = "Bit 5 - Tx transfer waits when stale data in Tx FIFO. This prevents stale bytes left in the TX FIFO from automatically being sent on the next I2C packet. Note: this should be used with TXEMPTY_ON_TREQ set to prevent the Slave State Machine from waiting for TX FIFO data without an interrupt notification when the FIFO data is stale."] # [inline (always)] # [must_use] pub fn sctr_txwait_stale_txfifo (& mut self) -> SCTR_TXWAIT_STALE_TXFIFO_W < SCTR_SPEC , 5 > { SCTR_TXWAIT_STALE_TXFIFO_W :: new (self) } # [doc = "Bit 6 - Rx full interrupt generated on RREQ condition as indicated in SSR"] # [inline (always)] # [must_use] pub fn sctr_rxfull_on_rreq (& mut self) -> SCTR_RXFULL_ON_RREQ_W < SCTR_SPEC , 6 > { SCTR_RXFULL_ON_RREQ_W :: new (self) } # [doc = "Bit 7 - Enable Default Host Address"] # [inline (always)] # [must_use] pub fn sctr_en_defhostadr (& mut self) -> SCTR_EN_DEFHOSTADR_W < SCTR_SPEC , 7 > { SCTR_EN_DEFHOSTADR_W :: new (self) } # [doc = "Bit 8 - Enable Alert Response Address"] # [inline (always)] # [must_use] pub fn sctr_en_alrespadr (& mut self) -> SCTR_EN_ALRESPADR_W < SCTR_SPEC , 8 > { SCTR_EN_ALRESPADR_W :: new (self) } # [doc = "Bit 9 - Enable Deault device address"] # [inline (always)] # [must_use] pub fn sctr_en_defdevadr (& mut self) -> SCTR_EN_DEFDEVADR_W < SCTR_SPEC , 9 > { SCTR_EN_DEFDEVADR_W :: new (self) } # [doc = "Bit 10 - Slave Wakeup Enable"] # [inline (always)] # [must_use] pub fn sctr_swuen (& mut self) -> SCTR_SWUEN_W < SCTR_SPEC , 10 > { SCTR_SWUEN_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "I2C Slave Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sctr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sctr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct SCTR_SPEC ; impl crate :: RegisterSpec for SCTR_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`sctr::R`](R) reader structure"] impl crate :: Readable for SCTR_SPEC { } # [doc = "`write(|w| ..)` method takes [`sctr::W`](W) writer structure"] impl crate :: Writable for SCTR_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets SCTR to value 0x0404"] impl crate :: Resettable for SCTR_SPEC { const RESET_VALUE : Self :: Ux = 0x0404 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/uart0/clkdiv.rs:1:4791 [INFO] [stdout] | [INFO] [stdout] 1 | ...use] pub fn clkdiv_ratio (& mut self) -> CLKDIV_RATIO_W < CLKDIV_SPEC , 0 > { CLKDIV_RATIO_W :: new (self) } # [doc = r" Writes raw bi... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `CLKDIV` reader"] pub type R = crate :: R < CLKDIV_SPEC > ; # [doc = "Register `CLKDIV` writer"] pub type W = crate :: W < CLKDIV_SPEC > ; # [doc = "Field `CLKDIV_RATIO` reader - Selects divide ratio of module clock"] pub type CLKDIV_RATIO_R = crate :: FieldReader < CLKDIV_RATIO_A > ; # [doc = "Selects divide ratio of module clock\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum CLKDIV_RATIO_A { # [doc = "0: DIV_BY_1"] CLKDIV_RATIO_DIV_BY_1 = 0 , # [doc = "1: DIV_BY_2"] CLKDIV_RATIO_DIV_BY_2 = 1 , # [doc = "2: DIV_BY_3"] CLKDIV_RATIO_DIV_BY_3 = 2 , # [doc = "3: DIV_BY_4"] CLKDIV_RATIO_DIV_BY_4 = 3 , # [doc = "4: DIV_BY_5"] CLKDIV_RATIO_DIV_BY_5 = 4 , # [doc = "5: DIV_BY_6"] CLKDIV_RATIO_DIV_BY_6 = 5 , # [doc = "6: DIV_BY_7"] CLKDIV_RATIO_DIV_BY_7 = 6 , # [doc = "7: DIV_BY_8"] CLKDIV_RATIO_DIV_BY_8 = 7 , } impl From < CLKDIV_RATIO_A > for u8 { # [inline (always)] fn from (variant : CLKDIV_RATIO_A) -> Self { variant as _ } } impl crate :: FieldSpec for CLKDIV_RATIO_A { type Ux = u8 ; } impl CLKDIV_RATIO_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CLKDIV_RATIO_A { match self . bits { 0 => CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_1 , 1 => CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_2 , 2 => CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_3 , 3 => CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_4 , 4 => CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_5 , 5 => CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_6 , 6 => CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_7 , 7 => CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_8 , _ => unreachable ! () , } } # [doc = "DIV_BY_1"] # [inline (always)] pub fn is_clkdiv_ratio_div_by_1 (& self) -> bool { * self == CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_1 } # [doc = "DIV_BY_2"] # [inline (always)] pub fn is_clkdiv_ratio_div_by_2 (& self) -> bool { * self == CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_2 } # [doc = "DIV_BY_3"] # [inline (always)] pub fn is_clkdiv_ratio_div_by_3 (& self) -> bool { * self == CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_3 } # [doc = "DIV_BY_4"] # [inline (always)] pub fn is_clkdiv_ratio_div_by_4 (& self) -> bool { * self == CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_4 } # [doc = "DIV_BY_5"] # [inline (always)] pub fn is_clkdiv_ratio_div_by_5 (& self) -> bool { * self == CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_5 } # [doc = "DIV_BY_6"] # [inline (always)] pub fn is_clkdiv_ratio_div_by_6 (& self) -> bool { * self == CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_6 } # [doc = "DIV_BY_7"] # [inline (always)] pub fn is_clkdiv_ratio_div_by_7 (& self) -> bool { * self == CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_7 } # [doc = "DIV_BY_8"] # [inline (always)] pub fn is_clkdiv_ratio_div_by_8 (& self) -> bool { * self == CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_8 } } # [doc = "Field `CLKDIV_RATIO` writer - Selects divide ratio of module clock"] pub type CLKDIV_RATIO_W < 'a , REG , const O : u8 > = crate :: FieldWriterSafe < 'a , REG , 3 , O , CLKDIV_RATIO_A > ; impl < 'a , REG , const O : u8 > CLKDIV_RATIO_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "DIV_BY_1"] # [inline (always)] pub fn clkdiv_ratio_div_by_1 (self) -> & 'a mut crate :: W < REG > { self . variant (CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_1) } # [doc = "DIV_BY_2"] # [inline (always)] pub fn clkdiv_ratio_div_by_2 (self) -> & 'a mut crate :: W < REG > { self . variant (CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_2) } # [doc = "DIV_BY_3"] # [inline (always)] pub fn clkdiv_ratio_div_by_3 (self) -> & 'a mut crate :: W < REG > { self . variant (CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_3) } # [doc = "DIV_BY_4"] # [inline (always)] pub fn clkdiv_ratio_div_by_4 (self) -> & 'a mut crate :: W < REG > { self . variant (CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_4) } # [doc = "DIV_BY_5"] # [inline (always)] pub fn clkdiv_ratio_div_by_5 (self) -> & 'a mut crate :: W < REG > { self . variant (CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_5) } # [doc = "DIV_BY_6"] # [inline (always)] pub fn clkdiv_ratio_div_by_6 (self) -> & 'a mut crate :: W < REG > { self . variant (CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_6) } # [doc = "DIV_BY_7"] # [inline (always)] pub fn clkdiv_ratio_div_by_7 (self) -> & 'a mut crate :: W < REG > { self . variant (CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_7) } # [doc = "DIV_BY_8"] # [inline (always)] pub fn clkdiv_ratio_div_by_8 (self) -> & 'a mut crate :: W < REG > { self . variant (CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_8) } } impl R { # [doc = "Bits 0:2 - Selects divide ratio of module clock"] # [inline (always)] pub fn clkdiv_ratio (& self) -> CLKDIV_RATIO_R { CLKDIV_RATIO_R :: new ((self . bits & 7) as u8) } } impl W { # [doc = "Bits 0:2 - Selects divide ratio of module clock"] # [inline (always)] # [must_use] pub fn clkdiv_ratio (& mut self) -> CLKDIV_RATIO_W <'_, CLKDIV_SPEC , 0 > { CLKDIV_RATIO_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Clock Divider\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clkdiv::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clkdiv::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CLKDIV_SPEC ; impl crate :: RegisterSpec for CLKDIV_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`clkdiv::R`](R) reader structure"] impl crate :: Readable for CLKDIV_SPEC { } # [doc = "`write(|w| ..)` method takes [`clkdiv::W`](W) writer structure"] impl crate :: Writable for CLKDIV_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets CLKDIV to value 0"] impl crate :: Resettable for CLKDIV_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/i2c1/master_i2cpecctl.rs:1:9830 [INFO] [stdout] | [INFO] [stdout] 1 | ...pecctl_peccnt (& mut self) -> MASTER_I2CPECCTL_PECCNT_W < MASTER_I2CPECCTL_SPEC , 0 > { MASTER_I2CPECCTL_PECCNT_W :: new (self) } # [d... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `MASTER_I2CPECCTL` reader"] pub type R = crate :: R < MASTER_I2CPECCTL_SPEC > ; # [doc = "Register `MASTER_I2CPECCTL` writer"] pub type W = crate :: W < MASTER_I2CPECCTL_SPEC > ; # [doc = "Field `MASTER_I2CPECCTL_PECCNT` reader - PEC Count When this field is non zero, the number of I2C bytes are counted (Note that although the PEC is calculated on the I2C address it is not counted at a byte). When the byte count = PECCNT and the state machine is transmitting, the contents of the LSFR is loaded into the shift register instead of the byte received from the Tx FIFO. When the state machine is receiving, after the last bit of this byte is received the LSFR is checked and if it is non-zero, a PEC RX Error interrupt is generated. The I2C packet must be padded to include the PEC byte for both transmit and receive. In transmit mode the FIFO must be loaded with a dummy PEC byte. In receive mode the PEC byte will be passed to the Rx FIFO. In the normal Master use case, FW would set PECEN=1 and PECCNT=SMB packet length (Not including Slave Address byte, but including the PEC byte). FW would then configure DMA to allow the packet to complete unassisted and write MCTR to initiate the transaction. Note that when the byte count = PEC CNT, the byte count is reset to 0 and multiple PEC calculation can automatically occur within a single I2C transaction. Note that any write to the MASTER_I2CPECCTL Register will clear the current PEC Byte Count in the Master State Machine."] pub type MASTER_I2CPECCTL_PECCNT_R = crate :: FieldReader < u16 > ; # [doc = "Field `MASTER_I2CPECCTL_PECCNT` writer - PEC Count When this field is non zero, the number of I2C bytes are counted (Note that although the PEC is calculated on the I2C address it is not counted at a byte). When the byte count = PECCNT and the state machine is transmitting, the contents of the LSFR is loaded into the shift register instead of the byte received from the Tx FIFO. When the state machine is receiving, after the last bit of this byte is received the LSFR is checked and if it is non-zero, a PEC RX Error interrupt is generated. The I2C packet must be padded to include the PEC byte for both transmit and receive. In transmit mode the FIFO must be loaded with a dummy PEC byte. In receive mode the PEC byte will be passed to the Rx FIFO. In the normal Master use case, FW would set PECEN=1 and PECCNT=SMB packet length (Not including Slave Address byte, but including the PEC byte). FW would then configure DMA to allow the packet to complete unassisted and write MCTR to initiate the transaction. Note that when the byte count = PEC CNT, the byte count is reset to 0 and multiple PEC calculation can automatically occur within a single I2C transaction. Note that any write to the MASTER_I2CPECCTL Register will clear the current PEC Byte Count in the Master State Machine."] pub type MASTER_I2CPECCTL_PECCNT_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 9 , O , u16 > ; # [doc = "Field `MASTER_I2CPECCTL_PECEN` reader - PEC Enable This bit enables the SMB Packet Error Checking (PEC). When enabled the PEC is calculated on all bits accept the Start, Stop, Ack and Nack. The PEC LSFR and the Byte Counter is set to 0 when the State Machine is in the IDLE state, which occur following a Stop or when a timeout occurs. The Counter is also set to 0 after the PEC byte is sent or received. Note that the NACK is automatically send following a PEC byte that results in a PEC error. The PEC Polynomial is x^8 + x^2 + x^1 + 1."] pub type MASTER_I2CPECCTL_PECEN_R = crate :: BitReader < MASTER_I2CPECCTL_PECEN_A > ; # [doc = "PEC Enable This bit enables the SMB Packet Error Checking (PEC). When enabled the PEC is calculated on all bits accept the Start, Stop, Ack and Nack. The PEC LSFR and the Byte Counter is set to 0 when the State Machine is in the IDLE state, which occur following a Stop or when a timeout occurs. The Counter is also set to 0 after the PEC byte is sent or received. Note that the NACK is automatically send following a PEC byte that results in a PEC error. The PEC Polynomial is x^8 + x^2 + x^1 + 1.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum MASTER_I2CPECCTL_PECEN_A { # [doc = "0: DISABLE"] MASTER_I2CPECCTL_PECEN_DISABLE = 0 , # [doc = "1: ENABLE"] MASTER_I2CPECCTL_PECEN_ENABLE = 1 , } impl From < MASTER_I2CPECCTL_PECEN_A > for bool { # [inline (always)] fn from (variant : MASTER_I2CPECCTL_PECEN_A) -> Self { variant as u8 != 0 } } impl MASTER_I2CPECCTL_PECEN_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> MASTER_I2CPECCTL_PECEN_A { match self . bits { false => MASTER_I2CPECCTL_PECEN_A :: MASTER_I2CPECCTL_PECEN_DISABLE , true => MASTER_I2CPECCTL_PECEN_A :: MASTER_I2CPECCTL_PECEN_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_master_i2cpecctl_pecen_disable (& self) -> bool { * self == MASTER_I2CPECCTL_PECEN_A :: MASTER_I2CPECCTL_PECEN_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_master_i2cpecctl_pecen_enable (& self) -> bool { * self == MASTER_I2CPECCTL_PECEN_A :: MASTER_I2CPECCTL_PECEN_ENABLE } } # [doc = "Field `MASTER_I2CPECCTL_PECEN` writer - PEC Enable This bit enables the SMB Packet Error Checking (PEC). When enabled the PEC is calculated on all bits accept the Start, Stop, Ack and Nack. The PEC LSFR and the Byte Counter is set to 0 when the State Machine is in the IDLE state, which occur following a Stop or when a timeout occurs. The Counter is also set to 0 after the PEC byte is sent or received. Note that the NACK is automatically send following a PEC byte that results in a PEC error. The PEC Polynomial is x^8 + x^2 + x^1 + 1."] pub type MASTER_I2CPECCTL_PECEN_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , MASTER_I2CPECCTL_PECEN_A > ; impl < 'a , REG , const O : u8 > MASTER_I2CPECCTL_PECEN_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn master_i2cpecctl_pecen_disable (self) -> & 'a mut crate :: W < REG > { self . variant (MASTER_I2CPECCTL_PECEN_A :: MASTER_I2CPECCTL_PECEN_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn master_i2cpecctl_pecen_enable (self) -> & 'a mut crate :: W < REG > { self . variant (MASTER_I2CPECCTL_PECEN_A :: MASTER_I2CPECCTL_PECEN_ENABLE) } } impl R { # [doc = "Bits 0:8 - PEC Count When this field is non zero, the number of I2C bytes are counted (Note that although the PEC is calculated on the I2C address it is not counted at a byte). When the byte count = PECCNT and the state machine is transmitting, the contents of the LSFR is loaded into the shift register instead of the byte received from the Tx FIFO. When the state machine is receiving, after the last bit of this byte is received the LSFR is checked and if it is non-zero, a PEC RX Error interrupt is generated. The I2C packet must be padded to include the PEC byte for both transmit and receive. In transmit mode the FIFO must be loaded with a dummy PEC byte. In receive mode the PEC byte will be passed to the Rx FIFO. In the normal Master use case, FW would set PECEN=1 and PECCNT=SMB packet length (Not including Slave Address byte, but including the PEC byte). FW would then configure DMA to allow the packet to complete unassisted and write MCTR to initiate the transaction. Note that when the byte count = PEC CNT, the byte count is reset to 0 and multiple PEC calculation can automatically occur within a single I2C transaction. Note that any write to the MASTER_I2CPECCTL Register will clear the current PEC Byte Count in the Master State Machine."] # [inline (always)] pub fn master_i2cpecctl_peccnt (& self) -> MASTER_I2CPECCTL_PECCNT_R { MASTER_I2CPECCTL_PECCNT_R :: new ((self . bits & 0x01ff) as u16) } # [doc = "Bit 12 - PEC Enable This bit enables the SMB Packet Error Checking (PEC). When enabled the PEC is calculated on all bits accept the Start, Stop, Ack and Nack. The PEC LSFR and the Byte Counter is set to 0 when the State Machine is in the IDLE state, which occur following a Stop or when a timeout occurs. The Counter is also set to 0 after the PEC byte is sent or received. Note that the NACK is automatically send following a PEC byte that results in a PEC error. The PEC Polynomial is x^8 + x^2 + x^1 + 1."] # [inline (always)] pub fn master_i2cpecctl_pecen (& self) -> MASTER_I2CPECCTL_PECEN_R { MASTER_I2CPECCTL_PECEN_R :: new (((self . bits >> 12) & 1) != 0) } } impl W { # [doc = "Bits 0:8 - PEC Count When this field is non zero, the number of I2C bytes are counted (Note that although the PEC is calculated on the I2C address it is not counted at a byte). When the byte count = PECCNT and the state machine is transmitting, the contents of the LSFR is loaded into the shift register instead of the byte received from the Tx FIFO. When the state machine is receiving, after the last bit of this byte is received the LSFR is checked and if it is non-zero, a PEC RX Error interrupt is generated. The I2C packet must be padded to include the PEC byte for both transmit and receive. In transmit mode the FIFO must be loaded with a dummy PEC byte. In receive mode the PEC byte will be passed to the Rx FIFO. In the normal Master use case, FW would set PECEN=1 and PECCNT=SMB packet length (Not including Slave Address byte, but including the PEC byte). FW would then configure DMA to allow the packet to complete unassisted and write MCTR to initiate the transaction. Note that when the byte count = PEC CNT, the byte count is reset to 0 and multiple PEC calculation can automatically occur within a single I2C transaction. Note that any write to the MASTER_I2CPECCTL Register will clear the current PEC Byte Count in the Master State Machine."] # [inline (always)] # [must_use] pub fn master_i2cpecctl_peccnt (& mut self) -> MASTER_I2CPECCTL_PECCNT_W <'_, MASTER_I2CPECCTL_SPEC , 0 > { MASTER_I2CPECCTL_PECCNT_W :: new (self) } # [doc = "Bit 12 - PEC Enable This bit enables the SMB Packet Error Checking (PEC). When enabled the PEC is calculated on all bits accept the Start, Stop, Ack and Nack. The PEC LSFR and the Byte Counter is set to 0 when the State Machine is in the IDLE state, which occur following a Stop or when a timeout occurs. The Counter is also set to 0 after the PEC byte is sent or received. Note that the NACK is automatically send following a PEC byte that results in a PEC error. The PEC Polynomial is x^8 + x^2 + x^1 + 1."] # [inline (always)] # [must_use] pub fn master_i2cpecctl_pecen (& mut self) -> MASTER_I2CPECCTL_PECEN_W < MASTER_I2CPECCTL_SPEC , 12 > { MASTER_I2CPECCTL_PECEN_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "I2C master PEC control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`master_i2cpecctl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`master_i2cpecctl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct MASTER_I2CPECCTL_SPEC ; impl crate :: RegisterSpec for MASTER_I2CPECCTL_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`master_i2cpecctl::R`](R) reader structure"] impl crate :: Readable for MASTER_I2CPECCTL_SPEC { } # [doc = "`write(|w| ..)` method takes [`master_i2cpecctl::W`](W) writer structure"] impl crate :: Writable for MASTER_I2CPECCTL_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets MASTER_I2CPECCTL to value 0"] impl crate :: Resettable for MASTER_I2CPECCTL_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/timg4/ccctl_01.rs:1:35355 [INFO] [stdout] | [INFO] [stdout] 1 | ... fn ccctl_01_cc2selu (& mut self) -> CCCTL_01_CC2SELU_W < CCCTL_01_SPEC , 22 > { CCCTL_01_CC2SELU_W :: new (self) } # [doc = "Bits 26:... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `CCCTL_01[%s]` reader"] pub type R = crate :: R < CCCTL_01_SPEC > ; # [doc = "Register `CCCTL_01[%s]` writer"] pub type W = crate :: W < CCCTL_01_SPEC > ; # [doc = "Field `CCCTL_01_CCOND` reader - Capture Condition. #br# Specifies the condition that generates a capture pulse. 4h-Fh = Reserved"] pub type CCCTL_01_CCOND_R = crate :: FieldReader < CCCTL_01_CCOND_A > ; # [doc = "Capture Condition. #br# Specifies the condition that generates a capture pulse. 4h-Fh = Reserved\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum CCCTL_01_CCOND_A { # [doc = "0: NOCAPTURE"] CCCTL_01_CCOND_NOCAPTURE = 0 , # [doc = "1: CC_TRIG_RISE"] CCCTL_01_CCOND_CC_TRIG_RISE = 1 , # [doc = "2: CC_TRIG_FALL"] CCCTL_01_CCOND_CC_TRIG_FALL = 2 , # [doc = "3: CC_TRIG_EDGE"] CCCTL_01_CCOND_CC_TRIG_EDGE = 3 , } impl From < CCCTL_01_CCOND_A > for u8 { # [inline (always)] fn from (variant : CCCTL_01_CCOND_A) -> Self { variant as _ } } impl crate :: FieldSpec for CCCTL_01_CCOND_A { type Ux = u8 ; } impl CCCTL_01_CCOND_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < CCCTL_01_CCOND_A > { match self . bits { 0 => Some (CCCTL_01_CCOND_A :: CCCTL_01_CCOND_NOCAPTURE) , 1 => Some (CCCTL_01_CCOND_A :: CCCTL_01_CCOND_CC_TRIG_RISE) , 2 => Some (CCCTL_01_CCOND_A :: CCCTL_01_CCOND_CC_TRIG_FALL) , 3 => Some (CCCTL_01_CCOND_A :: CCCTL_01_CCOND_CC_TRIG_EDGE) , _ => None , } } # [doc = "NOCAPTURE"] # [inline (always)] pub fn is_ccctl_01_ccond_nocapture (& self) -> bool { * self == CCCTL_01_CCOND_A :: CCCTL_01_CCOND_NOCAPTURE } # [doc = "CC_TRIG_RISE"] # [inline (always)] pub fn is_ccctl_01_ccond_cc_trig_rise (& self) -> bool { * self == CCCTL_01_CCOND_A :: CCCTL_01_CCOND_CC_TRIG_RISE } # [doc = "CC_TRIG_FALL"] # [inline (always)] pub fn is_ccctl_01_ccond_cc_trig_fall (& self) -> bool { * self == CCCTL_01_CCOND_A :: CCCTL_01_CCOND_CC_TRIG_FALL } # [doc = "CC_TRIG_EDGE"] # [inline (always)] pub fn is_ccctl_01_ccond_cc_trig_edge (& self) -> bool { * self == CCCTL_01_CCOND_A :: CCCTL_01_CCOND_CC_TRIG_EDGE } } # [doc = "Field `CCCTL_01_CCOND` writer - Capture Condition. #br# Specifies the condition that generates a capture pulse. 4h-Fh = Reserved"] pub type CCCTL_01_CCOND_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 3 , O , CCCTL_01_CCOND_A > ; impl < 'a , REG , const O : u8 > CCCTL_01_CCOND_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "NOCAPTURE"] # [inline (always)] pub fn ccctl_01_ccond_nocapture (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CCOND_A :: CCCTL_01_CCOND_NOCAPTURE) } # [doc = "CC_TRIG_RISE"] # [inline (always)] pub fn ccctl_01_ccond_cc_trig_rise (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CCOND_A :: CCCTL_01_CCOND_CC_TRIG_RISE) } # [doc = "CC_TRIG_FALL"] # [inline (always)] pub fn ccctl_01_ccond_cc_trig_fall (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CCOND_A :: CCCTL_01_CCOND_CC_TRIG_FALL) } # [doc = "CC_TRIG_EDGE"] # [inline (always)] pub fn ccctl_01_ccond_cc_trig_edge (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CCOND_A :: CCCTL_01_CCOND_CC_TRIG_EDGE) } } # [doc = "Field `CCCTL_01_ACOND` reader - Advance Condition. #br# Specifies the condition that generates an advance pulse. 6h-Fh = Reserved"] pub type CCCTL_01_ACOND_R = crate :: FieldReader < CCCTL_01_ACOND_A > ; # [doc = "Advance Condition. #br# Specifies the condition that generates an advance pulse. 6h-Fh = Reserved\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum CCCTL_01_ACOND_A { # [doc = "0: TIMCLK"] CCCTL_01_ACOND_TIMCLK = 0 , # [doc = "1: CC_TRIG_RISE"] CCCTL_01_ACOND_CC_TRIG_RISE = 1 , # [doc = "2: CC_TRIG_FALL"] CCCTL_01_ACOND_CC_TRIG_FALL = 2 , # [doc = "3: CC_TRIG_EDGE"] CCCTL_01_ACOND_CC_TRIG_EDGE = 3 , # [doc = "5: CC_TRIG_HIGH"] CCCTL_01_ACOND_CC_TRIG_HIGH = 5 , } impl From < CCCTL_01_ACOND_A > for u8 { # [inline (always)] fn from (variant : CCCTL_01_ACOND_A) -> Self { variant as _ } } impl crate :: FieldSpec for CCCTL_01_ACOND_A { type Ux = u8 ; } impl CCCTL_01_ACOND_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < CCCTL_01_ACOND_A > { match self . bits { 0 => Some (CCCTL_01_ACOND_A :: CCCTL_01_ACOND_TIMCLK) , 1 => Some (CCCTL_01_ACOND_A :: CCCTL_01_ACOND_CC_TRIG_RISE) , 2 => Some (CCCTL_01_ACOND_A :: CCCTL_01_ACOND_CC_TRIG_FALL) , 3 => Some (CCCTL_01_ACOND_A :: CCCTL_01_ACOND_CC_TRIG_EDGE) , 5 => Some (CCCTL_01_ACOND_A :: CCCTL_01_ACOND_CC_TRIG_HIGH) , _ => None , } } # [doc = "TIMCLK"] # [inline (always)] pub fn is_ccctl_01_acond_timclk (& self) -> bool { * self == CCCTL_01_ACOND_A :: CCCTL_01_ACOND_TIMCLK } # [doc = "CC_TRIG_RISE"] # [inline (always)] pub fn is_ccctl_01_acond_cc_trig_rise (& self) -> bool { * self == CCCTL_01_ACOND_A :: CCCTL_01_ACOND_CC_TRIG_RISE } # [doc = "CC_TRIG_FALL"] # [inline (always)] pub fn is_ccctl_01_acond_cc_trig_fall (& self) -> bool { * self == CCCTL_01_ACOND_A :: CCCTL_01_ACOND_CC_TRIG_FALL } # [doc = "CC_TRIG_EDGE"] # [inline (always)] pub fn is_ccctl_01_acond_cc_trig_edge (& self) -> bool { * self == CCCTL_01_ACOND_A :: CCCTL_01_ACOND_CC_TRIG_EDGE } # [doc = "CC_TRIG_HIGH"] # [inline (always)] pub fn is_ccctl_01_acond_cc_trig_high (& self) -> bool { * self == CCCTL_01_ACOND_A :: CCCTL_01_ACOND_CC_TRIG_HIGH } } # [doc = "Field `CCCTL_01_ACOND` writer - Advance Condition. #br# Specifies the condition that generates an advance pulse. 6h-Fh = Reserved"] pub type CCCTL_01_ACOND_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 3 , O , CCCTL_01_ACOND_A > ; impl < 'a , REG , const O : u8 > CCCTL_01_ACOND_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "TIMCLK"] # [inline (always)] pub fn ccctl_01_acond_timclk (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_ACOND_A :: CCCTL_01_ACOND_TIMCLK) } # [doc = "CC_TRIG_RISE"] # [inline (always)] pub fn ccctl_01_acond_cc_trig_rise (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_ACOND_A :: CCCTL_01_ACOND_CC_TRIG_RISE) } # [doc = "CC_TRIG_FALL"] # [inline (always)] pub fn ccctl_01_acond_cc_trig_fall (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_ACOND_A :: CCCTL_01_ACOND_CC_TRIG_FALL) } # [doc = "CC_TRIG_EDGE"] # [inline (always)] pub fn ccctl_01_acond_cc_trig_edge (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_ACOND_A :: CCCTL_01_ACOND_CC_TRIG_EDGE) } # [doc = "CC_TRIG_HIGH"] # [inline (always)] pub fn ccctl_01_acond_cc_trig_high (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_ACOND_A :: CCCTL_01_ACOND_CC_TRIG_HIGH) } } # [doc = "Field `CCCTL_01_LCOND` reader - Load Condition. #br# Specifies the condition that generates a load pulse. 4h-Fh = Reserved"] pub type CCCTL_01_LCOND_R = crate :: FieldReader < CCCTL_01_LCOND_A > ; # [doc = "Load Condition. #br# Specifies the condition that generates a load pulse. 4h-Fh = Reserved\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum CCCTL_01_LCOND_A { # [doc = "1: CC_TRIG_RISE"] CCCTL_01_LCOND_CC_TRIG_RISE = 1 , # [doc = "2: CC_TRIG_FALL"] CCCTL_01_LCOND_CC_TRIG_FALL = 2 , # [doc = "3: CC_TRIG_EDGE"] CCCTL_01_LCOND_CC_TRIG_EDGE = 3 , } impl From < CCCTL_01_LCOND_A > for u8 { # [inline (always)] fn from (variant : CCCTL_01_LCOND_A) -> Self { variant as _ } } impl crate :: FieldSpec for CCCTL_01_LCOND_A { type Ux = u8 ; } impl CCCTL_01_LCOND_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < CCCTL_01_LCOND_A > { match self . bits { 1 => Some (CCCTL_01_LCOND_A :: CCCTL_01_LCOND_CC_TRIG_RISE) , 2 => Some (CCCTL_01_LCOND_A :: CCCTL_01_LCOND_CC_TRIG_FALL) , 3 => Some (CCCTL_01_LCOND_A :: CCCTL_01_LCOND_CC_TRIG_EDGE) , _ => None , } } # [doc = "CC_TRIG_RISE"] # [inline (always)] pub fn is_ccctl_01_lcond_cc_trig_rise (& self) -> bool { * self == CCCTL_01_LCOND_A :: CCCTL_01_LCOND_CC_TRIG_RISE } # [doc = "CC_TRIG_FALL"] # [inline (always)] pub fn is_ccctl_01_lcond_cc_trig_fall (& self) -> bool { * self == CCCTL_01_LCOND_A :: CCCTL_01_LCOND_CC_TRIG_FALL } # [doc = "CC_TRIG_EDGE"] # [inline (always)] pub fn is_ccctl_01_lcond_cc_trig_edge (& self) -> bool { * self == CCCTL_01_LCOND_A :: CCCTL_01_LCOND_CC_TRIG_EDGE } } # [doc = "Field `CCCTL_01_LCOND` writer - Load Condition. #br# Specifies the condition that generates a load pulse. 4h-Fh = Reserved"] pub type CCCTL_01_LCOND_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 3 , O , CCCTL_01_LCOND_A > ; impl < 'a , REG , const O : u8 > CCCTL_01_LCOND_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "CC_TRIG_RISE"] # [inline (always)] pub fn ccctl_01_lcond_cc_trig_rise (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_LCOND_A :: CCCTL_01_LCOND_CC_TRIG_RISE) } # [doc = "CC_TRIG_FALL"] # [inline (always)] pub fn ccctl_01_lcond_cc_trig_fall (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_LCOND_A :: CCCTL_01_LCOND_CC_TRIG_FALL) } # [doc = "CC_TRIG_EDGE"] # [inline (always)] pub fn ccctl_01_lcond_cc_trig_edge (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_LCOND_A :: CCCTL_01_LCOND_CC_TRIG_EDGE) } } # [doc = "Field `CCCTL_01_ZCOND` reader - Zero Condition. #br# This field specifies the condition that generates a zero pulse. 4h-Fh = Reserved"] pub type CCCTL_01_ZCOND_R = crate :: FieldReader < CCCTL_01_ZCOND_A > ; # [doc = "Zero Condition. #br# This field specifies the condition that generates a zero pulse. 4h-Fh = Reserved\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum CCCTL_01_ZCOND_A { # [doc = "1: CC_TRIG_RISE"] CCCTL_01_ZCOND_CC_TRIG_RISE = 1 , # [doc = "2: CC_TRIG_FALL"] CCCTL_01_ZCOND_CC_TRIG_FALL = 2 , # [doc = "3: CC_TRIG_EDGE"] CCCTL_01_ZCOND_CC_TRIG_EDGE = 3 , } impl From < CCCTL_01_ZCOND_A > for u8 { # [inline (always)] fn from (variant : CCCTL_01_ZCOND_A) -> Self { variant as _ } } impl crate :: FieldSpec for CCCTL_01_ZCOND_A { type Ux = u8 ; } impl CCCTL_01_ZCOND_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < CCCTL_01_ZCOND_A > { match self . bits { 1 => Some (CCCTL_01_ZCOND_A :: CCCTL_01_ZCOND_CC_TRIG_RISE) , 2 => Some (CCCTL_01_ZCOND_A :: CCCTL_01_ZCOND_CC_TRIG_FALL) , 3 => Some (CCCTL_01_ZCOND_A :: CCCTL_01_ZCOND_CC_TRIG_EDGE) , _ => None , } } # [doc = "CC_TRIG_RISE"] # [inline (always)] pub fn is_ccctl_01_zcond_cc_trig_rise (& self) -> bool { * self == CCCTL_01_ZCOND_A :: CCCTL_01_ZCOND_CC_TRIG_RISE } # [doc = "CC_TRIG_FALL"] # [inline (always)] pub fn is_ccctl_01_zcond_cc_trig_fall (& self) -> bool { * self == CCCTL_01_ZCOND_A :: CCCTL_01_ZCOND_CC_TRIG_FALL } # [doc = "CC_TRIG_EDGE"] # [inline (always)] pub fn is_ccctl_01_zcond_cc_trig_edge (& self) -> bool { * self == CCCTL_01_ZCOND_A :: CCCTL_01_ZCOND_CC_TRIG_EDGE } } # [doc = "Field `CCCTL_01_ZCOND` writer - Zero Condition. #br# This field specifies the condition that generates a zero pulse. 4h-Fh = Reserved"] pub type CCCTL_01_ZCOND_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 3 , O , CCCTL_01_ZCOND_A > ; impl < 'a , REG , const O : u8 > CCCTL_01_ZCOND_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "CC_TRIG_RISE"] # [inline (always)] pub fn ccctl_01_zcond_cc_trig_rise (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_ZCOND_A :: CCCTL_01_ZCOND_CC_TRIG_RISE) } # [doc = "CC_TRIG_FALL"] # [inline (always)] pub fn ccctl_01_zcond_cc_trig_fall (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_ZCOND_A :: CCCTL_01_ZCOND_CC_TRIG_FALL) } # [doc = "CC_TRIG_EDGE"] # [inline (always)] pub fn ccctl_01_zcond_cc_trig_edge (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_ZCOND_A :: CCCTL_01_ZCOND_CC_TRIG_EDGE) } } # [doc = "Field `CCCTL_01_COC` reader - Capture or Compare. #br# Specifies whether the corresponding CC register is used as a capture register or a compare register (never both)."] pub type CCCTL_01_COC_R = crate :: BitReader < CCCTL_01_COC_A > ; # [doc = "Capture or Compare. #br# Specifies whether the corresponding CC register is used as a capture register or a compare register (never both).\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CCCTL_01_COC_A { # [doc = "0: COMPARE"] CCCTL_01_COC_COMPARE = 0 , # [doc = "1: CAPTURE"] CCCTL_01_COC_CAPTURE = 1 , } impl From < CCCTL_01_COC_A > for bool { # [inline (always)] fn from (variant : CCCTL_01_COC_A) -> Self { variant as u8 != 0 } } impl CCCTL_01_COC_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CCCTL_01_COC_A { match self . bits { false => CCCTL_01_COC_A :: CCCTL_01_COC_COMPARE , true => CCCTL_01_COC_A :: CCCTL_01_COC_CAPTURE , } } # [doc = "COMPARE"] # [inline (always)] pub fn is_ccctl_01_coc_compare (& self) -> bool { * self == CCCTL_01_COC_A :: CCCTL_01_COC_COMPARE } # [doc = "CAPTURE"] # [inline (always)] pub fn is_ccctl_01_coc_capture (& self) -> bool { * self == CCCTL_01_COC_A :: CCCTL_01_COC_CAPTURE } } # [doc = "Field `CCCTL_01_COC` writer - Capture or Compare. #br# Specifies whether the corresponding CC register is used as a capture register or a compare register (never both)."] pub type CCCTL_01_COC_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CCCTL_01_COC_A > ; impl < 'a , REG , const O : u8 > CCCTL_01_COC_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "COMPARE"] # [inline (always)] pub fn ccctl_01_coc_compare (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_COC_A :: CCCTL_01_COC_COMPARE) } # [doc = "CAPTURE"] # [inline (always)] pub fn ccctl_01_coc_capture (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_COC_A :: CCCTL_01_COC_CAPTURE) } } # [doc = "Field `CCCTL_01_CCUPD` reader - Capture and Compare Update Method This field controls how updates to the pipelined capture and compare register are performed (when operating in compare mode, COC=0)."] pub type CCCTL_01_CCUPD_R = crate :: FieldReader < CCCTL_01_CCUPD_A > ; # [doc = "Capture and Compare Update Method This field controls how updates to the pipelined capture and compare register are performed (when operating in compare mode, COC=0).\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum CCCTL_01_CCUPD_A { # [doc = "0: IMMEDIATELY"] CCCTL_01_CCUPD_IMMEDIATELY = 0 , # [doc = "1: ZERO_EVT"] CCCTL_01_CCUPD_ZERO_EVT = 1 , # [doc = "2: COMPARE_DOWN_EVT"] CCCTL_01_CCUPD_COMPARE_DOWN_EVT = 2 , # [doc = "3: COMPARE_UP_EVT"] CCCTL_01_CCUPD_COMPARE_UP_EVT = 3 , # [doc = "4: ZERO_LOAD_EVT"] CCCTL_01_CCUPD_ZERO_LOAD_EVT = 4 , # [doc = "5: ZERO_RC_ZERO_EVT"] CCCTL_01_CCUPD_ZERO_RC_ZERO_EVT = 5 , # [doc = "6: TRIG"] CCCTL_01_CCUPD_TRIG = 6 , } impl From < CCCTL_01_CCUPD_A > for u8 { # [inline (always)] fn from (variant : CCCTL_01_CCUPD_A) -> Self { variant as _ } } impl crate :: FieldSpec for CCCTL_01_CCUPD_A { type Ux = u8 ; } impl CCCTL_01_CCUPD_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < CCCTL_01_CCUPD_A > { match self . bits { 0 => Some (CCCTL_01_CCUPD_A :: CCCTL_01_CCUPD_IMMEDIATELY) , 1 => Some (CCCTL_01_CCUPD_A :: CCCTL_01_CCUPD_ZERO_EVT) , 2 => Some (CCCTL_01_CCUPD_A :: CCCTL_01_CCUPD_COMPARE_DOWN_EVT) , 3 => Some (CCCTL_01_CCUPD_A :: CCCTL_01_CCUPD_COMPARE_UP_EVT) , 4 => Some (CCCTL_01_CCUPD_A :: CCCTL_01_CCUPD_ZERO_LOAD_EVT) , 5 => Some (CCCTL_01_CCUPD_A :: CCCTL_01_CCUPD_ZERO_RC_ZERO_EVT) , 6 => Some (CCCTL_01_CCUPD_A :: CCCTL_01_CCUPD_TRIG) , _ => None , } } # [doc = "IMMEDIATELY"] # [inline (always)] pub fn is_ccctl_01_ccupd_immediately (& self) -> bool { * self == CCCTL_01_CCUPD_A :: CCCTL_01_CCUPD_IMMEDIATELY } # [doc = "ZERO_EVT"] # [inline (always)] pub fn is_ccctl_01_ccupd_zero_evt (& self) -> bool { * self == CCCTL_01_CCUPD_A :: CCCTL_01_CCUPD_ZERO_EVT } # [doc = "COMPARE_DOWN_EVT"] # [inline (always)] pub fn is_ccctl_01_ccupd_compare_down_evt (& self) -> bool { * self == CCCTL_01_CCUPD_A :: CCCTL_01_CCUPD_COMPARE_DOWN_EVT } # [doc = "COMPARE_UP_EVT"] # [inline (always)] pub fn is_ccctl_01_ccupd_compare_up_evt (& self) -> bool { * self == CCCTL_01_CCUPD_A :: CCCTL_01_CCUPD_COMPARE_UP_EVT } # [doc = "ZERO_LOAD_EVT"] # [inline (always)] pub fn is_ccctl_01_ccupd_zero_load_evt (& self) -> bool { * self == CCCTL_01_CCUPD_A :: CCCTL_01_CCUPD_ZERO_LOAD_EVT } # [doc = "ZERO_RC_ZERO_EVT"] # [inline (always)] pub fn is_ccctl_01_ccupd_zero_rc_zero_evt (& self) -> bool { * self == CCCTL_01_CCUPD_A :: CCCTL_01_CCUPD_ZERO_RC_ZERO_EVT } # [doc = "TRIG"] # [inline (always)] pub fn is_ccctl_01_ccupd_trig (& self) -> bool { * self == CCCTL_01_CCUPD_A :: CCCTL_01_CCUPD_TRIG } } # [doc = "Field `CCCTL_01_CCUPD` writer - Capture and Compare Update Method This field controls how updates to the pipelined capture and compare register are performed (when operating in compare mode, COC=0)."] pub type CCCTL_01_CCUPD_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 3 , O , CCCTL_01_CCUPD_A > ; impl < 'a , REG , const O : u8 > CCCTL_01_CCUPD_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "IMMEDIATELY"] # [inline (always)] pub fn ccctl_01_ccupd_immediately (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CCUPD_A :: CCCTL_01_CCUPD_IMMEDIATELY) } # [doc = "ZERO_EVT"] # [inline (always)] pub fn ccctl_01_ccupd_zero_evt (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CCUPD_A :: CCCTL_01_CCUPD_ZERO_EVT) } # [doc = "COMPARE_DOWN_EVT"] # [inline (always)] pub fn ccctl_01_ccupd_compare_down_evt (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CCUPD_A :: CCCTL_01_CCUPD_COMPARE_DOWN_EVT) } # [doc = "COMPARE_UP_EVT"] # [inline (always)] pub fn ccctl_01_ccupd_compare_up_evt (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CCUPD_A :: CCCTL_01_CCUPD_COMPARE_UP_EVT) } # [doc = "ZERO_LOAD_EVT"] # [inline (always)] pub fn ccctl_01_ccupd_zero_load_evt (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CCUPD_A :: CCCTL_01_CCUPD_ZERO_LOAD_EVT) } # [doc = "ZERO_RC_ZERO_EVT"] # [inline (always)] pub fn ccctl_01_ccupd_zero_rc_zero_evt (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CCUPD_A :: CCCTL_01_CCUPD_ZERO_RC_ZERO_EVT) } # [doc = "TRIG"] # [inline (always)] pub fn ccctl_01_ccupd_trig (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CCUPD_A :: CCCTL_01_CCUPD_TRIG) } } # [doc = "Field `CCCTL_01_CC2SELU` reader - Selects the source second CCU event."] pub type CCCTL_01_CC2SELU_R = crate :: FieldReader < CCCTL_01_CC2SELU_A > ; # [doc = "Selects the source second CCU event.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum CCCTL_01_CC2SELU_A { # [doc = "0: SEL_CCU0"] CCCTL_01_CC2SELU_SEL_CCU0 = 0 , # [doc = "1: SEL_CCU1"] CCCTL_01_CC2SELU_SEL_CCU1 = 1 , # [doc = "2: SEL_CCU2"] CCCTL_01_CC2SELU_SEL_CCU2 = 2 , # [doc = "3: SEL_CCU3"] CCCTL_01_CC2SELU_SEL_CCU3 = 3 , # [doc = "4: SEL_CCU4"] CCCTL_01_CC2SELU_SEL_CCU4 = 4 , # [doc = "5: SEL_CCU5"] CCCTL_01_CC2SELU_SEL_CCU5 = 5 , } impl From < CCCTL_01_CC2SELU_A > for u8 { # [inline (always)] fn from (variant : CCCTL_01_CC2SELU_A) -> Self { variant as _ } } impl crate :: FieldSpec for CCCTL_01_CC2SELU_A { type Ux = u8 ; } impl CCCTL_01_CC2SELU_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < CCCTL_01_CC2SELU_A > { match self . bits { 0 => Some (CCCTL_01_CC2SELU_A :: CCCTL_01_CC2SELU_SEL_CCU0) , 1 => Some (CCCTL_01_CC2SELU_A :: CCCTL_01_CC2SELU_SEL_CCU1) , 2 => Some (CCCTL_01_CC2SELU_A :: CCCTL_01_CC2SELU_SEL_CCU2) , 3 => Some (CCCTL_01_CC2SELU_A :: CCCTL_01_CC2SELU_SEL_CCU3) , 4 => Some (CCCTL_01_CC2SELU_A :: CCCTL_01_CC2SELU_SEL_CCU4) , 5 => Some (CCCTL_01_CC2SELU_A :: CCCTL_01_CC2SELU_SEL_CCU5) , _ => None , } } # [doc = "SEL_CCU0"] # [inline (always)] pub fn is_ccctl_01_cc2selu_sel_ccu0 (& self) -> bool { * self == CCCTL_01_CC2SELU_A :: CCCTL_01_CC2SELU_SEL_CCU0 } # [doc = "SEL_CCU1"] # [inline (always)] pub fn is_ccctl_01_cc2selu_sel_ccu1 (& self) -> bool { * self == CCCTL_01_CC2SELU_A :: CCCTL_01_CC2SELU_SEL_CCU1 } # [doc = "SEL_CCU2"] # [inline (always)] pub fn is_ccctl_01_cc2selu_sel_ccu2 (& self) -> bool { * self == CCCTL_01_CC2SELU_A :: CCCTL_01_CC2SELU_SEL_CCU2 } # [doc = "SEL_CCU3"] # [inline (always)] pub fn is_ccctl_01_cc2selu_sel_ccu3 (& self) -> bool { * self == CCCTL_01_CC2SELU_A :: CCCTL_01_CC2SELU_SEL_CCU3 } # [doc = "SEL_CCU4"] # [inline (always)] pub fn is_ccctl_01_cc2selu_sel_ccu4 (& self) -> bool { * self == CCCTL_01_CC2SELU_A :: CCCTL_01_CC2SELU_SEL_CCU4 } # [doc = "SEL_CCU5"] # [inline (always)] pub fn is_ccctl_01_cc2selu_sel_ccu5 (& self) -> bool { * self == CCCTL_01_CC2SELU_A :: CCCTL_01_CC2SELU_SEL_CCU5 } } # [doc = "Field `CCCTL_01_CC2SELU` writer - Selects the source second CCU event."] pub type CCCTL_01_CC2SELU_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 3 , O , CCCTL_01_CC2SELU_A > ; impl < 'a , REG , const O : u8 > CCCTL_01_CC2SELU_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "SEL_CCU0"] # [inline (always)] pub fn ccctl_01_cc2selu_sel_ccu0 (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CC2SELU_A :: CCCTL_01_CC2SELU_SEL_CCU0) } # [doc = "SEL_CCU1"] # [inline (always)] pub fn ccctl_01_cc2selu_sel_ccu1 (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CC2SELU_A :: CCCTL_01_CC2SELU_SEL_CCU1) } # [doc = "SEL_CCU2"] # [inline (always)] pub fn ccctl_01_cc2selu_sel_ccu2 (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CC2SELU_A :: CCCTL_01_CC2SELU_SEL_CCU2) } # [doc = "SEL_CCU3"] # [inline (always)] pub fn ccctl_01_cc2selu_sel_ccu3 (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CC2SELU_A :: CCCTL_01_CC2SELU_SEL_CCU3) } # [doc = "SEL_CCU4"] # [inline (always)] pub fn ccctl_01_cc2selu_sel_ccu4 (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CC2SELU_A :: CCCTL_01_CC2SELU_SEL_CCU4) } # [doc = "SEL_CCU5"] # [inline (always)] pub fn ccctl_01_cc2selu_sel_ccu5 (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CC2SELU_A :: CCCTL_01_CC2SELU_SEL_CCU5) } } # [doc = "Field `CCCTL_01_CCACTUPD` reader - CCACT shadow register Update Method This field controls how updates to the CCCACT shadow register are performed"] pub type CCCTL_01_CCACTUPD_R = crate :: FieldReader < CCCTL_01_CCACTUPD_A > ; # [doc = "CCACT shadow register Update Method This field controls how updates to the CCCACT shadow register are performed\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum CCCTL_01_CCACTUPD_A { # [doc = "0: IMMEDIATELY"] CCCTL_01_CCACTUPD_IMMEDIATELY = 0 , # [doc = "1: ZERO_EVT"] CCCTL_01_CCACTUPD_ZERO_EVT = 1 , # [doc = "2: COMPARE_DOWN_EVT"] CCCTL_01_CCACTUPD_COMPARE_DOWN_EVT = 2 , # [doc = "3: COMPARE_UP_EVT"] CCCTL_01_CCACTUPD_COMPARE_UP_EVT = 3 , # [doc = "4: ZERO_LOAD_EVT"] CCCTL_01_CCACTUPD_ZERO_LOAD_EVT = 4 , # [doc = "5: ZERO_RC_ZERO_EVT"] CCCTL_01_CCACTUPD_ZERO_RC_ZERO_EVT = 5 , # [doc = "6: TRIG"] CCCTL_01_CCACTUPD_TRIG = 6 , } impl From < CCCTL_01_CCACTUPD_A > for u8 { # [inline (always)] fn from (variant : CCCTL_01_CCACTUPD_A) -> Self { variant as _ } } impl crate :: FieldSpec for CCCTL_01_CCACTUPD_A { type Ux = u8 ; } impl CCCTL_01_CCACTUPD_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < CCCTL_01_CCACTUPD_A > { match self . bits { 0 => Some (CCCTL_01_CCACTUPD_A :: CCCTL_01_CCACTUPD_IMMEDIATELY) , 1 => Some (CCCTL_01_CCACTUPD_A :: CCCTL_01_CCACTUPD_ZERO_EVT) , 2 => Some (CCCTL_01_CCACTUPD_A :: CCCTL_01_CCACTUPD_COMPARE_DOWN_EVT) , 3 => Some (CCCTL_01_CCACTUPD_A :: CCCTL_01_CCACTUPD_COMPARE_UP_EVT) , 4 => Some (CCCTL_01_CCACTUPD_A :: CCCTL_01_CCACTUPD_ZERO_LOAD_EVT) , 5 => Some (CCCTL_01_CCACTUPD_A :: CCCTL_01_CCACTUPD_ZERO_RC_ZERO_EVT) , 6 => Some (CCCTL_01_CCACTUPD_A :: CCCTL_01_CCACTUPD_TRIG) , _ => None , } } # [doc = "IMMEDIATELY"] # [inline (always)] pub fn is_ccctl_01_ccactupd_immediately (& self) -> bool { * self == CCCTL_01_CCACTUPD_A :: CCCTL_01_CCACTUPD_IMMEDIATELY } # [doc = "ZERO_EVT"] # [inline (always)] pub fn is_ccctl_01_ccactupd_zero_evt (& self) -> bool { * self == CCCTL_01_CCACTUPD_A :: CCCTL_01_CCACTUPD_ZERO_EVT } # [doc = "COMPARE_DOWN_EVT"] # [inline (always)] pub fn is_ccctl_01_ccactupd_compare_down_evt (& self) -> bool { * self == CCCTL_01_CCACTUPD_A :: CCCTL_01_CCACTUPD_COMPARE_DOWN_EVT } # [doc = "COMPARE_UP_EVT"] # [inline (always)] pub fn is_ccctl_01_ccactupd_compare_up_evt (& self) -> bool { * self == CCCTL_01_CCACTUPD_A :: CCCTL_01_CCACTUPD_COMPARE_UP_EVT } # [doc = "ZERO_LOAD_EVT"] # [inline (always)] pub fn is_ccctl_01_ccactupd_zero_load_evt (& self) -> bool { * self == CCCTL_01_CCACTUPD_A :: CCCTL_01_CCACTUPD_ZERO_LOAD_EVT } # [doc = "ZERO_RC_ZERO_EVT"] # [inline (always)] pub fn is_ccctl_01_ccactupd_zero_rc_zero_evt (& self) -> bool { * self == CCCTL_01_CCACTUPD_A :: CCCTL_01_CCACTUPD_ZERO_RC_ZERO_EVT } # [doc = "TRIG"] # [inline (always)] pub fn is_ccctl_01_ccactupd_trig (& self) -> bool { * self == CCCTL_01_CCACTUPD_A :: CCCTL_01_CCACTUPD_TRIG } } # [doc = "Field `CCCTL_01_CCACTUPD` writer - CCACT shadow register Update Method This field controls how updates to the CCCACT shadow register are performed"] pub type CCCTL_01_CCACTUPD_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 3 , O , CCCTL_01_CCACTUPD_A > ; impl < 'a , REG , const O : u8 > CCCTL_01_CCACTUPD_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "IMMEDIATELY"] # [inline (always)] pub fn ccctl_01_ccactupd_immediately (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CCACTUPD_A :: CCCTL_01_CCACTUPD_IMMEDIATELY) } # [doc = "ZERO_EVT"] # [inline (always)] pub fn ccctl_01_ccactupd_zero_evt (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CCACTUPD_A :: CCCTL_01_CCACTUPD_ZERO_EVT) } # [doc = "COMPARE_DOWN_EVT"] # [inline (always)] pub fn ccctl_01_ccactupd_compare_down_evt (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CCACTUPD_A :: CCCTL_01_CCACTUPD_COMPARE_DOWN_EVT) } # [doc = "COMPARE_UP_EVT"] # [inline (always)] pub fn ccctl_01_ccactupd_compare_up_evt (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CCACTUPD_A :: CCCTL_01_CCACTUPD_COMPARE_UP_EVT) } # [doc = "ZERO_LOAD_EVT"] # [inline (always)] pub fn ccctl_01_ccactupd_zero_load_evt (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CCACTUPD_A :: CCCTL_01_CCACTUPD_ZERO_LOAD_EVT) } # [doc = "ZERO_RC_ZERO_EVT"] # [inline (always)] pub fn ccctl_01_ccactupd_zero_rc_zero_evt (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CCACTUPD_A :: CCCTL_01_CCACTUPD_ZERO_RC_ZERO_EVT) } # [doc = "TRIG"] # [inline (always)] pub fn ccctl_01_ccactupd_trig (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CCACTUPD_A :: CCCTL_01_CCACTUPD_TRIG) } } # [doc = "Field `CCCTL_01_CC2SELD` reader - Selects the source second CCD event."] pub type CCCTL_01_CC2SELD_R = crate :: FieldReader < CCCTL_01_CC2SELD_A > ; # [doc = "Selects the source second CCD event.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum CCCTL_01_CC2SELD_A { # [doc = "0: SEL_CCD0"] CCCTL_01_CC2SELD_SEL_CCD0 = 0 , # [doc = "1: SEL_CCD1"] CCCTL_01_CC2SELD_SEL_CCD1 = 1 , # [doc = "2: SEL_CCD2"] CCCTL_01_CC2SELD_SEL_CCD2 = 2 , # [doc = "3: SEL_CCD3"] CCCTL_01_CC2SELD_SEL_CCD3 = 3 , # [doc = "4: SEL_CCD4"] CCCTL_01_CC2SELD_SEL_CCD4 = 4 , # [doc = "5: SEL_CCD5"] CCCTL_01_CC2SELD_SEL_CCD5 = 5 , } impl From < CCCTL_01_CC2SELD_A > for u8 { # [inline (always)] fn from (variant : CCCTL_01_CC2SELD_A) -> Self { variant as _ } } impl crate :: FieldSpec for CCCTL_01_CC2SELD_A { type Ux = u8 ; } impl CCCTL_01_CC2SELD_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < CCCTL_01_CC2SELD_A > { match self . bits { 0 => Some (CCCTL_01_CC2SELD_A :: CCCTL_01_CC2SELD_SEL_CCD0) , 1 => Some (CCCTL_01_CC2SELD_A :: CCCTL_01_CC2SELD_SEL_CCD1) , 2 => Some (CCCTL_01_CC2SELD_A :: CCCTL_01_CC2SELD_SEL_CCD2) , 3 => Some (CCCTL_01_CC2SELD_A :: CCCTL_01_CC2SELD_SEL_CCD3) , 4 => Some (CCCTL_01_CC2SELD_A :: CCCTL_01_CC2SELD_SEL_CCD4) , 5 => Some (CCCTL_01_CC2SELD_A :: CCCTL_01_CC2SELD_SEL_CCD5) , _ => None , } } # [doc = "SEL_CCD0"] # [inline (always)] pub fn is_ccctl_01_cc2seld_sel_ccd0 (& self) -> bool { * self == CCCTL_01_CC2SELD_A :: CCCTL_01_CC2SELD_SEL_CCD0 } # [doc = "SEL_CCD1"] # [inline (always)] pub fn is_ccctl_01_cc2seld_sel_ccd1 (& self) -> bool { * self == CCCTL_01_CC2SELD_A :: CCCTL_01_CC2SELD_SEL_CCD1 } # [doc = "SEL_CCD2"] # [inline (always)] pub fn is_ccctl_01_cc2seld_sel_ccd2 (& self) -> bool { * self == CCCTL_01_CC2SELD_A :: CCCTL_01_CC2SELD_SEL_CCD2 } # [doc = "SEL_CCD3"] # [inline (always)] pub fn is_ccctl_01_cc2seld_sel_ccd3 (& self) -> bool { * self == CCCTL_01_CC2SELD_A :: CCCTL_01_CC2SELD_SEL_CCD3 } # [doc = "SEL_CCD4"] # [inline (always)] pub fn is_ccctl_01_cc2seld_sel_ccd4 (& self) -> bool { * self == CCCTL_01_CC2SELD_A :: CCCTL_01_CC2SELD_SEL_CCD4 } # [doc = "SEL_CCD5"] # [inline (always)] pub fn is_ccctl_01_cc2seld_sel_ccd5 (& self) -> bool { * self == CCCTL_01_CC2SELD_A :: CCCTL_01_CC2SELD_SEL_CCD5 } } # [doc = "Field `CCCTL_01_CC2SELD` writer - Selects the source second CCD event."] pub type CCCTL_01_CC2SELD_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 3 , O , CCCTL_01_CC2SELD_A > ; impl < 'a , REG , const O : u8 > CCCTL_01_CC2SELD_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "SEL_CCD0"] # [inline (always)] pub fn ccctl_01_cc2seld_sel_ccd0 (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CC2SELD_A :: CCCTL_01_CC2SELD_SEL_CCD0) } # [doc = "SEL_CCD1"] # [inline (always)] pub fn ccctl_01_cc2seld_sel_ccd1 (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CC2SELD_A :: CCCTL_01_CC2SELD_SEL_CCD1) } # [doc = "SEL_CCD2"] # [inline (always)] pub fn ccctl_01_cc2seld_sel_ccd2 (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CC2SELD_A :: CCCTL_01_CC2SELD_SEL_CCD2) } # [doc = "SEL_CCD3"] # [inline (always)] pub fn ccctl_01_cc2seld_sel_ccd3 (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CC2SELD_A :: CCCTL_01_CC2SELD_SEL_CCD3) } # [doc = "SEL_CCD4"] # [inline (always)] pub fn ccctl_01_cc2seld_sel_ccd4 (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CC2SELD_A :: CCCTL_01_CC2SELD_SEL_CCD4) } # [doc = "SEL_CCD5"] # [inline (always)] pub fn ccctl_01_cc2seld_sel_ccd5 (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CC2SELD_A :: CCCTL_01_CC2SELD_SEL_CCD5) } } impl R { # [doc = "Bits 0:2 - Capture Condition. #br# Specifies the condition that generates a capture pulse. 4h-Fh = Reserved"] # [inline (always)] pub fn ccctl_01_ccond (& self) -> CCCTL_01_CCOND_R { CCCTL_01_CCOND_R :: new ((self . bits & 7) as u8) } # [doc = "Bits 4:6 - Advance Condition. #br# Specifies the condition that generates an advance pulse. 6h-Fh = Reserved"] # [inline (always)] pub fn ccctl_01_acond (& self) -> CCCTL_01_ACOND_R { CCCTL_01_ACOND_R :: new (((self . bits >> 4) & 7) as u8) } # [doc = "Bits 8:10 - Load Condition. #br# Specifies the condition that generates a load pulse. 4h-Fh = Reserved"] # [inline (always)] pub fn ccctl_01_lcond (& self) -> CCCTL_01_LCOND_R { CCCTL_01_LCOND_R :: new (((self . bits >> 8) & 7) as u8) } # [doc = "Bits 12:14 - Zero Condition. #br# This field specifies the condition that generates a zero pulse. 4h-Fh = Reserved"] # [inline (always)] pub fn ccctl_01_zcond (& self) -> CCCTL_01_ZCOND_R { CCCTL_01_ZCOND_R :: new (((self . bits >> 12) & 7) as u8) } # [doc = "Bit 17 - Capture or Compare. #br# Specifies whether the corresponding CC register is used as a capture register or a compare register (never both)."] # [inline (always)] pub fn ccctl_01_coc (& self) -> CCCTL_01_COC_R { CCCTL_01_COC_R :: new (((self . bits >> 17) & 1) != 0) } # [doc = "Bits 18:20 - Capture and Compare Update Method This field controls how updates to the pipelined capture and compare register are performed (when operating in compare mode, COC=0)."] # [inline (always)] pub fn ccctl_01_ccupd (& self) -> CCCTL_01_CCUPD_R { CCCTL_01_CCUPD_R :: new (((self . bits >> 18) & 7) as u8) } # [doc = "Bits 22:24 - Selects the source second CCU event."] # [inline (always)] pub fn ccctl_01_cc2selu (& self) -> CCCTL_01_CC2SELU_R { CCCTL_01_CC2SELU_R :: new (((self . bits >> 22) & 7) as u8) } # [doc = "Bits 26:28 - CCACT shadow register Update Method This field controls how updates to the CCCACT shadow register are performed"] # [inline (always)] pub fn ccctl_01_ccactupd (& self) -> CCCTL_01_CCACTUPD_R { CCCTL_01_CCACTUPD_R :: new (((self . bits >> 26) & 7) as u8) } # [doc = "Bits 29:31 - Selects the source second CCD event."] # [inline (always)] pub fn ccctl_01_cc2seld (& self) -> CCCTL_01_CC2SELD_R { CCCTL_01_CC2SELD_R :: new (((self . bits >> 29) & 7) as u8) } } impl W { # [doc = "Bits 0:2 - Capture Condition. #br# Specifies the condition that generates a capture pulse. 4h-Fh = Reserved"] # [inline (always)] # [must_use] pub fn ccctl_01_ccond (& mut self) -> CCCTL_01_CCOND_W < CCCTL_01_SPEC , 0 > { CCCTL_01_CCOND_W :: new (self) } # [doc = "Bits 4:6 - Advance Condition. #br# Specifies the condition that generates an advance pulse. 6h-Fh = Reserved"] # [inline (always)] # [must_use] pub fn ccctl_01_acond (& mut self) -> CCCTL_01_ACOND_W < CCCTL_01_SPEC , 4 > { CCCTL_01_ACOND_W :: new (self) } # [doc = "Bits 8:10 - Load Condition. #br# Specifies the condition that generates a load pulse. 4h-Fh = Reserved"] # [inline (always)] # [must_use] pub fn ccctl_01_lcond (& mut self) -> CCCTL_01_LCOND_W < CCCTL_01_SPEC , 8 > { CCCTL_01_LCOND_W :: new (self) } # [doc = "Bits 12:14 - Zero Condition. #br# This field specifies the condition that generates a zero pulse. 4h-Fh = Reserved"] # [inline (always)] # [must_use] pub fn ccctl_01_zcond (& mut self) -> CCCTL_01_ZCOND_W < CCCTL_01_SPEC , 12 > { CCCTL_01_ZCOND_W :: new (self) } # [doc = "Bit 17 - Capture or Compare. #br# Specifies whether the corresponding CC register is used as a capture register or a compare register (never both)."] # [inline (always)] # [must_use] pub fn ccctl_01_coc (& mut self) -> CCCTL_01_COC_W < CCCTL_01_SPEC , 17 > { CCCTL_01_COC_W :: new (self) } # [doc = "Bits 18:20 - Capture and Compare Update Method This field controls how updates to the pipelined capture and compare register are performed (when operating in compare mode, COC=0)."] # [inline (always)] # [must_use] pub fn ccctl_01_ccupd (& mut self) -> CCCTL_01_CCUPD_W < CCCTL_01_SPEC , 18 > { CCCTL_01_CCUPD_W :: new (self) } # [doc = "Bits 22:24 - Selects the source second CCU event."] # [inline (always)] # [must_use] pub fn ccctl_01_cc2selu (& mut self) -> CCCTL_01_CC2SELU_W <'_, CCCTL_01_SPEC , 22 > { CCCTL_01_CC2SELU_W :: new (self) } # [doc = "Bits 26:28 - CCACT shadow register Update Method This field controls how updates to the CCCACT shadow register are performed"] # [inline (always)] # [must_use] pub fn ccctl_01_ccactupd (& mut self) -> CCCTL_01_CCACTUPD_W < CCCTL_01_SPEC , 26 > { CCCTL_01_CCACTUPD_W :: new (self) } # [doc = "Bits 29:31 - Selects the source second CCD event."] # [inline (always)] # [must_use] pub fn ccctl_01_cc2seld (& mut self) -> CCCTL_01_CC2SELD_W < CCCTL_01_SPEC , 29 > { CCCTL_01_CC2SELD_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Capture or Compare Control Registers\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ccctl_01::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ccctl_01::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CCCTL_01_SPEC ; impl crate :: RegisterSpec for CCCTL_01_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`ccctl_01::R`](R) reader structure"] impl crate :: Readable for CCCTL_01_SPEC { } # [doc = "`write(|w| ..)` method takes [`ccctl_01::W`](W) writer structure"] impl crate :: Writable for CCCTL_01_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets CCCTL_01[%s] [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/opa1/cfg.rs:1:16972 [INFO] [stdout] | [INFO] [stdout] 1 | ... [must_use] pub fn cfg_psel (& mut self) -> CFG_PSEL_W < CFG_SPEC , 3 > { CFG_PSEL_W :: new (self) } # [doc = "Bits 7:9 - Negative OA ... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `CFG` reader"] pub type R = crate :: R < CFG_SPEC > ; # [doc = "Register `CFG` writer"] pub type W = crate :: W < CFG_SPEC > ; # [doc = "Field `CFG_CHOP` reader - Chopping enable."] pub type CFG_CHOP_R = crate :: FieldReader < CFG_CHOP_A > ; # [doc = "Chopping enable.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum CFG_CHOP_A { # [doc = "0: OFF"] CFG_CHOP_OFF = 0 , # [doc = "1: ON"] CFG_CHOP_ON = 1 , # [doc = "2: AVGON"] CFG_CHOP_AVGON = 2 , } impl From < CFG_CHOP_A > for u8 { # [inline (always)] fn from (variant : CFG_CHOP_A) -> Self { variant as _ } } impl crate :: FieldSpec for CFG_CHOP_A { type Ux = u8 ; } impl CFG_CHOP_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < CFG_CHOP_A > { match self . bits { 0 => Some (CFG_CHOP_A :: CFG_CHOP_OFF) , 1 => Some (CFG_CHOP_A :: CFG_CHOP_ON) , 2 => Some (CFG_CHOP_A :: CFG_CHOP_AVGON) , _ => None , } } # [doc = "OFF"] # [inline (always)] pub fn is_cfg_chop_off (& self) -> bool { * self == CFG_CHOP_A :: CFG_CHOP_OFF } # [doc = "ON"] # [inline (always)] pub fn is_cfg_chop_on (& self) -> bool { * self == CFG_CHOP_A :: CFG_CHOP_ON } # [doc = "AVGON"] # [inline (always)] pub fn is_cfg_chop_avgon (& self) -> bool { * self == CFG_CHOP_A :: CFG_CHOP_AVGON } } # [doc = "Field `CFG_CHOP` writer - Chopping enable."] pub type CFG_CHOP_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 2 , O , CFG_CHOP_A > ; impl < 'a , REG , const O : u8 > CFG_CHOP_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "OFF"] # [inline (always)] pub fn cfg_chop_off (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_CHOP_A :: CFG_CHOP_OFF) } # [doc = "ON"] # [inline (always)] pub fn cfg_chop_on (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_CHOP_A :: CFG_CHOP_ON) } # [doc = "AVGON"] # [inline (always)] pub fn cfg_chop_avgon (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_CHOP_A :: CFG_CHOP_AVGON) } } # [doc = "Field `CFG_OUTPIN` reader - Enable output pin"] pub type CFG_OUTPIN_R = crate :: BitReader < CFG_OUTPIN_A > ; # [doc = "Enable output pin\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CFG_OUTPIN_A { # [doc = "0: DISABLED"] CFG_OUTPIN_DISABLED = 0 , # [doc = "1: ENABLED"] CFG_OUTPIN_ENABLED = 1 , } impl From < CFG_OUTPIN_A > for bool { # [inline (always)] fn from (variant : CFG_OUTPIN_A) -> Self { variant as u8 != 0 } } impl CFG_OUTPIN_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CFG_OUTPIN_A { match self . bits { false => CFG_OUTPIN_A :: CFG_OUTPIN_DISABLED , true => CFG_OUTPIN_A :: CFG_OUTPIN_ENABLED , } } # [doc = "DISABLED"] # [inline (always)] pub fn is_cfg_outpin_disabled (& self) -> bool { * self == CFG_OUTPIN_A :: CFG_OUTPIN_DISABLED } # [doc = "ENABLED"] # [inline (always)] pub fn is_cfg_outpin_enabled (& self) -> bool { * self == CFG_OUTPIN_A :: CFG_OUTPIN_ENABLED } } # [doc = "Field `CFG_OUTPIN` writer - Enable output pin"] pub type CFG_OUTPIN_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CFG_OUTPIN_A > ; impl < 'a , REG , const O : u8 > CFG_OUTPIN_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLED"] # [inline (always)] pub fn cfg_outpin_disabled (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_OUTPIN_A :: CFG_OUTPIN_DISABLED) } # [doc = "ENABLED"] # [inline (always)] pub fn cfg_outpin_enabled (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_OUTPIN_A :: CFG_OUTPIN_ENABLED) } } # [doc = "Field `CFG_PSEL` reader - Positive OA input selection. Please refer to the device specific datasheet for exact channels available."] pub type CFG_PSEL_R = crate :: FieldReader < CFG_PSEL_A > ; # [doc = "Positive OA input selection. Please refer to the device specific datasheet for exact channels available.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum CFG_PSEL_A { # [doc = "0: NC"] CFG_PSEL_NC = 0 , # [doc = "1: EXTPIN0"] CFG_PSEL_EXTPIN0 = 1 , # [doc = "2: EXTPIN1"] CFG_PSEL_EXTPIN1 = 2 , # [doc = "3: DAC12OUT"] CFG_PSEL_DAC12OUT = 3 , # [doc = "4: DAC8OUT"] CFG_PSEL_DAC8OUT = 4 , # [doc = "5: VREF"] CFG_PSEL_VREF = 5 , # [doc = "6: OANM1RTOP"] CFG_PSEL_OANM1RTOP = 6 , # [doc = "7: GPAMP_OUT_INT"] CFG_PSEL_GPAMP_OUT_INT = 7 , # [doc = "8: VSS"] CFG_PSEL_VSS = 8 , } impl From < CFG_PSEL_A > for u8 { # [inline (always)] fn from (variant : CFG_PSEL_A) -> Self { variant as _ } } impl crate :: FieldSpec for CFG_PSEL_A { type Ux = u8 ; } impl CFG_PSEL_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < CFG_PSEL_A > { match self . bits { 0 => Some (CFG_PSEL_A :: CFG_PSEL_NC) , 1 => Some (CFG_PSEL_A :: CFG_PSEL_EXTPIN0) , 2 => Some (CFG_PSEL_A :: CFG_PSEL_EXTPIN1) , 3 => Some (CFG_PSEL_A :: CFG_PSEL_DAC12OUT) , 4 => Some (CFG_PSEL_A :: CFG_PSEL_DAC8OUT) , 5 => Some (CFG_PSEL_A :: CFG_PSEL_VREF) , 6 => Some (CFG_PSEL_A :: CFG_PSEL_OANM1RTOP) , 7 => Some (CFG_PSEL_A :: CFG_PSEL_GPAMP_OUT_INT) , 8 => Some (CFG_PSEL_A :: CFG_PSEL_VSS) , _ => None , } } # [doc = "NC"] # [inline (always)] pub fn is_cfg_psel_nc (& self) -> bool { * self == CFG_PSEL_A :: CFG_PSEL_NC } # [doc = "EXTPIN0"] # [inline (always)] pub fn is_cfg_psel_extpin0 (& self) -> bool { * self == CFG_PSEL_A :: CFG_PSEL_EXTPIN0 } # [doc = "EXTPIN1"] # [inline (always)] pub fn is_cfg_psel_extpin1 (& self) -> bool { * self == CFG_PSEL_A :: CFG_PSEL_EXTPIN1 } # [doc = "DAC12OUT"] # [inline (always)] pub fn is_cfg_psel_dac12out (& self) -> bool { * self == CFG_PSEL_A :: CFG_PSEL_DAC12OUT } # [doc = "DAC8OUT"] # [inline (always)] pub fn is_cfg_psel_dac8out (& self) -> bool { * self == CFG_PSEL_A :: CFG_PSEL_DAC8OUT } # [doc = "VREF"] # [inline (always)] pub fn is_cfg_psel_vref (& self) -> bool { * self == CFG_PSEL_A :: CFG_PSEL_VREF } # [doc = "OANM1RTOP"] # [inline (always)] pub fn is_cfg_psel_oanm1rtop (& self) -> bool { * self == CFG_PSEL_A :: CFG_PSEL_OANM1RTOP } # [doc = "GPAMP_OUT_INT"] # [inline (always)] pub fn is_cfg_psel_gpamp_out_int (& self) -> bool { * self == CFG_PSEL_A :: CFG_PSEL_GPAMP_OUT_INT } # [doc = "VSS"] # [inline (always)] pub fn is_cfg_psel_vss (& self) -> bool { * self == CFG_PSEL_A :: CFG_PSEL_VSS } } # [doc = "Field `CFG_PSEL` writer - Positive OA input selection. Please refer to the device specific datasheet for exact channels available."] pub type CFG_PSEL_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 4 , O , CFG_PSEL_A > ; impl < 'a , REG , const O : u8 > CFG_PSEL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "NC"] # [inline (always)] pub fn cfg_psel_nc (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_PSEL_A :: CFG_PSEL_NC) } # [doc = "EXTPIN0"] # [inline (always)] pub fn cfg_psel_extpin0 (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_PSEL_A :: CFG_PSEL_EXTPIN0) } # [doc = "EXTPIN1"] # [inline (always)] pub fn cfg_psel_extpin1 (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_PSEL_A :: CFG_PSEL_EXTPIN1) } # [doc = "DAC12OUT"] # [inline (always)] pub fn cfg_psel_dac12out (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_PSEL_A :: CFG_PSEL_DAC12OUT) } # [doc = "DAC8OUT"] # [inline (always)] pub fn cfg_psel_dac8out (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_PSEL_A :: CFG_PSEL_DAC8OUT) } # [doc = "VREF"] # [inline (always)] pub fn cfg_psel_vref (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_PSEL_A :: CFG_PSEL_VREF) } # [doc = "OANM1RTOP"] # [inline (always)] pub fn cfg_psel_oanm1rtop (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_PSEL_A :: CFG_PSEL_OANM1RTOP) } # [doc = "GPAMP_OUT_INT"] # [inline (always)] pub fn cfg_psel_gpamp_out_int (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_PSEL_A :: CFG_PSEL_GPAMP_OUT_INT) } # [doc = "VSS"] # [inline (always)] pub fn cfg_psel_vss (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_PSEL_A :: CFG_PSEL_VSS) } } # [doc = "Field `CFG_NSEL` reader - Negative OA input selection. Please refer to the device specific datasheet for exact channels available."] pub type CFG_NSEL_R = crate :: FieldReader < CFG_NSEL_A > ; # [doc = "Negative OA input selection. Please refer to the device specific datasheet for exact channels available.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum CFG_NSEL_A { # [doc = "0: NC"] CFG_NSEL_NC = 0 , # [doc = "1: EXTPIN0"] CFG_NSEL_EXTPIN0 = 1 , # [doc = "2: EXTPIN1"] CFG_NSEL_EXTPIN1 = 2 , # [doc = "3: OANP1RBOT"] CFG_NSEL_OANP1RBOT = 3 , # [doc = "4: OANRTAP"] CFG_NSEL_OANRTAP = 4 , # [doc = "5: OANRTOP"] CFG_NSEL_OANRTOP = 5 , # [doc = "6: SPARE"] CFG_NSEL_SPARE = 6 , } impl From < CFG_NSEL_A > for u8 { # [inline (always)] fn from (variant : CFG_NSEL_A) -> Self { variant as _ } } impl crate :: FieldSpec for CFG_NSEL_A { type Ux = u8 ; } impl CFG_NSEL_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < CFG_NSEL_A > { match self . bits { 0 => Some (CFG_NSEL_A :: CFG_NSEL_NC) , 1 => Some (CFG_NSEL_A :: CFG_NSEL_EXTPIN0) , 2 => Some (CFG_NSEL_A :: CFG_NSEL_EXTPIN1) , 3 => Some (CFG_NSEL_A :: CFG_NSEL_OANP1RBOT) , 4 => Some (CFG_NSEL_A :: CFG_NSEL_OANRTAP) , 5 => Some (CFG_NSEL_A :: CFG_NSEL_OANRTOP) , 6 => Some (CFG_NSEL_A :: CFG_NSEL_SPARE) , _ => None , } } # [doc = "NC"] # [inline (always)] pub fn is_cfg_nsel_nc (& self) -> bool { * self == CFG_NSEL_A :: CFG_NSEL_NC } # [doc = "EXTPIN0"] # [inline (always)] pub fn is_cfg_nsel_extpin0 (& self) -> bool { * self == CFG_NSEL_A :: CFG_NSEL_EXTPIN0 } # [doc = "EXTPIN1"] # [inline (always)] pub fn is_cfg_nsel_extpin1 (& self) -> bool { * self == CFG_NSEL_A :: CFG_NSEL_EXTPIN1 } # [doc = "OANP1RBOT"] # [inline (always)] pub fn is_cfg_nsel_oanp1rbot (& self) -> bool { * self == CFG_NSEL_A :: CFG_NSEL_OANP1RBOT } # [doc = "OANRTAP"] # [inline (always)] pub fn is_cfg_nsel_oanrtap (& self) -> bool { * self == CFG_NSEL_A :: CFG_NSEL_OANRTAP } # [doc = "OANRTOP"] # [inline (always)] pub fn is_cfg_nsel_oanrtop (& self) -> bool { * self == CFG_NSEL_A :: CFG_NSEL_OANRTOP } # [doc = "SPARE"] # [inline (always)] pub fn is_cfg_nsel_spare (& self) -> bool { * self == CFG_NSEL_A :: CFG_NSEL_SPARE } } # [doc = "Field `CFG_NSEL` writer - Negative OA input selection. Please refer to the device specific datasheet for exact channels available."] pub type CFG_NSEL_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 3 , O , CFG_NSEL_A > ; impl < 'a , REG , const O : u8 > CFG_NSEL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "NC"] # [inline (always)] pub fn cfg_nsel_nc (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_NSEL_A :: CFG_NSEL_NC) } # [doc = "EXTPIN0"] # [inline (always)] pub fn cfg_nsel_extpin0 (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_NSEL_A :: CFG_NSEL_EXTPIN0) } # [doc = "EXTPIN1"] # [inline (always)] pub fn cfg_nsel_extpin1 (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_NSEL_A :: CFG_NSEL_EXTPIN1) } # [doc = "OANP1RBOT"] # [inline (always)] pub fn cfg_nsel_oanp1rbot (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_NSEL_A :: CFG_NSEL_OANP1RBOT) } # [doc = "OANRTAP"] # [inline (always)] pub fn cfg_nsel_oanrtap (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_NSEL_A :: CFG_NSEL_OANRTAP) } # [doc = "OANRTOP"] # [inline (always)] pub fn cfg_nsel_oanrtop (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_NSEL_A :: CFG_NSEL_OANRTOP) } # [doc = "SPARE"] # [inline (always)] pub fn cfg_nsel_spare (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_NSEL_A :: CFG_NSEL_SPARE) } } # [doc = "Field `CFG_MSEL` reader - MSEL Mux selection. Please refer to the device specific datasheet for exact channels available."] pub type CFG_MSEL_R = crate :: FieldReader < CFG_MSEL_A > ; # [doc = "MSEL Mux selection. Please refer to the device specific datasheet for exact channels available.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum CFG_MSEL_A { # [doc = "0: NC"] CFG_MSEL_NC = 0 , # [doc = "1: EXTNPIN1"] CFG_MSEL_EXTNPIN1 = 1 , # [doc = "2: VSS"] CFG_MSEL_VSS = 2 , # [doc = "3: DAC12OUT"] CFG_MSEL_DAC12OUT = 3 , # [doc = "4: OANM1RTOP"] CFG_MSEL_OANM1RTOP = 4 , } impl From < CFG_MSEL_A > for u8 { # [inline (always)] fn from (variant : CFG_MSEL_A) -> Self { variant as _ } } impl crate :: FieldSpec for CFG_MSEL_A { type Ux = u8 ; } impl CFG_MSEL_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < CFG_MSEL_A > { match self . bits { 0 => Some (CFG_MSEL_A :: CFG_MSEL_NC) , 1 => Some (CFG_MSEL_A :: CFG_MSEL_EXTNPIN1) , 2 => Some (CFG_MSEL_A :: CFG_MSEL_VSS) , 3 => Some (CFG_MSEL_A :: CFG_MSEL_DAC12OUT) , 4 => Some (CFG_MSEL_A :: CFG_MSEL_OANM1RTOP) , _ => None , } } # [doc = "NC"] # [inline (always)] pub fn is_cfg_msel_nc (& self) -> bool { * self == CFG_MSEL_A :: CFG_MSEL_NC } # [doc = "EXTNPIN1"] # [inline (always)] pub fn is_cfg_msel_extnpin1 (& self) -> bool { * self == CFG_MSEL_A :: CFG_MSEL_EXTNPIN1 } # [doc = "VSS"] # [inline (always)] pub fn is_cfg_msel_vss (& self) -> bool { * self == CFG_MSEL_A :: CFG_MSEL_VSS } # [doc = "DAC12OUT"] # [inline (always)] pub fn is_cfg_msel_dac12out (& self) -> bool { * self == CFG_MSEL_A :: CFG_MSEL_DAC12OUT } # [doc = "OANM1RTOP"] # [inline (always)] pub fn is_cfg_msel_oanm1rtop (& self) -> bool { * self == CFG_MSEL_A :: CFG_MSEL_OANM1RTOP } } # [doc = "Field `CFG_MSEL` writer - MSEL Mux selection. Please refer to the device specific datasheet for exact channels available."] pub type CFG_MSEL_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 3 , O , CFG_MSEL_A > ; impl < 'a , REG , const O : u8 > CFG_MSEL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "NC"] # [inline (always)] pub fn cfg_msel_nc (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_MSEL_A :: CFG_MSEL_NC) } # [doc = "EXTNPIN1"] # [inline (always)] pub fn cfg_msel_extnpin1 (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_MSEL_A :: CFG_MSEL_EXTNPIN1) } # [doc = "VSS"] # [inline (always)] pub fn cfg_msel_vss (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_MSEL_A :: CFG_MSEL_VSS) } # [doc = "DAC12OUT"] # [inline (always)] pub fn cfg_msel_dac12out (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_MSEL_A :: CFG_MSEL_DAC12OUT) } # [doc = "OANM1RTOP"] # [inline (always)] pub fn cfg_msel_oanm1rtop (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_MSEL_A :: CFG_MSEL_OANM1RTOP) } } # [doc = "Field `CFG_GAIN` reader - Gain setting. Refer to TRM for enumeration information."] pub type CFG_GAIN_R = crate :: FieldReader ; # [doc = "Field `CFG_GAIN` writer - Gain setting. Refer to TRM for enumeration information."] pub type CFG_GAIN_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 3 , O > ; impl R { # [doc = "Bits 0:1 - Chopping enable."] # [inline (always)] pub fn cfg_chop (& self) -> CFG_CHOP_R { CFG_CHOP_R :: new ((self . bits & 3) as u8) } # [doc = "Bit 2 - Enable output pin"] # [inline (always)] pub fn cfg_outpin (& self) -> CFG_OUTPIN_R { CFG_OUTPIN_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bits 3:6 - Positive OA input selection. Please refer to the device specific datasheet for exact channels available."] # [inline (always)] pub fn cfg_psel (& self) -> CFG_PSEL_R { CFG_PSEL_R :: new (((self . bits >> 3) & 0x0f) as u8) } # [doc = "Bits 7:9 - Negative OA input selection. Please refer to the device specific datasheet for exact channels available."] # [inline (always)] pub fn cfg_nsel (& self) -> CFG_NSEL_R { CFG_NSEL_R :: new (((self . bits >> 7) & 7) as u8) } # [doc = "Bits 10:12 - MSEL Mux selection. Please refer to the device specific datasheet for exact channels available."] # [inline (always)] pub fn cfg_msel (& self) -> CFG_MSEL_R { CFG_MSEL_R :: new (((self . bits >> 10) & 7) as u8) } # [doc = "Bits 13:15 - Gain setting. Refer to TRM for enumeration information."] # [inline (always)] pub fn cfg_gain (& self) -> CFG_GAIN_R { CFG_GAIN_R :: new (((self . bits >> 13) & 7) as u8) } } impl W { # [doc = "Bits 0:1 - Chopping enable."] # [inline (always)] # [must_use] pub fn cfg_chop (& mut self) -> CFG_CHOP_W < CFG_SPEC , 0 > { CFG_CHOP_W :: new (self) } # [doc = "Bit 2 - Enable output pin"] # [inline (always)] # [must_use] pub fn cfg_outpin (& mut self) -> CFG_OUTPIN_W < CFG_SPEC , 2 > { CFG_OUTPIN_W :: new (self) } # [doc = "Bits 3:6 - Positive OA input selection. Please refer to the device specific datasheet for exact channels available."] # [inline (always)] # [must_use] pub fn cfg_psel (& mut self) -> CFG_PSEL_W <'_, CFG_SPEC , 3 > { CFG_PSEL_W :: new (self) } # [doc = "Bits 7:9 - Negative OA input selection. Please refer to the device specific datasheet for exact channels available."] # [inline (always)] # [must_use] pub fn cfg_nsel (& mut self) -> CFG_NSEL_W < CFG_SPEC , 7 > { CFG_NSEL_W :: new (self) } # [doc = "Bits 10:12 - MSEL Mux selection. Please refer to the device specific datasheet for exact channels available."] # [inline (always)] # [must_use] pub fn cfg_msel (& mut self) -> CFG_MSEL_W < CFG_SPEC , 10 > { CFG_MSEL_W :: new (self) } # [doc = "Bits 13:15 - Gain setting. Refer to TRM for enumeration information."] # [inline (always)] # [must_use] pub fn cfg_gain (& mut self) -> CFG_GAIN_W < CFG_SPEC , 13 > { CFG_GAIN_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Configuration Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CFG_SPEC ; impl crate :: RegisterSpec for CFG_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`cfg::R`](R) reader structure"] impl crate :: Readable for CFG_SPEC { } # [doc = "`write(|w| ..)` method takes [`cfg::W`](W) writer structure"] impl crate :: Writable for CFG_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets CFG to value 0"] impl crate :: Resettable for CFG_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/cpuss/ctl.rs:1:7562 [INFO] [stdout] | [INFO] [stdout] 1 | ...ust_use] pub fn ctl_icache (& mut self) -> CTL_ICACHE_W < CTL_SPEC , 1 > { CTL_ICACHE_W :: new (self) } # [doc = "Bit 2 - Literal cach... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `CTL` reader"] pub type R = crate :: R < CTL_SPEC > ; # [doc = "Register `CTL` writer"] pub type W = crate :: W < CTL_SPEC > ; # [doc = "Field `CTL_PREFETCH` reader - Used to enable/disable instruction prefetch to Flash."] pub type CTL_PREFETCH_R = crate :: BitReader < CTL_PREFETCH_A > ; # [doc = "Used to enable/disable instruction prefetch to Flash.\n\nValue on reset: 1"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CTL_PREFETCH_A { # [doc = "0: DISABLE"] CTL_PREFETCH_DISABLE = 0 , # [doc = "1: ENABLE"] CTL_PREFETCH_ENABLE = 1 , } impl From < CTL_PREFETCH_A > for bool { # [inline (always)] fn from (variant : CTL_PREFETCH_A) -> Self { variant as u8 != 0 } } impl CTL_PREFETCH_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CTL_PREFETCH_A { match self . bits { false => CTL_PREFETCH_A :: CTL_PREFETCH_DISABLE , true => CTL_PREFETCH_A :: CTL_PREFETCH_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_ctl_prefetch_disable (& self) -> bool { * self == CTL_PREFETCH_A :: CTL_PREFETCH_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_ctl_prefetch_enable (& self) -> bool { * self == CTL_PREFETCH_A :: CTL_PREFETCH_ENABLE } } # [doc = "Field `CTL_PREFETCH` writer - Used to enable/disable instruction prefetch to Flash."] pub type CTL_PREFETCH_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL_PREFETCH_A > ; impl < 'a , REG , const O : u8 > CTL_PREFETCH_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn ctl_prefetch_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL_PREFETCH_A :: CTL_PREFETCH_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn ctl_prefetch_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL_PREFETCH_A :: CTL_PREFETCH_ENABLE) } } # [doc = "Field `CTL_ICACHE` reader - Used to enable/disable Instruction caching on flash access."] pub type CTL_ICACHE_R = crate :: BitReader < CTL_ICACHE_A > ; # [doc = "Used to enable/disable Instruction caching on flash access.\n\nValue on reset: 1"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CTL_ICACHE_A { # [doc = "0: DISABLE"] CTL_ICACHE_DISABLE = 0 , # [doc = "1: ENABLE"] CTL_ICACHE_ENABLE = 1 , } impl From < CTL_ICACHE_A > for bool { # [inline (always)] fn from (variant : CTL_ICACHE_A) -> Self { variant as u8 != 0 } } impl CTL_ICACHE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CTL_ICACHE_A { match self . bits { false => CTL_ICACHE_A :: CTL_ICACHE_DISABLE , true => CTL_ICACHE_A :: CTL_ICACHE_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_ctl_icache_disable (& self) -> bool { * self == CTL_ICACHE_A :: CTL_ICACHE_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_ctl_icache_enable (& self) -> bool { * self == CTL_ICACHE_A :: CTL_ICACHE_ENABLE } } # [doc = "Field `CTL_ICACHE` writer - Used to enable/disable Instruction caching on flash access."] pub type CTL_ICACHE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL_ICACHE_A > ; impl < 'a , REG , const O : u8 > CTL_ICACHE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn ctl_icache_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL_ICACHE_A :: CTL_ICACHE_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn ctl_icache_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL_ICACHE_A :: CTL_ICACHE_ENABLE) } } # [doc = "Field `CTL_LITEN` reader - Literal caching and prefetch enable. This bit is a subset of ICACHE/PREFETCH bit i.e. literal caching or literal prefetching will only happen if ICACHE or PREFETCH bits have been set respectively When enabled, the cache and prefetcher structures inside CPUSS will cache and prefetch literals When disabled, the cache and prefetcher structures inside CPUSS will not cache and prefetch literals"] pub type CTL_LITEN_R = crate :: BitReader < CTL_LITEN_A > ; # [doc = "Literal caching and prefetch enable. This bit is a subset of ICACHE/PREFETCH bit i.e. literal caching or literal prefetching will only happen if ICACHE or PREFETCH bits have been set respectively When enabled, the cache and prefetcher structures inside CPUSS will cache and prefetch literals When disabled, the cache and prefetcher structures inside CPUSS will not cache and prefetch literals\n\nValue on reset: 1"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CTL_LITEN_A { # [doc = "0: DISABLE"] CTL_LITEN_DISABLE = 0 , # [doc = "1: ENABLE"] CTL_LITEN_ENABLE = 1 , } impl From < CTL_LITEN_A > for bool { # [inline (always)] fn from (variant : CTL_LITEN_A) -> Self { variant as u8 != 0 } } impl CTL_LITEN_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CTL_LITEN_A { match self . bits { false => CTL_LITEN_A :: CTL_LITEN_DISABLE , true => CTL_LITEN_A :: CTL_LITEN_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_ctl_liten_disable (& self) -> bool { * self == CTL_LITEN_A :: CTL_LITEN_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_ctl_liten_enable (& self) -> bool { * self == CTL_LITEN_A :: CTL_LITEN_ENABLE } } # [doc = "Field `CTL_LITEN` writer - Literal caching and prefetch enable. This bit is a subset of ICACHE/PREFETCH bit i.e. literal caching or literal prefetching will only happen if ICACHE or PREFETCH bits have been set respectively When enabled, the cache and prefetcher structures inside CPUSS will cache and prefetch literals When disabled, the cache and prefetcher structures inside CPUSS will not cache and prefetch literals"] pub type CTL_LITEN_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL_LITEN_A > ; impl < 'a , REG , const O : u8 > CTL_LITEN_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn ctl_liten_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL_LITEN_A :: CTL_LITEN_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn ctl_liten_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL_LITEN_A :: CTL_LITEN_ENABLE) } } impl R { # [doc = "Bit 0 - Used to enable/disable instruction prefetch to Flash."] # [inline (always)] pub fn ctl_prefetch (& self) -> CTL_PREFETCH_R { CTL_PREFETCH_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - Used to enable/disable Instruction caching on flash access."] # [inline (always)] pub fn ctl_icache (& self) -> CTL_ICACHE_R { CTL_ICACHE_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - Literal caching and prefetch enable. This bit is a subset of ICACHE/PREFETCH bit i.e. literal caching or literal prefetching will only happen if ICACHE or PREFETCH bits have been set respectively When enabled, the cache and prefetcher structures inside CPUSS will cache and prefetch literals When disabled, the cache and prefetcher structures inside CPUSS will not cache and prefetch literals"] # [inline (always)] pub fn ctl_liten (& self) -> CTL_LITEN_R { CTL_LITEN_R :: new (((self . bits >> 2) & 1) != 0) } } impl W { # [doc = "Bit 0 - Used to enable/disable instruction prefetch to Flash."] # [inline (always)] # [must_use] pub fn ctl_prefetch (& mut self) -> CTL_PREFETCH_W < CTL_SPEC , 0 > { CTL_PREFETCH_W :: new (self) } # [doc = "Bit 1 - Used to enable/disable Instruction caching on flash access."] # [inline (always)] # [must_use] pub fn ctl_icache (& mut self) -> CTL_ICACHE_W <'_, CTL_SPEC , 1 > { CTL_ICACHE_W :: new (self) } # [doc = "Bit 2 - Literal caching and prefetch enable. This bit is a subset of ICACHE/PREFETCH bit i.e. literal caching or literal prefetching will only happen if ICACHE or PREFETCH bits have been set respectively When enabled, the cache and prefetcher structures inside CPUSS will cache and prefetch literals When disabled, the cache and prefetcher structures inside CPUSS will not cache and prefetch literals"] # [inline (always)] # [must_use] pub fn ctl_liten (& mut self) -> CTL_LITEN_W < CTL_SPEC , 2 > { CTL_LITEN_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Prefetch/Cache control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CTL_SPEC ; impl crate :: RegisterSpec for CTL_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`ctl::R`](R) reader structure"] impl crate :: Readable for CTL_SPEC { } # [doc = "`write(|w| ..)` method takes [`ctl::W`](W) writer structure"] impl crate :: Writable for CTL_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets CTL to value 0x07"] impl crate :: Resettable for CTL_SPEC { const RESET_VALUE : Self :: Ux = 0x07 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/sysctl/iclr.rs:1:2270 [INFO] [stdout] | [INFO] [stdout] 1 | ...e] pub fn iclr_lfoscgood (& mut self) -> ICLR_LFOSCGOOD_W < ICLR_SPEC , 0 > { ICLR_LFOSCGOOD_W :: new (self) } # [doc = "Bit 1 - Analo... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `ICLR` writer"] pub type W = crate :: W < ICLR_SPEC > ; # [doc = "Clear the LFOSCGOOD interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum ICLR_LFOSCGOOD_AW { # [doc = "0: NO_EFFECT"] ICLR_LFOSCGOOD_NO_EFFECT = 0 , # [doc = "1: CLR"] ICLR_LFOSCGOOD_CLR = 1 , } impl From < ICLR_LFOSCGOOD_AW > for bool { # [inline (always)] fn from (variant : ICLR_LFOSCGOOD_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `ICLR_LFOSCGOOD` writer - Clear the LFOSCGOOD interrupt."] pub type ICLR_LFOSCGOOD_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , ICLR_LFOSCGOOD_AW > ; impl < 'a , REG , const O : u8 > ICLR_LFOSCGOOD_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn iclr_lfoscgood_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (ICLR_LFOSCGOOD_AW :: ICLR_LFOSCGOOD_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn iclr_lfoscgood_clr (self) -> & 'a mut crate :: W < REG > { self . variant (ICLR_LFOSCGOOD_AW :: ICLR_LFOSCGOOD_CLR) } } # [doc = "Analog Clocking Consistency Error\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum ICLR_ANACLKERR_AW { # [doc = "0: NO_EFFECT"] ICLR_ANACLKERR_NO_EFFECT = 0 , # [doc = "1: CLR"] ICLR_ANACLKERR_CLR = 1 , } impl From < ICLR_ANACLKERR_AW > for bool { # [inline (always)] fn from (variant : ICLR_ANACLKERR_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `ICLR_ANACLKERR` writer - Analog Clocking Consistency Error"] pub type ICLR_ANACLKERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , ICLR_ANACLKERR_AW > ; impl < 'a , REG , const O : u8 > ICLR_ANACLKERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn iclr_anaclkerr_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (ICLR_ANACLKERR_AW :: ICLR_ANACLKERR_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn iclr_anaclkerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (ICLR_ANACLKERR_AW :: ICLR_ANACLKERR_CLR) } } impl W { # [doc = "Bit 0 - Clear the LFOSCGOOD interrupt."] # [inline (always)] # [must_use] pub fn iclr_lfoscgood (& mut self) -> ICLR_LFOSCGOOD_W <'_, ICLR_SPEC , 0 > { ICLR_LFOSCGOOD_W :: new (self) } # [doc = "Bit 1 - Analog Clocking Consistency Error"] # [inline (always)] # [must_use] pub fn iclr_anaclkerr (& mut self) -> ICLR_ANACLKERR_W < ICLR_SPEC , 1 > { ICLR_ANACLKERR_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "SYSCTL interrupt clear\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`iclr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct ICLR_SPEC ; impl crate :: RegisterSpec for ICLR_SPEC { type Ux = u32 ; } # [doc = "`write(|w| ..)` method takes [`iclr::W`](W) writer structure"] impl crate :: Writable for ICLR_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets ICLR to value 0"] impl crate :: Resettable for ICLR_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/i2c1/int_event1_iclr.rs:1:5345 [INFO] [stdout] | [INFO] [stdout] 1 | ...r_mrxfifotrg (& mut self) -> INT_EVENT1_ICLR_MRXFIFOTRG_W < INT_EVENT1_ICLR_SPEC , 0 > { INT_EVENT1_ICLR_MRXFIFOTRG_W :: new (self) } ... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `INT_EVENT1_ICLR` writer"] pub type W = crate :: W < INT_EVENT1_ICLR_SPEC > ; # [doc = "Master Receive FIFO Trigger Trigger when RX FIFO contains &gt;= defined bytes\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT1_ICLR_MRXFIFOTRG_AW { # [doc = "0: NO_EFFECT"] INT_EVENT1_ICLR_MRXFIFOTRG_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT1_ICLR_MRXFIFOTRG_CLR = 1 , } impl From < INT_EVENT1_ICLR_MRXFIFOTRG_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT1_ICLR_MRXFIFOTRG_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT1_ICLR_MRXFIFOTRG` writer - Master Receive FIFO Trigger Trigger when RX FIFO contains &gt;= defined bytes"] pub type INT_EVENT1_ICLR_MRXFIFOTRG_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT1_ICLR_MRXFIFOTRG_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT1_ICLR_MRXFIFOTRG_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event1_iclr_mrxfifotrg_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_ICLR_MRXFIFOTRG_AW :: INT_EVENT1_ICLR_MRXFIFOTRG_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event1_iclr_mrxfifotrg_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_ICLR_MRXFIFOTRG_AW :: INT_EVENT1_ICLR_MRXFIFOTRG_CLR) } } # [doc = "Master Transmit FIFO Trigger Trigger when Transmit FIFO contains &lt;= defined bytes\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT1_ICLR_MTXFIFOTRG_AW { # [doc = "0: NO_EFFECT"] INT_EVENT1_ICLR_MTXFIFOTRG_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT1_ICLR_MTXFIFOTRG_CLR = 1 , } impl From < INT_EVENT1_ICLR_MTXFIFOTRG_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT1_ICLR_MTXFIFOTRG_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT1_ICLR_MTXFIFOTRG` writer - Master Transmit FIFO Trigger Trigger when Transmit FIFO contains &lt;= defined bytes"] pub type INT_EVENT1_ICLR_MTXFIFOTRG_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT1_ICLR_MTXFIFOTRG_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT1_ICLR_MTXFIFOTRG_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event1_iclr_mtxfifotrg_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_ICLR_MTXFIFOTRG_AW :: INT_EVENT1_ICLR_MTXFIFOTRG_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event1_iclr_mtxfifotrg_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_ICLR_MTXFIFOTRG_AW :: INT_EVENT1_ICLR_MTXFIFOTRG_CLR) } } # [doc = "Slave Receive FIFO Trigger\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT1_ICLR_SRXFIFOTRG_AW { # [doc = "0: NO_EFFECT"] INT_EVENT1_ICLR_SRXFIFOTRG_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT1_ICLR_SRXFIFOTRG_CLR = 1 , } impl From < INT_EVENT1_ICLR_SRXFIFOTRG_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT1_ICLR_SRXFIFOTRG_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT1_ICLR_SRXFIFOTRG` writer - Slave Receive FIFO Trigger"] pub type INT_EVENT1_ICLR_SRXFIFOTRG_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT1_ICLR_SRXFIFOTRG_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT1_ICLR_SRXFIFOTRG_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event1_iclr_srxfifotrg_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_ICLR_SRXFIFOTRG_AW :: INT_EVENT1_ICLR_SRXFIFOTRG_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event1_iclr_srxfifotrg_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_ICLR_SRXFIFOTRG_AW :: INT_EVENT1_ICLR_SRXFIFOTRG_CLR) } } # [doc = "Slave Transmit FIFO Trigger\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT1_ICLR_STXFIFOTRG_AW { # [doc = "0: NO_EFFECT"] INT_EVENT1_ICLR_STXFIFOTRG_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT1_ICLR_STXFIFOTRG_CLR = 1 , } impl From < INT_EVENT1_ICLR_STXFIFOTRG_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT1_ICLR_STXFIFOTRG_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT1_ICLR_STXFIFOTRG` writer - Slave Transmit FIFO Trigger"] pub type INT_EVENT1_ICLR_STXFIFOTRG_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT1_ICLR_STXFIFOTRG_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT1_ICLR_STXFIFOTRG_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event1_iclr_stxfifotrg_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_ICLR_STXFIFOTRG_AW :: INT_EVENT1_ICLR_STXFIFOTRG_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event1_iclr_stxfifotrg_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_ICLR_STXFIFOTRG_AW :: INT_EVENT1_ICLR_STXFIFOTRG_CLR) } } impl W { # [doc = "Bit 0 - Master Receive FIFO Trigger Trigger when RX FIFO contains &gt;= defined bytes"] # [inline (always)] # [must_use] pub fn int_event1_iclr_mrxfifotrg (& mut self) -> INT_EVENT1_ICLR_MRXFIFOTRG_W <'_, INT_EVENT1_ICLR_SPEC , 0 > { INT_EVENT1_ICLR_MRXFIFOTRG_W :: new (self) } # [doc = "Bit 1 - Master Transmit FIFO Trigger Trigger when Transmit FIFO contains &lt;= defined bytes"] # [inline (always)] # [must_use] pub fn int_event1_iclr_mtxfifotrg (& mut self) -> INT_EVENT1_ICLR_MTXFIFOTRG_W < INT_EVENT1_ICLR_SPEC , 1 > { INT_EVENT1_ICLR_MTXFIFOTRG_W :: new (self) } # [doc = "Bit 2 - Slave Receive FIFO Trigger"] # [inline (always)] # [must_use] pub fn int_event1_iclr_srxfifotrg (& mut self) -> INT_EVENT1_ICLR_SRXFIFOTRG_W < INT_EVENT1_ICLR_SPEC , 2 > { INT_EVENT1_ICLR_SRXFIFOTRG_W :: new (self) } # [doc = "Bit 3 - Slave Transmit FIFO Trigger"] # [inline (always)] # [must_use] pub fn int_event1_iclr_stxfifotrg (& mut self) -> INT_EVENT1_ICLR_STXFIFOTRG_W < INT_EVENT1_ICLR_SPEC , 3 > { INT_EVENT1_ICLR_STXFIFOTRG_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Interrupt clear\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_event1_iclr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct INT_EVENT1_ICLR_SPEC ; impl crate :: RegisterSpec for INT_EVENT1_ICLR_SPEC { type Ux = u32 ; } # [doc = "`write(|w| ..)` method takes [`int_event1_iclr::W`](W) writer structure"] impl crate :: Writable for INT_EVENT1_ICLR_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets INT_EVENT1_ICLR to value 0"] impl crate :: Resettable for INT_EVENT1_ICLR_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/i2c1/mctr.rs:1:12619 [INFO] [stdout] | [INFO] [stdout] 1 | ...must_use] pub fn mctr_stop (& mut self) -> MCTR_STOP_W < MCTR_SPEC , 2 > { MCTR_STOP_W :: new (self) } # [doc = "Bit 3 - Data Acknowle... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `MCTR` reader"] pub type R = crate :: R < MCTR_SPEC > ; # [doc = "Register `MCTR` writer"] pub type W = crate :: W < MCTR_SPEC > ; # [doc = "Field `MCTR_BURSTRUN` reader - I2C Master Enable and start transaction"] pub type MCTR_BURSTRUN_R = crate :: BitReader < MCTR_BURSTRUN_A > ; # [doc = "I2C Master Enable and start transaction\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum MCTR_BURSTRUN_A { # [doc = "0: DISABLE"] MCTR_BURSTRUN_DISABLE = 0 , # [doc = "1: ENABLE"] MCTR_BURSTRUN_ENABLE = 1 , } impl From < MCTR_BURSTRUN_A > for bool { # [inline (always)] fn from (variant : MCTR_BURSTRUN_A) -> Self { variant as u8 != 0 } } impl MCTR_BURSTRUN_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> MCTR_BURSTRUN_A { match self . bits { false => MCTR_BURSTRUN_A :: MCTR_BURSTRUN_DISABLE , true => MCTR_BURSTRUN_A :: MCTR_BURSTRUN_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_mctr_burstrun_disable (& self) -> bool { * self == MCTR_BURSTRUN_A :: MCTR_BURSTRUN_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_mctr_burstrun_enable (& self) -> bool { * self == MCTR_BURSTRUN_A :: MCTR_BURSTRUN_ENABLE } } # [doc = "Field `MCTR_BURSTRUN` writer - I2C Master Enable and start transaction"] pub type MCTR_BURSTRUN_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , MCTR_BURSTRUN_A > ; impl < 'a , REG , const O : u8 > MCTR_BURSTRUN_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn mctr_burstrun_disable (self) -> & 'a mut crate :: W < REG > { self . variant (MCTR_BURSTRUN_A :: MCTR_BURSTRUN_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn mctr_burstrun_enable (self) -> & 'a mut crate :: W < REG > { self . variant (MCTR_BURSTRUN_A :: MCTR_BURSTRUN_ENABLE) } } # [doc = "Field `MCTR_START` reader - Generate START"] pub type MCTR_START_R = crate :: BitReader < MCTR_START_A > ; # [doc = "Generate START\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum MCTR_START_A { # [doc = "0: DISABLE"] MCTR_START_DISABLE = 0 , # [doc = "1: ENABLE"] MCTR_START_ENABLE = 1 , } impl From < MCTR_START_A > for bool { # [inline (always)] fn from (variant : MCTR_START_A) -> Self { variant as u8 != 0 } } impl MCTR_START_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> MCTR_START_A { match self . bits { false => MCTR_START_A :: MCTR_START_DISABLE , true => MCTR_START_A :: MCTR_START_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_mctr_start_disable (& self) -> bool { * self == MCTR_START_A :: MCTR_START_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_mctr_start_enable (& self) -> bool { * self == MCTR_START_A :: MCTR_START_ENABLE } } # [doc = "Field `MCTR_START` writer - Generate START"] pub type MCTR_START_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , MCTR_START_A > ; impl < 'a , REG , const O : u8 > MCTR_START_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn mctr_start_disable (self) -> & 'a mut crate :: W < REG > { self . variant (MCTR_START_A :: MCTR_START_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn mctr_start_enable (self) -> & 'a mut crate :: W < REG > { self . variant (MCTR_START_A :: MCTR_START_ENABLE) } } # [doc = "Field `MCTR_STOP` reader - Generate STOP"] pub type MCTR_STOP_R = crate :: BitReader < MCTR_STOP_A > ; # [doc = "Generate STOP\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum MCTR_STOP_A { # [doc = "0: DISABLE"] MCTR_STOP_DISABLE = 0 , # [doc = "1: ENABLE"] MCTR_STOP_ENABLE = 1 , } impl From < MCTR_STOP_A > for bool { # [inline (always)] fn from (variant : MCTR_STOP_A) -> Self { variant as u8 != 0 } } impl MCTR_STOP_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> MCTR_STOP_A { match self . bits { false => MCTR_STOP_A :: MCTR_STOP_DISABLE , true => MCTR_STOP_A :: MCTR_STOP_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_mctr_stop_disable (& self) -> bool { * self == MCTR_STOP_A :: MCTR_STOP_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_mctr_stop_enable (& self) -> bool { * self == MCTR_STOP_A :: MCTR_STOP_ENABLE } } # [doc = "Field `MCTR_STOP` writer - Generate STOP"] pub type MCTR_STOP_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , MCTR_STOP_A > ; impl < 'a , REG , const O : u8 > MCTR_STOP_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn mctr_stop_disable (self) -> & 'a mut crate :: W < REG > { self . variant (MCTR_STOP_A :: MCTR_STOP_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn mctr_stop_enable (self) -> & 'a mut crate :: W < REG > { self . variant (MCTR_STOP_A :: MCTR_STOP_ENABLE) } } # [doc = "Field `MCTR_ACK` reader - Data Acknowledge Enable. Software needs to configure this bit to send the ACK or NACK. See field decoding in Table: MCTR Field decoding."] pub type MCTR_ACK_R = crate :: BitReader < MCTR_ACK_A > ; # [doc = "Data Acknowledge Enable. Software needs to configure this bit to send the ACK or NACK. See field decoding in Table: MCTR Field decoding.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum MCTR_ACK_A { # [doc = "0: DISABLE"] MCTR_ACK_DISABLE = 0 , # [doc = "1: ENABLE"] MCTR_ACK_ENABLE = 1 , } impl From < MCTR_ACK_A > for bool { # [inline (always)] fn from (variant : MCTR_ACK_A) -> Self { variant as u8 != 0 } } impl MCTR_ACK_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> MCTR_ACK_A { match self . bits { false => MCTR_ACK_A :: MCTR_ACK_DISABLE , true => MCTR_ACK_A :: MCTR_ACK_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_mctr_ack_disable (& self) -> bool { * self == MCTR_ACK_A :: MCTR_ACK_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_mctr_ack_enable (& self) -> bool { * self == MCTR_ACK_A :: MCTR_ACK_ENABLE } } # [doc = "Field `MCTR_ACK` writer - Data Acknowledge Enable. Software needs to configure this bit to send the ACK or NACK. See field decoding in Table: MCTR Field decoding."] pub type MCTR_ACK_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , MCTR_ACK_A > ; impl < 'a , REG , const O : u8 > MCTR_ACK_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn mctr_ack_disable (self) -> & 'a mut crate :: W < REG > { self . variant (MCTR_ACK_A :: MCTR_ACK_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn mctr_ack_enable (self) -> & 'a mut crate :: W < REG > { self . variant (MCTR_ACK_A :: MCTR_ACK_ENABLE) } } # [doc = "Field `MCTR_MACKOEN` reader - Master ACK overrride Enable"] pub type MCTR_MACKOEN_R = crate :: BitReader < MCTR_MACKOEN_A > ; # [doc = "Master ACK overrride Enable\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum MCTR_MACKOEN_A { # [doc = "0: DISABLE"] MCTR_MACKOEN_DISABLE = 0 , # [doc = "1: ENABLE"] MCTR_MACKOEN_ENABLE = 1 , } impl From < MCTR_MACKOEN_A > for bool { # [inline (always)] fn from (variant : MCTR_MACKOEN_A) -> Self { variant as u8 != 0 } } impl MCTR_MACKOEN_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> MCTR_MACKOEN_A { match self . bits { false => MCTR_MACKOEN_A :: MCTR_MACKOEN_DISABLE , true => MCTR_MACKOEN_A :: MCTR_MACKOEN_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_mctr_mackoen_disable (& self) -> bool { * self == MCTR_MACKOEN_A :: MCTR_MACKOEN_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_mctr_mackoen_enable (& self) -> bool { * self == MCTR_MACKOEN_A :: MCTR_MACKOEN_ENABLE } } # [doc = "Field `MCTR_MACKOEN` writer - Master ACK overrride Enable"] pub type MCTR_MACKOEN_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , MCTR_MACKOEN_A > ; impl < 'a , REG , const O : u8 > MCTR_MACKOEN_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn mctr_mackoen_disable (self) -> & 'a mut crate :: W < REG > { self . variant (MCTR_MACKOEN_A :: MCTR_MACKOEN_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn mctr_mackoen_enable (self) -> & 'a mut crate :: W < REG > { self . variant (MCTR_MACKOEN_A :: MCTR_MACKOEN_ENABLE) } } # [doc = "Field `MCTR_RD_ON_TXEMPTY` reader - Read on TX Empty"] pub type MCTR_RD_ON_TXEMPTY_R = crate :: BitReader < MCTR_RD_ON_TXEMPTY_A > ; # [doc = "Read on TX Empty\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum MCTR_RD_ON_TXEMPTY_A { # [doc = "0: DISABLE"] MCTR_RD_ON_TXEMPTY_DISABLE = 0 , # [doc = "1: ENABLE"] MCTR_RD_ON_TXEMPTY_ENABLE = 1 , } impl From < MCTR_RD_ON_TXEMPTY_A > for bool { # [inline (always)] fn from (variant : MCTR_RD_ON_TXEMPTY_A) -> Self { variant as u8 != 0 } } impl MCTR_RD_ON_TXEMPTY_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> MCTR_RD_ON_TXEMPTY_A { match self . bits { false => MCTR_RD_ON_TXEMPTY_A :: MCTR_RD_ON_TXEMPTY_DISABLE , true => MCTR_RD_ON_TXEMPTY_A :: MCTR_RD_ON_TXEMPTY_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_mctr_rd_on_txempty_disable (& self) -> bool { * self == MCTR_RD_ON_TXEMPTY_A :: MCTR_RD_ON_TXEMPTY_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_mctr_rd_on_txempty_enable (& self) -> bool { * self == MCTR_RD_ON_TXEMPTY_A :: MCTR_RD_ON_TXEMPTY_ENABLE } } # [doc = "Field `MCTR_RD_ON_TXEMPTY` writer - Read on TX Empty"] pub type MCTR_RD_ON_TXEMPTY_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , MCTR_RD_ON_TXEMPTY_A > ; impl < 'a , REG , const O : u8 > MCTR_RD_ON_TXEMPTY_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn mctr_rd_on_txempty_disable (self) -> & 'a mut crate :: W < REG > { self . variant (MCTR_RD_ON_TXEMPTY_A :: MCTR_RD_ON_TXEMPTY_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn mctr_rd_on_txempty_enable (self) -> & 'a mut crate :: W < REG > { self . variant (MCTR_RD_ON_TXEMPTY_A :: MCTR_RD_ON_TXEMPTY_ENABLE) } } # [doc = "Field `MCTR_MBLEN` reader - I2C transaction length This field contains the programmed length of bytes of the Transaction."] pub type MCTR_MBLEN_R = crate :: FieldReader < u16 > ; # [doc = "Field `MCTR_MBLEN` writer - I2C transaction length This field contains the programmed length of bytes of the Transaction."] pub type MCTR_MBLEN_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 12 , O , u16 > ; impl R { # [doc = "Bit 0 - I2C Master Enable and start transaction"] # [inline (always)] pub fn mctr_burstrun (& self) -> MCTR_BURSTRUN_R { MCTR_BURSTRUN_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - Generate START"] # [inline (always)] pub fn mctr_start (& self) -> MCTR_START_R { MCTR_START_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - Generate STOP"] # [inline (always)] pub fn mctr_stop (& self) -> MCTR_STOP_R { MCTR_STOP_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - Data Acknowledge Enable. Software needs to configure this bit to send the ACK or NACK. See field decoding in Table: MCTR Field decoding."] # [inline (always)] pub fn mctr_ack (& self) -> MCTR_ACK_R { MCTR_ACK_R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - Master ACK overrride Enable"] # [inline (always)] pub fn mctr_mackoen (& self) -> MCTR_MACKOEN_R { MCTR_MACKOEN_R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - Read on TX Empty"] # [inline (always)] pub fn mctr_rd_on_txempty (& self) -> MCTR_RD_ON_TXEMPTY_R { MCTR_RD_ON_TXEMPTY_R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bits 16:27 - I2C transaction length This field contains the programmed length of bytes of the Transaction."] # [inline (always)] pub fn mctr_mblen (& self) -> MCTR_MBLEN_R { MCTR_MBLEN_R :: new (((self . bits >> 16) & 0x0fff) as u16) } } impl W { # [doc = "Bit 0 - I2C Master Enable and start transaction"] # [inline (always)] # [must_use] pub fn mctr_burstrun (& mut self) -> MCTR_BURSTRUN_W < MCTR_SPEC , 0 > { MCTR_BURSTRUN_W :: new (self) } # [doc = "Bit 1 - Generate START"] # [inline (always)] # [must_use] pub fn mctr_start (& mut self) -> MCTR_START_W < MCTR_SPEC , 1 > { MCTR_START_W :: new (self) } # [doc = "Bit 2 - Generate STOP"] # [inline (always)] # [must_use] pub fn mctr_stop (& mut self) -> MCTR_STOP_W <'_, MCTR_SPEC , 2 > { MCTR_STOP_W :: new (self) } # [doc = "Bit 3 - Data Acknowledge Enable. Software needs to configure this bit to send the ACK or NACK. See field decoding in Table: MCTR Field decoding."] # [inline (always)] # [must_use] pub fn mctr_ack (& mut self) -> MCTR_ACK_W < MCTR_SPEC , 3 > { MCTR_ACK_W :: new (self) } # [doc = "Bit 4 - Master ACK overrride Enable"] # [inline (always)] # [must_use] pub fn mctr_mackoen (& mut self) -> MCTR_MACKOEN_W < MCTR_SPEC , 4 > { MCTR_MACKOEN_W :: new (self) } # [doc = "Bit 5 - Read on TX Empty"] # [inline (always)] # [must_use] pub fn mctr_rd_on_txempty (& mut self) -> MCTR_RD_ON_TXEMPTY_W < MCTR_SPEC , 5 > { MCTR_RD_ON_TXEMPTY_W :: new (self) } # [doc = "Bits 16:27 - I2C transaction length This field contains the programmed length of bytes of the Transaction."] # [inline (always)] # [must_use] pub fn mctr_mblen (& mut self) -> MCTR_MBLEN_W < MCTR_SPEC , 16 > { MCTR_MBLEN_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "I2C Master Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mctr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mctr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct MCTR_SPEC ; impl crate :: RegisterSpec for MCTR_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`mctr::R`](R) reader structure"] impl crate :: Readable for MCTR_SPEC { } # [doc = "`write(|w| ..)` method takes [`mctr::W`](W) writer structure"] impl crate :: Writable for MCTR_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets MCTR to value 0"] impl crate :: Resettable for MCTR_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/i2c0/mcr.rs:1:9338 [INFO] [stdout] | [INFO] [stdout] 1 | ... [must_use] pub fn mcr_mmst (& mut self) -> MCR_MMST_W < MCR_SPEC , 1 > { MCR_MMST_W :: new (self) } # [doc = "Bit 2 - Clock Stretchin... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `MCR` reader"] pub type R = crate :: R < MCR_SPEC > ; # [doc = "Register `MCR` writer"] pub type W = crate :: W < MCR_SPEC > ; # [doc = "Field `MCR_ACTIVE` reader - Device Active After this bit has been set, it should not be set again unless it has been cleared by writing a 0 or by a reset, otherwise transfer failures may occur."] pub type MCR_ACTIVE_R = crate :: BitReader < MCR_ACTIVE_A > ; # [doc = "Device Active After this bit has been set, it should not be set again unless it has been cleared by writing a 0 or by a reset, otherwise transfer failures may occur.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum MCR_ACTIVE_A { # [doc = "0: DISABLE"] MCR_ACTIVE_DISABLE = 0 , # [doc = "1: ENABLE"] MCR_ACTIVE_ENABLE = 1 , } impl From < MCR_ACTIVE_A > for bool { # [inline (always)] fn from (variant : MCR_ACTIVE_A) -> Self { variant as u8 != 0 } } impl MCR_ACTIVE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> MCR_ACTIVE_A { match self . bits { false => MCR_ACTIVE_A :: MCR_ACTIVE_DISABLE , true => MCR_ACTIVE_A :: MCR_ACTIVE_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_mcr_active_disable (& self) -> bool { * self == MCR_ACTIVE_A :: MCR_ACTIVE_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_mcr_active_enable (& self) -> bool { * self == MCR_ACTIVE_A :: MCR_ACTIVE_ENABLE } } # [doc = "Field `MCR_ACTIVE` writer - Device Active After this bit has been set, it should not be set again unless it has been cleared by writing a 0 or by a reset, otherwise transfer failures may occur."] pub type MCR_ACTIVE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , MCR_ACTIVE_A > ; impl < 'a , REG , const O : u8 > MCR_ACTIVE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn mcr_active_disable (self) -> & 'a mut crate :: W < REG > { self . variant (MCR_ACTIVE_A :: MCR_ACTIVE_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn mcr_active_enable (self) -> & 'a mut crate :: W < REG > { self . variant (MCR_ACTIVE_A :: MCR_ACTIVE_ENABLE) } } # [doc = "Field `MCR_MMST` reader - Multimaster mode. In Multimaster mode the SCL high time counts once the SCL line has been detected high. If this is not enabled the high time counts as soon as the SCL line has been set high by the I2C controller."] pub type MCR_MMST_R = crate :: BitReader < MCR_MMST_A > ; # [doc = "Multimaster mode. In Multimaster mode the SCL high time counts once the SCL line has been detected high. If this is not enabled the high time counts as soon as the SCL line has been set high by the I2C controller.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum MCR_MMST_A { # [doc = "0: DISABLE"] MCR_MMST_DISABLE = 0 , # [doc = "1: ENABLE"] MCR_MMST_ENABLE = 1 , } impl From < MCR_MMST_A > for bool { # [inline (always)] fn from (variant : MCR_MMST_A) -> Self { variant as u8 != 0 } } impl MCR_MMST_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> MCR_MMST_A { match self . bits { false => MCR_MMST_A :: MCR_MMST_DISABLE , true => MCR_MMST_A :: MCR_MMST_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_mcr_mmst_disable (& self) -> bool { * self == MCR_MMST_A :: MCR_MMST_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_mcr_mmst_enable (& self) -> bool { * self == MCR_MMST_A :: MCR_MMST_ENABLE } } # [doc = "Field `MCR_MMST` writer - Multimaster mode. In Multimaster mode the SCL high time counts once the SCL line has been detected high. If this is not enabled the high time counts as soon as the SCL line has been set high by the I2C controller."] pub type MCR_MMST_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , MCR_MMST_A > ; impl < 'a , REG , const O : u8 > MCR_MMST_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn mcr_mmst_disable (self) -> & 'a mut crate :: W < REG > { self . variant (MCR_MMST_A :: MCR_MMST_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn mcr_mmst_enable (self) -> & 'a mut crate :: W < REG > { self . variant (MCR_MMST_A :: MCR_MMST_ENABLE) } } # [doc = "Field `MCR_CLKSTRETCH` reader - Clock Stretching. This bit controls the support for clock stretching of the I2C bus."] pub type MCR_CLKSTRETCH_R = crate :: BitReader < MCR_CLKSTRETCH_A > ; # [doc = "Clock Stretching. This bit controls the support for clock stretching of the I2C bus.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum MCR_CLKSTRETCH_A { # [doc = "0: DISABLE"] MCR_CLKSTRETCH_DISABLE = 0 , # [doc = "1: ENABLE"] MCR_CLKSTRETCH_ENABLE = 1 , } impl From < MCR_CLKSTRETCH_A > for bool { # [inline (always)] fn from (variant : MCR_CLKSTRETCH_A) -> Self { variant as u8 != 0 } } impl MCR_CLKSTRETCH_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> MCR_CLKSTRETCH_A { match self . bits { false => MCR_CLKSTRETCH_A :: MCR_CLKSTRETCH_DISABLE , true => MCR_CLKSTRETCH_A :: MCR_CLKSTRETCH_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_mcr_clkstretch_disable (& self) -> bool { * self == MCR_CLKSTRETCH_A :: MCR_CLKSTRETCH_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_mcr_clkstretch_enable (& self) -> bool { * self == MCR_CLKSTRETCH_A :: MCR_CLKSTRETCH_ENABLE } } # [doc = "Field `MCR_CLKSTRETCH` writer - Clock Stretching. This bit controls the support for clock stretching of the I2C bus."] pub type MCR_CLKSTRETCH_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , MCR_CLKSTRETCH_A > ; impl < 'a , REG , const O : u8 > MCR_CLKSTRETCH_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn mcr_clkstretch_disable (self) -> & 'a mut crate :: W < REG > { self . variant (MCR_CLKSTRETCH_A :: MCR_CLKSTRETCH_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn mcr_clkstretch_enable (self) -> & 'a mut crate :: W < REG > { self . variant (MCR_CLKSTRETCH_A :: MCR_CLKSTRETCH_ENABLE) } } # [doc = "Field `MCR_LPBK` reader - I2C Loopback"] pub type MCR_LPBK_R = crate :: BitReader < MCR_LPBK_A > ; # [doc = "I2C Loopback\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum MCR_LPBK_A { # [doc = "0: DISABLE"] MCR_LPBK_DISABLE = 0 , # [doc = "1: ENABLE"] MCR_LPBK_ENABLE = 1 , } impl From < MCR_LPBK_A > for bool { # [inline (always)] fn from (variant : MCR_LPBK_A) -> Self { variant as u8 != 0 } } impl MCR_LPBK_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> MCR_LPBK_A { match self . bits { false => MCR_LPBK_A :: MCR_LPBK_DISABLE , true => MCR_LPBK_A :: MCR_LPBK_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_mcr_lpbk_disable (& self) -> bool { * self == MCR_LPBK_A :: MCR_LPBK_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_mcr_lpbk_enable (& self) -> bool { * self == MCR_LPBK_A :: MCR_LPBK_ENABLE } } # [doc = "Field `MCR_LPBK` writer - I2C Loopback"] pub type MCR_LPBK_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , MCR_LPBK_A > ; impl < 'a , REG , const O : u8 > MCR_LPBK_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn mcr_lpbk_disable (self) -> & 'a mut crate :: W < REG > { self . variant (MCR_LPBK_A :: MCR_LPBK_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn mcr_lpbk_enable (self) -> & 'a mut crate :: W < REG > { self . variant (MCR_LPBK_A :: MCR_LPBK_ENABLE) } } impl R { # [doc = "Bit 0 - Device Active After this bit has been set, it should not be set again unless it has been cleared by writing a 0 or by a reset, otherwise transfer failures may occur."] # [inline (always)] pub fn mcr_active (& self) -> MCR_ACTIVE_R { MCR_ACTIVE_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - Multimaster mode. In Multimaster mode the SCL high time counts once the SCL line has been detected high. If this is not enabled the high time counts as soon as the SCL line has been set high by the I2C controller."] # [inline (always)] pub fn mcr_mmst (& self) -> MCR_MMST_R { MCR_MMST_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - Clock Stretching. This bit controls the support for clock stretching of the I2C bus."] # [inline (always)] pub fn mcr_clkstretch (& self) -> MCR_CLKSTRETCH_R { MCR_CLKSTRETCH_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 8 - I2C Loopback"] # [inline (always)] pub fn mcr_lpbk (& self) -> MCR_LPBK_R { MCR_LPBK_R :: new (((self . bits >> 8) & 1) != 0) } } impl W { # [doc = "Bit 0 - Device Active After this bit has been set, it should not be set again unless it has been cleared by writing a 0 or by a reset, otherwise transfer failures may occur."] # [inline (always)] # [must_use] pub fn mcr_active (& mut self) -> MCR_ACTIVE_W < MCR_SPEC , 0 > { MCR_ACTIVE_W :: new (self) } # [doc = "Bit 1 - Multimaster mode. In Multimaster mode the SCL high time counts once the SCL line has been detected high. If this is not enabled the high time counts as soon as the SCL line has been set high by the I2C controller."] # [inline (always)] # [must_use] pub fn mcr_mmst (& mut self) -> MCR_MMST_W <'_, MCR_SPEC , 1 > { MCR_MMST_W :: new (self) } # [doc = "Bit 2 - Clock Stretching. This bit controls the support for clock stretching of the I2C bus."] # [inline (always)] # [must_use] pub fn mcr_clkstretch (& mut self) -> MCR_CLKSTRETCH_W < MCR_SPEC , 2 > { MCR_CLKSTRETCH_W :: new (self) } # [doc = "Bit 8 - I2C Loopback"] # [inline (always)] # [must_use] pub fn mcr_lpbk (& mut self) -> MCR_LPBK_W < MCR_SPEC , 8 > { MCR_LPBK_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "I2C Master Configuration\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mcr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mcr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct MCR_SPEC ; impl crate :: RegisterSpec for MCR_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`mcr::R`](R) reader structure"] impl crate :: Readable for MCR_SPEC { } # [doc = "`write(|w| ..)` method takes [`mcr::W`](W) writer structure"] impl crate :: Writable for MCR_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets MCR to value 0"] impl crate :: Resettable for MCR_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/spi0/pdbgctl.rs:5:247 [INFO] [stdout] | [INFO] [stdout] 5 | ...se] pub fn pdbgctl_free (& mut self) -> PDBGCTL_FREE_W < PDBGCTL_SPEC , 0 > { PDBGCTL_FREE_W :: new (self) } # [doc = "Bit 1 - Soft ha... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 5 | is set to 'STOP'"] # [inline (always)] pub fn pdbgctl_soft (& self) -> PDBGCTL_SOFT_R { PDBGCTL_SOFT_R :: new (((self . bits >> 1) & 1) != 0) } } impl W { # [doc = "Bit 0 - Free run control"] # [inline (always)] # [must_use] pub fn pdbgctl_free (& mut self) -> PDBGCTL_FREE_W <'_, PDBGCTL_SPEC , 0 > { PDBGCTL_FREE_W :: new (self) } # [doc = "Bit 1 - Soft halt boundary control. This function is only available, if \\[FREE\\] [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/spi0/pdbgctl.rs:6:74 [INFO] [stdout] | [INFO] [stdout] 6 | ...se] pub fn pdbgctl_soft (& mut self) -> PDBGCTL_SOFT_W < PDBGCTL_SPEC , 1 > { PDBGCTL_SOFT_W :: new (self) } # [doc = r" Writes raw bi... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 6 | is set to 'STOP'"] # [inline (always)] # [must_use] pub fn pdbgctl_soft (& mut self) -> PDBGCTL_SOFT_W <'_, PDBGCTL_SPEC , 1 > { PDBGCTL_SOFT_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Peripheral Debug Control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pdbgctl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pdbgctl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PDBGCTL_SPEC ; impl crate :: RegisterSpec for PDBGCTL_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`pdbgctl::R`](R) reader structure"] impl crate :: Readable for PDBGCTL_SPEC { } # [doc = "`write(|w| ..)` method takes [`pdbgctl::W`](W) writer structure"] impl crate :: Writable for PDBGCTL_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets PDBGCTL to value 0"] impl crate :: Resettable for PDBGCTL_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/timg4/ccctl_01.rs:1:35645 [INFO] [stdout] | [INFO] [stdout] 1 | ...fn ccctl_01_ccactupd (& mut self) -> CCCTL_01_CCACTUPD_W < CCCTL_01_SPEC , 26 > { CCCTL_01_CCACTUPD_W :: new (self) } # [doc = "Bits 2... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `CCCTL_01[%s]` reader"] pub type R = crate :: R < CCCTL_01_SPEC > ; # [doc = "Register `CCCTL_01[%s]` writer"] pub type W = crate :: W < CCCTL_01_SPEC > ; # [doc = "Field `CCCTL_01_CCOND` reader - Capture Condition. #br# Specifies the condition that generates a capture pulse. 4h-Fh = Reserved"] pub type CCCTL_01_CCOND_R = crate :: FieldReader < CCCTL_01_CCOND_A > ; # [doc = "Capture Condition. #br# Specifies the condition that generates a capture pulse. 4h-Fh = Reserved\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum CCCTL_01_CCOND_A { # [doc = "0: NOCAPTURE"] CCCTL_01_CCOND_NOCAPTURE = 0 , # [doc = "1: CC_TRIG_RISE"] CCCTL_01_CCOND_CC_TRIG_RISE = 1 , # [doc = "2: CC_TRIG_FALL"] CCCTL_01_CCOND_CC_TRIG_FALL = 2 , # [doc = "3: CC_TRIG_EDGE"] CCCTL_01_CCOND_CC_TRIG_EDGE = 3 , } impl From < CCCTL_01_CCOND_A > for u8 { # [inline (always)] fn from (variant : CCCTL_01_CCOND_A) -> Self { variant as _ } } impl crate :: FieldSpec for CCCTL_01_CCOND_A { type Ux = u8 ; } impl CCCTL_01_CCOND_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < CCCTL_01_CCOND_A > { match self . bits { 0 => Some (CCCTL_01_CCOND_A :: CCCTL_01_CCOND_NOCAPTURE) , 1 => Some (CCCTL_01_CCOND_A :: CCCTL_01_CCOND_CC_TRIG_RISE) , 2 => Some (CCCTL_01_CCOND_A :: CCCTL_01_CCOND_CC_TRIG_FALL) , 3 => Some (CCCTL_01_CCOND_A :: CCCTL_01_CCOND_CC_TRIG_EDGE) , _ => None , } } # [doc = "NOCAPTURE"] # [inline (always)] pub fn is_ccctl_01_ccond_nocapture (& self) -> bool { * self == CCCTL_01_CCOND_A :: CCCTL_01_CCOND_NOCAPTURE } # [doc = "CC_TRIG_RISE"] # [inline (always)] pub fn is_ccctl_01_ccond_cc_trig_rise (& self) -> bool { * self == CCCTL_01_CCOND_A :: CCCTL_01_CCOND_CC_TRIG_RISE } # [doc = "CC_TRIG_FALL"] # [inline (always)] pub fn is_ccctl_01_ccond_cc_trig_fall (& self) -> bool { * self == CCCTL_01_CCOND_A :: CCCTL_01_CCOND_CC_TRIG_FALL } # [doc = "CC_TRIG_EDGE"] # [inline (always)] pub fn is_ccctl_01_ccond_cc_trig_edge (& self) -> bool { * self == CCCTL_01_CCOND_A :: CCCTL_01_CCOND_CC_TRIG_EDGE } } # [doc = "Field `CCCTL_01_CCOND` writer - Capture Condition. #br# Specifies the condition that generates a capture pulse. 4h-Fh = Reserved"] pub type CCCTL_01_CCOND_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 3 , O , CCCTL_01_CCOND_A > ; impl < 'a , REG , const O : u8 > CCCTL_01_CCOND_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "NOCAPTURE"] # [inline (always)] pub fn ccctl_01_ccond_nocapture (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CCOND_A :: CCCTL_01_CCOND_NOCAPTURE) } # [doc = "CC_TRIG_RISE"] # [inline (always)] pub fn ccctl_01_ccond_cc_trig_rise (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CCOND_A :: CCCTL_01_CCOND_CC_TRIG_RISE) } # [doc = "CC_TRIG_FALL"] # [inline (always)] pub fn ccctl_01_ccond_cc_trig_fall (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CCOND_A :: CCCTL_01_CCOND_CC_TRIG_FALL) } # [doc = "CC_TRIG_EDGE"] # [inline (always)] pub fn ccctl_01_ccond_cc_trig_edge (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CCOND_A :: CCCTL_01_CCOND_CC_TRIG_EDGE) } } # [doc = "Field `CCCTL_01_ACOND` reader - Advance Condition. #br# Specifies the condition that generates an advance pulse. 6h-Fh = Reserved"] pub type CCCTL_01_ACOND_R = crate :: FieldReader < CCCTL_01_ACOND_A > ; # [doc = "Advance Condition. #br# Specifies the condition that generates an advance pulse. 6h-Fh = Reserved\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum CCCTL_01_ACOND_A { # [doc = "0: TIMCLK"] CCCTL_01_ACOND_TIMCLK = 0 , # [doc = "1: CC_TRIG_RISE"] CCCTL_01_ACOND_CC_TRIG_RISE = 1 , # [doc = "2: CC_TRIG_FALL"] CCCTL_01_ACOND_CC_TRIG_FALL = 2 , # [doc = "3: CC_TRIG_EDGE"] CCCTL_01_ACOND_CC_TRIG_EDGE = 3 , # [doc = "5: CC_TRIG_HIGH"] CCCTL_01_ACOND_CC_TRIG_HIGH = 5 , } impl From < CCCTL_01_ACOND_A > for u8 { # [inline (always)] fn from (variant : CCCTL_01_ACOND_A) -> Self { variant as _ } } impl crate :: FieldSpec for CCCTL_01_ACOND_A { type Ux = u8 ; } impl CCCTL_01_ACOND_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < CCCTL_01_ACOND_A > { match self . bits { 0 => Some (CCCTL_01_ACOND_A :: CCCTL_01_ACOND_TIMCLK) , 1 => Some (CCCTL_01_ACOND_A :: CCCTL_01_ACOND_CC_TRIG_RISE) , 2 => Some (CCCTL_01_ACOND_A :: CCCTL_01_ACOND_CC_TRIG_FALL) , 3 => Some (CCCTL_01_ACOND_A :: CCCTL_01_ACOND_CC_TRIG_EDGE) , 5 => Some (CCCTL_01_ACOND_A :: CCCTL_01_ACOND_CC_TRIG_HIGH) , _ => None , } } # [doc = "TIMCLK"] # [inline (always)] pub fn is_ccctl_01_acond_timclk (& self) -> bool { * self == CCCTL_01_ACOND_A :: CCCTL_01_ACOND_TIMCLK } # [doc = "CC_TRIG_RISE"] # [inline (always)] pub fn is_ccctl_01_acond_cc_trig_rise (& self) -> bool { * self == CCCTL_01_ACOND_A :: CCCTL_01_ACOND_CC_TRIG_RISE } # [doc = "CC_TRIG_FALL"] # [inline (always)] pub fn is_ccctl_01_acond_cc_trig_fall (& self) -> bool { * self == CCCTL_01_ACOND_A :: CCCTL_01_ACOND_CC_TRIG_FALL } # [doc = "CC_TRIG_EDGE"] # [inline (always)] pub fn is_ccctl_01_acond_cc_trig_edge (& self) -> bool { * self == CCCTL_01_ACOND_A :: CCCTL_01_ACOND_CC_TRIG_EDGE } # [doc = "CC_TRIG_HIGH"] # [inline (always)] pub fn is_ccctl_01_acond_cc_trig_high (& self) -> bool { * self == CCCTL_01_ACOND_A :: CCCTL_01_ACOND_CC_TRIG_HIGH } } # [doc = "Field `CCCTL_01_ACOND` writer - Advance Condition. #br# Specifies the condition that generates an advance pulse. 6h-Fh = Reserved"] pub type CCCTL_01_ACOND_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 3 , O , CCCTL_01_ACOND_A > ; impl < 'a , REG , const O : u8 > CCCTL_01_ACOND_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "TIMCLK"] # [inline (always)] pub fn ccctl_01_acond_timclk (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_ACOND_A :: CCCTL_01_ACOND_TIMCLK) } # [doc = "CC_TRIG_RISE"] # [inline (always)] pub fn ccctl_01_acond_cc_trig_rise (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_ACOND_A :: CCCTL_01_ACOND_CC_TRIG_RISE) } # [doc = "CC_TRIG_FALL"] # [inline (always)] pub fn ccctl_01_acond_cc_trig_fall (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_ACOND_A :: CCCTL_01_ACOND_CC_TRIG_FALL) } # [doc = "CC_TRIG_EDGE"] # [inline (always)] pub fn ccctl_01_acond_cc_trig_edge (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_ACOND_A :: CCCTL_01_ACOND_CC_TRIG_EDGE) } # [doc = "CC_TRIG_HIGH"] # [inline (always)] pub fn ccctl_01_acond_cc_trig_high (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_ACOND_A :: CCCTL_01_ACOND_CC_TRIG_HIGH) } } # [doc = "Field `CCCTL_01_LCOND` reader - Load Condition. #br# Specifies the condition that generates a load pulse. 4h-Fh = Reserved"] pub type CCCTL_01_LCOND_R = crate :: FieldReader < CCCTL_01_LCOND_A > ; # [doc = "Load Condition. #br# Specifies the condition that generates a load pulse. 4h-Fh = Reserved\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum CCCTL_01_LCOND_A { # [doc = "1: CC_TRIG_RISE"] CCCTL_01_LCOND_CC_TRIG_RISE = 1 , # [doc = "2: CC_TRIG_FALL"] CCCTL_01_LCOND_CC_TRIG_FALL = 2 , # [doc = "3: CC_TRIG_EDGE"] CCCTL_01_LCOND_CC_TRIG_EDGE = 3 , } impl From < CCCTL_01_LCOND_A > for u8 { # [inline (always)] fn from (variant : CCCTL_01_LCOND_A) -> Self { variant as _ } } impl crate :: FieldSpec for CCCTL_01_LCOND_A { type Ux = u8 ; } impl CCCTL_01_LCOND_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < CCCTL_01_LCOND_A > { match self . bits { 1 => Some (CCCTL_01_LCOND_A :: CCCTL_01_LCOND_CC_TRIG_RISE) , 2 => Some (CCCTL_01_LCOND_A :: CCCTL_01_LCOND_CC_TRIG_FALL) , 3 => Some (CCCTL_01_LCOND_A :: CCCTL_01_LCOND_CC_TRIG_EDGE) , _ => None , } } # [doc = "CC_TRIG_RISE"] # [inline (always)] pub fn is_ccctl_01_lcond_cc_trig_rise (& self) -> bool { * self == CCCTL_01_LCOND_A :: CCCTL_01_LCOND_CC_TRIG_RISE } # [doc = "CC_TRIG_FALL"] # [inline (always)] pub fn is_ccctl_01_lcond_cc_trig_fall (& self) -> bool { * self == CCCTL_01_LCOND_A :: CCCTL_01_LCOND_CC_TRIG_FALL } # [doc = "CC_TRIG_EDGE"] # [inline (always)] pub fn is_ccctl_01_lcond_cc_trig_edge (& self) -> bool { * self == CCCTL_01_LCOND_A :: CCCTL_01_LCOND_CC_TRIG_EDGE } } # [doc = "Field `CCCTL_01_LCOND` writer - Load Condition. #br# Specifies the condition that generates a load pulse. 4h-Fh = Reserved"] pub type CCCTL_01_LCOND_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 3 , O , CCCTL_01_LCOND_A > ; impl < 'a , REG , const O : u8 > CCCTL_01_LCOND_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "CC_TRIG_RISE"] # [inline (always)] pub fn ccctl_01_lcond_cc_trig_rise (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_LCOND_A :: CCCTL_01_LCOND_CC_TRIG_RISE) } # [doc = "CC_TRIG_FALL"] # [inline (always)] pub fn ccctl_01_lcond_cc_trig_fall (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_LCOND_A :: CCCTL_01_LCOND_CC_TRIG_FALL) } # [doc = "CC_TRIG_EDGE"] # [inline (always)] pub fn ccctl_01_lcond_cc_trig_edge (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_LCOND_A :: CCCTL_01_LCOND_CC_TRIG_EDGE) } } # [doc = "Field `CCCTL_01_ZCOND` reader - Zero Condition. #br# This field specifies the condition that generates a zero pulse. 4h-Fh = Reserved"] pub type CCCTL_01_ZCOND_R = crate :: FieldReader < CCCTL_01_ZCOND_A > ; # [doc = "Zero Condition. #br# This field specifies the condition that generates a zero pulse. 4h-Fh = Reserved\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum CCCTL_01_ZCOND_A { # [doc = "1: CC_TRIG_RISE"] CCCTL_01_ZCOND_CC_TRIG_RISE = 1 , # [doc = "2: CC_TRIG_FALL"] CCCTL_01_ZCOND_CC_TRIG_FALL = 2 , # [doc = "3: CC_TRIG_EDGE"] CCCTL_01_ZCOND_CC_TRIG_EDGE = 3 , } impl From < CCCTL_01_ZCOND_A > for u8 { # [inline (always)] fn from (variant : CCCTL_01_ZCOND_A) -> Self { variant as _ } } impl crate :: FieldSpec for CCCTL_01_ZCOND_A { type Ux = u8 ; } impl CCCTL_01_ZCOND_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < CCCTL_01_ZCOND_A > { match self . bits { 1 => Some (CCCTL_01_ZCOND_A :: CCCTL_01_ZCOND_CC_TRIG_RISE) , 2 => Some (CCCTL_01_ZCOND_A :: CCCTL_01_ZCOND_CC_TRIG_FALL) , 3 => Some (CCCTL_01_ZCOND_A :: CCCTL_01_ZCOND_CC_TRIG_EDGE) , _ => None , } } # [doc = "CC_TRIG_RISE"] # [inline (always)] pub fn is_ccctl_01_zcond_cc_trig_rise (& self) -> bool { * self == CCCTL_01_ZCOND_A :: CCCTL_01_ZCOND_CC_TRIG_RISE } # [doc = "CC_TRIG_FALL"] # [inline (always)] pub fn is_ccctl_01_zcond_cc_trig_fall (& self) -> bool { * self == CCCTL_01_ZCOND_A :: CCCTL_01_ZCOND_CC_TRIG_FALL } # [doc = "CC_TRIG_EDGE"] # [inline (always)] pub fn is_ccctl_01_zcond_cc_trig_edge (& self) -> bool { * self == CCCTL_01_ZCOND_A :: CCCTL_01_ZCOND_CC_TRIG_EDGE } } # [doc = "Field `CCCTL_01_ZCOND` writer - Zero Condition. #br# This field specifies the condition that generates a zero pulse. 4h-Fh = Reserved"] pub type CCCTL_01_ZCOND_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 3 , O , CCCTL_01_ZCOND_A > ; impl < 'a , REG , const O : u8 > CCCTL_01_ZCOND_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "CC_TRIG_RISE"] # [inline (always)] pub fn ccctl_01_zcond_cc_trig_rise (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_ZCOND_A :: CCCTL_01_ZCOND_CC_TRIG_RISE) } # [doc = "CC_TRIG_FALL"] # [inline (always)] pub fn ccctl_01_zcond_cc_trig_fall (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_ZCOND_A :: CCCTL_01_ZCOND_CC_TRIG_FALL) } # [doc = "CC_TRIG_EDGE"] # [inline (always)] pub fn ccctl_01_zcond_cc_trig_edge (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_ZCOND_A :: CCCTL_01_ZCOND_CC_TRIG_EDGE) } } # [doc = "Field `CCCTL_01_COC` reader - Capture or Compare. #br# Specifies whether the corresponding CC register is used as a capture register or a compare register (never both)."] pub type CCCTL_01_COC_R = crate :: BitReader < CCCTL_01_COC_A > ; # [doc = "Capture or Compare. #br# Specifies whether the corresponding CC register is used as a capture register or a compare register (never both).\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CCCTL_01_COC_A { # [doc = "0: COMPARE"] CCCTL_01_COC_COMPARE = 0 , # [doc = "1: CAPTURE"] CCCTL_01_COC_CAPTURE = 1 , } impl From < CCCTL_01_COC_A > for bool { # [inline (always)] fn from (variant : CCCTL_01_COC_A) -> Self { variant as u8 != 0 } } impl CCCTL_01_COC_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CCCTL_01_COC_A { match self . bits { false => CCCTL_01_COC_A :: CCCTL_01_COC_COMPARE , true => CCCTL_01_COC_A :: CCCTL_01_COC_CAPTURE , } } # [doc = "COMPARE"] # [inline (always)] pub fn is_ccctl_01_coc_compare (& self) -> bool { * self == CCCTL_01_COC_A :: CCCTL_01_COC_COMPARE } # [doc = "CAPTURE"] # [inline (always)] pub fn is_ccctl_01_coc_capture (& self) -> bool { * self == CCCTL_01_COC_A :: CCCTL_01_COC_CAPTURE } } # [doc = "Field `CCCTL_01_COC` writer - Capture or Compare. #br# Specifies whether the corresponding CC register is used as a capture register or a compare register (never both)."] pub type CCCTL_01_COC_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CCCTL_01_COC_A > ; impl < 'a , REG , const O : u8 > CCCTL_01_COC_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "COMPARE"] # [inline (always)] pub fn ccctl_01_coc_compare (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_COC_A :: CCCTL_01_COC_COMPARE) } # [doc = "CAPTURE"] # [inline (always)] pub fn ccctl_01_coc_capture (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_COC_A :: CCCTL_01_COC_CAPTURE) } } # [doc = "Field `CCCTL_01_CCUPD` reader - Capture and Compare Update Method This field controls how updates to the pipelined capture and compare register are performed (when operating in compare mode, COC=0)."] pub type CCCTL_01_CCUPD_R = crate :: FieldReader < CCCTL_01_CCUPD_A > ; # [doc = "Capture and Compare Update Method This field controls how updates to the pipelined capture and compare register are performed (when operating in compare mode, COC=0).\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum CCCTL_01_CCUPD_A { # [doc = "0: IMMEDIATELY"] CCCTL_01_CCUPD_IMMEDIATELY = 0 , # [doc = "1: ZERO_EVT"] CCCTL_01_CCUPD_ZERO_EVT = 1 , # [doc = "2: COMPARE_DOWN_EVT"] CCCTL_01_CCUPD_COMPARE_DOWN_EVT = 2 , # [doc = "3: COMPARE_UP_EVT"] CCCTL_01_CCUPD_COMPARE_UP_EVT = 3 , # [doc = "4: ZERO_LOAD_EVT"] CCCTL_01_CCUPD_ZERO_LOAD_EVT = 4 , # [doc = "5: ZERO_RC_ZERO_EVT"] CCCTL_01_CCUPD_ZERO_RC_ZERO_EVT = 5 , # [doc = "6: TRIG"] CCCTL_01_CCUPD_TRIG = 6 , } impl From < CCCTL_01_CCUPD_A > for u8 { # [inline (always)] fn from (variant : CCCTL_01_CCUPD_A) -> Self { variant as _ } } impl crate :: FieldSpec for CCCTL_01_CCUPD_A { type Ux = u8 ; } impl CCCTL_01_CCUPD_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < CCCTL_01_CCUPD_A > { match self . bits { 0 => Some (CCCTL_01_CCUPD_A :: CCCTL_01_CCUPD_IMMEDIATELY) , 1 => Some (CCCTL_01_CCUPD_A :: CCCTL_01_CCUPD_ZERO_EVT) , 2 => Some (CCCTL_01_CCUPD_A :: CCCTL_01_CCUPD_COMPARE_DOWN_EVT) , 3 => Some (CCCTL_01_CCUPD_A :: CCCTL_01_CCUPD_COMPARE_UP_EVT) , 4 => Some (CCCTL_01_CCUPD_A :: CCCTL_01_CCUPD_ZERO_LOAD_EVT) , 5 => Some (CCCTL_01_CCUPD_A :: CCCTL_01_CCUPD_ZERO_RC_ZERO_EVT) , 6 => Some (CCCTL_01_CCUPD_A :: CCCTL_01_CCUPD_TRIG) , _ => None , } } # [doc = "IMMEDIATELY"] # [inline (always)] pub fn is_ccctl_01_ccupd_immediately (& self) -> bool { * self == CCCTL_01_CCUPD_A :: CCCTL_01_CCUPD_IMMEDIATELY } # [doc = "ZERO_EVT"] # [inline (always)] pub fn is_ccctl_01_ccupd_zero_evt (& self) -> bool { * self == CCCTL_01_CCUPD_A :: CCCTL_01_CCUPD_ZERO_EVT } # [doc = "COMPARE_DOWN_EVT"] # [inline (always)] pub fn is_ccctl_01_ccupd_compare_down_evt (& self) -> bool { * self == CCCTL_01_CCUPD_A :: CCCTL_01_CCUPD_COMPARE_DOWN_EVT } # [doc = "COMPARE_UP_EVT"] # [inline (always)] pub fn is_ccctl_01_ccupd_compare_up_evt (& self) -> bool { * self == CCCTL_01_CCUPD_A :: CCCTL_01_CCUPD_COMPARE_UP_EVT } # [doc = "ZERO_LOAD_EVT"] # [inline (always)] pub fn is_ccctl_01_ccupd_zero_load_evt (& self) -> bool { * self == CCCTL_01_CCUPD_A :: CCCTL_01_CCUPD_ZERO_LOAD_EVT } # [doc = "ZERO_RC_ZERO_EVT"] # [inline (always)] pub fn is_ccctl_01_ccupd_zero_rc_zero_evt (& self) -> bool { * self == CCCTL_01_CCUPD_A :: CCCTL_01_CCUPD_ZERO_RC_ZERO_EVT } # [doc = "TRIG"] # [inline (always)] pub fn is_ccctl_01_ccupd_trig (& self) -> bool { * self == CCCTL_01_CCUPD_A :: CCCTL_01_CCUPD_TRIG } } # [doc = "Field `CCCTL_01_CCUPD` writer - Capture and Compare Update Method This field controls how updates to the pipelined capture and compare register are performed (when operating in compare mode, COC=0)."] pub type CCCTL_01_CCUPD_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 3 , O , CCCTL_01_CCUPD_A > ; impl < 'a , REG , const O : u8 > CCCTL_01_CCUPD_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "IMMEDIATELY"] # [inline (always)] pub fn ccctl_01_ccupd_immediately (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CCUPD_A :: CCCTL_01_CCUPD_IMMEDIATELY) } # [doc = "ZERO_EVT"] # [inline (always)] pub fn ccctl_01_ccupd_zero_evt (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CCUPD_A :: CCCTL_01_CCUPD_ZERO_EVT) } # [doc = "COMPARE_DOWN_EVT"] # [inline (always)] pub fn ccctl_01_ccupd_compare_down_evt (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CCUPD_A :: CCCTL_01_CCUPD_COMPARE_DOWN_EVT) } # [doc = "COMPARE_UP_EVT"] # [inline (always)] pub fn ccctl_01_ccupd_compare_up_evt (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CCUPD_A :: CCCTL_01_CCUPD_COMPARE_UP_EVT) } # [doc = "ZERO_LOAD_EVT"] # [inline (always)] pub fn ccctl_01_ccupd_zero_load_evt (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CCUPD_A :: CCCTL_01_CCUPD_ZERO_LOAD_EVT) } # [doc = "ZERO_RC_ZERO_EVT"] # [inline (always)] pub fn ccctl_01_ccupd_zero_rc_zero_evt (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CCUPD_A :: CCCTL_01_CCUPD_ZERO_RC_ZERO_EVT) } # [doc = "TRIG"] # [inline (always)] pub fn ccctl_01_ccupd_trig (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CCUPD_A :: CCCTL_01_CCUPD_TRIG) } } # [doc = "Field `CCCTL_01_CC2SELU` reader - Selects the source second CCU event."] pub type CCCTL_01_CC2SELU_R = crate :: FieldReader < CCCTL_01_CC2SELU_A > ; # [doc = "Selects the source second CCU event.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum CCCTL_01_CC2SELU_A { # [doc = "0: SEL_CCU0"] CCCTL_01_CC2SELU_SEL_CCU0 = 0 , # [doc = "1: SEL_CCU1"] CCCTL_01_CC2SELU_SEL_CCU1 = 1 , # [doc = "2: SEL_CCU2"] CCCTL_01_CC2SELU_SEL_CCU2 = 2 , # [doc = "3: SEL_CCU3"] CCCTL_01_CC2SELU_SEL_CCU3 = 3 , # [doc = "4: SEL_CCU4"] CCCTL_01_CC2SELU_SEL_CCU4 = 4 , # [doc = "5: SEL_CCU5"] CCCTL_01_CC2SELU_SEL_CCU5 = 5 , } impl From < CCCTL_01_CC2SELU_A > for u8 { # [inline (always)] fn from (variant : CCCTL_01_CC2SELU_A) -> Self { variant as _ } } impl crate :: FieldSpec for CCCTL_01_CC2SELU_A { type Ux = u8 ; } impl CCCTL_01_CC2SELU_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < CCCTL_01_CC2SELU_A > { match self . bits { 0 => Some (CCCTL_01_CC2SELU_A :: CCCTL_01_CC2SELU_SEL_CCU0) , 1 => Some (CCCTL_01_CC2SELU_A :: CCCTL_01_CC2SELU_SEL_CCU1) , 2 => Some (CCCTL_01_CC2SELU_A :: CCCTL_01_CC2SELU_SEL_CCU2) , 3 => Some (CCCTL_01_CC2SELU_A :: CCCTL_01_CC2SELU_SEL_CCU3) , 4 => Some (CCCTL_01_CC2SELU_A :: CCCTL_01_CC2SELU_SEL_CCU4) , 5 => Some (CCCTL_01_CC2SELU_A :: CCCTL_01_CC2SELU_SEL_CCU5) , _ => None , } } # [doc = "SEL_CCU0"] # [inline (always)] pub fn is_ccctl_01_cc2selu_sel_ccu0 (& self) -> bool { * self == CCCTL_01_CC2SELU_A :: CCCTL_01_CC2SELU_SEL_CCU0 } # [doc = "SEL_CCU1"] # [inline (always)] pub fn is_ccctl_01_cc2selu_sel_ccu1 (& self) -> bool { * self == CCCTL_01_CC2SELU_A :: CCCTL_01_CC2SELU_SEL_CCU1 } # [doc = "SEL_CCU2"] # [inline (always)] pub fn is_ccctl_01_cc2selu_sel_ccu2 (& self) -> bool { * self == CCCTL_01_CC2SELU_A :: CCCTL_01_CC2SELU_SEL_CCU2 } # [doc = "SEL_CCU3"] # [inline (always)] pub fn is_ccctl_01_cc2selu_sel_ccu3 (& self) -> bool { * self == CCCTL_01_CC2SELU_A :: CCCTL_01_CC2SELU_SEL_CCU3 } # [doc = "SEL_CCU4"] # [inline (always)] pub fn is_ccctl_01_cc2selu_sel_ccu4 (& self) -> bool { * self == CCCTL_01_CC2SELU_A :: CCCTL_01_CC2SELU_SEL_CCU4 } # [doc = "SEL_CCU5"] # [inline (always)] pub fn is_ccctl_01_cc2selu_sel_ccu5 (& self) -> bool { * self == CCCTL_01_CC2SELU_A :: CCCTL_01_CC2SELU_SEL_CCU5 } } # [doc = "Field `CCCTL_01_CC2SELU` writer - Selects the source second CCU event."] pub type CCCTL_01_CC2SELU_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 3 , O , CCCTL_01_CC2SELU_A > ; impl < 'a , REG , const O : u8 > CCCTL_01_CC2SELU_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "SEL_CCU0"] # [inline (always)] pub fn ccctl_01_cc2selu_sel_ccu0 (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CC2SELU_A :: CCCTL_01_CC2SELU_SEL_CCU0) } # [doc = "SEL_CCU1"] # [inline (always)] pub fn ccctl_01_cc2selu_sel_ccu1 (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CC2SELU_A :: CCCTL_01_CC2SELU_SEL_CCU1) } # [doc = "SEL_CCU2"] # [inline (always)] pub fn ccctl_01_cc2selu_sel_ccu2 (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CC2SELU_A :: CCCTL_01_CC2SELU_SEL_CCU2) } # [doc = "SEL_CCU3"] # [inline (always)] pub fn ccctl_01_cc2selu_sel_ccu3 (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CC2SELU_A :: CCCTL_01_CC2SELU_SEL_CCU3) } # [doc = "SEL_CCU4"] # [inline (always)] pub fn ccctl_01_cc2selu_sel_ccu4 (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CC2SELU_A :: CCCTL_01_CC2SELU_SEL_CCU4) } # [doc = "SEL_CCU5"] # [inline (always)] pub fn ccctl_01_cc2selu_sel_ccu5 (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CC2SELU_A :: CCCTL_01_CC2SELU_SEL_CCU5) } } # [doc = "Field `CCCTL_01_CCACTUPD` reader - CCACT shadow register Update Method This field controls how updates to the CCCACT shadow register are performed"] pub type CCCTL_01_CCACTUPD_R = crate :: FieldReader < CCCTL_01_CCACTUPD_A > ; # [doc = "CCACT shadow register Update Method This field controls how updates to the CCCACT shadow register are performed\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum CCCTL_01_CCACTUPD_A { # [doc = "0: IMMEDIATELY"] CCCTL_01_CCACTUPD_IMMEDIATELY = 0 , # [doc = "1: ZERO_EVT"] CCCTL_01_CCACTUPD_ZERO_EVT = 1 , # [doc = "2: COMPARE_DOWN_EVT"] CCCTL_01_CCACTUPD_COMPARE_DOWN_EVT = 2 , # [doc = "3: COMPARE_UP_EVT"] CCCTL_01_CCACTUPD_COMPARE_UP_EVT = 3 , # [doc = "4: ZERO_LOAD_EVT"] CCCTL_01_CCACTUPD_ZERO_LOAD_EVT = 4 , # [doc = "5: ZERO_RC_ZERO_EVT"] CCCTL_01_CCACTUPD_ZERO_RC_ZERO_EVT = 5 , # [doc = "6: TRIG"] CCCTL_01_CCACTUPD_TRIG = 6 , } impl From < CCCTL_01_CCACTUPD_A > for u8 { # [inline (always)] fn from (variant : CCCTL_01_CCACTUPD_A) -> Self { variant as _ } } impl crate :: FieldSpec for CCCTL_01_CCACTUPD_A { type Ux = u8 ; } impl CCCTL_01_CCACTUPD_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < CCCTL_01_CCACTUPD_A > { match self . bits { 0 => Some (CCCTL_01_CCACTUPD_A :: CCCTL_01_CCACTUPD_IMMEDIATELY) , 1 => Some (CCCTL_01_CCACTUPD_A :: CCCTL_01_CCACTUPD_ZERO_EVT) , 2 => Some (CCCTL_01_CCACTUPD_A :: CCCTL_01_CCACTUPD_COMPARE_DOWN_EVT) , 3 => Some (CCCTL_01_CCACTUPD_A :: CCCTL_01_CCACTUPD_COMPARE_UP_EVT) , 4 => Some (CCCTL_01_CCACTUPD_A :: CCCTL_01_CCACTUPD_ZERO_LOAD_EVT) , 5 => Some (CCCTL_01_CCACTUPD_A :: CCCTL_01_CCACTUPD_ZERO_RC_ZERO_EVT) , 6 => Some (CCCTL_01_CCACTUPD_A :: CCCTL_01_CCACTUPD_TRIG) , _ => None , } } # [doc = "IMMEDIATELY"] # [inline (always)] pub fn is_ccctl_01_ccactupd_immediately (& self) -> bool { * self == CCCTL_01_CCACTUPD_A :: CCCTL_01_CCACTUPD_IMMEDIATELY } # [doc = "ZERO_EVT"] # [inline (always)] pub fn is_ccctl_01_ccactupd_zero_evt (& self) -> bool { * self == CCCTL_01_CCACTUPD_A :: CCCTL_01_CCACTUPD_ZERO_EVT } # [doc = "COMPARE_DOWN_EVT"] # [inline (always)] pub fn is_ccctl_01_ccactupd_compare_down_evt (& self) -> bool { * self == CCCTL_01_CCACTUPD_A :: CCCTL_01_CCACTUPD_COMPARE_DOWN_EVT } # [doc = "COMPARE_UP_EVT"] # [inline (always)] pub fn is_ccctl_01_ccactupd_compare_up_evt (& self) -> bool { * self == CCCTL_01_CCACTUPD_A :: CCCTL_01_CCACTUPD_COMPARE_UP_EVT } # [doc = "ZERO_LOAD_EVT"] # [inline (always)] pub fn is_ccctl_01_ccactupd_zero_load_evt (& self) -> bool { * self == CCCTL_01_CCACTUPD_A :: CCCTL_01_CCACTUPD_ZERO_LOAD_EVT } # [doc = "ZERO_RC_ZERO_EVT"] # [inline (always)] pub fn is_ccctl_01_ccactupd_zero_rc_zero_evt (& self) -> bool { * self == CCCTL_01_CCACTUPD_A :: CCCTL_01_CCACTUPD_ZERO_RC_ZERO_EVT } # [doc = "TRIG"] # [inline (always)] pub fn is_ccctl_01_ccactupd_trig (& self) -> bool { * self == CCCTL_01_CCACTUPD_A :: CCCTL_01_CCACTUPD_TRIG } } # [doc = "Field `CCCTL_01_CCACTUPD` writer - CCACT shadow register Update Method This field controls how updates to the CCCACT shadow register are performed"] pub type CCCTL_01_CCACTUPD_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 3 , O , CCCTL_01_CCACTUPD_A > ; impl < 'a , REG , const O : u8 > CCCTL_01_CCACTUPD_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "IMMEDIATELY"] # [inline (always)] pub fn ccctl_01_ccactupd_immediately (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CCACTUPD_A :: CCCTL_01_CCACTUPD_IMMEDIATELY) } # [doc = "ZERO_EVT"] # [inline (always)] pub fn ccctl_01_ccactupd_zero_evt (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CCACTUPD_A :: CCCTL_01_CCACTUPD_ZERO_EVT) } # [doc = "COMPARE_DOWN_EVT"] # [inline (always)] pub fn ccctl_01_ccactupd_compare_down_evt (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CCACTUPD_A :: CCCTL_01_CCACTUPD_COMPARE_DOWN_EVT) } # [doc = "COMPARE_UP_EVT"] # [inline (always)] pub fn ccctl_01_ccactupd_compare_up_evt (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CCACTUPD_A :: CCCTL_01_CCACTUPD_COMPARE_UP_EVT) } # [doc = "ZERO_LOAD_EVT"] # [inline (always)] pub fn ccctl_01_ccactupd_zero_load_evt (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CCACTUPD_A :: CCCTL_01_CCACTUPD_ZERO_LOAD_EVT) } # [doc = "ZERO_RC_ZERO_EVT"] # [inline (always)] pub fn ccctl_01_ccactupd_zero_rc_zero_evt (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CCACTUPD_A :: CCCTL_01_CCACTUPD_ZERO_RC_ZERO_EVT) } # [doc = "TRIG"] # [inline (always)] pub fn ccctl_01_ccactupd_trig (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CCACTUPD_A :: CCCTL_01_CCACTUPD_TRIG) } } # [doc = "Field `CCCTL_01_CC2SELD` reader - Selects the source second CCD event."] pub type CCCTL_01_CC2SELD_R = crate :: FieldReader < CCCTL_01_CC2SELD_A > ; # [doc = "Selects the source second CCD event.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum CCCTL_01_CC2SELD_A { # [doc = "0: SEL_CCD0"] CCCTL_01_CC2SELD_SEL_CCD0 = 0 , # [doc = "1: SEL_CCD1"] CCCTL_01_CC2SELD_SEL_CCD1 = 1 , # [doc = "2: SEL_CCD2"] CCCTL_01_CC2SELD_SEL_CCD2 = 2 , # [doc = "3: SEL_CCD3"] CCCTL_01_CC2SELD_SEL_CCD3 = 3 , # [doc = "4: SEL_CCD4"] CCCTL_01_CC2SELD_SEL_CCD4 = 4 , # [doc = "5: SEL_CCD5"] CCCTL_01_CC2SELD_SEL_CCD5 = 5 , } impl From < CCCTL_01_CC2SELD_A > for u8 { # [inline (always)] fn from (variant : CCCTL_01_CC2SELD_A) -> Self { variant as _ } } impl crate :: FieldSpec for CCCTL_01_CC2SELD_A { type Ux = u8 ; } impl CCCTL_01_CC2SELD_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < CCCTL_01_CC2SELD_A > { match self . bits { 0 => Some (CCCTL_01_CC2SELD_A :: CCCTL_01_CC2SELD_SEL_CCD0) , 1 => Some (CCCTL_01_CC2SELD_A :: CCCTL_01_CC2SELD_SEL_CCD1) , 2 => Some (CCCTL_01_CC2SELD_A :: CCCTL_01_CC2SELD_SEL_CCD2) , 3 => Some (CCCTL_01_CC2SELD_A :: CCCTL_01_CC2SELD_SEL_CCD3) , 4 => Some (CCCTL_01_CC2SELD_A :: CCCTL_01_CC2SELD_SEL_CCD4) , 5 => Some (CCCTL_01_CC2SELD_A :: CCCTL_01_CC2SELD_SEL_CCD5) , _ => None , } } # [doc = "SEL_CCD0"] # [inline (always)] pub fn is_ccctl_01_cc2seld_sel_ccd0 (& self) -> bool { * self == CCCTL_01_CC2SELD_A :: CCCTL_01_CC2SELD_SEL_CCD0 } # [doc = "SEL_CCD1"] # [inline (always)] pub fn is_ccctl_01_cc2seld_sel_ccd1 (& self) -> bool { * self == CCCTL_01_CC2SELD_A :: CCCTL_01_CC2SELD_SEL_CCD1 } # [doc = "SEL_CCD2"] # [inline (always)] pub fn is_ccctl_01_cc2seld_sel_ccd2 (& self) -> bool { * self == CCCTL_01_CC2SELD_A :: CCCTL_01_CC2SELD_SEL_CCD2 } # [doc = "SEL_CCD3"] # [inline (always)] pub fn is_ccctl_01_cc2seld_sel_ccd3 (& self) -> bool { * self == CCCTL_01_CC2SELD_A :: CCCTL_01_CC2SELD_SEL_CCD3 } # [doc = "SEL_CCD4"] # [inline (always)] pub fn is_ccctl_01_cc2seld_sel_ccd4 (& self) -> bool { * self == CCCTL_01_CC2SELD_A :: CCCTL_01_CC2SELD_SEL_CCD4 } # [doc = "SEL_CCD5"] # [inline (always)] pub fn is_ccctl_01_cc2seld_sel_ccd5 (& self) -> bool { * self == CCCTL_01_CC2SELD_A :: CCCTL_01_CC2SELD_SEL_CCD5 } } # [doc = "Field `CCCTL_01_CC2SELD` writer - Selects the source second CCD event."] pub type CCCTL_01_CC2SELD_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 3 , O , CCCTL_01_CC2SELD_A > ; impl < 'a , REG , const O : u8 > CCCTL_01_CC2SELD_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "SEL_CCD0"] # [inline (always)] pub fn ccctl_01_cc2seld_sel_ccd0 (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CC2SELD_A :: CCCTL_01_CC2SELD_SEL_CCD0) } # [doc = "SEL_CCD1"] # [inline (always)] pub fn ccctl_01_cc2seld_sel_ccd1 (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CC2SELD_A :: CCCTL_01_CC2SELD_SEL_CCD1) } # [doc = "SEL_CCD2"] # [inline (always)] pub fn ccctl_01_cc2seld_sel_ccd2 (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CC2SELD_A :: CCCTL_01_CC2SELD_SEL_CCD2) } # [doc = "SEL_CCD3"] # [inline (always)] pub fn ccctl_01_cc2seld_sel_ccd3 (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CC2SELD_A :: CCCTL_01_CC2SELD_SEL_CCD3) } # [doc = "SEL_CCD4"] # [inline (always)] pub fn ccctl_01_cc2seld_sel_ccd4 (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CC2SELD_A :: CCCTL_01_CC2SELD_SEL_CCD4) } # [doc = "SEL_CCD5"] # [inline (always)] pub fn ccctl_01_cc2seld_sel_ccd5 (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CC2SELD_A :: CCCTL_01_CC2SELD_SEL_CCD5) } } impl R { # [doc = "Bits 0:2 - Capture Condition. #br# Specifies the condition that generates a capture pulse. 4h-Fh = Reserved"] # [inline (always)] pub fn ccctl_01_ccond (& self) -> CCCTL_01_CCOND_R { CCCTL_01_CCOND_R :: new ((self . bits & 7) as u8) } # [doc = "Bits 4:6 - Advance Condition. #br# Specifies the condition that generates an advance pulse. 6h-Fh = Reserved"] # [inline (always)] pub fn ccctl_01_acond (& self) -> CCCTL_01_ACOND_R { CCCTL_01_ACOND_R :: new (((self . bits >> 4) & 7) as u8) } # [doc = "Bits 8:10 - Load Condition. #br# Specifies the condition that generates a load pulse. 4h-Fh = Reserved"] # [inline (always)] pub fn ccctl_01_lcond (& self) -> CCCTL_01_LCOND_R { CCCTL_01_LCOND_R :: new (((self . bits >> 8) & 7) as u8) } # [doc = "Bits 12:14 - Zero Condition. #br# This field specifies the condition that generates a zero pulse. 4h-Fh = Reserved"] # [inline (always)] pub fn ccctl_01_zcond (& self) -> CCCTL_01_ZCOND_R { CCCTL_01_ZCOND_R :: new (((self . bits >> 12) & 7) as u8) } # [doc = "Bit 17 - Capture or Compare. #br# Specifies whether the corresponding CC register is used as a capture register or a compare register (never both)."] # [inline (always)] pub fn ccctl_01_coc (& self) -> CCCTL_01_COC_R { CCCTL_01_COC_R :: new (((self . bits >> 17) & 1) != 0) } # [doc = "Bits 18:20 - Capture and Compare Update Method This field controls how updates to the pipelined capture and compare register are performed (when operating in compare mode, COC=0)."] # [inline (always)] pub fn ccctl_01_ccupd (& self) -> CCCTL_01_CCUPD_R { CCCTL_01_CCUPD_R :: new (((self . bits >> 18) & 7) as u8) } # [doc = "Bits 22:24 - Selects the source second CCU event."] # [inline (always)] pub fn ccctl_01_cc2selu (& self) -> CCCTL_01_CC2SELU_R { CCCTL_01_CC2SELU_R :: new (((self . bits >> 22) & 7) as u8) } # [doc = "Bits 26:28 - CCACT shadow register Update Method This field controls how updates to the CCCACT shadow register are performed"] # [inline (always)] pub fn ccctl_01_ccactupd (& self) -> CCCTL_01_CCACTUPD_R { CCCTL_01_CCACTUPD_R :: new (((self . bits >> 26) & 7) as u8) } # [doc = "Bits 29:31 - Selects the source second CCD event."] # [inline (always)] pub fn ccctl_01_cc2seld (& self) -> CCCTL_01_CC2SELD_R { CCCTL_01_CC2SELD_R :: new (((self . bits >> 29) & 7) as u8) } } impl W { # [doc = "Bits 0:2 - Capture Condition. #br# Specifies the condition that generates a capture pulse. 4h-Fh = Reserved"] # [inline (always)] # [must_use] pub fn ccctl_01_ccond (& mut self) -> CCCTL_01_CCOND_W < CCCTL_01_SPEC , 0 > { CCCTL_01_CCOND_W :: new (self) } # [doc = "Bits 4:6 - Advance Condition. #br# Specifies the condition that generates an advance pulse. 6h-Fh = Reserved"] # [inline (always)] # [must_use] pub fn ccctl_01_acond (& mut self) -> CCCTL_01_ACOND_W < CCCTL_01_SPEC , 4 > { CCCTL_01_ACOND_W :: new (self) } # [doc = "Bits 8:10 - Load Condition. #br# Specifies the condition that generates a load pulse. 4h-Fh = Reserved"] # [inline (always)] # [must_use] pub fn ccctl_01_lcond (& mut self) -> CCCTL_01_LCOND_W < CCCTL_01_SPEC , 8 > { CCCTL_01_LCOND_W :: new (self) } # [doc = "Bits 12:14 - Zero Condition. #br# This field specifies the condition that generates a zero pulse. 4h-Fh = Reserved"] # [inline (always)] # [must_use] pub fn ccctl_01_zcond (& mut self) -> CCCTL_01_ZCOND_W < CCCTL_01_SPEC , 12 > { CCCTL_01_ZCOND_W :: new (self) } # [doc = "Bit 17 - Capture or Compare. #br# Specifies whether the corresponding CC register is used as a capture register or a compare register (never both)."] # [inline (always)] # [must_use] pub fn ccctl_01_coc (& mut self) -> CCCTL_01_COC_W < CCCTL_01_SPEC , 17 > { CCCTL_01_COC_W :: new (self) } # [doc = "Bits 18:20 - Capture and Compare Update Method This field controls how updates to the pipelined capture and compare register are performed (when operating in compare mode, COC=0)."] # [inline (always)] # [must_use] pub fn ccctl_01_ccupd (& mut self) -> CCCTL_01_CCUPD_W < CCCTL_01_SPEC , 18 > { CCCTL_01_CCUPD_W :: new (self) } # [doc = "Bits 22:24 - Selects the source second CCU event."] # [inline (always)] # [must_use] pub fn ccctl_01_cc2selu (& mut self) -> CCCTL_01_CC2SELU_W < CCCTL_01_SPEC , 22 > { CCCTL_01_CC2SELU_W :: new (self) } # [doc = "Bits 26:28 - CCACT shadow register Update Method This field controls how updates to the CCCACT shadow register are performed"] # [inline (always)] # [must_use] pub fn ccctl_01_ccactupd (& mut self) -> CCCTL_01_CCACTUPD_W <'_, CCCTL_01_SPEC , 26 > { CCCTL_01_CCACTUPD_W :: new (self) } # [doc = "Bits 29:31 - Selects the source second CCD event."] # [inline (always)] # [must_use] pub fn ccctl_01_cc2seld (& mut self) -> CCCTL_01_CC2SELD_W < CCCTL_01_SPEC , 29 > { CCCTL_01_CC2SELD_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Capture or Compare Control Registers\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ccctl_01::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ccctl_01::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CCCTL_01_SPEC ; impl crate :: RegisterSpec for CCCTL_01_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`ccctl_01::R`](R) reader structure"] impl crate :: Readable for CCCTL_01_SPEC { } # [doc = "`write(|w| ..)` method takes [`ccctl_01::W`](W) writer structure"] impl crate :: Writable for CCCTL_01_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets CCCTL_01[%s] [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/i2c0/sackctl.rs:1:13327 [INFO] [stdout] | [INFO] [stdout] 1 | ...pub fn sackctl_ackoval (& mut self) -> SACKCTL_ACKOVAL_W < SACKCTL_SPEC , 1 > { SACKCTL_ACKOVAL_W :: new (self) } # [doc = "Bit 2 - Wh... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `SACKCTL` reader"] pub type R = crate :: R < SACKCTL_SPEC > ; # [doc = "Register `SACKCTL` writer"] pub type W = crate :: W < SACKCTL_SPEC > ; # [doc = "Field `SACKCTL_ACKOEN` reader - I2C Slave ACK Override Enable"] pub type SACKCTL_ACKOEN_R = crate :: BitReader < SACKCTL_ACKOEN_A > ; # [doc = "I2C Slave ACK Override Enable\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum SACKCTL_ACKOEN_A { # [doc = "0: DISABLE"] SACKCTL_ACKOEN_DISABLE = 0 , # [doc = "1: ENABLE"] SACKCTL_ACKOEN_ENABLE = 1 , } impl From < SACKCTL_ACKOEN_A > for bool { # [inline (always)] fn from (variant : SACKCTL_ACKOEN_A) -> Self { variant as u8 != 0 } } impl SACKCTL_ACKOEN_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> SACKCTL_ACKOEN_A { match self . bits { false => SACKCTL_ACKOEN_A :: SACKCTL_ACKOEN_DISABLE , true => SACKCTL_ACKOEN_A :: SACKCTL_ACKOEN_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_sackctl_ackoen_disable (& self) -> bool { * self == SACKCTL_ACKOEN_A :: SACKCTL_ACKOEN_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_sackctl_ackoen_enable (& self) -> bool { * self == SACKCTL_ACKOEN_A :: SACKCTL_ACKOEN_ENABLE } } # [doc = "Field `SACKCTL_ACKOEN` writer - I2C Slave ACK Override Enable"] pub type SACKCTL_ACKOEN_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , SACKCTL_ACKOEN_A > ; impl < 'a , REG , const O : u8 > SACKCTL_ACKOEN_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn sackctl_ackoen_disable (self) -> & 'a mut crate :: W < REG > { self . variant (SACKCTL_ACKOEN_A :: SACKCTL_ACKOEN_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn sackctl_ackoen_enable (self) -> & 'a mut crate :: W < REG > { self . variant (SACKCTL_ACKOEN_A :: SACKCTL_ACKOEN_ENABLE) } } # [doc = "Field `SACKCTL_ACKOVAL` reader - I2C Slave ACK Override Value Note: for General Call this bit will be ignored if set to NACK and slave continues to receive data."] pub type SACKCTL_ACKOVAL_R = crate :: BitReader < SACKCTL_ACKOVAL_A > ; # [doc = "I2C Slave ACK Override Value Note: for General Call this bit will be ignored if set to NACK and slave continues to receive data.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum SACKCTL_ACKOVAL_A { # [doc = "0: DISABLE"] SACKCTL_ACKOVAL_DISABLE = 0 , # [doc = "1: ENABLE"] SACKCTL_ACKOVAL_ENABLE = 1 , } impl From < SACKCTL_ACKOVAL_A > for bool { # [inline (always)] fn from (variant : SACKCTL_ACKOVAL_A) -> Self { variant as u8 != 0 } } impl SACKCTL_ACKOVAL_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> SACKCTL_ACKOVAL_A { match self . bits { false => SACKCTL_ACKOVAL_A :: SACKCTL_ACKOVAL_DISABLE , true => SACKCTL_ACKOVAL_A :: SACKCTL_ACKOVAL_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_sackctl_ackoval_disable (& self) -> bool { * self == SACKCTL_ACKOVAL_A :: SACKCTL_ACKOVAL_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_sackctl_ackoval_enable (& self) -> bool { * self == SACKCTL_ACKOVAL_A :: SACKCTL_ACKOVAL_ENABLE } } # [doc = "Field `SACKCTL_ACKOVAL` writer - I2C Slave ACK Override Value Note: for General Call this bit will be ignored if set to NACK and slave continues to receive data."] pub type SACKCTL_ACKOVAL_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , SACKCTL_ACKOVAL_A > ; impl < 'a , REG , const O : u8 > SACKCTL_ACKOVAL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn sackctl_ackoval_disable (self) -> & 'a mut crate :: W < REG > { self . variant (SACKCTL_ACKOVAL_A :: SACKCTL_ACKOVAL_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn sackctl_ackoval_enable (self) -> & 'a mut crate :: W < REG > { self . variant (SACKCTL_ACKOVAL_A :: SACKCTL_ACKOVAL_ENABLE) } } # [doc = "Field `SACKCTL_ACKOEN_ON_START` reader - When set this bit will automatically turn on the Slave ACKOEN field following a Start Condition."] pub type SACKCTL_ACKOEN_ON_START_R = crate :: BitReader < SACKCTL_ACKOEN_ON_START_A > ; # [doc = "When set this bit will automatically turn on the Slave ACKOEN field following a Start Condition.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum SACKCTL_ACKOEN_ON_START_A { # [doc = "0: DISABLE"] SACKCTL_ACKOEN_ON_START_DISABLE = 0 , # [doc = "1: ENABLE"] SACKCTL_ACKOEN_ON_START_ENABLE = 1 , } impl From < SACKCTL_ACKOEN_ON_START_A > for bool { # [inline (always)] fn from (variant : SACKCTL_ACKOEN_ON_START_A) -> Self { variant as u8 != 0 } } impl SACKCTL_ACKOEN_ON_START_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> SACKCTL_ACKOEN_ON_START_A { match self . bits { false => SACKCTL_ACKOEN_ON_START_A :: SACKCTL_ACKOEN_ON_START_DISABLE , true => SACKCTL_ACKOEN_ON_START_A :: SACKCTL_ACKOEN_ON_START_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_sackctl_ackoen_on_start_disable (& self) -> bool { * self == SACKCTL_ACKOEN_ON_START_A :: SACKCTL_ACKOEN_ON_START_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_sackctl_ackoen_on_start_enable (& self) -> bool { * self == SACKCTL_ACKOEN_ON_START_A :: SACKCTL_ACKOEN_ON_START_ENABLE } } # [doc = "Field `SACKCTL_ACKOEN_ON_START` writer - When set this bit will automatically turn on the Slave ACKOEN field following a Start Condition."] pub type SACKCTL_ACKOEN_ON_START_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , SACKCTL_ACKOEN_ON_START_A > ; impl < 'a , REG , const O : u8 > SACKCTL_ACKOEN_ON_START_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn sackctl_ackoen_on_start_disable (self) -> & 'a mut crate :: W < REG > { self . variant (SACKCTL_ACKOEN_ON_START_A :: SACKCTL_ACKOEN_ON_START_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn sackctl_ackoen_on_start_enable (self) -> & 'a mut crate :: W < REG > { self . variant (SACKCTL_ACKOEN_ON_START_A :: SACKCTL_ACKOEN_ON_START_ENABLE) } } # [doc = "Field `SACKCTL_ACKOEN_ON_PECNEXT` reader - When set this bit will automatically turn on the Slave ACKOEN field following the ACK/NACK of the byte received just prior to the PEC byte. Note that when ACKOEN is set the PEC byte will not automatically be ACKed/NACKed by the State Machine and FW must perform this function by writing SLAVE_SACKCTL."] pub type SACKCTL_ACKOEN_ON_PECNEXT_R = crate :: BitReader < SACKCTL_ACKOEN_ON_PECNEXT_A > ; # [doc = "When set this bit will automatically turn on the Slave ACKOEN field following the ACK/NACK of the byte received just prior to the PEC byte. Note that when ACKOEN is set the PEC byte will not automatically be ACKed/NACKed by the State Machine and FW must perform this function by writing SLAVE_SACKCTL.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum SACKCTL_ACKOEN_ON_PECNEXT_A { # [doc = "0: DISABLE"] SACKCTL_ACKOEN_ON_PECNEXT_DISABLE = 0 , # [doc = "1: ENABLE"] SACKCTL_ACKOEN_ON_PECNEXT_ENABLE = 1 , } impl From < SACKCTL_ACKOEN_ON_PECNEXT_A > for bool { # [inline (always)] fn from (variant : SACKCTL_ACKOEN_ON_PECNEXT_A) -> Self { variant as u8 != 0 } } impl SACKCTL_ACKOEN_ON_PECNEXT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> SACKCTL_ACKOEN_ON_PECNEXT_A { match self . bits { false => SACKCTL_ACKOEN_ON_PECNEXT_A :: SACKCTL_ACKOEN_ON_PECNEXT_DISABLE , true => SACKCTL_ACKOEN_ON_PECNEXT_A :: SACKCTL_ACKOEN_ON_PECNEXT_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_sackctl_ackoen_on_pecnext_disable (& self) -> bool { * self == SACKCTL_ACKOEN_ON_PECNEXT_A :: SACKCTL_ACKOEN_ON_PECNEXT_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_sackctl_ackoen_on_pecnext_enable (& self) -> bool { * self == SACKCTL_ACKOEN_ON_PECNEXT_A :: SACKCTL_ACKOEN_ON_PECNEXT_ENABLE } } # [doc = "Field `SACKCTL_ACKOEN_ON_PECNEXT` writer - When set this bit will automatically turn on the Slave ACKOEN field following the ACK/NACK of the byte received just prior to the PEC byte. Note that when ACKOEN is set the PEC byte will not automatically be ACKed/NACKed by the State Machine and FW must perform this function by writing SLAVE_SACKCTL."] pub type SACKCTL_ACKOEN_ON_PECNEXT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , SACKCTL_ACKOEN_ON_PECNEXT_A > ; impl < 'a , REG , const O : u8 > SACKCTL_ACKOEN_ON_PECNEXT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn sackctl_ackoen_on_pecnext_disable (self) -> & 'a mut crate :: W < REG > { self . variant (SACKCTL_ACKOEN_ON_PECNEXT_A :: SACKCTL_ACKOEN_ON_PECNEXT_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn sackctl_ackoen_on_pecnext_enable (self) -> & 'a mut crate :: W < REG > { self . variant (SACKCTL_ACKOEN_ON_PECNEXT_A :: SACKCTL_ACKOEN_ON_PECNEXT_ENABLE) } } # [doc = "Field `SACKCTL_ACKOEN_ON_PECDONE` reader - When set this bit will automatically turn on the Slave ACKOEN field following the ACK/NACK of the received PEC byte."] pub type SACKCTL_ACKOEN_ON_PECDONE_R = crate :: BitReader < SACKCTL_ACKOEN_ON_PECDONE_A > ; # [doc = "When set this bit will automatically turn on the Slave ACKOEN field following the ACK/NACK of the received PEC byte.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum SACKCTL_ACKOEN_ON_PECDONE_A { # [doc = "0: DISABLE"] SACKCTL_ACKOEN_ON_PECDONE_DISABLE = 0 , # [doc = "1: ENABLE"] SACKCTL_ACKOEN_ON_PECDONE_ENABLE = 1 , } impl From < SACKCTL_ACKOEN_ON_PECDONE_A > for bool { # [inline (always)] fn from (variant : SACKCTL_ACKOEN_ON_PECDONE_A) -> Self { variant as u8 != 0 } } impl SACKCTL_ACKOEN_ON_PECDONE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> SACKCTL_ACKOEN_ON_PECDONE_A { match self . bits { false => SACKCTL_ACKOEN_ON_PECDONE_A :: SACKCTL_ACKOEN_ON_PECDONE_DISABLE , true => SACKCTL_ACKOEN_ON_PECDONE_A :: SACKCTL_ACKOEN_ON_PECDONE_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_sackctl_ackoen_on_pecdone_disable (& self) -> bool { * self == SACKCTL_ACKOEN_ON_PECDONE_A :: SACKCTL_ACKOEN_ON_PECDONE_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_sackctl_ackoen_on_pecdone_enable (& self) -> bool { * self == SACKCTL_ACKOEN_ON_PECDONE_A :: SACKCTL_ACKOEN_ON_PECDONE_ENABLE } } # [doc = "Field `SACKCTL_ACKOEN_ON_PECDONE` writer - When set this bit will automatically turn on the Slave ACKOEN field following the ACK/NACK of the received PEC byte."] pub type SACKCTL_ACKOEN_ON_PECDONE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , SACKCTL_ACKOEN_ON_PECDONE_A > ; impl < 'a , REG , const O : u8 > SACKCTL_ACKOEN_ON_PECDONE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn sackctl_ackoen_on_pecdone_disable (self) -> & 'a mut crate :: W < REG > { self . variant (SACKCTL_ACKOEN_ON_PECDONE_A :: SACKCTL_ACKOEN_ON_PECDONE_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn sackctl_ackoen_on_pecdone_enable (self) -> & 'a mut crate :: W < REG > { self . variant (SACKCTL_ACKOEN_ON_PECDONE_A :: SACKCTL_ACKOEN_ON_PECDONE_ENABLE) } } impl R { # [doc = "Bit 0 - I2C Slave ACK Override Enable"] # [inline (always)] pub fn sackctl_ackoen (& self) -> SACKCTL_ACKOEN_R { SACKCTL_ACKOEN_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - I2C Slave ACK Override Value Note: for General Call this bit will be ignored if set to NACK and slave continues to receive data."] # [inline (always)] pub fn sackctl_ackoval (& self) -> SACKCTL_ACKOVAL_R { SACKCTL_ACKOVAL_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - When set this bit will automatically turn on the Slave ACKOEN field following a Start Condition."] # [inline (always)] pub fn sackctl_ackoen_on_start (& self) -> SACKCTL_ACKOEN_ON_START_R { SACKCTL_ACKOEN_ON_START_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - When set this bit will automatically turn on the Slave ACKOEN field following the ACK/NACK of the byte received just prior to the PEC byte. Note that when ACKOEN is set the PEC byte will not automatically be ACKed/NACKed by the State Machine and FW must perform this function by writing SLAVE_SACKCTL."] # [inline (always)] pub fn sackctl_ackoen_on_pecnext (& self) -> SACKCTL_ACKOEN_ON_PECNEXT_R { SACKCTL_ACKOEN_ON_PECNEXT_R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - When set this bit will automatically turn on the Slave ACKOEN field following the ACK/NACK of the received PEC byte."] # [inline (always)] pub fn sackctl_ackoen_on_pecdone (& self) -> SACKCTL_ACKOEN_ON_PECDONE_R { SACKCTL_ACKOEN_ON_PECDONE_R :: new (((self . bits >> 4) & 1) != 0) } } impl W { # [doc = "Bit 0 - I2C Slave ACK Override Enable"] # [inline (always)] # [must_use] pub fn sackctl_ackoen (& mut self) -> SACKCTL_ACKOEN_W < SACKCTL_SPEC , 0 > { SACKCTL_ACKOEN_W :: new (self) } # [doc = "Bit 1 - I2C Slave ACK Override Value Note: for General Call this bit will be ignored if set to NACK and slave continues to receive data."] # [inline (always)] # [must_use] pub fn sackctl_ackoval (& mut self) -> SACKCTL_ACKOVAL_W <'_, SACKCTL_SPEC , 1 > { SACKCTL_ACKOVAL_W :: new (self) } # [doc = "Bit 2 - When set this bit will automatically turn on the Slave ACKOEN field following a Start Condition."] # [inline (always)] # [must_use] pub fn sackctl_ackoen_on_start (& mut self) -> SACKCTL_ACKOEN_ON_START_W < SACKCTL_SPEC , 2 > { SACKCTL_ACKOEN_ON_START_W :: new (self) } # [doc = "Bit 3 - When set this bit will automatically turn on the Slave ACKOEN field following the ACK/NACK of the byte received just prior to the PEC byte. Note that when ACKOEN is set the PEC byte will not automatically be ACKed/NACKed by the State Machine and FW must perform this function by writing SLAVE_SACKCTL."] # [inline (always)] # [must_use] pub fn sackctl_ackoen_on_pecnext (& mut self) -> SACKCTL_ACKOEN_ON_PECNEXT_W < SACKCTL_SPEC , 3 > { SACKCTL_ACKOEN_ON_PECNEXT_W :: new (self) } # [doc = "Bit 4 - When set this bit will automatically turn on the Slave ACKOEN field following the ACK/NACK of the received PEC byte."] # [inline (always)] # [must_use] pub fn sackctl_ackoen_on_pecdone (& mut self) -> SACKCTL_ACKOEN_ON_PECDONE_W < SACKCTL_SPEC , 4 > { SACKCTL_ACKOEN_ON_PECDONE_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "I2C Slave ACK Control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sackctl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sackctl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct SACKCTL_SPEC ; impl crate :: RegisterSpec for SACKCTL_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`sackctl::R`](R) reader structure"] impl crate :: Readable for SACKCTL_SPEC { } # [doc = "`write(|w| ..)` method takes [`sackctl::W`](W) writer structure"] impl crate :: Writable for SACKCTL_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets SACKCTL to value 0"] impl crate :: Resettable for SACKCTL_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/opa0/rstctl.rs:1:3649 [INFO] [stdout] | [INFO] [stdout] 1 | ...t_use] pub fn rstctl_key (& mut self) -> RSTCTL_KEY_W < RSTCTL_SPEC , 24 > { RSTCTL_KEY_W :: new (self) } # [doc = r" Writes raw bits ... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `RSTCTL` writer"] pub type W = crate :: W < RSTCTL_SPEC > ; # [doc = "Assert reset to the peripheral\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum RSTCTL_RESETASSERT_AW { # [doc = "0: NOP"] RSTCTL_RESETASSERT_NOP = 0 , # [doc = "1: ASSERT"] RSTCTL_RESETASSERT_ASSERT = 1 , } impl From < RSTCTL_RESETASSERT_AW > for bool { # [inline (always)] fn from (variant : RSTCTL_RESETASSERT_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `RSTCTL_RESETASSERT` writer - Assert reset to the peripheral"] pub type RSTCTL_RESETASSERT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , RSTCTL_RESETASSERT_AW > ; impl < 'a , REG , const O : u8 > RSTCTL_RESETASSERT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NOP"] # [inline (always)] pub fn rstctl_resetassert_nop (self) -> & 'a mut crate :: W < REG > { self . variant (RSTCTL_RESETASSERT_AW :: RSTCTL_RESETASSERT_NOP) } # [doc = "ASSERT"] # [inline (always)] pub fn rstctl_resetassert_assert (self) -> & 'a mut crate :: W < REG > { self . variant (RSTCTL_RESETASSERT_AW :: RSTCTL_RESETASSERT_ASSERT) } } # [doc = "Clear the RESETSTKY bit in the STAT register\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum RSTCTL_RESETSTKYCLR_AW { # [doc = "0: NOP"] RSTCTL_RESETSTKYCLR_NOP = 0 , # [doc = "1: CLR"] RSTCTL_RESETSTKYCLR_CLR = 1 , } impl From < RSTCTL_RESETSTKYCLR_AW > for bool { # [inline (always)] fn from (variant : RSTCTL_RESETSTKYCLR_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `RSTCTL_RESETSTKYCLR` writer - Clear the RESETSTKY bit in the STAT register"] pub type RSTCTL_RESETSTKYCLR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , RSTCTL_RESETSTKYCLR_AW > ; impl < 'a , REG , const O : u8 > RSTCTL_RESETSTKYCLR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NOP"] # [inline (always)] pub fn rstctl_resetstkyclr_nop (self) -> & 'a mut crate :: W < REG > { self . variant (RSTCTL_RESETSTKYCLR_AW :: RSTCTL_RESETSTKYCLR_NOP) } # [doc = "CLR"] # [inline (always)] pub fn rstctl_resetstkyclr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (RSTCTL_RESETSTKYCLR_AW :: RSTCTL_RESETSTKYCLR_CLR) } } # [doc = "Unlock key\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum RSTCTL_KEY_AW { # [doc = "177: _TO_UNLOCK_W_"] RSTCTL_KEY_UNLOCK_W = 177 , } impl From < RSTCTL_KEY_AW > for u8 { # [inline (always)] fn from (variant : RSTCTL_KEY_AW) -> Self { variant as _ } } impl crate :: FieldSpec for RSTCTL_KEY_AW { type Ux = u8 ; } # [doc = "Field `RSTCTL_KEY` writer - Unlock key"] pub type RSTCTL_KEY_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 8 , O , RSTCTL_KEY_AW > ; impl < 'a , REG , const O : u8 > RSTCTL_KEY_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "_TO_UNLOCK_W_"] # [inline (always)] pub fn rstctl_key_unlock_w (self) -> & 'a mut crate :: W < REG > { self . variant (RSTCTL_KEY_AW :: RSTCTL_KEY_UNLOCK_W) } } impl W { # [doc = "Bit 0 - Assert reset to the peripheral"] # [inline (always)] # [must_use] pub fn rstctl_resetassert (& mut self) -> RSTCTL_RESETASSERT_W < RSTCTL_SPEC , 0 > { RSTCTL_RESETASSERT_W :: new (self) } # [doc = "Bit 1 - Clear the RESETSTKY bit in the STAT register"] # [inline (always)] # [must_use] pub fn rstctl_resetstkyclr (& mut self) -> RSTCTL_RESETSTKYCLR_W < RSTCTL_SPEC , 1 > { RSTCTL_RESETSTKYCLR_W :: new (self) } # [doc = "Bits 24:31 - Unlock key"] # [inline (always)] # [must_use] pub fn rstctl_key (& mut self) -> RSTCTL_KEY_W <'_, RSTCTL_SPEC , 24 > { RSTCTL_KEY_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Reset Control\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rstctl::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct RSTCTL_SPEC ; impl crate :: RegisterSpec for RSTCTL_SPEC { type Ux = u32 ; } # [doc = "`write(|w| ..)` method takes [`rstctl::W`](W) writer structure"] impl crate :: Writable for RSTCTL_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets RSTCTL to value 0"] impl crate :: Resettable for RSTCTL_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/cpuss/ctl.rs:1:8102 [INFO] [stdout] | [INFO] [stdout] 1 | ...[must_use] pub fn ctl_liten (& mut self) -> CTL_LITEN_W < CTL_SPEC , 2 > { CTL_LITEN_W :: new (self) } # [doc = r" Writes raw bits to ... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `CTL` reader"] pub type R = crate :: R < CTL_SPEC > ; # [doc = "Register `CTL` writer"] pub type W = crate :: W < CTL_SPEC > ; # [doc = "Field `CTL_PREFETCH` reader - Used to enable/disable instruction prefetch to Flash."] pub type CTL_PREFETCH_R = crate :: BitReader < CTL_PREFETCH_A > ; # [doc = "Used to enable/disable instruction prefetch to Flash.\n\nValue on reset: 1"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CTL_PREFETCH_A { # [doc = "0: DISABLE"] CTL_PREFETCH_DISABLE = 0 , # [doc = "1: ENABLE"] CTL_PREFETCH_ENABLE = 1 , } impl From < CTL_PREFETCH_A > for bool { # [inline (always)] fn from (variant : CTL_PREFETCH_A) -> Self { variant as u8 != 0 } } impl CTL_PREFETCH_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CTL_PREFETCH_A { match self . bits { false => CTL_PREFETCH_A :: CTL_PREFETCH_DISABLE , true => CTL_PREFETCH_A :: CTL_PREFETCH_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_ctl_prefetch_disable (& self) -> bool { * self == CTL_PREFETCH_A :: CTL_PREFETCH_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_ctl_prefetch_enable (& self) -> bool { * self == CTL_PREFETCH_A :: CTL_PREFETCH_ENABLE } } # [doc = "Field `CTL_PREFETCH` writer - Used to enable/disable instruction prefetch to Flash."] pub type CTL_PREFETCH_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL_PREFETCH_A > ; impl < 'a , REG , const O : u8 > CTL_PREFETCH_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn ctl_prefetch_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL_PREFETCH_A :: CTL_PREFETCH_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn ctl_prefetch_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL_PREFETCH_A :: CTL_PREFETCH_ENABLE) } } # [doc = "Field `CTL_ICACHE` reader - Used to enable/disable Instruction caching on flash access."] pub type CTL_ICACHE_R = crate :: BitReader < CTL_ICACHE_A > ; # [doc = "Used to enable/disable Instruction caching on flash access.\n\nValue on reset: 1"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CTL_ICACHE_A { # [doc = "0: DISABLE"] CTL_ICACHE_DISABLE = 0 , # [doc = "1: ENABLE"] CTL_ICACHE_ENABLE = 1 , } impl From < CTL_ICACHE_A > for bool { # [inline (always)] fn from (variant : CTL_ICACHE_A) -> Self { variant as u8 != 0 } } impl CTL_ICACHE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CTL_ICACHE_A { match self . bits { false => CTL_ICACHE_A :: CTL_ICACHE_DISABLE , true => CTL_ICACHE_A :: CTL_ICACHE_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_ctl_icache_disable (& self) -> bool { * self == CTL_ICACHE_A :: CTL_ICACHE_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_ctl_icache_enable (& self) -> bool { * self == CTL_ICACHE_A :: CTL_ICACHE_ENABLE } } # [doc = "Field `CTL_ICACHE` writer - Used to enable/disable Instruction caching on flash access."] pub type CTL_ICACHE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL_ICACHE_A > ; impl < 'a , REG , const O : u8 > CTL_ICACHE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn ctl_icache_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL_ICACHE_A :: CTL_ICACHE_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn ctl_icache_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL_ICACHE_A :: CTL_ICACHE_ENABLE) } } # [doc = "Field `CTL_LITEN` reader - Literal caching and prefetch enable. This bit is a subset of ICACHE/PREFETCH bit i.e. literal caching or literal prefetching will only happen if ICACHE or PREFETCH bits have been set respectively When enabled, the cache and prefetcher structures inside CPUSS will cache and prefetch literals When disabled, the cache and prefetcher structures inside CPUSS will not cache and prefetch literals"] pub type CTL_LITEN_R = crate :: BitReader < CTL_LITEN_A > ; # [doc = "Literal caching and prefetch enable. This bit is a subset of ICACHE/PREFETCH bit i.e. literal caching or literal prefetching will only happen if ICACHE or PREFETCH bits have been set respectively When enabled, the cache and prefetcher structures inside CPUSS will cache and prefetch literals When disabled, the cache and prefetcher structures inside CPUSS will not cache and prefetch literals\n\nValue on reset: 1"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CTL_LITEN_A { # [doc = "0: DISABLE"] CTL_LITEN_DISABLE = 0 , # [doc = "1: ENABLE"] CTL_LITEN_ENABLE = 1 , } impl From < CTL_LITEN_A > for bool { # [inline (always)] fn from (variant : CTL_LITEN_A) -> Self { variant as u8 != 0 } } impl CTL_LITEN_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CTL_LITEN_A { match self . bits { false => CTL_LITEN_A :: CTL_LITEN_DISABLE , true => CTL_LITEN_A :: CTL_LITEN_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_ctl_liten_disable (& self) -> bool { * self == CTL_LITEN_A :: CTL_LITEN_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_ctl_liten_enable (& self) -> bool { * self == CTL_LITEN_A :: CTL_LITEN_ENABLE } } # [doc = "Field `CTL_LITEN` writer - Literal caching and prefetch enable. This bit is a subset of ICACHE/PREFETCH bit i.e. literal caching or literal prefetching will only happen if ICACHE or PREFETCH bits have been set respectively When enabled, the cache and prefetcher structures inside CPUSS will cache and prefetch literals When disabled, the cache and prefetcher structures inside CPUSS will not cache and prefetch literals"] pub type CTL_LITEN_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL_LITEN_A > ; impl < 'a , REG , const O : u8 > CTL_LITEN_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn ctl_liten_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL_LITEN_A :: CTL_LITEN_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn ctl_liten_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL_LITEN_A :: CTL_LITEN_ENABLE) } } impl R { # [doc = "Bit 0 - Used to enable/disable instruction prefetch to Flash."] # [inline (always)] pub fn ctl_prefetch (& self) -> CTL_PREFETCH_R { CTL_PREFETCH_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - Used to enable/disable Instruction caching on flash access."] # [inline (always)] pub fn ctl_icache (& self) -> CTL_ICACHE_R { CTL_ICACHE_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - Literal caching and prefetch enable. This bit is a subset of ICACHE/PREFETCH bit i.e. literal caching or literal prefetching will only happen if ICACHE or PREFETCH bits have been set respectively When enabled, the cache and prefetcher structures inside CPUSS will cache and prefetch literals When disabled, the cache and prefetcher structures inside CPUSS will not cache and prefetch literals"] # [inline (always)] pub fn ctl_liten (& self) -> CTL_LITEN_R { CTL_LITEN_R :: new (((self . bits >> 2) & 1) != 0) } } impl W { # [doc = "Bit 0 - Used to enable/disable instruction prefetch to Flash."] # [inline (always)] # [must_use] pub fn ctl_prefetch (& mut self) -> CTL_PREFETCH_W < CTL_SPEC , 0 > { CTL_PREFETCH_W :: new (self) } # [doc = "Bit 1 - Used to enable/disable Instruction caching on flash access."] # [inline (always)] # [must_use] pub fn ctl_icache (& mut self) -> CTL_ICACHE_W < CTL_SPEC , 1 > { CTL_ICACHE_W :: new (self) } # [doc = "Bit 2 - Literal caching and prefetch enable. This bit is a subset of ICACHE/PREFETCH bit i.e. literal caching or literal prefetching will only happen if ICACHE or PREFETCH bits have been set respectively When enabled, the cache and prefetcher structures inside CPUSS will cache and prefetch literals When disabled, the cache and prefetcher structures inside CPUSS will not cache and prefetch literals"] # [inline (always)] # [must_use] pub fn ctl_liten (& mut self) -> CTL_LITEN_W <'_, CTL_SPEC , 2 > { CTL_LITEN_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Prefetch/Cache control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CTL_SPEC ; impl crate :: RegisterSpec for CTL_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`ctl::R`](R) reader structure"] impl crate :: Readable for CTL_SPEC { } # [doc = "`write(|w| ..)` method takes [`ctl::W`](W) writer structure"] impl crate :: Writable for CTL_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets CTL to value 0x07"] impl crate :: Resettable for CTL_SPEC { const RESET_VALUE : Self :: Ux = 0x07 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/i2c0/sctr.rs:1:24839 [INFO] [stdout] | [INFO] [stdout] 1 | ...pub fn sctr_sclkstretch (& mut self) -> SCTR_SCLKSTRETCH_W < SCTR_SPEC , 2 > { SCTR_SCLKSTRETCH_W :: new (self) } # [doc = "Bit 3 - Tx... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `SCTR` reader"] pub type R = crate :: R < SCTR_SPEC > ; # [doc = "Register `SCTR` writer"] pub type W = crate :: W < SCTR_SPEC > ; # [doc = "Field `SCTR_ACTIVE` reader - Device Active. Setting this bit enables the slave functionality."] pub type SCTR_ACTIVE_R = crate :: BitReader < SCTR_ACTIVE_A > ; # [doc = "Device Active. Setting this bit enables the slave functionality.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum SCTR_ACTIVE_A { # [doc = "0: DISABLE"] SCTR_ACTIVE_DISABLE = 0 , # [doc = "1: ENABLE"] SCTR_ACTIVE_ENABLE = 1 , } impl From < SCTR_ACTIVE_A > for bool { # [inline (always)] fn from (variant : SCTR_ACTIVE_A) -> Self { variant as u8 != 0 } } impl SCTR_ACTIVE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> SCTR_ACTIVE_A { match self . bits { false => SCTR_ACTIVE_A :: SCTR_ACTIVE_DISABLE , true => SCTR_ACTIVE_A :: SCTR_ACTIVE_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_sctr_active_disable (& self) -> bool { * self == SCTR_ACTIVE_A :: SCTR_ACTIVE_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_sctr_active_enable (& self) -> bool { * self == SCTR_ACTIVE_A :: SCTR_ACTIVE_ENABLE } } # [doc = "Field `SCTR_ACTIVE` writer - Device Active. Setting this bit enables the slave functionality."] pub type SCTR_ACTIVE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , SCTR_ACTIVE_A > ; impl < 'a , REG , const O : u8 > SCTR_ACTIVE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn sctr_active_disable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_ACTIVE_A :: SCTR_ACTIVE_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn sctr_active_enable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_ACTIVE_A :: SCTR_ACTIVE_ENABLE) } } # [doc = "Field `SCTR_GENCALL` reader - General call response enable. This bit is only available in UCBxI2COA0. Modify only when UCSWRST = 1. 0b = Do not respond to a general call 1b = Respond to a general call"] pub type SCTR_GENCALL_R = crate :: BitReader < SCTR_GENCALL_A > ; # [doc = "General call response enable. This bit is only available in UCBxI2COA0. Modify only when UCSWRST = 1. 0b = Do not respond to a general call 1b = Respond to a general call\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum SCTR_GENCALL_A { # [doc = "0: DISABLE"] SCTR_GENCALL_DISABLE = 0 , # [doc = "1: ENABLE"] SCTR_GENCALL_ENABLE = 1 , } impl From < SCTR_GENCALL_A > for bool { # [inline (always)] fn from (variant : SCTR_GENCALL_A) -> Self { variant as u8 != 0 } } impl SCTR_GENCALL_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> SCTR_GENCALL_A { match self . bits { false => SCTR_GENCALL_A :: SCTR_GENCALL_DISABLE , true => SCTR_GENCALL_A :: SCTR_GENCALL_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_sctr_gencall_disable (& self) -> bool { * self == SCTR_GENCALL_A :: SCTR_GENCALL_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_sctr_gencall_enable (& self) -> bool { * self == SCTR_GENCALL_A :: SCTR_GENCALL_ENABLE } } # [doc = "Field `SCTR_GENCALL` writer - General call response enable. This bit is only available in UCBxI2COA0. Modify only when UCSWRST = 1. 0b = Do not respond to a general call 1b = Respond to a general call"] pub type SCTR_GENCALL_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , SCTR_GENCALL_A > ; impl < 'a , REG , const O : u8 > SCTR_GENCALL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn sctr_gencall_disable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_GENCALL_A :: SCTR_GENCALL_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn sctr_gencall_enable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_GENCALL_A :: SCTR_GENCALL_ENABLE) } } # [doc = "Field `SCTR_SCLKSTRETCH` reader - Slave Clock Stretch Enable"] pub type SCTR_SCLKSTRETCH_R = crate :: BitReader < SCTR_SCLKSTRETCH_A > ; # [doc = "Slave Clock Stretch Enable\n\nValue on reset: 1"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum SCTR_SCLKSTRETCH_A { # [doc = "0: DISABLE"] SCTR_SCLKSTRETCH_DISABLE = 0 , # [doc = "1: ENABLE"] SCTR_SCLKSTRETCH_ENABLE = 1 , } impl From < SCTR_SCLKSTRETCH_A > for bool { # [inline (always)] fn from (variant : SCTR_SCLKSTRETCH_A) -> Self { variant as u8 != 0 } } impl SCTR_SCLKSTRETCH_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> SCTR_SCLKSTRETCH_A { match self . bits { false => SCTR_SCLKSTRETCH_A :: SCTR_SCLKSTRETCH_DISABLE , true => SCTR_SCLKSTRETCH_A :: SCTR_SCLKSTRETCH_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_sctr_sclkstretch_disable (& self) -> bool { * self == SCTR_SCLKSTRETCH_A :: SCTR_SCLKSTRETCH_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_sctr_sclkstretch_enable (& self) -> bool { * self == SCTR_SCLKSTRETCH_A :: SCTR_SCLKSTRETCH_ENABLE } } # [doc = "Field `SCTR_SCLKSTRETCH` writer - Slave Clock Stretch Enable"] pub type SCTR_SCLKSTRETCH_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , SCTR_SCLKSTRETCH_A > ; impl < 'a , REG , const O : u8 > SCTR_SCLKSTRETCH_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn sctr_sclkstretch_disable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_SCLKSTRETCH_A :: SCTR_SCLKSTRETCH_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn sctr_sclkstretch_enable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_SCLKSTRETCH_A :: SCTR_SCLKSTRETCH_ENABLE) } } # [doc = "Field `SCTR_TXEMPTY_ON_TREQ` reader - Tx Empty Interrupt on TREQ"] pub type SCTR_TXEMPTY_ON_TREQ_R = crate :: BitReader < SCTR_TXEMPTY_ON_TREQ_A > ; # [doc = "Tx Empty Interrupt on TREQ\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum SCTR_TXEMPTY_ON_TREQ_A { # [doc = "0: DISABLE"] SCTR_TXEMPTY_ON_TREQ_DISABLE = 0 , # [doc = "1: ENABLE"] SCTR_TXEMPTY_ON_TREQ_ENABLE = 1 , } impl From < SCTR_TXEMPTY_ON_TREQ_A > for bool { # [inline (always)] fn from (variant : SCTR_TXEMPTY_ON_TREQ_A) -> Self { variant as u8 != 0 } } impl SCTR_TXEMPTY_ON_TREQ_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> SCTR_TXEMPTY_ON_TREQ_A { match self . bits { false => SCTR_TXEMPTY_ON_TREQ_A :: SCTR_TXEMPTY_ON_TREQ_DISABLE , true => SCTR_TXEMPTY_ON_TREQ_A :: SCTR_TXEMPTY_ON_TREQ_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_sctr_txempty_on_treq_disable (& self) -> bool { * self == SCTR_TXEMPTY_ON_TREQ_A :: SCTR_TXEMPTY_ON_TREQ_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_sctr_txempty_on_treq_enable (& self) -> bool { * self == SCTR_TXEMPTY_ON_TREQ_A :: SCTR_TXEMPTY_ON_TREQ_ENABLE } } # [doc = "Field `SCTR_TXEMPTY_ON_TREQ` writer - Tx Empty Interrupt on TREQ"] pub type SCTR_TXEMPTY_ON_TREQ_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , SCTR_TXEMPTY_ON_TREQ_A > ; impl < 'a , REG , const O : u8 > SCTR_TXEMPTY_ON_TREQ_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn sctr_txempty_on_treq_disable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_TXEMPTY_ON_TREQ_A :: SCTR_TXEMPTY_ON_TREQ_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn sctr_txempty_on_treq_enable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_TXEMPTY_ON_TREQ_A :: SCTR_TXEMPTY_ON_TREQ_ENABLE) } } # [doc = "Field `SCTR_TXTRIG_TXMODE` reader - Tx Trigger when slave FSM is in Tx Mode"] pub type SCTR_TXTRIG_TXMODE_R = crate :: BitReader < SCTR_TXTRIG_TXMODE_A > ; # [doc = "Tx Trigger when slave FSM is in Tx Mode\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum SCTR_TXTRIG_TXMODE_A { # [doc = "0: DISABLE"] SCTR_TXTRIG_TXMODE_DISABLE = 0 , # [doc = "1: ENABLE"] SCTR_TXTRIG_TXMODE_ENABLE = 1 , } impl From < SCTR_TXTRIG_TXMODE_A > for bool { # [inline (always)] fn from (variant : SCTR_TXTRIG_TXMODE_A) -> Self { variant as u8 != 0 } } impl SCTR_TXTRIG_TXMODE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> SCTR_TXTRIG_TXMODE_A { match self . bits { false => SCTR_TXTRIG_TXMODE_A :: SCTR_TXTRIG_TXMODE_DISABLE , true => SCTR_TXTRIG_TXMODE_A :: SCTR_TXTRIG_TXMODE_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_sctr_txtrig_txmode_disable (& self) -> bool { * self == SCTR_TXTRIG_TXMODE_A :: SCTR_TXTRIG_TXMODE_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_sctr_txtrig_txmode_enable (& self) -> bool { * self == SCTR_TXTRIG_TXMODE_A :: SCTR_TXTRIG_TXMODE_ENABLE } } # [doc = "Field `SCTR_TXTRIG_TXMODE` writer - Tx Trigger when slave FSM is in Tx Mode"] pub type SCTR_TXTRIG_TXMODE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , SCTR_TXTRIG_TXMODE_A > ; impl < 'a , REG , const O : u8 > SCTR_TXTRIG_TXMODE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn sctr_txtrig_txmode_disable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_TXTRIG_TXMODE_A :: SCTR_TXTRIG_TXMODE_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn sctr_txtrig_txmode_enable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_TXTRIG_TXMODE_A :: SCTR_TXTRIG_TXMODE_ENABLE) } } # [doc = "Field `SCTR_TXWAIT_STALE_TXFIFO` reader - Tx transfer waits when stale data in Tx FIFO. This prevents stale bytes left in the TX FIFO from automatically being sent on the next I2C packet. Note: this should be used with TXEMPTY_ON_TREQ set to prevent the Slave State Machine from waiting for TX FIFO data without an interrupt notification when the FIFO data is stale."] pub type SCTR_TXWAIT_STALE_TXFIFO_R = crate :: BitReader < SCTR_TXWAIT_STALE_TXFIFO_A > ; # [doc = "Tx transfer waits when stale data in Tx FIFO. This prevents stale bytes left in the TX FIFO from automatically being sent on the next I2C packet. Note: this should be used with TXEMPTY_ON_TREQ set to prevent the Slave State Machine from waiting for TX FIFO data without an interrupt notification when the FIFO data is stale.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum SCTR_TXWAIT_STALE_TXFIFO_A { # [doc = "0: DISABLE"] SCTR_TXWAIT_STALE_TXFIFO_DISABLE = 0 , # [doc = "1: ENABLE"] SCTR_TXWAIT_STALE_TXFIFO_ENABLE = 1 , } impl From < SCTR_TXWAIT_STALE_TXFIFO_A > for bool { # [inline (always)] fn from (variant : SCTR_TXWAIT_STALE_TXFIFO_A) -> Self { variant as u8 != 0 } } impl SCTR_TXWAIT_STALE_TXFIFO_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> SCTR_TXWAIT_STALE_TXFIFO_A { match self . bits { false => SCTR_TXWAIT_STALE_TXFIFO_A :: SCTR_TXWAIT_STALE_TXFIFO_DISABLE , true => SCTR_TXWAIT_STALE_TXFIFO_A :: SCTR_TXWAIT_STALE_TXFIFO_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_sctr_txwait_stale_txfifo_disable (& self) -> bool { * self == SCTR_TXWAIT_STALE_TXFIFO_A :: SCTR_TXWAIT_STALE_TXFIFO_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_sctr_txwait_stale_txfifo_enable (& self) -> bool { * self == SCTR_TXWAIT_STALE_TXFIFO_A :: SCTR_TXWAIT_STALE_TXFIFO_ENABLE } } # [doc = "Field `SCTR_TXWAIT_STALE_TXFIFO` writer - Tx transfer waits when stale data in Tx FIFO. This prevents stale bytes left in the TX FIFO from automatically being sent on the next I2C packet. Note: this should be used with TXEMPTY_ON_TREQ set to prevent the Slave State Machine from waiting for TX FIFO data without an interrupt notification when the FIFO data is stale."] pub type SCTR_TXWAIT_STALE_TXFIFO_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , SCTR_TXWAIT_STALE_TXFIFO_A > ; impl < 'a , REG , const O : u8 > SCTR_TXWAIT_STALE_TXFIFO_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn sctr_txwait_stale_txfifo_disable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_TXWAIT_STALE_TXFIFO_A :: SCTR_TXWAIT_STALE_TXFIFO_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn sctr_txwait_stale_txfifo_enable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_TXWAIT_STALE_TXFIFO_A :: SCTR_TXWAIT_STALE_TXFIFO_ENABLE) } } # [doc = "Field `SCTR_RXFULL_ON_RREQ` reader - Rx full interrupt generated on RREQ condition as indicated in SSR"] pub type SCTR_RXFULL_ON_RREQ_R = crate :: BitReader < SCTR_RXFULL_ON_RREQ_A > ; # [doc = "Rx full interrupt generated on RREQ condition as indicated in SSR\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum SCTR_RXFULL_ON_RREQ_A { # [doc = "0: DISABLE"] SCTR_RXFULL_ON_RREQ_DISABLE = 0 , # [doc = "1: ENABLE"] SCTR_RXFULL_ON_RREQ_ENABLE = 1 , } impl From < SCTR_RXFULL_ON_RREQ_A > for bool { # [inline (always)] fn from (variant : SCTR_RXFULL_ON_RREQ_A) -> Self { variant as u8 != 0 } } impl SCTR_RXFULL_ON_RREQ_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> SCTR_RXFULL_ON_RREQ_A { match self . bits { false => SCTR_RXFULL_ON_RREQ_A :: SCTR_RXFULL_ON_RREQ_DISABLE , true => SCTR_RXFULL_ON_RREQ_A :: SCTR_RXFULL_ON_RREQ_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_sctr_rxfull_on_rreq_disable (& self) -> bool { * self == SCTR_RXFULL_ON_RREQ_A :: SCTR_RXFULL_ON_RREQ_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_sctr_rxfull_on_rreq_enable (& self) -> bool { * self == SCTR_RXFULL_ON_RREQ_A :: SCTR_RXFULL_ON_RREQ_ENABLE } } # [doc = "Field `SCTR_RXFULL_ON_RREQ` writer - Rx full interrupt generated on RREQ condition as indicated in SSR"] pub type SCTR_RXFULL_ON_RREQ_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , SCTR_RXFULL_ON_RREQ_A > ; impl < 'a , REG , const O : u8 > SCTR_RXFULL_ON_RREQ_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn sctr_rxfull_on_rreq_disable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_RXFULL_ON_RREQ_A :: SCTR_RXFULL_ON_RREQ_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn sctr_rxfull_on_rreq_enable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_RXFULL_ON_RREQ_A :: SCTR_RXFULL_ON_RREQ_ENABLE) } } # [doc = "Field `SCTR_EN_DEFHOSTADR` reader - Enable Default Host Address"] pub type SCTR_EN_DEFHOSTADR_R = crate :: BitReader < SCTR_EN_DEFHOSTADR_A > ; # [doc = "Enable Default Host Address\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum SCTR_EN_DEFHOSTADR_A { # [doc = "0: DISABLE"] SCTR_EN_DEFHOSTADR_DISABLE = 0 , # [doc = "1: ENABLE"] SCTR_EN_DEFHOSTADR_ENABLE = 1 , } impl From < SCTR_EN_DEFHOSTADR_A > for bool { # [inline (always)] fn from (variant : SCTR_EN_DEFHOSTADR_A) -> Self { variant as u8 != 0 } } impl SCTR_EN_DEFHOSTADR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> SCTR_EN_DEFHOSTADR_A { match self . bits { false => SCTR_EN_DEFHOSTADR_A :: SCTR_EN_DEFHOSTADR_DISABLE , true => SCTR_EN_DEFHOSTADR_A :: SCTR_EN_DEFHOSTADR_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_sctr_en_defhostadr_disable (& self) -> bool { * self == SCTR_EN_DEFHOSTADR_A :: SCTR_EN_DEFHOSTADR_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_sctr_en_defhostadr_enable (& self) -> bool { * self == SCTR_EN_DEFHOSTADR_A :: SCTR_EN_DEFHOSTADR_ENABLE } } # [doc = "Field `SCTR_EN_DEFHOSTADR` writer - Enable Default Host Address"] pub type SCTR_EN_DEFHOSTADR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , SCTR_EN_DEFHOSTADR_A > ; impl < 'a , REG , const O : u8 > SCTR_EN_DEFHOSTADR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn sctr_en_defhostadr_disable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_EN_DEFHOSTADR_A :: SCTR_EN_DEFHOSTADR_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn sctr_en_defhostadr_enable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_EN_DEFHOSTADR_A :: SCTR_EN_DEFHOSTADR_ENABLE) } } # [doc = "Field `SCTR_EN_ALRESPADR` reader - Enable Alert Response Address"] pub type SCTR_EN_ALRESPADR_R = crate :: BitReader < SCTR_EN_ALRESPADR_A > ; # [doc = "Enable Alert Response Address\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum SCTR_EN_ALRESPADR_A { # [doc = "0: DISABLE"] SCTR_EN_ALRESPADR_DISABLE = 0 , # [doc = "1: ENABLE"] SCTR_EN_ALRESPADR_ENABLE = 1 , } impl From < SCTR_EN_ALRESPADR_A > for bool { # [inline (always)] fn from (variant : SCTR_EN_ALRESPADR_A) -> Self { variant as u8 != 0 } } impl SCTR_EN_ALRESPADR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> SCTR_EN_ALRESPADR_A { match self . bits { false => SCTR_EN_ALRESPADR_A :: SCTR_EN_ALRESPADR_DISABLE , true => SCTR_EN_ALRESPADR_A :: SCTR_EN_ALRESPADR_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_sctr_en_alrespadr_disable (& self) -> bool { * self == SCTR_EN_ALRESPADR_A :: SCTR_EN_ALRESPADR_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_sctr_en_alrespadr_enable (& self) -> bool { * self == SCTR_EN_ALRESPADR_A :: SCTR_EN_ALRESPADR_ENABLE } } # [doc = "Field `SCTR_EN_ALRESPADR` writer - Enable Alert Response Address"] pub type SCTR_EN_ALRESPADR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , SCTR_EN_ALRESPADR_A > ; impl < 'a , REG , const O : u8 > SCTR_EN_ALRESPADR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn sctr_en_alrespadr_disable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_EN_ALRESPADR_A :: SCTR_EN_ALRESPADR_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn sctr_en_alrespadr_enable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_EN_ALRESPADR_A :: SCTR_EN_ALRESPADR_ENABLE) } } # [doc = "Field `SCTR_EN_DEFDEVADR` reader - Enable Deault device address"] pub type SCTR_EN_DEFDEVADR_R = crate :: BitReader < SCTR_EN_DEFDEVADR_A > ; # [doc = "Enable Deault device address\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum SCTR_EN_DEFDEVADR_A { # [doc = "0: DISABLE"] SCTR_EN_DEFDEVADR_DISABLE = 0 , # [doc = "1: ENABLE"] SCTR_EN_DEFDEVADR_ENABLE = 1 , } impl From < SCTR_EN_DEFDEVADR_A > for bool { # [inline (always)] fn from (variant : SCTR_EN_DEFDEVADR_A) -> Self { variant as u8 != 0 } } impl SCTR_EN_DEFDEVADR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> SCTR_EN_DEFDEVADR_A { match self . bits { false => SCTR_EN_DEFDEVADR_A :: SCTR_EN_DEFDEVADR_DISABLE , true => SCTR_EN_DEFDEVADR_A :: SCTR_EN_DEFDEVADR_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_sctr_en_defdevadr_disable (& self) -> bool { * self == SCTR_EN_DEFDEVADR_A :: SCTR_EN_DEFDEVADR_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_sctr_en_defdevadr_enable (& self) -> bool { * self == SCTR_EN_DEFDEVADR_A :: SCTR_EN_DEFDEVADR_ENABLE } } # [doc = "Field `SCTR_EN_DEFDEVADR` writer - Enable Deault device address"] pub type SCTR_EN_DEFDEVADR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , SCTR_EN_DEFDEVADR_A > ; impl < 'a , REG , const O : u8 > SCTR_EN_DEFDEVADR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn sctr_en_defdevadr_disable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_EN_DEFDEVADR_A :: SCTR_EN_DEFDEVADR_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn sctr_en_defdevadr_enable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_EN_DEFDEVADR_A :: SCTR_EN_DEFDEVADR_ENABLE) } } # [doc = "Field `SCTR_SWUEN` reader - Slave Wakeup Enable"] pub type SCTR_SWUEN_R = crate :: BitReader < SCTR_SWUEN_A > ; # [doc = "Slave Wakeup Enable\n\nValue on reset: 1"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum SCTR_SWUEN_A { # [doc = "0: DISABLE"] SCTR_SWUEN_DISABLE = 0 , # [doc = "1: ENABLE"] SCTR_SWUEN_ENABLE = 1 , } impl From < SCTR_SWUEN_A > for bool { # [inline (always)] fn from (variant : SCTR_SWUEN_A) -> Self { variant as u8 != 0 } } impl SCTR_SWUEN_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> SCTR_SWUEN_A { match self . bits { false => SCTR_SWUEN_A :: SCTR_SWUEN_DISABLE , true => SCTR_SWUEN_A :: SCTR_SWUEN_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_sctr_swuen_disable (& self) -> bool { * self == SCTR_SWUEN_A :: SCTR_SWUEN_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_sctr_swuen_enable (& self) -> bool { * self == SCTR_SWUEN_A :: SCTR_SWUEN_ENABLE } } # [doc = "Field `SCTR_SWUEN` writer - Slave Wakeup Enable"] pub type SCTR_SWUEN_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , SCTR_SWUEN_A > ; impl < 'a , REG , const O : u8 > SCTR_SWUEN_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn sctr_swuen_disable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_SWUEN_A :: SCTR_SWUEN_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn sctr_swuen_enable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_SWUEN_A :: SCTR_SWUEN_ENABLE) } } impl R { # [doc = "Bit 0 - Device Active. Setting this bit enables the slave functionality."] # [inline (always)] pub fn sctr_active (& self) -> SCTR_ACTIVE_R { SCTR_ACTIVE_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - General call response enable. This bit is only available in UCBxI2COA0. Modify only when UCSWRST = 1. 0b = Do not respond to a general call 1b = Respond to a general call"] # [inline (always)] pub fn sctr_gencall (& self) -> SCTR_GENCALL_R { SCTR_GENCALL_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - Slave Clock Stretch Enable"] # [inline (always)] pub fn sctr_sclkstretch (& self) -> SCTR_SCLKSTRETCH_R { SCTR_SCLKSTRETCH_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - Tx Empty Interrupt on TREQ"] # [inline (always)] pub fn sctr_txempty_on_treq (& self) -> SCTR_TXEMPTY_ON_TREQ_R { SCTR_TXEMPTY_ON_TREQ_R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - Tx Trigger when slave FSM is in Tx Mode"] # [inline (always)] pub fn sctr_txtrig_txmode (& self) -> SCTR_TXTRIG_TXMODE_R { SCTR_TXTRIG_TXMODE_R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - Tx transfer waits when stale data in Tx FIFO. This prevents stale bytes left in the TX FIFO from automatically being sent on the next I2C packet. Note: this should be used with TXEMPTY_ON_TREQ set to prevent the Slave State Machine from waiting for TX FIFO data without an interrupt notification when the FIFO data is stale."] # [inline (always)] pub fn sctr_txwait_stale_txfifo (& self) -> SCTR_TXWAIT_STALE_TXFIFO_R { SCTR_TXWAIT_STALE_TXFIFO_R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - Rx full interrupt generated on RREQ condition as indicated in SSR"] # [inline (always)] pub fn sctr_rxfull_on_rreq (& self) -> SCTR_RXFULL_ON_RREQ_R { SCTR_RXFULL_ON_RREQ_R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - Enable Default Host Address"] # [inline (always)] pub fn sctr_en_defhostadr (& self) -> SCTR_EN_DEFHOSTADR_R { SCTR_EN_DEFHOSTADR_R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - Enable Alert Response Address"] # [inline (always)] pub fn sctr_en_alrespadr (& self) -> SCTR_EN_ALRESPADR_R { SCTR_EN_ALRESPADR_R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - Enable Deault device address"] # [inline (always)] pub fn sctr_en_defdevadr (& self) -> SCTR_EN_DEFDEVADR_R { SCTR_EN_DEFDEVADR_R :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - Slave Wakeup Enable"] # [inline (always)] pub fn sctr_swuen (& self) -> SCTR_SWUEN_R { SCTR_SWUEN_R :: new (((self . bits >> 10) & 1) != 0) } } impl W { # [doc = "Bit 0 - Device Active. Setting this bit enables the slave functionality."] # [inline (always)] # [must_use] pub fn sctr_active (& mut self) -> SCTR_ACTIVE_W < SCTR_SPEC , 0 > { SCTR_ACTIVE_W :: new (self) } # [doc = "Bit 1 - General call response enable. This bit is only available in UCBxI2COA0. Modify only when UCSWRST = 1. 0b = Do not respond to a general call 1b = Respond to a general call"] # [inline (always)] # [must_use] pub fn sctr_gencall (& mut self) -> SCTR_GENCALL_W < SCTR_SPEC , 1 > { SCTR_GENCALL_W :: new (self) } # [doc = "Bit 2 - Slave Clock Stretch Enable"] # [inline (always)] # [must_use] pub fn sctr_sclkstretch (& mut self) -> SCTR_SCLKSTRETCH_W <'_, SCTR_SPEC , 2 > { SCTR_SCLKSTRETCH_W :: new (self) } # [doc = "Bit 3 - Tx Empty Interrupt on TREQ"] # [inline (always)] # [must_use] pub fn sctr_txempty_on_treq (& mut self) -> SCTR_TXEMPTY_ON_TREQ_W < SCTR_SPEC , 3 > { SCTR_TXEMPTY_ON_TREQ_W :: new (self) } # [doc = "Bit 4 - Tx Trigger when slave FSM is in Tx Mode"] # [inline (always)] # [must_use] pub fn sctr_txtrig_txmode (& mut self) -> SCTR_TXTRIG_TXMODE_W < SCTR_SPEC , 4 > { SCTR_TXTRIG_TXMODE_W :: new (self) } # [doc = "Bit 5 - Tx transfer waits when stale data in Tx FIFO. This prevents stale bytes left in the TX FIFO from automatically being sent on the next I2C packet. Note: this should be used with TXEMPTY_ON_TREQ set to prevent the Slave State Machine from waiting for TX FIFO data without an interrupt notification when the FIFO data is stale."] # [inline (always)] # [must_use] pub fn sctr_txwait_stale_txfifo (& mut self) -> SCTR_TXWAIT_STALE_TXFIFO_W < SCTR_SPEC , 5 > { SCTR_TXWAIT_STALE_TXFIFO_W :: new (self) } # [doc = "Bit 6 - Rx full interrupt generated on RREQ condition as indicated in SSR"] # [inline (always)] # [must_use] pub fn sctr_rxfull_on_rreq (& mut self) -> SCTR_RXFULL_ON_RREQ_W < SCTR_SPEC , 6 > { SCTR_RXFULL_ON_RREQ_W :: new (self) } # [doc = "Bit 7 - Enable Default Host Address"] # [inline (always)] # [must_use] pub fn sctr_en_defhostadr (& mut self) -> SCTR_EN_DEFHOSTADR_W < SCTR_SPEC , 7 > { SCTR_EN_DEFHOSTADR_W :: new (self) } # [doc = "Bit 8 - Enable Alert Response Address"] # [inline (always)] # [must_use] pub fn sctr_en_alrespadr (& mut self) -> SCTR_EN_ALRESPADR_W < SCTR_SPEC , 8 > { SCTR_EN_ALRESPADR_W :: new (self) } # [doc = "Bit 9 - Enable Deault device address"] # [inline (always)] # [must_use] pub fn sctr_en_defdevadr (& mut self) -> SCTR_EN_DEFDEVADR_W < SCTR_SPEC , 9 > { SCTR_EN_DEFDEVADR_W :: new (self) } # [doc = "Bit 10 - Slave Wakeup Enable"] # [inline (always)] # [must_use] pub fn sctr_swuen (& mut self) -> SCTR_SWUEN_W < SCTR_SPEC , 10 > { SCTR_SWUEN_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "I2C Slave Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sctr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sctr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct SCTR_SPEC ; impl crate :: RegisterSpec for SCTR_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`sctr::R`](R) reader structure"] impl crate :: Readable for SCTR_SPEC { } # [doc = "`write(|w| ..)` method takes [`sctr::W`](W) writer structure"] impl crate :: Writable for SCTR_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets SCTR to value 0x0404"] impl crate :: Resettable for SCTR_SPEC { const RESET_VALUE : Self :: Ux = 0x0404 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/uart0/clksel.rs:1:6426 [INFO] [stdout] | [INFO] [stdout] 1 | ...ub fn clksel_lfclk_sel (& mut self) -> CLKSEL_LFCLK_SEL_W < CLKSEL_SPEC , 1 > { CLKSEL_LFCLK_SEL_W :: new (self) } # [doc = "Bit 2 - S... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `CLKSEL` reader"] pub type R = crate :: R < CLKSEL_SPEC > ; # [doc = "Register `CLKSEL` writer"] pub type W = crate :: W < CLKSEL_SPEC > ; # [doc = "Field `CLKSEL_LFCLK_SEL` reader - Selects LFCLK as clock source if enabled"] pub type CLKSEL_LFCLK_SEL_R = crate :: BitReader < CLKSEL_LFCLK_SEL_A > ; # [doc = "Selects LFCLK as clock source if enabled\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CLKSEL_LFCLK_SEL_A { # [doc = "0: DISABLE"] CLKSEL_LFCLK_SEL_DISABLE = 0 , # [doc = "1: ENABLE"] CLKSEL_LFCLK_SEL_ENABLE = 1 , } impl From < CLKSEL_LFCLK_SEL_A > for bool { # [inline (always)] fn from (variant : CLKSEL_LFCLK_SEL_A) -> Self { variant as u8 != 0 } } impl CLKSEL_LFCLK_SEL_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CLKSEL_LFCLK_SEL_A { match self . bits { false => CLKSEL_LFCLK_SEL_A :: CLKSEL_LFCLK_SEL_DISABLE , true => CLKSEL_LFCLK_SEL_A :: CLKSEL_LFCLK_SEL_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_clksel_lfclk_sel_disable (& self) -> bool { * self == CLKSEL_LFCLK_SEL_A :: CLKSEL_LFCLK_SEL_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_clksel_lfclk_sel_enable (& self) -> bool { * self == CLKSEL_LFCLK_SEL_A :: CLKSEL_LFCLK_SEL_ENABLE } } # [doc = "Field `CLKSEL_LFCLK_SEL` writer - Selects LFCLK as clock source if enabled"] pub type CLKSEL_LFCLK_SEL_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CLKSEL_LFCLK_SEL_A > ; impl < 'a , REG , const O : u8 > CLKSEL_LFCLK_SEL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn clksel_lfclk_sel_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CLKSEL_LFCLK_SEL_A :: CLKSEL_LFCLK_SEL_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn clksel_lfclk_sel_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CLKSEL_LFCLK_SEL_A :: CLKSEL_LFCLK_SEL_ENABLE) } } # [doc = "Field `CLKSEL_MFCLK_SEL` reader - Selects MFCLK as clock source if enabled"] pub type CLKSEL_MFCLK_SEL_R = crate :: BitReader < CLKSEL_MFCLK_SEL_A > ; # [doc = "Selects MFCLK as clock source if enabled\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CLKSEL_MFCLK_SEL_A { # [doc = "0: DISABLE"] CLKSEL_MFCLK_SEL_DISABLE = 0 , # [doc = "1: ENABLE"] CLKSEL_MFCLK_SEL_ENABLE = 1 , } impl From < CLKSEL_MFCLK_SEL_A > for bool { # [inline (always)] fn from (variant : CLKSEL_MFCLK_SEL_A) -> Self { variant as u8 != 0 } } impl CLKSEL_MFCLK_SEL_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CLKSEL_MFCLK_SEL_A { match self . bits { false => CLKSEL_MFCLK_SEL_A :: CLKSEL_MFCLK_SEL_DISABLE , true => CLKSEL_MFCLK_SEL_A :: CLKSEL_MFCLK_SEL_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_clksel_mfclk_sel_disable (& self) -> bool { * self == CLKSEL_MFCLK_SEL_A :: CLKSEL_MFCLK_SEL_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_clksel_mfclk_sel_enable (& self) -> bool { * self == CLKSEL_MFCLK_SEL_A :: CLKSEL_MFCLK_SEL_ENABLE } } # [doc = "Field `CLKSEL_MFCLK_SEL` writer - Selects MFCLK as clock source if enabled"] pub type CLKSEL_MFCLK_SEL_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CLKSEL_MFCLK_SEL_A > ; impl < 'a , REG , const O : u8 > CLKSEL_MFCLK_SEL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn clksel_mfclk_sel_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CLKSEL_MFCLK_SEL_A :: CLKSEL_MFCLK_SEL_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn clksel_mfclk_sel_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CLKSEL_MFCLK_SEL_A :: CLKSEL_MFCLK_SEL_ENABLE) } } # [doc = "Field `CLKSEL_BUSCLK_SEL` reader - Selects BUS CLK as clock source if enabled"] pub type CLKSEL_BUSCLK_SEL_R = crate :: BitReader < CLKSEL_BUSCLK_SEL_A > ; # [doc = "Selects BUS CLK as clock source if enabled\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CLKSEL_BUSCLK_SEL_A { # [doc = "0: DISABLE"] CLKSEL_BUSCLK_SEL_DISABLE = 0 , # [doc = "1: ENABLE"] CLKSEL_BUSCLK_SEL_ENABLE = 1 , } impl From < CLKSEL_BUSCLK_SEL_A > for bool { # [inline (always)] fn from (variant : CLKSEL_BUSCLK_SEL_A) -> Self { variant as u8 != 0 } } impl CLKSEL_BUSCLK_SEL_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CLKSEL_BUSCLK_SEL_A { match self . bits { false => CLKSEL_BUSCLK_SEL_A :: CLKSEL_BUSCLK_SEL_DISABLE , true => CLKSEL_BUSCLK_SEL_A :: CLKSEL_BUSCLK_SEL_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_clksel_busclk_sel_disable (& self) -> bool { * self == CLKSEL_BUSCLK_SEL_A :: CLKSEL_BUSCLK_SEL_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_clksel_busclk_sel_enable (& self) -> bool { * self == CLKSEL_BUSCLK_SEL_A :: CLKSEL_BUSCLK_SEL_ENABLE } } # [doc = "Field `CLKSEL_BUSCLK_SEL` writer - Selects BUS CLK as clock source if enabled"] pub type CLKSEL_BUSCLK_SEL_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CLKSEL_BUSCLK_SEL_A > ; impl < 'a , REG , const O : u8 > CLKSEL_BUSCLK_SEL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn clksel_busclk_sel_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CLKSEL_BUSCLK_SEL_A :: CLKSEL_BUSCLK_SEL_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn clksel_busclk_sel_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CLKSEL_BUSCLK_SEL_A :: CLKSEL_BUSCLK_SEL_ENABLE) } } impl R { # [doc = "Bit 1 - Selects LFCLK as clock source if enabled"] # [inline (always)] pub fn clksel_lfclk_sel (& self) -> CLKSEL_LFCLK_SEL_R { CLKSEL_LFCLK_SEL_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - Selects MFCLK as clock source if enabled"] # [inline (always)] pub fn clksel_mfclk_sel (& self) -> CLKSEL_MFCLK_SEL_R { CLKSEL_MFCLK_SEL_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - Selects BUS CLK as clock source if enabled"] # [inline (always)] pub fn clksel_busclk_sel (& self) -> CLKSEL_BUSCLK_SEL_R { CLKSEL_BUSCLK_SEL_R :: new (((self . bits >> 3) & 1) != 0) } } impl W { # [doc = "Bit 1 - Selects LFCLK as clock source if enabled"] # [inline (always)] # [must_use] pub fn clksel_lfclk_sel (& mut self) -> CLKSEL_LFCLK_SEL_W <'_, CLKSEL_SPEC , 1 > { CLKSEL_LFCLK_SEL_W :: new (self) } # [doc = "Bit 2 - Selects MFCLK as clock source if enabled"] # [inline (always)] # [must_use] pub fn clksel_mfclk_sel (& mut self) -> CLKSEL_MFCLK_SEL_W < CLKSEL_SPEC , 2 > { CLKSEL_MFCLK_SEL_W :: new (self) } # [doc = "Bit 3 - Selects BUS CLK as clock source if enabled"] # [inline (always)] # [must_use] pub fn clksel_busclk_sel (& mut self) -> CLKSEL_BUSCLK_SEL_W < CLKSEL_SPEC , 3 > { CLKSEL_BUSCLK_SEL_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Clock Select for Ultra Low Power peripherals\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clksel::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clksel::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CLKSEL_SPEC ; impl crate :: RegisterSpec for CLKSEL_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`clksel::R`](R) reader structure"] impl crate :: Readable for CLKSEL_SPEC { } # [doc = "`write(|w| ..)` method takes [`clksel::W`](W) writer structure"] impl crate :: Writable for CLKSEL_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets CLKSEL to value 0"] impl crate :: Resettable for CLKSEL_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/i2c1/master_i2cpecctl.rs:1:10529 [INFO] [stdout] | [INFO] [stdout] 1 | ...cpecctl_pecen (& mut self) -> MASTER_I2CPECCTL_PECEN_W < MASTER_I2CPECCTL_SPEC , 12 > { MASTER_I2CPECCTL_PECEN_W :: new (self) } # [do... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `MASTER_I2CPECCTL` reader"] pub type R = crate :: R < MASTER_I2CPECCTL_SPEC > ; # [doc = "Register `MASTER_I2CPECCTL` writer"] pub type W = crate :: W < MASTER_I2CPECCTL_SPEC > ; # [doc = "Field `MASTER_I2CPECCTL_PECCNT` reader - PEC Count When this field is non zero, the number of I2C bytes are counted (Note that although the PEC is calculated on the I2C address it is not counted at a byte). When the byte count = PECCNT and the state machine is transmitting, the contents of the LSFR is loaded into the shift register instead of the byte received from the Tx FIFO. When the state machine is receiving, after the last bit of this byte is received the LSFR is checked and if it is non-zero, a PEC RX Error interrupt is generated. The I2C packet must be padded to include the PEC byte for both transmit and receive. In transmit mode the FIFO must be loaded with a dummy PEC byte. In receive mode the PEC byte will be passed to the Rx FIFO. In the normal Master use case, FW would set PECEN=1 and PECCNT=SMB packet length (Not including Slave Address byte, but including the PEC byte). FW would then configure DMA to allow the packet to complete unassisted and write MCTR to initiate the transaction. Note that when the byte count = PEC CNT, the byte count is reset to 0 and multiple PEC calculation can automatically occur within a single I2C transaction. Note that any write to the MASTER_I2CPECCTL Register will clear the current PEC Byte Count in the Master State Machine."] pub type MASTER_I2CPECCTL_PECCNT_R = crate :: FieldReader < u16 > ; # [doc = "Field `MASTER_I2CPECCTL_PECCNT` writer - PEC Count When this field is non zero, the number of I2C bytes are counted (Note that although the PEC is calculated on the I2C address it is not counted at a byte). When the byte count = PECCNT and the state machine is transmitting, the contents of the LSFR is loaded into the shift register instead of the byte received from the Tx FIFO. When the state machine is receiving, after the last bit of this byte is received the LSFR is checked and if it is non-zero, a PEC RX Error interrupt is generated. The I2C packet must be padded to include the PEC byte for both transmit and receive. In transmit mode the FIFO must be loaded with a dummy PEC byte. In receive mode the PEC byte will be passed to the Rx FIFO. In the normal Master use case, FW would set PECEN=1 and PECCNT=SMB packet length (Not including Slave Address byte, but including the PEC byte). FW would then configure DMA to allow the packet to complete unassisted and write MCTR to initiate the transaction. Note that when the byte count = PEC CNT, the byte count is reset to 0 and multiple PEC calculation can automatically occur within a single I2C transaction. Note that any write to the MASTER_I2CPECCTL Register will clear the current PEC Byte Count in the Master State Machine."] pub type MASTER_I2CPECCTL_PECCNT_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 9 , O , u16 > ; # [doc = "Field `MASTER_I2CPECCTL_PECEN` reader - PEC Enable This bit enables the SMB Packet Error Checking (PEC). When enabled the PEC is calculated on all bits accept the Start, Stop, Ack and Nack. The PEC LSFR and the Byte Counter is set to 0 when the State Machine is in the IDLE state, which occur following a Stop or when a timeout occurs. The Counter is also set to 0 after the PEC byte is sent or received. Note that the NACK is automatically send following a PEC byte that results in a PEC error. The PEC Polynomial is x^8 + x^2 + x^1 + 1."] pub type MASTER_I2CPECCTL_PECEN_R = crate :: BitReader < MASTER_I2CPECCTL_PECEN_A > ; # [doc = "PEC Enable This bit enables the SMB Packet Error Checking (PEC). When enabled the PEC is calculated on all bits accept the Start, Stop, Ack and Nack. The PEC LSFR and the Byte Counter is set to 0 when the State Machine is in the IDLE state, which occur following a Stop or when a timeout occurs. The Counter is also set to 0 after the PEC byte is sent or received. Note that the NACK is automatically send following a PEC byte that results in a PEC error. The PEC Polynomial is x^8 + x^2 + x^1 + 1.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum MASTER_I2CPECCTL_PECEN_A { # [doc = "0: DISABLE"] MASTER_I2CPECCTL_PECEN_DISABLE = 0 , # [doc = "1: ENABLE"] MASTER_I2CPECCTL_PECEN_ENABLE = 1 , } impl From < MASTER_I2CPECCTL_PECEN_A > for bool { # [inline (always)] fn from (variant : MASTER_I2CPECCTL_PECEN_A) -> Self { variant as u8 != 0 } } impl MASTER_I2CPECCTL_PECEN_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> MASTER_I2CPECCTL_PECEN_A { match self . bits { false => MASTER_I2CPECCTL_PECEN_A :: MASTER_I2CPECCTL_PECEN_DISABLE , true => MASTER_I2CPECCTL_PECEN_A :: MASTER_I2CPECCTL_PECEN_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_master_i2cpecctl_pecen_disable (& self) -> bool { * self == MASTER_I2CPECCTL_PECEN_A :: MASTER_I2CPECCTL_PECEN_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_master_i2cpecctl_pecen_enable (& self) -> bool { * self == MASTER_I2CPECCTL_PECEN_A :: MASTER_I2CPECCTL_PECEN_ENABLE } } # [doc = "Field `MASTER_I2CPECCTL_PECEN` writer - PEC Enable This bit enables the SMB Packet Error Checking (PEC). When enabled the PEC is calculated on all bits accept the Start, Stop, Ack and Nack. The PEC LSFR and the Byte Counter is set to 0 when the State Machine is in the IDLE state, which occur following a Stop or when a timeout occurs. The Counter is also set to 0 after the PEC byte is sent or received. Note that the NACK is automatically send following a PEC byte that results in a PEC error. The PEC Polynomial is x^8 + x^2 + x^1 + 1."] pub type MASTER_I2CPECCTL_PECEN_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , MASTER_I2CPECCTL_PECEN_A > ; impl < 'a , REG , const O : u8 > MASTER_I2CPECCTL_PECEN_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn master_i2cpecctl_pecen_disable (self) -> & 'a mut crate :: W < REG > { self . variant (MASTER_I2CPECCTL_PECEN_A :: MASTER_I2CPECCTL_PECEN_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn master_i2cpecctl_pecen_enable (self) -> & 'a mut crate :: W < REG > { self . variant (MASTER_I2CPECCTL_PECEN_A :: MASTER_I2CPECCTL_PECEN_ENABLE) } } impl R { # [doc = "Bits 0:8 - PEC Count When this field is non zero, the number of I2C bytes are counted (Note that although the PEC is calculated on the I2C address it is not counted at a byte). When the byte count = PECCNT and the state machine is transmitting, the contents of the LSFR is loaded into the shift register instead of the byte received from the Tx FIFO. When the state machine is receiving, after the last bit of this byte is received the LSFR is checked and if it is non-zero, a PEC RX Error interrupt is generated. The I2C packet must be padded to include the PEC byte for both transmit and receive. In transmit mode the FIFO must be loaded with a dummy PEC byte. In receive mode the PEC byte will be passed to the Rx FIFO. In the normal Master use case, FW would set PECEN=1 and PECCNT=SMB packet length (Not including Slave Address byte, but including the PEC byte). FW would then configure DMA to allow the packet to complete unassisted and write MCTR to initiate the transaction. Note that when the byte count = PEC CNT, the byte count is reset to 0 and multiple PEC calculation can automatically occur within a single I2C transaction. Note that any write to the MASTER_I2CPECCTL Register will clear the current PEC Byte Count in the Master State Machine."] # [inline (always)] pub fn master_i2cpecctl_peccnt (& self) -> MASTER_I2CPECCTL_PECCNT_R { MASTER_I2CPECCTL_PECCNT_R :: new ((self . bits & 0x01ff) as u16) } # [doc = "Bit 12 - PEC Enable This bit enables the SMB Packet Error Checking (PEC). When enabled the PEC is calculated on all bits accept the Start, Stop, Ack and Nack. The PEC LSFR and the Byte Counter is set to 0 when the State Machine is in the IDLE state, which occur following a Stop or when a timeout occurs. The Counter is also set to 0 after the PEC byte is sent or received. Note that the NACK is automatically send following a PEC byte that results in a PEC error. The PEC Polynomial is x^8 + x^2 + x^1 + 1."] # [inline (always)] pub fn master_i2cpecctl_pecen (& self) -> MASTER_I2CPECCTL_PECEN_R { MASTER_I2CPECCTL_PECEN_R :: new (((self . bits >> 12) & 1) != 0) } } impl W { # [doc = "Bits 0:8 - PEC Count When this field is non zero, the number of I2C bytes are counted (Note that although the PEC is calculated on the I2C address it is not counted at a byte). When the byte count = PECCNT and the state machine is transmitting, the contents of the LSFR is loaded into the shift register instead of the byte received from the Tx FIFO. When the state machine is receiving, after the last bit of this byte is received the LSFR is checked and if it is non-zero, a PEC RX Error interrupt is generated. The I2C packet must be padded to include the PEC byte for both transmit and receive. In transmit mode the FIFO must be loaded with a dummy PEC byte. In receive mode the PEC byte will be passed to the Rx FIFO. In the normal Master use case, FW would set PECEN=1 and PECCNT=SMB packet length (Not including Slave Address byte, but including the PEC byte). FW would then configure DMA to allow the packet to complete unassisted and write MCTR to initiate the transaction. Note that when the byte count = PEC CNT, the byte count is reset to 0 and multiple PEC calculation can automatically occur within a single I2C transaction. Note that any write to the MASTER_I2CPECCTL Register will clear the current PEC Byte Count in the Master State Machine."] # [inline (always)] # [must_use] pub fn master_i2cpecctl_peccnt (& mut self) -> MASTER_I2CPECCTL_PECCNT_W < MASTER_I2CPECCTL_SPEC , 0 > { MASTER_I2CPECCTL_PECCNT_W :: new (self) } # [doc = "Bit 12 - PEC Enable This bit enables the SMB Packet Error Checking (PEC). When enabled the PEC is calculated on all bits accept the Start, Stop, Ack and Nack. The PEC LSFR and the Byte Counter is set to 0 when the State Machine is in the IDLE state, which occur following a Stop or when a timeout occurs. The Counter is also set to 0 after the PEC byte is sent or received. Note that the NACK is automatically send following a PEC byte that results in a PEC error. The PEC Polynomial is x^8 + x^2 + x^1 + 1."] # [inline (always)] # [must_use] pub fn master_i2cpecctl_pecen (& mut self) -> MASTER_I2CPECCTL_PECEN_W <'_, MASTER_I2CPECCTL_SPEC , 12 > { MASTER_I2CPECCTL_PECEN_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "I2C master PEC control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`master_i2cpecctl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`master_i2cpecctl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct MASTER_I2CPECCTL_SPEC ; impl crate :: RegisterSpec for MASTER_I2CPECCTL_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`master_i2cpecctl::R`](R) reader structure"] impl crate :: Readable for MASTER_I2CPECCTL_SPEC { } # [doc = "`write(|w| ..)` method takes [`master_i2cpecctl::W`](W) writer structure"] impl crate :: Writable for MASTER_I2CPECCTL_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets MASTER_I2CPECCTL to value 0"] impl crate :: Resettable for MASTER_I2CPECCTL_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/i2c1/int_event1_iclr.rs:1:5642 [INFO] [stdout] | [INFO] [stdout] 1 | ...r_mtxfifotrg (& mut self) -> INT_EVENT1_ICLR_MTXFIFOTRG_W < INT_EVENT1_ICLR_SPEC , 1 > { INT_EVENT1_ICLR_MTXFIFOTRG_W :: new (self) } ... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `INT_EVENT1_ICLR` writer"] pub type W = crate :: W < INT_EVENT1_ICLR_SPEC > ; # [doc = "Master Receive FIFO Trigger Trigger when RX FIFO contains &gt;= defined bytes\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT1_ICLR_MRXFIFOTRG_AW { # [doc = "0: NO_EFFECT"] INT_EVENT1_ICLR_MRXFIFOTRG_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT1_ICLR_MRXFIFOTRG_CLR = 1 , } impl From < INT_EVENT1_ICLR_MRXFIFOTRG_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT1_ICLR_MRXFIFOTRG_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT1_ICLR_MRXFIFOTRG` writer - Master Receive FIFO Trigger Trigger when RX FIFO contains &gt;= defined bytes"] pub type INT_EVENT1_ICLR_MRXFIFOTRG_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT1_ICLR_MRXFIFOTRG_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT1_ICLR_MRXFIFOTRG_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event1_iclr_mrxfifotrg_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_ICLR_MRXFIFOTRG_AW :: INT_EVENT1_ICLR_MRXFIFOTRG_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event1_iclr_mrxfifotrg_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_ICLR_MRXFIFOTRG_AW :: INT_EVENT1_ICLR_MRXFIFOTRG_CLR) } } # [doc = "Master Transmit FIFO Trigger Trigger when Transmit FIFO contains &lt;= defined bytes\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT1_ICLR_MTXFIFOTRG_AW { # [doc = "0: NO_EFFECT"] INT_EVENT1_ICLR_MTXFIFOTRG_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT1_ICLR_MTXFIFOTRG_CLR = 1 , } impl From < INT_EVENT1_ICLR_MTXFIFOTRG_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT1_ICLR_MTXFIFOTRG_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT1_ICLR_MTXFIFOTRG` writer - Master Transmit FIFO Trigger Trigger when Transmit FIFO contains &lt;= defined bytes"] pub type INT_EVENT1_ICLR_MTXFIFOTRG_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT1_ICLR_MTXFIFOTRG_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT1_ICLR_MTXFIFOTRG_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event1_iclr_mtxfifotrg_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_ICLR_MTXFIFOTRG_AW :: INT_EVENT1_ICLR_MTXFIFOTRG_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event1_iclr_mtxfifotrg_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_ICLR_MTXFIFOTRG_AW :: INT_EVENT1_ICLR_MTXFIFOTRG_CLR) } } # [doc = "Slave Receive FIFO Trigger\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT1_ICLR_SRXFIFOTRG_AW { # [doc = "0: NO_EFFECT"] INT_EVENT1_ICLR_SRXFIFOTRG_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT1_ICLR_SRXFIFOTRG_CLR = 1 , } impl From < INT_EVENT1_ICLR_SRXFIFOTRG_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT1_ICLR_SRXFIFOTRG_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT1_ICLR_SRXFIFOTRG` writer - Slave Receive FIFO Trigger"] pub type INT_EVENT1_ICLR_SRXFIFOTRG_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT1_ICLR_SRXFIFOTRG_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT1_ICLR_SRXFIFOTRG_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event1_iclr_srxfifotrg_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_ICLR_SRXFIFOTRG_AW :: INT_EVENT1_ICLR_SRXFIFOTRG_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event1_iclr_srxfifotrg_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_ICLR_SRXFIFOTRG_AW :: INT_EVENT1_ICLR_SRXFIFOTRG_CLR) } } # [doc = "Slave Transmit FIFO Trigger\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT1_ICLR_STXFIFOTRG_AW { # [doc = "0: NO_EFFECT"] INT_EVENT1_ICLR_STXFIFOTRG_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT1_ICLR_STXFIFOTRG_CLR = 1 , } impl From < INT_EVENT1_ICLR_STXFIFOTRG_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT1_ICLR_STXFIFOTRG_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT1_ICLR_STXFIFOTRG` writer - Slave Transmit FIFO Trigger"] pub type INT_EVENT1_ICLR_STXFIFOTRG_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT1_ICLR_STXFIFOTRG_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT1_ICLR_STXFIFOTRG_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event1_iclr_stxfifotrg_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_ICLR_STXFIFOTRG_AW :: INT_EVENT1_ICLR_STXFIFOTRG_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event1_iclr_stxfifotrg_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_ICLR_STXFIFOTRG_AW :: INT_EVENT1_ICLR_STXFIFOTRG_CLR) } } impl W { # [doc = "Bit 0 - Master Receive FIFO Trigger Trigger when RX FIFO contains &gt;= defined bytes"] # [inline (always)] # [must_use] pub fn int_event1_iclr_mrxfifotrg (& mut self) -> INT_EVENT1_ICLR_MRXFIFOTRG_W < INT_EVENT1_ICLR_SPEC , 0 > { INT_EVENT1_ICLR_MRXFIFOTRG_W :: new (self) } # [doc = "Bit 1 - Master Transmit FIFO Trigger Trigger when Transmit FIFO contains &lt;= defined bytes"] # [inline (always)] # [must_use] pub fn int_event1_iclr_mtxfifotrg (& mut self) -> INT_EVENT1_ICLR_MTXFIFOTRG_W <'_, INT_EVENT1_ICLR_SPEC , 1 > { INT_EVENT1_ICLR_MTXFIFOTRG_W :: new (self) } # [doc = "Bit 2 - Slave Receive FIFO Trigger"] # [inline (always)] # [must_use] pub fn int_event1_iclr_srxfifotrg (& mut self) -> INT_EVENT1_ICLR_SRXFIFOTRG_W < INT_EVENT1_ICLR_SPEC , 2 > { INT_EVENT1_ICLR_SRXFIFOTRG_W :: new (self) } # [doc = "Bit 3 - Slave Transmit FIFO Trigger"] # [inline (always)] # [must_use] pub fn int_event1_iclr_stxfifotrg (& mut self) -> INT_EVENT1_ICLR_STXFIFOTRG_W < INT_EVENT1_ICLR_SPEC , 3 > { INT_EVENT1_ICLR_STXFIFOTRG_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Interrupt clear\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_event1_iclr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct INT_EVENT1_ICLR_SPEC ; impl crate :: RegisterSpec for INT_EVENT1_ICLR_SPEC { type Ux = u32 ; } # [doc = "`write(|w| ..)` method takes [`int_event1_iclr::W`](W) writer structure"] impl crate :: Writable for INT_EVENT1_ICLR_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets INT_EVENT1_ICLR to value 0"] impl crate :: Resettable for INT_EVENT1_ICLR_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/opa1/cfg.rs:1:17222 [INFO] [stdout] | [INFO] [stdout] 1 | ... [must_use] pub fn cfg_nsel (& mut self) -> CFG_NSEL_W < CFG_SPEC , 7 > { CFG_NSEL_W :: new (self) } # [doc = "Bits 10:12 - MSEL Mux s... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `CFG` reader"] pub type R = crate :: R < CFG_SPEC > ; # [doc = "Register `CFG` writer"] pub type W = crate :: W < CFG_SPEC > ; # [doc = "Field `CFG_CHOP` reader - Chopping enable."] pub type CFG_CHOP_R = crate :: FieldReader < CFG_CHOP_A > ; # [doc = "Chopping enable.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum CFG_CHOP_A { # [doc = "0: OFF"] CFG_CHOP_OFF = 0 , # [doc = "1: ON"] CFG_CHOP_ON = 1 , # [doc = "2: AVGON"] CFG_CHOP_AVGON = 2 , } impl From < CFG_CHOP_A > for u8 { # [inline (always)] fn from (variant : CFG_CHOP_A) -> Self { variant as _ } } impl crate :: FieldSpec for CFG_CHOP_A { type Ux = u8 ; } impl CFG_CHOP_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < CFG_CHOP_A > { match self . bits { 0 => Some (CFG_CHOP_A :: CFG_CHOP_OFF) , 1 => Some (CFG_CHOP_A :: CFG_CHOP_ON) , 2 => Some (CFG_CHOP_A :: CFG_CHOP_AVGON) , _ => None , } } # [doc = "OFF"] # [inline (always)] pub fn is_cfg_chop_off (& self) -> bool { * self == CFG_CHOP_A :: CFG_CHOP_OFF } # [doc = "ON"] # [inline (always)] pub fn is_cfg_chop_on (& self) -> bool { * self == CFG_CHOP_A :: CFG_CHOP_ON } # [doc = "AVGON"] # [inline (always)] pub fn is_cfg_chop_avgon (& self) -> bool { * self == CFG_CHOP_A :: CFG_CHOP_AVGON } } # [doc = "Field `CFG_CHOP` writer - Chopping enable."] pub type CFG_CHOP_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 2 , O , CFG_CHOP_A > ; impl < 'a , REG , const O : u8 > CFG_CHOP_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "OFF"] # [inline (always)] pub fn cfg_chop_off (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_CHOP_A :: CFG_CHOP_OFF) } # [doc = "ON"] # [inline (always)] pub fn cfg_chop_on (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_CHOP_A :: CFG_CHOP_ON) } # [doc = "AVGON"] # [inline (always)] pub fn cfg_chop_avgon (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_CHOP_A :: CFG_CHOP_AVGON) } } # [doc = "Field `CFG_OUTPIN` reader - Enable output pin"] pub type CFG_OUTPIN_R = crate :: BitReader < CFG_OUTPIN_A > ; # [doc = "Enable output pin\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CFG_OUTPIN_A { # [doc = "0: DISABLED"] CFG_OUTPIN_DISABLED = 0 , # [doc = "1: ENABLED"] CFG_OUTPIN_ENABLED = 1 , } impl From < CFG_OUTPIN_A > for bool { # [inline (always)] fn from (variant : CFG_OUTPIN_A) -> Self { variant as u8 != 0 } } impl CFG_OUTPIN_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CFG_OUTPIN_A { match self . bits { false => CFG_OUTPIN_A :: CFG_OUTPIN_DISABLED , true => CFG_OUTPIN_A :: CFG_OUTPIN_ENABLED , } } # [doc = "DISABLED"] # [inline (always)] pub fn is_cfg_outpin_disabled (& self) -> bool { * self == CFG_OUTPIN_A :: CFG_OUTPIN_DISABLED } # [doc = "ENABLED"] # [inline (always)] pub fn is_cfg_outpin_enabled (& self) -> bool { * self == CFG_OUTPIN_A :: CFG_OUTPIN_ENABLED } } # [doc = "Field `CFG_OUTPIN` writer - Enable output pin"] pub type CFG_OUTPIN_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CFG_OUTPIN_A > ; impl < 'a , REG , const O : u8 > CFG_OUTPIN_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLED"] # [inline (always)] pub fn cfg_outpin_disabled (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_OUTPIN_A :: CFG_OUTPIN_DISABLED) } # [doc = "ENABLED"] # [inline (always)] pub fn cfg_outpin_enabled (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_OUTPIN_A :: CFG_OUTPIN_ENABLED) } } # [doc = "Field `CFG_PSEL` reader - Positive OA input selection. Please refer to the device specific datasheet for exact channels available."] pub type CFG_PSEL_R = crate :: FieldReader < CFG_PSEL_A > ; # [doc = "Positive OA input selection. Please refer to the device specific datasheet for exact channels available.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum CFG_PSEL_A { # [doc = "0: NC"] CFG_PSEL_NC = 0 , # [doc = "1: EXTPIN0"] CFG_PSEL_EXTPIN0 = 1 , # [doc = "2: EXTPIN1"] CFG_PSEL_EXTPIN1 = 2 , # [doc = "3: DAC12OUT"] CFG_PSEL_DAC12OUT = 3 , # [doc = "4: DAC8OUT"] CFG_PSEL_DAC8OUT = 4 , # [doc = "5: VREF"] CFG_PSEL_VREF = 5 , # [doc = "6: OANM1RTOP"] CFG_PSEL_OANM1RTOP = 6 , # [doc = "7: GPAMP_OUT_INT"] CFG_PSEL_GPAMP_OUT_INT = 7 , # [doc = "8: VSS"] CFG_PSEL_VSS = 8 , } impl From < CFG_PSEL_A > for u8 { # [inline (always)] fn from (variant : CFG_PSEL_A) -> Self { variant as _ } } impl crate :: FieldSpec for CFG_PSEL_A { type Ux = u8 ; } impl CFG_PSEL_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < CFG_PSEL_A > { match self . bits { 0 => Some (CFG_PSEL_A :: CFG_PSEL_NC) , 1 => Some (CFG_PSEL_A :: CFG_PSEL_EXTPIN0) , 2 => Some (CFG_PSEL_A :: CFG_PSEL_EXTPIN1) , 3 => Some (CFG_PSEL_A :: CFG_PSEL_DAC12OUT) , 4 => Some (CFG_PSEL_A :: CFG_PSEL_DAC8OUT) , 5 => Some (CFG_PSEL_A :: CFG_PSEL_VREF) , 6 => Some (CFG_PSEL_A :: CFG_PSEL_OANM1RTOP) , 7 => Some (CFG_PSEL_A :: CFG_PSEL_GPAMP_OUT_INT) , 8 => Some (CFG_PSEL_A :: CFG_PSEL_VSS) , _ => None , } } # [doc = "NC"] # [inline (always)] pub fn is_cfg_psel_nc (& self) -> bool { * self == CFG_PSEL_A :: CFG_PSEL_NC } # [doc = "EXTPIN0"] # [inline (always)] pub fn is_cfg_psel_extpin0 (& self) -> bool { * self == CFG_PSEL_A :: CFG_PSEL_EXTPIN0 } # [doc = "EXTPIN1"] # [inline (always)] pub fn is_cfg_psel_extpin1 (& self) -> bool { * self == CFG_PSEL_A :: CFG_PSEL_EXTPIN1 } # [doc = "DAC12OUT"] # [inline (always)] pub fn is_cfg_psel_dac12out (& self) -> bool { * self == CFG_PSEL_A :: CFG_PSEL_DAC12OUT } # [doc = "DAC8OUT"] # [inline (always)] pub fn is_cfg_psel_dac8out (& self) -> bool { * self == CFG_PSEL_A :: CFG_PSEL_DAC8OUT } # [doc = "VREF"] # [inline (always)] pub fn is_cfg_psel_vref (& self) -> bool { * self == CFG_PSEL_A :: CFG_PSEL_VREF } # [doc = "OANM1RTOP"] # [inline (always)] pub fn is_cfg_psel_oanm1rtop (& self) -> bool { * self == CFG_PSEL_A :: CFG_PSEL_OANM1RTOP } # [doc = "GPAMP_OUT_INT"] # [inline (always)] pub fn is_cfg_psel_gpamp_out_int (& self) -> bool { * self == CFG_PSEL_A :: CFG_PSEL_GPAMP_OUT_INT } # [doc = "VSS"] # [inline (always)] pub fn is_cfg_psel_vss (& self) -> bool { * self == CFG_PSEL_A :: CFG_PSEL_VSS } } # [doc = "Field `CFG_PSEL` writer - Positive OA input selection. Please refer to the device specific datasheet for exact channels available."] pub type CFG_PSEL_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 4 , O , CFG_PSEL_A > ; impl < 'a , REG , const O : u8 > CFG_PSEL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "NC"] # [inline (always)] pub fn cfg_psel_nc (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_PSEL_A :: CFG_PSEL_NC) } # [doc = "EXTPIN0"] # [inline (always)] pub fn cfg_psel_extpin0 (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_PSEL_A :: CFG_PSEL_EXTPIN0) } # [doc = "EXTPIN1"] # [inline (always)] pub fn cfg_psel_extpin1 (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_PSEL_A :: CFG_PSEL_EXTPIN1) } # [doc = "DAC12OUT"] # [inline (always)] pub fn cfg_psel_dac12out (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_PSEL_A :: CFG_PSEL_DAC12OUT) } # [doc = "DAC8OUT"] # [inline (always)] pub fn cfg_psel_dac8out (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_PSEL_A :: CFG_PSEL_DAC8OUT) } # [doc = "VREF"] # [inline (always)] pub fn cfg_psel_vref (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_PSEL_A :: CFG_PSEL_VREF) } # [doc = "OANM1RTOP"] # [inline (always)] pub fn cfg_psel_oanm1rtop (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_PSEL_A :: CFG_PSEL_OANM1RTOP) } # [doc = "GPAMP_OUT_INT"] # [inline (always)] pub fn cfg_psel_gpamp_out_int (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_PSEL_A :: CFG_PSEL_GPAMP_OUT_INT) } # [doc = "VSS"] # [inline (always)] pub fn cfg_psel_vss (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_PSEL_A :: CFG_PSEL_VSS) } } # [doc = "Field `CFG_NSEL` reader - Negative OA input selection. Please refer to the device specific datasheet for exact channels available."] pub type CFG_NSEL_R = crate :: FieldReader < CFG_NSEL_A > ; # [doc = "Negative OA input selection. Please refer to the device specific datasheet for exact channels available.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum CFG_NSEL_A { # [doc = "0: NC"] CFG_NSEL_NC = 0 , # [doc = "1: EXTPIN0"] CFG_NSEL_EXTPIN0 = 1 , # [doc = "2: EXTPIN1"] CFG_NSEL_EXTPIN1 = 2 , # [doc = "3: OANP1RBOT"] CFG_NSEL_OANP1RBOT = 3 , # [doc = "4: OANRTAP"] CFG_NSEL_OANRTAP = 4 , # [doc = "5: OANRTOP"] CFG_NSEL_OANRTOP = 5 , # [doc = "6: SPARE"] CFG_NSEL_SPARE = 6 , } impl From < CFG_NSEL_A > for u8 { # [inline (always)] fn from (variant : CFG_NSEL_A) -> Self { variant as _ } } impl crate :: FieldSpec for CFG_NSEL_A { type Ux = u8 ; } impl CFG_NSEL_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < CFG_NSEL_A > { match self . bits { 0 => Some (CFG_NSEL_A :: CFG_NSEL_NC) , 1 => Some (CFG_NSEL_A :: CFG_NSEL_EXTPIN0) , 2 => Some (CFG_NSEL_A :: CFG_NSEL_EXTPIN1) , 3 => Some (CFG_NSEL_A :: CFG_NSEL_OANP1RBOT) , 4 => Some (CFG_NSEL_A :: CFG_NSEL_OANRTAP) , 5 => Some (CFG_NSEL_A :: CFG_NSEL_OANRTOP) , 6 => Some (CFG_NSEL_A :: CFG_NSEL_SPARE) , _ => None , } } # [doc = "NC"] # [inline (always)] pub fn is_cfg_nsel_nc (& self) -> bool { * self == CFG_NSEL_A :: CFG_NSEL_NC } # [doc = "EXTPIN0"] # [inline (always)] pub fn is_cfg_nsel_extpin0 (& self) -> bool { * self == CFG_NSEL_A :: CFG_NSEL_EXTPIN0 } # [doc = "EXTPIN1"] # [inline (always)] pub fn is_cfg_nsel_extpin1 (& self) -> bool { * self == CFG_NSEL_A :: CFG_NSEL_EXTPIN1 } # [doc = "OANP1RBOT"] # [inline (always)] pub fn is_cfg_nsel_oanp1rbot (& self) -> bool { * self == CFG_NSEL_A :: CFG_NSEL_OANP1RBOT } # [doc = "OANRTAP"] # [inline (always)] pub fn is_cfg_nsel_oanrtap (& self) -> bool { * self == CFG_NSEL_A :: CFG_NSEL_OANRTAP } # [doc = "OANRTOP"] # [inline (always)] pub fn is_cfg_nsel_oanrtop (& self) -> bool { * self == CFG_NSEL_A :: CFG_NSEL_OANRTOP } # [doc = "SPARE"] # [inline (always)] pub fn is_cfg_nsel_spare (& self) -> bool { * self == CFG_NSEL_A :: CFG_NSEL_SPARE } } # [doc = "Field `CFG_NSEL` writer - Negative OA input selection. Please refer to the device specific datasheet for exact channels available."] pub type CFG_NSEL_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 3 , O , CFG_NSEL_A > ; impl < 'a , REG , const O : u8 > CFG_NSEL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "NC"] # [inline (always)] pub fn cfg_nsel_nc (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_NSEL_A :: CFG_NSEL_NC) } # [doc = "EXTPIN0"] # [inline (always)] pub fn cfg_nsel_extpin0 (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_NSEL_A :: CFG_NSEL_EXTPIN0) } # [doc = "EXTPIN1"] # [inline (always)] pub fn cfg_nsel_extpin1 (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_NSEL_A :: CFG_NSEL_EXTPIN1) } # [doc = "OANP1RBOT"] # [inline (always)] pub fn cfg_nsel_oanp1rbot (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_NSEL_A :: CFG_NSEL_OANP1RBOT) } # [doc = "OANRTAP"] # [inline (always)] pub fn cfg_nsel_oanrtap (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_NSEL_A :: CFG_NSEL_OANRTAP) } # [doc = "OANRTOP"] # [inline (always)] pub fn cfg_nsel_oanrtop (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_NSEL_A :: CFG_NSEL_OANRTOP) } # [doc = "SPARE"] # [inline (always)] pub fn cfg_nsel_spare (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_NSEL_A :: CFG_NSEL_SPARE) } } # [doc = "Field `CFG_MSEL` reader - MSEL Mux selection. Please refer to the device specific datasheet for exact channels available."] pub type CFG_MSEL_R = crate :: FieldReader < CFG_MSEL_A > ; # [doc = "MSEL Mux selection. Please refer to the device specific datasheet for exact channels available.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum CFG_MSEL_A { # [doc = "0: NC"] CFG_MSEL_NC = 0 , # [doc = "1: EXTNPIN1"] CFG_MSEL_EXTNPIN1 = 1 , # [doc = "2: VSS"] CFG_MSEL_VSS = 2 , # [doc = "3: DAC12OUT"] CFG_MSEL_DAC12OUT = 3 , # [doc = "4: OANM1RTOP"] CFG_MSEL_OANM1RTOP = 4 , } impl From < CFG_MSEL_A > for u8 { # [inline (always)] fn from (variant : CFG_MSEL_A) -> Self { variant as _ } } impl crate :: FieldSpec for CFG_MSEL_A { type Ux = u8 ; } impl CFG_MSEL_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < CFG_MSEL_A > { match self . bits { 0 => Some (CFG_MSEL_A :: CFG_MSEL_NC) , 1 => Some (CFG_MSEL_A :: CFG_MSEL_EXTNPIN1) , 2 => Some (CFG_MSEL_A :: CFG_MSEL_VSS) , 3 => Some (CFG_MSEL_A :: CFG_MSEL_DAC12OUT) , 4 => Some (CFG_MSEL_A :: CFG_MSEL_OANM1RTOP) , _ => None , } } # [doc = "NC"] # [inline (always)] pub fn is_cfg_msel_nc (& self) -> bool { * self == CFG_MSEL_A :: CFG_MSEL_NC } # [doc = "EXTNPIN1"] # [inline (always)] pub fn is_cfg_msel_extnpin1 (& self) -> bool { * self == CFG_MSEL_A :: CFG_MSEL_EXTNPIN1 } # [doc = "VSS"] # [inline (always)] pub fn is_cfg_msel_vss (& self) -> bool { * self == CFG_MSEL_A :: CFG_MSEL_VSS } # [doc = "DAC12OUT"] # [inline (always)] pub fn is_cfg_msel_dac12out (& self) -> bool { * self == CFG_MSEL_A :: CFG_MSEL_DAC12OUT } # [doc = "OANM1RTOP"] # [inline (always)] pub fn is_cfg_msel_oanm1rtop (& self) -> bool { * self == CFG_MSEL_A :: CFG_MSEL_OANM1RTOP } } # [doc = "Field `CFG_MSEL` writer - MSEL Mux selection. Please refer to the device specific datasheet for exact channels available."] pub type CFG_MSEL_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 3 , O , CFG_MSEL_A > ; impl < 'a , REG , const O : u8 > CFG_MSEL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "NC"] # [inline (always)] pub fn cfg_msel_nc (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_MSEL_A :: CFG_MSEL_NC) } # [doc = "EXTNPIN1"] # [inline (always)] pub fn cfg_msel_extnpin1 (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_MSEL_A :: CFG_MSEL_EXTNPIN1) } # [doc = "VSS"] # [inline (always)] pub fn cfg_msel_vss (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_MSEL_A :: CFG_MSEL_VSS) } # [doc = "DAC12OUT"] # [inline (always)] pub fn cfg_msel_dac12out (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_MSEL_A :: CFG_MSEL_DAC12OUT) } # [doc = "OANM1RTOP"] # [inline (always)] pub fn cfg_msel_oanm1rtop (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_MSEL_A :: CFG_MSEL_OANM1RTOP) } } # [doc = "Field `CFG_GAIN` reader - Gain setting. Refer to TRM for enumeration information."] pub type CFG_GAIN_R = crate :: FieldReader ; # [doc = "Field `CFG_GAIN` writer - Gain setting. Refer to TRM for enumeration information."] pub type CFG_GAIN_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 3 , O > ; impl R { # [doc = "Bits 0:1 - Chopping enable."] # [inline (always)] pub fn cfg_chop (& self) -> CFG_CHOP_R { CFG_CHOP_R :: new ((self . bits & 3) as u8) } # [doc = "Bit 2 - Enable output pin"] # [inline (always)] pub fn cfg_outpin (& self) -> CFG_OUTPIN_R { CFG_OUTPIN_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bits 3:6 - Positive OA input selection. Please refer to the device specific datasheet for exact channels available."] # [inline (always)] pub fn cfg_psel (& self) -> CFG_PSEL_R { CFG_PSEL_R :: new (((self . bits >> 3) & 0x0f) as u8) } # [doc = "Bits 7:9 - Negative OA input selection. Please refer to the device specific datasheet for exact channels available."] # [inline (always)] pub fn cfg_nsel (& self) -> CFG_NSEL_R { CFG_NSEL_R :: new (((self . bits >> 7) & 7) as u8) } # [doc = "Bits 10:12 - MSEL Mux selection. Please refer to the device specific datasheet for exact channels available."] # [inline (always)] pub fn cfg_msel (& self) -> CFG_MSEL_R { CFG_MSEL_R :: new (((self . bits >> 10) & 7) as u8) } # [doc = "Bits 13:15 - Gain setting. Refer to TRM for enumeration information."] # [inline (always)] pub fn cfg_gain (& self) -> CFG_GAIN_R { CFG_GAIN_R :: new (((self . bits >> 13) & 7) as u8) } } impl W { # [doc = "Bits 0:1 - Chopping enable."] # [inline (always)] # [must_use] pub fn cfg_chop (& mut self) -> CFG_CHOP_W < CFG_SPEC , 0 > { CFG_CHOP_W :: new (self) } # [doc = "Bit 2 - Enable output pin"] # [inline (always)] # [must_use] pub fn cfg_outpin (& mut self) -> CFG_OUTPIN_W < CFG_SPEC , 2 > { CFG_OUTPIN_W :: new (self) } # [doc = "Bits 3:6 - Positive OA input selection. Please refer to the device specific datasheet for exact channels available."] # [inline (always)] # [must_use] pub fn cfg_psel (& mut self) -> CFG_PSEL_W < CFG_SPEC , 3 > { CFG_PSEL_W :: new (self) } # [doc = "Bits 7:9 - Negative OA input selection. Please refer to the device specific datasheet for exact channels available."] # [inline (always)] # [must_use] pub fn cfg_nsel (& mut self) -> CFG_NSEL_W <'_, CFG_SPEC , 7 > { CFG_NSEL_W :: new (self) } # [doc = "Bits 10:12 - MSEL Mux selection. Please refer to the device specific datasheet for exact channels available."] # [inline (always)] # [must_use] pub fn cfg_msel (& mut self) -> CFG_MSEL_W < CFG_SPEC , 10 > { CFG_MSEL_W :: new (self) } # [doc = "Bits 13:15 - Gain setting. Refer to TRM for enumeration information."] # [inline (always)] # [must_use] pub fn cfg_gain (& mut self) -> CFG_GAIN_W < CFG_SPEC , 13 > { CFG_GAIN_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Configuration Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CFG_SPEC ; impl crate :: RegisterSpec for CFG_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`cfg::R`](R) reader structure"] impl crate :: Readable for CFG_SPEC { } # [doc = "`write(|w| ..)` method takes [`cfg::W`](W) writer structure"] impl crate :: Writable for CFG_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets CFG to value 0"] impl crate :: Resettable for CFG_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/i2c1/mctr.rs:1:12901 [INFO] [stdout] | [INFO] [stdout] 1 | ... [must_use] pub fn mctr_ack (& mut self) -> MCTR_ACK_W < MCTR_SPEC , 3 > { MCTR_ACK_W :: new (self) } # [doc = "Bit 4 - Master ACK ove... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `MCTR` reader"] pub type R = crate :: R < MCTR_SPEC > ; # [doc = "Register `MCTR` writer"] pub type W = crate :: W < MCTR_SPEC > ; # [doc = "Field `MCTR_BURSTRUN` reader - I2C Master Enable and start transaction"] pub type MCTR_BURSTRUN_R = crate :: BitReader < MCTR_BURSTRUN_A > ; # [doc = "I2C Master Enable and start transaction\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum MCTR_BURSTRUN_A { # [doc = "0: DISABLE"] MCTR_BURSTRUN_DISABLE = 0 , # [doc = "1: ENABLE"] MCTR_BURSTRUN_ENABLE = 1 , } impl From < MCTR_BURSTRUN_A > for bool { # [inline (always)] fn from (variant : MCTR_BURSTRUN_A) -> Self { variant as u8 != 0 } } impl MCTR_BURSTRUN_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> MCTR_BURSTRUN_A { match self . bits { false => MCTR_BURSTRUN_A :: MCTR_BURSTRUN_DISABLE , true => MCTR_BURSTRUN_A :: MCTR_BURSTRUN_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_mctr_burstrun_disable (& self) -> bool { * self == MCTR_BURSTRUN_A :: MCTR_BURSTRUN_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_mctr_burstrun_enable (& self) -> bool { * self == MCTR_BURSTRUN_A :: MCTR_BURSTRUN_ENABLE } } # [doc = "Field `MCTR_BURSTRUN` writer - I2C Master Enable and start transaction"] pub type MCTR_BURSTRUN_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , MCTR_BURSTRUN_A > ; impl < 'a , REG , const O : u8 > MCTR_BURSTRUN_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn mctr_burstrun_disable (self) -> & 'a mut crate :: W < REG > { self . variant (MCTR_BURSTRUN_A :: MCTR_BURSTRUN_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn mctr_burstrun_enable (self) -> & 'a mut crate :: W < REG > { self . variant (MCTR_BURSTRUN_A :: MCTR_BURSTRUN_ENABLE) } } # [doc = "Field `MCTR_START` reader - Generate START"] pub type MCTR_START_R = crate :: BitReader < MCTR_START_A > ; # [doc = "Generate START\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum MCTR_START_A { # [doc = "0: DISABLE"] MCTR_START_DISABLE = 0 , # [doc = "1: ENABLE"] MCTR_START_ENABLE = 1 , } impl From < MCTR_START_A > for bool { # [inline (always)] fn from (variant : MCTR_START_A) -> Self { variant as u8 != 0 } } impl MCTR_START_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> MCTR_START_A { match self . bits { false => MCTR_START_A :: MCTR_START_DISABLE , true => MCTR_START_A :: MCTR_START_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_mctr_start_disable (& self) -> bool { * self == MCTR_START_A :: MCTR_START_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_mctr_start_enable (& self) -> bool { * self == MCTR_START_A :: MCTR_START_ENABLE } } # [doc = "Field `MCTR_START` writer - Generate START"] pub type MCTR_START_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , MCTR_START_A > ; impl < 'a , REG , const O : u8 > MCTR_START_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn mctr_start_disable (self) -> & 'a mut crate :: W < REG > { self . variant (MCTR_START_A :: MCTR_START_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn mctr_start_enable (self) -> & 'a mut crate :: W < REG > { self . variant (MCTR_START_A :: MCTR_START_ENABLE) } } # [doc = "Field `MCTR_STOP` reader - Generate STOP"] pub type MCTR_STOP_R = crate :: BitReader < MCTR_STOP_A > ; # [doc = "Generate STOP\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum MCTR_STOP_A { # [doc = "0: DISABLE"] MCTR_STOP_DISABLE = 0 , # [doc = "1: ENABLE"] MCTR_STOP_ENABLE = 1 , } impl From < MCTR_STOP_A > for bool { # [inline (always)] fn from (variant : MCTR_STOP_A) -> Self { variant as u8 != 0 } } impl MCTR_STOP_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> MCTR_STOP_A { match self . bits { false => MCTR_STOP_A :: MCTR_STOP_DISABLE , true => MCTR_STOP_A :: MCTR_STOP_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_mctr_stop_disable (& self) -> bool { * self == MCTR_STOP_A :: MCTR_STOP_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_mctr_stop_enable (& self) -> bool { * self == MCTR_STOP_A :: MCTR_STOP_ENABLE } } # [doc = "Field `MCTR_STOP` writer - Generate STOP"] pub type MCTR_STOP_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , MCTR_STOP_A > ; impl < 'a , REG , const O : u8 > MCTR_STOP_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn mctr_stop_disable (self) -> & 'a mut crate :: W < REG > { self . variant (MCTR_STOP_A :: MCTR_STOP_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn mctr_stop_enable (self) -> & 'a mut crate :: W < REG > { self . variant (MCTR_STOP_A :: MCTR_STOP_ENABLE) } } # [doc = "Field `MCTR_ACK` reader - Data Acknowledge Enable. Software needs to configure this bit to send the ACK or NACK. See field decoding in Table: MCTR Field decoding."] pub type MCTR_ACK_R = crate :: BitReader < MCTR_ACK_A > ; # [doc = "Data Acknowledge Enable. Software needs to configure this bit to send the ACK or NACK. See field decoding in Table: MCTR Field decoding.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum MCTR_ACK_A { # [doc = "0: DISABLE"] MCTR_ACK_DISABLE = 0 , # [doc = "1: ENABLE"] MCTR_ACK_ENABLE = 1 , } impl From < MCTR_ACK_A > for bool { # [inline (always)] fn from (variant : MCTR_ACK_A) -> Self { variant as u8 != 0 } } impl MCTR_ACK_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> MCTR_ACK_A { match self . bits { false => MCTR_ACK_A :: MCTR_ACK_DISABLE , true => MCTR_ACK_A :: MCTR_ACK_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_mctr_ack_disable (& self) -> bool { * self == MCTR_ACK_A :: MCTR_ACK_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_mctr_ack_enable (& self) -> bool { * self == MCTR_ACK_A :: MCTR_ACK_ENABLE } } # [doc = "Field `MCTR_ACK` writer - Data Acknowledge Enable. Software needs to configure this bit to send the ACK or NACK. See field decoding in Table: MCTR Field decoding."] pub type MCTR_ACK_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , MCTR_ACK_A > ; impl < 'a , REG , const O : u8 > MCTR_ACK_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn mctr_ack_disable (self) -> & 'a mut crate :: W < REG > { self . variant (MCTR_ACK_A :: MCTR_ACK_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn mctr_ack_enable (self) -> & 'a mut crate :: W < REG > { self . variant (MCTR_ACK_A :: MCTR_ACK_ENABLE) } } # [doc = "Field `MCTR_MACKOEN` reader - Master ACK overrride Enable"] pub type MCTR_MACKOEN_R = crate :: BitReader < MCTR_MACKOEN_A > ; # [doc = "Master ACK overrride Enable\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum MCTR_MACKOEN_A { # [doc = "0: DISABLE"] MCTR_MACKOEN_DISABLE = 0 , # [doc = "1: ENABLE"] MCTR_MACKOEN_ENABLE = 1 , } impl From < MCTR_MACKOEN_A > for bool { # [inline (always)] fn from (variant : MCTR_MACKOEN_A) -> Self { variant as u8 != 0 } } impl MCTR_MACKOEN_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> MCTR_MACKOEN_A { match self . bits { false => MCTR_MACKOEN_A :: MCTR_MACKOEN_DISABLE , true => MCTR_MACKOEN_A :: MCTR_MACKOEN_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_mctr_mackoen_disable (& self) -> bool { * self == MCTR_MACKOEN_A :: MCTR_MACKOEN_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_mctr_mackoen_enable (& self) -> bool { * self == MCTR_MACKOEN_A :: MCTR_MACKOEN_ENABLE } } # [doc = "Field `MCTR_MACKOEN` writer - Master ACK overrride Enable"] pub type MCTR_MACKOEN_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , MCTR_MACKOEN_A > ; impl < 'a , REG , const O : u8 > MCTR_MACKOEN_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn mctr_mackoen_disable (self) -> & 'a mut crate :: W < REG > { self . variant (MCTR_MACKOEN_A :: MCTR_MACKOEN_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn mctr_mackoen_enable (self) -> & 'a mut crate :: W < REG > { self . variant (MCTR_MACKOEN_A :: MCTR_MACKOEN_ENABLE) } } # [doc = "Field `MCTR_RD_ON_TXEMPTY` reader - Read on TX Empty"] pub type MCTR_RD_ON_TXEMPTY_R = crate :: BitReader < MCTR_RD_ON_TXEMPTY_A > ; # [doc = "Read on TX Empty\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum MCTR_RD_ON_TXEMPTY_A { # [doc = "0: DISABLE"] MCTR_RD_ON_TXEMPTY_DISABLE = 0 , # [doc = "1: ENABLE"] MCTR_RD_ON_TXEMPTY_ENABLE = 1 , } impl From < MCTR_RD_ON_TXEMPTY_A > for bool { # [inline (always)] fn from (variant : MCTR_RD_ON_TXEMPTY_A) -> Self { variant as u8 != 0 } } impl MCTR_RD_ON_TXEMPTY_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> MCTR_RD_ON_TXEMPTY_A { match self . bits { false => MCTR_RD_ON_TXEMPTY_A :: MCTR_RD_ON_TXEMPTY_DISABLE , true => MCTR_RD_ON_TXEMPTY_A :: MCTR_RD_ON_TXEMPTY_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_mctr_rd_on_txempty_disable (& self) -> bool { * self == MCTR_RD_ON_TXEMPTY_A :: MCTR_RD_ON_TXEMPTY_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_mctr_rd_on_txempty_enable (& self) -> bool { * self == MCTR_RD_ON_TXEMPTY_A :: MCTR_RD_ON_TXEMPTY_ENABLE } } # [doc = "Field `MCTR_RD_ON_TXEMPTY` writer - Read on TX Empty"] pub type MCTR_RD_ON_TXEMPTY_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , MCTR_RD_ON_TXEMPTY_A > ; impl < 'a , REG , const O : u8 > MCTR_RD_ON_TXEMPTY_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn mctr_rd_on_txempty_disable (self) -> & 'a mut crate :: W < REG > { self . variant (MCTR_RD_ON_TXEMPTY_A :: MCTR_RD_ON_TXEMPTY_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn mctr_rd_on_txempty_enable (self) -> & 'a mut crate :: W < REG > { self . variant (MCTR_RD_ON_TXEMPTY_A :: MCTR_RD_ON_TXEMPTY_ENABLE) } } # [doc = "Field `MCTR_MBLEN` reader - I2C transaction length This field contains the programmed length of bytes of the Transaction."] pub type MCTR_MBLEN_R = crate :: FieldReader < u16 > ; # [doc = "Field `MCTR_MBLEN` writer - I2C transaction length This field contains the programmed length of bytes of the Transaction."] pub type MCTR_MBLEN_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 12 , O , u16 > ; impl R { # [doc = "Bit 0 - I2C Master Enable and start transaction"] # [inline (always)] pub fn mctr_burstrun (& self) -> MCTR_BURSTRUN_R { MCTR_BURSTRUN_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - Generate START"] # [inline (always)] pub fn mctr_start (& self) -> MCTR_START_R { MCTR_START_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - Generate STOP"] # [inline (always)] pub fn mctr_stop (& self) -> MCTR_STOP_R { MCTR_STOP_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - Data Acknowledge Enable. Software needs to configure this bit to send the ACK or NACK. See field decoding in Table: MCTR Field decoding."] # [inline (always)] pub fn mctr_ack (& self) -> MCTR_ACK_R { MCTR_ACK_R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - Master ACK overrride Enable"] # [inline (always)] pub fn mctr_mackoen (& self) -> MCTR_MACKOEN_R { MCTR_MACKOEN_R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - Read on TX Empty"] # [inline (always)] pub fn mctr_rd_on_txempty (& self) -> MCTR_RD_ON_TXEMPTY_R { MCTR_RD_ON_TXEMPTY_R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bits 16:27 - I2C transaction length This field contains the programmed length of bytes of the Transaction."] # [inline (always)] pub fn mctr_mblen (& self) -> MCTR_MBLEN_R { MCTR_MBLEN_R :: new (((self . bits >> 16) & 0x0fff) as u16) } } impl W { # [doc = "Bit 0 - I2C Master Enable and start transaction"] # [inline (always)] # [must_use] pub fn mctr_burstrun (& mut self) -> MCTR_BURSTRUN_W < MCTR_SPEC , 0 > { MCTR_BURSTRUN_W :: new (self) } # [doc = "Bit 1 - Generate START"] # [inline (always)] # [must_use] pub fn mctr_start (& mut self) -> MCTR_START_W < MCTR_SPEC , 1 > { MCTR_START_W :: new (self) } # [doc = "Bit 2 - Generate STOP"] # [inline (always)] # [must_use] pub fn mctr_stop (& mut self) -> MCTR_STOP_W < MCTR_SPEC , 2 > { MCTR_STOP_W :: new (self) } # [doc = "Bit 3 - Data Acknowledge Enable. Software needs to configure this bit to send the ACK or NACK. See field decoding in Table: MCTR Field decoding."] # [inline (always)] # [must_use] pub fn mctr_ack (& mut self) -> MCTR_ACK_W <'_, MCTR_SPEC , 3 > { MCTR_ACK_W :: new (self) } # [doc = "Bit 4 - Master ACK overrride Enable"] # [inline (always)] # [must_use] pub fn mctr_mackoen (& mut self) -> MCTR_MACKOEN_W < MCTR_SPEC , 4 > { MCTR_MACKOEN_W :: new (self) } # [doc = "Bit 5 - Read on TX Empty"] # [inline (always)] # [must_use] pub fn mctr_rd_on_txempty (& mut self) -> MCTR_RD_ON_TXEMPTY_W < MCTR_SPEC , 5 > { MCTR_RD_ON_TXEMPTY_W :: new (self) } # [doc = "Bits 16:27 - I2C transaction length This field contains the programmed length of bytes of the Transaction."] # [inline (always)] # [must_use] pub fn mctr_mblen (& mut self) -> MCTR_MBLEN_W < MCTR_SPEC , 16 > { MCTR_MBLEN_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "I2C Master Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mctr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mctr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct MCTR_SPEC ; impl crate :: RegisterSpec for MCTR_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`mctr::R`](R) reader structure"] impl crate :: Readable for MCTR_SPEC { } # [doc = "`write(|w| ..)` method takes [`mctr::W`](W) writer structure"] impl crate :: Writable for MCTR_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets MCTR to value 0"] impl crate :: Resettable for MCTR_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/sysctl/iclr.rs:1:2465 [INFO] [stdout] | [INFO] [stdout] 1 | ...e] pub fn iclr_anaclkerr (& mut self) -> ICLR_ANACLKERR_W < ICLR_SPEC , 1 > { ICLR_ANACLKERR_W :: new (self) } # [doc = r" Writes raw ... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `ICLR` writer"] pub type W = crate :: W < ICLR_SPEC > ; # [doc = "Clear the LFOSCGOOD interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum ICLR_LFOSCGOOD_AW { # [doc = "0: NO_EFFECT"] ICLR_LFOSCGOOD_NO_EFFECT = 0 , # [doc = "1: CLR"] ICLR_LFOSCGOOD_CLR = 1 , } impl From < ICLR_LFOSCGOOD_AW > for bool { # [inline (always)] fn from (variant : ICLR_LFOSCGOOD_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `ICLR_LFOSCGOOD` writer - Clear the LFOSCGOOD interrupt."] pub type ICLR_LFOSCGOOD_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , ICLR_LFOSCGOOD_AW > ; impl < 'a , REG , const O : u8 > ICLR_LFOSCGOOD_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn iclr_lfoscgood_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (ICLR_LFOSCGOOD_AW :: ICLR_LFOSCGOOD_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn iclr_lfoscgood_clr (self) -> & 'a mut crate :: W < REG > { self . variant (ICLR_LFOSCGOOD_AW :: ICLR_LFOSCGOOD_CLR) } } # [doc = "Analog Clocking Consistency Error\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum ICLR_ANACLKERR_AW { # [doc = "0: NO_EFFECT"] ICLR_ANACLKERR_NO_EFFECT = 0 , # [doc = "1: CLR"] ICLR_ANACLKERR_CLR = 1 , } impl From < ICLR_ANACLKERR_AW > for bool { # [inline (always)] fn from (variant : ICLR_ANACLKERR_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `ICLR_ANACLKERR` writer - Analog Clocking Consistency Error"] pub type ICLR_ANACLKERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , ICLR_ANACLKERR_AW > ; impl < 'a , REG , const O : u8 > ICLR_ANACLKERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn iclr_anaclkerr_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (ICLR_ANACLKERR_AW :: ICLR_ANACLKERR_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn iclr_anaclkerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (ICLR_ANACLKERR_AW :: ICLR_ANACLKERR_CLR) } } impl W { # [doc = "Bit 0 - Clear the LFOSCGOOD interrupt."] # [inline (always)] # [must_use] pub fn iclr_lfoscgood (& mut self) -> ICLR_LFOSCGOOD_W < ICLR_SPEC , 0 > { ICLR_LFOSCGOOD_W :: new (self) } # [doc = "Bit 1 - Analog Clocking Consistency Error"] # [inline (always)] # [must_use] pub fn iclr_anaclkerr (& mut self) -> ICLR_ANACLKERR_W <'_, ICLR_SPEC , 1 > { ICLR_ANACLKERR_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "SYSCTL interrupt clear\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`iclr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct ICLR_SPEC ; impl crate :: RegisterSpec for ICLR_SPEC { type Ux = u32 ; } # [doc = "`write(|w| ..)` method takes [`iclr::W`](W) writer structure"] impl crate :: Writable for ICLR_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets ICLR to value 0"] impl crate :: Resettable for ICLR_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/i2c1/gfctl.rs:1:13307 [INFO] [stdout] | [INFO] [stdout] 1 | ...use] pub fn gfctl_agfsel (& mut self) -> GFCTL_AGFSEL_W < GFCTL_SPEC , 9 > { GFCTL_AGFSEL_W :: new (self) } # [doc = "Bit 11 - Analog ... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `GFCTL` reader"] pub type R = crate :: R < GFCTL_SPEC > ; # [doc = "Register `GFCTL` writer"] pub type W = crate :: W < GFCTL_SPEC > ; # [doc = "Field `GFCTL_DGFSEL` reader - Glitch Suppression Pulse Width This field controls the pulse width select for glitch suppression on the SCL and SDA lines. The following values are the glitch suppression values in terms of functional clocks. (Core Domain only)"] pub type GFCTL_DGFSEL_R = crate :: FieldReader < GFCTL_DGFSEL_A > ; # [doc = "Glitch Suppression Pulse Width This field controls the pulse width select for glitch suppression on the SCL and SDA lines. The following values are the glitch suppression values in terms of functional clocks. (Core Domain only)\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum GFCTL_DGFSEL_A { # [doc = "0: DISABLED"] GFCTL_DGFSEL_DISABLED = 0 , # [doc = "1: CLK_1"] GFCTL_DGFSEL_CLK_1 = 1 , # [doc = "2: CLK_2"] GFCTL_DGFSEL_CLK_2 = 2 , # [doc = "3: CLK_3"] GFCTL_DGFSEL_CLK_3 = 3 , # [doc = "4: CLK_4"] GFCTL_DGFSEL_CLK_4 = 4 , # [doc = "5: CLK_8"] GFCTL_DGFSEL_CLK_8 = 5 , # [doc = "6: CLK_16"] GFCTL_DGFSEL_CLK_16 = 6 , # [doc = "7: CLK_31"] GFCTL_DGFSEL_CLK_31 = 7 , } impl From < GFCTL_DGFSEL_A > for u8 { # [inline (always)] fn from (variant : GFCTL_DGFSEL_A) -> Self { variant as _ } } impl crate :: FieldSpec for GFCTL_DGFSEL_A { type Ux = u8 ; } impl GFCTL_DGFSEL_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> GFCTL_DGFSEL_A { match self . bits { 0 => GFCTL_DGFSEL_A :: GFCTL_DGFSEL_DISABLED , 1 => GFCTL_DGFSEL_A :: GFCTL_DGFSEL_CLK_1 , 2 => GFCTL_DGFSEL_A :: GFCTL_DGFSEL_CLK_2 , 3 => GFCTL_DGFSEL_A :: GFCTL_DGFSEL_CLK_3 , 4 => GFCTL_DGFSEL_A :: GFCTL_DGFSEL_CLK_4 , 5 => GFCTL_DGFSEL_A :: GFCTL_DGFSEL_CLK_8 , 6 => GFCTL_DGFSEL_A :: GFCTL_DGFSEL_CLK_16 , 7 => GFCTL_DGFSEL_A :: GFCTL_DGFSEL_CLK_31 , _ => unreachable ! () , } } # [doc = "DISABLED"] # [inline (always)] pub fn is_gfctl_dgfsel_disabled (& self) -> bool { * self == GFCTL_DGFSEL_A :: GFCTL_DGFSEL_DISABLED } # [doc = "CLK_1"] # [inline (always)] pub fn is_gfctl_dgfsel_clk_1 (& self) -> bool { * self == GFCTL_DGFSEL_A :: GFCTL_DGFSEL_CLK_1 } # [doc = "CLK_2"] # [inline (always)] pub fn is_gfctl_dgfsel_clk_2 (& self) -> bool { * self == GFCTL_DGFSEL_A :: GFCTL_DGFSEL_CLK_2 } # [doc = "CLK_3"] # [inline (always)] pub fn is_gfctl_dgfsel_clk_3 (& self) -> bool { * self == GFCTL_DGFSEL_A :: GFCTL_DGFSEL_CLK_3 } # [doc = "CLK_4"] # [inline (always)] pub fn is_gfctl_dgfsel_clk_4 (& self) -> bool { * self == GFCTL_DGFSEL_A :: GFCTL_DGFSEL_CLK_4 } # [doc = "CLK_8"] # [inline (always)] pub fn is_gfctl_dgfsel_clk_8 (& self) -> bool { * self == GFCTL_DGFSEL_A :: GFCTL_DGFSEL_CLK_8 } # [doc = "CLK_16"] # [inline (always)] pub fn is_gfctl_dgfsel_clk_16 (& self) -> bool { * self == GFCTL_DGFSEL_A :: GFCTL_DGFSEL_CLK_16 } # [doc = "CLK_31"] # [inline (always)] pub fn is_gfctl_dgfsel_clk_31 (& self) -> bool { * self == GFCTL_DGFSEL_A :: GFCTL_DGFSEL_CLK_31 } } # [doc = "Field `GFCTL_DGFSEL` writer - Glitch Suppression Pulse Width This field controls the pulse width select for glitch suppression on the SCL and SDA lines. The following values are the glitch suppression values in terms of functional clocks. (Core Domain only)"] pub type GFCTL_DGFSEL_W < 'a , REG , const O : u8 > = crate :: FieldWriterSafe < 'a , REG , 3 , O , GFCTL_DGFSEL_A > ; impl < 'a , REG , const O : u8 > GFCTL_DGFSEL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "DISABLED"] # [inline (always)] pub fn gfctl_dgfsel_disabled (self) -> & 'a mut crate :: W < REG > { self . variant (GFCTL_DGFSEL_A :: GFCTL_DGFSEL_DISABLED) } # [doc = "CLK_1"] # [inline (always)] pub fn gfctl_dgfsel_clk_1 (self) -> & 'a mut crate :: W < REG > { self . variant (GFCTL_DGFSEL_A :: GFCTL_DGFSEL_CLK_1) } # [doc = "CLK_2"] # [inline (always)] pub fn gfctl_dgfsel_clk_2 (self) -> & 'a mut crate :: W < REG > { self . variant (GFCTL_DGFSEL_A :: GFCTL_DGFSEL_CLK_2) } # [doc = "CLK_3"] # [inline (always)] pub fn gfctl_dgfsel_clk_3 (self) -> & 'a mut crate :: W < REG > { self . variant (GFCTL_DGFSEL_A :: GFCTL_DGFSEL_CLK_3) } # [doc = "CLK_4"] # [inline (always)] pub fn gfctl_dgfsel_clk_4 (self) -> & 'a mut crate :: W < REG > { self . variant (GFCTL_DGFSEL_A :: GFCTL_DGFSEL_CLK_4) } # [doc = "CLK_8"] # [inline (always)] pub fn gfctl_dgfsel_clk_8 (self) -> & 'a mut crate :: W < REG > { self . variant (GFCTL_DGFSEL_A :: GFCTL_DGFSEL_CLK_8) } # [doc = "CLK_16"] # [inline (always)] pub fn gfctl_dgfsel_clk_16 (self) -> & 'a mut crate :: W < REG > { self . variant (GFCTL_DGFSEL_A :: GFCTL_DGFSEL_CLK_16) } # [doc = "CLK_31"] # [inline (always)] pub fn gfctl_dgfsel_clk_31 (self) -> & 'a mut crate :: W < REG > { self . variant (GFCTL_DGFSEL_A :: GFCTL_DGFSEL_CLK_31) } } # [doc = "Field `GFCTL_AGFEN` reader - Analog Glitch Suppression Enable"] pub type GFCTL_AGFEN_R = crate :: BitReader < GFCTL_AGFEN_A > ; # [doc = "Analog Glitch Suppression Enable\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum GFCTL_AGFEN_A { # [doc = "0: DISABLE"] GFCTL_AGFEN_DISABLE = 0 , # [doc = "1: ENABLE"] GFCTL_AGFEN_ENABLE = 1 , } impl From < GFCTL_AGFEN_A > for bool { # [inline (always)] fn from (variant : GFCTL_AGFEN_A) -> Self { variant as u8 != 0 } } impl GFCTL_AGFEN_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> GFCTL_AGFEN_A { match self . bits { false => GFCTL_AGFEN_A :: GFCTL_AGFEN_DISABLE , true => GFCTL_AGFEN_A :: GFCTL_AGFEN_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_gfctl_agfen_disable (& self) -> bool { * self == GFCTL_AGFEN_A :: GFCTL_AGFEN_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_gfctl_agfen_enable (& self) -> bool { * self == GFCTL_AGFEN_A :: GFCTL_AGFEN_ENABLE } } # [doc = "Field `GFCTL_AGFEN` writer - Analog Glitch Suppression Enable"] pub type GFCTL_AGFEN_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , GFCTL_AGFEN_A > ; impl < 'a , REG , const O : u8 > GFCTL_AGFEN_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn gfctl_agfen_disable (self) -> & 'a mut crate :: W < REG > { self . variant (GFCTL_AGFEN_A :: GFCTL_AGFEN_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn gfctl_agfen_enable (self) -> & 'a mut crate :: W < REG > { self . variant (GFCTL_AGFEN_A :: GFCTL_AGFEN_ENABLE) } } # [doc = "Field `GFCTL_AGFSEL` reader - Analog Glitch Suppression Pulse Width This field controls the pulse width select for the analog glitch suppression on SCL and SDA lines. See device datasheet for exact values. (ULP I2C only)"] pub type GFCTL_AGFSEL_R = crate :: FieldReader < GFCTL_AGFSEL_A > ; # [doc = "Analog Glitch Suppression Pulse Width This field controls the pulse width select for the analog glitch suppression on SCL and SDA lines. See device datasheet for exact values. (ULP I2C only)\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum GFCTL_AGFSEL_A { # [doc = "0: AGLIT_5"] GFCTL_AGFSEL_AGLIT_5 = 0 , # [doc = "1: AGLIT_10"] GFCTL_AGFSEL_AGLIT_10 = 1 , # [doc = "2: AGLIT_25"] GFCTL_AGFSEL_AGLIT_25 = 2 , # [doc = "3: AGLIT_50"] GFCTL_AGFSEL_AGLIT_50 = 3 , } impl From < GFCTL_AGFSEL_A > for u8 { # [inline (always)] fn from (variant : GFCTL_AGFSEL_A) -> Self { variant as _ } } impl crate :: FieldSpec for GFCTL_AGFSEL_A { type Ux = u8 ; } impl GFCTL_AGFSEL_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> GFCTL_AGFSEL_A { match self . bits { 0 => GFCTL_AGFSEL_A :: GFCTL_AGFSEL_AGLIT_5 , 1 => GFCTL_AGFSEL_A :: GFCTL_AGFSEL_AGLIT_10 , 2 => GFCTL_AGFSEL_A :: GFCTL_AGFSEL_AGLIT_25 , 3 => GFCTL_AGFSEL_A :: GFCTL_AGFSEL_AGLIT_50 , _ => unreachable ! () , } } # [doc = "AGLIT_5"] # [inline (always)] pub fn is_gfctl_agfsel_aglit_5 (& self) -> bool { * self == GFCTL_AGFSEL_A :: GFCTL_AGFSEL_AGLIT_5 } # [doc = "AGLIT_10"] # [inline (always)] pub fn is_gfctl_agfsel_aglit_10 (& self) -> bool { * self == GFCTL_AGFSEL_A :: GFCTL_AGFSEL_AGLIT_10 } # [doc = "AGLIT_25"] # [inline (always)] pub fn is_gfctl_agfsel_aglit_25 (& self) -> bool { * self == GFCTL_AGFSEL_A :: GFCTL_AGFSEL_AGLIT_25 } # [doc = "AGLIT_50"] # [inline (always)] pub fn is_gfctl_agfsel_aglit_50 (& self) -> bool { * self == GFCTL_AGFSEL_A :: GFCTL_AGFSEL_AGLIT_50 } } # [doc = "Field `GFCTL_AGFSEL` writer - Analog Glitch Suppression Pulse Width This field controls the pulse width select for the analog glitch suppression on SCL and SDA lines. See device datasheet for exact values. (ULP I2C only)"] pub type GFCTL_AGFSEL_W < 'a , REG , const O : u8 > = crate :: FieldWriterSafe < 'a , REG , 2 , O , GFCTL_AGFSEL_A > ; impl < 'a , REG , const O : u8 > GFCTL_AGFSEL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "AGLIT_5"] # [inline (always)] pub fn gfctl_agfsel_aglit_5 (self) -> & 'a mut crate :: W < REG > { self . variant (GFCTL_AGFSEL_A :: GFCTL_AGFSEL_AGLIT_5) } # [doc = "AGLIT_10"] # [inline (always)] pub fn gfctl_agfsel_aglit_10 (self) -> & 'a mut crate :: W < REG > { self . variant (GFCTL_AGFSEL_A :: GFCTL_AGFSEL_AGLIT_10) } # [doc = "AGLIT_25"] # [inline (always)] pub fn gfctl_agfsel_aglit_25 (self) -> & 'a mut crate :: W < REG > { self . variant (GFCTL_AGFSEL_A :: GFCTL_AGFSEL_AGLIT_25) } # [doc = "AGLIT_50"] # [inline (always)] pub fn gfctl_agfsel_aglit_50 (self) -> & 'a mut crate :: W < REG > { self . variant (GFCTL_AGFSEL_A :: GFCTL_AGFSEL_AGLIT_50) } } # [doc = "Field `GFCTL_CHAIN` reader - Analog and digital noise filters chaining enable."] pub type GFCTL_CHAIN_R = crate :: BitReader < GFCTL_CHAIN_A > ; # [doc = "Analog and digital noise filters chaining enable.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum GFCTL_CHAIN_A { # [doc = "0: DISABLE"] GFCTL_CHAIN_DISABLE = 0 , # [doc = "1: ENABLE"] GFCTL_CHAIN_ENABLE = 1 , } impl From < GFCTL_CHAIN_A > for bool { # [inline (always)] fn from (variant : GFCTL_CHAIN_A) -> Self { variant as u8 != 0 } } impl GFCTL_CHAIN_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> GFCTL_CHAIN_A { match self . bits { false => GFCTL_CHAIN_A :: GFCTL_CHAIN_DISABLE , true => GFCTL_CHAIN_A :: GFCTL_CHAIN_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_gfctl_chain_disable (& self) -> bool { * self == GFCTL_CHAIN_A :: GFCTL_CHAIN_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_gfctl_chain_enable (& self) -> bool { * self == GFCTL_CHAIN_A :: GFCTL_CHAIN_ENABLE } } # [doc = "Field `GFCTL_CHAIN` writer - Analog and digital noise filters chaining enable."] pub type GFCTL_CHAIN_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , GFCTL_CHAIN_A > ; impl < 'a , REG , const O : u8 > GFCTL_CHAIN_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn gfctl_chain_disable (self) -> & 'a mut crate :: W < REG > { self . variant (GFCTL_CHAIN_A :: GFCTL_CHAIN_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn gfctl_chain_enable (self) -> & 'a mut crate :: W < REG > { self . variant (GFCTL_CHAIN_A :: GFCTL_CHAIN_ENABLE) } } impl R { # [doc = "Bits 0:2 - Glitch Suppression Pulse Width This field controls the pulse width select for glitch suppression on the SCL and SDA lines. The following values are the glitch suppression values in terms of functional clocks. (Core Domain only)"] # [inline (always)] pub fn gfctl_dgfsel (& self) -> GFCTL_DGFSEL_R { GFCTL_DGFSEL_R :: new ((self . bits & 7) as u8) } # [doc = "Bit 8 - Analog Glitch Suppression Enable"] # [inline (always)] pub fn gfctl_agfen (& self) -> GFCTL_AGFEN_R { GFCTL_AGFEN_R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bits 9:10 - Analog Glitch Suppression Pulse Width This field controls the pulse width select for the analog glitch suppression on SCL and SDA lines. See device datasheet for exact values. (ULP I2C only)"] # [inline (always)] pub fn gfctl_agfsel (& self) -> GFCTL_AGFSEL_R { GFCTL_AGFSEL_R :: new (((self . bits >> 9) & 3) as u8) } # [doc = "Bit 11 - Analog and digital noise filters chaining enable."] # [inline (always)] pub fn gfctl_chain (& self) -> GFCTL_CHAIN_R { GFCTL_CHAIN_R :: new (((self . bits >> 11) & 1) != 0) } } impl W { # [doc = "Bits 0:2 - Glitch Suppression Pulse Width This field controls the pulse width select for glitch suppression on the SCL and SDA lines. The following values are the glitch suppression values in terms of functional clocks. (Core Domain only)"] # [inline (always)] # [must_use] pub fn gfctl_dgfsel (& mut self) -> GFCTL_DGFSEL_W < GFCTL_SPEC , 0 > { GFCTL_DGFSEL_W :: new (self) } # [doc = "Bit 8 - Analog Glitch Suppression Enable"] # [inline (always)] # [must_use] pub fn gfctl_agfen (& mut self) -> GFCTL_AGFEN_W < GFCTL_SPEC , 8 > { GFCTL_AGFEN_W :: new (self) } # [doc = "Bits 9:10 - Analog Glitch Suppression Pulse Width This field controls the pulse width select for the analog glitch suppression on SCL and SDA lines. See device datasheet for exact values. (ULP I2C only)"] # [inline (always)] # [must_use] pub fn gfctl_agfsel (& mut self) -> GFCTL_AGFSEL_W <'_, GFCTL_SPEC , 9 > { GFCTL_AGFSEL_W :: new (self) } # [doc = "Bit 11 - Analog and digital noise filters chaining enable."] # [inline (always)] # [must_use] pub fn gfctl_chain (& mut self) -> GFCTL_CHAIN_W < GFCTL_SPEC , 11 > { GFCTL_CHAIN_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "I2C Glitch Filter Control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gfctl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gfctl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GFCTL_SPEC ; impl crate :: RegisterSpec for GFCTL_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`gfctl::R`](R) reader structure"] impl crate :: Readable for GFCTL_SPEC { } # [doc = "`write(|w| ..)` method takes [`gfctl::W`](W) writer structure"] impl crate :: Writable for GFCTL_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets GFCTL to value 0"] impl crate :: Resettable for GFCTL_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/spi0/int_event0_imask.rs:1:24451 [INFO] [stdout] | [INFO] [stdout] 1 | ..._rxfifo_ovf (& mut self) -> INT_EVENT0_IMASK_RXFIFO_OVF_W < INT_EVENT0_IMASK_SPEC , 0 > { INT_EVENT0_IMASK_RXFIFO_OVF_W :: new (self) ... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `INT_EVENT0_IMASK` reader"] pub type R = crate :: R < INT_EVENT0_IMASK_SPEC > ; # [doc = "Register `INT_EVENT0_IMASK` writer"] pub type W = crate :: W < INT_EVENT0_IMASK_SPEC > ; # [doc = "Field `INT_EVENT0_IMASK_RXFIFO_OVF` reader - RXFIFO overflow event mask."] pub type INT_EVENT0_IMASK_RXFIFO_OVF_R = crate :: BitReader < INT_EVENT0_IMASK_RXFIFO_OVF_A > ; # [doc = "RXFIFO overflow event mask.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_RXFIFO_OVF_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_RXFIFO_OVF_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_RXFIFO_OVF_SET = 1 , } impl From < INT_EVENT0_IMASK_RXFIFO_OVF_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_RXFIFO_OVF_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_RXFIFO_OVF_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_RXFIFO_OVF_A { match self . bits { false => INT_EVENT0_IMASK_RXFIFO_OVF_A :: INT_EVENT0_IMASK_RXFIFO_OVF_CLR , true => INT_EVENT0_IMASK_RXFIFO_OVF_A :: INT_EVENT0_IMASK_RXFIFO_OVF_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_rxfifo_ovf_clr (& self) -> bool { * self == INT_EVENT0_IMASK_RXFIFO_OVF_A :: INT_EVENT0_IMASK_RXFIFO_OVF_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_rxfifo_ovf_set (& self) -> bool { * self == INT_EVENT0_IMASK_RXFIFO_OVF_A :: INT_EVENT0_IMASK_RXFIFO_OVF_SET } } # [doc = "Field `INT_EVENT0_IMASK_RXFIFO_OVF` writer - RXFIFO overflow event mask."] pub type INT_EVENT0_IMASK_RXFIFO_OVF_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_RXFIFO_OVF_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_RXFIFO_OVF_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_rxfifo_ovf_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXFIFO_OVF_A :: INT_EVENT0_IMASK_RXFIFO_OVF_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_rxfifo_ovf_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXFIFO_OVF_A :: INT_EVENT0_IMASK_RXFIFO_OVF_SET) } } # [doc = "Field `INT_EVENT0_IMASK_PER` reader - Parity error event mask."] pub type INT_EVENT0_IMASK_PER_R = crate :: BitReader < INT_EVENT0_IMASK_PER_A > ; # [doc = "Parity error event mask.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_PER_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_PER_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_PER_SET = 1 , } impl From < INT_EVENT0_IMASK_PER_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_PER_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_PER_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_PER_A { match self . bits { false => INT_EVENT0_IMASK_PER_A :: INT_EVENT0_IMASK_PER_CLR , true => INT_EVENT0_IMASK_PER_A :: INT_EVENT0_IMASK_PER_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_per_clr (& self) -> bool { * self == INT_EVENT0_IMASK_PER_A :: INT_EVENT0_IMASK_PER_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_per_set (& self) -> bool { * self == INT_EVENT0_IMASK_PER_A :: INT_EVENT0_IMASK_PER_SET } } # [doc = "Field `INT_EVENT0_IMASK_PER` writer - Parity error event mask."] pub type INT_EVENT0_IMASK_PER_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_PER_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_PER_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_per_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_PER_A :: INT_EVENT0_IMASK_PER_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_per_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_PER_A :: INT_EVENT0_IMASK_PER_SET) } } # [doc = "Field `INT_EVENT0_IMASK_RTOUT` reader - Enable SPI Receive Time-Out event mask."] pub type INT_EVENT0_IMASK_RTOUT_R = crate :: BitReader < INT_EVENT0_IMASK_RTOUT_A > ; # [doc = "Enable SPI Receive Time-Out event mask.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_RTOUT_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_RTOUT_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_RTOUT_SET = 1 , } impl From < INT_EVENT0_IMASK_RTOUT_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_RTOUT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_RTOUT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_RTOUT_A { match self . bits { false => INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_CLR , true => INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_rtout_clr (& self) -> bool { * self == INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_rtout_set (& self) -> bool { * self == INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_SET } } # [doc = "Field `INT_EVENT0_IMASK_RTOUT` writer - Enable SPI Receive Time-Out event mask."] pub type INT_EVENT0_IMASK_RTOUT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_RTOUT_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_RTOUT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_rtout_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_rtout_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_SET) } } # [doc = "Field `INT_EVENT0_IMASK_RX` reader - Receive FIFO event.This interrupt is set if the selected Receive FIFO level has been reached"] pub type INT_EVENT0_IMASK_RX_R = crate :: BitReader < INT_EVENT0_IMASK_RX_A > ; # [doc = "Receive FIFO event.This interrupt is set if the selected Receive FIFO level has been reached\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_RX_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_RX_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_RX_SET = 1 , } impl From < INT_EVENT0_IMASK_RX_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_RX_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_RX_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_RX_A { match self . bits { false => INT_EVENT0_IMASK_RX_A :: INT_EVENT0_IMASK_RX_CLR , true => INT_EVENT0_IMASK_RX_A :: INT_EVENT0_IMASK_RX_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_rx_clr (& self) -> bool { * self == INT_EVENT0_IMASK_RX_A :: INT_EVENT0_IMASK_RX_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_rx_set (& self) -> bool { * self == INT_EVENT0_IMASK_RX_A :: INT_EVENT0_IMASK_RX_SET } } # [doc = "Field `INT_EVENT0_IMASK_RX` writer - Receive FIFO event.This interrupt is set if the selected Receive FIFO level has been reached"] pub type INT_EVENT0_IMASK_RX_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_RX_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_RX_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_rx_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RX_A :: INT_EVENT0_IMASK_RX_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_rx_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RX_A :: INT_EVENT0_IMASK_RX_SET) } } # [doc = "Field `INT_EVENT0_IMASK_TX` reader - Transmit FIFO event mask."] pub type INT_EVENT0_IMASK_TX_R = crate :: BitReader < INT_EVENT0_IMASK_TX_A > ; # [doc = "Transmit FIFO event mask.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_TX_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_TX_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_TX_SET = 1 , } impl From < INT_EVENT0_IMASK_TX_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_TX_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_TX_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_TX_A { match self . bits { false => INT_EVENT0_IMASK_TX_A :: INT_EVENT0_IMASK_TX_CLR , true => INT_EVENT0_IMASK_TX_A :: INT_EVENT0_IMASK_TX_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_tx_clr (& self) -> bool { * self == INT_EVENT0_IMASK_TX_A :: INT_EVENT0_IMASK_TX_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_tx_set (& self) -> bool { * self == INT_EVENT0_IMASK_TX_A :: INT_EVENT0_IMASK_TX_SET } } # [doc = "Field `INT_EVENT0_IMASK_TX` writer - Transmit FIFO event mask."] pub type INT_EVENT0_IMASK_TX_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_TX_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_TX_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_tx_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_TX_A :: INT_EVENT0_IMASK_TX_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_tx_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_TX_A :: INT_EVENT0_IMASK_TX_SET) } } # [doc = "Field `INT_EVENT0_IMASK_TXEMPTY` reader - Transmit FIFO Empty event mask."] pub type INT_EVENT0_IMASK_TXEMPTY_R = crate :: BitReader < INT_EVENT0_IMASK_TXEMPTY_A > ; # [doc = "Transmit FIFO Empty event mask.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_TXEMPTY_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_TXEMPTY_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_TXEMPTY_SET = 1 , } impl From < INT_EVENT0_IMASK_TXEMPTY_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_TXEMPTY_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_TXEMPTY_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_TXEMPTY_A { match self . bits { false => INT_EVENT0_IMASK_TXEMPTY_A :: INT_EVENT0_IMASK_TXEMPTY_CLR , true => INT_EVENT0_IMASK_TXEMPTY_A :: INT_EVENT0_IMASK_TXEMPTY_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_txempty_clr (& self) -> bool { * self == INT_EVENT0_IMASK_TXEMPTY_A :: INT_EVENT0_IMASK_TXEMPTY_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_txempty_set (& self) -> bool { * self == INT_EVENT0_IMASK_TXEMPTY_A :: INT_EVENT0_IMASK_TXEMPTY_SET } } # [doc = "Field `INT_EVENT0_IMASK_TXEMPTY` writer - Transmit FIFO Empty event mask."] pub type INT_EVENT0_IMASK_TXEMPTY_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_TXEMPTY_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_TXEMPTY_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_txempty_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_TXEMPTY_A :: INT_EVENT0_IMASK_TXEMPTY_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_txempty_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_TXEMPTY_A :: INT_EVENT0_IMASK_TXEMPTY_SET) } } # [doc = "Field `INT_EVENT0_IMASK_IDLE` reader - SPI Idle event mask."] pub type INT_EVENT0_IMASK_IDLE_R = crate :: BitReader < INT_EVENT0_IMASK_IDLE_A > ; # [doc = "SPI Idle event mask.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_IDLE_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_IDLE_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_IDLE_SET = 1 , } impl From < INT_EVENT0_IMASK_IDLE_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_IDLE_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_IDLE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_IDLE_A { match self . bits { false => INT_EVENT0_IMASK_IDLE_A :: INT_EVENT0_IMASK_IDLE_CLR , true => INT_EVENT0_IMASK_IDLE_A :: INT_EVENT0_IMASK_IDLE_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_idle_clr (& self) -> bool { * self == INT_EVENT0_IMASK_IDLE_A :: INT_EVENT0_IMASK_IDLE_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_idle_set (& self) -> bool { * self == INT_EVENT0_IMASK_IDLE_A :: INT_EVENT0_IMASK_IDLE_SET } } # [doc = "Field `INT_EVENT0_IMASK_IDLE` writer - SPI Idle event mask."] pub type INT_EVENT0_IMASK_IDLE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_IDLE_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_IDLE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_idle_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_IDLE_A :: INT_EVENT0_IMASK_IDLE_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_idle_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_IDLE_A :: INT_EVENT0_IMASK_IDLE_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DMA_DONE_RX` reader - DMA Done 1 event for RX event mask."] pub type INT_EVENT0_IMASK_DMA_DONE_RX_R = crate :: BitReader < INT_EVENT0_IMASK_DMA_DONE_RX_A > ; # [doc = "DMA Done 1 event for RX event mask.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DMA_DONE_RX_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DMA_DONE_RX_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DMA_DONE_RX_SET = 1 , } impl From < INT_EVENT0_IMASK_DMA_DONE_RX_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DMA_DONE_RX_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DMA_DONE_RX_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DMA_DONE_RX_A { match self . bits { false => INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_CLR , true => INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dma_done_rx_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dma_done_rx_set (& self) -> bool { * self == INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_SET } } # [doc = "Field `INT_EVENT0_IMASK_DMA_DONE_RX` writer - DMA Done 1 event for RX event mask."] pub type INT_EVENT0_IMASK_DMA_DONE_RX_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DMA_DONE_RX_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DMA_DONE_RX_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dma_done_rx_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dma_done_rx_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DMA_DONE_TX` reader - DMA Done 1 event for TX event mask."] pub type INT_EVENT0_IMASK_DMA_DONE_TX_R = crate :: BitReader < INT_EVENT0_IMASK_DMA_DONE_TX_A > ; # [doc = "DMA Done 1 event for TX event mask.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DMA_DONE_TX_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DMA_DONE_TX_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DMA_DONE_TX_SET = 1 , } impl From < INT_EVENT0_IMASK_DMA_DONE_TX_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DMA_DONE_TX_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DMA_DONE_TX_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DMA_DONE_TX_A { match self . bits { false => INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_CLR , true => INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dma_done_tx_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dma_done_tx_set (& self) -> bool { * self == INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_SET } } # [doc = "Field `INT_EVENT0_IMASK_DMA_DONE_TX` writer - DMA Done 1 event for TX event mask."] pub type INT_EVENT0_IMASK_DMA_DONE_TX_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DMA_DONE_TX_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DMA_DONE_TX_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dma_done_tx_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dma_done_tx_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_SET) } } # [doc = "Field `INT_EVENT0_IMASK_TXFIFO_UNF` reader - TX FIFO underflow interrupt mask"] pub type INT_EVENT0_IMASK_TXFIFO_UNF_R = crate :: BitReader < INT_EVENT0_IMASK_TXFIFO_UNF_A > ; # [doc = "TX FIFO underflow interrupt mask\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_TXFIFO_UNF_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_TXFIFO_UNF_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_TXFIFO_UNF_SET = 1 , } impl From < INT_EVENT0_IMASK_TXFIFO_UNF_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_TXFIFO_UNF_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_TXFIFO_UNF_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_TXFIFO_UNF_A { match self . bits { false => INT_EVENT0_IMASK_TXFIFO_UNF_A :: INT_EVENT0_IMASK_TXFIFO_UNF_CLR , true => INT_EVENT0_IMASK_TXFIFO_UNF_A :: INT_EVENT0_IMASK_TXFIFO_UNF_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_txfifo_unf_clr (& self) -> bool { * self == INT_EVENT0_IMASK_TXFIFO_UNF_A :: INT_EVENT0_IMASK_TXFIFO_UNF_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_txfifo_unf_set (& self) -> bool { * self == INT_EVENT0_IMASK_TXFIFO_UNF_A :: INT_EVENT0_IMASK_TXFIFO_UNF_SET } } # [doc = "Field `INT_EVENT0_IMASK_TXFIFO_UNF` writer - TX FIFO underflow interrupt mask"] pub type INT_EVENT0_IMASK_TXFIFO_UNF_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_TXFIFO_UNF_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_TXFIFO_UNF_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_txfifo_unf_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_TXFIFO_UNF_A :: INT_EVENT0_IMASK_TXFIFO_UNF_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_txfifo_unf_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_TXFIFO_UNF_A :: INT_EVENT0_IMASK_TXFIFO_UNF_SET) } } # [doc = "Field `INT_EVENT0_IMASK_RXFULL` reader - RX FIFO Full Interrupt Mask"] pub type INT_EVENT0_IMASK_RXFULL_R = crate :: BitReader < INT_EVENT0_IMASK_RXFULL_A > ; # [doc = "RX FIFO Full Interrupt Mask\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_RXFULL_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_RXFULL_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_RXFULL_SET = 1 , } impl From < INT_EVENT0_IMASK_RXFULL_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_RXFULL_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_RXFULL_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_RXFULL_A { match self . bits { false => INT_EVENT0_IMASK_RXFULL_A :: INT_EVENT0_IMASK_RXFULL_CLR , true => INT_EVENT0_IMASK_RXFULL_A :: INT_EVENT0_IMASK_RXFULL_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_rxfull_clr (& self) -> bool { * self == INT_EVENT0_IMASK_RXFULL_A :: INT_EVENT0_IMASK_RXFULL_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_rxfull_set (& self) -> bool { * self == INT_EVENT0_IMASK_RXFULL_A :: INT_EVENT0_IMASK_RXFULL_SET } } # [doc = "Field `INT_EVENT0_IMASK_RXFULL` writer - RX FIFO Full Interrupt Mask"] pub type INT_EVENT0_IMASK_RXFULL_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_RXFULL_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_RXFULL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_rxfull_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXFULL_A :: INT_EVENT0_IMASK_RXFULL_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_rxfull_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXFULL_A :: INT_EVENT0_IMASK_RXFULL_SET) } } impl R { # [doc = "Bit 0 - RXFIFO overflow event mask."] # [inline (always)] pub fn int_event0_imask_rxfifo_ovf (& self) -> INT_EVENT0_IMASK_RXFIFO_OVF_R { INT_EVENT0_IMASK_RXFIFO_OVF_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - Parity error event mask."] # [inline (always)] pub fn int_event0_imask_per (& self) -> INT_EVENT0_IMASK_PER_R { INT_EVENT0_IMASK_PER_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - Enable SPI Receive Time-Out event mask."] # [inline (always)] pub fn int_event0_imask_rtout (& self) -> INT_EVENT0_IMASK_RTOUT_R { INT_EVENT0_IMASK_RTOUT_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - Receive FIFO event.This interrupt is set if the selected Receive FIFO level has been reached"] # [inline (always)] pub fn int_event0_imask_rx (& self) -> INT_EVENT0_IMASK_RX_R { INT_EVENT0_IMASK_RX_R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - Transmit FIFO event mask."] # [inline (always)] pub fn int_event0_imask_tx (& self) -> INT_EVENT0_IMASK_TX_R { INT_EVENT0_IMASK_TX_R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - Transmit FIFO Empty event mask."] # [inline (always)] pub fn int_event0_imask_txempty (& self) -> INT_EVENT0_IMASK_TXEMPTY_R { INT_EVENT0_IMASK_TXEMPTY_R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - SPI Idle event mask."] # [inline (always)] pub fn int_event0_imask_idle (& self) -> INT_EVENT0_IMASK_IDLE_R { INT_EVENT0_IMASK_IDLE_R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - DMA Done 1 event for RX event mask."] # [inline (always)] pub fn int_event0_imask_dma_done_rx (& self) -> INT_EVENT0_IMASK_DMA_DONE_RX_R { INT_EVENT0_IMASK_DMA_DONE_RX_R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - DMA Done 1 event for TX event mask."] # [inline (always)] pub fn int_event0_imask_dma_done_tx (& self) -> INT_EVENT0_IMASK_DMA_DONE_TX_R { INT_EVENT0_IMASK_DMA_DONE_TX_R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - TX FIFO underflow interrupt mask"] # [inline (always)] pub fn int_event0_imask_txfifo_unf (& self) -> INT_EVENT0_IMASK_TXFIFO_UNF_R { INT_EVENT0_IMASK_TXFIFO_UNF_R :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - RX FIFO Full Interrupt Mask"] # [inline (always)] pub fn int_event0_imask_rxfull (& self) -> INT_EVENT0_IMASK_RXFULL_R { INT_EVENT0_IMASK_RXFULL_R :: new (((self . bits >> 10) & 1) != 0) } } impl W { # [doc = "Bit 0 - RXFIFO overflow event mask."] # [inline (always)] # [must_use] pub fn int_event0_imask_rxfifo_ovf (& mut self) -> INT_EVENT0_IMASK_RXFIFO_OVF_W <'_, INT_EVENT0_IMASK_SPEC , 0 > { INT_EVENT0_IMASK_RXFIFO_OVF_W :: new (self) } # [doc = "Bit 1 - Parity error event mask."] # [inline (always)] # [must_use] pub fn int_event0_imask_per (& mut self) -> INT_EVENT0_IMASK_PER_W < INT_EVENT0_IMASK_SPEC , 1 > { INT_EVENT0_IMASK_PER_W :: new (self) } # [doc = "Bit 2 - Enable SPI Receive Time-Out event mask."] # [inline (always)] # [must_use] pub fn int_event0_imask_rtout (& mut self) -> INT_EVENT0_IMASK_RTOUT_W < INT_EVENT0_IMASK_SPEC , 2 > { INT_EVENT0_IMASK_RTOUT_W :: new (self) } # [doc = "Bit 3 - Receive FIFO event.This interrupt is set if the selected Receive FIFO level has been reached"] # [inline (always)] # [must_use] pub fn int_event0_imask_rx (& mut self) -> INT_EVENT0_IMASK_RX_W < INT_EVENT0_IMASK_SPEC , 3 > { INT_EVENT0_IMASK_RX_W :: new (self) } # [doc = "Bit 4 - Transmit FIFO event mask."] # [inline (always)] # [must_use] pub fn int_event0_imask_tx (& mut self) -> INT_EVENT0_IMASK_TX_W < INT_EVENT0_IMASK_SPEC , 4 > { INT_EVENT0_IMASK_TX_W :: new (self) } # [doc = "Bit 5 - Transmit FIFO Empty event mask."] # [inline (always)] # [must_use] pub fn int_event0_imask_txempty (& mut self) -> INT_EVENT0_IMASK_TXEMPTY_W < INT_EVENT0_IMASK_SPEC , 5 > { INT_EVENT0_IMASK_TXEMPTY_W :: new (self) } # [doc = "Bit 6 - SPI Idle event mask."] # [inline (always)] # [must_use] pub fn int_event0_imask_idle (& mut self) -> INT_EVENT0_IMASK_IDLE_W < INT_EVENT0_IMASK_SPEC , 6 > { INT_EVENT0_IMASK_IDLE_W :: new (self) } # [doc = "Bit 7 - DMA Done 1 event for RX event mask."] # [inline (always)] # [must_use] pub fn int_event0_imask_dma_done_rx (& mut self) -> INT_EVENT0_IMASK_DMA_DONE_RX_W < INT_EVENT0_IMASK_SPEC , 7 > { INT_EVENT0_IMASK_DMA_DONE_RX_W :: new (self) } # [doc = "Bit 8 - DMA Done 1 event for TX event mask."] # [inline (always)] # [must_use] pub fn int_event0_imask_dma_done_tx (& mut self) -> INT_EVENT0_IMASK_DMA_DONE_TX_W < INT_EVENT0_IMASK_SPEC , 8 > { INT_EVENT0_IMASK_DMA_DONE_TX_W :: new (self) } # [doc = "Bit 9 - TX FIFO underflow interrupt mask"] # [inline (always)] # [must_use] pub fn int_event0_imask_txfifo_unf (& mut self) -> INT_EVENT0_IMASK_TXFIFO_UNF_W < INT_EVENT0_IMASK_SPEC , 9 > { INT_EVENT0_IMASK_TXFIFO_UNF_W :: new (self) } # [doc = "Bit 10 - RX FIFO Full Interrupt Mask"] # [inline (always)] # [must_use] pub fn int_event0_imask_rxfull (& mut self) -> INT_EVENT0_IMASK_RXFULL_W < INT_EVENT0_IMASK_SPEC , 10 > { INT_EVENT0_IMASK_RXFULL_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Interrupt mask\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_event0_imask::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_event0_imask::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct INT_EVENT0_IMASK_SPEC ; impl crate :: RegisterSpec for INT_EVENT0_IMASK_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`int_event0_imask::R`](R) reader structure"] impl crate :: Readable for INT_EVENT0_IMASK_SPEC { } # [doc = "`write(|w| ..)` method takes [`int_event0_imask::W`](W) writer structure"] impl crate :: Writable for INT_EVENT0_IMASK_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets INT_EVENT0_IMASK to value 0"] impl crate :: Resettable for INT_EVENT0_IMASK_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/timg4/ccctl_01.rs:1:35861 [INFO] [stdout] | [INFO] [stdout] 1 | ... fn ccctl_01_cc2seld (& mut self) -> CCCTL_01_CC2SELD_W < CCCTL_01_SPEC , 29 > { CCCTL_01_CC2SELD_W :: new (self) } # [doc = r" Writes... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `CCCTL_01[%s]` reader"] pub type R = crate :: R < CCCTL_01_SPEC > ; # [doc = "Register `CCCTL_01[%s]` writer"] pub type W = crate :: W < CCCTL_01_SPEC > ; # [doc = "Field `CCCTL_01_CCOND` reader - Capture Condition. #br# Specifies the condition that generates a capture pulse. 4h-Fh = Reserved"] pub type CCCTL_01_CCOND_R = crate :: FieldReader < CCCTL_01_CCOND_A > ; # [doc = "Capture Condition. #br# Specifies the condition that generates a capture pulse. 4h-Fh = Reserved\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum CCCTL_01_CCOND_A { # [doc = "0: NOCAPTURE"] CCCTL_01_CCOND_NOCAPTURE = 0 , # [doc = "1: CC_TRIG_RISE"] CCCTL_01_CCOND_CC_TRIG_RISE = 1 , # [doc = "2: CC_TRIG_FALL"] CCCTL_01_CCOND_CC_TRIG_FALL = 2 , # [doc = "3: CC_TRIG_EDGE"] CCCTL_01_CCOND_CC_TRIG_EDGE = 3 , } impl From < CCCTL_01_CCOND_A > for u8 { # [inline (always)] fn from (variant : CCCTL_01_CCOND_A) -> Self { variant as _ } } impl crate :: FieldSpec for CCCTL_01_CCOND_A { type Ux = u8 ; } impl CCCTL_01_CCOND_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < CCCTL_01_CCOND_A > { match self . bits { 0 => Some (CCCTL_01_CCOND_A :: CCCTL_01_CCOND_NOCAPTURE) , 1 => Some (CCCTL_01_CCOND_A :: CCCTL_01_CCOND_CC_TRIG_RISE) , 2 => Some (CCCTL_01_CCOND_A :: CCCTL_01_CCOND_CC_TRIG_FALL) , 3 => Some (CCCTL_01_CCOND_A :: CCCTL_01_CCOND_CC_TRIG_EDGE) , _ => None , } } # [doc = "NOCAPTURE"] # [inline (always)] pub fn is_ccctl_01_ccond_nocapture (& self) -> bool { * self == CCCTL_01_CCOND_A :: CCCTL_01_CCOND_NOCAPTURE } # [doc = "CC_TRIG_RISE"] # [inline (always)] pub fn is_ccctl_01_ccond_cc_trig_rise (& self) -> bool { * self == CCCTL_01_CCOND_A :: CCCTL_01_CCOND_CC_TRIG_RISE } # [doc = "CC_TRIG_FALL"] # [inline (always)] pub fn is_ccctl_01_ccond_cc_trig_fall (& self) -> bool { * self == CCCTL_01_CCOND_A :: CCCTL_01_CCOND_CC_TRIG_FALL } # [doc = "CC_TRIG_EDGE"] # [inline (always)] pub fn is_ccctl_01_ccond_cc_trig_edge (& self) -> bool { * self == CCCTL_01_CCOND_A :: CCCTL_01_CCOND_CC_TRIG_EDGE } } # [doc = "Field `CCCTL_01_CCOND` writer - Capture Condition. #br# Specifies the condition that generates a capture pulse. 4h-Fh = Reserved"] pub type CCCTL_01_CCOND_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 3 , O , CCCTL_01_CCOND_A > ; impl < 'a , REG , const O : u8 > CCCTL_01_CCOND_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "NOCAPTURE"] # [inline (always)] pub fn ccctl_01_ccond_nocapture (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CCOND_A :: CCCTL_01_CCOND_NOCAPTURE) } # [doc = "CC_TRIG_RISE"] # [inline (always)] pub fn ccctl_01_ccond_cc_trig_rise (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CCOND_A :: CCCTL_01_CCOND_CC_TRIG_RISE) } # [doc = "CC_TRIG_FALL"] # [inline (always)] pub fn ccctl_01_ccond_cc_trig_fall (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CCOND_A :: CCCTL_01_CCOND_CC_TRIG_FALL) } # [doc = "CC_TRIG_EDGE"] # [inline (always)] pub fn ccctl_01_ccond_cc_trig_edge (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CCOND_A :: CCCTL_01_CCOND_CC_TRIG_EDGE) } } # [doc = "Field `CCCTL_01_ACOND` reader - Advance Condition. #br# Specifies the condition that generates an advance pulse. 6h-Fh = Reserved"] pub type CCCTL_01_ACOND_R = crate :: FieldReader < CCCTL_01_ACOND_A > ; # [doc = "Advance Condition. #br# Specifies the condition that generates an advance pulse. 6h-Fh = Reserved\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum CCCTL_01_ACOND_A { # [doc = "0: TIMCLK"] CCCTL_01_ACOND_TIMCLK = 0 , # [doc = "1: CC_TRIG_RISE"] CCCTL_01_ACOND_CC_TRIG_RISE = 1 , # [doc = "2: CC_TRIG_FALL"] CCCTL_01_ACOND_CC_TRIG_FALL = 2 , # [doc = "3: CC_TRIG_EDGE"] CCCTL_01_ACOND_CC_TRIG_EDGE = 3 , # [doc = "5: CC_TRIG_HIGH"] CCCTL_01_ACOND_CC_TRIG_HIGH = 5 , } impl From < CCCTL_01_ACOND_A > for u8 { # [inline (always)] fn from (variant : CCCTL_01_ACOND_A) -> Self { variant as _ } } impl crate :: FieldSpec for CCCTL_01_ACOND_A { type Ux = u8 ; } impl CCCTL_01_ACOND_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < CCCTL_01_ACOND_A > { match self . bits { 0 => Some (CCCTL_01_ACOND_A :: CCCTL_01_ACOND_TIMCLK) , 1 => Some (CCCTL_01_ACOND_A :: CCCTL_01_ACOND_CC_TRIG_RISE) , 2 => Some (CCCTL_01_ACOND_A :: CCCTL_01_ACOND_CC_TRIG_FALL) , 3 => Some (CCCTL_01_ACOND_A :: CCCTL_01_ACOND_CC_TRIG_EDGE) , 5 => Some (CCCTL_01_ACOND_A :: CCCTL_01_ACOND_CC_TRIG_HIGH) , _ => None , } } # [doc = "TIMCLK"] # [inline (always)] pub fn is_ccctl_01_acond_timclk (& self) -> bool { * self == CCCTL_01_ACOND_A :: CCCTL_01_ACOND_TIMCLK } # [doc = "CC_TRIG_RISE"] # [inline (always)] pub fn is_ccctl_01_acond_cc_trig_rise (& self) -> bool { * self == CCCTL_01_ACOND_A :: CCCTL_01_ACOND_CC_TRIG_RISE } # [doc = "CC_TRIG_FALL"] # [inline (always)] pub fn is_ccctl_01_acond_cc_trig_fall (& self) -> bool { * self == CCCTL_01_ACOND_A :: CCCTL_01_ACOND_CC_TRIG_FALL } # [doc = "CC_TRIG_EDGE"] # [inline (always)] pub fn is_ccctl_01_acond_cc_trig_edge (& self) -> bool { * self == CCCTL_01_ACOND_A :: CCCTL_01_ACOND_CC_TRIG_EDGE } # [doc = "CC_TRIG_HIGH"] # [inline (always)] pub fn is_ccctl_01_acond_cc_trig_high (& self) -> bool { * self == CCCTL_01_ACOND_A :: CCCTL_01_ACOND_CC_TRIG_HIGH } } # [doc = "Field `CCCTL_01_ACOND` writer - Advance Condition. #br# Specifies the condition that generates an advance pulse. 6h-Fh = Reserved"] pub type CCCTL_01_ACOND_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 3 , O , CCCTL_01_ACOND_A > ; impl < 'a , REG , const O : u8 > CCCTL_01_ACOND_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "TIMCLK"] # [inline (always)] pub fn ccctl_01_acond_timclk (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_ACOND_A :: CCCTL_01_ACOND_TIMCLK) } # [doc = "CC_TRIG_RISE"] # [inline (always)] pub fn ccctl_01_acond_cc_trig_rise (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_ACOND_A :: CCCTL_01_ACOND_CC_TRIG_RISE) } # [doc = "CC_TRIG_FALL"] # [inline (always)] pub fn ccctl_01_acond_cc_trig_fall (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_ACOND_A :: CCCTL_01_ACOND_CC_TRIG_FALL) } # [doc = "CC_TRIG_EDGE"] # [inline (always)] pub fn ccctl_01_acond_cc_trig_edge (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_ACOND_A :: CCCTL_01_ACOND_CC_TRIG_EDGE) } # [doc = "CC_TRIG_HIGH"] # [inline (always)] pub fn ccctl_01_acond_cc_trig_high (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_ACOND_A :: CCCTL_01_ACOND_CC_TRIG_HIGH) } } # [doc = "Field `CCCTL_01_LCOND` reader - Load Condition. #br# Specifies the condition that generates a load pulse. 4h-Fh = Reserved"] pub type CCCTL_01_LCOND_R = crate :: FieldReader < CCCTL_01_LCOND_A > ; # [doc = "Load Condition. #br# Specifies the condition that generates a load pulse. 4h-Fh = Reserved\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum CCCTL_01_LCOND_A { # [doc = "1: CC_TRIG_RISE"] CCCTL_01_LCOND_CC_TRIG_RISE = 1 , # [doc = "2: CC_TRIG_FALL"] CCCTL_01_LCOND_CC_TRIG_FALL = 2 , # [doc = "3: CC_TRIG_EDGE"] CCCTL_01_LCOND_CC_TRIG_EDGE = 3 , } impl From < CCCTL_01_LCOND_A > for u8 { # [inline (always)] fn from (variant : CCCTL_01_LCOND_A) -> Self { variant as _ } } impl crate :: FieldSpec for CCCTL_01_LCOND_A { type Ux = u8 ; } impl CCCTL_01_LCOND_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < CCCTL_01_LCOND_A > { match self . bits { 1 => Some (CCCTL_01_LCOND_A :: CCCTL_01_LCOND_CC_TRIG_RISE) , 2 => Some (CCCTL_01_LCOND_A :: CCCTL_01_LCOND_CC_TRIG_FALL) , 3 => Some (CCCTL_01_LCOND_A :: CCCTL_01_LCOND_CC_TRIG_EDGE) , _ => None , } } # [doc = "CC_TRIG_RISE"] # [inline (always)] pub fn is_ccctl_01_lcond_cc_trig_rise (& self) -> bool { * self == CCCTL_01_LCOND_A :: CCCTL_01_LCOND_CC_TRIG_RISE } # [doc = "CC_TRIG_FALL"] # [inline (always)] pub fn is_ccctl_01_lcond_cc_trig_fall (& self) -> bool { * self == CCCTL_01_LCOND_A :: CCCTL_01_LCOND_CC_TRIG_FALL } # [doc = "CC_TRIG_EDGE"] # [inline (always)] pub fn is_ccctl_01_lcond_cc_trig_edge (& self) -> bool { * self == CCCTL_01_LCOND_A :: CCCTL_01_LCOND_CC_TRIG_EDGE } } # [doc = "Field `CCCTL_01_LCOND` writer - Load Condition. #br# Specifies the condition that generates a load pulse. 4h-Fh = Reserved"] pub type CCCTL_01_LCOND_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 3 , O , CCCTL_01_LCOND_A > ; impl < 'a , REG , const O : u8 > CCCTL_01_LCOND_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "CC_TRIG_RISE"] # [inline (always)] pub fn ccctl_01_lcond_cc_trig_rise (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_LCOND_A :: CCCTL_01_LCOND_CC_TRIG_RISE) } # [doc = "CC_TRIG_FALL"] # [inline (always)] pub fn ccctl_01_lcond_cc_trig_fall (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_LCOND_A :: CCCTL_01_LCOND_CC_TRIG_FALL) } # [doc = "CC_TRIG_EDGE"] # [inline (always)] pub fn ccctl_01_lcond_cc_trig_edge (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_LCOND_A :: CCCTL_01_LCOND_CC_TRIG_EDGE) } } # [doc = "Field `CCCTL_01_ZCOND` reader - Zero Condition. #br# This field specifies the condition that generates a zero pulse. 4h-Fh = Reserved"] pub type CCCTL_01_ZCOND_R = crate :: FieldReader < CCCTL_01_ZCOND_A > ; # [doc = "Zero Condition. #br# This field specifies the condition that generates a zero pulse. 4h-Fh = Reserved\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum CCCTL_01_ZCOND_A { # [doc = "1: CC_TRIG_RISE"] CCCTL_01_ZCOND_CC_TRIG_RISE = 1 , # [doc = "2: CC_TRIG_FALL"] CCCTL_01_ZCOND_CC_TRIG_FALL = 2 , # [doc = "3: CC_TRIG_EDGE"] CCCTL_01_ZCOND_CC_TRIG_EDGE = 3 , } impl From < CCCTL_01_ZCOND_A > for u8 { # [inline (always)] fn from (variant : CCCTL_01_ZCOND_A) -> Self { variant as _ } } impl crate :: FieldSpec for CCCTL_01_ZCOND_A { type Ux = u8 ; } impl CCCTL_01_ZCOND_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < CCCTL_01_ZCOND_A > { match self . bits { 1 => Some (CCCTL_01_ZCOND_A :: CCCTL_01_ZCOND_CC_TRIG_RISE) , 2 => Some (CCCTL_01_ZCOND_A :: CCCTL_01_ZCOND_CC_TRIG_FALL) , 3 => Some (CCCTL_01_ZCOND_A :: CCCTL_01_ZCOND_CC_TRIG_EDGE) , _ => None , } } # [doc = "CC_TRIG_RISE"] # [inline (always)] pub fn is_ccctl_01_zcond_cc_trig_rise (& self) -> bool { * self == CCCTL_01_ZCOND_A :: CCCTL_01_ZCOND_CC_TRIG_RISE } # [doc = "CC_TRIG_FALL"] # [inline (always)] pub fn is_ccctl_01_zcond_cc_trig_fall (& self) -> bool { * self == CCCTL_01_ZCOND_A :: CCCTL_01_ZCOND_CC_TRIG_FALL } # [doc = "CC_TRIG_EDGE"] # [inline (always)] pub fn is_ccctl_01_zcond_cc_trig_edge (& self) -> bool { * self == CCCTL_01_ZCOND_A :: CCCTL_01_ZCOND_CC_TRIG_EDGE } } # [doc = "Field `CCCTL_01_ZCOND` writer - Zero Condition. #br# This field specifies the condition that generates a zero pulse. 4h-Fh = Reserved"] pub type CCCTL_01_ZCOND_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 3 , O , CCCTL_01_ZCOND_A > ; impl < 'a , REG , const O : u8 > CCCTL_01_ZCOND_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "CC_TRIG_RISE"] # [inline (always)] pub fn ccctl_01_zcond_cc_trig_rise (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_ZCOND_A :: CCCTL_01_ZCOND_CC_TRIG_RISE) } # [doc = "CC_TRIG_FALL"] # [inline (always)] pub fn ccctl_01_zcond_cc_trig_fall (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_ZCOND_A :: CCCTL_01_ZCOND_CC_TRIG_FALL) } # [doc = "CC_TRIG_EDGE"] # [inline (always)] pub fn ccctl_01_zcond_cc_trig_edge (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_ZCOND_A :: CCCTL_01_ZCOND_CC_TRIG_EDGE) } } # [doc = "Field `CCCTL_01_COC` reader - Capture or Compare. #br# Specifies whether the corresponding CC register is used as a capture register or a compare register (never both)."] pub type CCCTL_01_COC_R = crate :: BitReader < CCCTL_01_COC_A > ; # [doc = "Capture or Compare. #br# Specifies whether the corresponding CC register is used as a capture register or a compare register (never both).\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CCCTL_01_COC_A { # [doc = "0: COMPARE"] CCCTL_01_COC_COMPARE = 0 , # [doc = "1: CAPTURE"] CCCTL_01_COC_CAPTURE = 1 , } impl From < CCCTL_01_COC_A > for bool { # [inline (always)] fn from (variant : CCCTL_01_COC_A) -> Self { variant as u8 != 0 } } impl CCCTL_01_COC_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CCCTL_01_COC_A { match self . bits { false => CCCTL_01_COC_A :: CCCTL_01_COC_COMPARE , true => CCCTL_01_COC_A :: CCCTL_01_COC_CAPTURE , } } # [doc = "COMPARE"] # [inline (always)] pub fn is_ccctl_01_coc_compare (& self) -> bool { * self == CCCTL_01_COC_A :: CCCTL_01_COC_COMPARE } # [doc = "CAPTURE"] # [inline (always)] pub fn is_ccctl_01_coc_capture (& self) -> bool { * self == CCCTL_01_COC_A :: CCCTL_01_COC_CAPTURE } } # [doc = "Field `CCCTL_01_COC` writer - Capture or Compare. #br# Specifies whether the corresponding CC register is used as a capture register or a compare register (never both)."] pub type CCCTL_01_COC_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CCCTL_01_COC_A > ; impl < 'a , REG , const O : u8 > CCCTL_01_COC_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "COMPARE"] # [inline (always)] pub fn ccctl_01_coc_compare (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_COC_A :: CCCTL_01_COC_COMPARE) } # [doc = "CAPTURE"] # [inline (always)] pub fn ccctl_01_coc_capture (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_COC_A :: CCCTL_01_COC_CAPTURE) } } # [doc = "Field `CCCTL_01_CCUPD` reader - Capture and Compare Update Method This field controls how updates to the pipelined capture and compare register are performed (when operating in compare mode, COC=0)."] pub type CCCTL_01_CCUPD_R = crate :: FieldReader < CCCTL_01_CCUPD_A > ; # [doc = "Capture and Compare Update Method This field controls how updates to the pipelined capture and compare register are performed (when operating in compare mode, COC=0).\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum CCCTL_01_CCUPD_A { # [doc = "0: IMMEDIATELY"] CCCTL_01_CCUPD_IMMEDIATELY = 0 , # [doc = "1: ZERO_EVT"] CCCTL_01_CCUPD_ZERO_EVT = 1 , # [doc = "2: COMPARE_DOWN_EVT"] CCCTL_01_CCUPD_COMPARE_DOWN_EVT = 2 , # [doc = "3: COMPARE_UP_EVT"] CCCTL_01_CCUPD_COMPARE_UP_EVT = 3 , # [doc = "4: ZERO_LOAD_EVT"] CCCTL_01_CCUPD_ZERO_LOAD_EVT = 4 , # [doc = "5: ZERO_RC_ZERO_EVT"] CCCTL_01_CCUPD_ZERO_RC_ZERO_EVT = 5 , # [doc = "6: TRIG"] CCCTL_01_CCUPD_TRIG = 6 , } impl From < CCCTL_01_CCUPD_A > for u8 { # [inline (always)] fn from (variant : CCCTL_01_CCUPD_A) -> Self { variant as _ } } impl crate :: FieldSpec for CCCTL_01_CCUPD_A { type Ux = u8 ; } impl CCCTL_01_CCUPD_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < CCCTL_01_CCUPD_A > { match self . bits { 0 => Some (CCCTL_01_CCUPD_A :: CCCTL_01_CCUPD_IMMEDIATELY) , 1 => Some (CCCTL_01_CCUPD_A :: CCCTL_01_CCUPD_ZERO_EVT) , 2 => Some (CCCTL_01_CCUPD_A :: CCCTL_01_CCUPD_COMPARE_DOWN_EVT) , 3 => Some (CCCTL_01_CCUPD_A :: CCCTL_01_CCUPD_COMPARE_UP_EVT) , 4 => Some (CCCTL_01_CCUPD_A :: CCCTL_01_CCUPD_ZERO_LOAD_EVT) , 5 => Some (CCCTL_01_CCUPD_A :: CCCTL_01_CCUPD_ZERO_RC_ZERO_EVT) , 6 => Some (CCCTL_01_CCUPD_A :: CCCTL_01_CCUPD_TRIG) , _ => None , } } # [doc = "IMMEDIATELY"] # [inline (always)] pub fn is_ccctl_01_ccupd_immediately (& self) -> bool { * self == CCCTL_01_CCUPD_A :: CCCTL_01_CCUPD_IMMEDIATELY } # [doc = "ZERO_EVT"] # [inline (always)] pub fn is_ccctl_01_ccupd_zero_evt (& self) -> bool { * self == CCCTL_01_CCUPD_A :: CCCTL_01_CCUPD_ZERO_EVT } # [doc = "COMPARE_DOWN_EVT"] # [inline (always)] pub fn is_ccctl_01_ccupd_compare_down_evt (& self) -> bool { * self == CCCTL_01_CCUPD_A :: CCCTL_01_CCUPD_COMPARE_DOWN_EVT } # [doc = "COMPARE_UP_EVT"] # [inline (always)] pub fn is_ccctl_01_ccupd_compare_up_evt (& self) -> bool { * self == CCCTL_01_CCUPD_A :: CCCTL_01_CCUPD_COMPARE_UP_EVT } # [doc = "ZERO_LOAD_EVT"] # [inline (always)] pub fn is_ccctl_01_ccupd_zero_load_evt (& self) -> bool { * self == CCCTL_01_CCUPD_A :: CCCTL_01_CCUPD_ZERO_LOAD_EVT } # [doc = "ZERO_RC_ZERO_EVT"] # [inline (always)] pub fn is_ccctl_01_ccupd_zero_rc_zero_evt (& self) -> bool { * self == CCCTL_01_CCUPD_A :: CCCTL_01_CCUPD_ZERO_RC_ZERO_EVT } # [doc = "TRIG"] # [inline (always)] pub fn is_ccctl_01_ccupd_trig (& self) -> bool { * self == CCCTL_01_CCUPD_A :: CCCTL_01_CCUPD_TRIG } } # [doc = "Field `CCCTL_01_CCUPD` writer - Capture and Compare Update Method This field controls how updates to the pipelined capture and compare register are performed (when operating in compare mode, COC=0)."] pub type CCCTL_01_CCUPD_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 3 , O , CCCTL_01_CCUPD_A > ; impl < 'a , REG , const O : u8 > CCCTL_01_CCUPD_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "IMMEDIATELY"] # [inline (always)] pub fn ccctl_01_ccupd_immediately (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CCUPD_A :: CCCTL_01_CCUPD_IMMEDIATELY) } # [doc = "ZERO_EVT"] # [inline (always)] pub fn ccctl_01_ccupd_zero_evt (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CCUPD_A :: CCCTL_01_CCUPD_ZERO_EVT) } # [doc = "COMPARE_DOWN_EVT"] # [inline (always)] pub fn ccctl_01_ccupd_compare_down_evt (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CCUPD_A :: CCCTL_01_CCUPD_COMPARE_DOWN_EVT) } # [doc = "COMPARE_UP_EVT"] # [inline (always)] pub fn ccctl_01_ccupd_compare_up_evt (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CCUPD_A :: CCCTL_01_CCUPD_COMPARE_UP_EVT) } # [doc = "ZERO_LOAD_EVT"] # [inline (always)] pub fn ccctl_01_ccupd_zero_load_evt (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CCUPD_A :: CCCTL_01_CCUPD_ZERO_LOAD_EVT) } # [doc = "ZERO_RC_ZERO_EVT"] # [inline (always)] pub fn ccctl_01_ccupd_zero_rc_zero_evt (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CCUPD_A :: CCCTL_01_CCUPD_ZERO_RC_ZERO_EVT) } # [doc = "TRIG"] # [inline (always)] pub fn ccctl_01_ccupd_trig (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CCUPD_A :: CCCTL_01_CCUPD_TRIG) } } # [doc = "Field `CCCTL_01_CC2SELU` reader - Selects the source second CCU event."] pub type CCCTL_01_CC2SELU_R = crate :: FieldReader < CCCTL_01_CC2SELU_A > ; # [doc = "Selects the source second CCU event.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum CCCTL_01_CC2SELU_A { # [doc = "0: SEL_CCU0"] CCCTL_01_CC2SELU_SEL_CCU0 = 0 , # [doc = "1: SEL_CCU1"] CCCTL_01_CC2SELU_SEL_CCU1 = 1 , # [doc = "2: SEL_CCU2"] CCCTL_01_CC2SELU_SEL_CCU2 = 2 , # [doc = "3: SEL_CCU3"] CCCTL_01_CC2SELU_SEL_CCU3 = 3 , # [doc = "4: SEL_CCU4"] CCCTL_01_CC2SELU_SEL_CCU4 = 4 , # [doc = "5: SEL_CCU5"] CCCTL_01_CC2SELU_SEL_CCU5 = 5 , } impl From < CCCTL_01_CC2SELU_A > for u8 { # [inline (always)] fn from (variant : CCCTL_01_CC2SELU_A) -> Self { variant as _ } } impl crate :: FieldSpec for CCCTL_01_CC2SELU_A { type Ux = u8 ; } impl CCCTL_01_CC2SELU_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < CCCTL_01_CC2SELU_A > { match self . bits { 0 => Some (CCCTL_01_CC2SELU_A :: CCCTL_01_CC2SELU_SEL_CCU0) , 1 => Some (CCCTL_01_CC2SELU_A :: CCCTL_01_CC2SELU_SEL_CCU1) , 2 => Some (CCCTL_01_CC2SELU_A :: CCCTL_01_CC2SELU_SEL_CCU2) , 3 => Some (CCCTL_01_CC2SELU_A :: CCCTL_01_CC2SELU_SEL_CCU3) , 4 => Some (CCCTL_01_CC2SELU_A :: CCCTL_01_CC2SELU_SEL_CCU4) , 5 => Some (CCCTL_01_CC2SELU_A :: CCCTL_01_CC2SELU_SEL_CCU5) , _ => None , } } # [doc = "SEL_CCU0"] # [inline (always)] pub fn is_ccctl_01_cc2selu_sel_ccu0 (& self) -> bool { * self == CCCTL_01_CC2SELU_A :: CCCTL_01_CC2SELU_SEL_CCU0 } # [doc = "SEL_CCU1"] # [inline (always)] pub fn is_ccctl_01_cc2selu_sel_ccu1 (& self) -> bool { * self == CCCTL_01_CC2SELU_A :: CCCTL_01_CC2SELU_SEL_CCU1 } # [doc = "SEL_CCU2"] # [inline (always)] pub fn is_ccctl_01_cc2selu_sel_ccu2 (& self) -> bool { * self == CCCTL_01_CC2SELU_A :: CCCTL_01_CC2SELU_SEL_CCU2 } # [doc = "SEL_CCU3"] # [inline (always)] pub fn is_ccctl_01_cc2selu_sel_ccu3 (& self) -> bool { * self == CCCTL_01_CC2SELU_A :: CCCTL_01_CC2SELU_SEL_CCU3 } # [doc = "SEL_CCU4"] # [inline (always)] pub fn is_ccctl_01_cc2selu_sel_ccu4 (& self) -> bool { * self == CCCTL_01_CC2SELU_A :: CCCTL_01_CC2SELU_SEL_CCU4 } # [doc = "SEL_CCU5"] # [inline (always)] pub fn is_ccctl_01_cc2selu_sel_ccu5 (& self) -> bool { * self == CCCTL_01_CC2SELU_A :: CCCTL_01_CC2SELU_SEL_CCU5 } } # [doc = "Field `CCCTL_01_CC2SELU` writer - Selects the source second CCU event."] pub type CCCTL_01_CC2SELU_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 3 , O , CCCTL_01_CC2SELU_A > ; impl < 'a , REG , const O : u8 > CCCTL_01_CC2SELU_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "SEL_CCU0"] # [inline (always)] pub fn ccctl_01_cc2selu_sel_ccu0 (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CC2SELU_A :: CCCTL_01_CC2SELU_SEL_CCU0) } # [doc = "SEL_CCU1"] # [inline (always)] pub fn ccctl_01_cc2selu_sel_ccu1 (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CC2SELU_A :: CCCTL_01_CC2SELU_SEL_CCU1) } # [doc = "SEL_CCU2"] # [inline (always)] pub fn ccctl_01_cc2selu_sel_ccu2 (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CC2SELU_A :: CCCTL_01_CC2SELU_SEL_CCU2) } # [doc = "SEL_CCU3"] # [inline (always)] pub fn ccctl_01_cc2selu_sel_ccu3 (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CC2SELU_A :: CCCTL_01_CC2SELU_SEL_CCU3) } # [doc = "SEL_CCU4"] # [inline (always)] pub fn ccctl_01_cc2selu_sel_ccu4 (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CC2SELU_A :: CCCTL_01_CC2SELU_SEL_CCU4) } # [doc = "SEL_CCU5"] # [inline (always)] pub fn ccctl_01_cc2selu_sel_ccu5 (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CC2SELU_A :: CCCTL_01_CC2SELU_SEL_CCU5) } } # [doc = "Field `CCCTL_01_CCACTUPD` reader - CCACT shadow register Update Method This field controls how updates to the CCCACT shadow register are performed"] pub type CCCTL_01_CCACTUPD_R = crate :: FieldReader < CCCTL_01_CCACTUPD_A > ; # [doc = "CCACT shadow register Update Method This field controls how updates to the CCCACT shadow register are performed\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum CCCTL_01_CCACTUPD_A { # [doc = "0: IMMEDIATELY"] CCCTL_01_CCACTUPD_IMMEDIATELY = 0 , # [doc = "1: ZERO_EVT"] CCCTL_01_CCACTUPD_ZERO_EVT = 1 , # [doc = "2: COMPARE_DOWN_EVT"] CCCTL_01_CCACTUPD_COMPARE_DOWN_EVT = 2 , # [doc = "3: COMPARE_UP_EVT"] CCCTL_01_CCACTUPD_COMPARE_UP_EVT = 3 , # [doc = "4: ZERO_LOAD_EVT"] CCCTL_01_CCACTUPD_ZERO_LOAD_EVT = 4 , # [doc = "5: ZERO_RC_ZERO_EVT"] CCCTL_01_CCACTUPD_ZERO_RC_ZERO_EVT = 5 , # [doc = "6: TRIG"] CCCTL_01_CCACTUPD_TRIG = 6 , } impl From < CCCTL_01_CCACTUPD_A > for u8 { # [inline (always)] fn from (variant : CCCTL_01_CCACTUPD_A) -> Self { variant as _ } } impl crate :: FieldSpec for CCCTL_01_CCACTUPD_A { type Ux = u8 ; } impl CCCTL_01_CCACTUPD_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < CCCTL_01_CCACTUPD_A > { match self . bits { 0 => Some (CCCTL_01_CCACTUPD_A :: CCCTL_01_CCACTUPD_IMMEDIATELY) , 1 => Some (CCCTL_01_CCACTUPD_A :: CCCTL_01_CCACTUPD_ZERO_EVT) , 2 => Some (CCCTL_01_CCACTUPD_A :: CCCTL_01_CCACTUPD_COMPARE_DOWN_EVT) , 3 => Some (CCCTL_01_CCACTUPD_A :: CCCTL_01_CCACTUPD_COMPARE_UP_EVT) , 4 => Some (CCCTL_01_CCACTUPD_A :: CCCTL_01_CCACTUPD_ZERO_LOAD_EVT) , 5 => Some (CCCTL_01_CCACTUPD_A :: CCCTL_01_CCACTUPD_ZERO_RC_ZERO_EVT) , 6 => Some (CCCTL_01_CCACTUPD_A :: CCCTL_01_CCACTUPD_TRIG) , _ => None , } } # [doc = "IMMEDIATELY"] # [inline (always)] pub fn is_ccctl_01_ccactupd_immediately (& self) -> bool { * self == CCCTL_01_CCACTUPD_A :: CCCTL_01_CCACTUPD_IMMEDIATELY } # [doc = "ZERO_EVT"] # [inline (always)] pub fn is_ccctl_01_ccactupd_zero_evt (& self) -> bool { * self == CCCTL_01_CCACTUPD_A :: CCCTL_01_CCACTUPD_ZERO_EVT } # [doc = "COMPARE_DOWN_EVT"] # [inline (always)] pub fn is_ccctl_01_ccactupd_compare_down_evt (& self) -> bool { * self == CCCTL_01_CCACTUPD_A :: CCCTL_01_CCACTUPD_COMPARE_DOWN_EVT } # [doc = "COMPARE_UP_EVT"] # [inline (always)] pub fn is_ccctl_01_ccactupd_compare_up_evt (& self) -> bool { * self == CCCTL_01_CCACTUPD_A :: CCCTL_01_CCACTUPD_COMPARE_UP_EVT } # [doc = "ZERO_LOAD_EVT"] # [inline (always)] pub fn is_ccctl_01_ccactupd_zero_load_evt (& self) -> bool { * self == CCCTL_01_CCACTUPD_A :: CCCTL_01_CCACTUPD_ZERO_LOAD_EVT } # [doc = "ZERO_RC_ZERO_EVT"] # [inline (always)] pub fn is_ccctl_01_ccactupd_zero_rc_zero_evt (& self) -> bool { * self == CCCTL_01_CCACTUPD_A :: CCCTL_01_CCACTUPD_ZERO_RC_ZERO_EVT } # [doc = "TRIG"] # [inline (always)] pub fn is_ccctl_01_ccactupd_trig (& self) -> bool { * self == CCCTL_01_CCACTUPD_A :: CCCTL_01_CCACTUPD_TRIG } } # [doc = "Field `CCCTL_01_CCACTUPD` writer - CCACT shadow register Update Method This field controls how updates to the CCCACT shadow register are performed"] pub type CCCTL_01_CCACTUPD_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 3 , O , CCCTL_01_CCACTUPD_A > ; impl < 'a , REG , const O : u8 > CCCTL_01_CCACTUPD_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "IMMEDIATELY"] # [inline (always)] pub fn ccctl_01_ccactupd_immediately (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CCACTUPD_A :: CCCTL_01_CCACTUPD_IMMEDIATELY) } # [doc = "ZERO_EVT"] # [inline (always)] pub fn ccctl_01_ccactupd_zero_evt (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CCACTUPD_A :: CCCTL_01_CCACTUPD_ZERO_EVT) } # [doc = "COMPARE_DOWN_EVT"] # [inline (always)] pub fn ccctl_01_ccactupd_compare_down_evt (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CCACTUPD_A :: CCCTL_01_CCACTUPD_COMPARE_DOWN_EVT) } # [doc = "COMPARE_UP_EVT"] # [inline (always)] pub fn ccctl_01_ccactupd_compare_up_evt (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CCACTUPD_A :: CCCTL_01_CCACTUPD_COMPARE_UP_EVT) } # [doc = "ZERO_LOAD_EVT"] # [inline (always)] pub fn ccctl_01_ccactupd_zero_load_evt (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CCACTUPD_A :: CCCTL_01_CCACTUPD_ZERO_LOAD_EVT) } # [doc = "ZERO_RC_ZERO_EVT"] # [inline (always)] pub fn ccctl_01_ccactupd_zero_rc_zero_evt (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CCACTUPD_A :: CCCTL_01_CCACTUPD_ZERO_RC_ZERO_EVT) } # [doc = "TRIG"] # [inline (always)] pub fn ccctl_01_ccactupd_trig (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CCACTUPD_A :: CCCTL_01_CCACTUPD_TRIG) } } # [doc = "Field `CCCTL_01_CC2SELD` reader - Selects the source second CCD event."] pub type CCCTL_01_CC2SELD_R = crate :: FieldReader < CCCTL_01_CC2SELD_A > ; # [doc = "Selects the source second CCD event.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum CCCTL_01_CC2SELD_A { # [doc = "0: SEL_CCD0"] CCCTL_01_CC2SELD_SEL_CCD0 = 0 , # [doc = "1: SEL_CCD1"] CCCTL_01_CC2SELD_SEL_CCD1 = 1 , # [doc = "2: SEL_CCD2"] CCCTL_01_CC2SELD_SEL_CCD2 = 2 , # [doc = "3: SEL_CCD3"] CCCTL_01_CC2SELD_SEL_CCD3 = 3 , # [doc = "4: SEL_CCD4"] CCCTL_01_CC2SELD_SEL_CCD4 = 4 , # [doc = "5: SEL_CCD5"] CCCTL_01_CC2SELD_SEL_CCD5 = 5 , } impl From < CCCTL_01_CC2SELD_A > for u8 { # [inline (always)] fn from (variant : CCCTL_01_CC2SELD_A) -> Self { variant as _ } } impl crate :: FieldSpec for CCCTL_01_CC2SELD_A { type Ux = u8 ; } impl CCCTL_01_CC2SELD_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < CCCTL_01_CC2SELD_A > { match self . bits { 0 => Some (CCCTL_01_CC2SELD_A :: CCCTL_01_CC2SELD_SEL_CCD0) , 1 => Some (CCCTL_01_CC2SELD_A :: CCCTL_01_CC2SELD_SEL_CCD1) , 2 => Some (CCCTL_01_CC2SELD_A :: CCCTL_01_CC2SELD_SEL_CCD2) , 3 => Some (CCCTL_01_CC2SELD_A :: CCCTL_01_CC2SELD_SEL_CCD3) , 4 => Some (CCCTL_01_CC2SELD_A :: CCCTL_01_CC2SELD_SEL_CCD4) , 5 => Some (CCCTL_01_CC2SELD_A :: CCCTL_01_CC2SELD_SEL_CCD5) , _ => None , } } # [doc = "SEL_CCD0"] # [inline (always)] pub fn is_ccctl_01_cc2seld_sel_ccd0 (& self) -> bool { * self == CCCTL_01_CC2SELD_A :: CCCTL_01_CC2SELD_SEL_CCD0 } # [doc = "SEL_CCD1"] # [inline (always)] pub fn is_ccctl_01_cc2seld_sel_ccd1 (& self) -> bool { * self == CCCTL_01_CC2SELD_A :: CCCTL_01_CC2SELD_SEL_CCD1 } # [doc = "SEL_CCD2"] # [inline (always)] pub fn is_ccctl_01_cc2seld_sel_ccd2 (& self) -> bool { * self == CCCTL_01_CC2SELD_A :: CCCTL_01_CC2SELD_SEL_CCD2 } # [doc = "SEL_CCD3"] # [inline (always)] pub fn is_ccctl_01_cc2seld_sel_ccd3 (& self) -> bool { * self == CCCTL_01_CC2SELD_A :: CCCTL_01_CC2SELD_SEL_CCD3 } # [doc = "SEL_CCD4"] # [inline (always)] pub fn is_ccctl_01_cc2seld_sel_ccd4 (& self) -> bool { * self == CCCTL_01_CC2SELD_A :: CCCTL_01_CC2SELD_SEL_CCD4 } # [doc = "SEL_CCD5"] # [inline (always)] pub fn is_ccctl_01_cc2seld_sel_ccd5 (& self) -> bool { * self == CCCTL_01_CC2SELD_A :: CCCTL_01_CC2SELD_SEL_CCD5 } } # [doc = "Field `CCCTL_01_CC2SELD` writer - Selects the source second CCD event."] pub type CCCTL_01_CC2SELD_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 3 , O , CCCTL_01_CC2SELD_A > ; impl < 'a , REG , const O : u8 > CCCTL_01_CC2SELD_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "SEL_CCD0"] # [inline (always)] pub fn ccctl_01_cc2seld_sel_ccd0 (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CC2SELD_A :: CCCTL_01_CC2SELD_SEL_CCD0) } # [doc = "SEL_CCD1"] # [inline (always)] pub fn ccctl_01_cc2seld_sel_ccd1 (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CC2SELD_A :: CCCTL_01_CC2SELD_SEL_CCD1) } # [doc = "SEL_CCD2"] # [inline (always)] pub fn ccctl_01_cc2seld_sel_ccd2 (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CC2SELD_A :: CCCTL_01_CC2SELD_SEL_CCD2) } # [doc = "SEL_CCD3"] # [inline (always)] pub fn ccctl_01_cc2seld_sel_ccd3 (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CC2SELD_A :: CCCTL_01_CC2SELD_SEL_CCD3) } # [doc = "SEL_CCD4"] # [inline (always)] pub fn ccctl_01_cc2seld_sel_ccd4 (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CC2SELD_A :: CCCTL_01_CC2SELD_SEL_CCD4) } # [doc = "SEL_CCD5"] # [inline (always)] pub fn ccctl_01_cc2seld_sel_ccd5 (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CC2SELD_A :: CCCTL_01_CC2SELD_SEL_CCD5) } } impl R { # [doc = "Bits 0:2 - Capture Condition. #br# Specifies the condition that generates a capture pulse. 4h-Fh = Reserved"] # [inline (always)] pub fn ccctl_01_ccond (& self) -> CCCTL_01_CCOND_R { CCCTL_01_CCOND_R :: new ((self . bits & 7) as u8) } # [doc = "Bits 4:6 - Advance Condition. #br# Specifies the condition that generates an advance pulse. 6h-Fh = Reserved"] # [inline (always)] pub fn ccctl_01_acond (& self) -> CCCTL_01_ACOND_R { CCCTL_01_ACOND_R :: new (((self . bits >> 4) & 7) as u8) } # [doc = "Bits 8:10 - Load Condition. #br# Specifies the condition that generates a load pulse. 4h-Fh = Reserved"] # [inline (always)] pub fn ccctl_01_lcond (& self) -> CCCTL_01_LCOND_R { CCCTL_01_LCOND_R :: new (((self . bits >> 8) & 7) as u8) } # [doc = "Bits 12:14 - Zero Condition. #br# This field specifies the condition that generates a zero pulse. 4h-Fh = Reserved"] # [inline (always)] pub fn ccctl_01_zcond (& self) -> CCCTL_01_ZCOND_R { CCCTL_01_ZCOND_R :: new (((self . bits >> 12) & 7) as u8) } # [doc = "Bit 17 - Capture or Compare. #br# Specifies whether the corresponding CC register is used as a capture register or a compare register (never both)."] # [inline (always)] pub fn ccctl_01_coc (& self) -> CCCTL_01_COC_R { CCCTL_01_COC_R :: new (((self . bits >> 17) & 1) != 0) } # [doc = "Bits 18:20 - Capture and Compare Update Method This field controls how updates to the pipelined capture and compare register are performed (when operating in compare mode, COC=0)."] # [inline (always)] pub fn ccctl_01_ccupd (& self) -> CCCTL_01_CCUPD_R { CCCTL_01_CCUPD_R :: new (((self . bits >> 18) & 7) as u8) } # [doc = "Bits 22:24 - Selects the source second CCU event."] # [inline (always)] pub fn ccctl_01_cc2selu (& self) -> CCCTL_01_CC2SELU_R { CCCTL_01_CC2SELU_R :: new (((self . bits >> 22) & 7) as u8) } # [doc = "Bits 26:28 - CCACT shadow register Update Method This field controls how updates to the CCCACT shadow register are performed"] # [inline (always)] pub fn ccctl_01_ccactupd (& self) -> CCCTL_01_CCACTUPD_R { CCCTL_01_CCACTUPD_R :: new (((self . bits >> 26) & 7) as u8) } # [doc = "Bits 29:31 - Selects the source second CCD event."] # [inline (always)] pub fn ccctl_01_cc2seld (& self) -> CCCTL_01_CC2SELD_R { CCCTL_01_CC2SELD_R :: new (((self . bits >> 29) & 7) as u8) } } impl W { # [doc = "Bits 0:2 - Capture Condition. #br# Specifies the condition that generates a capture pulse. 4h-Fh = Reserved"] # [inline (always)] # [must_use] pub fn ccctl_01_ccond (& mut self) -> CCCTL_01_CCOND_W < CCCTL_01_SPEC , 0 > { CCCTL_01_CCOND_W :: new (self) } # [doc = "Bits 4:6 - Advance Condition. #br# Specifies the condition that generates an advance pulse. 6h-Fh = Reserved"] # [inline (always)] # [must_use] pub fn ccctl_01_acond (& mut self) -> CCCTL_01_ACOND_W < CCCTL_01_SPEC , 4 > { CCCTL_01_ACOND_W :: new (self) } # [doc = "Bits 8:10 - Load Condition. #br# Specifies the condition that generates a load pulse. 4h-Fh = Reserved"] # [inline (always)] # [must_use] pub fn ccctl_01_lcond (& mut self) -> CCCTL_01_LCOND_W < CCCTL_01_SPEC , 8 > { CCCTL_01_LCOND_W :: new (self) } # [doc = "Bits 12:14 - Zero Condition. #br# This field specifies the condition that generates a zero pulse. 4h-Fh = Reserved"] # [inline (always)] # [must_use] pub fn ccctl_01_zcond (& mut self) -> CCCTL_01_ZCOND_W < CCCTL_01_SPEC , 12 > { CCCTL_01_ZCOND_W :: new (self) } # [doc = "Bit 17 - Capture or Compare. #br# Specifies whether the corresponding CC register is used as a capture register or a compare register (never both)."] # [inline (always)] # [must_use] pub fn ccctl_01_coc (& mut self) -> CCCTL_01_COC_W < CCCTL_01_SPEC , 17 > { CCCTL_01_COC_W :: new (self) } # [doc = "Bits 18:20 - Capture and Compare Update Method This field controls how updates to the pipelined capture and compare register are performed (when operating in compare mode, COC=0)."] # [inline (always)] # [must_use] pub fn ccctl_01_ccupd (& mut self) -> CCCTL_01_CCUPD_W < CCCTL_01_SPEC , 18 > { CCCTL_01_CCUPD_W :: new (self) } # [doc = "Bits 22:24 - Selects the source second CCU event."] # [inline (always)] # [must_use] pub fn ccctl_01_cc2selu (& mut self) -> CCCTL_01_CC2SELU_W < CCCTL_01_SPEC , 22 > { CCCTL_01_CC2SELU_W :: new (self) } # [doc = "Bits 26:28 - CCACT shadow register Update Method This field controls how updates to the CCCACT shadow register are performed"] # [inline (always)] # [must_use] pub fn ccctl_01_ccactupd (& mut self) -> CCCTL_01_CCACTUPD_W < CCCTL_01_SPEC , 26 > { CCCTL_01_CCACTUPD_W :: new (self) } # [doc = "Bits 29:31 - Selects the source second CCD event."] # [inline (always)] # [must_use] pub fn ccctl_01_cc2seld (& mut self) -> CCCTL_01_CC2SELD_W <'_, CCCTL_01_SPEC , 29 > { CCCTL_01_CC2SELD_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Capture or Compare Control Registers\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ccctl_01::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ccctl_01::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CCCTL_01_SPEC ; impl crate :: RegisterSpec for CCCTL_01_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`ccctl_01::R`](R) reader structure"] impl crate :: Readable for CCCTL_01_SPEC { } # [doc = "`write(|w| ..)` method takes [`ccctl_01::W`](W) writer structure"] impl crate :: Writable for CCCTL_01_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets CCCTL_01[%s] [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/opa0/clkovr.rs:10:111 [INFO] [stdout] | [INFO] [stdout] 10 | ...pub fn clkovr_override (& mut self) -> CLKOVR_OVERRIDE_W < CLKOVR_SPEC , 0 > { CLKOVR_OVERRIDE_W :: new (self) } # [doc = "Bit 1 - If ... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 10 | to override the automatic peripheral clock request"] # [inline (always)] # [must_use] pub fn clkovr_override (& mut self) -> CLKOVR_OVERRIDE_W <'_, CLKOVR_SPEC , 0 > { CLKOVR_OVERRIDE_W :: new (self) } # [doc = "Bit 1 - If \\[OVERRIDE\\] [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/opa0/clkovr.rs:11:159 [INFO] [stdout] | [INFO] [stdout] 11 | ...pub fn clkovr_run_stop (& mut self) -> CLKOVR_RUN_STOP_W < CLKOVR_SPEC , 1 > { CLKOVR_RUN_STOP_W :: new (self) } # [doc = r" Writes ra... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 11 | is enabled, this register is used to manually control the peripheral's clock request to the system"] # [inline (always)] # [must_use] pub fn clkovr_run_stop (& mut self) -> CLKOVR_RUN_STOP_W <'_, CLKOVR_SPEC , 1 > { CLKOVR_RUN_STOP_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Clock Override\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clkovr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clkovr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CLKOVR_SPEC ; impl crate :: RegisterSpec for CLKOVR_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`clkovr::R`](R) reader structure"] impl crate :: Readable for CLKOVR_SPEC { } # [doc = "`write(|w| ..)` method takes [`clkovr::W`](W) writer structure"] impl crate :: Writable for CLKOVR_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets CLKOVR to value 0"] impl crate :: Resettable for CLKOVR_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/uart0/clksel.rs:1:6636 [INFO] [stdout] | [INFO] [stdout] 1 | ...ub fn clksel_mfclk_sel (& mut self) -> CLKSEL_MFCLK_SEL_W < CLKSEL_SPEC , 2 > { CLKSEL_MFCLK_SEL_W :: new (self) } # [doc = "Bit 3 - S... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `CLKSEL` reader"] pub type R = crate :: R < CLKSEL_SPEC > ; # [doc = "Register `CLKSEL` writer"] pub type W = crate :: W < CLKSEL_SPEC > ; # [doc = "Field `CLKSEL_LFCLK_SEL` reader - Selects LFCLK as clock source if enabled"] pub type CLKSEL_LFCLK_SEL_R = crate :: BitReader < CLKSEL_LFCLK_SEL_A > ; # [doc = "Selects LFCLK as clock source if enabled\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CLKSEL_LFCLK_SEL_A { # [doc = "0: DISABLE"] CLKSEL_LFCLK_SEL_DISABLE = 0 , # [doc = "1: ENABLE"] CLKSEL_LFCLK_SEL_ENABLE = 1 , } impl From < CLKSEL_LFCLK_SEL_A > for bool { # [inline (always)] fn from (variant : CLKSEL_LFCLK_SEL_A) -> Self { variant as u8 != 0 } } impl CLKSEL_LFCLK_SEL_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CLKSEL_LFCLK_SEL_A { match self . bits { false => CLKSEL_LFCLK_SEL_A :: CLKSEL_LFCLK_SEL_DISABLE , true => CLKSEL_LFCLK_SEL_A :: CLKSEL_LFCLK_SEL_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_clksel_lfclk_sel_disable (& self) -> bool { * self == CLKSEL_LFCLK_SEL_A :: CLKSEL_LFCLK_SEL_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_clksel_lfclk_sel_enable (& self) -> bool { * self == CLKSEL_LFCLK_SEL_A :: CLKSEL_LFCLK_SEL_ENABLE } } # [doc = "Field `CLKSEL_LFCLK_SEL` writer - Selects LFCLK as clock source if enabled"] pub type CLKSEL_LFCLK_SEL_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CLKSEL_LFCLK_SEL_A > ; impl < 'a , REG , const O : u8 > CLKSEL_LFCLK_SEL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn clksel_lfclk_sel_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CLKSEL_LFCLK_SEL_A :: CLKSEL_LFCLK_SEL_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn clksel_lfclk_sel_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CLKSEL_LFCLK_SEL_A :: CLKSEL_LFCLK_SEL_ENABLE) } } # [doc = "Field `CLKSEL_MFCLK_SEL` reader - Selects MFCLK as clock source if enabled"] pub type CLKSEL_MFCLK_SEL_R = crate :: BitReader < CLKSEL_MFCLK_SEL_A > ; # [doc = "Selects MFCLK as clock source if enabled\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CLKSEL_MFCLK_SEL_A { # [doc = "0: DISABLE"] CLKSEL_MFCLK_SEL_DISABLE = 0 , # [doc = "1: ENABLE"] CLKSEL_MFCLK_SEL_ENABLE = 1 , } impl From < CLKSEL_MFCLK_SEL_A > for bool { # [inline (always)] fn from (variant : CLKSEL_MFCLK_SEL_A) -> Self { variant as u8 != 0 } } impl CLKSEL_MFCLK_SEL_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CLKSEL_MFCLK_SEL_A { match self . bits { false => CLKSEL_MFCLK_SEL_A :: CLKSEL_MFCLK_SEL_DISABLE , true => CLKSEL_MFCLK_SEL_A :: CLKSEL_MFCLK_SEL_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_clksel_mfclk_sel_disable (& self) -> bool { * self == CLKSEL_MFCLK_SEL_A :: CLKSEL_MFCLK_SEL_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_clksel_mfclk_sel_enable (& self) -> bool { * self == CLKSEL_MFCLK_SEL_A :: CLKSEL_MFCLK_SEL_ENABLE } } # [doc = "Field `CLKSEL_MFCLK_SEL` writer - Selects MFCLK as clock source if enabled"] pub type CLKSEL_MFCLK_SEL_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CLKSEL_MFCLK_SEL_A > ; impl < 'a , REG , const O : u8 > CLKSEL_MFCLK_SEL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn clksel_mfclk_sel_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CLKSEL_MFCLK_SEL_A :: CLKSEL_MFCLK_SEL_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn clksel_mfclk_sel_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CLKSEL_MFCLK_SEL_A :: CLKSEL_MFCLK_SEL_ENABLE) } } # [doc = "Field `CLKSEL_BUSCLK_SEL` reader - Selects BUS CLK as clock source if enabled"] pub type CLKSEL_BUSCLK_SEL_R = crate :: BitReader < CLKSEL_BUSCLK_SEL_A > ; # [doc = "Selects BUS CLK as clock source if enabled\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CLKSEL_BUSCLK_SEL_A { # [doc = "0: DISABLE"] CLKSEL_BUSCLK_SEL_DISABLE = 0 , # [doc = "1: ENABLE"] CLKSEL_BUSCLK_SEL_ENABLE = 1 , } impl From < CLKSEL_BUSCLK_SEL_A > for bool { # [inline (always)] fn from (variant : CLKSEL_BUSCLK_SEL_A) -> Self { variant as u8 != 0 } } impl CLKSEL_BUSCLK_SEL_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CLKSEL_BUSCLK_SEL_A { match self . bits { false => CLKSEL_BUSCLK_SEL_A :: CLKSEL_BUSCLK_SEL_DISABLE , true => CLKSEL_BUSCLK_SEL_A :: CLKSEL_BUSCLK_SEL_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_clksel_busclk_sel_disable (& self) -> bool { * self == CLKSEL_BUSCLK_SEL_A :: CLKSEL_BUSCLK_SEL_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_clksel_busclk_sel_enable (& self) -> bool { * self == CLKSEL_BUSCLK_SEL_A :: CLKSEL_BUSCLK_SEL_ENABLE } } # [doc = "Field `CLKSEL_BUSCLK_SEL` writer - Selects BUS CLK as clock source if enabled"] pub type CLKSEL_BUSCLK_SEL_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CLKSEL_BUSCLK_SEL_A > ; impl < 'a , REG , const O : u8 > CLKSEL_BUSCLK_SEL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn clksel_busclk_sel_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CLKSEL_BUSCLK_SEL_A :: CLKSEL_BUSCLK_SEL_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn clksel_busclk_sel_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CLKSEL_BUSCLK_SEL_A :: CLKSEL_BUSCLK_SEL_ENABLE) } } impl R { # [doc = "Bit 1 - Selects LFCLK as clock source if enabled"] # [inline (always)] pub fn clksel_lfclk_sel (& self) -> CLKSEL_LFCLK_SEL_R { CLKSEL_LFCLK_SEL_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - Selects MFCLK as clock source if enabled"] # [inline (always)] pub fn clksel_mfclk_sel (& self) -> CLKSEL_MFCLK_SEL_R { CLKSEL_MFCLK_SEL_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - Selects BUS CLK as clock source if enabled"] # [inline (always)] pub fn clksel_busclk_sel (& self) -> CLKSEL_BUSCLK_SEL_R { CLKSEL_BUSCLK_SEL_R :: new (((self . bits >> 3) & 1) != 0) } } impl W { # [doc = "Bit 1 - Selects LFCLK as clock source if enabled"] # [inline (always)] # [must_use] pub fn clksel_lfclk_sel (& mut self) -> CLKSEL_LFCLK_SEL_W < CLKSEL_SPEC , 1 > { CLKSEL_LFCLK_SEL_W :: new (self) } # [doc = "Bit 2 - Selects MFCLK as clock source if enabled"] # [inline (always)] # [must_use] pub fn clksel_mfclk_sel (& mut self) -> CLKSEL_MFCLK_SEL_W <'_, CLKSEL_SPEC , 2 > { CLKSEL_MFCLK_SEL_W :: new (self) } # [doc = "Bit 3 - Selects BUS CLK as clock source if enabled"] # [inline (always)] # [must_use] pub fn clksel_busclk_sel (& mut self) -> CLKSEL_BUSCLK_SEL_W < CLKSEL_SPEC , 3 > { CLKSEL_BUSCLK_SEL_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Clock Select for Ultra Low Power peripherals\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clksel::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clksel::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CLKSEL_SPEC ; impl crate :: RegisterSpec for CLKSEL_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`clksel::R`](R) reader structure"] impl crate :: Readable for CLKSEL_SPEC { } # [doc = "`write(|w| ..)` method takes [`clksel::W`](W) writer structure"] impl crate :: Writable for CLKSEL_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets CLKSEL to value 0"] impl crate :: Resettable for CLKSEL_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/i2c0/sackctl.rs:1:13599 [INFO] [stdout] | [INFO] [stdout] 1 | ...tl_ackoen_on_start (& mut self) -> SACKCTL_ACKOEN_ON_START_W < SACKCTL_SPEC , 2 > { SACKCTL_ACKOEN_ON_START_W :: new (self) } # [doc =... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `SACKCTL` reader"] pub type R = crate :: R < SACKCTL_SPEC > ; # [doc = "Register `SACKCTL` writer"] pub type W = crate :: W < SACKCTL_SPEC > ; # [doc = "Field `SACKCTL_ACKOEN` reader - I2C Slave ACK Override Enable"] pub type SACKCTL_ACKOEN_R = crate :: BitReader < SACKCTL_ACKOEN_A > ; # [doc = "I2C Slave ACK Override Enable\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum SACKCTL_ACKOEN_A { # [doc = "0: DISABLE"] SACKCTL_ACKOEN_DISABLE = 0 , # [doc = "1: ENABLE"] SACKCTL_ACKOEN_ENABLE = 1 , } impl From < SACKCTL_ACKOEN_A > for bool { # [inline (always)] fn from (variant : SACKCTL_ACKOEN_A) -> Self { variant as u8 != 0 } } impl SACKCTL_ACKOEN_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> SACKCTL_ACKOEN_A { match self . bits { false => SACKCTL_ACKOEN_A :: SACKCTL_ACKOEN_DISABLE , true => SACKCTL_ACKOEN_A :: SACKCTL_ACKOEN_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_sackctl_ackoen_disable (& self) -> bool { * self == SACKCTL_ACKOEN_A :: SACKCTL_ACKOEN_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_sackctl_ackoen_enable (& self) -> bool { * self == SACKCTL_ACKOEN_A :: SACKCTL_ACKOEN_ENABLE } } # [doc = "Field `SACKCTL_ACKOEN` writer - I2C Slave ACK Override Enable"] pub type SACKCTL_ACKOEN_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , SACKCTL_ACKOEN_A > ; impl < 'a , REG , const O : u8 > SACKCTL_ACKOEN_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn sackctl_ackoen_disable (self) -> & 'a mut crate :: W < REG > { self . variant (SACKCTL_ACKOEN_A :: SACKCTL_ACKOEN_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn sackctl_ackoen_enable (self) -> & 'a mut crate :: W < REG > { self . variant (SACKCTL_ACKOEN_A :: SACKCTL_ACKOEN_ENABLE) } } # [doc = "Field `SACKCTL_ACKOVAL` reader - I2C Slave ACK Override Value Note: for General Call this bit will be ignored if set to NACK and slave continues to receive data."] pub type SACKCTL_ACKOVAL_R = crate :: BitReader < SACKCTL_ACKOVAL_A > ; # [doc = "I2C Slave ACK Override Value Note: for General Call this bit will be ignored if set to NACK and slave continues to receive data.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum SACKCTL_ACKOVAL_A { # [doc = "0: DISABLE"] SACKCTL_ACKOVAL_DISABLE = 0 , # [doc = "1: ENABLE"] SACKCTL_ACKOVAL_ENABLE = 1 , } impl From < SACKCTL_ACKOVAL_A > for bool { # [inline (always)] fn from (variant : SACKCTL_ACKOVAL_A) -> Self { variant as u8 != 0 } } impl SACKCTL_ACKOVAL_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> SACKCTL_ACKOVAL_A { match self . bits { false => SACKCTL_ACKOVAL_A :: SACKCTL_ACKOVAL_DISABLE , true => SACKCTL_ACKOVAL_A :: SACKCTL_ACKOVAL_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_sackctl_ackoval_disable (& self) -> bool { * self == SACKCTL_ACKOVAL_A :: SACKCTL_ACKOVAL_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_sackctl_ackoval_enable (& self) -> bool { * self == SACKCTL_ACKOVAL_A :: SACKCTL_ACKOVAL_ENABLE } } # [doc = "Field `SACKCTL_ACKOVAL` writer - I2C Slave ACK Override Value Note: for General Call this bit will be ignored if set to NACK and slave continues to receive data."] pub type SACKCTL_ACKOVAL_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , SACKCTL_ACKOVAL_A > ; impl < 'a , REG , const O : u8 > SACKCTL_ACKOVAL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn sackctl_ackoval_disable (self) -> & 'a mut crate :: W < REG > { self . variant (SACKCTL_ACKOVAL_A :: SACKCTL_ACKOVAL_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn sackctl_ackoval_enable (self) -> & 'a mut crate :: W < REG > { self . variant (SACKCTL_ACKOVAL_A :: SACKCTL_ACKOVAL_ENABLE) } } # [doc = "Field `SACKCTL_ACKOEN_ON_START` reader - When set this bit will automatically turn on the Slave ACKOEN field following a Start Condition."] pub type SACKCTL_ACKOEN_ON_START_R = crate :: BitReader < SACKCTL_ACKOEN_ON_START_A > ; # [doc = "When set this bit will automatically turn on the Slave ACKOEN field following a Start Condition.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum SACKCTL_ACKOEN_ON_START_A { # [doc = "0: DISABLE"] SACKCTL_ACKOEN_ON_START_DISABLE = 0 , # [doc = "1: ENABLE"] SACKCTL_ACKOEN_ON_START_ENABLE = 1 , } impl From < SACKCTL_ACKOEN_ON_START_A > for bool { # [inline (always)] fn from (variant : SACKCTL_ACKOEN_ON_START_A) -> Self { variant as u8 != 0 } } impl SACKCTL_ACKOEN_ON_START_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> SACKCTL_ACKOEN_ON_START_A { match self . bits { false => SACKCTL_ACKOEN_ON_START_A :: SACKCTL_ACKOEN_ON_START_DISABLE , true => SACKCTL_ACKOEN_ON_START_A :: SACKCTL_ACKOEN_ON_START_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_sackctl_ackoen_on_start_disable (& self) -> bool { * self == SACKCTL_ACKOEN_ON_START_A :: SACKCTL_ACKOEN_ON_START_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_sackctl_ackoen_on_start_enable (& self) -> bool { * self == SACKCTL_ACKOEN_ON_START_A :: SACKCTL_ACKOEN_ON_START_ENABLE } } # [doc = "Field `SACKCTL_ACKOEN_ON_START` writer - When set this bit will automatically turn on the Slave ACKOEN field following a Start Condition."] pub type SACKCTL_ACKOEN_ON_START_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , SACKCTL_ACKOEN_ON_START_A > ; impl < 'a , REG , const O : u8 > SACKCTL_ACKOEN_ON_START_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn sackctl_ackoen_on_start_disable (self) -> & 'a mut crate :: W < REG > { self . variant (SACKCTL_ACKOEN_ON_START_A :: SACKCTL_ACKOEN_ON_START_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn sackctl_ackoen_on_start_enable (self) -> & 'a mut crate :: W < REG > { self . variant (SACKCTL_ACKOEN_ON_START_A :: SACKCTL_ACKOEN_ON_START_ENABLE) } } # [doc = "Field `SACKCTL_ACKOEN_ON_PECNEXT` reader - When set this bit will automatically turn on the Slave ACKOEN field following the ACK/NACK of the byte received just prior to the PEC byte. Note that when ACKOEN is set the PEC byte will not automatically be ACKed/NACKed by the State Machine and FW must perform this function by writing SLAVE_SACKCTL."] pub type SACKCTL_ACKOEN_ON_PECNEXT_R = crate :: BitReader < SACKCTL_ACKOEN_ON_PECNEXT_A > ; # [doc = "When set this bit will automatically turn on the Slave ACKOEN field following the ACK/NACK of the byte received just prior to the PEC byte. Note that when ACKOEN is set the PEC byte will not automatically be ACKed/NACKed by the State Machine and FW must perform this function by writing SLAVE_SACKCTL.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum SACKCTL_ACKOEN_ON_PECNEXT_A { # [doc = "0: DISABLE"] SACKCTL_ACKOEN_ON_PECNEXT_DISABLE = 0 , # [doc = "1: ENABLE"] SACKCTL_ACKOEN_ON_PECNEXT_ENABLE = 1 , } impl From < SACKCTL_ACKOEN_ON_PECNEXT_A > for bool { # [inline (always)] fn from (variant : SACKCTL_ACKOEN_ON_PECNEXT_A) -> Self { variant as u8 != 0 } } impl SACKCTL_ACKOEN_ON_PECNEXT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> SACKCTL_ACKOEN_ON_PECNEXT_A { match self . bits { false => SACKCTL_ACKOEN_ON_PECNEXT_A :: SACKCTL_ACKOEN_ON_PECNEXT_DISABLE , true => SACKCTL_ACKOEN_ON_PECNEXT_A :: SACKCTL_ACKOEN_ON_PECNEXT_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_sackctl_ackoen_on_pecnext_disable (& self) -> bool { * self == SACKCTL_ACKOEN_ON_PECNEXT_A :: SACKCTL_ACKOEN_ON_PECNEXT_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_sackctl_ackoen_on_pecnext_enable (& self) -> bool { * self == SACKCTL_ACKOEN_ON_PECNEXT_A :: SACKCTL_ACKOEN_ON_PECNEXT_ENABLE } } # [doc = "Field `SACKCTL_ACKOEN_ON_PECNEXT` writer - When set this bit will automatically turn on the Slave ACKOEN field following the ACK/NACK of the byte received just prior to the PEC byte. Note that when ACKOEN is set the PEC byte will not automatically be ACKed/NACKed by the State Machine and FW must perform this function by writing SLAVE_SACKCTL."] pub type SACKCTL_ACKOEN_ON_PECNEXT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , SACKCTL_ACKOEN_ON_PECNEXT_A > ; impl < 'a , REG , const O : u8 > SACKCTL_ACKOEN_ON_PECNEXT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn sackctl_ackoen_on_pecnext_disable (self) -> & 'a mut crate :: W < REG > { self . variant (SACKCTL_ACKOEN_ON_PECNEXT_A :: SACKCTL_ACKOEN_ON_PECNEXT_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn sackctl_ackoen_on_pecnext_enable (self) -> & 'a mut crate :: W < REG > { self . variant (SACKCTL_ACKOEN_ON_PECNEXT_A :: SACKCTL_ACKOEN_ON_PECNEXT_ENABLE) } } # [doc = "Field `SACKCTL_ACKOEN_ON_PECDONE` reader - When set this bit will automatically turn on the Slave ACKOEN field following the ACK/NACK of the received PEC byte."] pub type SACKCTL_ACKOEN_ON_PECDONE_R = crate :: BitReader < SACKCTL_ACKOEN_ON_PECDONE_A > ; # [doc = "When set this bit will automatically turn on the Slave ACKOEN field following the ACK/NACK of the received PEC byte.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum SACKCTL_ACKOEN_ON_PECDONE_A { # [doc = "0: DISABLE"] SACKCTL_ACKOEN_ON_PECDONE_DISABLE = 0 , # [doc = "1: ENABLE"] SACKCTL_ACKOEN_ON_PECDONE_ENABLE = 1 , } impl From < SACKCTL_ACKOEN_ON_PECDONE_A > for bool { # [inline (always)] fn from (variant : SACKCTL_ACKOEN_ON_PECDONE_A) -> Self { variant as u8 != 0 } } impl SACKCTL_ACKOEN_ON_PECDONE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> SACKCTL_ACKOEN_ON_PECDONE_A { match self . bits { false => SACKCTL_ACKOEN_ON_PECDONE_A :: SACKCTL_ACKOEN_ON_PECDONE_DISABLE , true => SACKCTL_ACKOEN_ON_PECDONE_A :: SACKCTL_ACKOEN_ON_PECDONE_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_sackctl_ackoen_on_pecdone_disable (& self) -> bool { * self == SACKCTL_ACKOEN_ON_PECDONE_A :: SACKCTL_ACKOEN_ON_PECDONE_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_sackctl_ackoen_on_pecdone_enable (& self) -> bool { * self == SACKCTL_ACKOEN_ON_PECDONE_A :: SACKCTL_ACKOEN_ON_PECDONE_ENABLE } } # [doc = "Field `SACKCTL_ACKOEN_ON_PECDONE` writer - When set this bit will automatically turn on the Slave ACKOEN field following the ACK/NACK of the received PEC byte."] pub type SACKCTL_ACKOEN_ON_PECDONE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , SACKCTL_ACKOEN_ON_PECDONE_A > ; impl < 'a , REG , const O : u8 > SACKCTL_ACKOEN_ON_PECDONE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn sackctl_ackoen_on_pecdone_disable (self) -> & 'a mut crate :: W < REG > { self . variant (SACKCTL_ACKOEN_ON_PECDONE_A :: SACKCTL_ACKOEN_ON_PECDONE_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn sackctl_ackoen_on_pecdone_enable (self) -> & 'a mut crate :: W < REG > { self . variant (SACKCTL_ACKOEN_ON_PECDONE_A :: SACKCTL_ACKOEN_ON_PECDONE_ENABLE) } } impl R { # [doc = "Bit 0 - I2C Slave ACK Override Enable"] # [inline (always)] pub fn sackctl_ackoen (& self) -> SACKCTL_ACKOEN_R { SACKCTL_ACKOEN_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - I2C Slave ACK Override Value Note: for General Call this bit will be ignored if set to NACK and slave continues to receive data."] # [inline (always)] pub fn sackctl_ackoval (& self) -> SACKCTL_ACKOVAL_R { SACKCTL_ACKOVAL_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - When set this bit will automatically turn on the Slave ACKOEN field following a Start Condition."] # [inline (always)] pub fn sackctl_ackoen_on_start (& self) -> SACKCTL_ACKOEN_ON_START_R { SACKCTL_ACKOEN_ON_START_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - When set this bit will automatically turn on the Slave ACKOEN field following the ACK/NACK of the byte received just prior to the PEC byte. Note that when ACKOEN is set the PEC byte will not automatically be ACKed/NACKed by the State Machine and FW must perform this function by writing SLAVE_SACKCTL."] # [inline (always)] pub fn sackctl_ackoen_on_pecnext (& self) -> SACKCTL_ACKOEN_ON_PECNEXT_R { SACKCTL_ACKOEN_ON_PECNEXT_R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - When set this bit will automatically turn on the Slave ACKOEN field following the ACK/NACK of the received PEC byte."] # [inline (always)] pub fn sackctl_ackoen_on_pecdone (& self) -> SACKCTL_ACKOEN_ON_PECDONE_R { SACKCTL_ACKOEN_ON_PECDONE_R :: new (((self . bits >> 4) & 1) != 0) } } impl W { # [doc = "Bit 0 - I2C Slave ACK Override Enable"] # [inline (always)] # [must_use] pub fn sackctl_ackoen (& mut self) -> SACKCTL_ACKOEN_W < SACKCTL_SPEC , 0 > { SACKCTL_ACKOEN_W :: new (self) } # [doc = "Bit 1 - I2C Slave ACK Override Value Note: for General Call this bit will be ignored if set to NACK and slave continues to receive data."] # [inline (always)] # [must_use] pub fn sackctl_ackoval (& mut self) -> SACKCTL_ACKOVAL_W < SACKCTL_SPEC , 1 > { SACKCTL_ACKOVAL_W :: new (self) } # [doc = "Bit 2 - When set this bit will automatically turn on the Slave ACKOEN field following a Start Condition."] # [inline (always)] # [must_use] pub fn sackctl_ackoen_on_start (& mut self) -> SACKCTL_ACKOEN_ON_START_W <'_, SACKCTL_SPEC , 2 > { SACKCTL_ACKOEN_ON_START_W :: new (self) } # [doc = "Bit 3 - When set this bit will automatically turn on the Slave ACKOEN field following the ACK/NACK of the byte received just prior to the PEC byte. Note that when ACKOEN is set the PEC byte will not automatically be ACKed/NACKed by the State Machine and FW must perform this function by writing SLAVE_SACKCTL."] # [inline (always)] # [must_use] pub fn sackctl_ackoen_on_pecnext (& mut self) -> SACKCTL_ACKOEN_ON_PECNEXT_W < SACKCTL_SPEC , 3 > { SACKCTL_ACKOEN_ON_PECNEXT_W :: new (self) } # [doc = "Bit 4 - When set this bit will automatically turn on the Slave ACKOEN field following the ACK/NACK of the received PEC byte."] # [inline (always)] # [must_use] pub fn sackctl_ackoen_on_pecdone (& mut self) -> SACKCTL_ACKOEN_ON_PECDONE_W < SACKCTL_SPEC , 4 > { SACKCTL_ACKOEN_ON_PECDONE_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "I2C Slave ACK Control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sackctl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sackctl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct SACKCTL_SPEC ; impl crate :: RegisterSpec for SACKCTL_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`sackctl::R`](R) reader structure"] impl crate :: Readable for SACKCTL_SPEC { } # [doc = "`write(|w| ..)` method takes [`sackctl::W`](W) writer structure"] impl crate :: Writable for SACKCTL_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets SACKCTL to value 0"] impl crate :: Resettable for SACKCTL_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/i2c1/soar.rs:1:5262 [INFO] [stdout] | [INFO] [stdout] 1 | ... [must_use] pub fn soar_oar (& mut self) -> SOAR_OAR_W < SOAR_SPEC , 0 > { SOAR_OAR_W :: new (self) } # [doc = "Bit 14 - I2C Slave Own... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `SOAR` reader"] pub type R = crate :: R < SOAR_SPEC > ; # [doc = "Register `SOAR` writer"] pub type W = crate :: W < SOAR_SPEC > ; # [doc = "Field `SOAR_OAR` reader - I2C Slave Own Address: This field specifies bits A9 through A0 of the slave address. In 7-bit addressing mode as selected by I2CSOAR.MODE bit, the top 3 bits are don't care"] pub type SOAR_OAR_R = crate :: FieldReader < u16 > ; # [doc = "Field `SOAR_OAR` writer - I2C Slave Own Address: This field specifies bits A9 through A0 of the slave address. In 7-bit addressing mode as selected by I2CSOAR.MODE bit, the top 3 bits are don't care"] pub type SOAR_OAR_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 10 , O , u16 > ; # [doc = "Field `SOAR_OAREN` reader - I2C Slave Own Address Enable"] pub type SOAR_OAREN_R = crate :: BitReader < SOAR_OAREN_A > ; # [doc = "I2C Slave Own Address Enable\n\nValue on reset: 1"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum SOAR_OAREN_A { # [doc = "0: DISABLE"] SOAR_OAREN_DISABLE = 0 , # [doc = "1: ENABLE"] SOAR_OAREN_ENABLE = 1 , } impl From < SOAR_OAREN_A > for bool { # [inline (always)] fn from (variant : SOAR_OAREN_A) -> Self { variant as u8 != 0 } } impl SOAR_OAREN_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> SOAR_OAREN_A { match self . bits { false => SOAR_OAREN_A :: SOAR_OAREN_DISABLE , true => SOAR_OAREN_A :: SOAR_OAREN_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_soar_oaren_disable (& self) -> bool { * self == SOAR_OAREN_A :: SOAR_OAREN_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_soar_oaren_enable (& self) -> bool { * self == SOAR_OAREN_A :: SOAR_OAREN_ENABLE } } # [doc = "Field `SOAR_OAREN` writer - I2C Slave Own Address Enable"] pub type SOAR_OAREN_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , SOAR_OAREN_A > ; impl < 'a , REG , const O : u8 > SOAR_OAREN_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn soar_oaren_disable (self) -> & 'a mut crate :: W < REG > { self . variant (SOAR_OAREN_A :: SOAR_OAREN_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn soar_oaren_enable (self) -> & 'a mut crate :: W < REG > { self . variant (SOAR_OAREN_A :: SOAR_OAREN_ENABLE) } } # [doc = "Field `SOAR_SMODE` reader - This bit selects the adressing mode to be used in slave mode. When 0, 7-bit addressing is used. When 1, 10-bit addressing is used."] pub type SOAR_SMODE_R = crate :: BitReader < SOAR_SMODE_A > ; # [doc = "This bit selects the adressing mode to be used in slave mode. When 0, 7-bit addressing is used. When 1, 10-bit addressing is used.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum SOAR_SMODE_A { # [doc = "0: MODE7"] SOAR_SMODE_MODE7 = 0 , # [doc = "1: MODE10"] SOAR_SMODE_MODE10 = 1 , } impl From < SOAR_SMODE_A > for bool { # [inline (always)] fn from (variant : SOAR_SMODE_A) -> Self { variant as u8 != 0 } } impl SOAR_SMODE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> SOAR_SMODE_A { match self . bits { false => SOAR_SMODE_A :: SOAR_SMODE_MODE7 , true => SOAR_SMODE_A :: SOAR_SMODE_MODE10 , } } # [doc = "MODE7"] # [inline (always)] pub fn is_soar_smode_mode7 (& self) -> bool { * self == SOAR_SMODE_A :: SOAR_SMODE_MODE7 } # [doc = "MODE10"] # [inline (always)] pub fn is_soar_smode_mode10 (& self) -> bool { * self == SOAR_SMODE_A :: SOAR_SMODE_MODE10 } } # [doc = "Field `SOAR_SMODE` writer - This bit selects the adressing mode to be used in slave mode. When 0, 7-bit addressing is used. When 1, 10-bit addressing is used."] pub type SOAR_SMODE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , SOAR_SMODE_A > ; impl < 'a , REG , const O : u8 > SOAR_SMODE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "MODE7"] # [inline (always)] pub fn soar_smode_mode7 (self) -> & 'a mut crate :: W < REG > { self . variant (SOAR_SMODE_A :: SOAR_SMODE_MODE7) } # [doc = "MODE10"] # [inline (always)] pub fn soar_smode_mode10 (self) -> & 'a mut crate :: W < REG > { self . variant (SOAR_SMODE_A :: SOAR_SMODE_MODE10) } } impl R { # [doc = "Bits 0:9 - I2C Slave Own Address: This field specifies bits A9 through A0 of the slave address. In 7-bit addressing mode as selected by I2CSOAR.MODE bit, the top 3 bits are don't care"] # [inline (always)] pub fn soar_oar (& self) -> SOAR_OAR_R { SOAR_OAR_R :: new ((self . bits & 0x03ff) as u16) } # [doc = "Bit 14 - I2C Slave Own Address Enable"] # [inline (always)] pub fn soar_oaren (& self) -> SOAR_OAREN_R { SOAR_OAREN_R :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - This bit selects the adressing mode to be used in slave mode. When 0, 7-bit addressing is used. When 1, 10-bit addressing is used."] # [inline (always)] pub fn soar_smode (& self) -> SOAR_SMODE_R { SOAR_SMODE_R :: new (((self . bits >> 15) & 1) != 0) } } impl W { # [doc = "Bits 0:9 - I2C Slave Own Address: This field specifies bits A9 through A0 of the slave address. In 7-bit addressing mode as selected by I2CSOAR.MODE bit, the top 3 bits are don't care"] # [inline (always)] # [must_use] pub fn soar_oar (& mut self) -> SOAR_OAR_W <'_, SOAR_SPEC , 0 > { SOAR_OAR_W :: new (self) } # [doc = "Bit 14 - I2C Slave Own Address Enable"] # [inline (always)] # [must_use] pub fn soar_oaren (& mut self) -> SOAR_OAREN_W < SOAR_SPEC , 14 > { SOAR_OAREN_W :: new (self) } # [doc = "Bit 15 - This bit selects the adressing mode to be used in slave mode. When 0, 7-bit addressing is used. When 1, 10-bit addressing is used."] # [inline (always)] # [must_use] pub fn soar_smode (& mut self) -> SOAR_SMODE_W < SOAR_SPEC , 15 > { SOAR_SMODE_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "I2C Slave Own Address\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`soar::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`soar::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct SOAR_SPEC ; impl crate :: RegisterSpec for SOAR_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`soar::R`](R) reader structure"] impl crate :: Readable for SOAR_SPEC { } # [doc = "`write(|w| ..)` method takes [`soar::W`](W) writer structure"] impl crate :: Writable for SOAR_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets SOAR to value 0x4000"] impl crate :: Resettable for SOAR_SPEC { const RESET_VALUE : Self :: Ux = 0x4000 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/i2c0/mcr.rs:1:9571 [INFO] [stdout] | [INFO] [stdout] 1 | ...e] pub fn mcr_clkstretch (& mut self) -> MCR_CLKSTRETCH_W < MCR_SPEC , 2 > { MCR_CLKSTRETCH_W :: new (self) } # [doc = "Bit 8 - I2C Lo... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `MCR` reader"] pub type R = crate :: R < MCR_SPEC > ; # [doc = "Register `MCR` writer"] pub type W = crate :: W < MCR_SPEC > ; # [doc = "Field `MCR_ACTIVE` reader - Device Active After this bit has been set, it should not be set again unless it has been cleared by writing a 0 or by a reset, otherwise transfer failures may occur."] pub type MCR_ACTIVE_R = crate :: BitReader < MCR_ACTIVE_A > ; # [doc = "Device Active After this bit has been set, it should not be set again unless it has been cleared by writing a 0 or by a reset, otherwise transfer failures may occur.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum MCR_ACTIVE_A { # [doc = "0: DISABLE"] MCR_ACTIVE_DISABLE = 0 , # [doc = "1: ENABLE"] MCR_ACTIVE_ENABLE = 1 , } impl From < MCR_ACTIVE_A > for bool { # [inline (always)] fn from (variant : MCR_ACTIVE_A) -> Self { variant as u8 != 0 } } impl MCR_ACTIVE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> MCR_ACTIVE_A { match self . bits { false => MCR_ACTIVE_A :: MCR_ACTIVE_DISABLE , true => MCR_ACTIVE_A :: MCR_ACTIVE_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_mcr_active_disable (& self) -> bool { * self == MCR_ACTIVE_A :: MCR_ACTIVE_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_mcr_active_enable (& self) -> bool { * self == MCR_ACTIVE_A :: MCR_ACTIVE_ENABLE } } # [doc = "Field `MCR_ACTIVE` writer - Device Active After this bit has been set, it should not be set again unless it has been cleared by writing a 0 or by a reset, otherwise transfer failures may occur."] pub type MCR_ACTIVE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , MCR_ACTIVE_A > ; impl < 'a , REG , const O : u8 > MCR_ACTIVE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn mcr_active_disable (self) -> & 'a mut crate :: W < REG > { self . variant (MCR_ACTIVE_A :: MCR_ACTIVE_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn mcr_active_enable (self) -> & 'a mut crate :: W < REG > { self . variant (MCR_ACTIVE_A :: MCR_ACTIVE_ENABLE) } } # [doc = "Field `MCR_MMST` reader - Multimaster mode. In Multimaster mode the SCL high time counts once the SCL line has been detected high. If this is not enabled the high time counts as soon as the SCL line has been set high by the I2C controller."] pub type MCR_MMST_R = crate :: BitReader < MCR_MMST_A > ; # [doc = "Multimaster mode. In Multimaster mode the SCL high time counts once the SCL line has been detected high. If this is not enabled the high time counts as soon as the SCL line has been set high by the I2C controller.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum MCR_MMST_A { # [doc = "0: DISABLE"] MCR_MMST_DISABLE = 0 , # [doc = "1: ENABLE"] MCR_MMST_ENABLE = 1 , } impl From < MCR_MMST_A > for bool { # [inline (always)] fn from (variant : MCR_MMST_A) -> Self { variant as u8 != 0 } } impl MCR_MMST_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> MCR_MMST_A { match self . bits { false => MCR_MMST_A :: MCR_MMST_DISABLE , true => MCR_MMST_A :: MCR_MMST_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_mcr_mmst_disable (& self) -> bool { * self == MCR_MMST_A :: MCR_MMST_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_mcr_mmst_enable (& self) -> bool { * self == MCR_MMST_A :: MCR_MMST_ENABLE } } # [doc = "Field `MCR_MMST` writer - Multimaster mode. In Multimaster mode the SCL high time counts once the SCL line has been detected high. If this is not enabled the high time counts as soon as the SCL line has been set high by the I2C controller."] pub type MCR_MMST_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , MCR_MMST_A > ; impl < 'a , REG , const O : u8 > MCR_MMST_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn mcr_mmst_disable (self) -> & 'a mut crate :: W < REG > { self . variant (MCR_MMST_A :: MCR_MMST_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn mcr_mmst_enable (self) -> & 'a mut crate :: W < REG > { self . variant (MCR_MMST_A :: MCR_MMST_ENABLE) } } # [doc = "Field `MCR_CLKSTRETCH` reader - Clock Stretching. This bit controls the support for clock stretching of the I2C bus."] pub type MCR_CLKSTRETCH_R = crate :: BitReader < MCR_CLKSTRETCH_A > ; # [doc = "Clock Stretching. This bit controls the support for clock stretching of the I2C bus.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum MCR_CLKSTRETCH_A { # [doc = "0: DISABLE"] MCR_CLKSTRETCH_DISABLE = 0 , # [doc = "1: ENABLE"] MCR_CLKSTRETCH_ENABLE = 1 , } impl From < MCR_CLKSTRETCH_A > for bool { # [inline (always)] fn from (variant : MCR_CLKSTRETCH_A) -> Self { variant as u8 != 0 } } impl MCR_CLKSTRETCH_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> MCR_CLKSTRETCH_A { match self . bits { false => MCR_CLKSTRETCH_A :: MCR_CLKSTRETCH_DISABLE , true => MCR_CLKSTRETCH_A :: MCR_CLKSTRETCH_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_mcr_clkstretch_disable (& self) -> bool { * self == MCR_CLKSTRETCH_A :: MCR_CLKSTRETCH_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_mcr_clkstretch_enable (& self) -> bool { * self == MCR_CLKSTRETCH_A :: MCR_CLKSTRETCH_ENABLE } } # [doc = "Field `MCR_CLKSTRETCH` writer - Clock Stretching. This bit controls the support for clock stretching of the I2C bus."] pub type MCR_CLKSTRETCH_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , MCR_CLKSTRETCH_A > ; impl < 'a , REG , const O : u8 > MCR_CLKSTRETCH_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn mcr_clkstretch_disable (self) -> & 'a mut crate :: W < REG > { self . variant (MCR_CLKSTRETCH_A :: MCR_CLKSTRETCH_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn mcr_clkstretch_enable (self) -> & 'a mut crate :: W < REG > { self . variant (MCR_CLKSTRETCH_A :: MCR_CLKSTRETCH_ENABLE) } } # [doc = "Field `MCR_LPBK` reader - I2C Loopback"] pub type MCR_LPBK_R = crate :: BitReader < MCR_LPBK_A > ; # [doc = "I2C Loopback\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum MCR_LPBK_A { # [doc = "0: DISABLE"] MCR_LPBK_DISABLE = 0 , # [doc = "1: ENABLE"] MCR_LPBK_ENABLE = 1 , } impl From < MCR_LPBK_A > for bool { # [inline (always)] fn from (variant : MCR_LPBK_A) -> Self { variant as u8 != 0 } } impl MCR_LPBK_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> MCR_LPBK_A { match self . bits { false => MCR_LPBK_A :: MCR_LPBK_DISABLE , true => MCR_LPBK_A :: MCR_LPBK_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_mcr_lpbk_disable (& self) -> bool { * self == MCR_LPBK_A :: MCR_LPBK_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_mcr_lpbk_enable (& self) -> bool { * self == MCR_LPBK_A :: MCR_LPBK_ENABLE } } # [doc = "Field `MCR_LPBK` writer - I2C Loopback"] pub type MCR_LPBK_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , MCR_LPBK_A > ; impl < 'a , REG , const O : u8 > MCR_LPBK_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn mcr_lpbk_disable (self) -> & 'a mut crate :: W < REG > { self . variant (MCR_LPBK_A :: MCR_LPBK_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn mcr_lpbk_enable (self) -> & 'a mut crate :: W < REG > { self . variant (MCR_LPBK_A :: MCR_LPBK_ENABLE) } } impl R { # [doc = "Bit 0 - Device Active After this bit has been set, it should not be set again unless it has been cleared by writing a 0 or by a reset, otherwise transfer failures may occur."] # [inline (always)] pub fn mcr_active (& self) -> MCR_ACTIVE_R { MCR_ACTIVE_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - Multimaster mode. In Multimaster mode the SCL high time counts once the SCL line has been detected high. If this is not enabled the high time counts as soon as the SCL line has been set high by the I2C controller."] # [inline (always)] pub fn mcr_mmst (& self) -> MCR_MMST_R { MCR_MMST_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - Clock Stretching. This bit controls the support for clock stretching of the I2C bus."] # [inline (always)] pub fn mcr_clkstretch (& self) -> MCR_CLKSTRETCH_R { MCR_CLKSTRETCH_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 8 - I2C Loopback"] # [inline (always)] pub fn mcr_lpbk (& self) -> MCR_LPBK_R { MCR_LPBK_R :: new (((self . bits >> 8) & 1) != 0) } } impl W { # [doc = "Bit 0 - Device Active After this bit has been set, it should not be set again unless it has been cleared by writing a 0 or by a reset, otherwise transfer failures may occur."] # [inline (always)] # [must_use] pub fn mcr_active (& mut self) -> MCR_ACTIVE_W < MCR_SPEC , 0 > { MCR_ACTIVE_W :: new (self) } # [doc = "Bit 1 - Multimaster mode. In Multimaster mode the SCL high time counts once the SCL line has been detected high. If this is not enabled the high time counts as soon as the SCL line has been set high by the I2C controller."] # [inline (always)] # [must_use] pub fn mcr_mmst (& mut self) -> MCR_MMST_W < MCR_SPEC , 1 > { MCR_MMST_W :: new (self) } # [doc = "Bit 2 - Clock Stretching. This bit controls the support for clock stretching of the I2C bus."] # [inline (always)] # [must_use] pub fn mcr_clkstretch (& mut self) -> MCR_CLKSTRETCH_W <'_, MCR_SPEC , 2 > { MCR_CLKSTRETCH_W :: new (self) } # [doc = "Bit 8 - I2C Loopback"] # [inline (always)] # [must_use] pub fn mcr_lpbk (& mut self) -> MCR_LPBK_W < MCR_SPEC , 8 > { MCR_LPBK_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "I2C Master Configuration\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mcr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mcr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct MCR_SPEC ; impl crate :: RegisterSpec for MCR_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`mcr::R`](R) reader structure"] impl crate :: Readable for MCR_SPEC { } # [doc = "`write(|w| ..)` method takes [`mcr::W`](W) writer structure"] impl crate :: Writable for MCR_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets MCR to value 0"] impl crate :: Resettable for MCR_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/opa1/cfg.rs:1:17465 [INFO] [stdout] | [INFO] [stdout] 1 | ... [must_use] pub fn cfg_msel (& mut self) -> CFG_MSEL_W < CFG_SPEC , 10 > { CFG_MSEL_W :: new (self) } # [doc = "Bits 13:15 - Gain sett... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `CFG` reader"] pub type R = crate :: R < CFG_SPEC > ; # [doc = "Register `CFG` writer"] pub type W = crate :: W < CFG_SPEC > ; # [doc = "Field `CFG_CHOP` reader - Chopping enable."] pub type CFG_CHOP_R = crate :: FieldReader < CFG_CHOP_A > ; # [doc = "Chopping enable.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum CFG_CHOP_A { # [doc = "0: OFF"] CFG_CHOP_OFF = 0 , # [doc = "1: ON"] CFG_CHOP_ON = 1 , # [doc = "2: AVGON"] CFG_CHOP_AVGON = 2 , } impl From < CFG_CHOP_A > for u8 { # [inline (always)] fn from (variant : CFG_CHOP_A) -> Self { variant as _ } } impl crate :: FieldSpec for CFG_CHOP_A { type Ux = u8 ; } impl CFG_CHOP_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < CFG_CHOP_A > { match self . bits { 0 => Some (CFG_CHOP_A :: CFG_CHOP_OFF) , 1 => Some (CFG_CHOP_A :: CFG_CHOP_ON) , 2 => Some (CFG_CHOP_A :: CFG_CHOP_AVGON) , _ => None , } } # [doc = "OFF"] # [inline (always)] pub fn is_cfg_chop_off (& self) -> bool { * self == CFG_CHOP_A :: CFG_CHOP_OFF } # [doc = "ON"] # [inline (always)] pub fn is_cfg_chop_on (& self) -> bool { * self == CFG_CHOP_A :: CFG_CHOP_ON } # [doc = "AVGON"] # [inline (always)] pub fn is_cfg_chop_avgon (& self) -> bool { * self == CFG_CHOP_A :: CFG_CHOP_AVGON } } # [doc = "Field `CFG_CHOP` writer - Chopping enable."] pub type CFG_CHOP_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 2 , O , CFG_CHOP_A > ; impl < 'a , REG , const O : u8 > CFG_CHOP_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "OFF"] # [inline (always)] pub fn cfg_chop_off (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_CHOP_A :: CFG_CHOP_OFF) } # [doc = "ON"] # [inline (always)] pub fn cfg_chop_on (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_CHOP_A :: CFG_CHOP_ON) } # [doc = "AVGON"] # [inline (always)] pub fn cfg_chop_avgon (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_CHOP_A :: CFG_CHOP_AVGON) } } # [doc = "Field `CFG_OUTPIN` reader - Enable output pin"] pub type CFG_OUTPIN_R = crate :: BitReader < CFG_OUTPIN_A > ; # [doc = "Enable output pin\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CFG_OUTPIN_A { # [doc = "0: DISABLED"] CFG_OUTPIN_DISABLED = 0 , # [doc = "1: ENABLED"] CFG_OUTPIN_ENABLED = 1 , } impl From < CFG_OUTPIN_A > for bool { # [inline (always)] fn from (variant : CFG_OUTPIN_A) -> Self { variant as u8 != 0 } } impl CFG_OUTPIN_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CFG_OUTPIN_A { match self . bits { false => CFG_OUTPIN_A :: CFG_OUTPIN_DISABLED , true => CFG_OUTPIN_A :: CFG_OUTPIN_ENABLED , } } # [doc = "DISABLED"] # [inline (always)] pub fn is_cfg_outpin_disabled (& self) -> bool { * self == CFG_OUTPIN_A :: CFG_OUTPIN_DISABLED } # [doc = "ENABLED"] # [inline (always)] pub fn is_cfg_outpin_enabled (& self) -> bool { * self == CFG_OUTPIN_A :: CFG_OUTPIN_ENABLED } } # [doc = "Field `CFG_OUTPIN` writer - Enable output pin"] pub type CFG_OUTPIN_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CFG_OUTPIN_A > ; impl < 'a , REG , const O : u8 > CFG_OUTPIN_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLED"] # [inline (always)] pub fn cfg_outpin_disabled (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_OUTPIN_A :: CFG_OUTPIN_DISABLED) } # [doc = "ENABLED"] # [inline (always)] pub fn cfg_outpin_enabled (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_OUTPIN_A :: CFG_OUTPIN_ENABLED) } } # [doc = "Field `CFG_PSEL` reader - Positive OA input selection. Please refer to the device specific datasheet for exact channels available."] pub type CFG_PSEL_R = crate :: FieldReader < CFG_PSEL_A > ; # [doc = "Positive OA input selection. Please refer to the device specific datasheet for exact channels available.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum CFG_PSEL_A { # [doc = "0: NC"] CFG_PSEL_NC = 0 , # [doc = "1: EXTPIN0"] CFG_PSEL_EXTPIN0 = 1 , # [doc = "2: EXTPIN1"] CFG_PSEL_EXTPIN1 = 2 , # [doc = "3: DAC12OUT"] CFG_PSEL_DAC12OUT = 3 , # [doc = "4: DAC8OUT"] CFG_PSEL_DAC8OUT = 4 , # [doc = "5: VREF"] CFG_PSEL_VREF = 5 , # [doc = "6: OANM1RTOP"] CFG_PSEL_OANM1RTOP = 6 , # [doc = "7: GPAMP_OUT_INT"] CFG_PSEL_GPAMP_OUT_INT = 7 , # [doc = "8: VSS"] CFG_PSEL_VSS = 8 , } impl From < CFG_PSEL_A > for u8 { # [inline (always)] fn from (variant : CFG_PSEL_A) -> Self { variant as _ } } impl crate :: FieldSpec for CFG_PSEL_A { type Ux = u8 ; } impl CFG_PSEL_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < CFG_PSEL_A > { match self . bits { 0 => Some (CFG_PSEL_A :: CFG_PSEL_NC) , 1 => Some (CFG_PSEL_A :: CFG_PSEL_EXTPIN0) , 2 => Some (CFG_PSEL_A :: CFG_PSEL_EXTPIN1) , 3 => Some (CFG_PSEL_A :: CFG_PSEL_DAC12OUT) , 4 => Some (CFG_PSEL_A :: CFG_PSEL_DAC8OUT) , 5 => Some (CFG_PSEL_A :: CFG_PSEL_VREF) , 6 => Some (CFG_PSEL_A :: CFG_PSEL_OANM1RTOP) , 7 => Some (CFG_PSEL_A :: CFG_PSEL_GPAMP_OUT_INT) , 8 => Some (CFG_PSEL_A :: CFG_PSEL_VSS) , _ => None , } } # [doc = "NC"] # [inline (always)] pub fn is_cfg_psel_nc (& self) -> bool { * self == CFG_PSEL_A :: CFG_PSEL_NC } # [doc = "EXTPIN0"] # [inline (always)] pub fn is_cfg_psel_extpin0 (& self) -> bool { * self == CFG_PSEL_A :: CFG_PSEL_EXTPIN0 } # [doc = "EXTPIN1"] # [inline (always)] pub fn is_cfg_psel_extpin1 (& self) -> bool { * self == CFG_PSEL_A :: CFG_PSEL_EXTPIN1 } # [doc = "DAC12OUT"] # [inline (always)] pub fn is_cfg_psel_dac12out (& self) -> bool { * self == CFG_PSEL_A :: CFG_PSEL_DAC12OUT } # [doc = "DAC8OUT"] # [inline (always)] pub fn is_cfg_psel_dac8out (& self) -> bool { * self == CFG_PSEL_A :: CFG_PSEL_DAC8OUT } # [doc = "VREF"] # [inline (always)] pub fn is_cfg_psel_vref (& self) -> bool { * self == CFG_PSEL_A :: CFG_PSEL_VREF } # [doc = "OANM1RTOP"] # [inline (always)] pub fn is_cfg_psel_oanm1rtop (& self) -> bool { * self == CFG_PSEL_A :: CFG_PSEL_OANM1RTOP } # [doc = "GPAMP_OUT_INT"] # [inline (always)] pub fn is_cfg_psel_gpamp_out_int (& self) -> bool { * self == CFG_PSEL_A :: CFG_PSEL_GPAMP_OUT_INT } # [doc = "VSS"] # [inline (always)] pub fn is_cfg_psel_vss (& self) -> bool { * self == CFG_PSEL_A :: CFG_PSEL_VSS } } # [doc = "Field `CFG_PSEL` writer - Positive OA input selection. Please refer to the device specific datasheet for exact channels available."] pub type CFG_PSEL_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 4 , O , CFG_PSEL_A > ; impl < 'a , REG , const O : u8 > CFG_PSEL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "NC"] # [inline (always)] pub fn cfg_psel_nc (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_PSEL_A :: CFG_PSEL_NC) } # [doc = "EXTPIN0"] # [inline (always)] pub fn cfg_psel_extpin0 (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_PSEL_A :: CFG_PSEL_EXTPIN0) } # [doc = "EXTPIN1"] # [inline (always)] pub fn cfg_psel_extpin1 (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_PSEL_A :: CFG_PSEL_EXTPIN1) } # [doc = "DAC12OUT"] # [inline (always)] pub fn cfg_psel_dac12out (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_PSEL_A :: CFG_PSEL_DAC12OUT) } # [doc = "DAC8OUT"] # [inline (always)] pub fn cfg_psel_dac8out (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_PSEL_A :: CFG_PSEL_DAC8OUT) } # [doc = "VREF"] # [inline (always)] pub fn cfg_psel_vref (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_PSEL_A :: CFG_PSEL_VREF) } # [doc = "OANM1RTOP"] # [inline (always)] pub fn cfg_psel_oanm1rtop (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_PSEL_A :: CFG_PSEL_OANM1RTOP) } # [doc = "GPAMP_OUT_INT"] # [inline (always)] pub fn cfg_psel_gpamp_out_int (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_PSEL_A :: CFG_PSEL_GPAMP_OUT_INT) } # [doc = "VSS"] # [inline (always)] pub fn cfg_psel_vss (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_PSEL_A :: CFG_PSEL_VSS) } } # [doc = "Field `CFG_NSEL` reader - Negative OA input selection. Please refer to the device specific datasheet for exact channels available."] pub type CFG_NSEL_R = crate :: FieldReader < CFG_NSEL_A > ; # [doc = "Negative OA input selection. Please refer to the device specific datasheet for exact channels available.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum CFG_NSEL_A { # [doc = "0: NC"] CFG_NSEL_NC = 0 , # [doc = "1: EXTPIN0"] CFG_NSEL_EXTPIN0 = 1 , # [doc = "2: EXTPIN1"] CFG_NSEL_EXTPIN1 = 2 , # [doc = "3: OANP1RBOT"] CFG_NSEL_OANP1RBOT = 3 , # [doc = "4: OANRTAP"] CFG_NSEL_OANRTAP = 4 , # [doc = "5: OANRTOP"] CFG_NSEL_OANRTOP = 5 , # [doc = "6: SPARE"] CFG_NSEL_SPARE = 6 , } impl From < CFG_NSEL_A > for u8 { # [inline (always)] fn from (variant : CFG_NSEL_A) -> Self { variant as _ } } impl crate :: FieldSpec for CFG_NSEL_A { type Ux = u8 ; } impl CFG_NSEL_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < CFG_NSEL_A > { match self . bits { 0 => Some (CFG_NSEL_A :: CFG_NSEL_NC) , 1 => Some (CFG_NSEL_A :: CFG_NSEL_EXTPIN0) , 2 => Some (CFG_NSEL_A :: CFG_NSEL_EXTPIN1) , 3 => Some (CFG_NSEL_A :: CFG_NSEL_OANP1RBOT) , 4 => Some (CFG_NSEL_A :: CFG_NSEL_OANRTAP) , 5 => Some (CFG_NSEL_A :: CFG_NSEL_OANRTOP) , 6 => Some (CFG_NSEL_A :: CFG_NSEL_SPARE) , _ => None , } } # [doc = "NC"] # [inline (always)] pub fn is_cfg_nsel_nc (& self) -> bool { * self == CFG_NSEL_A :: CFG_NSEL_NC } # [doc = "EXTPIN0"] # [inline (always)] pub fn is_cfg_nsel_extpin0 (& self) -> bool { * self == CFG_NSEL_A :: CFG_NSEL_EXTPIN0 } # [doc = "EXTPIN1"] # [inline (always)] pub fn is_cfg_nsel_extpin1 (& self) -> bool { * self == CFG_NSEL_A :: CFG_NSEL_EXTPIN1 } # [doc = "OANP1RBOT"] # [inline (always)] pub fn is_cfg_nsel_oanp1rbot (& self) -> bool { * self == CFG_NSEL_A :: CFG_NSEL_OANP1RBOT } # [doc = "OANRTAP"] # [inline (always)] pub fn is_cfg_nsel_oanrtap (& self) -> bool { * self == CFG_NSEL_A :: CFG_NSEL_OANRTAP } # [doc = "OANRTOP"] # [inline (always)] pub fn is_cfg_nsel_oanrtop (& self) -> bool { * self == CFG_NSEL_A :: CFG_NSEL_OANRTOP } # [doc = "SPARE"] # [inline (always)] pub fn is_cfg_nsel_spare (& self) -> bool { * self == CFG_NSEL_A :: CFG_NSEL_SPARE } } # [doc = "Field `CFG_NSEL` writer - Negative OA input selection. Please refer to the device specific datasheet for exact channels available."] pub type CFG_NSEL_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 3 , O , CFG_NSEL_A > ; impl < 'a , REG , const O : u8 > CFG_NSEL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "NC"] # [inline (always)] pub fn cfg_nsel_nc (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_NSEL_A :: CFG_NSEL_NC) } # [doc = "EXTPIN0"] # [inline (always)] pub fn cfg_nsel_extpin0 (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_NSEL_A :: CFG_NSEL_EXTPIN0) } # [doc = "EXTPIN1"] # [inline (always)] pub fn cfg_nsel_extpin1 (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_NSEL_A :: CFG_NSEL_EXTPIN1) } # [doc = "OANP1RBOT"] # [inline (always)] pub fn cfg_nsel_oanp1rbot (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_NSEL_A :: CFG_NSEL_OANP1RBOT) } # [doc = "OANRTAP"] # [inline (always)] pub fn cfg_nsel_oanrtap (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_NSEL_A :: CFG_NSEL_OANRTAP) } # [doc = "OANRTOP"] # [inline (always)] pub fn cfg_nsel_oanrtop (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_NSEL_A :: CFG_NSEL_OANRTOP) } # [doc = "SPARE"] # [inline (always)] pub fn cfg_nsel_spare (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_NSEL_A :: CFG_NSEL_SPARE) } } # [doc = "Field `CFG_MSEL` reader - MSEL Mux selection. Please refer to the device specific datasheet for exact channels available."] pub type CFG_MSEL_R = crate :: FieldReader < CFG_MSEL_A > ; # [doc = "MSEL Mux selection. Please refer to the device specific datasheet for exact channels available.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum CFG_MSEL_A { # [doc = "0: NC"] CFG_MSEL_NC = 0 , # [doc = "1: EXTNPIN1"] CFG_MSEL_EXTNPIN1 = 1 , # [doc = "2: VSS"] CFG_MSEL_VSS = 2 , # [doc = "3: DAC12OUT"] CFG_MSEL_DAC12OUT = 3 , # [doc = "4: OANM1RTOP"] CFG_MSEL_OANM1RTOP = 4 , } impl From < CFG_MSEL_A > for u8 { # [inline (always)] fn from (variant : CFG_MSEL_A) -> Self { variant as _ } } impl crate :: FieldSpec for CFG_MSEL_A { type Ux = u8 ; } impl CFG_MSEL_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < CFG_MSEL_A > { match self . bits { 0 => Some (CFG_MSEL_A :: CFG_MSEL_NC) , 1 => Some (CFG_MSEL_A :: CFG_MSEL_EXTNPIN1) , 2 => Some (CFG_MSEL_A :: CFG_MSEL_VSS) , 3 => Some (CFG_MSEL_A :: CFG_MSEL_DAC12OUT) , 4 => Some (CFG_MSEL_A :: CFG_MSEL_OANM1RTOP) , _ => None , } } # [doc = "NC"] # [inline (always)] pub fn is_cfg_msel_nc (& self) -> bool { * self == CFG_MSEL_A :: CFG_MSEL_NC } # [doc = "EXTNPIN1"] # [inline (always)] pub fn is_cfg_msel_extnpin1 (& self) -> bool { * self == CFG_MSEL_A :: CFG_MSEL_EXTNPIN1 } # [doc = "VSS"] # [inline (always)] pub fn is_cfg_msel_vss (& self) -> bool { * self == CFG_MSEL_A :: CFG_MSEL_VSS } # [doc = "DAC12OUT"] # [inline (always)] pub fn is_cfg_msel_dac12out (& self) -> bool { * self == CFG_MSEL_A :: CFG_MSEL_DAC12OUT } # [doc = "OANM1RTOP"] # [inline (always)] pub fn is_cfg_msel_oanm1rtop (& self) -> bool { * self == CFG_MSEL_A :: CFG_MSEL_OANM1RTOP } } # [doc = "Field `CFG_MSEL` writer - MSEL Mux selection. Please refer to the device specific datasheet for exact channels available."] pub type CFG_MSEL_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 3 , O , CFG_MSEL_A > ; impl < 'a , REG , const O : u8 > CFG_MSEL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "NC"] # [inline (always)] pub fn cfg_msel_nc (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_MSEL_A :: CFG_MSEL_NC) } # [doc = "EXTNPIN1"] # [inline (always)] pub fn cfg_msel_extnpin1 (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_MSEL_A :: CFG_MSEL_EXTNPIN1) } # [doc = "VSS"] # [inline (always)] pub fn cfg_msel_vss (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_MSEL_A :: CFG_MSEL_VSS) } # [doc = "DAC12OUT"] # [inline (always)] pub fn cfg_msel_dac12out (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_MSEL_A :: CFG_MSEL_DAC12OUT) } # [doc = "OANM1RTOP"] # [inline (always)] pub fn cfg_msel_oanm1rtop (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_MSEL_A :: CFG_MSEL_OANM1RTOP) } } # [doc = "Field `CFG_GAIN` reader - Gain setting. Refer to TRM for enumeration information."] pub type CFG_GAIN_R = crate :: FieldReader ; # [doc = "Field `CFG_GAIN` writer - Gain setting. Refer to TRM for enumeration information."] pub type CFG_GAIN_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 3 , O > ; impl R { # [doc = "Bits 0:1 - Chopping enable."] # [inline (always)] pub fn cfg_chop (& self) -> CFG_CHOP_R { CFG_CHOP_R :: new ((self . bits & 3) as u8) } # [doc = "Bit 2 - Enable output pin"] # [inline (always)] pub fn cfg_outpin (& self) -> CFG_OUTPIN_R { CFG_OUTPIN_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bits 3:6 - Positive OA input selection. Please refer to the device specific datasheet for exact channels available."] # [inline (always)] pub fn cfg_psel (& self) -> CFG_PSEL_R { CFG_PSEL_R :: new (((self . bits >> 3) & 0x0f) as u8) } # [doc = "Bits 7:9 - Negative OA input selection. Please refer to the device specific datasheet for exact channels available."] # [inline (always)] pub fn cfg_nsel (& self) -> CFG_NSEL_R { CFG_NSEL_R :: new (((self . bits >> 7) & 7) as u8) } # [doc = "Bits 10:12 - MSEL Mux selection. Please refer to the device specific datasheet for exact channels available."] # [inline (always)] pub fn cfg_msel (& self) -> CFG_MSEL_R { CFG_MSEL_R :: new (((self . bits >> 10) & 7) as u8) } # [doc = "Bits 13:15 - Gain setting. Refer to TRM for enumeration information."] # [inline (always)] pub fn cfg_gain (& self) -> CFG_GAIN_R { CFG_GAIN_R :: new (((self . bits >> 13) & 7) as u8) } } impl W { # [doc = "Bits 0:1 - Chopping enable."] # [inline (always)] # [must_use] pub fn cfg_chop (& mut self) -> CFG_CHOP_W < CFG_SPEC , 0 > { CFG_CHOP_W :: new (self) } # [doc = "Bit 2 - Enable output pin"] # [inline (always)] # [must_use] pub fn cfg_outpin (& mut self) -> CFG_OUTPIN_W < CFG_SPEC , 2 > { CFG_OUTPIN_W :: new (self) } # [doc = "Bits 3:6 - Positive OA input selection. Please refer to the device specific datasheet for exact channels available."] # [inline (always)] # [must_use] pub fn cfg_psel (& mut self) -> CFG_PSEL_W < CFG_SPEC , 3 > { CFG_PSEL_W :: new (self) } # [doc = "Bits 7:9 - Negative OA input selection. Please refer to the device specific datasheet for exact channels available."] # [inline (always)] # [must_use] pub fn cfg_nsel (& mut self) -> CFG_NSEL_W < CFG_SPEC , 7 > { CFG_NSEL_W :: new (self) } # [doc = "Bits 10:12 - MSEL Mux selection. Please refer to the device specific datasheet for exact channels available."] # [inline (always)] # [must_use] pub fn cfg_msel (& mut self) -> CFG_MSEL_W <'_, CFG_SPEC , 10 > { CFG_MSEL_W :: new (self) } # [doc = "Bits 13:15 - Gain setting. Refer to TRM for enumeration information."] # [inline (always)] # [must_use] pub fn cfg_gain (& mut self) -> CFG_GAIN_W < CFG_SPEC , 13 > { CFG_GAIN_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Configuration Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CFG_SPEC ; impl crate :: RegisterSpec for CFG_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`cfg::R`](R) reader structure"] impl crate :: Readable for CFG_SPEC { } # [doc = "`write(|w| ..)` method takes [`cfg::W`](W) writer structure"] impl crate :: Writable for CFG_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets CFG to value 0"] impl crate :: Resettable for CFG_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/i2c0/int_event0_iset.rs:1:38593 [INFO] [stdout] | [INFO] [stdout] 1 | ...t_mrxfifotrg (& mut self) -> INT_EVENT0_ISET_MRXFIFOTRG_W < INT_EVENT0_ISET_SPEC , 2 > { INT_EVENT0_ISET_MRXFIFOTRG_W :: new (self) } ... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `INT_EVENT0_ISET` writer"] pub type W = crate :: W < INT_EVENT0_ISET_SPEC > ; # [doc = "Master Receive Data Interrupt Signals that a byte has been received\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_MRXDONE_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_MRXDONE_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_MRXDONE_SET = 1 , } impl From < INT_EVENT0_ISET_MRXDONE_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_MRXDONE_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_MRXDONE` writer - Master Receive Data Interrupt Signals that a byte has been received"] pub type INT_EVENT0_ISET_MRXDONE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_MRXDONE_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_MRXDONE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_mrxdone_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MRXDONE_AW :: INT_EVENT0_ISET_MRXDONE_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_mrxdone_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MRXDONE_AW :: INT_EVENT0_ISET_MRXDONE_SET) } } # [doc = "Master Transmit Transaction completed Interrupt\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_MTXDONE_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_MTXDONE_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_MTXDONE_SET = 1 , } impl From < INT_EVENT0_ISET_MTXDONE_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_MTXDONE_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_MTXDONE` writer - Master Transmit Transaction completed Interrupt"] pub type INT_EVENT0_ISET_MTXDONE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_MTXDONE_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_MTXDONE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_mtxdone_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MTXDONE_AW :: INT_EVENT0_ISET_MTXDONE_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_mtxdone_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MTXDONE_AW :: INT_EVENT0_ISET_MTXDONE_SET) } } # [doc = "Master Receive FIFO Trigger Trigger when RX FIFO contains &gt;= defined bytes\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_MRXFIFOTRG_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_MRXFIFOTRG_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_MRXFIFOTRG_SET = 1 , } impl From < INT_EVENT0_ISET_MRXFIFOTRG_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_MRXFIFOTRG_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_MRXFIFOTRG` writer - Master Receive FIFO Trigger Trigger when RX FIFO contains &gt;= defined bytes"] pub type INT_EVENT0_ISET_MRXFIFOTRG_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_MRXFIFOTRG_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_MRXFIFOTRG_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_mrxfifotrg_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MRXFIFOTRG_AW :: INT_EVENT0_ISET_MRXFIFOTRG_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_mrxfifotrg_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MRXFIFOTRG_AW :: INT_EVENT0_ISET_MRXFIFOTRG_SET) } } # [doc = "Master Transmit FIFO Trigger Trigger when Transmit FIFO contains &lt;= defined bytes\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_MTXFIFOTRG_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_MTXFIFOTRG_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_MTXFIFOTRG_SET = 1 , } impl From < INT_EVENT0_ISET_MTXFIFOTRG_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_MTXFIFOTRG_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_MTXFIFOTRG` writer - Master Transmit FIFO Trigger Trigger when Transmit FIFO contains &lt;= defined bytes"] pub type INT_EVENT0_ISET_MTXFIFOTRG_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_MTXFIFOTRG_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_MTXFIFOTRG_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_mtxfifotrg_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MTXFIFOTRG_AW :: INT_EVENT0_ISET_MTXFIFOTRG_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_mtxfifotrg_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MTXFIFOTRG_AW :: INT_EVENT0_ISET_MTXFIFOTRG_SET) } } # [doc = "RXFIFO full event.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_MRXFIFOFULL_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_MRXFIFOFULL_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_MRXFIFOFULL_SET = 1 , } impl From < INT_EVENT0_ISET_MRXFIFOFULL_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_MRXFIFOFULL_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_MRXFIFOFULL` writer - RXFIFO full event."] pub type INT_EVENT0_ISET_MRXFIFOFULL_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_MRXFIFOFULL_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_MRXFIFOFULL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_mrxfifofull_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MRXFIFOFULL_AW :: INT_EVENT0_ISET_MRXFIFOFULL_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_mrxfifofull_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MRXFIFOFULL_AW :: INT_EVENT0_ISET_MRXFIFOFULL_SET) } } # [doc = "Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_MTXEMPTY_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_MTXEMPTY_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_MTXEMPTY_SET = 1 , } impl From < INT_EVENT0_ISET_MTXEMPTY_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_MTXEMPTY_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_MTXEMPTY` writer - Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode."] pub type INT_EVENT0_ISET_MTXEMPTY_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_MTXEMPTY_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_MTXEMPTY_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_mtxempty_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MTXEMPTY_AW :: INT_EVENT0_ISET_MTXEMPTY_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_mtxempty_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MTXEMPTY_AW :: INT_EVENT0_ISET_MTXEMPTY_SET) } } # [doc = "Address/Data NACK Interrupt\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_MNACK_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_MNACK_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_MNACK_SET = 1 , } impl From < INT_EVENT0_ISET_MNACK_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_MNACK_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_MNACK` writer - Address/Data NACK Interrupt"] pub type INT_EVENT0_ISET_MNACK_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_MNACK_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_MNACK_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_mnack_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MNACK_AW :: INT_EVENT0_ISET_MNACK_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_mnack_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MNACK_AW :: INT_EVENT0_ISET_MNACK_SET) } } # [doc = "START Detection Interrupt\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_MSTART_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_MSTART_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_MSTART_SET = 1 , } impl From < INT_EVENT0_ISET_MSTART_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_MSTART_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_MSTART` writer - START Detection Interrupt"] pub type INT_EVENT0_ISET_MSTART_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_MSTART_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_MSTART_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_mstart_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MSTART_AW :: INT_EVENT0_ISET_MSTART_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_mstart_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MSTART_AW :: INT_EVENT0_ISET_MSTART_SET) } } # [doc = "STOP Detection Interrupt\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_MSTOP_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_MSTOP_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_MSTOP_SET = 1 , } impl From < INT_EVENT0_ISET_MSTOP_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_MSTOP_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_MSTOP` writer - STOP Detection Interrupt"] pub type INT_EVENT0_ISET_MSTOP_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_MSTOP_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_MSTOP_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_mstop_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MSTOP_AW :: INT_EVENT0_ISET_MSTOP_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_mstop_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MSTOP_AW :: INT_EVENT0_ISET_MSTOP_SET) } } # [doc = "Arbitration Lost Interrupt\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_MARBLOST_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_MARBLOST_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_MARBLOST_SET = 1 , } impl From < INT_EVENT0_ISET_MARBLOST_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_MARBLOST_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_MARBLOST` writer - Arbitration Lost Interrupt"] pub type INT_EVENT0_ISET_MARBLOST_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_MARBLOST_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_MARBLOST_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_marblost_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MARBLOST_AW :: INT_EVENT0_ISET_MARBLOST_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_marblost_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MARBLOST_AW :: INT_EVENT0_ISET_MARBLOST_SET) } } # [doc = "DMA Done 1 on Event Channel 2\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_MDMA_DONE1_2_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_MDMA_DONE1_2_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_MDMA_DONE1_2_SET = 1 , } impl From < INT_EVENT0_ISET_MDMA_DONE1_2_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_MDMA_DONE1_2_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_MDMA_DONE1_2` writer - DMA Done 1 on Event Channel 2"] pub type INT_EVENT0_ISET_MDMA_DONE1_2_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_MDMA_DONE1_2_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_MDMA_DONE1_2_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_mdma_done1_2_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MDMA_DONE1_2_AW :: INT_EVENT0_ISET_MDMA_DONE1_2_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_mdma_done1_2_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MDMA_DONE1_2_AW :: INT_EVENT0_ISET_MDMA_DONE1_2_SET) } } # [doc = "DMA Done 1 on Event Channel 3\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_MDMA_DONE1_3_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_MDMA_DONE1_3_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_MDMA_DONE1_3_SET = 1 , } impl From < INT_EVENT0_ISET_MDMA_DONE1_3_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_MDMA_DONE1_3_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_MDMA_DONE1_3` writer - DMA Done 1 on Event Channel 3"] pub type INT_EVENT0_ISET_MDMA_DONE1_3_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_MDMA_DONE1_3_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_MDMA_DONE1_3_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_mdma_done1_3_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MDMA_DONE1_3_AW :: INT_EVENT0_ISET_MDMA_DONE1_3_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_mdma_done1_3_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MDMA_DONE1_3_AW :: INT_EVENT0_ISET_MDMA_DONE1_3_SET) } } # [doc = "Master RX Pec Error Interrupt\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_MPEC_RX_ERR_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_MPEC_RX_ERR_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_MPEC_RX_ERR_SET = 1 , } impl From < INT_EVENT0_ISET_MPEC_RX_ERR_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_MPEC_RX_ERR_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_MPEC_RX_ERR` writer - Master RX Pec Error Interrupt"] pub type INT_EVENT0_ISET_MPEC_RX_ERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_MPEC_RX_ERR_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_MPEC_RX_ERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_mpec_rx_err_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MPEC_RX_ERR_AW :: INT_EVENT0_ISET_MPEC_RX_ERR_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_mpec_rx_err_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MPEC_RX_ERR_AW :: INT_EVENT0_ISET_MPEC_RX_ERR_SET) } } # [doc = "Timeout A interrupt\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_TIMEOUTA_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_TIMEOUTA_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_TIMEOUTA_SET = 1 , } impl From < INT_EVENT0_ISET_TIMEOUTA_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_TIMEOUTA_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_TIMEOUTA` writer - Timeout A interrupt"] pub type INT_EVENT0_ISET_TIMEOUTA_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_TIMEOUTA_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_TIMEOUTA_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_timeouta_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_TIMEOUTA_AW :: INT_EVENT0_ISET_TIMEOUTA_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_timeouta_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_TIMEOUTA_AW :: INT_EVENT0_ISET_TIMEOUTA_SET) } } # [doc = "Timeout B Interrupt\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_TIMEOUTB_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_TIMEOUTB_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_TIMEOUTB_SET = 1 , } impl From < INT_EVENT0_ISET_TIMEOUTB_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_TIMEOUTB_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_TIMEOUTB` writer - Timeout B Interrupt"] pub type INT_EVENT0_ISET_TIMEOUTB_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_TIMEOUTB_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_TIMEOUTB_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_timeoutb_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_TIMEOUTB_AW :: INT_EVENT0_ISET_TIMEOUTB_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_timeoutb_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_TIMEOUTB_AW :: INT_EVENT0_ISET_TIMEOUTB_SET) } } # [doc = "Slave Receive Data Interrupt Signals that a byte has been received\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_SRXDONE_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_SRXDONE_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_SRXDONE_SET = 1 , } impl From < INT_EVENT0_ISET_SRXDONE_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_SRXDONE_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_SRXDONE` writer - Slave Receive Data Interrupt Signals that a byte has been received"] pub type INT_EVENT0_ISET_SRXDONE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_SRXDONE_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_SRXDONE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_srxdone_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_SRXDONE_AW :: INT_EVENT0_ISET_SRXDONE_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_srxdone_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_SRXDONE_AW :: INT_EVENT0_ISET_SRXDONE_SET) } } # [doc = "Slave Transmit Transaction completed Interrupt\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_STXDONE_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_STXDONE_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_STXDONE_SET = 1 , } impl From < INT_EVENT0_ISET_STXDONE_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_STXDONE_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_STXDONE` writer - Slave Transmit Transaction completed Interrupt"] pub type INT_EVENT0_ISET_STXDONE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_STXDONE_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_STXDONE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_stxdone_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_STXDONE_AW :: INT_EVENT0_ISET_STXDONE_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_stxdone_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_STXDONE_AW :: INT_EVENT0_ISET_STXDONE_SET) } } # [doc = "Slave Receive FIFO Trigger\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_SRXFIFOTRG_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_SRXFIFOTRG_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_SRXFIFOTRG_SET = 1 , } impl From < INT_EVENT0_ISET_SRXFIFOTRG_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_SRXFIFOTRG_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_SRXFIFOTRG` writer - Slave Receive FIFO Trigger"] pub type INT_EVENT0_ISET_SRXFIFOTRG_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_SRXFIFOTRG_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_SRXFIFOTRG_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_srxfifotrg_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_SRXFIFOTRG_AW :: INT_EVENT0_ISET_SRXFIFOTRG_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_srxfifotrg_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_SRXFIFOTRG_AW :: INT_EVENT0_ISET_SRXFIFOTRG_SET) } } # [doc = "Slave Transmit FIFO Trigger\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_STXFIFOTRG_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_STXFIFOTRG_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_STXFIFOTRG_SET = 1 , } impl From < INT_EVENT0_ISET_STXFIFOTRG_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_STXFIFOTRG_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_STXFIFOTRG` writer - Slave Transmit FIFO Trigger"] pub type INT_EVENT0_ISET_STXFIFOTRG_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_STXFIFOTRG_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_STXFIFOTRG_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_stxfifotrg_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_STXFIFOTRG_AW :: INT_EVENT0_ISET_STXFIFOTRG_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_stxfifotrg_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_STXFIFOTRG_AW :: INT_EVENT0_ISET_STXFIFOTRG_SET) } } # [doc = "RXFIFO full event. This interrupt is set if an RX FIFO is full.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_SRXFIFOFULL_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_SRXFIFOFULL_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_SRXFIFOFULL_SET = 1 , } impl From < INT_EVENT0_ISET_SRXFIFOFULL_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_SRXFIFOFULL_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_SRXFIFOFULL` writer - RXFIFO full event. This interrupt is set if an RX FIFO is full."] pub type INT_EVENT0_ISET_SRXFIFOFULL_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_SRXFIFOFULL_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_SRXFIFOFULL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_srxfifofull_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_SRXFIFOFULL_AW :: INT_EVENT0_ISET_SRXFIFOFULL_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_srxfifofull_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_SRXFIFOFULL_AW :: INT_EVENT0_ISET_SRXFIFOFULL_SET) } } # [doc = "Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_STXEMPTY_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_STXEMPTY_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_STXEMPTY_SET = 1 , } impl From < INT_EVENT0_ISET_STXEMPTY_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_STXEMPTY_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_STXEMPTY` writer - Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode."] pub type INT_EVENT0_ISET_STXEMPTY_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_STXEMPTY_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_STXEMPTY_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_stxempty_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_STXEMPTY_AW :: INT_EVENT0_ISET_STXEMPTY_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_stxempty_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_STXEMPTY_AW :: INT_EVENT0_ISET_STXEMPTY_SET) } } # [doc = "Start Condition Interrupt\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_SSTART_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_SSTART_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_SSTART_SET = 1 , } impl From < INT_EVENT0_ISET_SSTART_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_SSTART_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_SSTART` writer - Start Condition Interrupt"] pub type INT_EVENT0_ISET_SSTART_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_SSTART_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_SSTART_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_sstart_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_SSTART_AW :: INT_EVENT0_ISET_SSTART_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_sstart_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_SSTART_AW :: INT_EVENT0_ISET_SSTART_SET) } } # [doc = "Stop Condition Interrupt\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_SSTOP_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_SSTOP_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_SSTOP_SET = 1 , } impl From < INT_EVENT0_ISET_SSTOP_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_SSTOP_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_SSTOP` writer - Stop Condition Interrupt"] pub type INT_EVENT0_ISET_SSTOP_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_SSTOP_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_SSTOP_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_sstop_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_SSTOP_AW :: INT_EVENT0_ISET_SSTOP_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_sstop_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_SSTOP_AW :: INT_EVENT0_ISET_SSTOP_SET) } } # [doc = "General Call Interrupt\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_SGENCALL_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_SGENCALL_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_SGENCALL_SET = 1 , } impl From < INT_EVENT0_ISET_SGENCALL_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_SGENCALL_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_SGENCALL` writer - General Call Interrupt"] pub type INT_EVENT0_ISET_SGENCALL_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_SGENCALL_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_SGENCALL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_sgencall_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_SGENCALL_AW :: INT_EVENT0_ISET_SGENCALL_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_sgencall_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_SGENCALL_AW :: INT_EVENT0_ISET_SGENCALL_SET) } } # [doc = "DMA Done 1 on Event Channel 2\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_SDMA_DONE1_2_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_SDMA_DONE1_2_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_SDMA_DONE1_2_SET = 1 , } impl From < INT_EVENT0_ISET_SDMA_DONE1_2_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_SDMA_DONE1_2_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_SDMA_DONE1_2` writer - DMA Done 1 on Event Channel 2"] pub type INT_EVENT0_ISET_SDMA_DONE1_2_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_SDMA_DONE1_2_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_SDMA_DONE1_2_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_sdma_done1_2_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_SDMA_DONE1_2_AW :: INT_EVENT0_ISET_SDMA_DONE1_2_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_sdma_done1_2_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_SDMA_DONE1_2_AW :: INT_EVENT0_ISET_SDMA_DONE1_2_SET) } } # [doc = "DMA Done 1 on Event Channel 3\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_SDMA_DONE1_3_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_SDMA_DONE1_3_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_SDMA_DONE1_3_SET = 1 , } impl From < INT_EVENT0_ISET_SDMA_DONE1_3_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_SDMA_DONE1_3_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_SDMA_DONE1_3` writer - DMA Done 1 on Event Channel 3"] pub type INT_EVENT0_ISET_SDMA_DONE1_3_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_SDMA_DONE1_3_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_SDMA_DONE1_3_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_sdma_done1_3_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_SDMA_DONE1_3_AW :: INT_EVENT0_ISET_SDMA_DONE1_3_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_sdma_done1_3_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_SDMA_DONE1_3_AW :: INT_EVENT0_ISET_SDMA_DONE1_3_SET) } } # [doc = "Slave RX Pec Error Interrupt\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_SPEC_RX_ERR_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_SPEC_RX_ERR_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_SPEC_RX_ERR_SET = 1 , } impl From < INT_EVENT0_ISET_SPEC_RX_ERR_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_SPEC_RX_ERR_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_SPEC_RX_ERR` writer - Slave RX Pec Error Interrupt"] pub type INT_EVENT0_ISET_SPEC_RX_ERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_SPEC_RX_ERR_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_SPEC_RX_ERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_spec_rx_err_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_SPEC_RX_ERR_AW :: INT_EVENT0_ISET_SPEC_RX_ERR_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_spec_rx_err_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_SPEC_RX_ERR_AW :: INT_EVENT0_ISET_SPEC_RX_ERR_SET) } } # [doc = "Slave TX FIFO underflow\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_STX_UNFL_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_STX_UNFL_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_STX_UNFL_SET = 1 , } impl From < INT_EVENT0_ISET_STX_UNFL_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_STX_UNFL_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_STX_UNFL` writer - Slave TX FIFO underflow"] pub type INT_EVENT0_ISET_STX_UNFL_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_STX_UNFL_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_STX_UNFL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_stx_unfl_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_STX_UNFL_AW :: INT_EVENT0_ISET_STX_UNFL_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_stx_unfl_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_STX_UNFL_AW :: INT_EVENT0_ISET_STX_UNFL_SET) } } # [doc = "Slave RX FIFO overflow\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_SRX_OVFL_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_SRX_OVFL_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_SRX_OVFL_SET = 1 , } impl From < INT_EVENT0_ISET_SRX_OVFL_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_SRX_OVFL_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_SRX_OVFL` writer - Slave RX FIFO overflow"] pub type INT_EVENT0_ISET_SRX_OVFL_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_SRX_OVFL_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_SRX_OVFL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_srx_ovfl_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_SRX_OVFL_AW :: INT_EVENT0_ISET_SRX_OVFL_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_srx_ovfl_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_SRX_OVFL_AW :: INT_EVENT0_ISET_SRX_OVFL_SET) } } # [doc = "Slave Arbitration Lost\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_SARBLOST_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_SARBLOST_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_SARBLOST_SET = 1 , } impl From < INT_EVENT0_ISET_SARBLOST_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_SARBLOST_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_SARBLOST` writer - Slave Arbitration Lost"] pub type INT_EVENT0_ISET_SARBLOST_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_SARBLOST_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_SARBLOST_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_sarblost_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_SARBLOST_AW :: INT_EVENT0_ISET_SARBLOST_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_sarblost_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_SARBLOST_AW :: INT_EVENT0_ISET_SARBLOST_SET) } } # [doc = "Interrupt overflow\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_INTR_OVFL_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_INTR_OVFL_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_INTR_OVFL_SET = 1 , } impl From < INT_EVENT0_ISET_INTR_OVFL_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_INTR_OVFL_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_INTR_OVFL` writer - Interrupt overflow"] pub type INT_EVENT0_ISET_INTR_OVFL_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_INTR_OVFL_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_INTR_OVFL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_intr_ovfl_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_INTR_OVFL_AW :: INT_EVENT0_ISET_INTR_OVFL_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_intr_ovfl_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_INTR_OVFL_AW :: INT_EVENT0_ISET_INTR_OVFL_SET) } } impl W { # [doc = "Bit 0 - Master Receive Data Interrupt Signals that a byte has been received"] # [inline (always)] # [must_use] pub fn int_event0_iset_mrxdone (& mut self) -> INT_EVENT0_ISET_MRXDONE_W < INT_EVENT0_ISET_SPEC , 0 > { INT_EVENT0_ISET_MRXDONE_W :: new (self) } # [doc = "Bit 1 - Master Transmit Transaction completed Interrupt"] # [inline (always)] # [must_use] pub fn int_event0_iset_mtxdone (& mut self) -> INT_EVENT0_ISET_MTXDONE_W < INT_EVENT0_ISET_SPEC , 1 > { INT_EVENT0_ISET_MTXDONE_W :: new (self) } # [doc = "Bit 2 - Master Receive FIFO Trigger Trigger when RX FIFO contains &gt;= defined bytes"] # [inline (always)] # [must_use] pub fn int_event0_iset_mrxfifotrg (& mut self) -> INT_EVENT0_ISET_MRXFIFOTRG_W <'_, INT_EVENT0_ISET_SPEC , 2 > { INT_EVENT0_ISET_MRXFIFOTRG_W :: new (self) } # [doc = "Bit 3 - Master Transmit FIFO Trigger Trigger when Transmit FIFO contains &lt;= defined bytes"] # [inline (always)] # [must_use] pub fn int_event0_iset_mtxfifotrg (& mut self) -> INT_EVENT0_ISET_MTXFIFOTRG_W < INT_EVENT0_ISET_SPEC , 3 > { INT_EVENT0_ISET_MTXFIFOTRG_W :: new (self) } # [doc = "Bit 4 - RXFIFO full event."] # [inline (always)] # [must_use] pub fn int_event0_iset_mrxfifofull (& mut self) -> INT_EVENT0_ISET_MRXFIFOFULL_W < INT_EVENT0_ISET_SPEC , 4 > { INT_EVENT0_ISET_MRXFIFOFULL_W :: new (self) } # [doc = "Bit 5 - Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode."] # [inline (always)] # [must_use] pub fn int_event0_iset_mtxempty (& mut self) -> INT_EVENT0_ISET_MTXEMPTY_W < INT_EVENT0_ISET_SPEC , 5 > { INT_EVENT0_ISET_MTXEMPTY_W :: new (self) } # [doc = "Bit 7 - Address/Data NACK Interrupt"] # [inline (always)] # [must_use] pub fn int_event0_iset_mnack (& mut self) -> INT_EVENT0_ISET_MNACK_W < INT_EVENT0_ISET_SPEC , 7 > { INT_EVENT0_ISET_MNACK_W :: new (self) } # [doc = "Bit 8 - START Detection Interrupt"] # [inline (always)] # [must_use] pub fn int_event0_iset_mstart (& mut self) -> INT_EVENT0_ISET_MSTART_W < INT_EVENT0_ISET_SPEC , 8 > { INT_EVENT0_ISET_MSTART_W :: new (self) } # [doc = "Bit 9 - STOP Detection Interrupt"] # [inline (always)] # [must_use] pub fn int_event0_iset_mstop (& mut self) -> INT_EVENT0_ISET_MSTOP_W < INT_EVENT0_ISET_SPEC , 9 > { INT_EVENT0_ISET_MSTOP_W :: new (self) } # [doc = "Bit 10 - Arbitration Lost Interrupt"] # [inline (always)] # [must_use] pub fn int_event0_iset_marblost (& mut self) -> INT_EVENT0_ISET_MARBLOST_W < INT_EVENT0_ISET_SPEC , 10 > { INT_EVENT0_ISET_MARBLOST_W :: new (self) } # [doc = "Bit 11 - DMA Done 1 on Event Channel 2"] # [inline (always)] # [must_use] pub fn int_event0_iset_mdma_done1_2 (& mut self) -> INT_EVENT0_ISET_MDMA_DONE1_2_W < INT_EVENT0_ISET_SPEC , 11 > { INT_EVENT0_ISET_MDMA_DONE1_2_W :: new (self) } # [doc = "Bit 12 - DMA Done 1 on Event Channel 3"] # [inline (always)] # [must_use] pub fn int_event0_iset_mdma_done1_3 (& mut self) -> INT_EVENT0_ISET_MDMA_DONE1_3_W < INT_EVENT0_ISET_SPEC , 12 > { INT_EVENT0_ISET_MDMA_DONE1_3_W :: new (self) } # [doc = "Bit 13 - Master RX Pec Error Interrupt"] # [inline (always)] # [must_use] pub fn int_event0_iset_mpec_rx_err (& mut self) -> INT_EVENT0_ISET_MPEC_RX_ERR_W < INT_EVENT0_ISET_SPEC , 13 > { INT_EVENT0_ISET_MPEC_RX_ERR_W :: new (self) } # [doc = "Bit 14 - Timeout A interrupt"] # [inline (always)] # [must_use] pub fn int_event0_iset_timeouta (& mut self) -> INT_EVENT0_ISET_TIMEOUTA_W < INT_EVENT0_ISET_SPEC , 14 > { INT_EVENT0_ISET_TIMEOUTA_W :: new (self) } # [doc = "Bit 15 - Timeout B Interrupt"] # [inline (always)] # [must_use] pub fn int_event0_iset_timeoutb (& mut self) -> INT_EVENT0_ISET_TIMEOUTB_W < INT_EVENT0_ISET_SPEC , 15 > { INT_EVENT0_ISET_TIMEOUTB_W :: new (self) } # [doc = "Bit 16 - Slave Receive Data Interrupt Signals that a byte has been received"] # [inline (always)] # [must_use] pub fn int_event0_iset_srxdone (& mut self) -> INT_EVENT0_ISET_SRXDONE_W < INT_EVENT0_ISET_SPEC , 16 > { INT_EVENT0_ISET_SRXDONE_W :: new (self) } # [doc = "Bit 17 - Slave Transmit Transaction completed Interrupt"] # [inline (always)] # [must_use] pub fn int_event0_iset_stxdone (& mut self) -> INT_EVENT0_ISET_STXDONE_W < INT_EVENT0_ISET_SPEC , 17 > { INT_EVENT0_ISET_STXDONE_W :: new (self) } # [doc = "Bit 18 - Slave Receive FIFO Trigger"] # [inline (always)] # [must_use] pub fn int_event0_iset_srxfifotrg (& mut self) -> INT_EVENT0_ISET_SRXFIFOTRG_W < INT_EVENT0_ISET_SPEC , 18 > { INT_EVENT0_ISET_SRXFIFOTRG_W :: new (self) } # [doc = "Bit 19 - Slave Transmit FIFO Trigger"] # [inline (always)] # [must_use] pub fn int_event0_iset_stxfifotrg (& mut self) -> INT_EVENT0_ISET_STXFIFOTRG_W < INT_EVENT0_ISET_SPEC , 19 > { INT_EVENT0_ISET_STXFIFOTRG_W :: new (self) } # [doc = "Bit 20 - RXFIFO full event. This interrupt is set if an RX FIFO is full."] # [inline (always)] # [must_use] pub fn int_event0_iset_srxfifofull (& mut self) -> INT_EVENT0_ISET_SRXFIFOFULL_W < INT_EVENT0_ISET_SPEC , 20 > { INT_EVENT0_ISET_SRXFIFOFULL_W :: new (self) } # [doc = "Bit 21 - Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode."] # [inline (always)] # [must_use] pub fn int_event0_iset_stxempty (& mut self) -> INT_EVENT0_ISET_STXEMPTY_W < INT_EVENT0_ISET_SPEC , 21 > { INT_EVENT0_ISET_STXEMPTY_W :: new (self) } # [doc = "Bit 22 - Start Condition Interrupt"] # [inline (always)] # [must_use] pub fn int_event0_iset_sstart (& mut self) -> INT_EVENT0_ISET_SSTART_W < INT_EVENT0_ISET_SPEC , 22 > { INT_EVENT0_ISET_SSTART_W :: new (self) } # [doc = "Bit 23 - Stop Condition Interrupt"] # [inline (always)] # [must_use] pub fn int_event0_iset_sstop (& mut self) -> INT_EVENT0_ISET_SSTOP_W < INT_EVENT0_ISET_SPEC , 23 > { INT_EVENT0_ISET_SSTOP_W :: new (self) } # [doc = "Bit 24 - General Call Interrupt"] # [inline (always)] # [must_use] pub fn int_event0_iset_sgencall (& mut self) -> INT_EVENT0_ISET_SGENCALL_W < INT_EVENT0_ISET_SPEC , 24 > { INT_EVENT0_ISET_SGENCALL_W :: new (self) } # [doc = "Bit 25 - DMA Done 1 on Event Channel 2"] # [inline (always)] # [must_use] pub fn int_event0_iset_sdma_done1_2 (& mut self) -> INT_EVENT0_ISET_SDMA_DONE1_2_W < INT_EVENT0_ISET_SPEC , 25 > { INT_EVENT0_ISET_SDMA_DONE1_2_W :: new (self) } # [doc = "Bit 26 - DMA Done 1 on Event Channel 3"] # [inline (always)] # [must_use] pub fn int_event0_iset_sdma_done1_3 (& mut self) -> INT_EVENT0_ISET_SDMA_DONE1_3_W < INT_EVENT0_ISET_SPEC , 26 > { INT_EVENT0_ISET_SDMA_DONE1_3_W :: new (self) } # [doc = "Bit 27 - Slave RX Pec Error Interrupt"] # [inline (always)] # [must_use] pub fn int_event0_iset_spec_rx_err (& mut self) -> INT_EVENT0_ISET_SPEC_RX_ERR_W < INT_EVENT0_ISET_SPEC , 27 > { INT_EVENT0_ISET_SPEC_RX_ERR_W :: new (self) } # [doc = "Bit 28 - Slave TX FIFO underflow"] # [inline (always)] # [must_use] pub fn int_event0_iset_stx_unfl (& mut self) -> INT_EVENT0_ISET_STX_UNFL_W < INT_EVENT0_ISET_SPEC , 28 > { INT_EVENT0_ISET_STX_UNFL_W :: new (self) } # [doc = "Bit 29 - Slave RX FIFO overflow"] # [inline (always)] # [must_use] pub fn int_event0_iset_srx_ovfl (& mut self) -> INT_EVENT0_ISET_SRX_OVFL_W < INT_EVENT0_ISET_SPEC , 29 > { INT_EVENT0_ISET_SRX_OVFL_W :: new (self) } # [doc = "Bit 30 - Slave Arbitration Lost"] # [inline (always)] # [must_use] pub fn int_event0_iset_sarblost (& mut self) -> INT_EVENT0_ISET_SARBLOST_W < INT_EVENT0_ISET_SPEC , 30 > { INT_EVENT0_ISET_SARBLOST_W :: new (self) } # [doc = "Bit 31 - Interrupt overflow"] # [inline (always)] # [must_use] pub fn int_event0_iset_intr_ovfl (& mut self) -> INT_EVENT0_ISET_INTR_OVFL_W < INT_EVENT0_ISET_SPEC , 31 > { INT_EVENT0_ISET_INTR_OVFL_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Interrupt set\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_event0_iset::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct INT_EVENT0_ISET_SPEC ; impl crate :: RegisterSpec for INT_EVENT0_ISET_SPEC { type Ux = u32 ; } # [doc = "`write(|w| ..)` method takes [`int_event0_iset::W`](W) writer structure"] impl crate :: Writable for INT_EVENT0_ISET_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets INT_EVENT0_ISET to value 0"] impl crate :: Resettable for INT_EVENT0_ISET_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/i2c1/int_event1_iclr.rs:1:5877 [INFO] [stdout] | [INFO] [stdout] 1 | ...r_srxfifotrg (& mut self) -> INT_EVENT1_ICLR_SRXFIFOTRG_W < INT_EVENT1_ICLR_SPEC , 2 > { INT_EVENT1_ICLR_SRXFIFOTRG_W :: new (self) } ... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `INT_EVENT1_ICLR` writer"] pub type W = crate :: W < INT_EVENT1_ICLR_SPEC > ; # [doc = "Master Receive FIFO Trigger Trigger when RX FIFO contains &gt;= defined bytes\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT1_ICLR_MRXFIFOTRG_AW { # [doc = "0: NO_EFFECT"] INT_EVENT1_ICLR_MRXFIFOTRG_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT1_ICLR_MRXFIFOTRG_CLR = 1 , } impl From < INT_EVENT1_ICLR_MRXFIFOTRG_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT1_ICLR_MRXFIFOTRG_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT1_ICLR_MRXFIFOTRG` writer - Master Receive FIFO Trigger Trigger when RX FIFO contains &gt;= defined bytes"] pub type INT_EVENT1_ICLR_MRXFIFOTRG_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT1_ICLR_MRXFIFOTRG_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT1_ICLR_MRXFIFOTRG_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event1_iclr_mrxfifotrg_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_ICLR_MRXFIFOTRG_AW :: INT_EVENT1_ICLR_MRXFIFOTRG_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event1_iclr_mrxfifotrg_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_ICLR_MRXFIFOTRG_AW :: INT_EVENT1_ICLR_MRXFIFOTRG_CLR) } } # [doc = "Master Transmit FIFO Trigger Trigger when Transmit FIFO contains &lt;= defined bytes\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT1_ICLR_MTXFIFOTRG_AW { # [doc = "0: NO_EFFECT"] INT_EVENT1_ICLR_MTXFIFOTRG_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT1_ICLR_MTXFIFOTRG_CLR = 1 , } impl From < INT_EVENT1_ICLR_MTXFIFOTRG_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT1_ICLR_MTXFIFOTRG_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT1_ICLR_MTXFIFOTRG` writer - Master Transmit FIFO Trigger Trigger when Transmit FIFO contains &lt;= defined bytes"] pub type INT_EVENT1_ICLR_MTXFIFOTRG_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT1_ICLR_MTXFIFOTRG_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT1_ICLR_MTXFIFOTRG_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event1_iclr_mtxfifotrg_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_ICLR_MTXFIFOTRG_AW :: INT_EVENT1_ICLR_MTXFIFOTRG_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event1_iclr_mtxfifotrg_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_ICLR_MTXFIFOTRG_AW :: INT_EVENT1_ICLR_MTXFIFOTRG_CLR) } } # [doc = "Slave Receive FIFO Trigger\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT1_ICLR_SRXFIFOTRG_AW { # [doc = "0: NO_EFFECT"] INT_EVENT1_ICLR_SRXFIFOTRG_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT1_ICLR_SRXFIFOTRG_CLR = 1 , } impl From < INT_EVENT1_ICLR_SRXFIFOTRG_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT1_ICLR_SRXFIFOTRG_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT1_ICLR_SRXFIFOTRG` writer - Slave Receive FIFO Trigger"] pub type INT_EVENT1_ICLR_SRXFIFOTRG_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT1_ICLR_SRXFIFOTRG_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT1_ICLR_SRXFIFOTRG_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event1_iclr_srxfifotrg_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_ICLR_SRXFIFOTRG_AW :: INT_EVENT1_ICLR_SRXFIFOTRG_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event1_iclr_srxfifotrg_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_ICLR_SRXFIFOTRG_AW :: INT_EVENT1_ICLR_SRXFIFOTRG_CLR) } } # [doc = "Slave Transmit FIFO Trigger\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT1_ICLR_STXFIFOTRG_AW { # [doc = "0: NO_EFFECT"] INT_EVENT1_ICLR_STXFIFOTRG_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT1_ICLR_STXFIFOTRG_CLR = 1 , } impl From < INT_EVENT1_ICLR_STXFIFOTRG_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT1_ICLR_STXFIFOTRG_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT1_ICLR_STXFIFOTRG` writer - Slave Transmit FIFO Trigger"] pub type INT_EVENT1_ICLR_STXFIFOTRG_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT1_ICLR_STXFIFOTRG_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT1_ICLR_STXFIFOTRG_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event1_iclr_stxfifotrg_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_ICLR_STXFIFOTRG_AW :: INT_EVENT1_ICLR_STXFIFOTRG_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event1_iclr_stxfifotrg_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_ICLR_STXFIFOTRG_AW :: INT_EVENT1_ICLR_STXFIFOTRG_CLR) } } impl W { # [doc = "Bit 0 - Master Receive FIFO Trigger Trigger when RX FIFO contains &gt;= defined bytes"] # [inline (always)] # [must_use] pub fn int_event1_iclr_mrxfifotrg (& mut self) -> INT_EVENT1_ICLR_MRXFIFOTRG_W < INT_EVENT1_ICLR_SPEC , 0 > { INT_EVENT1_ICLR_MRXFIFOTRG_W :: new (self) } # [doc = "Bit 1 - Master Transmit FIFO Trigger Trigger when Transmit FIFO contains &lt;= defined bytes"] # [inline (always)] # [must_use] pub fn int_event1_iclr_mtxfifotrg (& mut self) -> INT_EVENT1_ICLR_MTXFIFOTRG_W < INT_EVENT1_ICLR_SPEC , 1 > { INT_EVENT1_ICLR_MTXFIFOTRG_W :: new (self) } # [doc = "Bit 2 - Slave Receive FIFO Trigger"] # [inline (always)] # [must_use] pub fn int_event1_iclr_srxfifotrg (& mut self) -> INT_EVENT1_ICLR_SRXFIFOTRG_W <'_, INT_EVENT1_ICLR_SPEC , 2 > { INT_EVENT1_ICLR_SRXFIFOTRG_W :: new (self) } # [doc = "Bit 3 - Slave Transmit FIFO Trigger"] # [inline (always)] # [must_use] pub fn int_event1_iclr_stxfifotrg (& mut self) -> INT_EVENT1_ICLR_STXFIFOTRG_W < INT_EVENT1_ICLR_SPEC , 3 > { INT_EVENT1_ICLR_STXFIFOTRG_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Interrupt clear\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_event1_iclr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct INT_EVENT1_ICLR_SPEC ; impl crate :: RegisterSpec for INT_EVENT1_ICLR_SPEC { type Ux = u32 ; } # [doc = "`write(|w| ..)` method takes [`int_event1_iclr::W`](W) writer structure"] impl crate :: Writable for INT_EVENT1_ICLR_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets INT_EVENT1_ICLR to value 0"] impl crate :: Resettable for INT_EVENT1_ICLR_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/i2c1/soar.rs:1:5437 [INFO] [stdout] | [INFO] [stdout] 1 | ...st_use] pub fn soar_oaren (& mut self) -> SOAR_OAREN_W < SOAR_SPEC , 14 > { SOAR_OAREN_W :: new (self) } # [doc = "Bit 15 - This bit s... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `SOAR` reader"] pub type R = crate :: R < SOAR_SPEC > ; # [doc = "Register `SOAR` writer"] pub type W = crate :: W < SOAR_SPEC > ; # [doc = "Field `SOAR_OAR` reader - I2C Slave Own Address: This field specifies bits A9 through A0 of the slave address. In 7-bit addressing mode as selected by I2CSOAR.MODE bit, the top 3 bits are don't care"] pub type SOAR_OAR_R = crate :: FieldReader < u16 > ; # [doc = "Field `SOAR_OAR` writer - I2C Slave Own Address: This field specifies bits A9 through A0 of the slave address. In 7-bit addressing mode as selected by I2CSOAR.MODE bit, the top 3 bits are don't care"] pub type SOAR_OAR_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 10 , O , u16 > ; # [doc = "Field `SOAR_OAREN` reader - I2C Slave Own Address Enable"] pub type SOAR_OAREN_R = crate :: BitReader < SOAR_OAREN_A > ; # [doc = "I2C Slave Own Address Enable\n\nValue on reset: 1"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum SOAR_OAREN_A { # [doc = "0: DISABLE"] SOAR_OAREN_DISABLE = 0 , # [doc = "1: ENABLE"] SOAR_OAREN_ENABLE = 1 , } impl From < SOAR_OAREN_A > for bool { # [inline (always)] fn from (variant : SOAR_OAREN_A) -> Self { variant as u8 != 0 } } impl SOAR_OAREN_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> SOAR_OAREN_A { match self . bits { false => SOAR_OAREN_A :: SOAR_OAREN_DISABLE , true => SOAR_OAREN_A :: SOAR_OAREN_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_soar_oaren_disable (& self) -> bool { * self == SOAR_OAREN_A :: SOAR_OAREN_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_soar_oaren_enable (& self) -> bool { * self == SOAR_OAREN_A :: SOAR_OAREN_ENABLE } } # [doc = "Field `SOAR_OAREN` writer - I2C Slave Own Address Enable"] pub type SOAR_OAREN_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , SOAR_OAREN_A > ; impl < 'a , REG , const O : u8 > SOAR_OAREN_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn soar_oaren_disable (self) -> & 'a mut crate :: W < REG > { self . variant (SOAR_OAREN_A :: SOAR_OAREN_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn soar_oaren_enable (self) -> & 'a mut crate :: W < REG > { self . variant (SOAR_OAREN_A :: SOAR_OAREN_ENABLE) } } # [doc = "Field `SOAR_SMODE` reader - This bit selects the adressing mode to be used in slave mode. When 0, 7-bit addressing is used. When 1, 10-bit addressing is used."] pub type SOAR_SMODE_R = crate :: BitReader < SOAR_SMODE_A > ; # [doc = "This bit selects the adressing mode to be used in slave mode. When 0, 7-bit addressing is used. When 1, 10-bit addressing is used.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum SOAR_SMODE_A { # [doc = "0: MODE7"] SOAR_SMODE_MODE7 = 0 , # [doc = "1: MODE10"] SOAR_SMODE_MODE10 = 1 , } impl From < SOAR_SMODE_A > for bool { # [inline (always)] fn from (variant : SOAR_SMODE_A) -> Self { variant as u8 != 0 } } impl SOAR_SMODE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> SOAR_SMODE_A { match self . bits { false => SOAR_SMODE_A :: SOAR_SMODE_MODE7 , true => SOAR_SMODE_A :: SOAR_SMODE_MODE10 , } } # [doc = "MODE7"] # [inline (always)] pub fn is_soar_smode_mode7 (& self) -> bool { * self == SOAR_SMODE_A :: SOAR_SMODE_MODE7 } # [doc = "MODE10"] # [inline (always)] pub fn is_soar_smode_mode10 (& self) -> bool { * self == SOAR_SMODE_A :: SOAR_SMODE_MODE10 } } # [doc = "Field `SOAR_SMODE` writer - This bit selects the adressing mode to be used in slave mode. When 0, 7-bit addressing is used. When 1, 10-bit addressing is used."] pub type SOAR_SMODE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , SOAR_SMODE_A > ; impl < 'a , REG , const O : u8 > SOAR_SMODE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "MODE7"] # [inline (always)] pub fn soar_smode_mode7 (self) -> & 'a mut crate :: W < REG > { self . variant (SOAR_SMODE_A :: SOAR_SMODE_MODE7) } # [doc = "MODE10"] # [inline (always)] pub fn soar_smode_mode10 (self) -> & 'a mut crate :: W < REG > { self . variant (SOAR_SMODE_A :: SOAR_SMODE_MODE10) } } impl R { # [doc = "Bits 0:9 - I2C Slave Own Address: This field specifies bits A9 through A0 of the slave address. In 7-bit addressing mode as selected by I2CSOAR.MODE bit, the top 3 bits are don't care"] # [inline (always)] pub fn soar_oar (& self) -> SOAR_OAR_R { SOAR_OAR_R :: new ((self . bits & 0x03ff) as u16) } # [doc = "Bit 14 - I2C Slave Own Address Enable"] # [inline (always)] pub fn soar_oaren (& self) -> SOAR_OAREN_R { SOAR_OAREN_R :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - This bit selects the adressing mode to be used in slave mode. When 0, 7-bit addressing is used. When 1, 10-bit addressing is used."] # [inline (always)] pub fn soar_smode (& self) -> SOAR_SMODE_R { SOAR_SMODE_R :: new (((self . bits >> 15) & 1) != 0) } } impl W { # [doc = "Bits 0:9 - I2C Slave Own Address: This field specifies bits A9 through A0 of the slave address. In 7-bit addressing mode as selected by I2CSOAR.MODE bit, the top 3 bits are don't care"] # [inline (always)] # [must_use] pub fn soar_oar (& mut self) -> SOAR_OAR_W < SOAR_SPEC , 0 > { SOAR_OAR_W :: new (self) } # [doc = "Bit 14 - I2C Slave Own Address Enable"] # [inline (always)] # [must_use] pub fn soar_oaren (& mut self) -> SOAR_OAREN_W <'_, SOAR_SPEC , 14 > { SOAR_OAREN_W :: new (self) } # [doc = "Bit 15 - This bit selects the adressing mode to be used in slave mode. When 0, 7-bit addressing is used. When 1, 10-bit addressing is used."] # [inline (always)] # [must_use] pub fn soar_smode (& mut self) -> SOAR_SMODE_W < SOAR_SPEC , 15 > { SOAR_SMODE_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "I2C Slave Own Address\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`soar::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`soar::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct SOAR_SPEC ; impl crate :: RegisterSpec for SOAR_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`soar::R`](R) reader structure"] impl crate :: Readable for SOAR_SPEC { } # [doc = "`write(|w| ..)` method takes [`soar::W`](W) writer structure"] impl crate :: Writable for SOAR_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets SOAR to value 0x4000"] impl crate :: Resettable for SOAR_SPEC { const RESET_VALUE : Self :: Ux = 0x4000 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/opa0/pwrctl.rs:1:2896 [INFO] [stdout] | [INFO] [stdout] 1 | ...pub fn pwrctl_auto_off (& mut self) -> PWRCTL_AUTO_OFF_W < PWRCTL_SPEC , 0 > { PWRCTL_AUTO_OFF_W :: new (self) } # [doc = r" Writes ra... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `PWRCTL` reader"] pub type R = crate :: R < PWRCTL_SPEC > ; # [doc = "Register `PWRCTL` writer"] pub type W = crate :: W < PWRCTL_SPEC > ; # [doc = "Field `PWRCTL_AUTO_OFF` reader - When set the peripheral will remove its local IP request for enable so that it can be disabled if no other entities in the system are requesting it to be enabled."] pub type PWRCTL_AUTO_OFF_R = crate :: BitReader < PWRCTL_AUTO_OFF_A > ; # [doc = "When set the peripheral will remove its local IP request for enable so that it can be disabled if no other entities in the system are requesting it to be enabled.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum PWRCTL_AUTO_OFF_A { # [doc = "0: DISABLE"] PWRCTL_AUTO_OFF_DISABLE = 0 , # [doc = "1: ENABLE"] PWRCTL_AUTO_OFF_ENABLE = 1 , } impl From < PWRCTL_AUTO_OFF_A > for bool { # [inline (always)] fn from (variant : PWRCTL_AUTO_OFF_A) -> Self { variant as u8 != 0 } } impl PWRCTL_AUTO_OFF_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> PWRCTL_AUTO_OFF_A { match self . bits { false => PWRCTL_AUTO_OFF_A :: PWRCTL_AUTO_OFF_DISABLE , true => PWRCTL_AUTO_OFF_A :: PWRCTL_AUTO_OFF_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_pwrctl_auto_off_disable (& self) -> bool { * self == PWRCTL_AUTO_OFF_A :: PWRCTL_AUTO_OFF_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_pwrctl_auto_off_enable (& self) -> bool { * self == PWRCTL_AUTO_OFF_A :: PWRCTL_AUTO_OFF_ENABLE } } # [doc = "Field `PWRCTL_AUTO_OFF` writer - When set the peripheral will remove its local IP request for enable so that it can be disabled if no other entities in the system are requesting it to be enabled."] pub type PWRCTL_AUTO_OFF_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , PWRCTL_AUTO_OFF_A > ; impl < 'a , REG , const O : u8 > PWRCTL_AUTO_OFF_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn pwrctl_auto_off_disable (self) -> & 'a mut crate :: W < REG > { self . variant (PWRCTL_AUTO_OFF_A :: PWRCTL_AUTO_OFF_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn pwrctl_auto_off_enable (self) -> & 'a mut crate :: W < REG > { self . variant (PWRCTL_AUTO_OFF_A :: PWRCTL_AUTO_OFF_ENABLE) } } impl R { # [doc = "Bit 0 - When set the peripheral will remove its local IP request for enable so that it can be disabled if no other entities in the system are requesting it to be enabled."] # [inline (always)] pub fn pwrctl_auto_off (& self) -> PWRCTL_AUTO_OFF_R { PWRCTL_AUTO_OFF_R :: new ((self . bits & 1) != 0) } } impl W { # [doc = "Bit 0 - When set the peripheral will remove its local IP request for enable so that it can be disabled if no other entities in the system are requesting it to be enabled."] # [inline (always)] # [must_use] pub fn pwrctl_auto_off (& mut self) -> PWRCTL_AUTO_OFF_W <'_, PWRCTL_SPEC , 0 > { PWRCTL_AUTO_OFF_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Power Control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pwrctl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pwrctl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PWRCTL_SPEC ; impl crate :: RegisterSpec for PWRCTL_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`pwrctl::R`](R) reader structure"] impl crate :: Readable for PWRCTL_SPEC { } # [doc = "`write(|w| ..)` method takes [`pwrctl::W`](W) writer structure"] impl crate :: Writable for PWRCTL_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets PWRCTL to value 0"] impl crate :: Resettable for PWRCTL_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/spi0/int_event0_imask.rs:1:24681 [INFO] [stdout] | [INFO] [stdout] 1 | ...vent0_imask_per (& mut self) -> INT_EVENT0_IMASK_PER_W < INT_EVENT0_IMASK_SPEC , 1 > { INT_EVENT0_IMASK_PER_W :: new (self) } # [doc =... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `INT_EVENT0_IMASK` reader"] pub type R = crate :: R < INT_EVENT0_IMASK_SPEC > ; # [doc = "Register `INT_EVENT0_IMASK` writer"] pub type W = crate :: W < INT_EVENT0_IMASK_SPEC > ; # [doc = "Field `INT_EVENT0_IMASK_RXFIFO_OVF` reader - RXFIFO overflow event mask."] pub type INT_EVENT0_IMASK_RXFIFO_OVF_R = crate :: BitReader < INT_EVENT0_IMASK_RXFIFO_OVF_A > ; # [doc = "RXFIFO overflow event mask.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_RXFIFO_OVF_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_RXFIFO_OVF_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_RXFIFO_OVF_SET = 1 , } impl From < INT_EVENT0_IMASK_RXFIFO_OVF_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_RXFIFO_OVF_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_RXFIFO_OVF_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_RXFIFO_OVF_A { match self . bits { false => INT_EVENT0_IMASK_RXFIFO_OVF_A :: INT_EVENT0_IMASK_RXFIFO_OVF_CLR , true => INT_EVENT0_IMASK_RXFIFO_OVF_A :: INT_EVENT0_IMASK_RXFIFO_OVF_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_rxfifo_ovf_clr (& self) -> bool { * self == INT_EVENT0_IMASK_RXFIFO_OVF_A :: INT_EVENT0_IMASK_RXFIFO_OVF_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_rxfifo_ovf_set (& self) -> bool { * self == INT_EVENT0_IMASK_RXFIFO_OVF_A :: INT_EVENT0_IMASK_RXFIFO_OVF_SET } } # [doc = "Field `INT_EVENT0_IMASK_RXFIFO_OVF` writer - RXFIFO overflow event mask."] pub type INT_EVENT0_IMASK_RXFIFO_OVF_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_RXFIFO_OVF_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_RXFIFO_OVF_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_rxfifo_ovf_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXFIFO_OVF_A :: INT_EVENT0_IMASK_RXFIFO_OVF_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_rxfifo_ovf_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXFIFO_OVF_A :: INT_EVENT0_IMASK_RXFIFO_OVF_SET) } } # [doc = "Field `INT_EVENT0_IMASK_PER` reader - Parity error event mask."] pub type INT_EVENT0_IMASK_PER_R = crate :: BitReader < INT_EVENT0_IMASK_PER_A > ; # [doc = "Parity error event mask.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_PER_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_PER_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_PER_SET = 1 , } impl From < INT_EVENT0_IMASK_PER_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_PER_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_PER_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_PER_A { match self . bits { false => INT_EVENT0_IMASK_PER_A :: INT_EVENT0_IMASK_PER_CLR , true => INT_EVENT0_IMASK_PER_A :: INT_EVENT0_IMASK_PER_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_per_clr (& self) -> bool { * self == INT_EVENT0_IMASK_PER_A :: INT_EVENT0_IMASK_PER_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_per_set (& self) -> bool { * self == INT_EVENT0_IMASK_PER_A :: INT_EVENT0_IMASK_PER_SET } } # [doc = "Field `INT_EVENT0_IMASK_PER` writer - Parity error event mask."] pub type INT_EVENT0_IMASK_PER_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_PER_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_PER_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_per_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_PER_A :: INT_EVENT0_IMASK_PER_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_per_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_PER_A :: INT_EVENT0_IMASK_PER_SET) } } # [doc = "Field `INT_EVENT0_IMASK_RTOUT` reader - Enable SPI Receive Time-Out event mask."] pub type INT_EVENT0_IMASK_RTOUT_R = crate :: BitReader < INT_EVENT0_IMASK_RTOUT_A > ; # [doc = "Enable SPI Receive Time-Out event mask.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_RTOUT_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_RTOUT_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_RTOUT_SET = 1 , } impl From < INT_EVENT0_IMASK_RTOUT_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_RTOUT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_RTOUT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_RTOUT_A { match self . bits { false => INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_CLR , true => INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_rtout_clr (& self) -> bool { * self == INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_rtout_set (& self) -> bool { * self == INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_SET } } # [doc = "Field `INT_EVENT0_IMASK_RTOUT` writer - Enable SPI Receive Time-Out event mask."] pub type INT_EVENT0_IMASK_RTOUT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_RTOUT_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_RTOUT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_rtout_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_rtout_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_SET) } } # [doc = "Field `INT_EVENT0_IMASK_RX` reader - Receive FIFO event.This interrupt is set if the selected Receive FIFO level has been reached"] pub type INT_EVENT0_IMASK_RX_R = crate :: BitReader < INT_EVENT0_IMASK_RX_A > ; # [doc = "Receive FIFO event.This interrupt is set if the selected Receive FIFO level has been reached\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_RX_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_RX_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_RX_SET = 1 , } impl From < INT_EVENT0_IMASK_RX_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_RX_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_RX_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_RX_A { match self . bits { false => INT_EVENT0_IMASK_RX_A :: INT_EVENT0_IMASK_RX_CLR , true => INT_EVENT0_IMASK_RX_A :: INT_EVENT0_IMASK_RX_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_rx_clr (& self) -> bool { * self == INT_EVENT0_IMASK_RX_A :: INT_EVENT0_IMASK_RX_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_rx_set (& self) -> bool { * self == INT_EVENT0_IMASK_RX_A :: INT_EVENT0_IMASK_RX_SET } } # [doc = "Field `INT_EVENT0_IMASK_RX` writer - Receive FIFO event.This interrupt is set if the selected Receive FIFO level has been reached"] pub type INT_EVENT0_IMASK_RX_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_RX_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_RX_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_rx_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RX_A :: INT_EVENT0_IMASK_RX_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_rx_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RX_A :: INT_EVENT0_IMASK_RX_SET) } } # [doc = "Field `INT_EVENT0_IMASK_TX` reader - Transmit FIFO event mask."] pub type INT_EVENT0_IMASK_TX_R = crate :: BitReader < INT_EVENT0_IMASK_TX_A > ; # [doc = "Transmit FIFO event mask.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_TX_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_TX_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_TX_SET = 1 , } impl From < INT_EVENT0_IMASK_TX_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_TX_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_TX_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_TX_A { match self . bits { false => INT_EVENT0_IMASK_TX_A :: INT_EVENT0_IMASK_TX_CLR , true => INT_EVENT0_IMASK_TX_A :: INT_EVENT0_IMASK_TX_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_tx_clr (& self) -> bool { * self == INT_EVENT0_IMASK_TX_A :: INT_EVENT0_IMASK_TX_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_tx_set (& self) -> bool { * self == INT_EVENT0_IMASK_TX_A :: INT_EVENT0_IMASK_TX_SET } } # [doc = "Field `INT_EVENT0_IMASK_TX` writer - Transmit FIFO event mask."] pub type INT_EVENT0_IMASK_TX_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_TX_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_TX_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_tx_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_TX_A :: INT_EVENT0_IMASK_TX_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_tx_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_TX_A :: INT_EVENT0_IMASK_TX_SET) } } # [doc = "Field `INT_EVENT0_IMASK_TXEMPTY` reader - Transmit FIFO Empty event mask."] pub type INT_EVENT0_IMASK_TXEMPTY_R = crate :: BitReader < INT_EVENT0_IMASK_TXEMPTY_A > ; # [doc = "Transmit FIFO Empty event mask.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_TXEMPTY_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_TXEMPTY_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_TXEMPTY_SET = 1 , } impl From < INT_EVENT0_IMASK_TXEMPTY_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_TXEMPTY_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_TXEMPTY_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_TXEMPTY_A { match self . bits { false => INT_EVENT0_IMASK_TXEMPTY_A :: INT_EVENT0_IMASK_TXEMPTY_CLR , true => INT_EVENT0_IMASK_TXEMPTY_A :: INT_EVENT0_IMASK_TXEMPTY_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_txempty_clr (& self) -> bool { * self == INT_EVENT0_IMASK_TXEMPTY_A :: INT_EVENT0_IMASK_TXEMPTY_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_txempty_set (& self) -> bool { * self == INT_EVENT0_IMASK_TXEMPTY_A :: INT_EVENT0_IMASK_TXEMPTY_SET } } # [doc = "Field `INT_EVENT0_IMASK_TXEMPTY` writer - Transmit FIFO Empty event mask."] pub type INT_EVENT0_IMASK_TXEMPTY_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_TXEMPTY_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_TXEMPTY_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_txempty_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_TXEMPTY_A :: INT_EVENT0_IMASK_TXEMPTY_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_txempty_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_TXEMPTY_A :: INT_EVENT0_IMASK_TXEMPTY_SET) } } # [doc = "Field `INT_EVENT0_IMASK_IDLE` reader - SPI Idle event mask."] pub type INT_EVENT0_IMASK_IDLE_R = crate :: BitReader < INT_EVENT0_IMASK_IDLE_A > ; # [doc = "SPI Idle event mask.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_IDLE_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_IDLE_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_IDLE_SET = 1 , } impl From < INT_EVENT0_IMASK_IDLE_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_IDLE_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_IDLE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_IDLE_A { match self . bits { false => INT_EVENT0_IMASK_IDLE_A :: INT_EVENT0_IMASK_IDLE_CLR , true => INT_EVENT0_IMASK_IDLE_A :: INT_EVENT0_IMASK_IDLE_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_idle_clr (& self) -> bool { * self == INT_EVENT0_IMASK_IDLE_A :: INT_EVENT0_IMASK_IDLE_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_idle_set (& self) -> bool { * self == INT_EVENT0_IMASK_IDLE_A :: INT_EVENT0_IMASK_IDLE_SET } } # [doc = "Field `INT_EVENT0_IMASK_IDLE` writer - SPI Idle event mask."] pub type INT_EVENT0_IMASK_IDLE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_IDLE_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_IDLE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_idle_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_IDLE_A :: INT_EVENT0_IMASK_IDLE_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_idle_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_IDLE_A :: INT_EVENT0_IMASK_IDLE_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DMA_DONE_RX` reader - DMA Done 1 event for RX event mask."] pub type INT_EVENT0_IMASK_DMA_DONE_RX_R = crate :: BitReader < INT_EVENT0_IMASK_DMA_DONE_RX_A > ; # [doc = "DMA Done 1 event for RX event mask.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DMA_DONE_RX_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DMA_DONE_RX_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DMA_DONE_RX_SET = 1 , } impl From < INT_EVENT0_IMASK_DMA_DONE_RX_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DMA_DONE_RX_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DMA_DONE_RX_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DMA_DONE_RX_A { match self . bits { false => INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_CLR , true => INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dma_done_rx_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dma_done_rx_set (& self) -> bool { * self == INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_SET } } # [doc = "Field `INT_EVENT0_IMASK_DMA_DONE_RX` writer - DMA Done 1 event for RX event mask."] pub type INT_EVENT0_IMASK_DMA_DONE_RX_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DMA_DONE_RX_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DMA_DONE_RX_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dma_done_rx_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dma_done_rx_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DMA_DONE_TX` reader - DMA Done 1 event for TX event mask."] pub type INT_EVENT0_IMASK_DMA_DONE_TX_R = crate :: BitReader < INT_EVENT0_IMASK_DMA_DONE_TX_A > ; # [doc = "DMA Done 1 event for TX event mask.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DMA_DONE_TX_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DMA_DONE_TX_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DMA_DONE_TX_SET = 1 , } impl From < INT_EVENT0_IMASK_DMA_DONE_TX_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DMA_DONE_TX_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DMA_DONE_TX_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DMA_DONE_TX_A { match self . bits { false => INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_CLR , true => INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dma_done_tx_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dma_done_tx_set (& self) -> bool { * self == INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_SET } } # [doc = "Field `INT_EVENT0_IMASK_DMA_DONE_TX` writer - DMA Done 1 event for TX event mask."] pub type INT_EVENT0_IMASK_DMA_DONE_TX_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DMA_DONE_TX_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DMA_DONE_TX_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dma_done_tx_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dma_done_tx_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_SET) } } # [doc = "Field `INT_EVENT0_IMASK_TXFIFO_UNF` reader - TX FIFO underflow interrupt mask"] pub type INT_EVENT0_IMASK_TXFIFO_UNF_R = crate :: BitReader < INT_EVENT0_IMASK_TXFIFO_UNF_A > ; # [doc = "TX FIFO underflow interrupt mask\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_TXFIFO_UNF_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_TXFIFO_UNF_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_TXFIFO_UNF_SET = 1 , } impl From < INT_EVENT0_IMASK_TXFIFO_UNF_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_TXFIFO_UNF_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_TXFIFO_UNF_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_TXFIFO_UNF_A { match self . bits { false => INT_EVENT0_IMASK_TXFIFO_UNF_A :: INT_EVENT0_IMASK_TXFIFO_UNF_CLR , true => INT_EVENT0_IMASK_TXFIFO_UNF_A :: INT_EVENT0_IMASK_TXFIFO_UNF_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_txfifo_unf_clr (& self) -> bool { * self == INT_EVENT0_IMASK_TXFIFO_UNF_A :: INT_EVENT0_IMASK_TXFIFO_UNF_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_txfifo_unf_set (& self) -> bool { * self == INT_EVENT0_IMASK_TXFIFO_UNF_A :: INT_EVENT0_IMASK_TXFIFO_UNF_SET } } # [doc = "Field `INT_EVENT0_IMASK_TXFIFO_UNF` writer - TX FIFO underflow interrupt mask"] pub type INT_EVENT0_IMASK_TXFIFO_UNF_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_TXFIFO_UNF_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_TXFIFO_UNF_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_txfifo_unf_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_TXFIFO_UNF_A :: INT_EVENT0_IMASK_TXFIFO_UNF_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_txfifo_unf_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_TXFIFO_UNF_A :: INT_EVENT0_IMASK_TXFIFO_UNF_SET) } } # [doc = "Field `INT_EVENT0_IMASK_RXFULL` reader - RX FIFO Full Interrupt Mask"] pub type INT_EVENT0_IMASK_RXFULL_R = crate :: BitReader < INT_EVENT0_IMASK_RXFULL_A > ; # [doc = "RX FIFO Full Interrupt Mask\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_RXFULL_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_RXFULL_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_RXFULL_SET = 1 , } impl From < INT_EVENT0_IMASK_RXFULL_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_RXFULL_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_RXFULL_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_RXFULL_A { match self . bits { false => INT_EVENT0_IMASK_RXFULL_A :: INT_EVENT0_IMASK_RXFULL_CLR , true => INT_EVENT0_IMASK_RXFULL_A :: INT_EVENT0_IMASK_RXFULL_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_rxfull_clr (& self) -> bool { * self == INT_EVENT0_IMASK_RXFULL_A :: INT_EVENT0_IMASK_RXFULL_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_rxfull_set (& self) -> bool { * self == INT_EVENT0_IMASK_RXFULL_A :: INT_EVENT0_IMASK_RXFULL_SET } } # [doc = "Field `INT_EVENT0_IMASK_RXFULL` writer - RX FIFO Full Interrupt Mask"] pub type INT_EVENT0_IMASK_RXFULL_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_RXFULL_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_RXFULL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_rxfull_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXFULL_A :: INT_EVENT0_IMASK_RXFULL_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_rxfull_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXFULL_A :: INT_EVENT0_IMASK_RXFULL_SET) } } impl R { # [doc = "Bit 0 - RXFIFO overflow event mask."] # [inline (always)] pub fn int_event0_imask_rxfifo_ovf (& self) -> INT_EVENT0_IMASK_RXFIFO_OVF_R { INT_EVENT0_IMASK_RXFIFO_OVF_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - Parity error event mask."] # [inline (always)] pub fn int_event0_imask_per (& self) -> INT_EVENT0_IMASK_PER_R { INT_EVENT0_IMASK_PER_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - Enable SPI Receive Time-Out event mask."] # [inline (always)] pub fn int_event0_imask_rtout (& self) -> INT_EVENT0_IMASK_RTOUT_R { INT_EVENT0_IMASK_RTOUT_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - Receive FIFO event.This interrupt is set if the selected Receive FIFO level has been reached"] # [inline (always)] pub fn int_event0_imask_rx (& self) -> INT_EVENT0_IMASK_RX_R { INT_EVENT0_IMASK_RX_R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - Transmit FIFO event mask."] # [inline (always)] pub fn int_event0_imask_tx (& self) -> INT_EVENT0_IMASK_TX_R { INT_EVENT0_IMASK_TX_R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - Transmit FIFO Empty event mask."] # [inline (always)] pub fn int_event0_imask_txempty (& self) -> INT_EVENT0_IMASK_TXEMPTY_R { INT_EVENT0_IMASK_TXEMPTY_R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - SPI Idle event mask."] # [inline (always)] pub fn int_event0_imask_idle (& self) -> INT_EVENT0_IMASK_IDLE_R { INT_EVENT0_IMASK_IDLE_R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - DMA Done 1 event for RX event mask."] # [inline (always)] pub fn int_event0_imask_dma_done_rx (& self) -> INT_EVENT0_IMASK_DMA_DONE_RX_R { INT_EVENT0_IMASK_DMA_DONE_RX_R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - DMA Done 1 event for TX event mask."] # [inline (always)] pub fn int_event0_imask_dma_done_tx (& self) -> INT_EVENT0_IMASK_DMA_DONE_TX_R { INT_EVENT0_IMASK_DMA_DONE_TX_R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - TX FIFO underflow interrupt mask"] # [inline (always)] pub fn int_event0_imask_txfifo_unf (& self) -> INT_EVENT0_IMASK_TXFIFO_UNF_R { INT_EVENT0_IMASK_TXFIFO_UNF_R :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - RX FIFO Full Interrupt Mask"] # [inline (always)] pub fn int_event0_imask_rxfull (& self) -> INT_EVENT0_IMASK_RXFULL_R { INT_EVENT0_IMASK_RXFULL_R :: new (((self . bits >> 10) & 1) != 0) } } impl W { # [doc = "Bit 0 - RXFIFO overflow event mask."] # [inline (always)] # [must_use] pub fn int_event0_imask_rxfifo_ovf (& mut self) -> INT_EVENT0_IMASK_RXFIFO_OVF_W < INT_EVENT0_IMASK_SPEC , 0 > { INT_EVENT0_IMASK_RXFIFO_OVF_W :: new (self) } # [doc = "Bit 1 - Parity error event mask."] # [inline (always)] # [must_use] pub fn int_event0_imask_per (& mut self) -> INT_EVENT0_IMASK_PER_W <'_, INT_EVENT0_IMASK_SPEC , 1 > { INT_EVENT0_IMASK_PER_W :: new (self) } # [doc = "Bit 2 - Enable SPI Receive Time-Out event mask."] # [inline (always)] # [must_use] pub fn int_event0_imask_rtout (& mut self) -> INT_EVENT0_IMASK_RTOUT_W < INT_EVENT0_IMASK_SPEC , 2 > { INT_EVENT0_IMASK_RTOUT_W :: new (self) } # [doc = "Bit 3 - Receive FIFO event.This interrupt is set if the selected Receive FIFO level has been reached"] # [inline (always)] # [must_use] pub fn int_event0_imask_rx (& mut self) -> INT_EVENT0_IMASK_RX_W < INT_EVENT0_IMASK_SPEC , 3 > { INT_EVENT0_IMASK_RX_W :: new (self) } # [doc = "Bit 4 - Transmit FIFO event mask."] # [inline (always)] # [must_use] pub fn int_event0_imask_tx (& mut self) -> INT_EVENT0_IMASK_TX_W < INT_EVENT0_IMASK_SPEC , 4 > { INT_EVENT0_IMASK_TX_W :: new (self) } # [doc = "Bit 5 - Transmit FIFO Empty event mask."] # [inline (always)] # [must_use] pub fn int_event0_imask_txempty (& mut self) -> INT_EVENT0_IMASK_TXEMPTY_W < INT_EVENT0_IMASK_SPEC , 5 > { INT_EVENT0_IMASK_TXEMPTY_W :: new (self) } # [doc = "Bit 6 - SPI Idle event mask."] # [inline (always)] # [must_use] pub fn int_event0_imask_idle (& mut self) -> INT_EVENT0_IMASK_IDLE_W < INT_EVENT0_IMASK_SPEC , 6 > { INT_EVENT0_IMASK_IDLE_W :: new (self) } # [doc = "Bit 7 - DMA Done 1 event for RX event mask."] # [inline (always)] # [must_use] pub fn int_event0_imask_dma_done_rx (& mut self) -> INT_EVENT0_IMASK_DMA_DONE_RX_W < INT_EVENT0_IMASK_SPEC , 7 > { INT_EVENT0_IMASK_DMA_DONE_RX_W :: new (self) } # [doc = "Bit 8 - DMA Done 1 event for TX event mask."] # [inline (always)] # [must_use] pub fn int_event0_imask_dma_done_tx (& mut self) -> INT_EVENT0_IMASK_DMA_DONE_TX_W < INT_EVENT0_IMASK_SPEC , 8 > { INT_EVENT0_IMASK_DMA_DONE_TX_W :: new (self) } # [doc = "Bit 9 - TX FIFO underflow interrupt mask"] # [inline (always)] # [must_use] pub fn int_event0_imask_txfifo_unf (& mut self) -> INT_EVENT0_IMASK_TXFIFO_UNF_W < INT_EVENT0_IMASK_SPEC , 9 > { INT_EVENT0_IMASK_TXFIFO_UNF_W :: new (self) } # [doc = "Bit 10 - RX FIFO Full Interrupt Mask"] # [inline (always)] # [must_use] pub fn int_event0_imask_rxfull (& mut self) -> INT_EVENT0_IMASK_RXFULL_W < INT_EVENT0_IMASK_SPEC , 10 > { INT_EVENT0_IMASK_RXFULL_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Interrupt mask\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_event0_imask::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_event0_imask::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct INT_EVENT0_IMASK_SPEC ; impl crate :: RegisterSpec for INT_EVENT0_IMASK_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`int_event0_imask::R`](R) reader structure"] impl crate :: Readable for INT_EVENT0_IMASK_SPEC { } # [doc = "`write(|w| ..)` method takes [`int_event0_imask::W`](W) writer structure"] impl crate :: Writable for INT_EVENT0_IMASK_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets INT_EVENT0_IMASK to value 0"] impl crate :: Resettable for INT_EVENT0_IMASK_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/timg4/octl_01.rs:1:9948 [INFO] [stdout] | [INFO] [stdout] 1 | ...se] pub fn octl_01_ccpo (& mut self) -> OCTL_01_CCPO_W < OCTL_01_SPEC , 0 > { OCTL_01_CCPO_W :: new (self) } # [doc = "Bit 4 - CCP Out... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `OCTL_01[%s]` reader"] pub type R = crate :: R < OCTL_01_SPEC > ; # [doc = "Register `OCTL_01[%s]` writer"] pub type W = crate :: W < OCTL_01_SPEC > ; # [doc = "Field `OCTL_01_CCPO` reader - CCP Output Source"] pub type OCTL_01_CCPO_R = crate :: FieldReader < OCTL_01_CCPO_A > ; # [doc = "CCP Output Source\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum OCTL_01_CCPO_A { # [doc = "0: FUNCVAL"] OCTL_01_CCPO_FUNCVAL = 0 , # [doc = "1: LOAD"] OCTL_01_CCPO_LOAD = 1 , # [doc = "2: CMPVAL"] OCTL_01_CCPO_CMPVAL = 2 , # [doc = "4: ZERO"] OCTL_01_CCPO_ZERO = 4 , # [doc = "5: CAPCOND"] OCTL_01_CCPO_CAPCOND = 5 , # [doc = "6: FAULTCOND"] OCTL_01_CCPO_FAULTCOND = 6 , # [doc = "8: CC0_MIRROR_ALL"] OCTL_01_CCPO_CC0_MIRROR_ALL = 8 , # [doc = "9: CC1_MIRROR_ALL"] OCTL_01_CCPO_CC1_MIRROR_ALL = 9 , # [doc = "12: DEADBAND"] OCTL_01_CCPO_DEADBAND = 12 , # [doc = "13: CNTDIR"] OCTL_01_CCPO_CNTDIR = 13 , } impl From < OCTL_01_CCPO_A > for u8 { # [inline (always)] fn from (variant : OCTL_01_CCPO_A) -> Self { variant as _ } } impl crate :: FieldSpec for OCTL_01_CCPO_A { type Ux = u8 ; } impl OCTL_01_CCPO_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < OCTL_01_CCPO_A > { match self . bits { 0 => Some (OCTL_01_CCPO_A :: OCTL_01_CCPO_FUNCVAL) , 1 => Some (OCTL_01_CCPO_A :: OCTL_01_CCPO_LOAD) , 2 => Some (OCTL_01_CCPO_A :: OCTL_01_CCPO_CMPVAL) , 4 => Some (OCTL_01_CCPO_A :: OCTL_01_CCPO_ZERO) , 5 => Some (OCTL_01_CCPO_A :: OCTL_01_CCPO_CAPCOND) , 6 => Some (OCTL_01_CCPO_A :: OCTL_01_CCPO_FAULTCOND) , 8 => Some (OCTL_01_CCPO_A :: OCTL_01_CCPO_CC0_MIRROR_ALL) , 9 => Some (OCTL_01_CCPO_A :: OCTL_01_CCPO_CC1_MIRROR_ALL) , 12 => Some (OCTL_01_CCPO_A :: OCTL_01_CCPO_DEADBAND) , 13 => Some (OCTL_01_CCPO_A :: OCTL_01_CCPO_CNTDIR) , _ => None , } } # [doc = "FUNCVAL"] # [inline (always)] pub fn is_octl_01_ccpo_funcval (& self) -> bool { * self == OCTL_01_CCPO_A :: OCTL_01_CCPO_FUNCVAL } # [doc = "LOAD"] # [inline (always)] pub fn is_octl_01_ccpo_load (& self) -> bool { * self == OCTL_01_CCPO_A :: OCTL_01_CCPO_LOAD } # [doc = "CMPVAL"] # [inline (always)] pub fn is_octl_01_ccpo_cmpval (& self) -> bool { * self == OCTL_01_CCPO_A :: OCTL_01_CCPO_CMPVAL } # [doc = "ZERO"] # [inline (always)] pub fn is_octl_01_ccpo_zero (& self) -> bool { * self == OCTL_01_CCPO_A :: OCTL_01_CCPO_ZERO } # [doc = "CAPCOND"] # [inline (always)] pub fn is_octl_01_ccpo_capcond (& self) -> bool { * self == OCTL_01_CCPO_A :: OCTL_01_CCPO_CAPCOND } # [doc = "FAULTCOND"] # [inline (always)] pub fn is_octl_01_ccpo_faultcond (& self) -> bool { * self == OCTL_01_CCPO_A :: OCTL_01_CCPO_FAULTCOND } # [doc = "CC0_MIRROR_ALL"] # [inline (always)] pub fn is_octl_01_ccpo_cc0_mirror_all (& self) -> bool { * self == OCTL_01_CCPO_A :: OCTL_01_CCPO_CC0_MIRROR_ALL } # [doc = "CC1_MIRROR_ALL"] # [inline (always)] pub fn is_octl_01_ccpo_cc1_mirror_all (& self) -> bool { * self == OCTL_01_CCPO_A :: OCTL_01_CCPO_CC1_MIRROR_ALL } # [doc = "DEADBAND"] # [inline (always)] pub fn is_octl_01_ccpo_deadband (& self) -> bool { * self == OCTL_01_CCPO_A :: OCTL_01_CCPO_DEADBAND } # [doc = "CNTDIR"] # [inline (always)] pub fn is_octl_01_ccpo_cntdir (& self) -> bool { * self == OCTL_01_CCPO_A :: OCTL_01_CCPO_CNTDIR } } # [doc = "Field `OCTL_01_CCPO` writer - CCP Output Source"] pub type OCTL_01_CCPO_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 4 , O , OCTL_01_CCPO_A > ; impl < 'a , REG , const O : u8 > OCTL_01_CCPO_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "FUNCVAL"] # [inline (always)] pub fn octl_01_ccpo_funcval (self) -> & 'a mut crate :: W < REG > { self . variant (OCTL_01_CCPO_A :: OCTL_01_CCPO_FUNCVAL) } # [doc = "LOAD"] # [inline (always)] pub fn octl_01_ccpo_load (self) -> & 'a mut crate :: W < REG > { self . variant (OCTL_01_CCPO_A :: OCTL_01_CCPO_LOAD) } # [doc = "CMPVAL"] # [inline (always)] pub fn octl_01_ccpo_cmpval (self) -> & 'a mut crate :: W < REG > { self . variant (OCTL_01_CCPO_A :: OCTL_01_CCPO_CMPVAL) } # [doc = "ZERO"] # [inline (always)] pub fn octl_01_ccpo_zero (self) -> & 'a mut crate :: W < REG > { self . variant (OCTL_01_CCPO_A :: OCTL_01_CCPO_ZERO) } # [doc = "CAPCOND"] # [inline (always)] pub fn octl_01_ccpo_capcond (self) -> & 'a mut crate :: W < REG > { self . variant (OCTL_01_CCPO_A :: OCTL_01_CCPO_CAPCOND) } # [doc = "FAULTCOND"] # [inline (always)] pub fn octl_01_ccpo_faultcond (self) -> & 'a mut crate :: W < REG > { self . variant (OCTL_01_CCPO_A :: OCTL_01_CCPO_FAULTCOND) } # [doc = "CC0_MIRROR_ALL"] # [inline (always)] pub fn octl_01_ccpo_cc0_mirror_all (self) -> & 'a mut crate :: W < REG > { self . variant (OCTL_01_CCPO_A :: OCTL_01_CCPO_CC0_MIRROR_ALL) } # [doc = "CC1_MIRROR_ALL"] # [inline (always)] pub fn octl_01_ccpo_cc1_mirror_all (self) -> & 'a mut crate :: W < REG > { self . variant (OCTL_01_CCPO_A :: OCTL_01_CCPO_CC1_MIRROR_ALL) } # [doc = "DEADBAND"] # [inline (always)] pub fn octl_01_ccpo_deadband (self) -> & 'a mut crate :: W < REG > { self . variant (OCTL_01_CCPO_A :: OCTL_01_CCPO_DEADBAND) } # [doc = "CNTDIR"] # [inline (always)] pub fn octl_01_ccpo_cntdir (self) -> & 'a mut crate :: W < REG > { self . variant (OCTL_01_CCPO_A :: OCTL_01_CCPO_CNTDIR) } } # [doc = "Field `OCTL_01_CCPOINV` reader - CCP Output Invert The output as selected by CCPO is conditionally inverted."] pub type OCTL_01_CCPOINV_R = crate :: BitReader < OCTL_01_CCPOINV_A > ; # [doc = "CCP Output Invert The output as selected by CCPO is conditionally inverted.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum OCTL_01_CCPOINV_A { # [doc = "0: NOINV"] OCTL_01_CCPOINV_NOINV = 0 , # [doc = "1: INV"] OCTL_01_CCPOINV_INV = 1 , } impl From < OCTL_01_CCPOINV_A > for bool { # [inline (always)] fn from (variant : OCTL_01_CCPOINV_A) -> Self { variant as u8 != 0 } } impl OCTL_01_CCPOINV_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> OCTL_01_CCPOINV_A { match self . bits { false => OCTL_01_CCPOINV_A :: OCTL_01_CCPOINV_NOINV , true => OCTL_01_CCPOINV_A :: OCTL_01_CCPOINV_INV , } } # [doc = "NOINV"] # [inline (always)] pub fn is_octl_01_ccpoinv_noinv (& self) -> bool { * self == OCTL_01_CCPOINV_A :: OCTL_01_CCPOINV_NOINV } # [doc = "INV"] # [inline (always)] pub fn is_octl_01_ccpoinv_inv (& self) -> bool { * self == OCTL_01_CCPOINV_A :: OCTL_01_CCPOINV_INV } } # [doc = "Field `OCTL_01_CCPOINV` writer - CCP Output Invert The output as selected by CCPO is conditionally inverted."] pub type OCTL_01_CCPOINV_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , OCTL_01_CCPOINV_A > ; impl < 'a , REG , const O : u8 > OCTL_01_CCPOINV_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NOINV"] # [inline (always)] pub fn octl_01_ccpoinv_noinv (self) -> & 'a mut crate :: W < REG > { self . variant (OCTL_01_CCPOINV_A :: OCTL_01_CCPOINV_NOINV) } # [doc = "INV"] # [inline (always)] pub fn octl_01_ccpoinv_inv (self) -> & 'a mut crate :: W < REG > { self . variant (OCTL_01_CCPOINV_A :: OCTL_01_CCPOINV_INV) } } # [doc = "Field `OCTL_01_CCPIV` reader - CCP Initial Value This bit specifies the logical value put on the signal generator state while the counter is disabled (CTRCTL.EN == 0)."] pub type OCTL_01_CCPIV_R = crate :: BitReader < OCTL_01_CCPIV_A > ; # [doc = "CCP Initial Value This bit specifies the logical value put on the signal generator state while the counter is disabled (CTRCTL.EN == 0).\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum OCTL_01_CCPIV_A { # [doc = "0: LOW"] OCTL_01_CCPIV_LOW = 0 , # [doc = "1: HIGH"] OCTL_01_CCPIV_HIGH = 1 , } impl From < OCTL_01_CCPIV_A > for bool { # [inline (always)] fn from (variant : OCTL_01_CCPIV_A) -> Self { variant as u8 != 0 } } impl OCTL_01_CCPIV_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> OCTL_01_CCPIV_A { match self . bits { false => OCTL_01_CCPIV_A :: OCTL_01_CCPIV_LOW , true => OCTL_01_CCPIV_A :: OCTL_01_CCPIV_HIGH , } } # [doc = "LOW"] # [inline (always)] pub fn is_octl_01_ccpiv_low (& self) -> bool { * self == OCTL_01_CCPIV_A :: OCTL_01_CCPIV_LOW } # [doc = "HIGH"] # [inline (always)] pub fn is_octl_01_ccpiv_high (& self) -> bool { * self == OCTL_01_CCPIV_A :: OCTL_01_CCPIV_HIGH } } # [doc = "Field `OCTL_01_CCPIV` writer - CCP Initial Value This bit specifies the logical value put on the signal generator state while the counter is disabled (CTRCTL.EN == 0)."] pub type OCTL_01_CCPIV_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , OCTL_01_CCPIV_A > ; impl < 'a , REG , const O : u8 > OCTL_01_CCPIV_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "LOW"] # [inline (always)] pub fn octl_01_ccpiv_low (self) -> & 'a mut crate :: W < REG > { self . variant (OCTL_01_CCPIV_A :: OCTL_01_CCPIV_LOW) } # [doc = "HIGH"] # [inline (always)] pub fn octl_01_ccpiv_high (self) -> & 'a mut crate :: W < REG > { self . variant (OCTL_01_CCPIV_A :: OCTL_01_CCPIV_HIGH) } } impl R { # [doc = "Bits 0:3 - CCP Output Source"] # [inline (always)] pub fn octl_01_ccpo (& self) -> OCTL_01_CCPO_R { OCTL_01_CCPO_R :: new ((self . bits & 0x0f) as u8) } # [doc = "Bit 4 - CCP Output Invert The output as selected by CCPO is conditionally inverted."] # [inline (always)] pub fn octl_01_ccpoinv (& self) -> OCTL_01_CCPOINV_R { OCTL_01_CCPOINV_R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - CCP Initial Value This bit specifies the logical value put on the signal generator state while the counter is disabled (CTRCTL.EN == 0)."] # [inline (always)] pub fn octl_01_ccpiv (& self) -> OCTL_01_CCPIV_R { OCTL_01_CCPIV_R :: new (((self . bits >> 5) & 1) != 0) } } impl W { # [doc = "Bits 0:3 - CCP Output Source"] # [inline (always)] # [must_use] pub fn octl_01_ccpo (& mut self) -> OCTL_01_CCPO_W <'_, OCTL_01_SPEC , 0 > { OCTL_01_CCPO_W :: new (self) } # [doc = "Bit 4 - CCP Output Invert The output as selected by CCPO is conditionally inverted."] # [inline (always)] # [must_use] pub fn octl_01_ccpoinv (& mut self) -> OCTL_01_CCPOINV_W < OCTL_01_SPEC , 4 > { OCTL_01_CCPOINV_W :: new (self) } # [doc = "Bit 5 - CCP Initial Value This bit specifies the logical value put on the signal generator state while the counter is disabled (CTRCTL.EN == 0)."] # [inline (always)] # [must_use] pub fn octl_01_ccpiv (& mut self) -> OCTL_01_CCPIV_W < OCTL_01_SPEC , 5 > { OCTL_01_CCPIV_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "CCP Output Control Registers\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`octl_01::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`octl_01::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct OCTL_01_SPEC ; impl crate :: RegisterSpec for OCTL_01_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`octl_01::R`](R) reader structure"] impl crate :: Readable for OCTL_01_SPEC { } # [doc = "`write(|w| ..)` method takes [`octl_01::W`](W) writer structure"] impl crate :: Writable for OCTL_01_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets OCTL_01[%s] [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/i2c0/sctr.rs:1:25037 [INFO] [stdout] | [INFO] [stdout] 1 | ... sctr_txempty_on_treq (& mut self) -> SCTR_TXEMPTY_ON_TREQ_W < SCTR_SPEC , 3 > { SCTR_TXEMPTY_ON_TREQ_W :: new (self) } # [doc = "Bit ... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `SCTR` reader"] pub type R = crate :: R < SCTR_SPEC > ; # [doc = "Register `SCTR` writer"] pub type W = crate :: W < SCTR_SPEC > ; # [doc = "Field `SCTR_ACTIVE` reader - Device Active. Setting this bit enables the slave functionality."] pub type SCTR_ACTIVE_R = crate :: BitReader < SCTR_ACTIVE_A > ; # [doc = "Device Active. Setting this bit enables the slave functionality.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum SCTR_ACTIVE_A { # [doc = "0: DISABLE"] SCTR_ACTIVE_DISABLE = 0 , # [doc = "1: ENABLE"] SCTR_ACTIVE_ENABLE = 1 , } impl From < SCTR_ACTIVE_A > for bool { # [inline (always)] fn from (variant : SCTR_ACTIVE_A) -> Self { variant as u8 != 0 } } impl SCTR_ACTIVE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> SCTR_ACTIVE_A { match self . bits { false => SCTR_ACTIVE_A :: SCTR_ACTIVE_DISABLE , true => SCTR_ACTIVE_A :: SCTR_ACTIVE_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_sctr_active_disable (& self) -> bool { * self == SCTR_ACTIVE_A :: SCTR_ACTIVE_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_sctr_active_enable (& self) -> bool { * self == SCTR_ACTIVE_A :: SCTR_ACTIVE_ENABLE } } # [doc = "Field `SCTR_ACTIVE` writer - Device Active. Setting this bit enables the slave functionality."] pub type SCTR_ACTIVE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , SCTR_ACTIVE_A > ; impl < 'a , REG , const O : u8 > SCTR_ACTIVE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn sctr_active_disable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_ACTIVE_A :: SCTR_ACTIVE_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn sctr_active_enable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_ACTIVE_A :: SCTR_ACTIVE_ENABLE) } } # [doc = "Field `SCTR_GENCALL` reader - General call response enable. This bit is only available in UCBxI2COA0. Modify only when UCSWRST = 1. 0b = Do not respond to a general call 1b = Respond to a general call"] pub type SCTR_GENCALL_R = crate :: BitReader < SCTR_GENCALL_A > ; # [doc = "General call response enable. This bit is only available in UCBxI2COA0. Modify only when UCSWRST = 1. 0b = Do not respond to a general call 1b = Respond to a general call\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum SCTR_GENCALL_A { # [doc = "0: DISABLE"] SCTR_GENCALL_DISABLE = 0 , # [doc = "1: ENABLE"] SCTR_GENCALL_ENABLE = 1 , } impl From < SCTR_GENCALL_A > for bool { # [inline (always)] fn from (variant : SCTR_GENCALL_A) -> Self { variant as u8 != 0 } } impl SCTR_GENCALL_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> SCTR_GENCALL_A { match self . bits { false => SCTR_GENCALL_A :: SCTR_GENCALL_DISABLE , true => SCTR_GENCALL_A :: SCTR_GENCALL_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_sctr_gencall_disable (& self) -> bool { * self == SCTR_GENCALL_A :: SCTR_GENCALL_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_sctr_gencall_enable (& self) -> bool { * self == SCTR_GENCALL_A :: SCTR_GENCALL_ENABLE } } # [doc = "Field `SCTR_GENCALL` writer - General call response enable. This bit is only available in UCBxI2COA0. Modify only when UCSWRST = 1. 0b = Do not respond to a general call 1b = Respond to a general call"] pub type SCTR_GENCALL_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , SCTR_GENCALL_A > ; impl < 'a , REG , const O : u8 > SCTR_GENCALL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn sctr_gencall_disable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_GENCALL_A :: SCTR_GENCALL_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn sctr_gencall_enable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_GENCALL_A :: SCTR_GENCALL_ENABLE) } } # [doc = "Field `SCTR_SCLKSTRETCH` reader - Slave Clock Stretch Enable"] pub type SCTR_SCLKSTRETCH_R = crate :: BitReader < SCTR_SCLKSTRETCH_A > ; # [doc = "Slave Clock Stretch Enable\n\nValue on reset: 1"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum SCTR_SCLKSTRETCH_A { # [doc = "0: DISABLE"] SCTR_SCLKSTRETCH_DISABLE = 0 , # [doc = "1: ENABLE"] SCTR_SCLKSTRETCH_ENABLE = 1 , } impl From < SCTR_SCLKSTRETCH_A > for bool { # [inline (always)] fn from (variant : SCTR_SCLKSTRETCH_A) -> Self { variant as u8 != 0 } } impl SCTR_SCLKSTRETCH_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> SCTR_SCLKSTRETCH_A { match self . bits { false => SCTR_SCLKSTRETCH_A :: SCTR_SCLKSTRETCH_DISABLE , true => SCTR_SCLKSTRETCH_A :: SCTR_SCLKSTRETCH_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_sctr_sclkstretch_disable (& self) -> bool { * self == SCTR_SCLKSTRETCH_A :: SCTR_SCLKSTRETCH_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_sctr_sclkstretch_enable (& self) -> bool { * self == SCTR_SCLKSTRETCH_A :: SCTR_SCLKSTRETCH_ENABLE } } # [doc = "Field `SCTR_SCLKSTRETCH` writer - Slave Clock Stretch Enable"] pub type SCTR_SCLKSTRETCH_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , SCTR_SCLKSTRETCH_A > ; impl < 'a , REG , const O : u8 > SCTR_SCLKSTRETCH_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn sctr_sclkstretch_disable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_SCLKSTRETCH_A :: SCTR_SCLKSTRETCH_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn sctr_sclkstretch_enable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_SCLKSTRETCH_A :: SCTR_SCLKSTRETCH_ENABLE) } } # [doc = "Field `SCTR_TXEMPTY_ON_TREQ` reader - Tx Empty Interrupt on TREQ"] pub type SCTR_TXEMPTY_ON_TREQ_R = crate :: BitReader < SCTR_TXEMPTY_ON_TREQ_A > ; # [doc = "Tx Empty Interrupt on TREQ\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum SCTR_TXEMPTY_ON_TREQ_A { # [doc = "0: DISABLE"] SCTR_TXEMPTY_ON_TREQ_DISABLE = 0 , # [doc = "1: ENABLE"] SCTR_TXEMPTY_ON_TREQ_ENABLE = 1 , } impl From < SCTR_TXEMPTY_ON_TREQ_A > for bool { # [inline (always)] fn from (variant : SCTR_TXEMPTY_ON_TREQ_A) -> Self { variant as u8 != 0 } } impl SCTR_TXEMPTY_ON_TREQ_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> SCTR_TXEMPTY_ON_TREQ_A { match self . bits { false => SCTR_TXEMPTY_ON_TREQ_A :: SCTR_TXEMPTY_ON_TREQ_DISABLE , true => SCTR_TXEMPTY_ON_TREQ_A :: SCTR_TXEMPTY_ON_TREQ_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_sctr_txempty_on_treq_disable (& self) -> bool { * self == SCTR_TXEMPTY_ON_TREQ_A :: SCTR_TXEMPTY_ON_TREQ_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_sctr_txempty_on_treq_enable (& self) -> bool { * self == SCTR_TXEMPTY_ON_TREQ_A :: SCTR_TXEMPTY_ON_TREQ_ENABLE } } # [doc = "Field `SCTR_TXEMPTY_ON_TREQ` writer - Tx Empty Interrupt on TREQ"] pub type SCTR_TXEMPTY_ON_TREQ_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , SCTR_TXEMPTY_ON_TREQ_A > ; impl < 'a , REG , const O : u8 > SCTR_TXEMPTY_ON_TREQ_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn sctr_txempty_on_treq_disable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_TXEMPTY_ON_TREQ_A :: SCTR_TXEMPTY_ON_TREQ_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn sctr_txempty_on_treq_enable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_TXEMPTY_ON_TREQ_A :: SCTR_TXEMPTY_ON_TREQ_ENABLE) } } # [doc = "Field `SCTR_TXTRIG_TXMODE` reader - Tx Trigger when slave FSM is in Tx Mode"] pub type SCTR_TXTRIG_TXMODE_R = crate :: BitReader < SCTR_TXTRIG_TXMODE_A > ; # [doc = "Tx Trigger when slave FSM is in Tx Mode\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum SCTR_TXTRIG_TXMODE_A { # [doc = "0: DISABLE"] SCTR_TXTRIG_TXMODE_DISABLE = 0 , # [doc = "1: ENABLE"] SCTR_TXTRIG_TXMODE_ENABLE = 1 , } impl From < SCTR_TXTRIG_TXMODE_A > for bool { # [inline (always)] fn from (variant : SCTR_TXTRIG_TXMODE_A) -> Self { variant as u8 != 0 } } impl SCTR_TXTRIG_TXMODE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> SCTR_TXTRIG_TXMODE_A { match self . bits { false => SCTR_TXTRIG_TXMODE_A :: SCTR_TXTRIG_TXMODE_DISABLE , true => SCTR_TXTRIG_TXMODE_A :: SCTR_TXTRIG_TXMODE_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_sctr_txtrig_txmode_disable (& self) -> bool { * self == SCTR_TXTRIG_TXMODE_A :: SCTR_TXTRIG_TXMODE_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_sctr_txtrig_txmode_enable (& self) -> bool { * self == SCTR_TXTRIG_TXMODE_A :: SCTR_TXTRIG_TXMODE_ENABLE } } # [doc = "Field `SCTR_TXTRIG_TXMODE` writer - Tx Trigger when slave FSM is in Tx Mode"] pub type SCTR_TXTRIG_TXMODE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , SCTR_TXTRIG_TXMODE_A > ; impl < 'a , REG , const O : u8 > SCTR_TXTRIG_TXMODE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn sctr_txtrig_txmode_disable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_TXTRIG_TXMODE_A :: SCTR_TXTRIG_TXMODE_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn sctr_txtrig_txmode_enable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_TXTRIG_TXMODE_A :: SCTR_TXTRIG_TXMODE_ENABLE) } } # [doc = "Field `SCTR_TXWAIT_STALE_TXFIFO` reader - Tx transfer waits when stale data in Tx FIFO. This prevents stale bytes left in the TX FIFO from automatically being sent on the next I2C packet. Note: this should be used with TXEMPTY_ON_TREQ set to prevent the Slave State Machine from waiting for TX FIFO data without an interrupt notification when the FIFO data is stale."] pub type SCTR_TXWAIT_STALE_TXFIFO_R = crate :: BitReader < SCTR_TXWAIT_STALE_TXFIFO_A > ; # [doc = "Tx transfer waits when stale data in Tx FIFO. This prevents stale bytes left in the TX FIFO from automatically being sent on the next I2C packet. Note: this should be used with TXEMPTY_ON_TREQ set to prevent the Slave State Machine from waiting for TX FIFO data without an interrupt notification when the FIFO data is stale.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum SCTR_TXWAIT_STALE_TXFIFO_A { # [doc = "0: DISABLE"] SCTR_TXWAIT_STALE_TXFIFO_DISABLE = 0 , # [doc = "1: ENABLE"] SCTR_TXWAIT_STALE_TXFIFO_ENABLE = 1 , } impl From < SCTR_TXWAIT_STALE_TXFIFO_A > for bool { # [inline (always)] fn from (variant : SCTR_TXWAIT_STALE_TXFIFO_A) -> Self { variant as u8 != 0 } } impl SCTR_TXWAIT_STALE_TXFIFO_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> SCTR_TXWAIT_STALE_TXFIFO_A { match self . bits { false => SCTR_TXWAIT_STALE_TXFIFO_A :: SCTR_TXWAIT_STALE_TXFIFO_DISABLE , true => SCTR_TXWAIT_STALE_TXFIFO_A :: SCTR_TXWAIT_STALE_TXFIFO_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_sctr_txwait_stale_txfifo_disable (& self) -> bool { * self == SCTR_TXWAIT_STALE_TXFIFO_A :: SCTR_TXWAIT_STALE_TXFIFO_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_sctr_txwait_stale_txfifo_enable (& self) -> bool { * self == SCTR_TXWAIT_STALE_TXFIFO_A :: SCTR_TXWAIT_STALE_TXFIFO_ENABLE } } # [doc = "Field `SCTR_TXWAIT_STALE_TXFIFO` writer - Tx transfer waits when stale data in Tx FIFO. This prevents stale bytes left in the TX FIFO from automatically being sent on the next I2C packet. Note: this should be used with TXEMPTY_ON_TREQ set to prevent the Slave State Machine from waiting for TX FIFO data without an interrupt notification when the FIFO data is stale."] pub type SCTR_TXWAIT_STALE_TXFIFO_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , SCTR_TXWAIT_STALE_TXFIFO_A > ; impl < 'a , REG , const O : u8 > SCTR_TXWAIT_STALE_TXFIFO_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn sctr_txwait_stale_txfifo_disable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_TXWAIT_STALE_TXFIFO_A :: SCTR_TXWAIT_STALE_TXFIFO_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn sctr_txwait_stale_txfifo_enable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_TXWAIT_STALE_TXFIFO_A :: SCTR_TXWAIT_STALE_TXFIFO_ENABLE) } } # [doc = "Field `SCTR_RXFULL_ON_RREQ` reader - Rx full interrupt generated on RREQ condition as indicated in SSR"] pub type SCTR_RXFULL_ON_RREQ_R = crate :: BitReader < SCTR_RXFULL_ON_RREQ_A > ; # [doc = "Rx full interrupt generated on RREQ condition as indicated in SSR\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum SCTR_RXFULL_ON_RREQ_A { # [doc = "0: DISABLE"] SCTR_RXFULL_ON_RREQ_DISABLE = 0 , # [doc = "1: ENABLE"] SCTR_RXFULL_ON_RREQ_ENABLE = 1 , } impl From < SCTR_RXFULL_ON_RREQ_A > for bool { # [inline (always)] fn from (variant : SCTR_RXFULL_ON_RREQ_A) -> Self { variant as u8 != 0 } } impl SCTR_RXFULL_ON_RREQ_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> SCTR_RXFULL_ON_RREQ_A { match self . bits { false => SCTR_RXFULL_ON_RREQ_A :: SCTR_RXFULL_ON_RREQ_DISABLE , true => SCTR_RXFULL_ON_RREQ_A :: SCTR_RXFULL_ON_RREQ_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_sctr_rxfull_on_rreq_disable (& self) -> bool { * self == SCTR_RXFULL_ON_RREQ_A :: SCTR_RXFULL_ON_RREQ_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_sctr_rxfull_on_rreq_enable (& self) -> bool { * self == SCTR_RXFULL_ON_RREQ_A :: SCTR_RXFULL_ON_RREQ_ENABLE } } # [doc = "Field `SCTR_RXFULL_ON_RREQ` writer - Rx full interrupt generated on RREQ condition as indicated in SSR"] pub type SCTR_RXFULL_ON_RREQ_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , SCTR_RXFULL_ON_RREQ_A > ; impl < 'a , REG , const O : u8 > SCTR_RXFULL_ON_RREQ_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn sctr_rxfull_on_rreq_disable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_RXFULL_ON_RREQ_A :: SCTR_RXFULL_ON_RREQ_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn sctr_rxfull_on_rreq_enable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_RXFULL_ON_RREQ_A :: SCTR_RXFULL_ON_RREQ_ENABLE) } } # [doc = "Field `SCTR_EN_DEFHOSTADR` reader - Enable Default Host Address"] pub type SCTR_EN_DEFHOSTADR_R = crate :: BitReader < SCTR_EN_DEFHOSTADR_A > ; # [doc = "Enable Default Host Address\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum SCTR_EN_DEFHOSTADR_A { # [doc = "0: DISABLE"] SCTR_EN_DEFHOSTADR_DISABLE = 0 , # [doc = "1: ENABLE"] SCTR_EN_DEFHOSTADR_ENABLE = 1 , } impl From < SCTR_EN_DEFHOSTADR_A > for bool { # [inline (always)] fn from (variant : SCTR_EN_DEFHOSTADR_A) -> Self { variant as u8 != 0 } } impl SCTR_EN_DEFHOSTADR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> SCTR_EN_DEFHOSTADR_A { match self . bits { false => SCTR_EN_DEFHOSTADR_A :: SCTR_EN_DEFHOSTADR_DISABLE , true => SCTR_EN_DEFHOSTADR_A :: SCTR_EN_DEFHOSTADR_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_sctr_en_defhostadr_disable (& self) -> bool { * self == SCTR_EN_DEFHOSTADR_A :: SCTR_EN_DEFHOSTADR_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_sctr_en_defhostadr_enable (& self) -> bool { * self == SCTR_EN_DEFHOSTADR_A :: SCTR_EN_DEFHOSTADR_ENABLE } } # [doc = "Field `SCTR_EN_DEFHOSTADR` writer - Enable Default Host Address"] pub type SCTR_EN_DEFHOSTADR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , SCTR_EN_DEFHOSTADR_A > ; impl < 'a , REG , const O : u8 > SCTR_EN_DEFHOSTADR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn sctr_en_defhostadr_disable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_EN_DEFHOSTADR_A :: SCTR_EN_DEFHOSTADR_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn sctr_en_defhostadr_enable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_EN_DEFHOSTADR_A :: SCTR_EN_DEFHOSTADR_ENABLE) } } # [doc = "Field `SCTR_EN_ALRESPADR` reader - Enable Alert Response Address"] pub type SCTR_EN_ALRESPADR_R = crate :: BitReader < SCTR_EN_ALRESPADR_A > ; # [doc = "Enable Alert Response Address\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum SCTR_EN_ALRESPADR_A { # [doc = "0: DISABLE"] SCTR_EN_ALRESPADR_DISABLE = 0 , # [doc = "1: ENABLE"] SCTR_EN_ALRESPADR_ENABLE = 1 , } impl From < SCTR_EN_ALRESPADR_A > for bool { # [inline (always)] fn from (variant : SCTR_EN_ALRESPADR_A) -> Self { variant as u8 != 0 } } impl SCTR_EN_ALRESPADR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> SCTR_EN_ALRESPADR_A { match self . bits { false => SCTR_EN_ALRESPADR_A :: SCTR_EN_ALRESPADR_DISABLE , true => SCTR_EN_ALRESPADR_A :: SCTR_EN_ALRESPADR_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_sctr_en_alrespadr_disable (& self) -> bool { * self == SCTR_EN_ALRESPADR_A :: SCTR_EN_ALRESPADR_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_sctr_en_alrespadr_enable (& self) -> bool { * self == SCTR_EN_ALRESPADR_A :: SCTR_EN_ALRESPADR_ENABLE } } # [doc = "Field `SCTR_EN_ALRESPADR` writer - Enable Alert Response Address"] pub type SCTR_EN_ALRESPADR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , SCTR_EN_ALRESPADR_A > ; impl < 'a , REG , const O : u8 > SCTR_EN_ALRESPADR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn sctr_en_alrespadr_disable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_EN_ALRESPADR_A :: SCTR_EN_ALRESPADR_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn sctr_en_alrespadr_enable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_EN_ALRESPADR_A :: SCTR_EN_ALRESPADR_ENABLE) } } # [doc = "Field `SCTR_EN_DEFDEVADR` reader - Enable Deault device address"] pub type SCTR_EN_DEFDEVADR_R = crate :: BitReader < SCTR_EN_DEFDEVADR_A > ; # [doc = "Enable Deault device address\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum SCTR_EN_DEFDEVADR_A { # [doc = "0: DISABLE"] SCTR_EN_DEFDEVADR_DISABLE = 0 , # [doc = "1: ENABLE"] SCTR_EN_DEFDEVADR_ENABLE = 1 , } impl From < SCTR_EN_DEFDEVADR_A > for bool { # [inline (always)] fn from (variant : SCTR_EN_DEFDEVADR_A) -> Self { variant as u8 != 0 } } impl SCTR_EN_DEFDEVADR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> SCTR_EN_DEFDEVADR_A { match self . bits { false => SCTR_EN_DEFDEVADR_A :: SCTR_EN_DEFDEVADR_DISABLE , true => SCTR_EN_DEFDEVADR_A :: SCTR_EN_DEFDEVADR_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_sctr_en_defdevadr_disable (& self) -> bool { * self == SCTR_EN_DEFDEVADR_A :: SCTR_EN_DEFDEVADR_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_sctr_en_defdevadr_enable (& self) -> bool { * self == SCTR_EN_DEFDEVADR_A :: SCTR_EN_DEFDEVADR_ENABLE } } # [doc = "Field `SCTR_EN_DEFDEVADR` writer - Enable Deault device address"] pub type SCTR_EN_DEFDEVADR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , SCTR_EN_DEFDEVADR_A > ; impl < 'a , REG , const O : u8 > SCTR_EN_DEFDEVADR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn sctr_en_defdevadr_disable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_EN_DEFDEVADR_A :: SCTR_EN_DEFDEVADR_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn sctr_en_defdevadr_enable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_EN_DEFDEVADR_A :: SCTR_EN_DEFDEVADR_ENABLE) } } # [doc = "Field `SCTR_SWUEN` reader - Slave Wakeup Enable"] pub type SCTR_SWUEN_R = crate :: BitReader < SCTR_SWUEN_A > ; # [doc = "Slave Wakeup Enable\n\nValue on reset: 1"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum SCTR_SWUEN_A { # [doc = "0: DISABLE"] SCTR_SWUEN_DISABLE = 0 , # [doc = "1: ENABLE"] SCTR_SWUEN_ENABLE = 1 , } impl From < SCTR_SWUEN_A > for bool { # [inline (always)] fn from (variant : SCTR_SWUEN_A) -> Self { variant as u8 != 0 } } impl SCTR_SWUEN_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> SCTR_SWUEN_A { match self . bits { false => SCTR_SWUEN_A :: SCTR_SWUEN_DISABLE , true => SCTR_SWUEN_A :: SCTR_SWUEN_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_sctr_swuen_disable (& self) -> bool { * self == SCTR_SWUEN_A :: SCTR_SWUEN_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_sctr_swuen_enable (& self) -> bool { * self == SCTR_SWUEN_A :: SCTR_SWUEN_ENABLE } } # [doc = "Field `SCTR_SWUEN` writer - Slave Wakeup Enable"] pub type SCTR_SWUEN_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , SCTR_SWUEN_A > ; impl < 'a , REG , const O : u8 > SCTR_SWUEN_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn sctr_swuen_disable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_SWUEN_A :: SCTR_SWUEN_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn sctr_swuen_enable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_SWUEN_A :: SCTR_SWUEN_ENABLE) } } impl R { # [doc = "Bit 0 - Device Active. Setting this bit enables the slave functionality."] # [inline (always)] pub fn sctr_active (& self) -> SCTR_ACTIVE_R { SCTR_ACTIVE_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - General call response enable. This bit is only available in UCBxI2COA0. Modify only when UCSWRST = 1. 0b = Do not respond to a general call 1b = Respond to a general call"] # [inline (always)] pub fn sctr_gencall (& self) -> SCTR_GENCALL_R { SCTR_GENCALL_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - Slave Clock Stretch Enable"] # [inline (always)] pub fn sctr_sclkstretch (& self) -> SCTR_SCLKSTRETCH_R { SCTR_SCLKSTRETCH_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - Tx Empty Interrupt on TREQ"] # [inline (always)] pub fn sctr_txempty_on_treq (& self) -> SCTR_TXEMPTY_ON_TREQ_R { SCTR_TXEMPTY_ON_TREQ_R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - Tx Trigger when slave FSM is in Tx Mode"] # [inline (always)] pub fn sctr_txtrig_txmode (& self) -> SCTR_TXTRIG_TXMODE_R { SCTR_TXTRIG_TXMODE_R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - Tx transfer waits when stale data in Tx FIFO. This prevents stale bytes left in the TX FIFO from automatically being sent on the next I2C packet. Note: this should be used with TXEMPTY_ON_TREQ set to prevent the Slave State Machine from waiting for TX FIFO data without an interrupt notification when the FIFO data is stale."] # [inline (always)] pub fn sctr_txwait_stale_txfifo (& self) -> SCTR_TXWAIT_STALE_TXFIFO_R { SCTR_TXWAIT_STALE_TXFIFO_R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - Rx full interrupt generated on RREQ condition as indicated in SSR"] # [inline (always)] pub fn sctr_rxfull_on_rreq (& self) -> SCTR_RXFULL_ON_RREQ_R { SCTR_RXFULL_ON_RREQ_R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - Enable Default Host Address"] # [inline (always)] pub fn sctr_en_defhostadr (& self) -> SCTR_EN_DEFHOSTADR_R { SCTR_EN_DEFHOSTADR_R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - Enable Alert Response Address"] # [inline (always)] pub fn sctr_en_alrespadr (& self) -> SCTR_EN_ALRESPADR_R { SCTR_EN_ALRESPADR_R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - Enable Deault device address"] # [inline (always)] pub fn sctr_en_defdevadr (& self) -> SCTR_EN_DEFDEVADR_R { SCTR_EN_DEFDEVADR_R :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - Slave Wakeup Enable"] # [inline (always)] pub fn sctr_swuen (& self) -> SCTR_SWUEN_R { SCTR_SWUEN_R :: new (((self . bits >> 10) & 1) != 0) } } impl W { # [doc = "Bit 0 - Device Active. Setting this bit enables the slave functionality."] # [inline (always)] # [must_use] pub fn sctr_active (& mut self) -> SCTR_ACTIVE_W < SCTR_SPEC , 0 > { SCTR_ACTIVE_W :: new (self) } # [doc = "Bit 1 - General call response enable. This bit is only available in UCBxI2COA0. Modify only when UCSWRST = 1. 0b = Do not respond to a general call 1b = Respond to a general call"] # [inline (always)] # [must_use] pub fn sctr_gencall (& mut self) -> SCTR_GENCALL_W < SCTR_SPEC , 1 > { SCTR_GENCALL_W :: new (self) } # [doc = "Bit 2 - Slave Clock Stretch Enable"] # [inline (always)] # [must_use] pub fn sctr_sclkstretch (& mut self) -> SCTR_SCLKSTRETCH_W < SCTR_SPEC , 2 > { SCTR_SCLKSTRETCH_W :: new (self) } # [doc = "Bit 3 - Tx Empty Interrupt on TREQ"] # [inline (always)] # [must_use] pub fn sctr_txempty_on_treq (& mut self) -> SCTR_TXEMPTY_ON_TREQ_W <'_, SCTR_SPEC , 3 > { SCTR_TXEMPTY_ON_TREQ_W :: new (self) } # [doc = "Bit 4 - Tx Trigger when slave FSM is in Tx Mode"] # [inline (always)] # [must_use] pub fn sctr_txtrig_txmode (& mut self) -> SCTR_TXTRIG_TXMODE_W < SCTR_SPEC , 4 > { SCTR_TXTRIG_TXMODE_W :: new (self) } # [doc = "Bit 5 - Tx transfer waits when stale data in Tx FIFO. This prevents stale bytes left in the TX FIFO from automatically being sent on the next I2C packet. Note: this should be used with TXEMPTY_ON_TREQ set to prevent the Slave State Machine from waiting for TX FIFO data without an interrupt notification when the FIFO data is stale."] # [inline (always)] # [must_use] pub fn sctr_txwait_stale_txfifo (& mut self) -> SCTR_TXWAIT_STALE_TXFIFO_W < SCTR_SPEC , 5 > { SCTR_TXWAIT_STALE_TXFIFO_W :: new (self) } # [doc = "Bit 6 - Rx full interrupt generated on RREQ condition as indicated in SSR"] # [inline (always)] # [must_use] pub fn sctr_rxfull_on_rreq (& mut self) -> SCTR_RXFULL_ON_RREQ_W < SCTR_SPEC , 6 > { SCTR_RXFULL_ON_RREQ_W :: new (self) } # [doc = "Bit 7 - Enable Default Host Address"] # [inline (always)] # [must_use] pub fn sctr_en_defhostadr (& mut self) -> SCTR_EN_DEFHOSTADR_W < SCTR_SPEC , 7 > { SCTR_EN_DEFHOSTADR_W :: new (self) } # [doc = "Bit 8 - Enable Alert Response Address"] # [inline (always)] # [must_use] pub fn sctr_en_alrespadr (& mut self) -> SCTR_EN_ALRESPADR_W < SCTR_SPEC , 8 > { SCTR_EN_ALRESPADR_W :: new (self) } # [doc = "Bit 9 - Enable Deault device address"] # [inline (always)] # [must_use] pub fn sctr_en_defdevadr (& mut self) -> SCTR_EN_DEFDEVADR_W < SCTR_SPEC , 9 > { SCTR_EN_DEFDEVADR_W :: new (self) } # [doc = "Bit 10 - Slave Wakeup Enable"] # [inline (always)] # [must_use] pub fn sctr_swuen (& mut self) -> SCTR_SWUEN_W < SCTR_SPEC , 10 > { SCTR_SWUEN_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "I2C Slave Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sctr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sctr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct SCTR_SPEC ; impl crate :: RegisterSpec for SCTR_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`sctr::R`](R) reader structure"] impl crate :: Readable for SCTR_SPEC { } # [doc = "`write(|w| ..)` method takes [`sctr::W`](W) writer structure"] impl crate :: Writable for SCTR_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets SCTR to value 0x0404"] impl crate :: Resettable for SCTR_SPEC { const RESET_VALUE : Self :: Ux = 0x0404 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/i2c1/gfctl.rs:1:13513 [INFO] [stdout] | [INFO] [stdout] 1 | ..._use] pub fn gfctl_chain (& mut self) -> GFCTL_CHAIN_W < GFCTL_SPEC , 11 > { GFCTL_CHAIN_W :: new (self) } # [doc = r" Writes raw bits... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `GFCTL` reader"] pub type R = crate :: R < GFCTL_SPEC > ; # [doc = "Register `GFCTL` writer"] pub type W = crate :: W < GFCTL_SPEC > ; # [doc = "Field `GFCTL_DGFSEL` reader - Glitch Suppression Pulse Width This field controls the pulse width select for glitch suppression on the SCL and SDA lines. The following values are the glitch suppression values in terms of functional clocks. (Core Domain only)"] pub type GFCTL_DGFSEL_R = crate :: FieldReader < GFCTL_DGFSEL_A > ; # [doc = "Glitch Suppression Pulse Width This field controls the pulse width select for glitch suppression on the SCL and SDA lines. The following values are the glitch suppression values in terms of functional clocks. (Core Domain only)\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum GFCTL_DGFSEL_A { # [doc = "0: DISABLED"] GFCTL_DGFSEL_DISABLED = 0 , # [doc = "1: CLK_1"] GFCTL_DGFSEL_CLK_1 = 1 , # [doc = "2: CLK_2"] GFCTL_DGFSEL_CLK_2 = 2 , # [doc = "3: CLK_3"] GFCTL_DGFSEL_CLK_3 = 3 , # [doc = "4: CLK_4"] GFCTL_DGFSEL_CLK_4 = 4 , # [doc = "5: CLK_8"] GFCTL_DGFSEL_CLK_8 = 5 , # [doc = "6: CLK_16"] GFCTL_DGFSEL_CLK_16 = 6 , # [doc = "7: CLK_31"] GFCTL_DGFSEL_CLK_31 = 7 , } impl From < GFCTL_DGFSEL_A > for u8 { # [inline (always)] fn from (variant : GFCTL_DGFSEL_A) -> Self { variant as _ } } impl crate :: FieldSpec for GFCTL_DGFSEL_A { type Ux = u8 ; } impl GFCTL_DGFSEL_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> GFCTL_DGFSEL_A { match self . bits { 0 => GFCTL_DGFSEL_A :: GFCTL_DGFSEL_DISABLED , 1 => GFCTL_DGFSEL_A :: GFCTL_DGFSEL_CLK_1 , 2 => GFCTL_DGFSEL_A :: GFCTL_DGFSEL_CLK_2 , 3 => GFCTL_DGFSEL_A :: GFCTL_DGFSEL_CLK_3 , 4 => GFCTL_DGFSEL_A :: GFCTL_DGFSEL_CLK_4 , 5 => GFCTL_DGFSEL_A :: GFCTL_DGFSEL_CLK_8 , 6 => GFCTL_DGFSEL_A :: GFCTL_DGFSEL_CLK_16 , 7 => GFCTL_DGFSEL_A :: GFCTL_DGFSEL_CLK_31 , _ => unreachable ! () , } } # [doc = "DISABLED"] # [inline (always)] pub fn is_gfctl_dgfsel_disabled (& self) -> bool { * self == GFCTL_DGFSEL_A :: GFCTL_DGFSEL_DISABLED } # [doc = "CLK_1"] # [inline (always)] pub fn is_gfctl_dgfsel_clk_1 (& self) -> bool { * self == GFCTL_DGFSEL_A :: GFCTL_DGFSEL_CLK_1 } # [doc = "CLK_2"] # [inline (always)] pub fn is_gfctl_dgfsel_clk_2 (& self) -> bool { * self == GFCTL_DGFSEL_A :: GFCTL_DGFSEL_CLK_2 } # [doc = "CLK_3"] # [inline (always)] pub fn is_gfctl_dgfsel_clk_3 (& self) -> bool { * self == GFCTL_DGFSEL_A :: GFCTL_DGFSEL_CLK_3 } # [doc = "CLK_4"] # [inline (always)] pub fn is_gfctl_dgfsel_clk_4 (& self) -> bool { * self == GFCTL_DGFSEL_A :: GFCTL_DGFSEL_CLK_4 } # [doc = "CLK_8"] # [inline (always)] pub fn is_gfctl_dgfsel_clk_8 (& self) -> bool { * self == GFCTL_DGFSEL_A :: GFCTL_DGFSEL_CLK_8 } # [doc = "CLK_16"] # [inline (always)] pub fn is_gfctl_dgfsel_clk_16 (& self) -> bool { * self == GFCTL_DGFSEL_A :: GFCTL_DGFSEL_CLK_16 } # [doc = "CLK_31"] # [inline (always)] pub fn is_gfctl_dgfsel_clk_31 (& self) -> bool { * self == GFCTL_DGFSEL_A :: GFCTL_DGFSEL_CLK_31 } } # [doc = "Field `GFCTL_DGFSEL` writer - Glitch Suppression Pulse Width This field controls the pulse width select for glitch suppression on the SCL and SDA lines. The following values are the glitch suppression values in terms of functional clocks. (Core Domain only)"] pub type GFCTL_DGFSEL_W < 'a , REG , const O : u8 > = crate :: FieldWriterSafe < 'a , REG , 3 , O , GFCTL_DGFSEL_A > ; impl < 'a , REG , const O : u8 > GFCTL_DGFSEL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "DISABLED"] # [inline (always)] pub fn gfctl_dgfsel_disabled (self) -> & 'a mut crate :: W < REG > { self . variant (GFCTL_DGFSEL_A :: GFCTL_DGFSEL_DISABLED) } # [doc = "CLK_1"] # [inline (always)] pub fn gfctl_dgfsel_clk_1 (self) -> & 'a mut crate :: W < REG > { self . variant (GFCTL_DGFSEL_A :: GFCTL_DGFSEL_CLK_1) } # [doc = "CLK_2"] # [inline (always)] pub fn gfctl_dgfsel_clk_2 (self) -> & 'a mut crate :: W < REG > { self . variant (GFCTL_DGFSEL_A :: GFCTL_DGFSEL_CLK_2) } # [doc = "CLK_3"] # [inline (always)] pub fn gfctl_dgfsel_clk_3 (self) -> & 'a mut crate :: W < REG > { self . variant (GFCTL_DGFSEL_A :: GFCTL_DGFSEL_CLK_3) } # [doc = "CLK_4"] # [inline (always)] pub fn gfctl_dgfsel_clk_4 (self) -> & 'a mut crate :: W < REG > { self . variant (GFCTL_DGFSEL_A :: GFCTL_DGFSEL_CLK_4) } # [doc = "CLK_8"] # [inline (always)] pub fn gfctl_dgfsel_clk_8 (self) -> & 'a mut crate :: W < REG > { self . variant (GFCTL_DGFSEL_A :: GFCTL_DGFSEL_CLK_8) } # [doc = "CLK_16"] # [inline (always)] pub fn gfctl_dgfsel_clk_16 (self) -> & 'a mut crate :: W < REG > { self . variant (GFCTL_DGFSEL_A :: GFCTL_DGFSEL_CLK_16) } # [doc = "CLK_31"] # [inline (always)] pub fn gfctl_dgfsel_clk_31 (self) -> & 'a mut crate :: W < REG > { self . variant (GFCTL_DGFSEL_A :: GFCTL_DGFSEL_CLK_31) } } # [doc = "Field `GFCTL_AGFEN` reader - Analog Glitch Suppression Enable"] pub type GFCTL_AGFEN_R = crate :: BitReader < GFCTL_AGFEN_A > ; # [doc = "Analog Glitch Suppression Enable\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum GFCTL_AGFEN_A { # [doc = "0: DISABLE"] GFCTL_AGFEN_DISABLE = 0 , # [doc = "1: ENABLE"] GFCTL_AGFEN_ENABLE = 1 , } impl From < GFCTL_AGFEN_A > for bool { # [inline (always)] fn from (variant : GFCTL_AGFEN_A) -> Self { variant as u8 != 0 } } impl GFCTL_AGFEN_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> GFCTL_AGFEN_A { match self . bits { false => GFCTL_AGFEN_A :: GFCTL_AGFEN_DISABLE , true => GFCTL_AGFEN_A :: GFCTL_AGFEN_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_gfctl_agfen_disable (& self) -> bool { * self == GFCTL_AGFEN_A :: GFCTL_AGFEN_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_gfctl_agfen_enable (& self) -> bool { * self == GFCTL_AGFEN_A :: GFCTL_AGFEN_ENABLE } } # [doc = "Field `GFCTL_AGFEN` writer - Analog Glitch Suppression Enable"] pub type GFCTL_AGFEN_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , GFCTL_AGFEN_A > ; impl < 'a , REG , const O : u8 > GFCTL_AGFEN_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn gfctl_agfen_disable (self) -> & 'a mut crate :: W < REG > { self . variant (GFCTL_AGFEN_A :: GFCTL_AGFEN_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn gfctl_agfen_enable (self) -> & 'a mut crate :: W < REG > { self . variant (GFCTL_AGFEN_A :: GFCTL_AGFEN_ENABLE) } } # [doc = "Field `GFCTL_AGFSEL` reader - Analog Glitch Suppression Pulse Width This field controls the pulse width select for the analog glitch suppression on SCL and SDA lines. See device datasheet for exact values. (ULP I2C only)"] pub type GFCTL_AGFSEL_R = crate :: FieldReader < GFCTL_AGFSEL_A > ; # [doc = "Analog Glitch Suppression Pulse Width This field controls the pulse width select for the analog glitch suppression on SCL and SDA lines. See device datasheet for exact values. (ULP I2C only)\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum GFCTL_AGFSEL_A { # [doc = "0: AGLIT_5"] GFCTL_AGFSEL_AGLIT_5 = 0 , # [doc = "1: AGLIT_10"] GFCTL_AGFSEL_AGLIT_10 = 1 , # [doc = "2: AGLIT_25"] GFCTL_AGFSEL_AGLIT_25 = 2 , # [doc = "3: AGLIT_50"] GFCTL_AGFSEL_AGLIT_50 = 3 , } impl From < GFCTL_AGFSEL_A > for u8 { # [inline (always)] fn from (variant : GFCTL_AGFSEL_A) -> Self { variant as _ } } impl crate :: FieldSpec for GFCTL_AGFSEL_A { type Ux = u8 ; } impl GFCTL_AGFSEL_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> GFCTL_AGFSEL_A { match self . bits { 0 => GFCTL_AGFSEL_A :: GFCTL_AGFSEL_AGLIT_5 , 1 => GFCTL_AGFSEL_A :: GFCTL_AGFSEL_AGLIT_10 , 2 => GFCTL_AGFSEL_A :: GFCTL_AGFSEL_AGLIT_25 , 3 => GFCTL_AGFSEL_A :: GFCTL_AGFSEL_AGLIT_50 , _ => unreachable ! () , } } # [doc = "AGLIT_5"] # [inline (always)] pub fn is_gfctl_agfsel_aglit_5 (& self) -> bool { * self == GFCTL_AGFSEL_A :: GFCTL_AGFSEL_AGLIT_5 } # [doc = "AGLIT_10"] # [inline (always)] pub fn is_gfctl_agfsel_aglit_10 (& self) -> bool { * self == GFCTL_AGFSEL_A :: GFCTL_AGFSEL_AGLIT_10 } # [doc = "AGLIT_25"] # [inline (always)] pub fn is_gfctl_agfsel_aglit_25 (& self) -> bool { * self == GFCTL_AGFSEL_A :: GFCTL_AGFSEL_AGLIT_25 } # [doc = "AGLIT_50"] # [inline (always)] pub fn is_gfctl_agfsel_aglit_50 (& self) -> bool { * self == GFCTL_AGFSEL_A :: GFCTL_AGFSEL_AGLIT_50 } } # [doc = "Field `GFCTL_AGFSEL` writer - Analog Glitch Suppression Pulse Width This field controls the pulse width select for the analog glitch suppression on SCL and SDA lines. See device datasheet for exact values. (ULP I2C only)"] pub type GFCTL_AGFSEL_W < 'a , REG , const O : u8 > = crate :: FieldWriterSafe < 'a , REG , 2 , O , GFCTL_AGFSEL_A > ; impl < 'a , REG , const O : u8 > GFCTL_AGFSEL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "AGLIT_5"] # [inline (always)] pub fn gfctl_agfsel_aglit_5 (self) -> & 'a mut crate :: W < REG > { self . variant (GFCTL_AGFSEL_A :: GFCTL_AGFSEL_AGLIT_5) } # [doc = "AGLIT_10"] # [inline (always)] pub fn gfctl_agfsel_aglit_10 (self) -> & 'a mut crate :: W < REG > { self . variant (GFCTL_AGFSEL_A :: GFCTL_AGFSEL_AGLIT_10) } # [doc = "AGLIT_25"] # [inline (always)] pub fn gfctl_agfsel_aglit_25 (self) -> & 'a mut crate :: W < REG > { self . variant (GFCTL_AGFSEL_A :: GFCTL_AGFSEL_AGLIT_25) } # [doc = "AGLIT_50"] # [inline (always)] pub fn gfctl_agfsel_aglit_50 (self) -> & 'a mut crate :: W < REG > { self . variant (GFCTL_AGFSEL_A :: GFCTL_AGFSEL_AGLIT_50) } } # [doc = "Field `GFCTL_CHAIN` reader - Analog and digital noise filters chaining enable."] pub type GFCTL_CHAIN_R = crate :: BitReader < GFCTL_CHAIN_A > ; # [doc = "Analog and digital noise filters chaining enable.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum GFCTL_CHAIN_A { # [doc = "0: DISABLE"] GFCTL_CHAIN_DISABLE = 0 , # [doc = "1: ENABLE"] GFCTL_CHAIN_ENABLE = 1 , } impl From < GFCTL_CHAIN_A > for bool { # [inline (always)] fn from (variant : GFCTL_CHAIN_A) -> Self { variant as u8 != 0 } } impl GFCTL_CHAIN_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> GFCTL_CHAIN_A { match self . bits { false => GFCTL_CHAIN_A :: GFCTL_CHAIN_DISABLE , true => GFCTL_CHAIN_A :: GFCTL_CHAIN_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_gfctl_chain_disable (& self) -> bool { * self == GFCTL_CHAIN_A :: GFCTL_CHAIN_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_gfctl_chain_enable (& self) -> bool { * self == GFCTL_CHAIN_A :: GFCTL_CHAIN_ENABLE } } # [doc = "Field `GFCTL_CHAIN` writer - Analog and digital noise filters chaining enable."] pub type GFCTL_CHAIN_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , GFCTL_CHAIN_A > ; impl < 'a , REG , const O : u8 > GFCTL_CHAIN_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn gfctl_chain_disable (self) -> & 'a mut crate :: W < REG > { self . variant (GFCTL_CHAIN_A :: GFCTL_CHAIN_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn gfctl_chain_enable (self) -> & 'a mut crate :: W < REG > { self . variant (GFCTL_CHAIN_A :: GFCTL_CHAIN_ENABLE) } } impl R { # [doc = "Bits 0:2 - Glitch Suppression Pulse Width This field controls the pulse width select for glitch suppression on the SCL and SDA lines. The following values are the glitch suppression values in terms of functional clocks. (Core Domain only)"] # [inline (always)] pub fn gfctl_dgfsel (& self) -> GFCTL_DGFSEL_R { GFCTL_DGFSEL_R :: new ((self . bits & 7) as u8) } # [doc = "Bit 8 - Analog Glitch Suppression Enable"] # [inline (always)] pub fn gfctl_agfen (& self) -> GFCTL_AGFEN_R { GFCTL_AGFEN_R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bits 9:10 - Analog Glitch Suppression Pulse Width This field controls the pulse width select for the analog glitch suppression on SCL and SDA lines. See device datasheet for exact values. (ULP I2C only)"] # [inline (always)] pub fn gfctl_agfsel (& self) -> GFCTL_AGFSEL_R { GFCTL_AGFSEL_R :: new (((self . bits >> 9) & 3) as u8) } # [doc = "Bit 11 - Analog and digital noise filters chaining enable."] # [inline (always)] pub fn gfctl_chain (& self) -> GFCTL_CHAIN_R { GFCTL_CHAIN_R :: new (((self . bits >> 11) & 1) != 0) } } impl W { # [doc = "Bits 0:2 - Glitch Suppression Pulse Width This field controls the pulse width select for glitch suppression on the SCL and SDA lines. The following values are the glitch suppression values in terms of functional clocks. (Core Domain only)"] # [inline (always)] # [must_use] pub fn gfctl_dgfsel (& mut self) -> GFCTL_DGFSEL_W < GFCTL_SPEC , 0 > { GFCTL_DGFSEL_W :: new (self) } # [doc = "Bit 8 - Analog Glitch Suppression Enable"] # [inline (always)] # [must_use] pub fn gfctl_agfen (& mut self) -> GFCTL_AGFEN_W < GFCTL_SPEC , 8 > { GFCTL_AGFEN_W :: new (self) } # [doc = "Bits 9:10 - Analog Glitch Suppression Pulse Width This field controls the pulse width select for the analog glitch suppression on SCL and SDA lines. See device datasheet for exact values. (ULP I2C only)"] # [inline (always)] # [must_use] pub fn gfctl_agfsel (& mut self) -> GFCTL_AGFSEL_W < GFCTL_SPEC , 9 > { GFCTL_AGFSEL_W :: new (self) } # [doc = "Bit 11 - Analog and digital noise filters chaining enable."] # [inline (always)] # [must_use] pub fn gfctl_chain (& mut self) -> GFCTL_CHAIN_W <'_, GFCTL_SPEC , 11 > { GFCTL_CHAIN_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "I2C Glitch Filter Control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gfctl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gfctl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GFCTL_SPEC ; impl crate :: RegisterSpec for GFCTL_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`gfctl::R`](R) reader structure"] impl crate :: Readable for GFCTL_SPEC { } # [doc = "`write(|w| ..)` method takes [`gfctl::W`](W) writer structure"] impl crate :: Writable for GFCTL_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets GFCTL to value 0"] impl crate :: Resettable for GFCTL_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/sysctl/nmiiset.rs:1:2193 [INFO] [stdout] | [INFO] [stdout] 1 | ... pub fn nmiiset_borlvl (& mut self) -> NMIISET_BORLVL_W < NMIISET_SPEC , 0 > { NMIISET_BORLVL_W :: new (self) } # [doc = "Bit 1 - Watc... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `NMIISET` writer"] pub type W = crate :: W < NMIISET_SPEC > ; # [doc = "Set the BORLVL NMI\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum NMIISET_BORLVL_AW { # [doc = "0: NO_EFFECT"] NMIISET_BORLVL_NO_EFFECT = 0 , # [doc = "1: SET"] NMIISET_BORLVL_SET = 1 , } impl From < NMIISET_BORLVL_AW > for bool { # [inline (always)] fn from (variant : NMIISET_BORLVL_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `NMIISET_BORLVL` writer - Set the BORLVL NMI"] pub type NMIISET_BORLVL_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , NMIISET_BORLVL_AW > ; impl < 'a , REG , const O : u8 > NMIISET_BORLVL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn nmiiset_borlvl_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (NMIISET_BORLVL_AW :: NMIISET_BORLVL_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn nmiiset_borlvl_set (self) -> & 'a mut crate :: W < REG > { self . variant (NMIISET_BORLVL_AW :: NMIISET_BORLVL_SET) } } # [doc = "Watch Dog 0 Fault\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum NMIISET_WWDT0_AW { # [doc = "0: NO_EFFECT"] NMIISET_WWDT0_NO_EFFECT = 0 , # [doc = "1: SET"] NMIISET_WWDT0_SET = 1 , } impl From < NMIISET_WWDT0_AW > for bool { # [inline (always)] fn from (variant : NMIISET_WWDT0_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `NMIISET_WWDT0` writer - Watch Dog 0 Fault"] pub type NMIISET_WWDT0_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , NMIISET_WWDT0_AW > ; impl < 'a , REG , const O : u8 > NMIISET_WWDT0_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn nmiiset_wwdt0_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (NMIISET_WWDT0_AW :: NMIISET_WWDT0_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn nmiiset_wwdt0_set (self) -> & 'a mut crate :: W < REG > { self . variant (NMIISET_WWDT0_AW :: NMIISET_WWDT0_SET) } } impl W { # [doc = "Bit 0 - Set the BORLVL NMI"] # [inline (always)] # [must_use] pub fn nmiiset_borlvl (& mut self) -> NMIISET_BORLVL_W <'_, NMIISET_SPEC , 0 > { NMIISET_BORLVL_W :: new (self) } # [doc = "Bit 1 - Watch Dog 0 Fault"] # [inline (always)] # [must_use] pub fn nmiiset_wwdt0 (& mut self) -> NMIISET_WWDT0_W < NMIISET_SPEC , 1 > { NMIISET_WWDT0_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "NMI interrupt set\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`nmiiset::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct NMIISET_SPEC ; impl crate :: RegisterSpec for NMIISET_SPEC { type Ux = u32 ; } # [doc = "`write(|w| ..)` method takes [`nmiiset::W`](W) writer structure"] impl crate :: Writable for NMIISET_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets NMIISET to value 0"] impl crate :: Resettable for NMIISET_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/spi0/int_event0_imask.rs:1:24914 [INFO] [stdout] | [INFO] [stdout] 1 | ...t0_imask_rtout (& mut self) -> INT_EVENT0_IMASK_RTOUT_W < INT_EVENT0_IMASK_SPEC , 2 > { INT_EVENT0_IMASK_RTOUT_W :: new (self) } # [do... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `INT_EVENT0_IMASK` reader"] pub type R = crate :: R < INT_EVENT0_IMASK_SPEC > ; # [doc = "Register `INT_EVENT0_IMASK` writer"] pub type W = crate :: W < INT_EVENT0_IMASK_SPEC > ; # [doc = "Field `INT_EVENT0_IMASK_RXFIFO_OVF` reader - RXFIFO overflow event mask."] pub type INT_EVENT0_IMASK_RXFIFO_OVF_R = crate :: BitReader < INT_EVENT0_IMASK_RXFIFO_OVF_A > ; # [doc = "RXFIFO overflow event mask.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_RXFIFO_OVF_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_RXFIFO_OVF_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_RXFIFO_OVF_SET = 1 , } impl From < INT_EVENT0_IMASK_RXFIFO_OVF_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_RXFIFO_OVF_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_RXFIFO_OVF_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_RXFIFO_OVF_A { match self . bits { false => INT_EVENT0_IMASK_RXFIFO_OVF_A :: INT_EVENT0_IMASK_RXFIFO_OVF_CLR , true => INT_EVENT0_IMASK_RXFIFO_OVF_A :: INT_EVENT0_IMASK_RXFIFO_OVF_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_rxfifo_ovf_clr (& self) -> bool { * self == INT_EVENT0_IMASK_RXFIFO_OVF_A :: INT_EVENT0_IMASK_RXFIFO_OVF_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_rxfifo_ovf_set (& self) -> bool { * self == INT_EVENT0_IMASK_RXFIFO_OVF_A :: INT_EVENT0_IMASK_RXFIFO_OVF_SET } } # [doc = "Field `INT_EVENT0_IMASK_RXFIFO_OVF` writer - RXFIFO overflow event mask."] pub type INT_EVENT0_IMASK_RXFIFO_OVF_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_RXFIFO_OVF_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_RXFIFO_OVF_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_rxfifo_ovf_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXFIFO_OVF_A :: INT_EVENT0_IMASK_RXFIFO_OVF_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_rxfifo_ovf_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXFIFO_OVF_A :: INT_EVENT0_IMASK_RXFIFO_OVF_SET) } } # [doc = "Field `INT_EVENT0_IMASK_PER` reader - Parity error event mask."] pub type INT_EVENT0_IMASK_PER_R = crate :: BitReader < INT_EVENT0_IMASK_PER_A > ; # [doc = "Parity error event mask.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_PER_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_PER_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_PER_SET = 1 , } impl From < INT_EVENT0_IMASK_PER_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_PER_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_PER_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_PER_A { match self . bits { false => INT_EVENT0_IMASK_PER_A :: INT_EVENT0_IMASK_PER_CLR , true => INT_EVENT0_IMASK_PER_A :: INT_EVENT0_IMASK_PER_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_per_clr (& self) -> bool { * self == INT_EVENT0_IMASK_PER_A :: INT_EVENT0_IMASK_PER_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_per_set (& self) -> bool { * self == INT_EVENT0_IMASK_PER_A :: INT_EVENT0_IMASK_PER_SET } } # [doc = "Field `INT_EVENT0_IMASK_PER` writer - Parity error event mask."] pub type INT_EVENT0_IMASK_PER_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_PER_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_PER_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_per_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_PER_A :: INT_EVENT0_IMASK_PER_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_per_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_PER_A :: INT_EVENT0_IMASK_PER_SET) } } # [doc = "Field `INT_EVENT0_IMASK_RTOUT` reader - Enable SPI Receive Time-Out event mask."] pub type INT_EVENT0_IMASK_RTOUT_R = crate :: BitReader < INT_EVENT0_IMASK_RTOUT_A > ; # [doc = "Enable SPI Receive Time-Out event mask.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_RTOUT_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_RTOUT_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_RTOUT_SET = 1 , } impl From < INT_EVENT0_IMASK_RTOUT_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_RTOUT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_RTOUT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_RTOUT_A { match self . bits { false => INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_CLR , true => INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_rtout_clr (& self) -> bool { * self == INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_rtout_set (& self) -> bool { * self == INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_SET } } # [doc = "Field `INT_EVENT0_IMASK_RTOUT` writer - Enable SPI Receive Time-Out event mask."] pub type INT_EVENT0_IMASK_RTOUT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_RTOUT_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_RTOUT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_rtout_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_rtout_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_SET) } } # [doc = "Field `INT_EVENT0_IMASK_RX` reader - Receive FIFO event.This interrupt is set if the selected Receive FIFO level has been reached"] pub type INT_EVENT0_IMASK_RX_R = crate :: BitReader < INT_EVENT0_IMASK_RX_A > ; # [doc = "Receive FIFO event.This interrupt is set if the selected Receive FIFO level has been reached\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_RX_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_RX_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_RX_SET = 1 , } impl From < INT_EVENT0_IMASK_RX_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_RX_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_RX_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_RX_A { match self . bits { false => INT_EVENT0_IMASK_RX_A :: INT_EVENT0_IMASK_RX_CLR , true => INT_EVENT0_IMASK_RX_A :: INT_EVENT0_IMASK_RX_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_rx_clr (& self) -> bool { * self == INT_EVENT0_IMASK_RX_A :: INT_EVENT0_IMASK_RX_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_rx_set (& self) -> bool { * self == INT_EVENT0_IMASK_RX_A :: INT_EVENT0_IMASK_RX_SET } } # [doc = "Field `INT_EVENT0_IMASK_RX` writer - Receive FIFO event.This interrupt is set if the selected Receive FIFO level has been reached"] pub type INT_EVENT0_IMASK_RX_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_RX_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_RX_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_rx_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RX_A :: INT_EVENT0_IMASK_RX_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_rx_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RX_A :: INT_EVENT0_IMASK_RX_SET) } } # [doc = "Field `INT_EVENT0_IMASK_TX` reader - Transmit FIFO event mask."] pub type INT_EVENT0_IMASK_TX_R = crate :: BitReader < INT_EVENT0_IMASK_TX_A > ; # [doc = "Transmit FIFO event mask.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_TX_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_TX_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_TX_SET = 1 , } impl From < INT_EVENT0_IMASK_TX_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_TX_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_TX_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_TX_A { match self . bits { false => INT_EVENT0_IMASK_TX_A :: INT_EVENT0_IMASK_TX_CLR , true => INT_EVENT0_IMASK_TX_A :: INT_EVENT0_IMASK_TX_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_tx_clr (& self) -> bool { * self == INT_EVENT0_IMASK_TX_A :: INT_EVENT0_IMASK_TX_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_tx_set (& self) -> bool { * self == INT_EVENT0_IMASK_TX_A :: INT_EVENT0_IMASK_TX_SET } } # [doc = "Field `INT_EVENT0_IMASK_TX` writer - Transmit FIFO event mask."] pub type INT_EVENT0_IMASK_TX_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_TX_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_TX_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_tx_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_TX_A :: INT_EVENT0_IMASK_TX_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_tx_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_TX_A :: INT_EVENT0_IMASK_TX_SET) } } # [doc = "Field `INT_EVENT0_IMASK_TXEMPTY` reader - Transmit FIFO Empty event mask."] pub type INT_EVENT0_IMASK_TXEMPTY_R = crate :: BitReader < INT_EVENT0_IMASK_TXEMPTY_A > ; # [doc = "Transmit FIFO Empty event mask.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_TXEMPTY_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_TXEMPTY_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_TXEMPTY_SET = 1 , } impl From < INT_EVENT0_IMASK_TXEMPTY_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_TXEMPTY_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_TXEMPTY_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_TXEMPTY_A { match self . bits { false => INT_EVENT0_IMASK_TXEMPTY_A :: INT_EVENT0_IMASK_TXEMPTY_CLR , true => INT_EVENT0_IMASK_TXEMPTY_A :: INT_EVENT0_IMASK_TXEMPTY_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_txempty_clr (& self) -> bool { * self == INT_EVENT0_IMASK_TXEMPTY_A :: INT_EVENT0_IMASK_TXEMPTY_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_txempty_set (& self) -> bool { * self == INT_EVENT0_IMASK_TXEMPTY_A :: INT_EVENT0_IMASK_TXEMPTY_SET } } # [doc = "Field `INT_EVENT0_IMASK_TXEMPTY` writer - Transmit FIFO Empty event mask."] pub type INT_EVENT0_IMASK_TXEMPTY_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_TXEMPTY_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_TXEMPTY_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_txempty_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_TXEMPTY_A :: INT_EVENT0_IMASK_TXEMPTY_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_txempty_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_TXEMPTY_A :: INT_EVENT0_IMASK_TXEMPTY_SET) } } # [doc = "Field `INT_EVENT0_IMASK_IDLE` reader - SPI Idle event mask."] pub type INT_EVENT0_IMASK_IDLE_R = crate :: BitReader < INT_EVENT0_IMASK_IDLE_A > ; # [doc = "SPI Idle event mask.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_IDLE_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_IDLE_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_IDLE_SET = 1 , } impl From < INT_EVENT0_IMASK_IDLE_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_IDLE_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_IDLE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_IDLE_A { match self . bits { false => INT_EVENT0_IMASK_IDLE_A :: INT_EVENT0_IMASK_IDLE_CLR , true => INT_EVENT0_IMASK_IDLE_A :: INT_EVENT0_IMASK_IDLE_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_idle_clr (& self) -> bool { * self == INT_EVENT0_IMASK_IDLE_A :: INT_EVENT0_IMASK_IDLE_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_idle_set (& self) -> bool { * self == INT_EVENT0_IMASK_IDLE_A :: INT_EVENT0_IMASK_IDLE_SET } } # [doc = "Field `INT_EVENT0_IMASK_IDLE` writer - SPI Idle event mask."] pub type INT_EVENT0_IMASK_IDLE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_IDLE_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_IDLE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_idle_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_IDLE_A :: INT_EVENT0_IMASK_IDLE_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_idle_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_IDLE_A :: INT_EVENT0_IMASK_IDLE_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DMA_DONE_RX` reader - DMA Done 1 event for RX event mask."] pub type INT_EVENT0_IMASK_DMA_DONE_RX_R = crate :: BitReader < INT_EVENT0_IMASK_DMA_DONE_RX_A > ; # [doc = "DMA Done 1 event for RX event mask.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DMA_DONE_RX_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DMA_DONE_RX_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DMA_DONE_RX_SET = 1 , } impl From < INT_EVENT0_IMASK_DMA_DONE_RX_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DMA_DONE_RX_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DMA_DONE_RX_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DMA_DONE_RX_A { match self . bits { false => INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_CLR , true => INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dma_done_rx_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dma_done_rx_set (& self) -> bool { * self == INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_SET } } # [doc = "Field `INT_EVENT0_IMASK_DMA_DONE_RX` writer - DMA Done 1 event for RX event mask."] pub type INT_EVENT0_IMASK_DMA_DONE_RX_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DMA_DONE_RX_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DMA_DONE_RX_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dma_done_rx_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dma_done_rx_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DMA_DONE_TX` reader - DMA Done 1 event for TX event mask."] pub type INT_EVENT0_IMASK_DMA_DONE_TX_R = crate :: BitReader < INT_EVENT0_IMASK_DMA_DONE_TX_A > ; # [doc = "DMA Done 1 event for TX event mask.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DMA_DONE_TX_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DMA_DONE_TX_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DMA_DONE_TX_SET = 1 , } impl From < INT_EVENT0_IMASK_DMA_DONE_TX_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DMA_DONE_TX_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DMA_DONE_TX_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DMA_DONE_TX_A { match self . bits { false => INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_CLR , true => INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dma_done_tx_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dma_done_tx_set (& self) -> bool { * self == INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_SET } } # [doc = "Field `INT_EVENT0_IMASK_DMA_DONE_TX` writer - DMA Done 1 event for TX event mask."] pub type INT_EVENT0_IMASK_DMA_DONE_TX_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DMA_DONE_TX_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DMA_DONE_TX_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dma_done_tx_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dma_done_tx_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_SET) } } # [doc = "Field `INT_EVENT0_IMASK_TXFIFO_UNF` reader - TX FIFO underflow interrupt mask"] pub type INT_EVENT0_IMASK_TXFIFO_UNF_R = crate :: BitReader < INT_EVENT0_IMASK_TXFIFO_UNF_A > ; # [doc = "TX FIFO underflow interrupt mask\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_TXFIFO_UNF_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_TXFIFO_UNF_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_TXFIFO_UNF_SET = 1 , } impl From < INT_EVENT0_IMASK_TXFIFO_UNF_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_TXFIFO_UNF_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_TXFIFO_UNF_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_TXFIFO_UNF_A { match self . bits { false => INT_EVENT0_IMASK_TXFIFO_UNF_A :: INT_EVENT0_IMASK_TXFIFO_UNF_CLR , true => INT_EVENT0_IMASK_TXFIFO_UNF_A :: INT_EVENT0_IMASK_TXFIFO_UNF_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_txfifo_unf_clr (& self) -> bool { * self == INT_EVENT0_IMASK_TXFIFO_UNF_A :: INT_EVENT0_IMASK_TXFIFO_UNF_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_txfifo_unf_set (& self) -> bool { * self == INT_EVENT0_IMASK_TXFIFO_UNF_A :: INT_EVENT0_IMASK_TXFIFO_UNF_SET } } # [doc = "Field `INT_EVENT0_IMASK_TXFIFO_UNF` writer - TX FIFO underflow interrupt mask"] pub type INT_EVENT0_IMASK_TXFIFO_UNF_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_TXFIFO_UNF_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_TXFIFO_UNF_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_txfifo_unf_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_TXFIFO_UNF_A :: INT_EVENT0_IMASK_TXFIFO_UNF_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_txfifo_unf_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_TXFIFO_UNF_A :: INT_EVENT0_IMASK_TXFIFO_UNF_SET) } } # [doc = "Field `INT_EVENT0_IMASK_RXFULL` reader - RX FIFO Full Interrupt Mask"] pub type INT_EVENT0_IMASK_RXFULL_R = crate :: BitReader < INT_EVENT0_IMASK_RXFULL_A > ; # [doc = "RX FIFO Full Interrupt Mask\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_RXFULL_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_RXFULL_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_RXFULL_SET = 1 , } impl From < INT_EVENT0_IMASK_RXFULL_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_RXFULL_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_RXFULL_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_RXFULL_A { match self . bits { false => INT_EVENT0_IMASK_RXFULL_A :: INT_EVENT0_IMASK_RXFULL_CLR , true => INT_EVENT0_IMASK_RXFULL_A :: INT_EVENT0_IMASK_RXFULL_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_rxfull_clr (& self) -> bool { * self == INT_EVENT0_IMASK_RXFULL_A :: INT_EVENT0_IMASK_RXFULL_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_rxfull_set (& self) -> bool { * self == INT_EVENT0_IMASK_RXFULL_A :: INT_EVENT0_IMASK_RXFULL_SET } } # [doc = "Field `INT_EVENT0_IMASK_RXFULL` writer - RX FIFO Full Interrupt Mask"] pub type INT_EVENT0_IMASK_RXFULL_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_RXFULL_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_RXFULL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_rxfull_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXFULL_A :: INT_EVENT0_IMASK_RXFULL_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_rxfull_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXFULL_A :: INT_EVENT0_IMASK_RXFULL_SET) } } impl R { # [doc = "Bit 0 - RXFIFO overflow event mask."] # [inline (always)] pub fn int_event0_imask_rxfifo_ovf (& self) -> INT_EVENT0_IMASK_RXFIFO_OVF_R { INT_EVENT0_IMASK_RXFIFO_OVF_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - Parity error event mask."] # [inline (always)] pub fn int_event0_imask_per (& self) -> INT_EVENT0_IMASK_PER_R { INT_EVENT0_IMASK_PER_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - Enable SPI Receive Time-Out event mask."] # [inline (always)] pub fn int_event0_imask_rtout (& self) -> INT_EVENT0_IMASK_RTOUT_R { INT_EVENT0_IMASK_RTOUT_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - Receive FIFO event.This interrupt is set if the selected Receive FIFO level has been reached"] # [inline (always)] pub fn int_event0_imask_rx (& self) -> INT_EVENT0_IMASK_RX_R { INT_EVENT0_IMASK_RX_R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - Transmit FIFO event mask."] # [inline (always)] pub fn int_event0_imask_tx (& self) -> INT_EVENT0_IMASK_TX_R { INT_EVENT0_IMASK_TX_R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - Transmit FIFO Empty event mask."] # [inline (always)] pub fn int_event0_imask_txempty (& self) -> INT_EVENT0_IMASK_TXEMPTY_R { INT_EVENT0_IMASK_TXEMPTY_R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - SPI Idle event mask."] # [inline (always)] pub fn int_event0_imask_idle (& self) -> INT_EVENT0_IMASK_IDLE_R { INT_EVENT0_IMASK_IDLE_R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - DMA Done 1 event for RX event mask."] # [inline (always)] pub fn int_event0_imask_dma_done_rx (& self) -> INT_EVENT0_IMASK_DMA_DONE_RX_R { INT_EVENT0_IMASK_DMA_DONE_RX_R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - DMA Done 1 event for TX event mask."] # [inline (always)] pub fn int_event0_imask_dma_done_tx (& self) -> INT_EVENT0_IMASK_DMA_DONE_TX_R { INT_EVENT0_IMASK_DMA_DONE_TX_R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - TX FIFO underflow interrupt mask"] # [inline (always)] pub fn int_event0_imask_txfifo_unf (& self) -> INT_EVENT0_IMASK_TXFIFO_UNF_R { INT_EVENT0_IMASK_TXFIFO_UNF_R :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - RX FIFO Full Interrupt Mask"] # [inline (always)] pub fn int_event0_imask_rxfull (& self) -> INT_EVENT0_IMASK_RXFULL_R { INT_EVENT0_IMASK_RXFULL_R :: new (((self . bits >> 10) & 1) != 0) } } impl W { # [doc = "Bit 0 - RXFIFO overflow event mask."] # [inline (always)] # [must_use] pub fn int_event0_imask_rxfifo_ovf (& mut self) -> INT_EVENT0_IMASK_RXFIFO_OVF_W < INT_EVENT0_IMASK_SPEC , 0 > { INT_EVENT0_IMASK_RXFIFO_OVF_W :: new (self) } # [doc = "Bit 1 - Parity error event mask."] # [inline (always)] # [must_use] pub fn int_event0_imask_per (& mut self) -> INT_EVENT0_IMASK_PER_W < INT_EVENT0_IMASK_SPEC , 1 > { INT_EVENT0_IMASK_PER_W :: new (self) } # [doc = "Bit 2 - Enable SPI Receive Time-Out event mask."] # [inline (always)] # [must_use] pub fn int_event0_imask_rtout (& mut self) -> INT_EVENT0_IMASK_RTOUT_W <'_, INT_EVENT0_IMASK_SPEC , 2 > { INT_EVENT0_IMASK_RTOUT_W :: new (self) } # [doc = "Bit 3 - Receive FIFO event.This interrupt is set if the selected Receive FIFO level has been reached"] # [inline (always)] # [must_use] pub fn int_event0_imask_rx (& mut self) -> INT_EVENT0_IMASK_RX_W < INT_EVENT0_IMASK_SPEC , 3 > { INT_EVENT0_IMASK_RX_W :: new (self) } # [doc = "Bit 4 - Transmit FIFO event mask."] # [inline (always)] # [must_use] pub fn int_event0_imask_tx (& mut self) -> INT_EVENT0_IMASK_TX_W < INT_EVENT0_IMASK_SPEC , 4 > { INT_EVENT0_IMASK_TX_W :: new (self) } # [doc = "Bit 5 - Transmit FIFO Empty event mask."] # [inline (always)] # [must_use] pub fn int_event0_imask_txempty (& mut self) -> INT_EVENT0_IMASK_TXEMPTY_W < INT_EVENT0_IMASK_SPEC , 5 > { INT_EVENT0_IMASK_TXEMPTY_W :: new (self) } # [doc = "Bit 6 - SPI Idle event mask."] # [inline (always)] # [must_use] pub fn int_event0_imask_idle (& mut self) -> INT_EVENT0_IMASK_IDLE_W < INT_EVENT0_IMASK_SPEC , 6 > { INT_EVENT0_IMASK_IDLE_W :: new (self) } # [doc = "Bit 7 - DMA Done 1 event for RX event mask."] # [inline (always)] # [must_use] pub fn int_event0_imask_dma_done_rx (& mut self) -> INT_EVENT0_IMASK_DMA_DONE_RX_W < INT_EVENT0_IMASK_SPEC , 7 > { INT_EVENT0_IMASK_DMA_DONE_RX_W :: new (self) } # [doc = "Bit 8 - DMA Done 1 event for TX event mask."] # [inline (always)] # [must_use] pub fn int_event0_imask_dma_done_tx (& mut self) -> INT_EVENT0_IMASK_DMA_DONE_TX_W < INT_EVENT0_IMASK_SPEC , 8 > { INT_EVENT0_IMASK_DMA_DONE_TX_W :: new (self) } # [doc = "Bit 9 - TX FIFO underflow interrupt mask"] # [inline (always)] # [must_use] pub fn int_event0_imask_txfifo_unf (& mut self) -> INT_EVENT0_IMASK_TXFIFO_UNF_W < INT_EVENT0_IMASK_SPEC , 9 > { INT_EVENT0_IMASK_TXFIFO_UNF_W :: new (self) } # [doc = "Bit 10 - RX FIFO Full Interrupt Mask"] # [inline (always)] # [must_use] pub fn int_event0_imask_rxfull (& mut self) -> INT_EVENT0_IMASK_RXFULL_W < INT_EVENT0_IMASK_SPEC , 10 > { INT_EVENT0_IMASK_RXFULL_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Interrupt mask\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_event0_imask::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_event0_imask::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct INT_EVENT0_IMASK_SPEC ; impl crate :: RegisterSpec for INT_EVENT0_IMASK_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`int_event0_imask::R`](R) reader structure"] impl crate :: Readable for INT_EVENT0_IMASK_SPEC { } # [doc = "`write(|w| ..)` method takes [`int_event0_imask::W`](W) writer structure"] impl crate :: Writable for INT_EVENT0_IMASK_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets INT_EVENT0_IMASK to value 0"] impl crate :: Resettable for INT_EVENT0_IMASK_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/gpioa/fsub_0.rs:1:2067 [INFO] [stdout] | [INFO] [stdout] 1 | ...e] pub fn fsub_0_chanid (& mut self) -> FSUB_0_CHANID_W < FSUB_0_SPEC , 0 > { FSUB_0_CHANID_W :: new (self) } # [doc = r" Writes raw b... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `FSUB_0` reader"] pub type R = crate :: R < FSUB_0_SPEC > ; # [doc = "Register `FSUB_0` writer"] pub type W = crate :: W < FSUB_0_SPEC > ; # [doc = "Field `FSUB_0_CHANID` reader - 0 = disconnected. 1-15 = connected to channelID = CHANID."] pub type FSUB_0_CHANID_R = crate :: FieldReader < FSUB_0_CHANID_A > ; # [doc = "0 = disconnected. 1-15 = connected to channelID = CHANID.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum FSUB_0_CHANID_A { # [doc = "0: UNCONNECTED"] FSUB_0_CHANID_UNCONNECTED = 0 , } impl From < FSUB_0_CHANID_A > for u8 { # [inline (always)] fn from (variant : FSUB_0_CHANID_A) -> Self { variant as _ } } impl crate :: FieldSpec for FSUB_0_CHANID_A { type Ux = u8 ; } impl FSUB_0_CHANID_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < FSUB_0_CHANID_A > { match self . bits { 0 => Some (FSUB_0_CHANID_A :: FSUB_0_CHANID_UNCONNECTED) , _ => None , } } # [doc = "UNCONNECTED"] # [inline (always)] pub fn is_fsub_0_chanid_unconnected (& self) -> bool { * self == FSUB_0_CHANID_A :: FSUB_0_CHANID_UNCONNECTED } } # [doc = "Field `FSUB_0_CHANID` writer - 0 = disconnected. 1-15 = connected to channelID = CHANID."] pub type FSUB_0_CHANID_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 2 , O , FSUB_0_CHANID_A > ; impl < 'a , REG , const O : u8 > FSUB_0_CHANID_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "UNCONNECTED"] # [inline (always)] pub fn fsub_0_chanid_unconnected (self) -> & 'a mut crate :: W < REG > { self . variant (FSUB_0_CHANID_A :: FSUB_0_CHANID_UNCONNECTED) } } impl R { # [doc = "Bits 0:1 - 0 = disconnected. 1-15 = connected to channelID = CHANID."] # [inline (always)] pub fn fsub_0_chanid (& self) -> FSUB_0_CHANID_R { FSUB_0_CHANID_R :: new ((self . bits & 3) as u8) } } impl W { # [doc = "Bits 0:1 - 0 = disconnected. 1-15 = connected to channelID = CHANID."] # [inline (always)] # [must_use] pub fn fsub_0_chanid (& mut self) -> FSUB_0_CHANID_W <'_, FSUB_0_SPEC , 0 > { FSUB_0_CHANID_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Subsciber Port 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fsub_0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fsub_0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct FSUB_0_SPEC ; impl crate :: RegisterSpec for FSUB_0_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`fsub_0::R`](R) reader structure"] impl crate :: Readable for FSUB_0_SPEC { } # [doc = "`write(|w| ..)` method takes [`fsub_0::W`](W) writer structure"] impl crate :: Writable for FSUB_0_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets FSUB_0 to value 0"] impl crate :: Resettable for FSUB_0_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/opa1/cfg.rs:1:17669 [INFO] [stdout] | [INFO] [stdout] 1 | ... [must_use] pub fn cfg_gain (& mut self) -> CFG_GAIN_W < CFG_SPEC , 13 > { CFG_GAIN_W :: new (self) } # [doc = r" Writes raw bits to t... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `CFG` reader"] pub type R = crate :: R < CFG_SPEC > ; # [doc = "Register `CFG` writer"] pub type W = crate :: W < CFG_SPEC > ; # [doc = "Field `CFG_CHOP` reader - Chopping enable."] pub type CFG_CHOP_R = crate :: FieldReader < CFG_CHOP_A > ; # [doc = "Chopping enable.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum CFG_CHOP_A { # [doc = "0: OFF"] CFG_CHOP_OFF = 0 , # [doc = "1: ON"] CFG_CHOP_ON = 1 , # [doc = "2: AVGON"] CFG_CHOP_AVGON = 2 , } impl From < CFG_CHOP_A > for u8 { # [inline (always)] fn from (variant : CFG_CHOP_A) -> Self { variant as _ } } impl crate :: FieldSpec for CFG_CHOP_A { type Ux = u8 ; } impl CFG_CHOP_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < CFG_CHOP_A > { match self . bits { 0 => Some (CFG_CHOP_A :: CFG_CHOP_OFF) , 1 => Some (CFG_CHOP_A :: CFG_CHOP_ON) , 2 => Some (CFG_CHOP_A :: CFG_CHOP_AVGON) , _ => None , } } # [doc = "OFF"] # [inline (always)] pub fn is_cfg_chop_off (& self) -> bool { * self == CFG_CHOP_A :: CFG_CHOP_OFF } # [doc = "ON"] # [inline (always)] pub fn is_cfg_chop_on (& self) -> bool { * self == CFG_CHOP_A :: CFG_CHOP_ON } # [doc = "AVGON"] # [inline (always)] pub fn is_cfg_chop_avgon (& self) -> bool { * self == CFG_CHOP_A :: CFG_CHOP_AVGON } } # [doc = "Field `CFG_CHOP` writer - Chopping enable."] pub type CFG_CHOP_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 2 , O , CFG_CHOP_A > ; impl < 'a , REG , const O : u8 > CFG_CHOP_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "OFF"] # [inline (always)] pub fn cfg_chop_off (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_CHOP_A :: CFG_CHOP_OFF) } # [doc = "ON"] # [inline (always)] pub fn cfg_chop_on (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_CHOP_A :: CFG_CHOP_ON) } # [doc = "AVGON"] # [inline (always)] pub fn cfg_chop_avgon (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_CHOP_A :: CFG_CHOP_AVGON) } } # [doc = "Field `CFG_OUTPIN` reader - Enable output pin"] pub type CFG_OUTPIN_R = crate :: BitReader < CFG_OUTPIN_A > ; # [doc = "Enable output pin\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CFG_OUTPIN_A { # [doc = "0: DISABLED"] CFG_OUTPIN_DISABLED = 0 , # [doc = "1: ENABLED"] CFG_OUTPIN_ENABLED = 1 , } impl From < CFG_OUTPIN_A > for bool { # [inline (always)] fn from (variant : CFG_OUTPIN_A) -> Self { variant as u8 != 0 } } impl CFG_OUTPIN_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CFG_OUTPIN_A { match self . bits { false => CFG_OUTPIN_A :: CFG_OUTPIN_DISABLED , true => CFG_OUTPIN_A :: CFG_OUTPIN_ENABLED , } } # [doc = "DISABLED"] # [inline (always)] pub fn is_cfg_outpin_disabled (& self) -> bool { * self == CFG_OUTPIN_A :: CFG_OUTPIN_DISABLED } # [doc = "ENABLED"] # [inline (always)] pub fn is_cfg_outpin_enabled (& self) -> bool { * self == CFG_OUTPIN_A :: CFG_OUTPIN_ENABLED } } # [doc = "Field `CFG_OUTPIN` writer - Enable output pin"] pub type CFG_OUTPIN_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CFG_OUTPIN_A > ; impl < 'a , REG , const O : u8 > CFG_OUTPIN_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLED"] # [inline (always)] pub fn cfg_outpin_disabled (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_OUTPIN_A :: CFG_OUTPIN_DISABLED) } # [doc = "ENABLED"] # [inline (always)] pub fn cfg_outpin_enabled (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_OUTPIN_A :: CFG_OUTPIN_ENABLED) } } # [doc = "Field `CFG_PSEL` reader - Positive OA input selection. Please refer to the device specific datasheet for exact channels available."] pub type CFG_PSEL_R = crate :: FieldReader < CFG_PSEL_A > ; # [doc = "Positive OA input selection. Please refer to the device specific datasheet for exact channels available.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum CFG_PSEL_A { # [doc = "0: NC"] CFG_PSEL_NC = 0 , # [doc = "1: EXTPIN0"] CFG_PSEL_EXTPIN0 = 1 , # [doc = "2: EXTPIN1"] CFG_PSEL_EXTPIN1 = 2 , # [doc = "3: DAC12OUT"] CFG_PSEL_DAC12OUT = 3 , # [doc = "4: DAC8OUT"] CFG_PSEL_DAC8OUT = 4 , # [doc = "5: VREF"] CFG_PSEL_VREF = 5 , # [doc = "6: OANM1RTOP"] CFG_PSEL_OANM1RTOP = 6 , # [doc = "7: GPAMP_OUT_INT"] CFG_PSEL_GPAMP_OUT_INT = 7 , # [doc = "8: VSS"] CFG_PSEL_VSS = 8 , } impl From < CFG_PSEL_A > for u8 { # [inline (always)] fn from (variant : CFG_PSEL_A) -> Self { variant as _ } } impl crate :: FieldSpec for CFG_PSEL_A { type Ux = u8 ; } impl CFG_PSEL_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < CFG_PSEL_A > { match self . bits { 0 => Some (CFG_PSEL_A :: CFG_PSEL_NC) , 1 => Some (CFG_PSEL_A :: CFG_PSEL_EXTPIN0) , 2 => Some (CFG_PSEL_A :: CFG_PSEL_EXTPIN1) , 3 => Some (CFG_PSEL_A :: CFG_PSEL_DAC12OUT) , 4 => Some (CFG_PSEL_A :: CFG_PSEL_DAC8OUT) , 5 => Some (CFG_PSEL_A :: CFG_PSEL_VREF) , 6 => Some (CFG_PSEL_A :: CFG_PSEL_OANM1RTOP) , 7 => Some (CFG_PSEL_A :: CFG_PSEL_GPAMP_OUT_INT) , 8 => Some (CFG_PSEL_A :: CFG_PSEL_VSS) , _ => None , } } # [doc = "NC"] # [inline (always)] pub fn is_cfg_psel_nc (& self) -> bool { * self == CFG_PSEL_A :: CFG_PSEL_NC } # [doc = "EXTPIN0"] # [inline (always)] pub fn is_cfg_psel_extpin0 (& self) -> bool { * self == CFG_PSEL_A :: CFG_PSEL_EXTPIN0 } # [doc = "EXTPIN1"] # [inline (always)] pub fn is_cfg_psel_extpin1 (& self) -> bool { * self == CFG_PSEL_A :: CFG_PSEL_EXTPIN1 } # [doc = "DAC12OUT"] # [inline (always)] pub fn is_cfg_psel_dac12out (& self) -> bool { * self == CFG_PSEL_A :: CFG_PSEL_DAC12OUT } # [doc = "DAC8OUT"] # [inline (always)] pub fn is_cfg_psel_dac8out (& self) -> bool { * self == CFG_PSEL_A :: CFG_PSEL_DAC8OUT } # [doc = "VREF"] # [inline (always)] pub fn is_cfg_psel_vref (& self) -> bool { * self == CFG_PSEL_A :: CFG_PSEL_VREF } # [doc = "OANM1RTOP"] # [inline (always)] pub fn is_cfg_psel_oanm1rtop (& self) -> bool { * self == CFG_PSEL_A :: CFG_PSEL_OANM1RTOP } # [doc = "GPAMP_OUT_INT"] # [inline (always)] pub fn is_cfg_psel_gpamp_out_int (& self) -> bool { * self == CFG_PSEL_A :: CFG_PSEL_GPAMP_OUT_INT } # [doc = "VSS"] # [inline (always)] pub fn is_cfg_psel_vss (& self) -> bool { * self == CFG_PSEL_A :: CFG_PSEL_VSS } } # [doc = "Field `CFG_PSEL` writer - Positive OA input selection. Please refer to the device specific datasheet for exact channels available."] pub type CFG_PSEL_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 4 , O , CFG_PSEL_A > ; impl < 'a , REG , const O : u8 > CFG_PSEL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "NC"] # [inline (always)] pub fn cfg_psel_nc (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_PSEL_A :: CFG_PSEL_NC) } # [doc = "EXTPIN0"] # [inline (always)] pub fn cfg_psel_extpin0 (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_PSEL_A :: CFG_PSEL_EXTPIN0) } # [doc = "EXTPIN1"] # [inline (always)] pub fn cfg_psel_extpin1 (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_PSEL_A :: CFG_PSEL_EXTPIN1) } # [doc = "DAC12OUT"] # [inline (always)] pub fn cfg_psel_dac12out (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_PSEL_A :: CFG_PSEL_DAC12OUT) } # [doc = "DAC8OUT"] # [inline (always)] pub fn cfg_psel_dac8out (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_PSEL_A :: CFG_PSEL_DAC8OUT) } # [doc = "VREF"] # [inline (always)] pub fn cfg_psel_vref (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_PSEL_A :: CFG_PSEL_VREF) } # [doc = "OANM1RTOP"] # [inline (always)] pub fn cfg_psel_oanm1rtop (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_PSEL_A :: CFG_PSEL_OANM1RTOP) } # [doc = "GPAMP_OUT_INT"] # [inline (always)] pub fn cfg_psel_gpamp_out_int (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_PSEL_A :: CFG_PSEL_GPAMP_OUT_INT) } # [doc = "VSS"] # [inline (always)] pub fn cfg_psel_vss (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_PSEL_A :: CFG_PSEL_VSS) } } # [doc = "Field `CFG_NSEL` reader - Negative OA input selection. Please refer to the device specific datasheet for exact channels available."] pub type CFG_NSEL_R = crate :: FieldReader < CFG_NSEL_A > ; # [doc = "Negative OA input selection. Please refer to the device specific datasheet for exact channels available.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum CFG_NSEL_A { # [doc = "0: NC"] CFG_NSEL_NC = 0 , # [doc = "1: EXTPIN0"] CFG_NSEL_EXTPIN0 = 1 , # [doc = "2: EXTPIN1"] CFG_NSEL_EXTPIN1 = 2 , # [doc = "3: OANP1RBOT"] CFG_NSEL_OANP1RBOT = 3 , # [doc = "4: OANRTAP"] CFG_NSEL_OANRTAP = 4 , # [doc = "5: OANRTOP"] CFG_NSEL_OANRTOP = 5 , # [doc = "6: SPARE"] CFG_NSEL_SPARE = 6 , } impl From < CFG_NSEL_A > for u8 { # [inline (always)] fn from (variant : CFG_NSEL_A) -> Self { variant as _ } } impl crate :: FieldSpec for CFG_NSEL_A { type Ux = u8 ; } impl CFG_NSEL_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < CFG_NSEL_A > { match self . bits { 0 => Some (CFG_NSEL_A :: CFG_NSEL_NC) , 1 => Some (CFG_NSEL_A :: CFG_NSEL_EXTPIN0) , 2 => Some (CFG_NSEL_A :: CFG_NSEL_EXTPIN1) , 3 => Some (CFG_NSEL_A :: CFG_NSEL_OANP1RBOT) , 4 => Some (CFG_NSEL_A :: CFG_NSEL_OANRTAP) , 5 => Some (CFG_NSEL_A :: CFG_NSEL_OANRTOP) , 6 => Some (CFG_NSEL_A :: CFG_NSEL_SPARE) , _ => None , } } # [doc = "NC"] # [inline (always)] pub fn is_cfg_nsel_nc (& self) -> bool { * self == CFG_NSEL_A :: CFG_NSEL_NC } # [doc = "EXTPIN0"] # [inline (always)] pub fn is_cfg_nsel_extpin0 (& self) -> bool { * self == CFG_NSEL_A :: CFG_NSEL_EXTPIN0 } # [doc = "EXTPIN1"] # [inline (always)] pub fn is_cfg_nsel_extpin1 (& self) -> bool { * self == CFG_NSEL_A :: CFG_NSEL_EXTPIN1 } # [doc = "OANP1RBOT"] # [inline (always)] pub fn is_cfg_nsel_oanp1rbot (& self) -> bool { * self == CFG_NSEL_A :: CFG_NSEL_OANP1RBOT } # [doc = "OANRTAP"] # [inline (always)] pub fn is_cfg_nsel_oanrtap (& self) -> bool { * self == CFG_NSEL_A :: CFG_NSEL_OANRTAP } # [doc = "OANRTOP"] # [inline (always)] pub fn is_cfg_nsel_oanrtop (& self) -> bool { * self == CFG_NSEL_A :: CFG_NSEL_OANRTOP } # [doc = "SPARE"] # [inline (always)] pub fn is_cfg_nsel_spare (& self) -> bool { * self == CFG_NSEL_A :: CFG_NSEL_SPARE } } # [doc = "Field `CFG_NSEL` writer - Negative OA input selection. Please refer to the device specific datasheet for exact channels available."] pub type CFG_NSEL_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 3 , O , CFG_NSEL_A > ; impl < 'a , REG , const O : u8 > CFG_NSEL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "NC"] # [inline (always)] pub fn cfg_nsel_nc (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_NSEL_A :: CFG_NSEL_NC) } # [doc = "EXTPIN0"] # [inline (always)] pub fn cfg_nsel_extpin0 (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_NSEL_A :: CFG_NSEL_EXTPIN0) } # [doc = "EXTPIN1"] # [inline (always)] pub fn cfg_nsel_extpin1 (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_NSEL_A :: CFG_NSEL_EXTPIN1) } # [doc = "OANP1RBOT"] # [inline (always)] pub fn cfg_nsel_oanp1rbot (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_NSEL_A :: CFG_NSEL_OANP1RBOT) } # [doc = "OANRTAP"] # [inline (always)] pub fn cfg_nsel_oanrtap (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_NSEL_A :: CFG_NSEL_OANRTAP) } # [doc = "OANRTOP"] # [inline (always)] pub fn cfg_nsel_oanrtop (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_NSEL_A :: CFG_NSEL_OANRTOP) } # [doc = "SPARE"] # [inline (always)] pub fn cfg_nsel_spare (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_NSEL_A :: CFG_NSEL_SPARE) } } # [doc = "Field `CFG_MSEL` reader - MSEL Mux selection. Please refer to the device specific datasheet for exact channels available."] pub type CFG_MSEL_R = crate :: FieldReader < CFG_MSEL_A > ; # [doc = "MSEL Mux selection. Please refer to the device specific datasheet for exact channels available.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum CFG_MSEL_A { # [doc = "0: NC"] CFG_MSEL_NC = 0 , # [doc = "1: EXTNPIN1"] CFG_MSEL_EXTNPIN1 = 1 , # [doc = "2: VSS"] CFG_MSEL_VSS = 2 , # [doc = "3: DAC12OUT"] CFG_MSEL_DAC12OUT = 3 , # [doc = "4: OANM1RTOP"] CFG_MSEL_OANM1RTOP = 4 , } impl From < CFG_MSEL_A > for u8 { # [inline (always)] fn from (variant : CFG_MSEL_A) -> Self { variant as _ } } impl crate :: FieldSpec for CFG_MSEL_A { type Ux = u8 ; } impl CFG_MSEL_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < CFG_MSEL_A > { match self . bits { 0 => Some (CFG_MSEL_A :: CFG_MSEL_NC) , 1 => Some (CFG_MSEL_A :: CFG_MSEL_EXTNPIN1) , 2 => Some (CFG_MSEL_A :: CFG_MSEL_VSS) , 3 => Some (CFG_MSEL_A :: CFG_MSEL_DAC12OUT) , 4 => Some (CFG_MSEL_A :: CFG_MSEL_OANM1RTOP) , _ => None , } } # [doc = "NC"] # [inline (always)] pub fn is_cfg_msel_nc (& self) -> bool { * self == CFG_MSEL_A :: CFG_MSEL_NC } # [doc = "EXTNPIN1"] # [inline (always)] pub fn is_cfg_msel_extnpin1 (& self) -> bool { * self == CFG_MSEL_A :: CFG_MSEL_EXTNPIN1 } # [doc = "VSS"] # [inline (always)] pub fn is_cfg_msel_vss (& self) -> bool { * self == CFG_MSEL_A :: CFG_MSEL_VSS } # [doc = "DAC12OUT"] # [inline (always)] pub fn is_cfg_msel_dac12out (& self) -> bool { * self == CFG_MSEL_A :: CFG_MSEL_DAC12OUT } # [doc = "OANM1RTOP"] # [inline (always)] pub fn is_cfg_msel_oanm1rtop (& self) -> bool { * self == CFG_MSEL_A :: CFG_MSEL_OANM1RTOP } } # [doc = "Field `CFG_MSEL` writer - MSEL Mux selection. Please refer to the device specific datasheet for exact channels available."] pub type CFG_MSEL_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 3 , O , CFG_MSEL_A > ; impl < 'a , REG , const O : u8 > CFG_MSEL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "NC"] # [inline (always)] pub fn cfg_msel_nc (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_MSEL_A :: CFG_MSEL_NC) } # [doc = "EXTNPIN1"] # [inline (always)] pub fn cfg_msel_extnpin1 (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_MSEL_A :: CFG_MSEL_EXTNPIN1) } # [doc = "VSS"] # [inline (always)] pub fn cfg_msel_vss (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_MSEL_A :: CFG_MSEL_VSS) } # [doc = "DAC12OUT"] # [inline (always)] pub fn cfg_msel_dac12out (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_MSEL_A :: CFG_MSEL_DAC12OUT) } # [doc = "OANM1RTOP"] # [inline (always)] pub fn cfg_msel_oanm1rtop (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_MSEL_A :: CFG_MSEL_OANM1RTOP) } } # [doc = "Field `CFG_GAIN` reader - Gain setting. Refer to TRM for enumeration information."] pub type CFG_GAIN_R = crate :: FieldReader ; # [doc = "Field `CFG_GAIN` writer - Gain setting. Refer to TRM for enumeration information."] pub type CFG_GAIN_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 3 , O > ; impl R { # [doc = "Bits 0:1 - Chopping enable."] # [inline (always)] pub fn cfg_chop (& self) -> CFG_CHOP_R { CFG_CHOP_R :: new ((self . bits & 3) as u8) } # [doc = "Bit 2 - Enable output pin"] # [inline (always)] pub fn cfg_outpin (& self) -> CFG_OUTPIN_R { CFG_OUTPIN_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bits 3:6 - Positive OA input selection. Please refer to the device specific datasheet for exact channels available."] # [inline (always)] pub fn cfg_psel (& self) -> CFG_PSEL_R { CFG_PSEL_R :: new (((self . bits >> 3) & 0x0f) as u8) } # [doc = "Bits 7:9 - Negative OA input selection. Please refer to the device specific datasheet for exact channels available."] # [inline (always)] pub fn cfg_nsel (& self) -> CFG_NSEL_R { CFG_NSEL_R :: new (((self . bits >> 7) & 7) as u8) } # [doc = "Bits 10:12 - MSEL Mux selection. Please refer to the device specific datasheet for exact channels available."] # [inline (always)] pub fn cfg_msel (& self) -> CFG_MSEL_R { CFG_MSEL_R :: new (((self . bits >> 10) & 7) as u8) } # [doc = "Bits 13:15 - Gain setting. Refer to TRM for enumeration information."] # [inline (always)] pub fn cfg_gain (& self) -> CFG_GAIN_R { CFG_GAIN_R :: new (((self . bits >> 13) & 7) as u8) } } impl W { # [doc = "Bits 0:1 - Chopping enable."] # [inline (always)] # [must_use] pub fn cfg_chop (& mut self) -> CFG_CHOP_W < CFG_SPEC , 0 > { CFG_CHOP_W :: new (self) } # [doc = "Bit 2 - Enable output pin"] # [inline (always)] # [must_use] pub fn cfg_outpin (& mut self) -> CFG_OUTPIN_W < CFG_SPEC , 2 > { CFG_OUTPIN_W :: new (self) } # [doc = "Bits 3:6 - Positive OA input selection. Please refer to the device specific datasheet for exact channels available."] # [inline (always)] # [must_use] pub fn cfg_psel (& mut self) -> CFG_PSEL_W < CFG_SPEC , 3 > { CFG_PSEL_W :: new (self) } # [doc = "Bits 7:9 - Negative OA input selection. Please refer to the device specific datasheet for exact channels available."] # [inline (always)] # [must_use] pub fn cfg_nsel (& mut self) -> CFG_NSEL_W < CFG_SPEC , 7 > { CFG_NSEL_W :: new (self) } # [doc = "Bits 10:12 - MSEL Mux selection. Please refer to the device specific datasheet for exact channels available."] # [inline (always)] # [must_use] pub fn cfg_msel (& mut self) -> CFG_MSEL_W < CFG_SPEC , 10 > { CFG_MSEL_W :: new (self) } # [doc = "Bits 13:15 - Gain setting. Refer to TRM for enumeration information."] # [inline (always)] # [must_use] pub fn cfg_gain (& mut self) -> CFG_GAIN_W <'_, CFG_SPEC , 13 > { CFG_GAIN_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Configuration Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CFG_SPEC ; impl crate :: RegisterSpec for CFG_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`cfg::R`](R) reader structure"] impl crate :: Readable for CFG_SPEC { } # [doc = "`write(|w| ..)` method takes [`cfg::W`](W) writer structure"] impl crate :: Writable for CFG_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets CFG to value 0"] impl crate :: Resettable for CFG_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/i2c1/mctr.rs:1:13076 [INFO] [stdout] | [INFO] [stdout] 1 | ..._use] pub fn mctr_mackoen (& mut self) -> MCTR_MACKOEN_W < MCTR_SPEC , 4 > { MCTR_MACKOEN_W :: new (self) } # [doc = "Bit 5 - Read on ... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `MCTR` reader"] pub type R = crate :: R < MCTR_SPEC > ; # [doc = "Register `MCTR` writer"] pub type W = crate :: W < MCTR_SPEC > ; # [doc = "Field `MCTR_BURSTRUN` reader - I2C Master Enable and start transaction"] pub type MCTR_BURSTRUN_R = crate :: BitReader < MCTR_BURSTRUN_A > ; # [doc = "I2C Master Enable and start transaction\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum MCTR_BURSTRUN_A { # [doc = "0: DISABLE"] MCTR_BURSTRUN_DISABLE = 0 , # [doc = "1: ENABLE"] MCTR_BURSTRUN_ENABLE = 1 , } impl From < MCTR_BURSTRUN_A > for bool { # [inline (always)] fn from (variant : MCTR_BURSTRUN_A) -> Self { variant as u8 != 0 } } impl MCTR_BURSTRUN_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> MCTR_BURSTRUN_A { match self . bits { false => MCTR_BURSTRUN_A :: MCTR_BURSTRUN_DISABLE , true => MCTR_BURSTRUN_A :: MCTR_BURSTRUN_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_mctr_burstrun_disable (& self) -> bool { * self == MCTR_BURSTRUN_A :: MCTR_BURSTRUN_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_mctr_burstrun_enable (& self) -> bool { * self == MCTR_BURSTRUN_A :: MCTR_BURSTRUN_ENABLE } } # [doc = "Field `MCTR_BURSTRUN` writer - I2C Master Enable and start transaction"] pub type MCTR_BURSTRUN_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , MCTR_BURSTRUN_A > ; impl < 'a , REG , const O : u8 > MCTR_BURSTRUN_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn mctr_burstrun_disable (self) -> & 'a mut crate :: W < REG > { self . variant (MCTR_BURSTRUN_A :: MCTR_BURSTRUN_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn mctr_burstrun_enable (self) -> & 'a mut crate :: W < REG > { self . variant (MCTR_BURSTRUN_A :: MCTR_BURSTRUN_ENABLE) } } # [doc = "Field `MCTR_START` reader - Generate START"] pub type MCTR_START_R = crate :: BitReader < MCTR_START_A > ; # [doc = "Generate START\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum MCTR_START_A { # [doc = "0: DISABLE"] MCTR_START_DISABLE = 0 , # [doc = "1: ENABLE"] MCTR_START_ENABLE = 1 , } impl From < MCTR_START_A > for bool { # [inline (always)] fn from (variant : MCTR_START_A) -> Self { variant as u8 != 0 } } impl MCTR_START_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> MCTR_START_A { match self . bits { false => MCTR_START_A :: MCTR_START_DISABLE , true => MCTR_START_A :: MCTR_START_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_mctr_start_disable (& self) -> bool { * self == MCTR_START_A :: MCTR_START_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_mctr_start_enable (& self) -> bool { * self == MCTR_START_A :: MCTR_START_ENABLE } } # [doc = "Field `MCTR_START` writer - Generate START"] pub type MCTR_START_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , MCTR_START_A > ; impl < 'a , REG , const O : u8 > MCTR_START_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn mctr_start_disable (self) -> & 'a mut crate :: W < REG > { self . variant (MCTR_START_A :: MCTR_START_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn mctr_start_enable (self) -> & 'a mut crate :: W < REG > { self . variant (MCTR_START_A :: MCTR_START_ENABLE) } } # [doc = "Field `MCTR_STOP` reader - Generate STOP"] pub type MCTR_STOP_R = crate :: BitReader < MCTR_STOP_A > ; # [doc = "Generate STOP\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum MCTR_STOP_A { # [doc = "0: DISABLE"] MCTR_STOP_DISABLE = 0 , # [doc = "1: ENABLE"] MCTR_STOP_ENABLE = 1 , } impl From < MCTR_STOP_A > for bool { # [inline (always)] fn from (variant : MCTR_STOP_A) -> Self { variant as u8 != 0 } } impl MCTR_STOP_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> MCTR_STOP_A { match self . bits { false => MCTR_STOP_A :: MCTR_STOP_DISABLE , true => MCTR_STOP_A :: MCTR_STOP_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_mctr_stop_disable (& self) -> bool { * self == MCTR_STOP_A :: MCTR_STOP_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_mctr_stop_enable (& self) -> bool { * self == MCTR_STOP_A :: MCTR_STOP_ENABLE } } # [doc = "Field `MCTR_STOP` writer - Generate STOP"] pub type MCTR_STOP_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , MCTR_STOP_A > ; impl < 'a , REG , const O : u8 > MCTR_STOP_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn mctr_stop_disable (self) -> & 'a mut crate :: W < REG > { self . variant (MCTR_STOP_A :: MCTR_STOP_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn mctr_stop_enable (self) -> & 'a mut crate :: W < REG > { self . variant (MCTR_STOP_A :: MCTR_STOP_ENABLE) } } # [doc = "Field `MCTR_ACK` reader - Data Acknowledge Enable. Software needs to configure this bit to send the ACK or NACK. See field decoding in Table: MCTR Field decoding."] pub type MCTR_ACK_R = crate :: BitReader < MCTR_ACK_A > ; # [doc = "Data Acknowledge Enable. Software needs to configure this bit to send the ACK or NACK. See field decoding in Table: MCTR Field decoding.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum MCTR_ACK_A { # [doc = "0: DISABLE"] MCTR_ACK_DISABLE = 0 , # [doc = "1: ENABLE"] MCTR_ACK_ENABLE = 1 , } impl From < MCTR_ACK_A > for bool { # [inline (always)] fn from (variant : MCTR_ACK_A) -> Self { variant as u8 != 0 } } impl MCTR_ACK_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> MCTR_ACK_A { match self . bits { false => MCTR_ACK_A :: MCTR_ACK_DISABLE , true => MCTR_ACK_A :: MCTR_ACK_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_mctr_ack_disable (& self) -> bool { * self == MCTR_ACK_A :: MCTR_ACK_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_mctr_ack_enable (& self) -> bool { * self == MCTR_ACK_A :: MCTR_ACK_ENABLE } } # [doc = "Field `MCTR_ACK` writer - Data Acknowledge Enable. Software needs to configure this bit to send the ACK or NACK. See field decoding in Table: MCTR Field decoding."] pub type MCTR_ACK_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , MCTR_ACK_A > ; impl < 'a , REG , const O : u8 > MCTR_ACK_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn mctr_ack_disable (self) -> & 'a mut crate :: W < REG > { self . variant (MCTR_ACK_A :: MCTR_ACK_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn mctr_ack_enable (self) -> & 'a mut crate :: W < REG > { self . variant (MCTR_ACK_A :: MCTR_ACK_ENABLE) } } # [doc = "Field `MCTR_MACKOEN` reader - Master ACK overrride Enable"] pub type MCTR_MACKOEN_R = crate :: BitReader < MCTR_MACKOEN_A > ; # [doc = "Master ACK overrride Enable\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum MCTR_MACKOEN_A { # [doc = "0: DISABLE"] MCTR_MACKOEN_DISABLE = 0 , # [doc = "1: ENABLE"] MCTR_MACKOEN_ENABLE = 1 , } impl From < MCTR_MACKOEN_A > for bool { # [inline (always)] fn from (variant : MCTR_MACKOEN_A) -> Self { variant as u8 != 0 } } impl MCTR_MACKOEN_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> MCTR_MACKOEN_A { match self . bits { false => MCTR_MACKOEN_A :: MCTR_MACKOEN_DISABLE , true => MCTR_MACKOEN_A :: MCTR_MACKOEN_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_mctr_mackoen_disable (& self) -> bool { * self == MCTR_MACKOEN_A :: MCTR_MACKOEN_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_mctr_mackoen_enable (& self) -> bool { * self == MCTR_MACKOEN_A :: MCTR_MACKOEN_ENABLE } } # [doc = "Field `MCTR_MACKOEN` writer - Master ACK overrride Enable"] pub type MCTR_MACKOEN_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , MCTR_MACKOEN_A > ; impl < 'a , REG , const O : u8 > MCTR_MACKOEN_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn mctr_mackoen_disable (self) -> & 'a mut crate :: W < REG > { self . variant (MCTR_MACKOEN_A :: MCTR_MACKOEN_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn mctr_mackoen_enable (self) -> & 'a mut crate :: W < REG > { self . variant (MCTR_MACKOEN_A :: MCTR_MACKOEN_ENABLE) } } # [doc = "Field `MCTR_RD_ON_TXEMPTY` reader - Read on TX Empty"] pub type MCTR_RD_ON_TXEMPTY_R = crate :: BitReader < MCTR_RD_ON_TXEMPTY_A > ; # [doc = "Read on TX Empty\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum MCTR_RD_ON_TXEMPTY_A { # [doc = "0: DISABLE"] MCTR_RD_ON_TXEMPTY_DISABLE = 0 , # [doc = "1: ENABLE"] MCTR_RD_ON_TXEMPTY_ENABLE = 1 , } impl From < MCTR_RD_ON_TXEMPTY_A > for bool { # [inline (always)] fn from (variant : MCTR_RD_ON_TXEMPTY_A) -> Self { variant as u8 != 0 } } impl MCTR_RD_ON_TXEMPTY_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> MCTR_RD_ON_TXEMPTY_A { match self . bits { false => MCTR_RD_ON_TXEMPTY_A :: MCTR_RD_ON_TXEMPTY_DISABLE , true => MCTR_RD_ON_TXEMPTY_A :: MCTR_RD_ON_TXEMPTY_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_mctr_rd_on_txempty_disable (& self) -> bool { * self == MCTR_RD_ON_TXEMPTY_A :: MCTR_RD_ON_TXEMPTY_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_mctr_rd_on_txempty_enable (& self) -> bool { * self == MCTR_RD_ON_TXEMPTY_A :: MCTR_RD_ON_TXEMPTY_ENABLE } } # [doc = "Field `MCTR_RD_ON_TXEMPTY` writer - Read on TX Empty"] pub type MCTR_RD_ON_TXEMPTY_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , MCTR_RD_ON_TXEMPTY_A > ; impl < 'a , REG , const O : u8 > MCTR_RD_ON_TXEMPTY_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn mctr_rd_on_txempty_disable (self) -> & 'a mut crate :: W < REG > { self . variant (MCTR_RD_ON_TXEMPTY_A :: MCTR_RD_ON_TXEMPTY_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn mctr_rd_on_txempty_enable (self) -> & 'a mut crate :: W < REG > { self . variant (MCTR_RD_ON_TXEMPTY_A :: MCTR_RD_ON_TXEMPTY_ENABLE) } } # [doc = "Field `MCTR_MBLEN` reader - I2C transaction length This field contains the programmed length of bytes of the Transaction."] pub type MCTR_MBLEN_R = crate :: FieldReader < u16 > ; # [doc = "Field `MCTR_MBLEN` writer - I2C transaction length This field contains the programmed length of bytes of the Transaction."] pub type MCTR_MBLEN_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 12 , O , u16 > ; impl R { # [doc = "Bit 0 - I2C Master Enable and start transaction"] # [inline (always)] pub fn mctr_burstrun (& self) -> MCTR_BURSTRUN_R { MCTR_BURSTRUN_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - Generate START"] # [inline (always)] pub fn mctr_start (& self) -> MCTR_START_R { MCTR_START_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - Generate STOP"] # [inline (always)] pub fn mctr_stop (& self) -> MCTR_STOP_R { MCTR_STOP_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - Data Acknowledge Enable. Software needs to configure this bit to send the ACK or NACK. See field decoding in Table: MCTR Field decoding."] # [inline (always)] pub fn mctr_ack (& self) -> MCTR_ACK_R { MCTR_ACK_R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - Master ACK overrride Enable"] # [inline (always)] pub fn mctr_mackoen (& self) -> MCTR_MACKOEN_R { MCTR_MACKOEN_R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - Read on TX Empty"] # [inline (always)] pub fn mctr_rd_on_txempty (& self) -> MCTR_RD_ON_TXEMPTY_R { MCTR_RD_ON_TXEMPTY_R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bits 16:27 - I2C transaction length This field contains the programmed length of bytes of the Transaction."] # [inline (always)] pub fn mctr_mblen (& self) -> MCTR_MBLEN_R { MCTR_MBLEN_R :: new (((self . bits >> 16) & 0x0fff) as u16) } } impl W { # [doc = "Bit 0 - I2C Master Enable and start transaction"] # [inline (always)] # [must_use] pub fn mctr_burstrun (& mut self) -> MCTR_BURSTRUN_W < MCTR_SPEC , 0 > { MCTR_BURSTRUN_W :: new (self) } # [doc = "Bit 1 - Generate START"] # [inline (always)] # [must_use] pub fn mctr_start (& mut self) -> MCTR_START_W < MCTR_SPEC , 1 > { MCTR_START_W :: new (self) } # [doc = "Bit 2 - Generate STOP"] # [inline (always)] # [must_use] pub fn mctr_stop (& mut self) -> MCTR_STOP_W < MCTR_SPEC , 2 > { MCTR_STOP_W :: new (self) } # [doc = "Bit 3 - Data Acknowledge Enable. Software needs to configure this bit to send the ACK or NACK. See field decoding in Table: MCTR Field decoding."] # [inline (always)] # [must_use] pub fn mctr_ack (& mut self) -> MCTR_ACK_W < MCTR_SPEC , 3 > { MCTR_ACK_W :: new (self) } # [doc = "Bit 4 - Master ACK overrride Enable"] # [inline (always)] # [must_use] pub fn mctr_mackoen (& mut self) -> MCTR_MACKOEN_W <'_, MCTR_SPEC , 4 > { MCTR_MACKOEN_W :: new (self) } # [doc = "Bit 5 - Read on TX Empty"] # [inline (always)] # [must_use] pub fn mctr_rd_on_txempty (& mut self) -> MCTR_RD_ON_TXEMPTY_W < MCTR_SPEC , 5 > { MCTR_RD_ON_TXEMPTY_W :: new (self) } # [doc = "Bits 16:27 - I2C transaction length This field contains the programmed length of bytes of the Transaction."] # [inline (always)] # [must_use] pub fn mctr_mblen (& mut self) -> MCTR_MBLEN_W < MCTR_SPEC , 16 > { MCTR_MBLEN_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "I2C Master Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mctr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mctr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct MCTR_SPEC ; impl crate :: RegisterSpec for MCTR_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`mctr::R`](R) reader structure"] impl crate :: Readable for MCTR_SPEC { } # [doc = "`write(|w| ..)` method takes [`mctr::W`](W) writer structure"] impl crate :: Writable for MCTR_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets MCTR to value 0"] impl crate :: Resettable for MCTR_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/i2c0/int_event0_iset.rs:1:38890 [INFO] [stdout] | [INFO] [stdout] 1 | ...t_mtxfifotrg (& mut self) -> INT_EVENT0_ISET_MTXFIFOTRG_W < INT_EVENT0_ISET_SPEC , 3 > { INT_EVENT0_ISET_MTXFIFOTRG_W :: new (self) } ... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `INT_EVENT0_ISET` writer"] pub type W = crate :: W < INT_EVENT0_ISET_SPEC > ; # [doc = "Master Receive Data Interrupt Signals that a byte has been received\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_MRXDONE_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_MRXDONE_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_MRXDONE_SET = 1 , } impl From < INT_EVENT0_ISET_MRXDONE_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_MRXDONE_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_MRXDONE` writer - Master Receive Data Interrupt Signals that a byte has been received"] pub type INT_EVENT0_ISET_MRXDONE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_MRXDONE_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_MRXDONE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_mrxdone_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MRXDONE_AW :: INT_EVENT0_ISET_MRXDONE_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_mrxdone_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MRXDONE_AW :: INT_EVENT0_ISET_MRXDONE_SET) } } # [doc = "Master Transmit Transaction completed Interrupt\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_MTXDONE_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_MTXDONE_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_MTXDONE_SET = 1 , } impl From < INT_EVENT0_ISET_MTXDONE_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_MTXDONE_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_MTXDONE` writer - Master Transmit Transaction completed Interrupt"] pub type INT_EVENT0_ISET_MTXDONE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_MTXDONE_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_MTXDONE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_mtxdone_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MTXDONE_AW :: INT_EVENT0_ISET_MTXDONE_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_mtxdone_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MTXDONE_AW :: INT_EVENT0_ISET_MTXDONE_SET) } } # [doc = "Master Receive FIFO Trigger Trigger when RX FIFO contains &gt;= defined bytes\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_MRXFIFOTRG_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_MRXFIFOTRG_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_MRXFIFOTRG_SET = 1 , } impl From < INT_EVENT0_ISET_MRXFIFOTRG_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_MRXFIFOTRG_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_MRXFIFOTRG` writer - Master Receive FIFO Trigger Trigger when RX FIFO contains &gt;= defined bytes"] pub type INT_EVENT0_ISET_MRXFIFOTRG_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_MRXFIFOTRG_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_MRXFIFOTRG_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_mrxfifotrg_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MRXFIFOTRG_AW :: INT_EVENT0_ISET_MRXFIFOTRG_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_mrxfifotrg_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MRXFIFOTRG_AW :: INT_EVENT0_ISET_MRXFIFOTRG_SET) } } # [doc = "Master Transmit FIFO Trigger Trigger when Transmit FIFO contains &lt;= defined bytes\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_MTXFIFOTRG_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_MTXFIFOTRG_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_MTXFIFOTRG_SET = 1 , } impl From < INT_EVENT0_ISET_MTXFIFOTRG_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_MTXFIFOTRG_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_MTXFIFOTRG` writer - Master Transmit FIFO Trigger Trigger when Transmit FIFO contains &lt;= defined bytes"] pub type INT_EVENT0_ISET_MTXFIFOTRG_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_MTXFIFOTRG_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_MTXFIFOTRG_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_mtxfifotrg_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MTXFIFOTRG_AW :: INT_EVENT0_ISET_MTXFIFOTRG_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_mtxfifotrg_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MTXFIFOTRG_AW :: INT_EVENT0_ISET_MTXFIFOTRG_SET) } } # [doc = "RXFIFO full event.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_MRXFIFOFULL_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_MRXFIFOFULL_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_MRXFIFOFULL_SET = 1 , } impl From < INT_EVENT0_ISET_MRXFIFOFULL_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_MRXFIFOFULL_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_MRXFIFOFULL` writer - RXFIFO full event."] pub type INT_EVENT0_ISET_MRXFIFOFULL_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_MRXFIFOFULL_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_MRXFIFOFULL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_mrxfifofull_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MRXFIFOFULL_AW :: INT_EVENT0_ISET_MRXFIFOFULL_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_mrxfifofull_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MRXFIFOFULL_AW :: INT_EVENT0_ISET_MRXFIFOFULL_SET) } } # [doc = "Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_MTXEMPTY_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_MTXEMPTY_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_MTXEMPTY_SET = 1 , } impl From < INT_EVENT0_ISET_MTXEMPTY_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_MTXEMPTY_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_MTXEMPTY` writer - Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode."] pub type INT_EVENT0_ISET_MTXEMPTY_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_MTXEMPTY_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_MTXEMPTY_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_mtxempty_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MTXEMPTY_AW :: INT_EVENT0_ISET_MTXEMPTY_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_mtxempty_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MTXEMPTY_AW :: INT_EVENT0_ISET_MTXEMPTY_SET) } } # [doc = "Address/Data NACK Interrupt\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_MNACK_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_MNACK_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_MNACK_SET = 1 , } impl From < INT_EVENT0_ISET_MNACK_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_MNACK_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_MNACK` writer - Address/Data NACK Interrupt"] pub type INT_EVENT0_ISET_MNACK_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_MNACK_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_MNACK_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_mnack_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MNACK_AW :: INT_EVENT0_ISET_MNACK_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_mnack_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MNACK_AW :: INT_EVENT0_ISET_MNACK_SET) } } # [doc = "START Detection Interrupt\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_MSTART_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_MSTART_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_MSTART_SET = 1 , } impl From < INT_EVENT0_ISET_MSTART_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_MSTART_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_MSTART` writer - START Detection Interrupt"] pub type INT_EVENT0_ISET_MSTART_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_MSTART_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_MSTART_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_mstart_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MSTART_AW :: INT_EVENT0_ISET_MSTART_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_mstart_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MSTART_AW :: INT_EVENT0_ISET_MSTART_SET) } } # [doc = "STOP Detection Interrupt\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_MSTOP_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_MSTOP_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_MSTOP_SET = 1 , } impl From < INT_EVENT0_ISET_MSTOP_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_MSTOP_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_MSTOP` writer - STOP Detection Interrupt"] pub type INT_EVENT0_ISET_MSTOP_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_MSTOP_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_MSTOP_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_mstop_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MSTOP_AW :: INT_EVENT0_ISET_MSTOP_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_mstop_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MSTOP_AW :: INT_EVENT0_ISET_MSTOP_SET) } } # [doc = "Arbitration Lost Interrupt\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_MARBLOST_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_MARBLOST_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_MARBLOST_SET = 1 , } impl From < INT_EVENT0_ISET_MARBLOST_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_MARBLOST_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_MARBLOST` writer - Arbitration Lost Interrupt"] pub type INT_EVENT0_ISET_MARBLOST_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_MARBLOST_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_MARBLOST_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_marblost_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MARBLOST_AW :: INT_EVENT0_ISET_MARBLOST_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_marblost_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MARBLOST_AW :: INT_EVENT0_ISET_MARBLOST_SET) } } # [doc = "DMA Done 1 on Event Channel 2\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_MDMA_DONE1_2_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_MDMA_DONE1_2_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_MDMA_DONE1_2_SET = 1 , } impl From < INT_EVENT0_ISET_MDMA_DONE1_2_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_MDMA_DONE1_2_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_MDMA_DONE1_2` writer - DMA Done 1 on Event Channel 2"] pub type INT_EVENT0_ISET_MDMA_DONE1_2_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_MDMA_DONE1_2_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_MDMA_DONE1_2_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_mdma_done1_2_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MDMA_DONE1_2_AW :: INT_EVENT0_ISET_MDMA_DONE1_2_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_mdma_done1_2_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MDMA_DONE1_2_AW :: INT_EVENT0_ISET_MDMA_DONE1_2_SET) } } # [doc = "DMA Done 1 on Event Channel 3\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_MDMA_DONE1_3_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_MDMA_DONE1_3_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_MDMA_DONE1_3_SET = 1 , } impl From < INT_EVENT0_ISET_MDMA_DONE1_3_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_MDMA_DONE1_3_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_MDMA_DONE1_3` writer - DMA Done 1 on Event Channel 3"] pub type INT_EVENT0_ISET_MDMA_DONE1_3_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_MDMA_DONE1_3_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_MDMA_DONE1_3_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_mdma_done1_3_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MDMA_DONE1_3_AW :: INT_EVENT0_ISET_MDMA_DONE1_3_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_mdma_done1_3_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MDMA_DONE1_3_AW :: INT_EVENT0_ISET_MDMA_DONE1_3_SET) } } # [doc = "Master RX Pec Error Interrupt\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_MPEC_RX_ERR_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_MPEC_RX_ERR_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_MPEC_RX_ERR_SET = 1 , } impl From < INT_EVENT0_ISET_MPEC_RX_ERR_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_MPEC_RX_ERR_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_MPEC_RX_ERR` writer - Master RX Pec Error Interrupt"] pub type INT_EVENT0_ISET_MPEC_RX_ERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_MPEC_RX_ERR_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_MPEC_RX_ERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_mpec_rx_err_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MPEC_RX_ERR_AW :: INT_EVENT0_ISET_MPEC_RX_ERR_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_mpec_rx_err_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MPEC_RX_ERR_AW :: INT_EVENT0_ISET_MPEC_RX_ERR_SET) } } # [doc = "Timeout A interrupt\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_TIMEOUTA_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_TIMEOUTA_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_TIMEOUTA_SET = 1 , } impl From < INT_EVENT0_ISET_TIMEOUTA_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_TIMEOUTA_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_TIMEOUTA` writer - Timeout A interrupt"] pub type INT_EVENT0_ISET_TIMEOUTA_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_TIMEOUTA_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_TIMEOUTA_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_timeouta_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_TIMEOUTA_AW :: INT_EVENT0_ISET_TIMEOUTA_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_timeouta_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_TIMEOUTA_AW :: INT_EVENT0_ISET_TIMEOUTA_SET) } } # [doc = "Timeout B Interrupt\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_TIMEOUTB_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_TIMEOUTB_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_TIMEOUTB_SET = 1 , } impl From < INT_EVENT0_ISET_TIMEOUTB_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_TIMEOUTB_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_TIMEOUTB` writer - Timeout B Interrupt"] pub type INT_EVENT0_ISET_TIMEOUTB_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_TIMEOUTB_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_TIMEOUTB_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_timeoutb_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_TIMEOUTB_AW :: INT_EVENT0_ISET_TIMEOUTB_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_timeoutb_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_TIMEOUTB_AW :: INT_EVENT0_ISET_TIMEOUTB_SET) } } # [doc = "Slave Receive Data Interrupt Signals that a byte has been received\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_SRXDONE_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_SRXDONE_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_SRXDONE_SET = 1 , } impl From < INT_EVENT0_ISET_SRXDONE_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_SRXDONE_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_SRXDONE` writer - Slave Receive Data Interrupt Signals that a byte has been received"] pub type INT_EVENT0_ISET_SRXDONE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_SRXDONE_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_SRXDONE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_srxdone_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_SRXDONE_AW :: INT_EVENT0_ISET_SRXDONE_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_srxdone_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_SRXDONE_AW :: INT_EVENT0_ISET_SRXDONE_SET) } } # [doc = "Slave Transmit Transaction completed Interrupt\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_STXDONE_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_STXDONE_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_STXDONE_SET = 1 , } impl From < INT_EVENT0_ISET_STXDONE_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_STXDONE_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_STXDONE` writer - Slave Transmit Transaction completed Interrupt"] pub type INT_EVENT0_ISET_STXDONE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_STXDONE_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_STXDONE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_stxdone_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_STXDONE_AW :: INT_EVENT0_ISET_STXDONE_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_stxdone_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_STXDONE_AW :: INT_EVENT0_ISET_STXDONE_SET) } } # [doc = "Slave Receive FIFO Trigger\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_SRXFIFOTRG_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_SRXFIFOTRG_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_SRXFIFOTRG_SET = 1 , } impl From < INT_EVENT0_ISET_SRXFIFOTRG_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_SRXFIFOTRG_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_SRXFIFOTRG` writer - Slave Receive FIFO Trigger"] pub type INT_EVENT0_ISET_SRXFIFOTRG_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_SRXFIFOTRG_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_SRXFIFOTRG_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_srxfifotrg_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_SRXFIFOTRG_AW :: INT_EVENT0_ISET_SRXFIFOTRG_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_srxfifotrg_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_SRXFIFOTRG_AW :: INT_EVENT0_ISET_SRXFIFOTRG_SET) } } # [doc = "Slave Transmit FIFO Trigger\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_STXFIFOTRG_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_STXFIFOTRG_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_STXFIFOTRG_SET = 1 , } impl From < INT_EVENT0_ISET_STXFIFOTRG_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_STXFIFOTRG_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_STXFIFOTRG` writer - Slave Transmit FIFO Trigger"] pub type INT_EVENT0_ISET_STXFIFOTRG_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_STXFIFOTRG_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_STXFIFOTRG_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_stxfifotrg_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_STXFIFOTRG_AW :: INT_EVENT0_ISET_STXFIFOTRG_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_stxfifotrg_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_STXFIFOTRG_AW :: INT_EVENT0_ISET_STXFIFOTRG_SET) } } # [doc = "RXFIFO full event. This interrupt is set if an RX FIFO is full.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_SRXFIFOFULL_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_SRXFIFOFULL_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_SRXFIFOFULL_SET = 1 , } impl From < INT_EVENT0_ISET_SRXFIFOFULL_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_SRXFIFOFULL_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_SRXFIFOFULL` writer - RXFIFO full event. This interrupt is set if an RX FIFO is full."] pub type INT_EVENT0_ISET_SRXFIFOFULL_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_SRXFIFOFULL_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_SRXFIFOFULL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_srxfifofull_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_SRXFIFOFULL_AW :: INT_EVENT0_ISET_SRXFIFOFULL_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_srxfifofull_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_SRXFIFOFULL_AW :: INT_EVENT0_ISET_SRXFIFOFULL_SET) } } # [doc = "Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_STXEMPTY_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_STXEMPTY_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_STXEMPTY_SET = 1 , } impl From < INT_EVENT0_ISET_STXEMPTY_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_STXEMPTY_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_STXEMPTY` writer - Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode."] pub type INT_EVENT0_ISET_STXEMPTY_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_STXEMPTY_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_STXEMPTY_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_stxempty_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_STXEMPTY_AW :: INT_EVENT0_ISET_STXEMPTY_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_stxempty_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_STXEMPTY_AW :: INT_EVENT0_ISET_STXEMPTY_SET) } } # [doc = "Start Condition Interrupt\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_SSTART_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_SSTART_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_SSTART_SET = 1 , } impl From < INT_EVENT0_ISET_SSTART_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_SSTART_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_SSTART` writer - Start Condition Interrupt"] pub type INT_EVENT0_ISET_SSTART_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_SSTART_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_SSTART_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_sstart_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_SSTART_AW :: INT_EVENT0_ISET_SSTART_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_sstart_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_SSTART_AW :: INT_EVENT0_ISET_SSTART_SET) } } # [doc = "Stop Condition Interrupt\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_SSTOP_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_SSTOP_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_SSTOP_SET = 1 , } impl From < INT_EVENT0_ISET_SSTOP_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_SSTOP_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_SSTOP` writer - Stop Condition Interrupt"] pub type INT_EVENT0_ISET_SSTOP_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_SSTOP_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_SSTOP_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_sstop_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_SSTOP_AW :: INT_EVENT0_ISET_SSTOP_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_sstop_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_SSTOP_AW :: INT_EVENT0_ISET_SSTOP_SET) } } # [doc = "General Call Interrupt\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_SGENCALL_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_SGENCALL_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_SGENCALL_SET = 1 , } impl From < INT_EVENT0_ISET_SGENCALL_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_SGENCALL_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_SGENCALL` writer - General Call Interrupt"] pub type INT_EVENT0_ISET_SGENCALL_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_SGENCALL_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_SGENCALL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_sgencall_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_SGENCALL_AW :: INT_EVENT0_ISET_SGENCALL_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_sgencall_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_SGENCALL_AW :: INT_EVENT0_ISET_SGENCALL_SET) } } # [doc = "DMA Done 1 on Event Channel 2\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_SDMA_DONE1_2_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_SDMA_DONE1_2_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_SDMA_DONE1_2_SET = 1 , } impl From < INT_EVENT0_ISET_SDMA_DONE1_2_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_SDMA_DONE1_2_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_SDMA_DONE1_2` writer - DMA Done 1 on Event Channel 2"] pub type INT_EVENT0_ISET_SDMA_DONE1_2_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_SDMA_DONE1_2_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_SDMA_DONE1_2_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_sdma_done1_2_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_SDMA_DONE1_2_AW :: INT_EVENT0_ISET_SDMA_DONE1_2_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_sdma_done1_2_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_SDMA_DONE1_2_AW :: INT_EVENT0_ISET_SDMA_DONE1_2_SET) } } # [doc = "DMA Done 1 on Event Channel 3\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_SDMA_DONE1_3_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_SDMA_DONE1_3_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_SDMA_DONE1_3_SET = 1 , } impl From < INT_EVENT0_ISET_SDMA_DONE1_3_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_SDMA_DONE1_3_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_SDMA_DONE1_3` writer - DMA Done 1 on Event Channel 3"] pub type INT_EVENT0_ISET_SDMA_DONE1_3_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_SDMA_DONE1_3_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_SDMA_DONE1_3_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_sdma_done1_3_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_SDMA_DONE1_3_AW :: INT_EVENT0_ISET_SDMA_DONE1_3_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_sdma_done1_3_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_SDMA_DONE1_3_AW :: INT_EVENT0_ISET_SDMA_DONE1_3_SET) } } # [doc = "Slave RX Pec Error Interrupt\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_SPEC_RX_ERR_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_SPEC_RX_ERR_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_SPEC_RX_ERR_SET = 1 , } impl From < INT_EVENT0_ISET_SPEC_RX_ERR_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_SPEC_RX_ERR_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_SPEC_RX_ERR` writer - Slave RX Pec Error Interrupt"] pub type INT_EVENT0_ISET_SPEC_RX_ERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_SPEC_RX_ERR_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_SPEC_RX_ERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_spec_rx_err_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_SPEC_RX_ERR_AW :: INT_EVENT0_ISET_SPEC_RX_ERR_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_spec_rx_err_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_SPEC_RX_ERR_AW :: INT_EVENT0_ISET_SPEC_RX_ERR_SET) } } # [doc = "Slave TX FIFO underflow\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_STX_UNFL_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_STX_UNFL_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_STX_UNFL_SET = 1 , } impl From < INT_EVENT0_ISET_STX_UNFL_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_STX_UNFL_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_STX_UNFL` writer - Slave TX FIFO underflow"] pub type INT_EVENT0_ISET_STX_UNFL_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_STX_UNFL_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_STX_UNFL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_stx_unfl_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_STX_UNFL_AW :: INT_EVENT0_ISET_STX_UNFL_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_stx_unfl_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_STX_UNFL_AW :: INT_EVENT0_ISET_STX_UNFL_SET) } } # [doc = "Slave RX FIFO overflow\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_SRX_OVFL_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_SRX_OVFL_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_SRX_OVFL_SET = 1 , } impl From < INT_EVENT0_ISET_SRX_OVFL_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_SRX_OVFL_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_SRX_OVFL` writer - Slave RX FIFO overflow"] pub type INT_EVENT0_ISET_SRX_OVFL_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_SRX_OVFL_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_SRX_OVFL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_srx_ovfl_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_SRX_OVFL_AW :: INT_EVENT0_ISET_SRX_OVFL_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_srx_ovfl_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_SRX_OVFL_AW :: INT_EVENT0_ISET_SRX_OVFL_SET) } } # [doc = "Slave Arbitration Lost\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_SARBLOST_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_SARBLOST_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_SARBLOST_SET = 1 , } impl From < INT_EVENT0_ISET_SARBLOST_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_SARBLOST_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_SARBLOST` writer - Slave Arbitration Lost"] pub type INT_EVENT0_ISET_SARBLOST_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_SARBLOST_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_SARBLOST_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_sarblost_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_SARBLOST_AW :: INT_EVENT0_ISET_SARBLOST_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_sarblost_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_SARBLOST_AW :: INT_EVENT0_ISET_SARBLOST_SET) } } # [doc = "Interrupt overflow\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_INTR_OVFL_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_INTR_OVFL_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_INTR_OVFL_SET = 1 , } impl From < INT_EVENT0_ISET_INTR_OVFL_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_INTR_OVFL_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_INTR_OVFL` writer - Interrupt overflow"] pub type INT_EVENT0_ISET_INTR_OVFL_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_INTR_OVFL_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_INTR_OVFL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_intr_ovfl_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_INTR_OVFL_AW :: INT_EVENT0_ISET_INTR_OVFL_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_intr_ovfl_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_INTR_OVFL_AW :: INT_EVENT0_ISET_INTR_OVFL_SET) } } impl W { # [doc = "Bit 0 - Master Receive Data Interrupt Signals that a byte has been received"] # [inline (always)] # [must_use] pub fn int_event0_iset_mrxdone (& mut self) -> INT_EVENT0_ISET_MRXDONE_W < INT_EVENT0_ISET_SPEC , 0 > { INT_EVENT0_ISET_MRXDONE_W :: new (self) } # [doc = "Bit 1 - Master Transmit Transaction completed Interrupt"] # [inline (always)] # [must_use] pub fn int_event0_iset_mtxdone (& mut self) -> INT_EVENT0_ISET_MTXDONE_W < INT_EVENT0_ISET_SPEC , 1 > { INT_EVENT0_ISET_MTXDONE_W :: new (self) } # [doc = "Bit 2 - Master Receive FIFO Trigger Trigger when RX FIFO contains &gt;= defined bytes"] # [inline (always)] # [must_use] pub fn int_event0_iset_mrxfifotrg (& mut self) -> INT_EVENT0_ISET_MRXFIFOTRG_W < INT_EVENT0_ISET_SPEC , 2 > { INT_EVENT0_ISET_MRXFIFOTRG_W :: new (self) } # [doc = "Bit 3 - Master Transmit FIFO Trigger Trigger when Transmit FIFO contains &lt;= defined bytes"] # [inline (always)] # [must_use] pub fn int_event0_iset_mtxfifotrg (& mut self) -> INT_EVENT0_ISET_MTXFIFOTRG_W <'_, INT_EVENT0_ISET_SPEC , 3 > { INT_EVENT0_ISET_MTXFIFOTRG_W :: new (self) } # [doc = "Bit 4 - RXFIFO full event."] # [inline (always)] # [must_use] pub fn int_event0_iset_mrxfifofull (& mut self) -> INT_EVENT0_ISET_MRXFIFOFULL_W < INT_EVENT0_ISET_SPEC , 4 > { INT_EVENT0_ISET_MRXFIFOFULL_W :: new (self) } # [doc = "Bit 5 - Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode."] # [inline (always)] # [must_use] pub fn int_event0_iset_mtxempty (& mut self) -> INT_EVENT0_ISET_MTXEMPTY_W < INT_EVENT0_ISET_SPEC , 5 > { INT_EVENT0_ISET_MTXEMPTY_W :: new (self) } # [doc = "Bit 7 - Address/Data NACK Interrupt"] # [inline (always)] # [must_use] pub fn int_event0_iset_mnack (& mut self) -> INT_EVENT0_ISET_MNACK_W < INT_EVENT0_ISET_SPEC , 7 > { INT_EVENT0_ISET_MNACK_W :: new (self) } # [doc = "Bit 8 - START Detection Interrupt"] # [inline (always)] # [must_use] pub fn int_event0_iset_mstart (& mut self) -> INT_EVENT0_ISET_MSTART_W < INT_EVENT0_ISET_SPEC , 8 > { INT_EVENT0_ISET_MSTART_W :: new (self) } # [doc = "Bit 9 - STOP Detection Interrupt"] # [inline (always)] # [must_use] pub fn int_event0_iset_mstop (& mut self) -> INT_EVENT0_ISET_MSTOP_W < INT_EVENT0_ISET_SPEC , 9 > { INT_EVENT0_ISET_MSTOP_W :: new (self) } # [doc = "Bit 10 - Arbitration Lost Interrupt"] # [inline (always)] # [must_use] pub fn int_event0_iset_marblost (& mut self) -> INT_EVENT0_ISET_MARBLOST_W < INT_EVENT0_ISET_SPEC , 10 > { INT_EVENT0_ISET_MARBLOST_W :: new (self) } # [doc = "Bit 11 - DMA Done 1 on Event Channel 2"] # [inline (always)] # [must_use] pub fn int_event0_iset_mdma_done1_2 (& mut self) -> INT_EVENT0_ISET_MDMA_DONE1_2_W < INT_EVENT0_ISET_SPEC , 11 > { INT_EVENT0_ISET_MDMA_DONE1_2_W :: new (self) } # [doc = "Bit 12 - DMA Done 1 on Event Channel 3"] # [inline (always)] # [must_use] pub fn int_event0_iset_mdma_done1_3 (& mut self) -> INT_EVENT0_ISET_MDMA_DONE1_3_W < INT_EVENT0_ISET_SPEC , 12 > { INT_EVENT0_ISET_MDMA_DONE1_3_W :: new (self) } # [doc = "Bit 13 - Master RX Pec Error Interrupt"] # [inline (always)] # [must_use] pub fn int_event0_iset_mpec_rx_err (& mut self) -> INT_EVENT0_ISET_MPEC_RX_ERR_W < INT_EVENT0_ISET_SPEC , 13 > { INT_EVENT0_ISET_MPEC_RX_ERR_W :: new (self) } # [doc = "Bit 14 - Timeout A interrupt"] # [inline (always)] # [must_use] pub fn int_event0_iset_timeouta (& mut self) -> INT_EVENT0_ISET_TIMEOUTA_W < INT_EVENT0_ISET_SPEC , 14 > { INT_EVENT0_ISET_TIMEOUTA_W :: new (self) } # [doc = "Bit 15 - Timeout B Interrupt"] # [inline (always)] # [must_use] pub fn int_event0_iset_timeoutb (& mut self) -> INT_EVENT0_ISET_TIMEOUTB_W < INT_EVENT0_ISET_SPEC , 15 > { INT_EVENT0_ISET_TIMEOUTB_W :: new (self) } # [doc = "Bit 16 - Slave Receive Data Interrupt Signals that a byte has been received"] # [inline (always)] # [must_use] pub fn int_event0_iset_srxdone (& mut self) -> INT_EVENT0_ISET_SRXDONE_W < INT_EVENT0_ISET_SPEC , 16 > { INT_EVENT0_ISET_SRXDONE_W :: new (self) } # [doc = "Bit 17 - Slave Transmit Transaction completed Interrupt"] # [inline (always)] # [must_use] pub fn int_event0_iset_stxdone (& mut self) -> INT_EVENT0_ISET_STXDONE_W < INT_EVENT0_ISET_SPEC , 17 > { INT_EVENT0_ISET_STXDONE_W :: new (self) } # [doc = "Bit 18 - Slave Receive FIFO Trigger"] # [inline (always)] # [must_use] pub fn int_event0_iset_srxfifotrg (& mut self) -> INT_EVENT0_ISET_SRXFIFOTRG_W < INT_EVENT0_ISET_SPEC , 18 > { INT_EVENT0_ISET_SRXFIFOTRG_W :: new (self) } # [doc = "Bit 19 - Slave Transmit FIFO Trigger"] # [inline (always)] # [must_use] pub fn int_event0_iset_stxfifotrg (& mut self) -> INT_EVENT0_ISET_STXFIFOTRG_W < INT_EVENT0_ISET_SPEC , 19 > { INT_EVENT0_ISET_STXFIFOTRG_W :: new (self) } # [doc = "Bit 20 - RXFIFO full event. This interrupt is set if an RX FIFO is full."] # [inline (always)] # [must_use] pub fn int_event0_iset_srxfifofull (& mut self) -> INT_EVENT0_ISET_SRXFIFOFULL_W < INT_EVENT0_ISET_SPEC , 20 > { INT_EVENT0_ISET_SRXFIFOFULL_W :: new (self) } # [doc = "Bit 21 - Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode."] # [inline (always)] # [must_use] pub fn int_event0_iset_stxempty (& mut self) -> INT_EVENT0_ISET_STXEMPTY_W < INT_EVENT0_ISET_SPEC , 21 > { INT_EVENT0_ISET_STXEMPTY_W :: new (self) } # [doc = "Bit 22 - Start Condition Interrupt"] # [inline (always)] # [must_use] pub fn int_event0_iset_sstart (& mut self) -> INT_EVENT0_ISET_SSTART_W < INT_EVENT0_ISET_SPEC , 22 > { INT_EVENT0_ISET_SSTART_W :: new (self) } # [doc = "Bit 23 - Stop Condition Interrupt"] # [inline (always)] # [must_use] pub fn int_event0_iset_sstop (& mut self) -> INT_EVENT0_ISET_SSTOP_W < INT_EVENT0_ISET_SPEC , 23 > { INT_EVENT0_ISET_SSTOP_W :: new (self) } # [doc = "Bit 24 - General Call Interrupt"] # [inline (always)] # [must_use] pub fn int_event0_iset_sgencall (& mut self) -> INT_EVENT0_ISET_SGENCALL_W < INT_EVENT0_ISET_SPEC , 24 > { INT_EVENT0_ISET_SGENCALL_W :: new (self) } # [doc = "Bit 25 - DMA Done 1 on Event Channel 2"] # [inline (always)] # [must_use] pub fn int_event0_iset_sdma_done1_2 (& mut self) -> INT_EVENT0_ISET_SDMA_DONE1_2_W < INT_EVENT0_ISET_SPEC , 25 > { INT_EVENT0_ISET_SDMA_DONE1_2_W :: new (self) } # [doc = "Bit 26 - DMA Done 1 on Event Channel 3"] # [inline (always)] # [must_use] pub fn int_event0_iset_sdma_done1_3 (& mut self) -> INT_EVENT0_ISET_SDMA_DONE1_3_W < INT_EVENT0_ISET_SPEC , 26 > { INT_EVENT0_ISET_SDMA_DONE1_3_W :: new (self) } # [doc = "Bit 27 - Slave RX Pec Error Interrupt"] # [inline (always)] # [must_use] pub fn int_event0_iset_spec_rx_err (& mut self) -> INT_EVENT0_ISET_SPEC_RX_ERR_W < INT_EVENT0_ISET_SPEC , 27 > { INT_EVENT0_ISET_SPEC_RX_ERR_W :: new (self) } # [doc = "Bit 28 - Slave TX FIFO underflow"] # [inline (always)] # [must_use] pub fn int_event0_iset_stx_unfl (& mut self) -> INT_EVENT0_ISET_STX_UNFL_W < INT_EVENT0_ISET_SPEC , 28 > { INT_EVENT0_ISET_STX_UNFL_W :: new (self) } # [doc = "Bit 29 - Slave RX FIFO overflow"] # [inline (always)] # [must_use] pub fn int_event0_iset_srx_ovfl (& mut self) -> INT_EVENT0_ISET_SRX_OVFL_W < INT_EVENT0_ISET_SPEC , 29 > { INT_EVENT0_ISET_SRX_OVFL_W :: new (self) } # [doc = "Bit 30 - Slave Arbitration Lost"] # [inline (always)] # [must_use] pub fn int_event0_iset_sarblost (& mut self) -> INT_EVENT0_ISET_SARBLOST_W < INT_EVENT0_ISET_SPEC , 30 > { INT_EVENT0_ISET_SARBLOST_W :: new (self) } # [doc = "Bit 31 - Interrupt overflow"] # [inline (always)] # [must_use] pub fn int_event0_iset_intr_ovfl (& mut self) -> INT_EVENT0_ISET_INTR_OVFL_W < INT_EVENT0_ISET_SPEC , 31 > { INT_EVENT0_ISET_INTR_OVFL_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Interrupt set\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_event0_iset::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct INT_EVENT0_ISET_SPEC ; impl crate :: RegisterSpec for INT_EVENT0_ISET_SPEC { type Ux = u32 ; } # [doc = "`write(|w| ..)` method takes [`int_event0_iset::W`](W) writer structure"] impl crate :: Writable for INT_EVENT0_ISET_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets INT_EVENT0_ISET to value 0"] impl crate :: Resettable for INT_EVENT0_ISET_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/opa0/ctl.rs:1:1892 [INFO] [stdout] | [INFO] [stdout] 1 | ...ust_use] pub fn ctl_enable (& mut self) -> CTL_ENABLE_W < CTL_SPEC , 0 > { CTL_ENABLE_W :: new (self) } # [doc = r" Writes raw bits to... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `CTL` reader"] pub type R = crate :: R < CTL_SPEC > ; # [doc = "Register `CTL` writer"] pub type W = crate :: W < CTL_SPEC > ; # [doc = "Field `CTL_ENABLE` reader - OAxn Enable."] pub type CTL_ENABLE_R = crate :: BitReader < CTL_ENABLE_A > ; # [doc = "OAxn Enable.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CTL_ENABLE_A { # [doc = "0: OFF"] CTL_ENABLE_OFF = 0 , # [doc = "1: ON"] CTL_ENABLE_ON = 1 , } impl From < CTL_ENABLE_A > for bool { # [inline (always)] fn from (variant : CTL_ENABLE_A) -> Self { variant as u8 != 0 } } impl CTL_ENABLE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CTL_ENABLE_A { match self . bits { false => CTL_ENABLE_A :: CTL_ENABLE_OFF , true => CTL_ENABLE_A :: CTL_ENABLE_ON , } } # [doc = "OFF"] # [inline (always)] pub fn is_ctl_enable_off (& self) -> bool { * self == CTL_ENABLE_A :: CTL_ENABLE_OFF } # [doc = "ON"] # [inline (always)] pub fn is_ctl_enable_on (& self) -> bool { * self == CTL_ENABLE_A :: CTL_ENABLE_ON } } # [doc = "Field `CTL_ENABLE` writer - OAxn Enable."] pub type CTL_ENABLE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL_ENABLE_A > ; impl < 'a , REG , const O : u8 > CTL_ENABLE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "OFF"] # [inline (always)] pub fn ctl_enable_off (self) -> & 'a mut crate :: W < REG > { self . variant (CTL_ENABLE_A :: CTL_ENABLE_OFF) } # [doc = "ON"] # [inline (always)] pub fn ctl_enable_on (self) -> & 'a mut crate :: W < REG > { self . variant (CTL_ENABLE_A :: CTL_ENABLE_ON) } } impl R { # [doc = "Bit 0 - OAxn Enable."] # [inline (always)] pub fn ctl_enable (& self) -> CTL_ENABLE_R { CTL_ENABLE_R :: new ((self . bits & 1) != 0) } } impl W { # [doc = "Bit 0 - OAxn Enable."] # [inline (always)] # [must_use] pub fn ctl_enable (& mut self) -> CTL_ENABLE_W <'_, CTL_SPEC , 0 > { CTL_ENABLE_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CTL_SPEC ; impl crate :: RegisterSpec for CTL_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`ctl::R`](R) reader structure"] impl crate :: Readable for CTL_SPEC { } # [doc = "`write(|w| ..)` method takes [`ctl::W`](W) writer structure"] impl crate :: Writable for CTL_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets CTL to value 0"] impl crate :: Resettable for CTL_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/i2c1/int_event1_iclr.rs:1:6113 [INFO] [stdout] | [INFO] [stdout] 1 | ...r_stxfifotrg (& mut self) -> INT_EVENT1_ICLR_STXFIFOTRG_W < INT_EVENT1_ICLR_SPEC , 3 > { INT_EVENT1_ICLR_STXFIFOTRG_W :: new (self) } ... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `INT_EVENT1_ICLR` writer"] pub type W = crate :: W < INT_EVENT1_ICLR_SPEC > ; # [doc = "Master Receive FIFO Trigger Trigger when RX FIFO contains &gt;= defined bytes\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT1_ICLR_MRXFIFOTRG_AW { # [doc = "0: NO_EFFECT"] INT_EVENT1_ICLR_MRXFIFOTRG_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT1_ICLR_MRXFIFOTRG_CLR = 1 , } impl From < INT_EVENT1_ICLR_MRXFIFOTRG_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT1_ICLR_MRXFIFOTRG_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT1_ICLR_MRXFIFOTRG` writer - Master Receive FIFO Trigger Trigger when RX FIFO contains &gt;= defined bytes"] pub type INT_EVENT1_ICLR_MRXFIFOTRG_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT1_ICLR_MRXFIFOTRG_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT1_ICLR_MRXFIFOTRG_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event1_iclr_mrxfifotrg_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_ICLR_MRXFIFOTRG_AW :: INT_EVENT1_ICLR_MRXFIFOTRG_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event1_iclr_mrxfifotrg_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_ICLR_MRXFIFOTRG_AW :: INT_EVENT1_ICLR_MRXFIFOTRG_CLR) } } # [doc = "Master Transmit FIFO Trigger Trigger when Transmit FIFO contains &lt;= defined bytes\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT1_ICLR_MTXFIFOTRG_AW { # [doc = "0: NO_EFFECT"] INT_EVENT1_ICLR_MTXFIFOTRG_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT1_ICLR_MTXFIFOTRG_CLR = 1 , } impl From < INT_EVENT1_ICLR_MTXFIFOTRG_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT1_ICLR_MTXFIFOTRG_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT1_ICLR_MTXFIFOTRG` writer - Master Transmit FIFO Trigger Trigger when Transmit FIFO contains &lt;= defined bytes"] pub type INT_EVENT1_ICLR_MTXFIFOTRG_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT1_ICLR_MTXFIFOTRG_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT1_ICLR_MTXFIFOTRG_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event1_iclr_mtxfifotrg_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_ICLR_MTXFIFOTRG_AW :: INT_EVENT1_ICLR_MTXFIFOTRG_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event1_iclr_mtxfifotrg_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_ICLR_MTXFIFOTRG_AW :: INT_EVENT1_ICLR_MTXFIFOTRG_CLR) } } # [doc = "Slave Receive FIFO Trigger\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT1_ICLR_SRXFIFOTRG_AW { # [doc = "0: NO_EFFECT"] INT_EVENT1_ICLR_SRXFIFOTRG_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT1_ICLR_SRXFIFOTRG_CLR = 1 , } impl From < INT_EVENT1_ICLR_SRXFIFOTRG_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT1_ICLR_SRXFIFOTRG_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT1_ICLR_SRXFIFOTRG` writer - Slave Receive FIFO Trigger"] pub type INT_EVENT1_ICLR_SRXFIFOTRG_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT1_ICLR_SRXFIFOTRG_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT1_ICLR_SRXFIFOTRG_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event1_iclr_srxfifotrg_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_ICLR_SRXFIFOTRG_AW :: INT_EVENT1_ICLR_SRXFIFOTRG_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event1_iclr_srxfifotrg_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_ICLR_SRXFIFOTRG_AW :: INT_EVENT1_ICLR_SRXFIFOTRG_CLR) } } # [doc = "Slave Transmit FIFO Trigger\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT1_ICLR_STXFIFOTRG_AW { # [doc = "0: NO_EFFECT"] INT_EVENT1_ICLR_STXFIFOTRG_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_EVENT1_ICLR_STXFIFOTRG_CLR = 1 , } impl From < INT_EVENT1_ICLR_STXFIFOTRG_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT1_ICLR_STXFIFOTRG_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT1_ICLR_STXFIFOTRG` writer - Slave Transmit FIFO Trigger"] pub type INT_EVENT1_ICLR_STXFIFOTRG_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT1_ICLR_STXFIFOTRG_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT1_ICLR_STXFIFOTRG_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event1_iclr_stxfifotrg_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_ICLR_STXFIFOTRG_AW :: INT_EVENT1_ICLR_STXFIFOTRG_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_event1_iclr_stxfifotrg_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_ICLR_STXFIFOTRG_AW :: INT_EVENT1_ICLR_STXFIFOTRG_CLR) } } impl W { # [doc = "Bit 0 - Master Receive FIFO Trigger Trigger when RX FIFO contains &gt;= defined bytes"] # [inline (always)] # [must_use] pub fn int_event1_iclr_mrxfifotrg (& mut self) -> INT_EVENT1_ICLR_MRXFIFOTRG_W < INT_EVENT1_ICLR_SPEC , 0 > { INT_EVENT1_ICLR_MRXFIFOTRG_W :: new (self) } # [doc = "Bit 1 - Master Transmit FIFO Trigger Trigger when Transmit FIFO contains &lt;= defined bytes"] # [inline (always)] # [must_use] pub fn int_event1_iclr_mtxfifotrg (& mut self) -> INT_EVENT1_ICLR_MTXFIFOTRG_W < INT_EVENT1_ICLR_SPEC , 1 > { INT_EVENT1_ICLR_MTXFIFOTRG_W :: new (self) } # [doc = "Bit 2 - Slave Receive FIFO Trigger"] # [inline (always)] # [must_use] pub fn int_event1_iclr_srxfifotrg (& mut self) -> INT_EVENT1_ICLR_SRXFIFOTRG_W < INT_EVENT1_ICLR_SPEC , 2 > { INT_EVENT1_ICLR_SRXFIFOTRG_W :: new (self) } # [doc = "Bit 3 - Slave Transmit FIFO Trigger"] # [inline (always)] # [must_use] pub fn int_event1_iclr_stxfifotrg (& mut self) -> INT_EVENT1_ICLR_STXFIFOTRG_W <'_, INT_EVENT1_ICLR_SPEC , 3 > { INT_EVENT1_ICLR_STXFIFOTRG_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Interrupt clear\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_event1_iclr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct INT_EVENT1_ICLR_SPEC ; impl crate :: RegisterSpec for INT_EVENT1_ICLR_SPEC { type Ux = u32 ; } # [doc = "`write(|w| ..)` method takes [`int_event1_iclr::W`](W) writer structure"] impl crate :: Writable for INT_EVENT1_ICLR_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets INT_EVENT1_ICLR to value 0"] impl crate :: Resettable for INT_EVENT1_ICLR_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/i2c0/mcr.rs:1:9738 [INFO] [stdout] | [INFO] [stdout] 1 | ... [must_use] pub fn mcr_lpbk (& mut self) -> MCR_LPBK_W < MCR_SPEC , 8 > { MCR_LPBK_W :: new (self) } # [doc = r" Writes raw bits to th... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `MCR` reader"] pub type R = crate :: R < MCR_SPEC > ; # [doc = "Register `MCR` writer"] pub type W = crate :: W < MCR_SPEC > ; # [doc = "Field `MCR_ACTIVE` reader - Device Active After this bit has been set, it should not be set again unless it has been cleared by writing a 0 or by a reset, otherwise transfer failures may occur."] pub type MCR_ACTIVE_R = crate :: BitReader < MCR_ACTIVE_A > ; # [doc = "Device Active After this bit has been set, it should not be set again unless it has been cleared by writing a 0 or by a reset, otherwise transfer failures may occur.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum MCR_ACTIVE_A { # [doc = "0: DISABLE"] MCR_ACTIVE_DISABLE = 0 , # [doc = "1: ENABLE"] MCR_ACTIVE_ENABLE = 1 , } impl From < MCR_ACTIVE_A > for bool { # [inline (always)] fn from (variant : MCR_ACTIVE_A) -> Self { variant as u8 != 0 } } impl MCR_ACTIVE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> MCR_ACTIVE_A { match self . bits { false => MCR_ACTIVE_A :: MCR_ACTIVE_DISABLE , true => MCR_ACTIVE_A :: MCR_ACTIVE_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_mcr_active_disable (& self) -> bool { * self == MCR_ACTIVE_A :: MCR_ACTIVE_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_mcr_active_enable (& self) -> bool { * self == MCR_ACTIVE_A :: MCR_ACTIVE_ENABLE } } # [doc = "Field `MCR_ACTIVE` writer - Device Active After this bit has been set, it should not be set again unless it has been cleared by writing a 0 or by a reset, otherwise transfer failures may occur."] pub type MCR_ACTIVE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , MCR_ACTIVE_A > ; impl < 'a , REG , const O : u8 > MCR_ACTIVE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn mcr_active_disable (self) -> & 'a mut crate :: W < REG > { self . variant (MCR_ACTIVE_A :: MCR_ACTIVE_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn mcr_active_enable (self) -> & 'a mut crate :: W < REG > { self . variant (MCR_ACTIVE_A :: MCR_ACTIVE_ENABLE) } } # [doc = "Field `MCR_MMST` reader - Multimaster mode. In Multimaster mode the SCL high time counts once the SCL line has been detected high. If this is not enabled the high time counts as soon as the SCL line has been set high by the I2C controller."] pub type MCR_MMST_R = crate :: BitReader < MCR_MMST_A > ; # [doc = "Multimaster mode. In Multimaster mode the SCL high time counts once the SCL line has been detected high. If this is not enabled the high time counts as soon as the SCL line has been set high by the I2C controller.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum MCR_MMST_A { # [doc = "0: DISABLE"] MCR_MMST_DISABLE = 0 , # [doc = "1: ENABLE"] MCR_MMST_ENABLE = 1 , } impl From < MCR_MMST_A > for bool { # [inline (always)] fn from (variant : MCR_MMST_A) -> Self { variant as u8 != 0 } } impl MCR_MMST_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> MCR_MMST_A { match self . bits { false => MCR_MMST_A :: MCR_MMST_DISABLE , true => MCR_MMST_A :: MCR_MMST_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_mcr_mmst_disable (& self) -> bool { * self == MCR_MMST_A :: MCR_MMST_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_mcr_mmst_enable (& self) -> bool { * self == MCR_MMST_A :: MCR_MMST_ENABLE } } # [doc = "Field `MCR_MMST` writer - Multimaster mode. In Multimaster mode the SCL high time counts once the SCL line has been detected high. If this is not enabled the high time counts as soon as the SCL line has been set high by the I2C controller."] pub type MCR_MMST_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , MCR_MMST_A > ; impl < 'a , REG , const O : u8 > MCR_MMST_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn mcr_mmst_disable (self) -> & 'a mut crate :: W < REG > { self . variant (MCR_MMST_A :: MCR_MMST_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn mcr_mmst_enable (self) -> & 'a mut crate :: W < REG > { self . variant (MCR_MMST_A :: MCR_MMST_ENABLE) } } # [doc = "Field `MCR_CLKSTRETCH` reader - Clock Stretching. This bit controls the support for clock stretching of the I2C bus."] pub type MCR_CLKSTRETCH_R = crate :: BitReader < MCR_CLKSTRETCH_A > ; # [doc = "Clock Stretching. This bit controls the support for clock stretching of the I2C bus.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum MCR_CLKSTRETCH_A { # [doc = "0: DISABLE"] MCR_CLKSTRETCH_DISABLE = 0 , # [doc = "1: ENABLE"] MCR_CLKSTRETCH_ENABLE = 1 , } impl From < MCR_CLKSTRETCH_A > for bool { # [inline (always)] fn from (variant : MCR_CLKSTRETCH_A) -> Self { variant as u8 != 0 } } impl MCR_CLKSTRETCH_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> MCR_CLKSTRETCH_A { match self . bits { false => MCR_CLKSTRETCH_A :: MCR_CLKSTRETCH_DISABLE , true => MCR_CLKSTRETCH_A :: MCR_CLKSTRETCH_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_mcr_clkstretch_disable (& self) -> bool { * self == MCR_CLKSTRETCH_A :: MCR_CLKSTRETCH_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_mcr_clkstretch_enable (& self) -> bool { * self == MCR_CLKSTRETCH_A :: MCR_CLKSTRETCH_ENABLE } } # [doc = "Field `MCR_CLKSTRETCH` writer - Clock Stretching. This bit controls the support for clock stretching of the I2C bus."] pub type MCR_CLKSTRETCH_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , MCR_CLKSTRETCH_A > ; impl < 'a , REG , const O : u8 > MCR_CLKSTRETCH_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn mcr_clkstretch_disable (self) -> & 'a mut crate :: W < REG > { self . variant (MCR_CLKSTRETCH_A :: MCR_CLKSTRETCH_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn mcr_clkstretch_enable (self) -> & 'a mut crate :: W < REG > { self . variant (MCR_CLKSTRETCH_A :: MCR_CLKSTRETCH_ENABLE) } } # [doc = "Field `MCR_LPBK` reader - I2C Loopback"] pub type MCR_LPBK_R = crate :: BitReader < MCR_LPBK_A > ; # [doc = "I2C Loopback\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum MCR_LPBK_A { # [doc = "0: DISABLE"] MCR_LPBK_DISABLE = 0 , # [doc = "1: ENABLE"] MCR_LPBK_ENABLE = 1 , } impl From < MCR_LPBK_A > for bool { # [inline (always)] fn from (variant : MCR_LPBK_A) -> Self { variant as u8 != 0 } } impl MCR_LPBK_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> MCR_LPBK_A { match self . bits { false => MCR_LPBK_A :: MCR_LPBK_DISABLE , true => MCR_LPBK_A :: MCR_LPBK_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_mcr_lpbk_disable (& self) -> bool { * self == MCR_LPBK_A :: MCR_LPBK_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_mcr_lpbk_enable (& self) -> bool { * self == MCR_LPBK_A :: MCR_LPBK_ENABLE } } # [doc = "Field `MCR_LPBK` writer - I2C Loopback"] pub type MCR_LPBK_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , MCR_LPBK_A > ; impl < 'a , REG , const O : u8 > MCR_LPBK_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn mcr_lpbk_disable (self) -> & 'a mut crate :: W < REG > { self . variant (MCR_LPBK_A :: MCR_LPBK_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn mcr_lpbk_enable (self) -> & 'a mut crate :: W < REG > { self . variant (MCR_LPBK_A :: MCR_LPBK_ENABLE) } } impl R { # [doc = "Bit 0 - Device Active After this bit has been set, it should not be set again unless it has been cleared by writing a 0 or by a reset, otherwise transfer failures may occur."] # [inline (always)] pub fn mcr_active (& self) -> MCR_ACTIVE_R { MCR_ACTIVE_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - Multimaster mode. In Multimaster mode the SCL high time counts once the SCL line has been detected high. If this is not enabled the high time counts as soon as the SCL line has been set high by the I2C controller."] # [inline (always)] pub fn mcr_mmst (& self) -> MCR_MMST_R { MCR_MMST_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - Clock Stretching. This bit controls the support for clock stretching of the I2C bus."] # [inline (always)] pub fn mcr_clkstretch (& self) -> MCR_CLKSTRETCH_R { MCR_CLKSTRETCH_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 8 - I2C Loopback"] # [inline (always)] pub fn mcr_lpbk (& self) -> MCR_LPBK_R { MCR_LPBK_R :: new (((self . bits >> 8) & 1) != 0) } } impl W { # [doc = "Bit 0 - Device Active After this bit has been set, it should not be set again unless it has been cleared by writing a 0 or by a reset, otherwise transfer failures may occur."] # [inline (always)] # [must_use] pub fn mcr_active (& mut self) -> MCR_ACTIVE_W < MCR_SPEC , 0 > { MCR_ACTIVE_W :: new (self) } # [doc = "Bit 1 - Multimaster mode. In Multimaster mode the SCL high time counts once the SCL line has been detected high. If this is not enabled the high time counts as soon as the SCL line has been set high by the I2C controller."] # [inline (always)] # [must_use] pub fn mcr_mmst (& mut self) -> MCR_MMST_W < MCR_SPEC , 1 > { MCR_MMST_W :: new (self) } # [doc = "Bit 2 - Clock Stretching. This bit controls the support for clock stretching of the I2C bus."] # [inline (always)] # [must_use] pub fn mcr_clkstretch (& mut self) -> MCR_CLKSTRETCH_W < MCR_SPEC , 2 > { MCR_CLKSTRETCH_W :: new (self) } # [doc = "Bit 8 - I2C Loopback"] # [inline (always)] # [must_use] pub fn mcr_lpbk (& mut self) -> MCR_LPBK_W <'_, MCR_SPEC , 8 > { MCR_LPBK_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "I2C Master Configuration\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mcr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mcr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct MCR_SPEC ; impl crate :: RegisterSpec for MCR_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`mcr::R`](R) reader structure"] impl crate :: Readable for MCR_SPEC { } # [doc = "`write(|w| ..)` method takes [`mcr::W`](W) writer structure"] impl crate :: Writable for MCR_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets MCR to value 0"] impl crate :: Resettable for MCR_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/i2c0/sctr.rs:1:25254 [INFO] [stdout] | [INFO] [stdout] 1 | ... fn sctr_txtrig_txmode (& mut self) -> SCTR_TXTRIG_TXMODE_W < SCTR_SPEC , 4 > { SCTR_TXTRIG_TXMODE_W :: new (self) } # [doc = "Bit 5 -... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `SCTR` reader"] pub type R = crate :: R < SCTR_SPEC > ; # [doc = "Register `SCTR` writer"] pub type W = crate :: W < SCTR_SPEC > ; # [doc = "Field `SCTR_ACTIVE` reader - Device Active. Setting this bit enables the slave functionality."] pub type SCTR_ACTIVE_R = crate :: BitReader < SCTR_ACTIVE_A > ; # [doc = "Device Active. Setting this bit enables the slave functionality.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum SCTR_ACTIVE_A { # [doc = "0: DISABLE"] SCTR_ACTIVE_DISABLE = 0 , # [doc = "1: ENABLE"] SCTR_ACTIVE_ENABLE = 1 , } impl From < SCTR_ACTIVE_A > for bool { # [inline (always)] fn from (variant : SCTR_ACTIVE_A) -> Self { variant as u8 != 0 } } impl SCTR_ACTIVE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> SCTR_ACTIVE_A { match self . bits { false => SCTR_ACTIVE_A :: SCTR_ACTIVE_DISABLE , true => SCTR_ACTIVE_A :: SCTR_ACTIVE_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_sctr_active_disable (& self) -> bool { * self == SCTR_ACTIVE_A :: SCTR_ACTIVE_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_sctr_active_enable (& self) -> bool { * self == SCTR_ACTIVE_A :: SCTR_ACTIVE_ENABLE } } # [doc = "Field `SCTR_ACTIVE` writer - Device Active. Setting this bit enables the slave functionality."] pub type SCTR_ACTIVE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , SCTR_ACTIVE_A > ; impl < 'a , REG , const O : u8 > SCTR_ACTIVE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn sctr_active_disable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_ACTIVE_A :: SCTR_ACTIVE_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn sctr_active_enable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_ACTIVE_A :: SCTR_ACTIVE_ENABLE) } } # [doc = "Field `SCTR_GENCALL` reader - General call response enable. This bit is only available in UCBxI2COA0. Modify only when UCSWRST = 1. 0b = Do not respond to a general call 1b = Respond to a general call"] pub type SCTR_GENCALL_R = crate :: BitReader < SCTR_GENCALL_A > ; # [doc = "General call response enable. This bit is only available in UCBxI2COA0. Modify only when UCSWRST = 1. 0b = Do not respond to a general call 1b = Respond to a general call\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum SCTR_GENCALL_A { # [doc = "0: DISABLE"] SCTR_GENCALL_DISABLE = 0 , # [doc = "1: ENABLE"] SCTR_GENCALL_ENABLE = 1 , } impl From < SCTR_GENCALL_A > for bool { # [inline (always)] fn from (variant : SCTR_GENCALL_A) -> Self { variant as u8 != 0 } } impl SCTR_GENCALL_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> SCTR_GENCALL_A { match self . bits { false => SCTR_GENCALL_A :: SCTR_GENCALL_DISABLE , true => SCTR_GENCALL_A :: SCTR_GENCALL_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_sctr_gencall_disable (& self) -> bool { * self == SCTR_GENCALL_A :: SCTR_GENCALL_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_sctr_gencall_enable (& self) -> bool { * self == SCTR_GENCALL_A :: SCTR_GENCALL_ENABLE } } # [doc = "Field `SCTR_GENCALL` writer - General call response enable. This bit is only available in UCBxI2COA0. Modify only when UCSWRST = 1. 0b = Do not respond to a general call 1b = Respond to a general call"] pub type SCTR_GENCALL_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , SCTR_GENCALL_A > ; impl < 'a , REG , const O : u8 > SCTR_GENCALL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn sctr_gencall_disable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_GENCALL_A :: SCTR_GENCALL_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn sctr_gencall_enable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_GENCALL_A :: SCTR_GENCALL_ENABLE) } } # [doc = "Field `SCTR_SCLKSTRETCH` reader - Slave Clock Stretch Enable"] pub type SCTR_SCLKSTRETCH_R = crate :: BitReader < SCTR_SCLKSTRETCH_A > ; # [doc = "Slave Clock Stretch Enable\n\nValue on reset: 1"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum SCTR_SCLKSTRETCH_A { # [doc = "0: DISABLE"] SCTR_SCLKSTRETCH_DISABLE = 0 , # [doc = "1: ENABLE"] SCTR_SCLKSTRETCH_ENABLE = 1 , } impl From < SCTR_SCLKSTRETCH_A > for bool { # [inline (always)] fn from (variant : SCTR_SCLKSTRETCH_A) -> Self { variant as u8 != 0 } } impl SCTR_SCLKSTRETCH_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> SCTR_SCLKSTRETCH_A { match self . bits { false => SCTR_SCLKSTRETCH_A :: SCTR_SCLKSTRETCH_DISABLE , true => SCTR_SCLKSTRETCH_A :: SCTR_SCLKSTRETCH_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_sctr_sclkstretch_disable (& self) -> bool { * self == SCTR_SCLKSTRETCH_A :: SCTR_SCLKSTRETCH_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_sctr_sclkstretch_enable (& self) -> bool { * self == SCTR_SCLKSTRETCH_A :: SCTR_SCLKSTRETCH_ENABLE } } # [doc = "Field `SCTR_SCLKSTRETCH` writer - Slave Clock Stretch Enable"] pub type SCTR_SCLKSTRETCH_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , SCTR_SCLKSTRETCH_A > ; impl < 'a , REG , const O : u8 > SCTR_SCLKSTRETCH_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn sctr_sclkstretch_disable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_SCLKSTRETCH_A :: SCTR_SCLKSTRETCH_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn sctr_sclkstretch_enable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_SCLKSTRETCH_A :: SCTR_SCLKSTRETCH_ENABLE) } } # [doc = "Field `SCTR_TXEMPTY_ON_TREQ` reader - Tx Empty Interrupt on TREQ"] pub type SCTR_TXEMPTY_ON_TREQ_R = crate :: BitReader < SCTR_TXEMPTY_ON_TREQ_A > ; # [doc = "Tx Empty Interrupt on TREQ\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum SCTR_TXEMPTY_ON_TREQ_A { # [doc = "0: DISABLE"] SCTR_TXEMPTY_ON_TREQ_DISABLE = 0 , # [doc = "1: ENABLE"] SCTR_TXEMPTY_ON_TREQ_ENABLE = 1 , } impl From < SCTR_TXEMPTY_ON_TREQ_A > for bool { # [inline (always)] fn from (variant : SCTR_TXEMPTY_ON_TREQ_A) -> Self { variant as u8 != 0 } } impl SCTR_TXEMPTY_ON_TREQ_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> SCTR_TXEMPTY_ON_TREQ_A { match self . bits { false => SCTR_TXEMPTY_ON_TREQ_A :: SCTR_TXEMPTY_ON_TREQ_DISABLE , true => SCTR_TXEMPTY_ON_TREQ_A :: SCTR_TXEMPTY_ON_TREQ_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_sctr_txempty_on_treq_disable (& self) -> bool { * self == SCTR_TXEMPTY_ON_TREQ_A :: SCTR_TXEMPTY_ON_TREQ_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_sctr_txempty_on_treq_enable (& self) -> bool { * self == SCTR_TXEMPTY_ON_TREQ_A :: SCTR_TXEMPTY_ON_TREQ_ENABLE } } # [doc = "Field `SCTR_TXEMPTY_ON_TREQ` writer - Tx Empty Interrupt on TREQ"] pub type SCTR_TXEMPTY_ON_TREQ_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , SCTR_TXEMPTY_ON_TREQ_A > ; impl < 'a , REG , const O : u8 > SCTR_TXEMPTY_ON_TREQ_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn sctr_txempty_on_treq_disable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_TXEMPTY_ON_TREQ_A :: SCTR_TXEMPTY_ON_TREQ_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn sctr_txempty_on_treq_enable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_TXEMPTY_ON_TREQ_A :: SCTR_TXEMPTY_ON_TREQ_ENABLE) } } # [doc = "Field `SCTR_TXTRIG_TXMODE` reader - Tx Trigger when slave FSM is in Tx Mode"] pub type SCTR_TXTRIG_TXMODE_R = crate :: BitReader < SCTR_TXTRIG_TXMODE_A > ; # [doc = "Tx Trigger when slave FSM is in Tx Mode\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum SCTR_TXTRIG_TXMODE_A { # [doc = "0: DISABLE"] SCTR_TXTRIG_TXMODE_DISABLE = 0 , # [doc = "1: ENABLE"] SCTR_TXTRIG_TXMODE_ENABLE = 1 , } impl From < SCTR_TXTRIG_TXMODE_A > for bool { # [inline (always)] fn from (variant : SCTR_TXTRIG_TXMODE_A) -> Self { variant as u8 != 0 } } impl SCTR_TXTRIG_TXMODE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> SCTR_TXTRIG_TXMODE_A { match self . bits { false => SCTR_TXTRIG_TXMODE_A :: SCTR_TXTRIG_TXMODE_DISABLE , true => SCTR_TXTRIG_TXMODE_A :: SCTR_TXTRIG_TXMODE_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_sctr_txtrig_txmode_disable (& self) -> bool { * self == SCTR_TXTRIG_TXMODE_A :: SCTR_TXTRIG_TXMODE_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_sctr_txtrig_txmode_enable (& self) -> bool { * self == SCTR_TXTRIG_TXMODE_A :: SCTR_TXTRIG_TXMODE_ENABLE } } # [doc = "Field `SCTR_TXTRIG_TXMODE` writer - Tx Trigger when slave FSM is in Tx Mode"] pub type SCTR_TXTRIG_TXMODE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , SCTR_TXTRIG_TXMODE_A > ; impl < 'a , REG , const O : u8 > SCTR_TXTRIG_TXMODE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn sctr_txtrig_txmode_disable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_TXTRIG_TXMODE_A :: SCTR_TXTRIG_TXMODE_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn sctr_txtrig_txmode_enable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_TXTRIG_TXMODE_A :: SCTR_TXTRIG_TXMODE_ENABLE) } } # [doc = "Field `SCTR_TXWAIT_STALE_TXFIFO` reader - Tx transfer waits when stale data in Tx FIFO. This prevents stale bytes left in the TX FIFO from automatically being sent on the next I2C packet. Note: this should be used with TXEMPTY_ON_TREQ set to prevent the Slave State Machine from waiting for TX FIFO data without an interrupt notification when the FIFO data is stale."] pub type SCTR_TXWAIT_STALE_TXFIFO_R = crate :: BitReader < SCTR_TXWAIT_STALE_TXFIFO_A > ; # [doc = "Tx transfer waits when stale data in Tx FIFO. This prevents stale bytes left in the TX FIFO from automatically being sent on the next I2C packet. Note: this should be used with TXEMPTY_ON_TREQ set to prevent the Slave State Machine from waiting for TX FIFO data without an interrupt notification when the FIFO data is stale.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum SCTR_TXWAIT_STALE_TXFIFO_A { # [doc = "0: DISABLE"] SCTR_TXWAIT_STALE_TXFIFO_DISABLE = 0 , # [doc = "1: ENABLE"] SCTR_TXWAIT_STALE_TXFIFO_ENABLE = 1 , } impl From < SCTR_TXWAIT_STALE_TXFIFO_A > for bool { # [inline (always)] fn from (variant : SCTR_TXWAIT_STALE_TXFIFO_A) -> Self { variant as u8 != 0 } } impl SCTR_TXWAIT_STALE_TXFIFO_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> SCTR_TXWAIT_STALE_TXFIFO_A { match self . bits { false => SCTR_TXWAIT_STALE_TXFIFO_A :: SCTR_TXWAIT_STALE_TXFIFO_DISABLE , true => SCTR_TXWAIT_STALE_TXFIFO_A :: SCTR_TXWAIT_STALE_TXFIFO_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_sctr_txwait_stale_txfifo_disable (& self) -> bool { * self == SCTR_TXWAIT_STALE_TXFIFO_A :: SCTR_TXWAIT_STALE_TXFIFO_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_sctr_txwait_stale_txfifo_enable (& self) -> bool { * self == SCTR_TXWAIT_STALE_TXFIFO_A :: SCTR_TXWAIT_STALE_TXFIFO_ENABLE } } # [doc = "Field `SCTR_TXWAIT_STALE_TXFIFO` writer - Tx transfer waits when stale data in Tx FIFO. This prevents stale bytes left in the TX FIFO from automatically being sent on the next I2C packet. Note: this should be used with TXEMPTY_ON_TREQ set to prevent the Slave State Machine from waiting for TX FIFO data without an interrupt notification when the FIFO data is stale."] pub type SCTR_TXWAIT_STALE_TXFIFO_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , SCTR_TXWAIT_STALE_TXFIFO_A > ; impl < 'a , REG , const O : u8 > SCTR_TXWAIT_STALE_TXFIFO_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn sctr_txwait_stale_txfifo_disable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_TXWAIT_STALE_TXFIFO_A :: SCTR_TXWAIT_STALE_TXFIFO_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn sctr_txwait_stale_txfifo_enable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_TXWAIT_STALE_TXFIFO_A :: SCTR_TXWAIT_STALE_TXFIFO_ENABLE) } } # [doc = "Field `SCTR_RXFULL_ON_RREQ` reader - Rx full interrupt generated on RREQ condition as indicated in SSR"] pub type SCTR_RXFULL_ON_RREQ_R = crate :: BitReader < SCTR_RXFULL_ON_RREQ_A > ; # [doc = "Rx full interrupt generated on RREQ condition as indicated in SSR\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum SCTR_RXFULL_ON_RREQ_A { # [doc = "0: DISABLE"] SCTR_RXFULL_ON_RREQ_DISABLE = 0 , # [doc = "1: ENABLE"] SCTR_RXFULL_ON_RREQ_ENABLE = 1 , } impl From < SCTR_RXFULL_ON_RREQ_A > for bool { # [inline (always)] fn from (variant : SCTR_RXFULL_ON_RREQ_A) -> Self { variant as u8 != 0 } } impl SCTR_RXFULL_ON_RREQ_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> SCTR_RXFULL_ON_RREQ_A { match self . bits { false => SCTR_RXFULL_ON_RREQ_A :: SCTR_RXFULL_ON_RREQ_DISABLE , true => SCTR_RXFULL_ON_RREQ_A :: SCTR_RXFULL_ON_RREQ_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_sctr_rxfull_on_rreq_disable (& self) -> bool { * self == SCTR_RXFULL_ON_RREQ_A :: SCTR_RXFULL_ON_RREQ_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_sctr_rxfull_on_rreq_enable (& self) -> bool { * self == SCTR_RXFULL_ON_RREQ_A :: SCTR_RXFULL_ON_RREQ_ENABLE } } # [doc = "Field `SCTR_RXFULL_ON_RREQ` writer - Rx full interrupt generated on RREQ condition as indicated in SSR"] pub type SCTR_RXFULL_ON_RREQ_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , SCTR_RXFULL_ON_RREQ_A > ; impl < 'a , REG , const O : u8 > SCTR_RXFULL_ON_RREQ_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn sctr_rxfull_on_rreq_disable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_RXFULL_ON_RREQ_A :: SCTR_RXFULL_ON_RREQ_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn sctr_rxfull_on_rreq_enable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_RXFULL_ON_RREQ_A :: SCTR_RXFULL_ON_RREQ_ENABLE) } } # [doc = "Field `SCTR_EN_DEFHOSTADR` reader - Enable Default Host Address"] pub type SCTR_EN_DEFHOSTADR_R = crate :: BitReader < SCTR_EN_DEFHOSTADR_A > ; # [doc = "Enable Default Host Address\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum SCTR_EN_DEFHOSTADR_A { # [doc = "0: DISABLE"] SCTR_EN_DEFHOSTADR_DISABLE = 0 , # [doc = "1: ENABLE"] SCTR_EN_DEFHOSTADR_ENABLE = 1 , } impl From < SCTR_EN_DEFHOSTADR_A > for bool { # [inline (always)] fn from (variant : SCTR_EN_DEFHOSTADR_A) -> Self { variant as u8 != 0 } } impl SCTR_EN_DEFHOSTADR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> SCTR_EN_DEFHOSTADR_A { match self . bits { false => SCTR_EN_DEFHOSTADR_A :: SCTR_EN_DEFHOSTADR_DISABLE , true => SCTR_EN_DEFHOSTADR_A :: SCTR_EN_DEFHOSTADR_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_sctr_en_defhostadr_disable (& self) -> bool { * self == SCTR_EN_DEFHOSTADR_A :: SCTR_EN_DEFHOSTADR_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_sctr_en_defhostadr_enable (& self) -> bool { * self == SCTR_EN_DEFHOSTADR_A :: SCTR_EN_DEFHOSTADR_ENABLE } } # [doc = "Field `SCTR_EN_DEFHOSTADR` writer - Enable Default Host Address"] pub type SCTR_EN_DEFHOSTADR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , SCTR_EN_DEFHOSTADR_A > ; impl < 'a , REG , const O : u8 > SCTR_EN_DEFHOSTADR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn sctr_en_defhostadr_disable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_EN_DEFHOSTADR_A :: SCTR_EN_DEFHOSTADR_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn sctr_en_defhostadr_enable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_EN_DEFHOSTADR_A :: SCTR_EN_DEFHOSTADR_ENABLE) } } # [doc = "Field `SCTR_EN_ALRESPADR` reader - Enable Alert Response Address"] pub type SCTR_EN_ALRESPADR_R = crate :: BitReader < SCTR_EN_ALRESPADR_A > ; # [doc = "Enable Alert Response Address\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum SCTR_EN_ALRESPADR_A { # [doc = "0: DISABLE"] SCTR_EN_ALRESPADR_DISABLE = 0 , # [doc = "1: ENABLE"] SCTR_EN_ALRESPADR_ENABLE = 1 , } impl From < SCTR_EN_ALRESPADR_A > for bool { # [inline (always)] fn from (variant : SCTR_EN_ALRESPADR_A) -> Self { variant as u8 != 0 } } impl SCTR_EN_ALRESPADR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> SCTR_EN_ALRESPADR_A { match self . bits { false => SCTR_EN_ALRESPADR_A :: SCTR_EN_ALRESPADR_DISABLE , true => SCTR_EN_ALRESPADR_A :: SCTR_EN_ALRESPADR_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_sctr_en_alrespadr_disable (& self) -> bool { * self == SCTR_EN_ALRESPADR_A :: SCTR_EN_ALRESPADR_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_sctr_en_alrespadr_enable (& self) -> bool { * self == SCTR_EN_ALRESPADR_A :: SCTR_EN_ALRESPADR_ENABLE } } # [doc = "Field `SCTR_EN_ALRESPADR` writer - Enable Alert Response Address"] pub type SCTR_EN_ALRESPADR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , SCTR_EN_ALRESPADR_A > ; impl < 'a , REG , const O : u8 > SCTR_EN_ALRESPADR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn sctr_en_alrespadr_disable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_EN_ALRESPADR_A :: SCTR_EN_ALRESPADR_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn sctr_en_alrespadr_enable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_EN_ALRESPADR_A :: SCTR_EN_ALRESPADR_ENABLE) } } # [doc = "Field `SCTR_EN_DEFDEVADR` reader - Enable Deault device address"] pub type SCTR_EN_DEFDEVADR_R = crate :: BitReader < SCTR_EN_DEFDEVADR_A > ; # [doc = "Enable Deault device address\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum SCTR_EN_DEFDEVADR_A { # [doc = "0: DISABLE"] SCTR_EN_DEFDEVADR_DISABLE = 0 , # [doc = "1: ENABLE"] SCTR_EN_DEFDEVADR_ENABLE = 1 , } impl From < SCTR_EN_DEFDEVADR_A > for bool { # [inline (always)] fn from (variant : SCTR_EN_DEFDEVADR_A) -> Self { variant as u8 != 0 } } impl SCTR_EN_DEFDEVADR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> SCTR_EN_DEFDEVADR_A { match self . bits { false => SCTR_EN_DEFDEVADR_A :: SCTR_EN_DEFDEVADR_DISABLE , true => SCTR_EN_DEFDEVADR_A :: SCTR_EN_DEFDEVADR_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_sctr_en_defdevadr_disable (& self) -> bool { * self == SCTR_EN_DEFDEVADR_A :: SCTR_EN_DEFDEVADR_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_sctr_en_defdevadr_enable (& self) -> bool { * self == SCTR_EN_DEFDEVADR_A :: SCTR_EN_DEFDEVADR_ENABLE } } # [doc = "Field `SCTR_EN_DEFDEVADR` writer - Enable Deault device address"] pub type SCTR_EN_DEFDEVADR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , SCTR_EN_DEFDEVADR_A > ; impl < 'a , REG , const O : u8 > SCTR_EN_DEFDEVADR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn sctr_en_defdevadr_disable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_EN_DEFDEVADR_A :: SCTR_EN_DEFDEVADR_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn sctr_en_defdevadr_enable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_EN_DEFDEVADR_A :: SCTR_EN_DEFDEVADR_ENABLE) } } # [doc = "Field `SCTR_SWUEN` reader - Slave Wakeup Enable"] pub type SCTR_SWUEN_R = crate :: BitReader < SCTR_SWUEN_A > ; # [doc = "Slave Wakeup Enable\n\nValue on reset: 1"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum SCTR_SWUEN_A { # [doc = "0: DISABLE"] SCTR_SWUEN_DISABLE = 0 , # [doc = "1: ENABLE"] SCTR_SWUEN_ENABLE = 1 , } impl From < SCTR_SWUEN_A > for bool { # [inline (always)] fn from (variant : SCTR_SWUEN_A) -> Self { variant as u8 != 0 } } impl SCTR_SWUEN_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> SCTR_SWUEN_A { match self . bits { false => SCTR_SWUEN_A :: SCTR_SWUEN_DISABLE , true => SCTR_SWUEN_A :: SCTR_SWUEN_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_sctr_swuen_disable (& self) -> bool { * self == SCTR_SWUEN_A :: SCTR_SWUEN_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_sctr_swuen_enable (& self) -> bool { * self == SCTR_SWUEN_A :: SCTR_SWUEN_ENABLE } } # [doc = "Field `SCTR_SWUEN` writer - Slave Wakeup Enable"] pub type SCTR_SWUEN_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , SCTR_SWUEN_A > ; impl < 'a , REG , const O : u8 > SCTR_SWUEN_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn sctr_swuen_disable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_SWUEN_A :: SCTR_SWUEN_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn sctr_swuen_enable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_SWUEN_A :: SCTR_SWUEN_ENABLE) } } impl R { # [doc = "Bit 0 - Device Active. Setting this bit enables the slave functionality."] # [inline (always)] pub fn sctr_active (& self) -> SCTR_ACTIVE_R { SCTR_ACTIVE_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - General call response enable. This bit is only available in UCBxI2COA0. Modify only when UCSWRST = 1. 0b = Do not respond to a general call 1b = Respond to a general call"] # [inline (always)] pub fn sctr_gencall (& self) -> SCTR_GENCALL_R { SCTR_GENCALL_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - Slave Clock Stretch Enable"] # [inline (always)] pub fn sctr_sclkstretch (& self) -> SCTR_SCLKSTRETCH_R { SCTR_SCLKSTRETCH_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - Tx Empty Interrupt on TREQ"] # [inline (always)] pub fn sctr_txempty_on_treq (& self) -> SCTR_TXEMPTY_ON_TREQ_R { SCTR_TXEMPTY_ON_TREQ_R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - Tx Trigger when slave FSM is in Tx Mode"] # [inline (always)] pub fn sctr_txtrig_txmode (& self) -> SCTR_TXTRIG_TXMODE_R { SCTR_TXTRIG_TXMODE_R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - Tx transfer waits when stale data in Tx FIFO. This prevents stale bytes left in the TX FIFO from automatically being sent on the next I2C packet. Note: this should be used with TXEMPTY_ON_TREQ set to prevent the Slave State Machine from waiting for TX FIFO data without an interrupt notification when the FIFO data is stale."] # [inline (always)] pub fn sctr_txwait_stale_txfifo (& self) -> SCTR_TXWAIT_STALE_TXFIFO_R { SCTR_TXWAIT_STALE_TXFIFO_R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - Rx full interrupt generated on RREQ condition as indicated in SSR"] # [inline (always)] pub fn sctr_rxfull_on_rreq (& self) -> SCTR_RXFULL_ON_RREQ_R { SCTR_RXFULL_ON_RREQ_R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - Enable Default Host Address"] # [inline (always)] pub fn sctr_en_defhostadr (& self) -> SCTR_EN_DEFHOSTADR_R { SCTR_EN_DEFHOSTADR_R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - Enable Alert Response Address"] # [inline (always)] pub fn sctr_en_alrespadr (& self) -> SCTR_EN_ALRESPADR_R { SCTR_EN_ALRESPADR_R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - Enable Deault device address"] # [inline (always)] pub fn sctr_en_defdevadr (& self) -> SCTR_EN_DEFDEVADR_R { SCTR_EN_DEFDEVADR_R :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - Slave Wakeup Enable"] # [inline (always)] pub fn sctr_swuen (& self) -> SCTR_SWUEN_R { SCTR_SWUEN_R :: new (((self . bits >> 10) & 1) != 0) } } impl W { # [doc = "Bit 0 - Device Active. Setting this bit enables the slave functionality."] # [inline (always)] # [must_use] pub fn sctr_active (& mut self) -> SCTR_ACTIVE_W < SCTR_SPEC , 0 > { SCTR_ACTIVE_W :: new (self) } # [doc = "Bit 1 - General call response enable. This bit is only available in UCBxI2COA0. Modify only when UCSWRST = 1. 0b = Do not respond to a general call 1b = Respond to a general call"] # [inline (always)] # [must_use] pub fn sctr_gencall (& mut self) -> SCTR_GENCALL_W < SCTR_SPEC , 1 > { SCTR_GENCALL_W :: new (self) } # [doc = "Bit 2 - Slave Clock Stretch Enable"] # [inline (always)] # [must_use] pub fn sctr_sclkstretch (& mut self) -> SCTR_SCLKSTRETCH_W < SCTR_SPEC , 2 > { SCTR_SCLKSTRETCH_W :: new (self) } # [doc = "Bit 3 - Tx Empty Interrupt on TREQ"] # [inline (always)] # [must_use] pub fn sctr_txempty_on_treq (& mut self) -> SCTR_TXEMPTY_ON_TREQ_W < SCTR_SPEC , 3 > { SCTR_TXEMPTY_ON_TREQ_W :: new (self) } # [doc = "Bit 4 - Tx Trigger when slave FSM is in Tx Mode"] # [inline (always)] # [must_use] pub fn sctr_txtrig_txmode (& mut self) -> SCTR_TXTRIG_TXMODE_W <'_, SCTR_SPEC , 4 > { SCTR_TXTRIG_TXMODE_W :: new (self) } # [doc = "Bit 5 - Tx transfer waits when stale data in Tx FIFO. This prevents stale bytes left in the TX FIFO from automatically being sent on the next I2C packet. Note: this should be used with TXEMPTY_ON_TREQ set to prevent the Slave State Machine from waiting for TX FIFO data without an interrupt notification when the FIFO data is stale."] # [inline (always)] # [must_use] pub fn sctr_txwait_stale_txfifo (& mut self) -> SCTR_TXWAIT_STALE_TXFIFO_W < SCTR_SPEC , 5 > { SCTR_TXWAIT_STALE_TXFIFO_W :: new (self) } # [doc = "Bit 6 - Rx full interrupt generated on RREQ condition as indicated in SSR"] # [inline (always)] # [must_use] pub fn sctr_rxfull_on_rreq (& mut self) -> SCTR_RXFULL_ON_RREQ_W < SCTR_SPEC , 6 > { SCTR_RXFULL_ON_RREQ_W :: new (self) } # [doc = "Bit 7 - Enable Default Host Address"] # [inline (always)] # [must_use] pub fn sctr_en_defhostadr (& mut self) -> SCTR_EN_DEFHOSTADR_W < SCTR_SPEC , 7 > { SCTR_EN_DEFHOSTADR_W :: new (self) } # [doc = "Bit 8 - Enable Alert Response Address"] # [inline (always)] # [must_use] pub fn sctr_en_alrespadr (& mut self) -> SCTR_EN_ALRESPADR_W < SCTR_SPEC , 8 > { SCTR_EN_ALRESPADR_W :: new (self) } # [doc = "Bit 9 - Enable Deault device address"] # [inline (always)] # [must_use] pub fn sctr_en_defdevadr (& mut self) -> SCTR_EN_DEFDEVADR_W < SCTR_SPEC , 9 > { SCTR_EN_DEFDEVADR_W :: new (self) } # [doc = "Bit 10 - Slave Wakeup Enable"] # [inline (always)] # [must_use] pub fn sctr_swuen (& mut self) -> SCTR_SWUEN_W < SCTR_SPEC , 10 > { SCTR_SWUEN_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "I2C Slave Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sctr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sctr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct SCTR_SPEC ; impl crate :: RegisterSpec for SCTR_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`sctr::R`](R) reader structure"] impl crate :: Readable for SCTR_SPEC { } # [doc = "`write(|w| ..)` method takes [`sctr::W`](W) writer structure"] impl crate :: Writable for SCTR_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets SCTR to value 0x0404"] impl crate :: Resettable for SCTR_SPEC { const RESET_VALUE : Self :: Ux = 0x0404 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/sysctl/nmiiset.rs:1:2374 [INFO] [stdout] | [INFO] [stdout] 1 | ...e] pub fn nmiiset_wwdt0 (& mut self) -> NMIISET_WWDT0_W < NMIISET_SPEC , 1 > { NMIISET_WWDT0_W :: new (self) } # [doc = r" Writes raw ... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `NMIISET` writer"] pub type W = crate :: W < NMIISET_SPEC > ; # [doc = "Set the BORLVL NMI\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum NMIISET_BORLVL_AW { # [doc = "0: NO_EFFECT"] NMIISET_BORLVL_NO_EFFECT = 0 , # [doc = "1: SET"] NMIISET_BORLVL_SET = 1 , } impl From < NMIISET_BORLVL_AW > for bool { # [inline (always)] fn from (variant : NMIISET_BORLVL_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `NMIISET_BORLVL` writer - Set the BORLVL NMI"] pub type NMIISET_BORLVL_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , NMIISET_BORLVL_AW > ; impl < 'a , REG , const O : u8 > NMIISET_BORLVL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn nmiiset_borlvl_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (NMIISET_BORLVL_AW :: NMIISET_BORLVL_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn nmiiset_borlvl_set (self) -> & 'a mut crate :: W < REG > { self . variant (NMIISET_BORLVL_AW :: NMIISET_BORLVL_SET) } } # [doc = "Watch Dog 0 Fault\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum NMIISET_WWDT0_AW { # [doc = "0: NO_EFFECT"] NMIISET_WWDT0_NO_EFFECT = 0 , # [doc = "1: SET"] NMIISET_WWDT0_SET = 1 , } impl From < NMIISET_WWDT0_AW > for bool { # [inline (always)] fn from (variant : NMIISET_WWDT0_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `NMIISET_WWDT0` writer - Watch Dog 0 Fault"] pub type NMIISET_WWDT0_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , NMIISET_WWDT0_AW > ; impl < 'a , REG , const O : u8 > NMIISET_WWDT0_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn nmiiset_wwdt0_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (NMIISET_WWDT0_AW :: NMIISET_WWDT0_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn nmiiset_wwdt0_set (self) -> & 'a mut crate :: W < REG > { self . variant (NMIISET_WWDT0_AW :: NMIISET_WWDT0_SET) } } impl W { # [doc = "Bit 0 - Set the BORLVL NMI"] # [inline (always)] # [must_use] pub fn nmiiset_borlvl (& mut self) -> NMIISET_BORLVL_W < NMIISET_SPEC , 0 > { NMIISET_BORLVL_W :: new (self) } # [doc = "Bit 1 - Watch Dog 0 Fault"] # [inline (always)] # [must_use] pub fn nmiiset_wwdt0 (& mut self) -> NMIISET_WWDT0_W <'_, NMIISET_SPEC , 1 > { NMIISET_WWDT0_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "NMI interrupt set\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`nmiiset::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct NMIISET_SPEC ; impl crate :: RegisterSpec for NMIISET_SPEC { type Ux = u32 ; } # [doc = "`write(|w| ..)` method takes [`nmiiset::W`](W) writer structure"] impl crate :: Writable for NMIISET_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets NMIISET to value 0"] impl crate :: Resettable for NMIISET_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/i2c1/timeout_ctl.rs:1:7920 [INFO] [stdout] | [INFO] [stdout] 1 | ...timeout_ctl_tcntla (& mut self) -> TIMEOUT_CTL_TCNTLA_W < TIMEOUT_CTL_SPEC , 0 > { TIMEOUT_CTL_TCNTLA_W :: new (self) } # [doc = "Bit ... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `TIMEOUT_CTL` reader"] pub type R = crate :: R < TIMEOUT_CTL_SPEC > ; # [doc = "Register `TIMEOUT_CTL` writer"] pub type W = crate :: W < TIMEOUT_CTL_SPEC > ; # [doc = "Field `TIMEOUT_CTL_TCNTLA` reader - Timeout counter A load value Counter A is used for SCL low detection. This field contains the upper 8 bits of a 12-bit pre-load value for the Timeout A count. NOTE: The value of CNTLA must be greater than 1h. Each count is equal to 520 times the timeout period of functional clock. For example, with 8MHz functional clock and a 100KHz operating I2C clock, one timeout period will be equal to (1 / 8MHz) * 520 or 65 us."] pub type TIMEOUT_CTL_TCNTLA_R = crate :: FieldReader ; # [doc = "Field `TIMEOUT_CTL_TCNTLA` writer - Timeout counter A load value Counter A is used for SCL low detection. This field contains the upper 8 bits of a 12-bit pre-load value for the Timeout A count. NOTE: The value of CNTLA must be greater than 1h. Each count is equal to 520 times the timeout period of functional clock. For example, with 8MHz functional clock and a 100KHz operating I2C clock, one timeout period will be equal to (1 / 8MHz) * 520 or 65 us."] pub type TIMEOUT_CTL_TCNTLA_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 8 , O > ; # [doc = "Field `TIMEOUT_CTL_TCNTAEN` reader - Timeout Counter A Enable"] pub type TIMEOUT_CTL_TCNTAEN_R = crate :: BitReader < TIMEOUT_CTL_TCNTAEN_A > ; # [doc = "Timeout Counter A Enable\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum TIMEOUT_CTL_TCNTAEN_A { # [doc = "0: DISABLE"] TIMEOUT_CTL_TCNTAEN_DISABLE = 0 , # [doc = "1: ENABLE"] TIMEOUT_CTL_TCNTAEN_ENABLE = 1 , } impl From < TIMEOUT_CTL_TCNTAEN_A > for bool { # [inline (always)] fn from (variant : TIMEOUT_CTL_TCNTAEN_A) -> Self { variant as u8 != 0 } } impl TIMEOUT_CTL_TCNTAEN_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> TIMEOUT_CTL_TCNTAEN_A { match self . bits { false => TIMEOUT_CTL_TCNTAEN_A :: TIMEOUT_CTL_TCNTAEN_DISABLE , true => TIMEOUT_CTL_TCNTAEN_A :: TIMEOUT_CTL_TCNTAEN_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_timeout_ctl_tcntaen_disable (& self) -> bool { * self == TIMEOUT_CTL_TCNTAEN_A :: TIMEOUT_CTL_TCNTAEN_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_timeout_ctl_tcntaen_enable (& self) -> bool { * self == TIMEOUT_CTL_TCNTAEN_A :: TIMEOUT_CTL_TCNTAEN_ENABLE } } # [doc = "Field `TIMEOUT_CTL_TCNTAEN` writer - Timeout Counter A Enable"] pub type TIMEOUT_CTL_TCNTAEN_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , TIMEOUT_CTL_TCNTAEN_A > ; impl < 'a , REG , const O : u8 > TIMEOUT_CTL_TCNTAEN_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn timeout_ctl_tcntaen_disable (self) -> & 'a mut crate :: W < REG > { self . variant (TIMEOUT_CTL_TCNTAEN_A :: TIMEOUT_CTL_TCNTAEN_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn timeout_ctl_tcntaen_enable (self) -> & 'a mut crate :: W < REG > { self . variant (TIMEOUT_CTL_TCNTAEN_A :: TIMEOUT_CTL_TCNTAEN_ENABLE) } } # [doc = "Field `TIMEOUT_CTL_TCNTLB` reader - Timeout Count B Load: Counter B is used for SCL High Detection. This field contains the upper 8 bits of a 12-bit pre-load value for the Timeout B count. NOTE: The value of CNTLB must be greater than 1h. Each count is equal to 1* clock period. For example, with 10MHz functional clock one timeout period will be equal to1*100ns."] pub type TIMEOUT_CTL_TCNTLB_R = crate :: FieldReader ; # [doc = "Field `TIMEOUT_CTL_TCNTLB` writer - Timeout Count B Load: Counter B is used for SCL High Detection. This field contains the upper 8 bits of a 12-bit pre-load value for the Timeout B count. NOTE: The value of CNTLB must be greater than 1h. Each count is equal to 1* clock period. For example, with 10MHz functional clock one timeout period will be equal to1*100ns."] pub type TIMEOUT_CTL_TCNTLB_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 8 , O > ; # [doc = "Field `TIMEOUT_CTL_TCNTBEN` reader - Timeout Counter B Enable"] pub type TIMEOUT_CTL_TCNTBEN_R = crate :: BitReader < TIMEOUT_CTL_TCNTBEN_A > ; # [doc = "Timeout Counter B Enable\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum TIMEOUT_CTL_TCNTBEN_A { # [doc = "0: DISABLE"] TIMEOUT_CTL_TCNTBEN_DISABLE = 0 , # [doc = "1: ENABLE"] TIMEOUT_CTL_TCNTBEN_ENABLE = 1 , } impl From < TIMEOUT_CTL_TCNTBEN_A > for bool { # [inline (always)] fn from (variant : TIMEOUT_CTL_TCNTBEN_A) -> Self { variant as u8 != 0 } } impl TIMEOUT_CTL_TCNTBEN_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> TIMEOUT_CTL_TCNTBEN_A { match self . bits { false => TIMEOUT_CTL_TCNTBEN_A :: TIMEOUT_CTL_TCNTBEN_DISABLE , true => TIMEOUT_CTL_TCNTBEN_A :: TIMEOUT_CTL_TCNTBEN_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_timeout_ctl_tcntben_disable (& self) -> bool { * self == TIMEOUT_CTL_TCNTBEN_A :: TIMEOUT_CTL_TCNTBEN_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_timeout_ctl_tcntben_enable (& self) -> bool { * self == TIMEOUT_CTL_TCNTBEN_A :: TIMEOUT_CTL_TCNTBEN_ENABLE } } # [doc = "Field `TIMEOUT_CTL_TCNTBEN` writer - Timeout Counter B Enable"] pub type TIMEOUT_CTL_TCNTBEN_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , TIMEOUT_CTL_TCNTBEN_A > ; impl < 'a , REG , const O : u8 > TIMEOUT_CTL_TCNTBEN_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn timeout_ctl_tcntben_disable (self) -> & 'a mut crate :: W < REG > { self . variant (TIMEOUT_CTL_TCNTBEN_A :: TIMEOUT_CTL_TCNTBEN_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn timeout_ctl_tcntben_enable (self) -> & 'a mut crate :: W < REG > { self . variant (TIMEOUT_CTL_TCNTBEN_A :: TIMEOUT_CTL_TCNTBEN_ENABLE) } } impl R { # [doc = "Bits 0:7 - Timeout counter A load value Counter A is used for SCL low detection. This field contains the upper 8 bits of a 12-bit pre-load value for the Timeout A count. NOTE: The value of CNTLA must be greater than 1h. Each count is equal to 520 times the timeout period of functional clock. For example, with 8MHz functional clock and a 100KHz operating I2C clock, one timeout period will be equal to (1 / 8MHz) * 520 or 65 us."] # [inline (always)] pub fn timeout_ctl_tcntla (& self) -> TIMEOUT_CTL_TCNTLA_R { TIMEOUT_CTL_TCNTLA_R :: new ((self . bits & 0xff) as u8) } # [doc = "Bit 15 - Timeout Counter A Enable"] # [inline (always)] pub fn timeout_ctl_tcntaen (& self) -> TIMEOUT_CTL_TCNTAEN_R { TIMEOUT_CTL_TCNTAEN_R :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bits 16:23 - Timeout Count B Load: Counter B is used for SCL High Detection. This field contains the upper 8 bits of a 12-bit pre-load value for the Timeout B count. NOTE: The value of CNTLB must be greater than 1h. Each count is equal to 1* clock period. For example, with 10MHz functional clock one timeout period will be equal to1*100ns."] # [inline (always)] pub fn timeout_ctl_tcntlb (& self) -> TIMEOUT_CTL_TCNTLB_R { TIMEOUT_CTL_TCNTLB_R :: new (((self . bits >> 16) & 0xff) as u8) } # [doc = "Bit 31 - Timeout Counter B Enable"] # [inline (always)] pub fn timeout_ctl_tcntben (& self) -> TIMEOUT_CTL_TCNTBEN_R { TIMEOUT_CTL_TCNTBEN_R :: new (((self . bits >> 31) & 1) != 0) } } impl W { # [doc = "Bits 0:7 - Timeout counter A load value Counter A is used for SCL low detection. This field contains the upper 8 bits of a 12-bit pre-load value for the Timeout A count. NOTE: The value of CNTLA must be greater than 1h. Each count is equal to 520 times the timeout period of functional clock. For example, with 8MHz functional clock and a 100KHz operating I2C clock, one timeout period will be equal to (1 / 8MHz) * 520 or 65 us."] # [inline (always)] # [must_use] pub fn timeout_ctl_tcntla (& mut self) -> TIMEOUT_CTL_TCNTLA_W <'_, TIMEOUT_CTL_SPEC , 0 > { TIMEOUT_CTL_TCNTLA_W :: new (self) } # [doc = "Bit 15 - Timeout Counter A Enable"] # [inline (always)] # [must_use] pub fn timeout_ctl_tcntaen (& mut self) -> TIMEOUT_CTL_TCNTAEN_W < TIMEOUT_CTL_SPEC , 15 > { TIMEOUT_CTL_TCNTAEN_W :: new (self) } # [doc = "Bits 16:23 - Timeout Count B Load: Counter B is used for SCL High Detection. This field contains the upper 8 bits of a 12-bit pre-load value for the Timeout B count. NOTE: The value of CNTLB must be greater than 1h. Each count is equal to 1* clock period. For example, with 10MHz functional clock one timeout period will be equal to1*100ns."] # [inline (always)] # [must_use] pub fn timeout_ctl_tcntlb (& mut self) -> TIMEOUT_CTL_TCNTLB_W < TIMEOUT_CTL_SPEC , 16 > { TIMEOUT_CTL_TCNTLB_W :: new (self) } # [doc = "Bit 31 - Timeout Counter B Enable"] # [inline (always)] # [must_use] pub fn timeout_ctl_tcntben (& mut self) -> TIMEOUT_CTL_TCNTBEN_W < TIMEOUT_CTL_SPEC , 31 > { TIMEOUT_CTL_TCNTBEN_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "I2C Timeout Count Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`timeout_ctl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`timeout_ctl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct TIMEOUT_CTL_SPEC ; impl crate :: RegisterSpec for TIMEOUT_CTL_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`timeout_ctl::R`](R) reader structure"] impl crate :: Readable for TIMEOUT_CTL_SPEC { } # [doc = "`write(|w| ..)` method takes [`timeout_ctl::W`](W) writer structure"] impl crate :: Writable for TIMEOUT_CTL_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets TIMEOUT_CTL to value 0x0002_0002"] impl crate :: Resettable for TIMEOUT_CTL_SPEC { const RESET_VALUE : Self :: Ux = 0x0002_0002 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/timg4/octl_01.rs:1:10185 [INFO] [stdout] | [INFO] [stdout] 1 | ...pub fn octl_01_ccpoinv (& mut self) -> OCTL_01_CCPOINV_W < OCTL_01_SPEC , 4 > { OCTL_01_CCPOINV_W :: new (self) } # [doc = "Bit 5 - CC... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `OCTL_01[%s]` reader"] pub type R = crate :: R < OCTL_01_SPEC > ; # [doc = "Register `OCTL_01[%s]` writer"] pub type W = crate :: W < OCTL_01_SPEC > ; # [doc = "Field `OCTL_01_CCPO` reader - CCP Output Source"] pub type OCTL_01_CCPO_R = crate :: FieldReader < OCTL_01_CCPO_A > ; # [doc = "CCP Output Source\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum OCTL_01_CCPO_A { # [doc = "0: FUNCVAL"] OCTL_01_CCPO_FUNCVAL = 0 , # [doc = "1: LOAD"] OCTL_01_CCPO_LOAD = 1 , # [doc = "2: CMPVAL"] OCTL_01_CCPO_CMPVAL = 2 , # [doc = "4: ZERO"] OCTL_01_CCPO_ZERO = 4 , # [doc = "5: CAPCOND"] OCTL_01_CCPO_CAPCOND = 5 , # [doc = "6: FAULTCOND"] OCTL_01_CCPO_FAULTCOND = 6 , # [doc = "8: CC0_MIRROR_ALL"] OCTL_01_CCPO_CC0_MIRROR_ALL = 8 , # [doc = "9: CC1_MIRROR_ALL"] OCTL_01_CCPO_CC1_MIRROR_ALL = 9 , # [doc = "12: DEADBAND"] OCTL_01_CCPO_DEADBAND = 12 , # [doc = "13: CNTDIR"] OCTL_01_CCPO_CNTDIR = 13 , } impl From < OCTL_01_CCPO_A > for u8 { # [inline (always)] fn from (variant : OCTL_01_CCPO_A) -> Self { variant as _ } } impl crate :: FieldSpec for OCTL_01_CCPO_A { type Ux = u8 ; } impl OCTL_01_CCPO_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < OCTL_01_CCPO_A > { match self . bits { 0 => Some (OCTL_01_CCPO_A :: OCTL_01_CCPO_FUNCVAL) , 1 => Some (OCTL_01_CCPO_A :: OCTL_01_CCPO_LOAD) , 2 => Some (OCTL_01_CCPO_A :: OCTL_01_CCPO_CMPVAL) , 4 => Some (OCTL_01_CCPO_A :: OCTL_01_CCPO_ZERO) , 5 => Some (OCTL_01_CCPO_A :: OCTL_01_CCPO_CAPCOND) , 6 => Some (OCTL_01_CCPO_A :: OCTL_01_CCPO_FAULTCOND) , 8 => Some (OCTL_01_CCPO_A :: OCTL_01_CCPO_CC0_MIRROR_ALL) , 9 => Some (OCTL_01_CCPO_A :: OCTL_01_CCPO_CC1_MIRROR_ALL) , 12 => Some (OCTL_01_CCPO_A :: OCTL_01_CCPO_DEADBAND) , 13 => Some (OCTL_01_CCPO_A :: OCTL_01_CCPO_CNTDIR) , _ => None , } } # [doc = "FUNCVAL"] # [inline (always)] pub fn is_octl_01_ccpo_funcval (& self) -> bool { * self == OCTL_01_CCPO_A :: OCTL_01_CCPO_FUNCVAL } # [doc = "LOAD"] # [inline (always)] pub fn is_octl_01_ccpo_load (& self) -> bool { * self == OCTL_01_CCPO_A :: OCTL_01_CCPO_LOAD } # [doc = "CMPVAL"] # [inline (always)] pub fn is_octl_01_ccpo_cmpval (& self) -> bool { * self == OCTL_01_CCPO_A :: OCTL_01_CCPO_CMPVAL } # [doc = "ZERO"] # [inline (always)] pub fn is_octl_01_ccpo_zero (& self) -> bool { * self == OCTL_01_CCPO_A :: OCTL_01_CCPO_ZERO } # [doc = "CAPCOND"] # [inline (always)] pub fn is_octl_01_ccpo_capcond (& self) -> bool { * self == OCTL_01_CCPO_A :: OCTL_01_CCPO_CAPCOND } # [doc = "FAULTCOND"] # [inline (always)] pub fn is_octl_01_ccpo_faultcond (& self) -> bool { * self == OCTL_01_CCPO_A :: OCTL_01_CCPO_FAULTCOND } # [doc = "CC0_MIRROR_ALL"] # [inline (always)] pub fn is_octl_01_ccpo_cc0_mirror_all (& self) -> bool { * self == OCTL_01_CCPO_A :: OCTL_01_CCPO_CC0_MIRROR_ALL } # [doc = "CC1_MIRROR_ALL"] # [inline (always)] pub fn is_octl_01_ccpo_cc1_mirror_all (& self) -> bool { * self == OCTL_01_CCPO_A :: OCTL_01_CCPO_CC1_MIRROR_ALL } # [doc = "DEADBAND"] # [inline (always)] pub fn is_octl_01_ccpo_deadband (& self) -> bool { * self == OCTL_01_CCPO_A :: OCTL_01_CCPO_DEADBAND } # [doc = "CNTDIR"] # [inline (always)] pub fn is_octl_01_ccpo_cntdir (& self) -> bool { * self == OCTL_01_CCPO_A :: OCTL_01_CCPO_CNTDIR } } # [doc = "Field `OCTL_01_CCPO` writer - CCP Output Source"] pub type OCTL_01_CCPO_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 4 , O , OCTL_01_CCPO_A > ; impl < 'a , REG , const O : u8 > OCTL_01_CCPO_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "FUNCVAL"] # [inline (always)] pub fn octl_01_ccpo_funcval (self) -> & 'a mut crate :: W < REG > { self . variant (OCTL_01_CCPO_A :: OCTL_01_CCPO_FUNCVAL) } # [doc = "LOAD"] # [inline (always)] pub fn octl_01_ccpo_load (self) -> & 'a mut crate :: W < REG > { self . variant (OCTL_01_CCPO_A :: OCTL_01_CCPO_LOAD) } # [doc = "CMPVAL"] # [inline (always)] pub fn octl_01_ccpo_cmpval (self) -> & 'a mut crate :: W < REG > { self . variant (OCTL_01_CCPO_A :: OCTL_01_CCPO_CMPVAL) } # [doc = "ZERO"] # [inline (always)] pub fn octl_01_ccpo_zero (self) -> & 'a mut crate :: W < REG > { self . variant (OCTL_01_CCPO_A :: OCTL_01_CCPO_ZERO) } # [doc = "CAPCOND"] # [inline (always)] pub fn octl_01_ccpo_capcond (self) -> & 'a mut crate :: W < REG > { self . variant (OCTL_01_CCPO_A :: OCTL_01_CCPO_CAPCOND) } # [doc = "FAULTCOND"] # [inline (always)] pub fn octl_01_ccpo_faultcond (self) -> & 'a mut crate :: W < REG > { self . variant (OCTL_01_CCPO_A :: OCTL_01_CCPO_FAULTCOND) } # [doc = "CC0_MIRROR_ALL"] # [inline (always)] pub fn octl_01_ccpo_cc0_mirror_all (self) -> & 'a mut crate :: W < REG > { self . variant (OCTL_01_CCPO_A :: OCTL_01_CCPO_CC0_MIRROR_ALL) } # [doc = "CC1_MIRROR_ALL"] # [inline (always)] pub fn octl_01_ccpo_cc1_mirror_all (self) -> & 'a mut crate :: W < REG > { self . variant (OCTL_01_CCPO_A :: OCTL_01_CCPO_CC1_MIRROR_ALL) } # [doc = "DEADBAND"] # [inline (always)] pub fn octl_01_ccpo_deadband (self) -> & 'a mut crate :: W < REG > { self . variant (OCTL_01_CCPO_A :: OCTL_01_CCPO_DEADBAND) } # [doc = "CNTDIR"] # [inline (always)] pub fn octl_01_ccpo_cntdir (self) -> & 'a mut crate :: W < REG > { self . variant (OCTL_01_CCPO_A :: OCTL_01_CCPO_CNTDIR) } } # [doc = "Field `OCTL_01_CCPOINV` reader - CCP Output Invert The output as selected by CCPO is conditionally inverted."] pub type OCTL_01_CCPOINV_R = crate :: BitReader < OCTL_01_CCPOINV_A > ; # [doc = "CCP Output Invert The output as selected by CCPO is conditionally inverted.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum OCTL_01_CCPOINV_A { # [doc = "0: NOINV"] OCTL_01_CCPOINV_NOINV = 0 , # [doc = "1: INV"] OCTL_01_CCPOINV_INV = 1 , } impl From < OCTL_01_CCPOINV_A > for bool { # [inline (always)] fn from (variant : OCTL_01_CCPOINV_A) -> Self { variant as u8 != 0 } } impl OCTL_01_CCPOINV_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> OCTL_01_CCPOINV_A { match self . bits { false => OCTL_01_CCPOINV_A :: OCTL_01_CCPOINV_NOINV , true => OCTL_01_CCPOINV_A :: OCTL_01_CCPOINV_INV , } } # [doc = "NOINV"] # [inline (always)] pub fn is_octl_01_ccpoinv_noinv (& self) -> bool { * self == OCTL_01_CCPOINV_A :: OCTL_01_CCPOINV_NOINV } # [doc = "INV"] # [inline (always)] pub fn is_octl_01_ccpoinv_inv (& self) -> bool { * self == OCTL_01_CCPOINV_A :: OCTL_01_CCPOINV_INV } } # [doc = "Field `OCTL_01_CCPOINV` writer - CCP Output Invert The output as selected by CCPO is conditionally inverted."] pub type OCTL_01_CCPOINV_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , OCTL_01_CCPOINV_A > ; impl < 'a , REG , const O : u8 > OCTL_01_CCPOINV_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NOINV"] # [inline (always)] pub fn octl_01_ccpoinv_noinv (self) -> & 'a mut crate :: W < REG > { self . variant (OCTL_01_CCPOINV_A :: OCTL_01_CCPOINV_NOINV) } # [doc = "INV"] # [inline (always)] pub fn octl_01_ccpoinv_inv (self) -> & 'a mut crate :: W < REG > { self . variant (OCTL_01_CCPOINV_A :: OCTL_01_CCPOINV_INV) } } # [doc = "Field `OCTL_01_CCPIV` reader - CCP Initial Value This bit specifies the logical value put on the signal generator state while the counter is disabled (CTRCTL.EN == 0)."] pub type OCTL_01_CCPIV_R = crate :: BitReader < OCTL_01_CCPIV_A > ; # [doc = "CCP Initial Value This bit specifies the logical value put on the signal generator state while the counter is disabled (CTRCTL.EN == 0).\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum OCTL_01_CCPIV_A { # [doc = "0: LOW"] OCTL_01_CCPIV_LOW = 0 , # [doc = "1: HIGH"] OCTL_01_CCPIV_HIGH = 1 , } impl From < OCTL_01_CCPIV_A > for bool { # [inline (always)] fn from (variant : OCTL_01_CCPIV_A) -> Self { variant as u8 != 0 } } impl OCTL_01_CCPIV_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> OCTL_01_CCPIV_A { match self . bits { false => OCTL_01_CCPIV_A :: OCTL_01_CCPIV_LOW , true => OCTL_01_CCPIV_A :: OCTL_01_CCPIV_HIGH , } } # [doc = "LOW"] # [inline (always)] pub fn is_octl_01_ccpiv_low (& self) -> bool { * self == OCTL_01_CCPIV_A :: OCTL_01_CCPIV_LOW } # [doc = "HIGH"] # [inline (always)] pub fn is_octl_01_ccpiv_high (& self) -> bool { * self == OCTL_01_CCPIV_A :: OCTL_01_CCPIV_HIGH } } # [doc = "Field `OCTL_01_CCPIV` writer - CCP Initial Value This bit specifies the logical value put on the signal generator state while the counter is disabled (CTRCTL.EN == 0)."] pub type OCTL_01_CCPIV_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , OCTL_01_CCPIV_A > ; impl < 'a , REG , const O : u8 > OCTL_01_CCPIV_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "LOW"] # [inline (always)] pub fn octl_01_ccpiv_low (self) -> & 'a mut crate :: W < REG > { self . variant (OCTL_01_CCPIV_A :: OCTL_01_CCPIV_LOW) } # [doc = "HIGH"] # [inline (always)] pub fn octl_01_ccpiv_high (self) -> & 'a mut crate :: W < REG > { self . variant (OCTL_01_CCPIV_A :: OCTL_01_CCPIV_HIGH) } } impl R { # [doc = "Bits 0:3 - CCP Output Source"] # [inline (always)] pub fn octl_01_ccpo (& self) -> OCTL_01_CCPO_R { OCTL_01_CCPO_R :: new ((self . bits & 0x0f) as u8) } # [doc = "Bit 4 - CCP Output Invert The output as selected by CCPO is conditionally inverted."] # [inline (always)] pub fn octl_01_ccpoinv (& self) -> OCTL_01_CCPOINV_R { OCTL_01_CCPOINV_R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - CCP Initial Value This bit specifies the logical value put on the signal generator state while the counter is disabled (CTRCTL.EN == 0)."] # [inline (always)] pub fn octl_01_ccpiv (& self) -> OCTL_01_CCPIV_R { OCTL_01_CCPIV_R :: new (((self . bits >> 5) & 1) != 0) } } impl W { # [doc = "Bits 0:3 - CCP Output Source"] # [inline (always)] # [must_use] pub fn octl_01_ccpo (& mut self) -> OCTL_01_CCPO_W < OCTL_01_SPEC , 0 > { OCTL_01_CCPO_W :: new (self) } # [doc = "Bit 4 - CCP Output Invert The output as selected by CCPO is conditionally inverted."] # [inline (always)] # [must_use] pub fn octl_01_ccpoinv (& mut self) -> OCTL_01_CCPOINV_W <'_, OCTL_01_SPEC , 4 > { OCTL_01_CCPOINV_W :: new (self) } # [doc = "Bit 5 - CCP Initial Value This bit specifies the logical value put on the signal generator state while the counter is disabled (CTRCTL.EN == 0)."] # [inline (always)] # [must_use] pub fn octl_01_ccpiv (& mut self) -> OCTL_01_CCPIV_W < OCTL_01_SPEC , 5 > { OCTL_01_CCPIV_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "CCP Output Control Registers\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`octl_01::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`octl_01::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct OCTL_01_SPEC ; impl crate :: RegisterSpec for OCTL_01_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`octl_01::R`](R) reader structure"] impl crate :: Readable for OCTL_01_SPEC { } # [doc = "`write(|w| ..)` method takes [`octl_01::W`](W) writer structure"] impl crate :: Writable for OCTL_01_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets OCTL_01[%s] [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/gpioa/fsub_1.rs:1:2067 [INFO] [stdout] | [INFO] [stdout] 1 | ...e] pub fn fsub_1_chanid (& mut self) -> FSUB_1_CHANID_W < FSUB_1_SPEC , 0 > { FSUB_1_CHANID_W :: new (self) } # [doc = r" Writes raw b... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `FSUB_1` reader"] pub type R = crate :: R < FSUB_1_SPEC > ; # [doc = "Register `FSUB_1` writer"] pub type W = crate :: W < FSUB_1_SPEC > ; # [doc = "Field `FSUB_1_CHANID` reader - 0 = disconnected. 1-15 = connected to channelID = CHANID."] pub type FSUB_1_CHANID_R = crate :: FieldReader < FSUB_1_CHANID_A > ; # [doc = "0 = disconnected. 1-15 = connected to channelID = CHANID.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum FSUB_1_CHANID_A { # [doc = "0: UNCONNECTED"] FSUB_1_CHANID_UNCONNECTED = 0 , } impl From < FSUB_1_CHANID_A > for u8 { # [inline (always)] fn from (variant : FSUB_1_CHANID_A) -> Self { variant as _ } } impl crate :: FieldSpec for FSUB_1_CHANID_A { type Ux = u8 ; } impl FSUB_1_CHANID_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < FSUB_1_CHANID_A > { match self . bits { 0 => Some (FSUB_1_CHANID_A :: FSUB_1_CHANID_UNCONNECTED) , _ => None , } } # [doc = "UNCONNECTED"] # [inline (always)] pub fn is_fsub_1_chanid_unconnected (& self) -> bool { * self == FSUB_1_CHANID_A :: FSUB_1_CHANID_UNCONNECTED } } # [doc = "Field `FSUB_1_CHANID` writer - 0 = disconnected. 1-15 = connected to channelID = CHANID."] pub type FSUB_1_CHANID_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 2 , O , FSUB_1_CHANID_A > ; impl < 'a , REG , const O : u8 > FSUB_1_CHANID_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "UNCONNECTED"] # [inline (always)] pub fn fsub_1_chanid_unconnected (self) -> & 'a mut crate :: W < REG > { self . variant (FSUB_1_CHANID_A :: FSUB_1_CHANID_UNCONNECTED) } } impl R { # [doc = "Bits 0:1 - 0 = disconnected. 1-15 = connected to channelID = CHANID."] # [inline (always)] pub fn fsub_1_chanid (& self) -> FSUB_1_CHANID_R { FSUB_1_CHANID_R :: new ((self . bits & 3) as u8) } } impl W { # [doc = "Bits 0:1 - 0 = disconnected. 1-15 = connected to channelID = CHANID."] # [inline (always)] # [must_use] pub fn fsub_1_chanid (& mut self) -> FSUB_1_CHANID_W <'_, FSUB_1_SPEC , 0 > { FSUB_1_CHANID_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Subscriber Port 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fsub_1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fsub_1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct FSUB_1_SPEC ; impl crate :: RegisterSpec for FSUB_1_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`fsub_1::R`](R) reader structure"] impl crate :: Readable for FSUB_1_SPEC { } # [doc = "`write(|w| ..)` method takes [`fsub_1::W`](W) writer structure"] impl crate :: Writable for FSUB_1_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets FSUB_1 to value 0"] impl crate :: Resettable for FSUB_1_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/i2c1/soar.rs:1:5719 [INFO] [stdout] | [INFO] [stdout] 1 | ...st_use] pub fn soar_smode (& mut self) -> SOAR_SMODE_W < SOAR_SPEC , 15 > { SOAR_SMODE_W :: new (self) } # [doc = r" Writes raw bits t... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `SOAR` reader"] pub type R = crate :: R < SOAR_SPEC > ; # [doc = "Register `SOAR` writer"] pub type W = crate :: W < SOAR_SPEC > ; # [doc = "Field `SOAR_OAR` reader - I2C Slave Own Address: This field specifies bits A9 through A0 of the slave address. In 7-bit addressing mode as selected by I2CSOAR.MODE bit, the top 3 bits are don't care"] pub type SOAR_OAR_R = crate :: FieldReader < u16 > ; # [doc = "Field `SOAR_OAR` writer - I2C Slave Own Address: This field specifies bits A9 through A0 of the slave address. In 7-bit addressing mode as selected by I2CSOAR.MODE bit, the top 3 bits are don't care"] pub type SOAR_OAR_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 10 , O , u16 > ; # [doc = "Field `SOAR_OAREN` reader - I2C Slave Own Address Enable"] pub type SOAR_OAREN_R = crate :: BitReader < SOAR_OAREN_A > ; # [doc = "I2C Slave Own Address Enable\n\nValue on reset: 1"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum SOAR_OAREN_A { # [doc = "0: DISABLE"] SOAR_OAREN_DISABLE = 0 , # [doc = "1: ENABLE"] SOAR_OAREN_ENABLE = 1 , } impl From < SOAR_OAREN_A > for bool { # [inline (always)] fn from (variant : SOAR_OAREN_A) -> Self { variant as u8 != 0 } } impl SOAR_OAREN_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> SOAR_OAREN_A { match self . bits { false => SOAR_OAREN_A :: SOAR_OAREN_DISABLE , true => SOAR_OAREN_A :: SOAR_OAREN_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_soar_oaren_disable (& self) -> bool { * self == SOAR_OAREN_A :: SOAR_OAREN_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_soar_oaren_enable (& self) -> bool { * self == SOAR_OAREN_A :: SOAR_OAREN_ENABLE } } # [doc = "Field `SOAR_OAREN` writer - I2C Slave Own Address Enable"] pub type SOAR_OAREN_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , SOAR_OAREN_A > ; impl < 'a , REG , const O : u8 > SOAR_OAREN_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn soar_oaren_disable (self) -> & 'a mut crate :: W < REG > { self . variant (SOAR_OAREN_A :: SOAR_OAREN_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn soar_oaren_enable (self) -> & 'a mut crate :: W < REG > { self . variant (SOAR_OAREN_A :: SOAR_OAREN_ENABLE) } } # [doc = "Field `SOAR_SMODE` reader - This bit selects the adressing mode to be used in slave mode. When 0, 7-bit addressing is used. When 1, 10-bit addressing is used."] pub type SOAR_SMODE_R = crate :: BitReader < SOAR_SMODE_A > ; # [doc = "This bit selects the adressing mode to be used in slave mode. When 0, 7-bit addressing is used. When 1, 10-bit addressing is used.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum SOAR_SMODE_A { # [doc = "0: MODE7"] SOAR_SMODE_MODE7 = 0 , # [doc = "1: MODE10"] SOAR_SMODE_MODE10 = 1 , } impl From < SOAR_SMODE_A > for bool { # [inline (always)] fn from (variant : SOAR_SMODE_A) -> Self { variant as u8 != 0 } } impl SOAR_SMODE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> SOAR_SMODE_A { match self . bits { false => SOAR_SMODE_A :: SOAR_SMODE_MODE7 , true => SOAR_SMODE_A :: SOAR_SMODE_MODE10 , } } # [doc = "MODE7"] # [inline (always)] pub fn is_soar_smode_mode7 (& self) -> bool { * self == SOAR_SMODE_A :: SOAR_SMODE_MODE7 } # [doc = "MODE10"] # [inline (always)] pub fn is_soar_smode_mode10 (& self) -> bool { * self == SOAR_SMODE_A :: SOAR_SMODE_MODE10 } } # [doc = "Field `SOAR_SMODE` writer - This bit selects the adressing mode to be used in slave mode. When 0, 7-bit addressing is used. When 1, 10-bit addressing is used."] pub type SOAR_SMODE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , SOAR_SMODE_A > ; impl < 'a , REG , const O : u8 > SOAR_SMODE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "MODE7"] # [inline (always)] pub fn soar_smode_mode7 (self) -> & 'a mut crate :: W < REG > { self . variant (SOAR_SMODE_A :: SOAR_SMODE_MODE7) } # [doc = "MODE10"] # [inline (always)] pub fn soar_smode_mode10 (self) -> & 'a mut crate :: W < REG > { self . variant (SOAR_SMODE_A :: SOAR_SMODE_MODE10) } } impl R { # [doc = "Bits 0:9 - I2C Slave Own Address: This field specifies bits A9 through A0 of the slave address. In 7-bit addressing mode as selected by I2CSOAR.MODE bit, the top 3 bits are don't care"] # [inline (always)] pub fn soar_oar (& self) -> SOAR_OAR_R { SOAR_OAR_R :: new ((self . bits & 0x03ff) as u16) } # [doc = "Bit 14 - I2C Slave Own Address Enable"] # [inline (always)] pub fn soar_oaren (& self) -> SOAR_OAREN_R { SOAR_OAREN_R :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - This bit selects the adressing mode to be used in slave mode. When 0, 7-bit addressing is used. When 1, 10-bit addressing is used."] # [inline (always)] pub fn soar_smode (& self) -> SOAR_SMODE_R { SOAR_SMODE_R :: new (((self . bits >> 15) & 1) != 0) } } impl W { # [doc = "Bits 0:9 - I2C Slave Own Address: This field specifies bits A9 through A0 of the slave address. In 7-bit addressing mode as selected by I2CSOAR.MODE bit, the top 3 bits are don't care"] # [inline (always)] # [must_use] pub fn soar_oar (& mut self) -> SOAR_OAR_W < SOAR_SPEC , 0 > { SOAR_OAR_W :: new (self) } # [doc = "Bit 14 - I2C Slave Own Address Enable"] # [inline (always)] # [must_use] pub fn soar_oaren (& mut self) -> SOAR_OAREN_W < SOAR_SPEC , 14 > { SOAR_OAREN_W :: new (self) } # [doc = "Bit 15 - This bit selects the adressing mode to be used in slave mode. When 0, 7-bit addressing is used. When 1, 10-bit addressing is used."] # [inline (always)] # [must_use] pub fn soar_smode (& mut self) -> SOAR_SMODE_W <'_, SOAR_SPEC , 15 > { SOAR_SMODE_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "I2C Slave Own Address\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`soar::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`soar::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct SOAR_SPEC ; impl crate :: RegisterSpec for SOAR_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`soar::R`](R) reader structure"] impl crate :: Readable for SOAR_SPEC { } # [doc = "`write(|w| ..)` method takes [`soar::W`](W) writer structure"] impl crate :: Writable for SOAR_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets SOAR to value 0x4000"] impl crate :: Resettable for SOAR_SPEC { const RESET_VALUE : Self :: Ux = 0x4000 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/uart0/clksel.rs:1:6849 [INFO] [stdout] | [INFO] [stdout] 1 | ... fn clksel_busclk_sel (& mut self) -> CLKSEL_BUSCLK_SEL_W < CLKSEL_SPEC , 3 > { CLKSEL_BUSCLK_SEL_W :: new (self) } # [doc = r" Writes... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `CLKSEL` reader"] pub type R = crate :: R < CLKSEL_SPEC > ; # [doc = "Register `CLKSEL` writer"] pub type W = crate :: W < CLKSEL_SPEC > ; # [doc = "Field `CLKSEL_LFCLK_SEL` reader - Selects LFCLK as clock source if enabled"] pub type CLKSEL_LFCLK_SEL_R = crate :: BitReader < CLKSEL_LFCLK_SEL_A > ; # [doc = "Selects LFCLK as clock source if enabled\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CLKSEL_LFCLK_SEL_A { # [doc = "0: DISABLE"] CLKSEL_LFCLK_SEL_DISABLE = 0 , # [doc = "1: ENABLE"] CLKSEL_LFCLK_SEL_ENABLE = 1 , } impl From < CLKSEL_LFCLK_SEL_A > for bool { # [inline (always)] fn from (variant : CLKSEL_LFCLK_SEL_A) -> Self { variant as u8 != 0 } } impl CLKSEL_LFCLK_SEL_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CLKSEL_LFCLK_SEL_A { match self . bits { false => CLKSEL_LFCLK_SEL_A :: CLKSEL_LFCLK_SEL_DISABLE , true => CLKSEL_LFCLK_SEL_A :: CLKSEL_LFCLK_SEL_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_clksel_lfclk_sel_disable (& self) -> bool { * self == CLKSEL_LFCLK_SEL_A :: CLKSEL_LFCLK_SEL_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_clksel_lfclk_sel_enable (& self) -> bool { * self == CLKSEL_LFCLK_SEL_A :: CLKSEL_LFCLK_SEL_ENABLE } } # [doc = "Field `CLKSEL_LFCLK_SEL` writer - Selects LFCLK as clock source if enabled"] pub type CLKSEL_LFCLK_SEL_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CLKSEL_LFCLK_SEL_A > ; impl < 'a , REG , const O : u8 > CLKSEL_LFCLK_SEL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn clksel_lfclk_sel_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CLKSEL_LFCLK_SEL_A :: CLKSEL_LFCLK_SEL_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn clksel_lfclk_sel_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CLKSEL_LFCLK_SEL_A :: CLKSEL_LFCLK_SEL_ENABLE) } } # [doc = "Field `CLKSEL_MFCLK_SEL` reader - Selects MFCLK as clock source if enabled"] pub type CLKSEL_MFCLK_SEL_R = crate :: BitReader < CLKSEL_MFCLK_SEL_A > ; # [doc = "Selects MFCLK as clock source if enabled\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CLKSEL_MFCLK_SEL_A { # [doc = "0: DISABLE"] CLKSEL_MFCLK_SEL_DISABLE = 0 , # [doc = "1: ENABLE"] CLKSEL_MFCLK_SEL_ENABLE = 1 , } impl From < CLKSEL_MFCLK_SEL_A > for bool { # [inline (always)] fn from (variant : CLKSEL_MFCLK_SEL_A) -> Self { variant as u8 != 0 } } impl CLKSEL_MFCLK_SEL_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CLKSEL_MFCLK_SEL_A { match self . bits { false => CLKSEL_MFCLK_SEL_A :: CLKSEL_MFCLK_SEL_DISABLE , true => CLKSEL_MFCLK_SEL_A :: CLKSEL_MFCLK_SEL_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_clksel_mfclk_sel_disable (& self) -> bool { * self == CLKSEL_MFCLK_SEL_A :: CLKSEL_MFCLK_SEL_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_clksel_mfclk_sel_enable (& self) -> bool { * self == CLKSEL_MFCLK_SEL_A :: CLKSEL_MFCLK_SEL_ENABLE } } # [doc = "Field `CLKSEL_MFCLK_SEL` writer - Selects MFCLK as clock source if enabled"] pub type CLKSEL_MFCLK_SEL_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CLKSEL_MFCLK_SEL_A > ; impl < 'a , REG , const O : u8 > CLKSEL_MFCLK_SEL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn clksel_mfclk_sel_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CLKSEL_MFCLK_SEL_A :: CLKSEL_MFCLK_SEL_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn clksel_mfclk_sel_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CLKSEL_MFCLK_SEL_A :: CLKSEL_MFCLK_SEL_ENABLE) } } # [doc = "Field `CLKSEL_BUSCLK_SEL` reader - Selects BUS CLK as clock source if enabled"] pub type CLKSEL_BUSCLK_SEL_R = crate :: BitReader < CLKSEL_BUSCLK_SEL_A > ; # [doc = "Selects BUS CLK as clock source if enabled\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CLKSEL_BUSCLK_SEL_A { # [doc = "0: DISABLE"] CLKSEL_BUSCLK_SEL_DISABLE = 0 , # [doc = "1: ENABLE"] CLKSEL_BUSCLK_SEL_ENABLE = 1 , } impl From < CLKSEL_BUSCLK_SEL_A > for bool { # [inline (always)] fn from (variant : CLKSEL_BUSCLK_SEL_A) -> Self { variant as u8 != 0 } } impl CLKSEL_BUSCLK_SEL_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CLKSEL_BUSCLK_SEL_A { match self . bits { false => CLKSEL_BUSCLK_SEL_A :: CLKSEL_BUSCLK_SEL_DISABLE , true => CLKSEL_BUSCLK_SEL_A :: CLKSEL_BUSCLK_SEL_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_clksel_busclk_sel_disable (& self) -> bool { * self == CLKSEL_BUSCLK_SEL_A :: CLKSEL_BUSCLK_SEL_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_clksel_busclk_sel_enable (& self) -> bool { * self == CLKSEL_BUSCLK_SEL_A :: CLKSEL_BUSCLK_SEL_ENABLE } } # [doc = "Field `CLKSEL_BUSCLK_SEL` writer - Selects BUS CLK as clock source if enabled"] pub type CLKSEL_BUSCLK_SEL_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CLKSEL_BUSCLK_SEL_A > ; impl < 'a , REG , const O : u8 > CLKSEL_BUSCLK_SEL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn clksel_busclk_sel_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CLKSEL_BUSCLK_SEL_A :: CLKSEL_BUSCLK_SEL_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn clksel_busclk_sel_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CLKSEL_BUSCLK_SEL_A :: CLKSEL_BUSCLK_SEL_ENABLE) } } impl R { # [doc = "Bit 1 - Selects LFCLK as clock source if enabled"] # [inline (always)] pub fn clksel_lfclk_sel (& self) -> CLKSEL_LFCLK_SEL_R { CLKSEL_LFCLK_SEL_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - Selects MFCLK as clock source if enabled"] # [inline (always)] pub fn clksel_mfclk_sel (& self) -> CLKSEL_MFCLK_SEL_R { CLKSEL_MFCLK_SEL_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - Selects BUS CLK as clock source if enabled"] # [inline (always)] pub fn clksel_busclk_sel (& self) -> CLKSEL_BUSCLK_SEL_R { CLKSEL_BUSCLK_SEL_R :: new (((self . bits >> 3) & 1) != 0) } } impl W { # [doc = "Bit 1 - Selects LFCLK as clock source if enabled"] # [inline (always)] # [must_use] pub fn clksel_lfclk_sel (& mut self) -> CLKSEL_LFCLK_SEL_W < CLKSEL_SPEC , 1 > { CLKSEL_LFCLK_SEL_W :: new (self) } # [doc = "Bit 2 - Selects MFCLK as clock source if enabled"] # [inline (always)] # [must_use] pub fn clksel_mfclk_sel (& mut self) -> CLKSEL_MFCLK_SEL_W < CLKSEL_SPEC , 2 > { CLKSEL_MFCLK_SEL_W :: new (self) } # [doc = "Bit 3 - Selects BUS CLK as clock source if enabled"] # [inline (always)] # [must_use] pub fn clksel_busclk_sel (& mut self) -> CLKSEL_BUSCLK_SEL_W <'_, CLKSEL_SPEC , 3 > { CLKSEL_BUSCLK_SEL_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Clock Select for Ultra Low Power peripherals\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clksel::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clksel::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CLKSEL_SPEC ; impl crate :: RegisterSpec for CLKSEL_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`clksel::R`](R) reader structure"] impl crate :: Readable for CLKSEL_SPEC { } # [doc = "`write(|w| ..)` method takes [`clksel::W`](W) writer structure"] impl crate :: Writable for CLKSEL_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets CLKSEL to value 0"] impl crate :: Resettable for CLKSEL_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/i2c0/sackctl.rs:1:14094 [INFO] [stdout] | [INFO] [stdout] 1 | ...ackoen_on_pecnext (& mut self) -> SACKCTL_ACKOEN_ON_PECNEXT_W < SACKCTL_SPEC , 3 > { SACKCTL_ACKOEN_ON_PECNEXT_W :: new (self) } # [do... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `SACKCTL` reader"] pub type R = crate :: R < SACKCTL_SPEC > ; # [doc = "Register `SACKCTL` writer"] pub type W = crate :: W < SACKCTL_SPEC > ; # [doc = "Field `SACKCTL_ACKOEN` reader - I2C Slave ACK Override Enable"] pub type SACKCTL_ACKOEN_R = crate :: BitReader < SACKCTL_ACKOEN_A > ; # [doc = "I2C Slave ACK Override Enable\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum SACKCTL_ACKOEN_A { # [doc = "0: DISABLE"] SACKCTL_ACKOEN_DISABLE = 0 , # [doc = "1: ENABLE"] SACKCTL_ACKOEN_ENABLE = 1 , } impl From < SACKCTL_ACKOEN_A > for bool { # [inline (always)] fn from (variant : SACKCTL_ACKOEN_A) -> Self { variant as u8 != 0 } } impl SACKCTL_ACKOEN_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> SACKCTL_ACKOEN_A { match self . bits { false => SACKCTL_ACKOEN_A :: SACKCTL_ACKOEN_DISABLE , true => SACKCTL_ACKOEN_A :: SACKCTL_ACKOEN_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_sackctl_ackoen_disable (& self) -> bool { * self == SACKCTL_ACKOEN_A :: SACKCTL_ACKOEN_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_sackctl_ackoen_enable (& self) -> bool { * self == SACKCTL_ACKOEN_A :: SACKCTL_ACKOEN_ENABLE } } # [doc = "Field `SACKCTL_ACKOEN` writer - I2C Slave ACK Override Enable"] pub type SACKCTL_ACKOEN_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , SACKCTL_ACKOEN_A > ; impl < 'a , REG , const O : u8 > SACKCTL_ACKOEN_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn sackctl_ackoen_disable (self) -> & 'a mut crate :: W < REG > { self . variant (SACKCTL_ACKOEN_A :: SACKCTL_ACKOEN_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn sackctl_ackoen_enable (self) -> & 'a mut crate :: W < REG > { self . variant (SACKCTL_ACKOEN_A :: SACKCTL_ACKOEN_ENABLE) } } # [doc = "Field `SACKCTL_ACKOVAL` reader - I2C Slave ACK Override Value Note: for General Call this bit will be ignored if set to NACK and slave continues to receive data."] pub type SACKCTL_ACKOVAL_R = crate :: BitReader < SACKCTL_ACKOVAL_A > ; # [doc = "I2C Slave ACK Override Value Note: for General Call this bit will be ignored if set to NACK and slave continues to receive data.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum SACKCTL_ACKOVAL_A { # [doc = "0: DISABLE"] SACKCTL_ACKOVAL_DISABLE = 0 , # [doc = "1: ENABLE"] SACKCTL_ACKOVAL_ENABLE = 1 , } impl From < SACKCTL_ACKOVAL_A > for bool { # [inline (always)] fn from (variant : SACKCTL_ACKOVAL_A) -> Self { variant as u8 != 0 } } impl SACKCTL_ACKOVAL_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> SACKCTL_ACKOVAL_A { match self . bits { false => SACKCTL_ACKOVAL_A :: SACKCTL_ACKOVAL_DISABLE , true => SACKCTL_ACKOVAL_A :: SACKCTL_ACKOVAL_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_sackctl_ackoval_disable (& self) -> bool { * self == SACKCTL_ACKOVAL_A :: SACKCTL_ACKOVAL_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_sackctl_ackoval_enable (& self) -> bool { * self == SACKCTL_ACKOVAL_A :: SACKCTL_ACKOVAL_ENABLE } } # [doc = "Field `SACKCTL_ACKOVAL` writer - I2C Slave ACK Override Value Note: for General Call this bit will be ignored if set to NACK and slave continues to receive data."] pub type SACKCTL_ACKOVAL_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , SACKCTL_ACKOVAL_A > ; impl < 'a , REG , const O : u8 > SACKCTL_ACKOVAL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn sackctl_ackoval_disable (self) -> & 'a mut crate :: W < REG > { self . variant (SACKCTL_ACKOVAL_A :: SACKCTL_ACKOVAL_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn sackctl_ackoval_enable (self) -> & 'a mut crate :: W < REG > { self . variant (SACKCTL_ACKOVAL_A :: SACKCTL_ACKOVAL_ENABLE) } } # [doc = "Field `SACKCTL_ACKOEN_ON_START` reader - When set this bit will automatically turn on the Slave ACKOEN field following a Start Condition."] pub type SACKCTL_ACKOEN_ON_START_R = crate :: BitReader < SACKCTL_ACKOEN_ON_START_A > ; # [doc = "When set this bit will automatically turn on the Slave ACKOEN field following a Start Condition.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum SACKCTL_ACKOEN_ON_START_A { # [doc = "0: DISABLE"] SACKCTL_ACKOEN_ON_START_DISABLE = 0 , # [doc = "1: ENABLE"] SACKCTL_ACKOEN_ON_START_ENABLE = 1 , } impl From < SACKCTL_ACKOEN_ON_START_A > for bool { # [inline (always)] fn from (variant : SACKCTL_ACKOEN_ON_START_A) -> Self { variant as u8 != 0 } } impl SACKCTL_ACKOEN_ON_START_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> SACKCTL_ACKOEN_ON_START_A { match self . bits { false => SACKCTL_ACKOEN_ON_START_A :: SACKCTL_ACKOEN_ON_START_DISABLE , true => SACKCTL_ACKOEN_ON_START_A :: SACKCTL_ACKOEN_ON_START_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_sackctl_ackoen_on_start_disable (& self) -> bool { * self == SACKCTL_ACKOEN_ON_START_A :: SACKCTL_ACKOEN_ON_START_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_sackctl_ackoen_on_start_enable (& self) -> bool { * self == SACKCTL_ACKOEN_ON_START_A :: SACKCTL_ACKOEN_ON_START_ENABLE } } # [doc = "Field `SACKCTL_ACKOEN_ON_START` writer - When set this bit will automatically turn on the Slave ACKOEN field following a Start Condition."] pub type SACKCTL_ACKOEN_ON_START_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , SACKCTL_ACKOEN_ON_START_A > ; impl < 'a , REG , const O : u8 > SACKCTL_ACKOEN_ON_START_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn sackctl_ackoen_on_start_disable (self) -> & 'a mut crate :: W < REG > { self . variant (SACKCTL_ACKOEN_ON_START_A :: SACKCTL_ACKOEN_ON_START_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn sackctl_ackoen_on_start_enable (self) -> & 'a mut crate :: W < REG > { self . variant (SACKCTL_ACKOEN_ON_START_A :: SACKCTL_ACKOEN_ON_START_ENABLE) } } # [doc = "Field `SACKCTL_ACKOEN_ON_PECNEXT` reader - When set this bit will automatically turn on the Slave ACKOEN field following the ACK/NACK of the byte received just prior to the PEC byte. Note that when ACKOEN is set the PEC byte will not automatically be ACKed/NACKed by the State Machine and FW must perform this function by writing SLAVE_SACKCTL."] pub type SACKCTL_ACKOEN_ON_PECNEXT_R = crate :: BitReader < SACKCTL_ACKOEN_ON_PECNEXT_A > ; # [doc = "When set this bit will automatically turn on the Slave ACKOEN field following the ACK/NACK of the byte received just prior to the PEC byte. Note that when ACKOEN is set the PEC byte will not automatically be ACKed/NACKed by the State Machine and FW must perform this function by writing SLAVE_SACKCTL.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum SACKCTL_ACKOEN_ON_PECNEXT_A { # [doc = "0: DISABLE"] SACKCTL_ACKOEN_ON_PECNEXT_DISABLE = 0 , # [doc = "1: ENABLE"] SACKCTL_ACKOEN_ON_PECNEXT_ENABLE = 1 , } impl From < SACKCTL_ACKOEN_ON_PECNEXT_A > for bool { # [inline (always)] fn from (variant : SACKCTL_ACKOEN_ON_PECNEXT_A) -> Self { variant as u8 != 0 } } impl SACKCTL_ACKOEN_ON_PECNEXT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> SACKCTL_ACKOEN_ON_PECNEXT_A { match self . bits { false => SACKCTL_ACKOEN_ON_PECNEXT_A :: SACKCTL_ACKOEN_ON_PECNEXT_DISABLE , true => SACKCTL_ACKOEN_ON_PECNEXT_A :: SACKCTL_ACKOEN_ON_PECNEXT_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_sackctl_ackoen_on_pecnext_disable (& self) -> bool { * self == SACKCTL_ACKOEN_ON_PECNEXT_A :: SACKCTL_ACKOEN_ON_PECNEXT_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_sackctl_ackoen_on_pecnext_enable (& self) -> bool { * self == SACKCTL_ACKOEN_ON_PECNEXT_A :: SACKCTL_ACKOEN_ON_PECNEXT_ENABLE } } # [doc = "Field `SACKCTL_ACKOEN_ON_PECNEXT` writer - When set this bit will automatically turn on the Slave ACKOEN field following the ACK/NACK of the byte received just prior to the PEC byte. Note that when ACKOEN is set the PEC byte will not automatically be ACKed/NACKed by the State Machine and FW must perform this function by writing SLAVE_SACKCTL."] pub type SACKCTL_ACKOEN_ON_PECNEXT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , SACKCTL_ACKOEN_ON_PECNEXT_A > ; impl < 'a , REG , const O : u8 > SACKCTL_ACKOEN_ON_PECNEXT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn sackctl_ackoen_on_pecnext_disable (self) -> & 'a mut crate :: W < REG > { self . variant (SACKCTL_ACKOEN_ON_PECNEXT_A :: SACKCTL_ACKOEN_ON_PECNEXT_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn sackctl_ackoen_on_pecnext_enable (self) -> & 'a mut crate :: W < REG > { self . variant (SACKCTL_ACKOEN_ON_PECNEXT_A :: SACKCTL_ACKOEN_ON_PECNEXT_ENABLE) } } # [doc = "Field `SACKCTL_ACKOEN_ON_PECDONE` reader - When set this bit will automatically turn on the Slave ACKOEN field following the ACK/NACK of the received PEC byte."] pub type SACKCTL_ACKOEN_ON_PECDONE_R = crate :: BitReader < SACKCTL_ACKOEN_ON_PECDONE_A > ; # [doc = "When set this bit will automatically turn on the Slave ACKOEN field following the ACK/NACK of the received PEC byte.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum SACKCTL_ACKOEN_ON_PECDONE_A { # [doc = "0: DISABLE"] SACKCTL_ACKOEN_ON_PECDONE_DISABLE = 0 , # [doc = "1: ENABLE"] SACKCTL_ACKOEN_ON_PECDONE_ENABLE = 1 , } impl From < SACKCTL_ACKOEN_ON_PECDONE_A > for bool { # [inline (always)] fn from (variant : SACKCTL_ACKOEN_ON_PECDONE_A) -> Self { variant as u8 != 0 } } impl SACKCTL_ACKOEN_ON_PECDONE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> SACKCTL_ACKOEN_ON_PECDONE_A { match self . bits { false => SACKCTL_ACKOEN_ON_PECDONE_A :: SACKCTL_ACKOEN_ON_PECDONE_DISABLE , true => SACKCTL_ACKOEN_ON_PECDONE_A :: SACKCTL_ACKOEN_ON_PECDONE_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_sackctl_ackoen_on_pecdone_disable (& self) -> bool { * self == SACKCTL_ACKOEN_ON_PECDONE_A :: SACKCTL_ACKOEN_ON_PECDONE_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_sackctl_ackoen_on_pecdone_enable (& self) -> bool { * self == SACKCTL_ACKOEN_ON_PECDONE_A :: SACKCTL_ACKOEN_ON_PECDONE_ENABLE } } # [doc = "Field `SACKCTL_ACKOEN_ON_PECDONE` writer - When set this bit will automatically turn on the Slave ACKOEN field following the ACK/NACK of the received PEC byte."] pub type SACKCTL_ACKOEN_ON_PECDONE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , SACKCTL_ACKOEN_ON_PECDONE_A > ; impl < 'a , REG , const O : u8 > SACKCTL_ACKOEN_ON_PECDONE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn sackctl_ackoen_on_pecdone_disable (self) -> & 'a mut crate :: W < REG > { self . variant (SACKCTL_ACKOEN_ON_PECDONE_A :: SACKCTL_ACKOEN_ON_PECDONE_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn sackctl_ackoen_on_pecdone_enable (self) -> & 'a mut crate :: W < REG > { self . variant (SACKCTL_ACKOEN_ON_PECDONE_A :: SACKCTL_ACKOEN_ON_PECDONE_ENABLE) } } impl R { # [doc = "Bit 0 - I2C Slave ACK Override Enable"] # [inline (always)] pub fn sackctl_ackoen (& self) -> SACKCTL_ACKOEN_R { SACKCTL_ACKOEN_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - I2C Slave ACK Override Value Note: for General Call this bit will be ignored if set to NACK and slave continues to receive data."] # [inline (always)] pub fn sackctl_ackoval (& self) -> SACKCTL_ACKOVAL_R { SACKCTL_ACKOVAL_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - When set this bit will automatically turn on the Slave ACKOEN field following a Start Condition."] # [inline (always)] pub fn sackctl_ackoen_on_start (& self) -> SACKCTL_ACKOEN_ON_START_R { SACKCTL_ACKOEN_ON_START_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - When set this bit will automatically turn on the Slave ACKOEN field following the ACK/NACK of the byte received just prior to the PEC byte. Note that when ACKOEN is set the PEC byte will not automatically be ACKed/NACKed by the State Machine and FW must perform this function by writing SLAVE_SACKCTL."] # [inline (always)] pub fn sackctl_ackoen_on_pecnext (& self) -> SACKCTL_ACKOEN_ON_PECNEXT_R { SACKCTL_ACKOEN_ON_PECNEXT_R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - When set this bit will automatically turn on the Slave ACKOEN field following the ACK/NACK of the received PEC byte."] # [inline (always)] pub fn sackctl_ackoen_on_pecdone (& self) -> SACKCTL_ACKOEN_ON_PECDONE_R { SACKCTL_ACKOEN_ON_PECDONE_R :: new (((self . bits >> 4) & 1) != 0) } } impl W { # [doc = "Bit 0 - I2C Slave ACK Override Enable"] # [inline (always)] # [must_use] pub fn sackctl_ackoen (& mut self) -> SACKCTL_ACKOEN_W < SACKCTL_SPEC , 0 > { SACKCTL_ACKOEN_W :: new (self) } # [doc = "Bit 1 - I2C Slave ACK Override Value Note: for General Call this bit will be ignored if set to NACK and slave continues to receive data."] # [inline (always)] # [must_use] pub fn sackctl_ackoval (& mut self) -> SACKCTL_ACKOVAL_W < SACKCTL_SPEC , 1 > { SACKCTL_ACKOVAL_W :: new (self) } # [doc = "Bit 2 - When set this bit will automatically turn on the Slave ACKOEN field following a Start Condition."] # [inline (always)] # [must_use] pub fn sackctl_ackoen_on_start (& mut self) -> SACKCTL_ACKOEN_ON_START_W < SACKCTL_SPEC , 2 > { SACKCTL_ACKOEN_ON_START_W :: new (self) } # [doc = "Bit 3 - When set this bit will automatically turn on the Slave ACKOEN field following the ACK/NACK of the byte received just prior to the PEC byte. Note that when ACKOEN is set the PEC byte will not automatically be ACKed/NACKed by the State Machine and FW must perform this function by writing SLAVE_SACKCTL."] # [inline (always)] # [must_use] pub fn sackctl_ackoen_on_pecnext (& mut self) -> SACKCTL_ACKOEN_ON_PECNEXT_W <'_, SACKCTL_SPEC , 3 > { SACKCTL_ACKOEN_ON_PECNEXT_W :: new (self) } # [doc = "Bit 4 - When set this bit will automatically turn on the Slave ACKOEN field following the ACK/NACK of the received PEC byte."] # [inline (always)] # [must_use] pub fn sackctl_ackoen_on_pecdone (& mut self) -> SACKCTL_ACKOEN_ON_PECDONE_W < SACKCTL_SPEC , 4 > { SACKCTL_ACKOEN_ON_PECDONE_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "I2C Slave ACK Control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sackctl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sackctl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct SACKCTL_SPEC ; impl crate :: RegisterSpec for SACKCTL_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`sackctl::R`](R) reader structure"] impl crate :: Readable for SACKCTL_SPEC { } # [doc = "`write(|w| ..)` method takes [`sackctl::W`](W) writer structure"] impl crate :: Writable for SACKCTL_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets SACKCTL to value 0"] impl crate :: Resettable for SACKCTL_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/opa0/cfgbase.rs:1:4840 [INFO] [stdout] | [INFO] [stdout] 1 | ..._use] pub fn cfgbase_gbw (& mut self) -> CFGBASE_GBW_W < CFGBASE_SPEC , 0 > { CFGBASE_GBW_W :: new (self) } # [doc = "Bit 2 - Rail-to-... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `CFGBASE` reader"] pub type R = crate :: R < CFGBASE_SPEC > ; # [doc = "Register `CFGBASE` writer"] pub type W = crate :: W < CFGBASE_SPEC > ; # [doc = "Field `CFGBASE_GBW` reader - Select gain bandwidth which affects current as well the gain bandwidth. The lower gain bandwidth has lower current. See device specific datasheet for values. Can only be modified when STAT.BUSY=0."] pub type CFGBASE_GBW_R = crate :: BitReader < CFGBASE_GBW_A > ; # [doc = "Select gain bandwidth which affects current as well the gain bandwidth. The lower gain bandwidth has lower current. See device specific datasheet for values. Can only be modified when STAT.BUSY=0.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CFGBASE_GBW_A { # [doc = "0: LOWGAIN"] CFGBASE_GBW_LOWGAIN = 0 , # [doc = "1: HIGHGAIN"] CFGBASE_GBW_HIGHGAIN = 1 , } impl From < CFGBASE_GBW_A > for bool { # [inline (always)] fn from (variant : CFGBASE_GBW_A) -> Self { variant as u8 != 0 } } impl CFGBASE_GBW_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CFGBASE_GBW_A { match self . bits { false => CFGBASE_GBW_A :: CFGBASE_GBW_LOWGAIN , true => CFGBASE_GBW_A :: CFGBASE_GBW_HIGHGAIN , } } # [doc = "LOWGAIN"] # [inline (always)] pub fn is_cfgbase_gbw_lowgain (& self) -> bool { * self == CFGBASE_GBW_A :: CFGBASE_GBW_LOWGAIN } # [doc = "HIGHGAIN"] # [inline (always)] pub fn is_cfgbase_gbw_highgain (& self) -> bool { * self == CFGBASE_GBW_A :: CFGBASE_GBW_HIGHGAIN } } # [doc = "Field `CFGBASE_GBW` writer - Select gain bandwidth which affects current as well the gain bandwidth. The lower gain bandwidth has lower current. See device specific datasheet for values. Can only be modified when STAT.BUSY=0."] pub type CFGBASE_GBW_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CFGBASE_GBW_A > ; impl < 'a , REG , const O : u8 > CFGBASE_GBW_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "LOWGAIN"] # [inline (always)] pub fn cfgbase_gbw_lowgain (self) -> & 'a mut crate :: W < REG > { self . variant (CFGBASE_GBW_A :: CFGBASE_GBW_LOWGAIN) } # [doc = "HIGHGAIN"] # [inline (always)] pub fn cfgbase_gbw_highgain (self) -> & 'a mut crate :: W < REG > { self . variant (CFGBASE_GBW_A :: CFGBASE_GBW_HIGHGAIN) } } # [doc = "Field `CFGBASE_RRI` reader - Rail-to-rail input enable. Can only be modified when STAT.BUSY=0"] pub type CFGBASE_RRI_R = crate :: BitReader < CFGBASE_RRI_A > ; # [doc = "Rail-to-rail input enable. Can only be modified when STAT.BUSY=0\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CFGBASE_RRI_A { # [doc = "0: OFF"] CFGBASE_RRI_OFF = 0 , # [doc = "1: ON"] CFGBASE_RRI_ON = 1 , } impl From < CFGBASE_RRI_A > for bool { # [inline (always)] fn from (variant : CFGBASE_RRI_A) -> Self { variant as u8 != 0 } } impl CFGBASE_RRI_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CFGBASE_RRI_A { match self . bits { false => CFGBASE_RRI_A :: CFGBASE_RRI_OFF , true => CFGBASE_RRI_A :: CFGBASE_RRI_ON , } } # [doc = "OFF"] # [inline (always)] pub fn is_cfgbase_rri_off (& self) -> bool { * self == CFGBASE_RRI_A :: CFGBASE_RRI_OFF } # [doc = "ON"] # [inline (always)] pub fn is_cfgbase_rri_on (& self) -> bool { * self == CFGBASE_RRI_A :: CFGBASE_RRI_ON } } # [doc = "Field `CFGBASE_RRI` writer - Rail-to-rail input enable. Can only be modified when STAT.BUSY=0"] pub type CFGBASE_RRI_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CFGBASE_RRI_A > ; impl < 'a , REG , const O : u8 > CFGBASE_RRI_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "OFF"] # [inline (always)] pub fn cfgbase_rri_off (self) -> & 'a mut crate :: W < REG > { self . variant (CFGBASE_RRI_A :: CFGBASE_RRI_OFF) } # [doc = "ON"] # [inline (always)] pub fn cfgbase_rri_on (self) -> & 'a mut crate :: W < REG > { self . variant (CFGBASE_RRI_A :: CFGBASE_RRI_ON) } } impl R { # [doc = "Bit 0 - Select gain bandwidth which affects current as well the gain bandwidth. The lower gain bandwidth has lower current. See device specific datasheet for values. Can only be modified when STAT.BUSY=0."] # [inline (always)] pub fn cfgbase_gbw (& self) -> CFGBASE_GBW_R { CFGBASE_GBW_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 2 - Rail-to-rail input enable. Can only be modified when STAT.BUSY=0"] # [inline (always)] pub fn cfgbase_rri (& self) -> CFGBASE_RRI_R { CFGBASE_RRI_R :: new (((self . bits >> 2) & 1) != 0) } } impl W { # [doc = "Bit 0 - Select gain bandwidth which affects current as well the gain bandwidth. The lower gain bandwidth has lower current. See device specific datasheet for values. Can only be modified when STAT.BUSY=0."] # [inline (always)] # [must_use] pub fn cfgbase_gbw (& mut self) -> CFGBASE_GBW_W <'_, CFGBASE_SPEC , 0 > { CFGBASE_GBW_W :: new (self) } # [doc = "Bit 2 - Rail-to-rail input enable. Can only be modified when STAT.BUSY=0"] # [inline (always)] # [must_use] pub fn cfgbase_rri (& mut self) -> CFGBASE_RRI_W < CFGBASE_SPEC , 2 > { CFGBASE_RRI_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Configuration Base Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cfgbase::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cfgbase::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CFGBASE_SPEC ; impl crate :: RegisterSpec for CFGBASE_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`cfgbase::R`](R) reader structure"] impl crate :: Readable for CFGBASE_SPEC { } # [doc = "`write(|w| ..)` method takes [`cfgbase::W`](W) writer structure"] impl crate :: Writable for CFGBASE_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets CFGBASE to value 0"] impl crate :: Resettable for CFGBASE_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/spi0/int_event0_imask.rs:1:25201 [INFO] [stdout] | [INFO] [stdout] 1 | ...event0_imask_rx (& mut self) -> INT_EVENT0_IMASK_RX_W < INT_EVENT0_IMASK_SPEC , 3 > { INT_EVENT0_IMASK_RX_W :: new (self) } # [doc = "... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `INT_EVENT0_IMASK` reader"] pub type R = crate :: R < INT_EVENT0_IMASK_SPEC > ; # [doc = "Register `INT_EVENT0_IMASK` writer"] pub type W = crate :: W < INT_EVENT0_IMASK_SPEC > ; # [doc = "Field `INT_EVENT0_IMASK_RXFIFO_OVF` reader - RXFIFO overflow event mask."] pub type INT_EVENT0_IMASK_RXFIFO_OVF_R = crate :: BitReader < INT_EVENT0_IMASK_RXFIFO_OVF_A > ; # [doc = "RXFIFO overflow event mask.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_RXFIFO_OVF_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_RXFIFO_OVF_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_RXFIFO_OVF_SET = 1 , } impl From < INT_EVENT0_IMASK_RXFIFO_OVF_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_RXFIFO_OVF_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_RXFIFO_OVF_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_RXFIFO_OVF_A { match self . bits { false => INT_EVENT0_IMASK_RXFIFO_OVF_A :: INT_EVENT0_IMASK_RXFIFO_OVF_CLR , true => INT_EVENT0_IMASK_RXFIFO_OVF_A :: INT_EVENT0_IMASK_RXFIFO_OVF_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_rxfifo_ovf_clr (& self) -> bool { * self == INT_EVENT0_IMASK_RXFIFO_OVF_A :: INT_EVENT0_IMASK_RXFIFO_OVF_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_rxfifo_ovf_set (& self) -> bool { * self == INT_EVENT0_IMASK_RXFIFO_OVF_A :: INT_EVENT0_IMASK_RXFIFO_OVF_SET } } # [doc = "Field `INT_EVENT0_IMASK_RXFIFO_OVF` writer - RXFIFO overflow event mask."] pub type INT_EVENT0_IMASK_RXFIFO_OVF_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_RXFIFO_OVF_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_RXFIFO_OVF_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_rxfifo_ovf_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXFIFO_OVF_A :: INT_EVENT0_IMASK_RXFIFO_OVF_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_rxfifo_ovf_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXFIFO_OVF_A :: INT_EVENT0_IMASK_RXFIFO_OVF_SET) } } # [doc = "Field `INT_EVENT0_IMASK_PER` reader - Parity error event mask."] pub type INT_EVENT0_IMASK_PER_R = crate :: BitReader < INT_EVENT0_IMASK_PER_A > ; # [doc = "Parity error event mask.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_PER_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_PER_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_PER_SET = 1 , } impl From < INT_EVENT0_IMASK_PER_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_PER_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_PER_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_PER_A { match self . bits { false => INT_EVENT0_IMASK_PER_A :: INT_EVENT0_IMASK_PER_CLR , true => INT_EVENT0_IMASK_PER_A :: INT_EVENT0_IMASK_PER_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_per_clr (& self) -> bool { * self == INT_EVENT0_IMASK_PER_A :: INT_EVENT0_IMASK_PER_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_per_set (& self) -> bool { * self == INT_EVENT0_IMASK_PER_A :: INT_EVENT0_IMASK_PER_SET } } # [doc = "Field `INT_EVENT0_IMASK_PER` writer - Parity error event mask."] pub type INT_EVENT0_IMASK_PER_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_PER_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_PER_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_per_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_PER_A :: INT_EVENT0_IMASK_PER_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_per_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_PER_A :: INT_EVENT0_IMASK_PER_SET) } } # [doc = "Field `INT_EVENT0_IMASK_RTOUT` reader - Enable SPI Receive Time-Out event mask."] pub type INT_EVENT0_IMASK_RTOUT_R = crate :: BitReader < INT_EVENT0_IMASK_RTOUT_A > ; # [doc = "Enable SPI Receive Time-Out event mask.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_RTOUT_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_RTOUT_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_RTOUT_SET = 1 , } impl From < INT_EVENT0_IMASK_RTOUT_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_RTOUT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_RTOUT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_RTOUT_A { match self . bits { false => INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_CLR , true => INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_rtout_clr (& self) -> bool { * self == INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_rtout_set (& self) -> bool { * self == INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_SET } } # [doc = "Field `INT_EVENT0_IMASK_RTOUT` writer - Enable SPI Receive Time-Out event mask."] pub type INT_EVENT0_IMASK_RTOUT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_RTOUT_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_RTOUT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_rtout_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_rtout_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_SET) } } # [doc = "Field `INT_EVENT0_IMASK_RX` reader - Receive FIFO event.This interrupt is set if the selected Receive FIFO level has been reached"] pub type INT_EVENT0_IMASK_RX_R = crate :: BitReader < INT_EVENT0_IMASK_RX_A > ; # [doc = "Receive FIFO event.This interrupt is set if the selected Receive FIFO level has been reached\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_RX_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_RX_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_RX_SET = 1 , } impl From < INT_EVENT0_IMASK_RX_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_RX_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_RX_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_RX_A { match self . bits { false => INT_EVENT0_IMASK_RX_A :: INT_EVENT0_IMASK_RX_CLR , true => INT_EVENT0_IMASK_RX_A :: INT_EVENT0_IMASK_RX_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_rx_clr (& self) -> bool { * self == INT_EVENT0_IMASK_RX_A :: INT_EVENT0_IMASK_RX_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_rx_set (& self) -> bool { * self == INT_EVENT0_IMASK_RX_A :: INT_EVENT0_IMASK_RX_SET } } # [doc = "Field `INT_EVENT0_IMASK_RX` writer - Receive FIFO event.This interrupt is set if the selected Receive FIFO level has been reached"] pub type INT_EVENT0_IMASK_RX_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_RX_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_RX_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_rx_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RX_A :: INT_EVENT0_IMASK_RX_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_rx_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RX_A :: INT_EVENT0_IMASK_RX_SET) } } # [doc = "Field `INT_EVENT0_IMASK_TX` reader - Transmit FIFO event mask."] pub type INT_EVENT0_IMASK_TX_R = crate :: BitReader < INT_EVENT0_IMASK_TX_A > ; # [doc = "Transmit FIFO event mask.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_TX_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_TX_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_TX_SET = 1 , } impl From < INT_EVENT0_IMASK_TX_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_TX_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_TX_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_TX_A { match self . bits { false => INT_EVENT0_IMASK_TX_A :: INT_EVENT0_IMASK_TX_CLR , true => INT_EVENT0_IMASK_TX_A :: INT_EVENT0_IMASK_TX_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_tx_clr (& self) -> bool { * self == INT_EVENT0_IMASK_TX_A :: INT_EVENT0_IMASK_TX_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_tx_set (& self) -> bool { * self == INT_EVENT0_IMASK_TX_A :: INT_EVENT0_IMASK_TX_SET } } # [doc = "Field `INT_EVENT0_IMASK_TX` writer - Transmit FIFO event mask."] pub type INT_EVENT0_IMASK_TX_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_TX_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_TX_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_tx_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_TX_A :: INT_EVENT0_IMASK_TX_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_tx_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_TX_A :: INT_EVENT0_IMASK_TX_SET) } } # [doc = "Field `INT_EVENT0_IMASK_TXEMPTY` reader - Transmit FIFO Empty event mask."] pub type INT_EVENT0_IMASK_TXEMPTY_R = crate :: BitReader < INT_EVENT0_IMASK_TXEMPTY_A > ; # [doc = "Transmit FIFO Empty event mask.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_TXEMPTY_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_TXEMPTY_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_TXEMPTY_SET = 1 , } impl From < INT_EVENT0_IMASK_TXEMPTY_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_TXEMPTY_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_TXEMPTY_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_TXEMPTY_A { match self . bits { false => INT_EVENT0_IMASK_TXEMPTY_A :: INT_EVENT0_IMASK_TXEMPTY_CLR , true => INT_EVENT0_IMASK_TXEMPTY_A :: INT_EVENT0_IMASK_TXEMPTY_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_txempty_clr (& self) -> bool { * self == INT_EVENT0_IMASK_TXEMPTY_A :: INT_EVENT0_IMASK_TXEMPTY_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_txempty_set (& self) -> bool { * self == INT_EVENT0_IMASK_TXEMPTY_A :: INT_EVENT0_IMASK_TXEMPTY_SET } } # [doc = "Field `INT_EVENT0_IMASK_TXEMPTY` writer - Transmit FIFO Empty event mask."] pub type INT_EVENT0_IMASK_TXEMPTY_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_TXEMPTY_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_TXEMPTY_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_txempty_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_TXEMPTY_A :: INT_EVENT0_IMASK_TXEMPTY_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_txempty_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_TXEMPTY_A :: INT_EVENT0_IMASK_TXEMPTY_SET) } } # [doc = "Field `INT_EVENT0_IMASK_IDLE` reader - SPI Idle event mask."] pub type INT_EVENT0_IMASK_IDLE_R = crate :: BitReader < INT_EVENT0_IMASK_IDLE_A > ; # [doc = "SPI Idle event mask.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_IDLE_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_IDLE_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_IDLE_SET = 1 , } impl From < INT_EVENT0_IMASK_IDLE_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_IDLE_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_IDLE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_IDLE_A { match self . bits { false => INT_EVENT0_IMASK_IDLE_A :: INT_EVENT0_IMASK_IDLE_CLR , true => INT_EVENT0_IMASK_IDLE_A :: INT_EVENT0_IMASK_IDLE_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_idle_clr (& self) -> bool { * self == INT_EVENT0_IMASK_IDLE_A :: INT_EVENT0_IMASK_IDLE_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_idle_set (& self) -> bool { * self == INT_EVENT0_IMASK_IDLE_A :: INT_EVENT0_IMASK_IDLE_SET } } # [doc = "Field `INT_EVENT0_IMASK_IDLE` writer - SPI Idle event mask."] pub type INT_EVENT0_IMASK_IDLE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_IDLE_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_IDLE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_idle_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_IDLE_A :: INT_EVENT0_IMASK_IDLE_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_idle_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_IDLE_A :: INT_EVENT0_IMASK_IDLE_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DMA_DONE_RX` reader - DMA Done 1 event for RX event mask."] pub type INT_EVENT0_IMASK_DMA_DONE_RX_R = crate :: BitReader < INT_EVENT0_IMASK_DMA_DONE_RX_A > ; # [doc = "DMA Done 1 event for RX event mask.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DMA_DONE_RX_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DMA_DONE_RX_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DMA_DONE_RX_SET = 1 , } impl From < INT_EVENT0_IMASK_DMA_DONE_RX_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DMA_DONE_RX_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DMA_DONE_RX_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DMA_DONE_RX_A { match self . bits { false => INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_CLR , true => INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dma_done_rx_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dma_done_rx_set (& self) -> bool { * self == INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_SET } } # [doc = "Field `INT_EVENT0_IMASK_DMA_DONE_RX` writer - DMA Done 1 event for RX event mask."] pub type INT_EVENT0_IMASK_DMA_DONE_RX_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DMA_DONE_RX_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DMA_DONE_RX_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dma_done_rx_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dma_done_rx_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DMA_DONE_TX` reader - DMA Done 1 event for TX event mask."] pub type INT_EVENT0_IMASK_DMA_DONE_TX_R = crate :: BitReader < INT_EVENT0_IMASK_DMA_DONE_TX_A > ; # [doc = "DMA Done 1 event for TX event mask.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DMA_DONE_TX_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DMA_DONE_TX_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DMA_DONE_TX_SET = 1 , } impl From < INT_EVENT0_IMASK_DMA_DONE_TX_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DMA_DONE_TX_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DMA_DONE_TX_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DMA_DONE_TX_A { match self . bits { false => INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_CLR , true => INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dma_done_tx_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dma_done_tx_set (& self) -> bool { * self == INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_SET } } # [doc = "Field `INT_EVENT0_IMASK_DMA_DONE_TX` writer - DMA Done 1 event for TX event mask."] pub type INT_EVENT0_IMASK_DMA_DONE_TX_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DMA_DONE_TX_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DMA_DONE_TX_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dma_done_tx_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dma_done_tx_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_SET) } } # [doc = "Field `INT_EVENT0_IMASK_TXFIFO_UNF` reader - TX FIFO underflow interrupt mask"] pub type INT_EVENT0_IMASK_TXFIFO_UNF_R = crate :: BitReader < INT_EVENT0_IMASK_TXFIFO_UNF_A > ; # [doc = "TX FIFO underflow interrupt mask\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_TXFIFO_UNF_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_TXFIFO_UNF_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_TXFIFO_UNF_SET = 1 , } impl From < INT_EVENT0_IMASK_TXFIFO_UNF_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_TXFIFO_UNF_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_TXFIFO_UNF_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_TXFIFO_UNF_A { match self . bits { false => INT_EVENT0_IMASK_TXFIFO_UNF_A :: INT_EVENT0_IMASK_TXFIFO_UNF_CLR , true => INT_EVENT0_IMASK_TXFIFO_UNF_A :: INT_EVENT0_IMASK_TXFIFO_UNF_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_txfifo_unf_clr (& self) -> bool { * self == INT_EVENT0_IMASK_TXFIFO_UNF_A :: INT_EVENT0_IMASK_TXFIFO_UNF_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_txfifo_unf_set (& self) -> bool { * self == INT_EVENT0_IMASK_TXFIFO_UNF_A :: INT_EVENT0_IMASK_TXFIFO_UNF_SET } } # [doc = "Field `INT_EVENT0_IMASK_TXFIFO_UNF` writer - TX FIFO underflow interrupt mask"] pub type INT_EVENT0_IMASK_TXFIFO_UNF_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_TXFIFO_UNF_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_TXFIFO_UNF_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_txfifo_unf_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_TXFIFO_UNF_A :: INT_EVENT0_IMASK_TXFIFO_UNF_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_txfifo_unf_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_TXFIFO_UNF_A :: INT_EVENT0_IMASK_TXFIFO_UNF_SET) } } # [doc = "Field `INT_EVENT0_IMASK_RXFULL` reader - RX FIFO Full Interrupt Mask"] pub type INT_EVENT0_IMASK_RXFULL_R = crate :: BitReader < INT_EVENT0_IMASK_RXFULL_A > ; # [doc = "RX FIFO Full Interrupt Mask\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_RXFULL_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_RXFULL_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_RXFULL_SET = 1 , } impl From < INT_EVENT0_IMASK_RXFULL_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_RXFULL_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_RXFULL_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_RXFULL_A { match self . bits { false => INT_EVENT0_IMASK_RXFULL_A :: INT_EVENT0_IMASK_RXFULL_CLR , true => INT_EVENT0_IMASK_RXFULL_A :: INT_EVENT0_IMASK_RXFULL_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_rxfull_clr (& self) -> bool { * self == INT_EVENT0_IMASK_RXFULL_A :: INT_EVENT0_IMASK_RXFULL_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_rxfull_set (& self) -> bool { * self == INT_EVENT0_IMASK_RXFULL_A :: INT_EVENT0_IMASK_RXFULL_SET } } # [doc = "Field `INT_EVENT0_IMASK_RXFULL` writer - RX FIFO Full Interrupt Mask"] pub type INT_EVENT0_IMASK_RXFULL_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_RXFULL_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_RXFULL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_rxfull_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXFULL_A :: INT_EVENT0_IMASK_RXFULL_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_rxfull_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXFULL_A :: INT_EVENT0_IMASK_RXFULL_SET) } } impl R { # [doc = "Bit 0 - RXFIFO overflow event mask."] # [inline (always)] pub fn int_event0_imask_rxfifo_ovf (& self) -> INT_EVENT0_IMASK_RXFIFO_OVF_R { INT_EVENT0_IMASK_RXFIFO_OVF_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - Parity error event mask."] # [inline (always)] pub fn int_event0_imask_per (& self) -> INT_EVENT0_IMASK_PER_R { INT_EVENT0_IMASK_PER_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - Enable SPI Receive Time-Out event mask."] # [inline (always)] pub fn int_event0_imask_rtout (& self) -> INT_EVENT0_IMASK_RTOUT_R { INT_EVENT0_IMASK_RTOUT_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - Receive FIFO event.This interrupt is set if the selected Receive FIFO level has been reached"] # [inline (always)] pub fn int_event0_imask_rx (& self) -> INT_EVENT0_IMASK_RX_R { INT_EVENT0_IMASK_RX_R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - Transmit FIFO event mask."] # [inline (always)] pub fn int_event0_imask_tx (& self) -> INT_EVENT0_IMASK_TX_R { INT_EVENT0_IMASK_TX_R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - Transmit FIFO Empty event mask."] # [inline (always)] pub fn int_event0_imask_txempty (& self) -> INT_EVENT0_IMASK_TXEMPTY_R { INT_EVENT0_IMASK_TXEMPTY_R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - SPI Idle event mask."] # [inline (always)] pub fn int_event0_imask_idle (& self) -> INT_EVENT0_IMASK_IDLE_R { INT_EVENT0_IMASK_IDLE_R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - DMA Done 1 event for RX event mask."] # [inline (always)] pub fn int_event0_imask_dma_done_rx (& self) -> INT_EVENT0_IMASK_DMA_DONE_RX_R { INT_EVENT0_IMASK_DMA_DONE_RX_R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - DMA Done 1 event for TX event mask."] # [inline (always)] pub fn int_event0_imask_dma_done_tx (& self) -> INT_EVENT0_IMASK_DMA_DONE_TX_R { INT_EVENT0_IMASK_DMA_DONE_TX_R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - TX FIFO underflow interrupt mask"] # [inline (always)] pub fn int_event0_imask_txfifo_unf (& self) -> INT_EVENT0_IMASK_TXFIFO_UNF_R { INT_EVENT0_IMASK_TXFIFO_UNF_R :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - RX FIFO Full Interrupt Mask"] # [inline (always)] pub fn int_event0_imask_rxfull (& self) -> INT_EVENT0_IMASK_RXFULL_R { INT_EVENT0_IMASK_RXFULL_R :: new (((self . bits >> 10) & 1) != 0) } } impl W { # [doc = "Bit 0 - RXFIFO overflow event mask."] # [inline (always)] # [must_use] pub fn int_event0_imask_rxfifo_ovf (& mut self) -> INT_EVENT0_IMASK_RXFIFO_OVF_W < INT_EVENT0_IMASK_SPEC , 0 > { INT_EVENT0_IMASK_RXFIFO_OVF_W :: new (self) } # [doc = "Bit 1 - Parity error event mask."] # [inline (always)] # [must_use] pub fn int_event0_imask_per (& mut self) -> INT_EVENT0_IMASK_PER_W < INT_EVENT0_IMASK_SPEC , 1 > { INT_EVENT0_IMASK_PER_W :: new (self) } # [doc = "Bit 2 - Enable SPI Receive Time-Out event mask."] # [inline (always)] # [must_use] pub fn int_event0_imask_rtout (& mut self) -> INT_EVENT0_IMASK_RTOUT_W < INT_EVENT0_IMASK_SPEC , 2 > { INT_EVENT0_IMASK_RTOUT_W :: new (self) } # [doc = "Bit 3 - Receive FIFO event.This interrupt is set if the selected Receive FIFO level has been reached"] # [inline (always)] # [must_use] pub fn int_event0_imask_rx (& mut self) -> INT_EVENT0_IMASK_RX_W <'_, INT_EVENT0_IMASK_SPEC , 3 > { INT_EVENT0_IMASK_RX_W :: new (self) } # [doc = "Bit 4 - Transmit FIFO event mask."] # [inline (always)] # [must_use] pub fn int_event0_imask_tx (& mut self) -> INT_EVENT0_IMASK_TX_W < INT_EVENT0_IMASK_SPEC , 4 > { INT_EVENT0_IMASK_TX_W :: new (self) } # [doc = "Bit 5 - Transmit FIFO Empty event mask."] # [inline (always)] # [must_use] pub fn int_event0_imask_txempty (& mut self) -> INT_EVENT0_IMASK_TXEMPTY_W < INT_EVENT0_IMASK_SPEC , 5 > { INT_EVENT0_IMASK_TXEMPTY_W :: new (self) } # [doc = "Bit 6 - SPI Idle event mask."] # [inline (always)] # [must_use] pub fn int_event0_imask_idle (& mut self) -> INT_EVENT0_IMASK_IDLE_W < INT_EVENT0_IMASK_SPEC , 6 > { INT_EVENT0_IMASK_IDLE_W :: new (self) } # [doc = "Bit 7 - DMA Done 1 event for RX event mask."] # [inline (always)] # [must_use] pub fn int_event0_imask_dma_done_rx (& mut self) -> INT_EVENT0_IMASK_DMA_DONE_RX_W < INT_EVENT0_IMASK_SPEC , 7 > { INT_EVENT0_IMASK_DMA_DONE_RX_W :: new (self) } # [doc = "Bit 8 - DMA Done 1 event for TX event mask."] # [inline (always)] # [must_use] pub fn int_event0_imask_dma_done_tx (& mut self) -> INT_EVENT0_IMASK_DMA_DONE_TX_W < INT_EVENT0_IMASK_SPEC , 8 > { INT_EVENT0_IMASK_DMA_DONE_TX_W :: new (self) } # [doc = "Bit 9 - TX FIFO underflow interrupt mask"] # [inline (always)] # [must_use] pub fn int_event0_imask_txfifo_unf (& mut self) -> INT_EVENT0_IMASK_TXFIFO_UNF_W < INT_EVENT0_IMASK_SPEC , 9 > { INT_EVENT0_IMASK_TXFIFO_UNF_W :: new (self) } # [doc = "Bit 10 - RX FIFO Full Interrupt Mask"] # [inline (always)] # [must_use] pub fn int_event0_imask_rxfull (& mut self) -> INT_EVENT0_IMASK_RXFULL_W < INT_EVENT0_IMASK_SPEC , 10 > { INT_EVENT0_IMASK_RXFULL_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Interrupt mask\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_event0_imask::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_event0_imask::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct INT_EVENT0_IMASK_SPEC ; impl crate :: RegisterSpec for INT_EVENT0_IMASK_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`int_event0_imask::R`](R) reader structure"] impl crate :: Readable for INT_EVENT0_IMASK_SPEC { } # [doc = "`write(|w| ..)` method takes [`int_event0_imask::W`](W) writer structure"] impl crate :: Writable for INT_EVENT0_IMASK_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets INT_EVENT0_IMASK to value 0"] impl crate :: Resettable for INT_EVENT0_IMASK_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/i2c1/mctr.rs:1:13254 [INFO] [stdout] | [INFO] [stdout] 1 | ... fn mctr_rd_on_txempty (& mut self) -> MCTR_RD_ON_TXEMPTY_W < MCTR_SPEC , 5 > { MCTR_RD_ON_TXEMPTY_W :: new (self) } # [doc = "Bits 16... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `MCTR` reader"] pub type R = crate :: R < MCTR_SPEC > ; # [doc = "Register `MCTR` writer"] pub type W = crate :: W < MCTR_SPEC > ; # [doc = "Field `MCTR_BURSTRUN` reader - I2C Master Enable and start transaction"] pub type MCTR_BURSTRUN_R = crate :: BitReader < MCTR_BURSTRUN_A > ; # [doc = "I2C Master Enable and start transaction\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum MCTR_BURSTRUN_A { # [doc = "0: DISABLE"] MCTR_BURSTRUN_DISABLE = 0 , # [doc = "1: ENABLE"] MCTR_BURSTRUN_ENABLE = 1 , } impl From < MCTR_BURSTRUN_A > for bool { # [inline (always)] fn from (variant : MCTR_BURSTRUN_A) -> Self { variant as u8 != 0 } } impl MCTR_BURSTRUN_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> MCTR_BURSTRUN_A { match self . bits { false => MCTR_BURSTRUN_A :: MCTR_BURSTRUN_DISABLE , true => MCTR_BURSTRUN_A :: MCTR_BURSTRUN_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_mctr_burstrun_disable (& self) -> bool { * self == MCTR_BURSTRUN_A :: MCTR_BURSTRUN_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_mctr_burstrun_enable (& self) -> bool { * self == MCTR_BURSTRUN_A :: MCTR_BURSTRUN_ENABLE } } # [doc = "Field `MCTR_BURSTRUN` writer - I2C Master Enable and start transaction"] pub type MCTR_BURSTRUN_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , MCTR_BURSTRUN_A > ; impl < 'a , REG , const O : u8 > MCTR_BURSTRUN_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn mctr_burstrun_disable (self) -> & 'a mut crate :: W < REG > { self . variant (MCTR_BURSTRUN_A :: MCTR_BURSTRUN_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn mctr_burstrun_enable (self) -> & 'a mut crate :: W < REG > { self . variant (MCTR_BURSTRUN_A :: MCTR_BURSTRUN_ENABLE) } } # [doc = "Field `MCTR_START` reader - Generate START"] pub type MCTR_START_R = crate :: BitReader < MCTR_START_A > ; # [doc = "Generate START\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum MCTR_START_A { # [doc = "0: DISABLE"] MCTR_START_DISABLE = 0 , # [doc = "1: ENABLE"] MCTR_START_ENABLE = 1 , } impl From < MCTR_START_A > for bool { # [inline (always)] fn from (variant : MCTR_START_A) -> Self { variant as u8 != 0 } } impl MCTR_START_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> MCTR_START_A { match self . bits { false => MCTR_START_A :: MCTR_START_DISABLE , true => MCTR_START_A :: MCTR_START_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_mctr_start_disable (& self) -> bool { * self == MCTR_START_A :: MCTR_START_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_mctr_start_enable (& self) -> bool { * self == MCTR_START_A :: MCTR_START_ENABLE } } # [doc = "Field `MCTR_START` writer - Generate START"] pub type MCTR_START_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , MCTR_START_A > ; impl < 'a , REG , const O : u8 > MCTR_START_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn mctr_start_disable (self) -> & 'a mut crate :: W < REG > { self . variant (MCTR_START_A :: MCTR_START_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn mctr_start_enable (self) -> & 'a mut crate :: W < REG > { self . variant (MCTR_START_A :: MCTR_START_ENABLE) } } # [doc = "Field `MCTR_STOP` reader - Generate STOP"] pub type MCTR_STOP_R = crate :: BitReader < MCTR_STOP_A > ; # [doc = "Generate STOP\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum MCTR_STOP_A { # [doc = "0: DISABLE"] MCTR_STOP_DISABLE = 0 , # [doc = "1: ENABLE"] MCTR_STOP_ENABLE = 1 , } impl From < MCTR_STOP_A > for bool { # [inline (always)] fn from (variant : MCTR_STOP_A) -> Self { variant as u8 != 0 } } impl MCTR_STOP_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> MCTR_STOP_A { match self . bits { false => MCTR_STOP_A :: MCTR_STOP_DISABLE , true => MCTR_STOP_A :: MCTR_STOP_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_mctr_stop_disable (& self) -> bool { * self == MCTR_STOP_A :: MCTR_STOP_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_mctr_stop_enable (& self) -> bool { * self == MCTR_STOP_A :: MCTR_STOP_ENABLE } } # [doc = "Field `MCTR_STOP` writer - Generate STOP"] pub type MCTR_STOP_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , MCTR_STOP_A > ; impl < 'a , REG , const O : u8 > MCTR_STOP_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn mctr_stop_disable (self) -> & 'a mut crate :: W < REG > { self . variant (MCTR_STOP_A :: MCTR_STOP_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn mctr_stop_enable (self) -> & 'a mut crate :: W < REG > { self . variant (MCTR_STOP_A :: MCTR_STOP_ENABLE) } } # [doc = "Field `MCTR_ACK` reader - Data Acknowledge Enable. Software needs to configure this bit to send the ACK or NACK. See field decoding in Table: MCTR Field decoding."] pub type MCTR_ACK_R = crate :: BitReader < MCTR_ACK_A > ; # [doc = "Data Acknowledge Enable. Software needs to configure this bit to send the ACK or NACK. See field decoding in Table: MCTR Field decoding.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum MCTR_ACK_A { # [doc = "0: DISABLE"] MCTR_ACK_DISABLE = 0 , # [doc = "1: ENABLE"] MCTR_ACK_ENABLE = 1 , } impl From < MCTR_ACK_A > for bool { # [inline (always)] fn from (variant : MCTR_ACK_A) -> Self { variant as u8 != 0 } } impl MCTR_ACK_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> MCTR_ACK_A { match self . bits { false => MCTR_ACK_A :: MCTR_ACK_DISABLE , true => MCTR_ACK_A :: MCTR_ACK_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_mctr_ack_disable (& self) -> bool { * self == MCTR_ACK_A :: MCTR_ACK_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_mctr_ack_enable (& self) -> bool { * self == MCTR_ACK_A :: MCTR_ACK_ENABLE } } # [doc = "Field `MCTR_ACK` writer - Data Acknowledge Enable. Software needs to configure this bit to send the ACK or NACK. See field decoding in Table: MCTR Field decoding."] pub type MCTR_ACK_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , MCTR_ACK_A > ; impl < 'a , REG , const O : u8 > MCTR_ACK_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn mctr_ack_disable (self) -> & 'a mut crate :: W < REG > { self . variant (MCTR_ACK_A :: MCTR_ACK_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn mctr_ack_enable (self) -> & 'a mut crate :: W < REG > { self . variant (MCTR_ACK_A :: MCTR_ACK_ENABLE) } } # [doc = "Field `MCTR_MACKOEN` reader - Master ACK overrride Enable"] pub type MCTR_MACKOEN_R = crate :: BitReader < MCTR_MACKOEN_A > ; # [doc = "Master ACK overrride Enable\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum MCTR_MACKOEN_A { # [doc = "0: DISABLE"] MCTR_MACKOEN_DISABLE = 0 , # [doc = "1: ENABLE"] MCTR_MACKOEN_ENABLE = 1 , } impl From < MCTR_MACKOEN_A > for bool { # [inline (always)] fn from (variant : MCTR_MACKOEN_A) -> Self { variant as u8 != 0 } } impl MCTR_MACKOEN_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> MCTR_MACKOEN_A { match self . bits { false => MCTR_MACKOEN_A :: MCTR_MACKOEN_DISABLE , true => MCTR_MACKOEN_A :: MCTR_MACKOEN_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_mctr_mackoen_disable (& self) -> bool { * self == MCTR_MACKOEN_A :: MCTR_MACKOEN_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_mctr_mackoen_enable (& self) -> bool { * self == MCTR_MACKOEN_A :: MCTR_MACKOEN_ENABLE } } # [doc = "Field `MCTR_MACKOEN` writer - Master ACK overrride Enable"] pub type MCTR_MACKOEN_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , MCTR_MACKOEN_A > ; impl < 'a , REG , const O : u8 > MCTR_MACKOEN_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn mctr_mackoen_disable (self) -> & 'a mut crate :: W < REG > { self . variant (MCTR_MACKOEN_A :: MCTR_MACKOEN_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn mctr_mackoen_enable (self) -> & 'a mut crate :: W < REG > { self . variant (MCTR_MACKOEN_A :: MCTR_MACKOEN_ENABLE) } } # [doc = "Field `MCTR_RD_ON_TXEMPTY` reader - Read on TX Empty"] pub type MCTR_RD_ON_TXEMPTY_R = crate :: BitReader < MCTR_RD_ON_TXEMPTY_A > ; # [doc = "Read on TX Empty\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum MCTR_RD_ON_TXEMPTY_A { # [doc = "0: DISABLE"] MCTR_RD_ON_TXEMPTY_DISABLE = 0 , # [doc = "1: ENABLE"] MCTR_RD_ON_TXEMPTY_ENABLE = 1 , } impl From < MCTR_RD_ON_TXEMPTY_A > for bool { # [inline (always)] fn from (variant : MCTR_RD_ON_TXEMPTY_A) -> Self { variant as u8 != 0 } } impl MCTR_RD_ON_TXEMPTY_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> MCTR_RD_ON_TXEMPTY_A { match self . bits { false => MCTR_RD_ON_TXEMPTY_A :: MCTR_RD_ON_TXEMPTY_DISABLE , true => MCTR_RD_ON_TXEMPTY_A :: MCTR_RD_ON_TXEMPTY_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_mctr_rd_on_txempty_disable (& self) -> bool { * self == MCTR_RD_ON_TXEMPTY_A :: MCTR_RD_ON_TXEMPTY_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_mctr_rd_on_txempty_enable (& self) -> bool { * self == MCTR_RD_ON_TXEMPTY_A :: MCTR_RD_ON_TXEMPTY_ENABLE } } # [doc = "Field `MCTR_RD_ON_TXEMPTY` writer - Read on TX Empty"] pub type MCTR_RD_ON_TXEMPTY_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , MCTR_RD_ON_TXEMPTY_A > ; impl < 'a , REG , const O : u8 > MCTR_RD_ON_TXEMPTY_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn mctr_rd_on_txempty_disable (self) -> & 'a mut crate :: W < REG > { self . variant (MCTR_RD_ON_TXEMPTY_A :: MCTR_RD_ON_TXEMPTY_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn mctr_rd_on_txempty_enable (self) -> & 'a mut crate :: W < REG > { self . variant (MCTR_RD_ON_TXEMPTY_A :: MCTR_RD_ON_TXEMPTY_ENABLE) } } # [doc = "Field `MCTR_MBLEN` reader - I2C transaction length This field contains the programmed length of bytes of the Transaction."] pub type MCTR_MBLEN_R = crate :: FieldReader < u16 > ; # [doc = "Field `MCTR_MBLEN` writer - I2C transaction length This field contains the programmed length of bytes of the Transaction."] pub type MCTR_MBLEN_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 12 , O , u16 > ; impl R { # [doc = "Bit 0 - I2C Master Enable and start transaction"] # [inline (always)] pub fn mctr_burstrun (& self) -> MCTR_BURSTRUN_R { MCTR_BURSTRUN_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - Generate START"] # [inline (always)] pub fn mctr_start (& self) -> MCTR_START_R { MCTR_START_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - Generate STOP"] # [inline (always)] pub fn mctr_stop (& self) -> MCTR_STOP_R { MCTR_STOP_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - Data Acknowledge Enable. Software needs to configure this bit to send the ACK or NACK. See field decoding in Table: MCTR Field decoding."] # [inline (always)] pub fn mctr_ack (& self) -> MCTR_ACK_R { MCTR_ACK_R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - Master ACK overrride Enable"] # [inline (always)] pub fn mctr_mackoen (& self) -> MCTR_MACKOEN_R { MCTR_MACKOEN_R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - Read on TX Empty"] # [inline (always)] pub fn mctr_rd_on_txempty (& self) -> MCTR_RD_ON_TXEMPTY_R { MCTR_RD_ON_TXEMPTY_R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bits 16:27 - I2C transaction length This field contains the programmed length of bytes of the Transaction."] # [inline (always)] pub fn mctr_mblen (& self) -> MCTR_MBLEN_R { MCTR_MBLEN_R :: new (((self . bits >> 16) & 0x0fff) as u16) } } impl W { # [doc = "Bit 0 - I2C Master Enable and start transaction"] # [inline (always)] # [must_use] pub fn mctr_burstrun (& mut self) -> MCTR_BURSTRUN_W < MCTR_SPEC , 0 > { MCTR_BURSTRUN_W :: new (self) } # [doc = "Bit 1 - Generate START"] # [inline (always)] # [must_use] pub fn mctr_start (& mut self) -> MCTR_START_W < MCTR_SPEC , 1 > { MCTR_START_W :: new (self) } # [doc = "Bit 2 - Generate STOP"] # [inline (always)] # [must_use] pub fn mctr_stop (& mut self) -> MCTR_STOP_W < MCTR_SPEC , 2 > { MCTR_STOP_W :: new (self) } # [doc = "Bit 3 - Data Acknowledge Enable. Software needs to configure this bit to send the ACK or NACK. See field decoding in Table: MCTR Field decoding."] # [inline (always)] # [must_use] pub fn mctr_ack (& mut self) -> MCTR_ACK_W < MCTR_SPEC , 3 > { MCTR_ACK_W :: new (self) } # [doc = "Bit 4 - Master ACK overrride Enable"] # [inline (always)] # [must_use] pub fn mctr_mackoen (& mut self) -> MCTR_MACKOEN_W < MCTR_SPEC , 4 > { MCTR_MACKOEN_W :: new (self) } # [doc = "Bit 5 - Read on TX Empty"] # [inline (always)] # [must_use] pub fn mctr_rd_on_txempty (& mut self) -> MCTR_RD_ON_TXEMPTY_W <'_, MCTR_SPEC , 5 > { MCTR_RD_ON_TXEMPTY_W :: new (self) } # [doc = "Bits 16:27 - I2C transaction length This field contains the programmed length of bytes of the Transaction."] # [inline (always)] # [must_use] pub fn mctr_mblen (& mut self) -> MCTR_MBLEN_W < MCTR_SPEC , 16 > { MCTR_MBLEN_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "I2C Master Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mctr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mctr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct MCTR_SPEC ; impl crate :: RegisterSpec for MCTR_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`mctr::R`](R) reader structure"] impl crate :: Readable for MCTR_SPEC { } # [doc = "`write(|w| ..)` method takes [`mctr::W`](W) writer structure"] impl crate :: Writable for MCTR_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets MCTR to value 0"] impl crate :: Resettable for MCTR_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/i2c0/sctr.rs:1:25758 [INFO] [stdout] | [INFO] [stdout] 1 | ...txwait_stale_txfifo (& mut self) -> SCTR_TXWAIT_STALE_TXFIFO_W < SCTR_SPEC , 5 > { SCTR_TXWAIT_STALE_TXFIFO_W :: new (self) } # [doc =... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `SCTR` reader"] pub type R = crate :: R < SCTR_SPEC > ; # [doc = "Register `SCTR` writer"] pub type W = crate :: W < SCTR_SPEC > ; # [doc = "Field `SCTR_ACTIVE` reader - Device Active. Setting this bit enables the slave functionality."] pub type SCTR_ACTIVE_R = crate :: BitReader < SCTR_ACTIVE_A > ; # [doc = "Device Active. Setting this bit enables the slave functionality.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum SCTR_ACTIVE_A { # [doc = "0: DISABLE"] SCTR_ACTIVE_DISABLE = 0 , # [doc = "1: ENABLE"] SCTR_ACTIVE_ENABLE = 1 , } impl From < SCTR_ACTIVE_A > for bool { # [inline (always)] fn from (variant : SCTR_ACTIVE_A) -> Self { variant as u8 != 0 } } impl SCTR_ACTIVE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> SCTR_ACTIVE_A { match self . bits { false => SCTR_ACTIVE_A :: SCTR_ACTIVE_DISABLE , true => SCTR_ACTIVE_A :: SCTR_ACTIVE_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_sctr_active_disable (& self) -> bool { * self == SCTR_ACTIVE_A :: SCTR_ACTIVE_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_sctr_active_enable (& self) -> bool { * self == SCTR_ACTIVE_A :: SCTR_ACTIVE_ENABLE } } # [doc = "Field `SCTR_ACTIVE` writer - Device Active. Setting this bit enables the slave functionality."] pub type SCTR_ACTIVE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , SCTR_ACTIVE_A > ; impl < 'a , REG , const O : u8 > SCTR_ACTIVE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn sctr_active_disable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_ACTIVE_A :: SCTR_ACTIVE_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn sctr_active_enable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_ACTIVE_A :: SCTR_ACTIVE_ENABLE) } } # [doc = "Field `SCTR_GENCALL` reader - General call response enable. This bit is only available in UCBxI2COA0. Modify only when UCSWRST = 1. 0b = Do not respond to a general call 1b = Respond to a general call"] pub type SCTR_GENCALL_R = crate :: BitReader < SCTR_GENCALL_A > ; # [doc = "General call response enable. This bit is only available in UCBxI2COA0. Modify only when UCSWRST = 1. 0b = Do not respond to a general call 1b = Respond to a general call\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum SCTR_GENCALL_A { # [doc = "0: DISABLE"] SCTR_GENCALL_DISABLE = 0 , # [doc = "1: ENABLE"] SCTR_GENCALL_ENABLE = 1 , } impl From < SCTR_GENCALL_A > for bool { # [inline (always)] fn from (variant : SCTR_GENCALL_A) -> Self { variant as u8 != 0 } } impl SCTR_GENCALL_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> SCTR_GENCALL_A { match self . bits { false => SCTR_GENCALL_A :: SCTR_GENCALL_DISABLE , true => SCTR_GENCALL_A :: SCTR_GENCALL_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_sctr_gencall_disable (& self) -> bool { * self == SCTR_GENCALL_A :: SCTR_GENCALL_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_sctr_gencall_enable (& self) -> bool { * self == SCTR_GENCALL_A :: SCTR_GENCALL_ENABLE } } # [doc = "Field `SCTR_GENCALL` writer - General call response enable. This bit is only available in UCBxI2COA0. Modify only when UCSWRST = 1. 0b = Do not respond to a general call 1b = Respond to a general call"] pub type SCTR_GENCALL_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , SCTR_GENCALL_A > ; impl < 'a , REG , const O : u8 > SCTR_GENCALL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn sctr_gencall_disable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_GENCALL_A :: SCTR_GENCALL_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn sctr_gencall_enable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_GENCALL_A :: SCTR_GENCALL_ENABLE) } } # [doc = "Field `SCTR_SCLKSTRETCH` reader - Slave Clock Stretch Enable"] pub type SCTR_SCLKSTRETCH_R = crate :: BitReader < SCTR_SCLKSTRETCH_A > ; # [doc = "Slave Clock Stretch Enable\n\nValue on reset: 1"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum SCTR_SCLKSTRETCH_A { # [doc = "0: DISABLE"] SCTR_SCLKSTRETCH_DISABLE = 0 , # [doc = "1: ENABLE"] SCTR_SCLKSTRETCH_ENABLE = 1 , } impl From < SCTR_SCLKSTRETCH_A > for bool { # [inline (always)] fn from (variant : SCTR_SCLKSTRETCH_A) -> Self { variant as u8 != 0 } } impl SCTR_SCLKSTRETCH_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> SCTR_SCLKSTRETCH_A { match self . bits { false => SCTR_SCLKSTRETCH_A :: SCTR_SCLKSTRETCH_DISABLE , true => SCTR_SCLKSTRETCH_A :: SCTR_SCLKSTRETCH_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_sctr_sclkstretch_disable (& self) -> bool { * self == SCTR_SCLKSTRETCH_A :: SCTR_SCLKSTRETCH_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_sctr_sclkstretch_enable (& self) -> bool { * self == SCTR_SCLKSTRETCH_A :: SCTR_SCLKSTRETCH_ENABLE } } # [doc = "Field `SCTR_SCLKSTRETCH` writer - Slave Clock Stretch Enable"] pub type SCTR_SCLKSTRETCH_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , SCTR_SCLKSTRETCH_A > ; impl < 'a , REG , const O : u8 > SCTR_SCLKSTRETCH_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn sctr_sclkstretch_disable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_SCLKSTRETCH_A :: SCTR_SCLKSTRETCH_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn sctr_sclkstretch_enable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_SCLKSTRETCH_A :: SCTR_SCLKSTRETCH_ENABLE) } } # [doc = "Field `SCTR_TXEMPTY_ON_TREQ` reader - Tx Empty Interrupt on TREQ"] pub type SCTR_TXEMPTY_ON_TREQ_R = crate :: BitReader < SCTR_TXEMPTY_ON_TREQ_A > ; # [doc = "Tx Empty Interrupt on TREQ\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum SCTR_TXEMPTY_ON_TREQ_A { # [doc = "0: DISABLE"] SCTR_TXEMPTY_ON_TREQ_DISABLE = 0 , # [doc = "1: ENABLE"] SCTR_TXEMPTY_ON_TREQ_ENABLE = 1 , } impl From < SCTR_TXEMPTY_ON_TREQ_A > for bool { # [inline (always)] fn from (variant : SCTR_TXEMPTY_ON_TREQ_A) -> Self { variant as u8 != 0 } } impl SCTR_TXEMPTY_ON_TREQ_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> SCTR_TXEMPTY_ON_TREQ_A { match self . bits { false => SCTR_TXEMPTY_ON_TREQ_A :: SCTR_TXEMPTY_ON_TREQ_DISABLE , true => SCTR_TXEMPTY_ON_TREQ_A :: SCTR_TXEMPTY_ON_TREQ_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_sctr_txempty_on_treq_disable (& self) -> bool { * self == SCTR_TXEMPTY_ON_TREQ_A :: SCTR_TXEMPTY_ON_TREQ_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_sctr_txempty_on_treq_enable (& self) -> bool { * self == SCTR_TXEMPTY_ON_TREQ_A :: SCTR_TXEMPTY_ON_TREQ_ENABLE } } # [doc = "Field `SCTR_TXEMPTY_ON_TREQ` writer - Tx Empty Interrupt on TREQ"] pub type SCTR_TXEMPTY_ON_TREQ_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , SCTR_TXEMPTY_ON_TREQ_A > ; impl < 'a , REG , const O : u8 > SCTR_TXEMPTY_ON_TREQ_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn sctr_txempty_on_treq_disable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_TXEMPTY_ON_TREQ_A :: SCTR_TXEMPTY_ON_TREQ_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn sctr_txempty_on_treq_enable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_TXEMPTY_ON_TREQ_A :: SCTR_TXEMPTY_ON_TREQ_ENABLE) } } # [doc = "Field `SCTR_TXTRIG_TXMODE` reader - Tx Trigger when slave FSM is in Tx Mode"] pub type SCTR_TXTRIG_TXMODE_R = crate :: BitReader < SCTR_TXTRIG_TXMODE_A > ; # [doc = "Tx Trigger when slave FSM is in Tx Mode\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum SCTR_TXTRIG_TXMODE_A { # [doc = "0: DISABLE"] SCTR_TXTRIG_TXMODE_DISABLE = 0 , # [doc = "1: ENABLE"] SCTR_TXTRIG_TXMODE_ENABLE = 1 , } impl From < SCTR_TXTRIG_TXMODE_A > for bool { # [inline (always)] fn from (variant : SCTR_TXTRIG_TXMODE_A) -> Self { variant as u8 != 0 } } impl SCTR_TXTRIG_TXMODE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> SCTR_TXTRIG_TXMODE_A { match self . bits { false => SCTR_TXTRIG_TXMODE_A :: SCTR_TXTRIG_TXMODE_DISABLE , true => SCTR_TXTRIG_TXMODE_A :: SCTR_TXTRIG_TXMODE_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_sctr_txtrig_txmode_disable (& self) -> bool { * self == SCTR_TXTRIG_TXMODE_A :: SCTR_TXTRIG_TXMODE_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_sctr_txtrig_txmode_enable (& self) -> bool { * self == SCTR_TXTRIG_TXMODE_A :: SCTR_TXTRIG_TXMODE_ENABLE } } # [doc = "Field `SCTR_TXTRIG_TXMODE` writer - Tx Trigger when slave FSM is in Tx Mode"] pub type SCTR_TXTRIG_TXMODE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , SCTR_TXTRIG_TXMODE_A > ; impl < 'a , REG , const O : u8 > SCTR_TXTRIG_TXMODE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn sctr_txtrig_txmode_disable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_TXTRIG_TXMODE_A :: SCTR_TXTRIG_TXMODE_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn sctr_txtrig_txmode_enable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_TXTRIG_TXMODE_A :: SCTR_TXTRIG_TXMODE_ENABLE) } } # [doc = "Field `SCTR_TXWAIT_STALE_TXFIFO` reader - Tx transfer waits when stale data in Tx FIFO. This prevents stale bytes left in the TX FIFO from automatically being sent on the next I2C packet. Note: this should be used with TXEMPTY_ON_TREQ set to prevent the Slave State Machine from waiting for TX FIFO data without an interrupt notification when the FIFO data is stale."] pub type SCTR_TXWAIT_STALE_TXFIFO_R = crate :: BitReader < SCTR_TXWAIT_STALE_TXFIFO_A > ; # [doc = "Tx transfer waits when stale data in Tx FIFO. This prevents stale bytes left in the TX FIFO from automatically being sent on the next I2C packet. Note: this should be used with TXEMPTY_ON_TREQ set to prevent the Slave State Machine from waiting for TX FIFO data without an interrupt notification when the FIFO data is stale.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum SCTR_TXWAIT_STALE_TXFIFO_A { # [doc = "0: DISABLE"] SCTR_TXWAIT_STALE_TXFIFO_DISABLE = 0 , # [doc = "1: ENABLE"] SCTR_TXWAIT_STALE_TXFIFO_ENABLE = 1 , } impl From < SCTR_TXWAIT_STALE_TXFIFO_A > for bool { # [inline (always)] fn from (variant : SCTR_TXWAIT_STALE_TXFIFO_A) -> Self { variant as u8 != 0 } } impl SCTR_TXWAIT_STALE_TXFIFO_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> SCTR_TXWAIT_STALE_TXFIFO_A { match self . bits { false => SCTR_TXWAIT_STALE_TXFIFO_A :: SCTR_TXWAIT_STALE_TXFIFO_DISABLE , true => SCTR_TXWAIT_STALE_TXFIFO_A :: SCTR_TXWAIT_STALE_TXFIFO_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_sctr_txwait_stale_txfifo_disable (& self) -> bool { * self == SCTR_TXWAIT_STALE_TXFIFO_A :: SCTR_TXWAIT_STALE_TXFIFO_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_sctr_txwait_stale_txfifo_enable (& self) -> bool { * self == SCTR_TXWAIT_STALE_TXFIFO_A :: SCTR_TXWAIT_STALE_TXFIFO_ENABLE } } # [doc = "Field `SCTR_TXWAIT_STALE_TXFIFO` writer - Tx transfer waits when stale data in Tx FIFO. This prevents stale bytes left in the TX FIFO from automatically being sent on the next I2C packet. Note: this should be used with TXEMPTY_ON_TREQ set to prevent the Slave State Machine from waiting for TX FIFO data without an interrupt notification when the FIFO data is stale."] pub type SCTR_TXWAIT_STALE_TXFIFO_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , SCTR_TXWAIT_STALE_TXFIFO_A > ; impl < 'a , REG , const O : u8 > SCTR_TXWAIT_STALE_TXFIFO_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn sctr_txwait_stale_txfifo_disable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_TXWAIT_STALE_TXFIFO_A :: SCTR_TXWAIT_STALE_TXFIFO_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn sctr_txwait_stale_txfifo_enable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_TXWAIT_STALE_TXFIFO_A :: SCTR_TXWAIT_STALE_TXFIFO_ENABLE) } } # [doc = "Field `SCTR_RXFULL_ON_RREQ` reader - Rx full interrupt generated on RREQ condition as indicated in SSR"] pub type SCTR_RXFULL_ON_RREQ_R = crate :: BitReader < SCTR_RXFULL_ON_RREQ_A > ; # [doc = "Rx full interrupt generated on RREQ condition as indicated in SSR\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum SCTR_RXFULL_ON_RREQ_A { # [doc = "0: DISABLE"] SCTR_RXFULL_ON_RREQ_DISABLE = 0 , # [doc = "1: ENABLE"] SCTR_RXFULL_ON_RREQ_ENABLE = 1 , } impl From < SCTR_RXFULL_ON_RREQ_A > for bool { # [inline (always)] fn from (variant : SCTR_RXFULL_ON_RREQ_A) -> Self { variant as u8 != 0 } } impl SCTR_RXFULL_ON_RREQ_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> SCTR_RXFULL_ON_RREQ_A { match self . bits { false => SCTR_RXFULL_ON_RREQ_A :: SCTR_RXFULL_ON_RREQ_DISABLE , true => SCTR_RXFULL_ON_RREQ_A :: SCTR_RXFULL_ON_RREQ_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_sctr_rxfull_on_rreq_disable (& self) -> bool { * self == SCTR_RXFULL_ON_RREQ_A :: SCTR_RXFULL_ON_RREQ_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_sctr_rxfull_on_rreq_enable (& self) -> bool { * self == SCTR_RXFULL_ON_RREQ_A :: SCTR_RXFULL_ON_RREQ_ENABLE } } # [doc = "Field `SCTR_RXFULL_ON_RREQ` writer - Rx full interrupt generated on RREQ condition as indicated in SSR"] pub type SCTR_RXFULL_ON_RREQ_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , SCTR_RXFULL_ON_RREQ_A > ; impl < 'a , REG , const O : u8 > SCTR_RXFULL_ON_RREQ_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn sctr_rxfull_on_rreq_disable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_RXFULL_ON_RREQ_A :: SCTR_RXFULL_ON_RREQ_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn sctr_rxfull_on_rreq_enable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_RXFULL_ON_RREQ_A :: SCTR_RXFULL_ON_RREQ_ENABLE) } } # [doc = "Field `SCTR_EN_DEFHOSTADR` reader - Enable Default Host Address"] pub type SCTR_EN_DEFHOSTADR_R = crate :: BitReader < SCTR_EN_DEFHOSTADR_A > ; # [doc = "Enable Default Host Address\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum SCTR_EN_DEFHOSTADR_A { # [doc = "0: DISABLE"] SCTR_EN_DEFHOSTADR_DISABLE = 0 , # [doc = "1: ENABLE"] SCTR_EN_DEFHOSTADR_ENABLE = 1 , } impl From < SCTR_EN_DEFHOSTADR_A > for bool { # [inline (always)] fn from (variant : SCTR_EN_DEFHOSTADR_A) -> Self { variant as u8 != 0 } } impl SCTR_EN_DEFHOSTADR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> SCTR_EN_DEFHOSTADR_A { match self . bits { false => SCTR_EN_DEFHOSTADR_A :: SCTR_EN_DEFHOSTADR_DISABLE , true => SCTR_EN_DEFHOSTADR_A :: SCTR_EN_DEFHOSTADR_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_sctr_en_defhostadr_disable (& self) -> bool { * self == SCTR_EN_DEFHOSTADR_A :: SCTR_EN_DEFHOSTADR_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_sctr_en_defhostadr_enable (& self) -> bool { * self == SCTR_EN_DEFHOSTADR_A :: SCTR_EN_DEFHOSTADR_ENABLE } } # [doc = "Field `SCTR_EN_DEFHOSTADR` writer - Enable Default Host Address"] pub type SCTR_EN_DEFHOSTADR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , SCTR_EN_DEFHOSTADR_A > ; impl < 'a , REG , const O : u8 > SCTR_EN_DEFHOSTADR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn sctr_en_defhostadr_disable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_EN_DEFHOSTADR_A :: SCTR_EN_DEFHOSTADR_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn sctr_en_defhostadr_enable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_EN_DEFHOSTADR_A :: SCTR_EN_DEFHOSTADR_ENABLE) } } # [doc = "Field `SCTR_EN_ALRESPADR` reader - Enable Alert Response Address"] pub type SCTR_EN_ALRESPADR_R = crate :: BitReader < SCTR_EN_ALRESPADR_A > ; # [doc = "Enable Alert Response Address\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum SCTR_EN_ALRESPADR_A { # [doc = "0: DISABLE"] SCTR_EN_ALRESPADR_DISABLE = 0 , # [doc = "1: ENABLE"] SCTR_EN_ALRESPADR_ENABLE = 1 , } impl From < SCTR_EN_ALRESPADR_A > for bool { # [inline (always)] fn from (variant : SCTR_EN_ALRESPADR_A) -> Self { variant as u8 != 0 } } impl SCTR_EN_ALRESPADR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> SCTR_EN_ALRESPADR_A { match self . bits { false => SCTR_EN_ALRESPADR_A :: SCTR_EN_ALRESPADR_DISABLE , true => SCTR_EN_ALRESPADR_A :: SCTR_EN_ALRESPADR_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_sctr_en_alrespadr_disable (& self) -> bool { * self == SCTR_EN_ALRESPADR_A :: SCTR_EN_ALRESPADR_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_sctr_en_alrespadr_enable (& self) -> bool { * self == SCTR_EN_ALRESPADR_A :: SCTR_EN_ALRESPADR_ENABLE } } # [doc = "Field `SCTR_EN_ALRESPADR` writer - Enable Alert Response Address"] pub type SCTR_EN_ALRESPADR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , SCTR_EN_ALRESPADR_A > ; impl < 'a , REG , const O : u8 > SCTR_EN_ALRESPADR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn sctr_en_alrespadr_disable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_EN_ALRESPADR_A :: SCTR_EN_ALRESPADR_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn sctr_en_alrespadr_enable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_EN_ALRESPADR_A :: SCTR_EN_ALRESPADR_ENABLE) } } # [doc = "Field `SCTR_EN_DEFDEVADR` reader - Enable Deault device address"] pub type SCTR_EN_DEFDEVADR_R = crate :: BitReader < SCTR_EN_DEFDEVADR_A > ; # [doc = "Enable Deault device address\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum SCTR_EN_DEFDEVADR_A { # [doc = "0: DISABLE"] SCTR_EN_DEFDEVADR_DISABLE = 0 , # [doc = "1: ENABLE"] SCTR_EN_DEFDEVADR_ENABLE = 1 , } impl From < SCTR_EN_DEFDEVADR_A > for bool { # [inline (always)] fn from (variant : SCTR_EN_DEFDEVADR_A) -> Self { variant as u8 != 0 } } impl SCTR_EN_DEFDEVADR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> SCTR_EN_DEFDEVADR_A { match self . bits { false => SCTR_EN_DEFDEVADR_A :: SCTR_EN_DEFDEVADR_DISABLE , true => SCTR_EN_DEFDEVADR_A :: SCTR_EN_DEFDEVADR_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_sctr_en_defdevadr_disable (& self) -> bool { * self == SCTR_EN_DEFDEVADR_A :: SCTR_EN_DEFDEVADR_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_sctr_en_defdevadr_enable (& self) -> bool { * self == SCTR_EN_DEFDEVADR_A :: SCTR_EN_DEFDEVADR_ENABLE } } # [doc = "Field `SCTR_EN_DEFDEVADR` writer - Enable Deault device address"] pub type SCTR_EN_DEFDEVADR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , SCTR_EN_DEFDEVADR_A > ; impl < 'a , REG , const O : u8 > SCTR_EN_DEFDEVADR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn sctr_en_defdevadr_disable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_EN_DEFDEVADR_A :: SCTR_EN_DEFDEVADR_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn sctr_en_defdevadr_enable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_EN_DEFDEVADR_A :: SCTR_EN_DEFDEVADR_ENABLE) } } # [doc = "Field `SCTR_SWUEN` reader - Slave Wakeup Enable"] pub type SCTR_SWUEN_R = crate :: BitReader < SCTR_SWUEN_A > ; # [doc = "Slave Wakeup Enable\n\nValue on reset: 1"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum SCTR_SWUEN_A { # [doc = "0: DISABLE"] SCTR_SWUEN_DISABLE = 0 , # [doc = "1: ENABLE"] SCTR_SWUEN_ENABLE = 1 , } impl From < SCTR_SWUEN_A > for bool { # [inline (always)] fn from (variant : SCTR_SWUEN_A) -> Self { variant as u8 != 0 } } impl SCTR_SWUEN_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> SCTR_SWUEN_A { match self . bits { false => SCTR_SWUEN_A :: SCTR_SWUEN_DISABLE , true => SCTR_SWUEN_A :: SCTR_SWUEN_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_sctr_swuen_disable (& self) -> bool { * self == SCTR_SWUEN_A :: SCTR_SWUEN_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_sctr_swuen_enable (& self) -> bool { * self == SCTR_SWUEN_A :: SCTR_SWUEN_ENABLE } } # [doc = "Field `SCTR_SWUEN` writer - Slave Wakeup Enable"] pub type SCTR_SWUEN_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , SCTR_SWUEN_A > ; impl < 'a , REG , const O : u8 > SCTR_SWUEN_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn sctr_swuen_disable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_SWUEN_A :: SCTR_SWUEN_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn sctr_swuen_enable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_SWUEN_A :: SCTR_SWUEN_ENABLE) } } impl R { # [doc = "Bit 0 - Device Active. Setting this bit enables the slave functionality."] # [inline (always)] pub fn sctr_active (& self) -> SCTR_ACTIVE_R { SCTR_ACTIVE_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - General call response enable. This bit is only available in UCBxI2COA0. Modify only when UCSWRST = 1. 0b = Do not respond to a general call 1b = Respond to a general call"] # [inline (always)] pub fn sctr_gencall (& self) -> SCTR_GENCALL_R { SCTR_GENCALL_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - Slave Clock Stretch Enable"] # [inline (always)] pub fn sctr_sclkstretch (& self) -> SCTR_SCLKSTRETCH_R { SCTR_SCLKSTRETCH_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - Tx Empty Interrupt on TREQ"] # [inline (always)] pub fn sctr_txempty_on_treq (& self) -> SCTR_TXEMPTY_ON_TREQ_R { SCTR_TXEMPTY_ON_TREQ_R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - Tx Trigger when slave FSM is in Tx Mode"] # [inline (always)] pub fn sctr_txtrig_txmode (& self) -> SCTR_TXTRIG_TXMODE_R { SCTR_TXTRIG_TXMODE_R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - Tx transfer waits when stale data in Tx FIFO. This prevents stale bytes left in the TX FIFO from automatically being sent on the next I2C packet. Note: this should be used with TXEMPTY_ON_TREQ set to prevent the Slave State Machine from waiting for TX FIFO data without an interrupt notification when the FIFO data is stale."] # [inline (always)] pub fn sctr_txwait_stale_txfifo (& self) -> SCTR_TXWAIT_STALE_TXFIFO_R { SCTR_TXWAIT_STALE_TXFIFO_R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - Rx full interrupt generated on RREQ condition as indicated in SSR"] # [inline (always)] pub fn sctr_rxfull_on_rreq (& self) -> SCTR_RXFULL_ON_RREQ_R { SCTR_RXFULL_ON_RREQ_R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - Enable Default Host Address"] # [inline (always)] pub fn sctr_en_defhostadr (& self) -> SCTR_EN_DEFHOSTADR_R { SCTR_EN_DEFHOSTADR_R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - Enable Alert Response Address"] # [inline (always)] pub fn sctr_en_alrespadr (& self) -> SCTR_EN_ALRESPADR_R { SCTR_EN_ALRESPADR_R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - Enable Deault device address"] # [inline (always)] pub fn sctr_en_defdevadr (& self) -> SCTR_EN_DEFDEVADR_R { SCTR_EN_DEFDEVADR_R :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - Slave Wakeup Enable"] # [inline (always)] pub fn sctr_swuen (& self) -> SCTR_SWUEN_R { SCTR_SWUEN_R :: new (((self . bits >> 10) & 1) != 0) } } impl W { # [doc = "Bit 0 - Device Active. Setting this bit enables the slave functionality."] # [inline (always)] # [must_use] pub fn sctr_active (& mut self) -> SCTR_ACTIVE_W < SCTR_SPEC , 0 > { SCTR_ACTIVE_W :: new (self) } # [doc = "Bit 1 - General call response enable. This bit is only available in UCBxI2COA0. Modify only when UCSWRST = 1. 0b = Do not respond to a general call 1b = Respond to a general call"] # [inline (always)] # [must_use] pub fn sctr_gencall (& mut self) -> SCTR_GENCALL_W < SCTR_SPEC , 1 > { SCTR_GENCALL_W :: new (self) } # [doc = "Bit 2 - Slave Clock Stretch Enable"] # [inline (always)] # [must_use] pub fn sctr_sclkstretch (& mut self) -> SCTR_SCLKSTRETCH_W < SCTR_SPEC , 2 > { SCTR_SCLKSTRETCH_W :: new (self) } # [doc = "Bit 3 - Tx Empty Interrupt on TREQ"] # [inline (always)] # [must_use] pub fn sctr_txempty_on_treq (& mut self) -> SCTR_TXEMPTY_ON_TREQ_W < SCTR_SPEC , 3 > { SCTR_TXEMPTY_ON_TREQ_W :: new (self) } # [doc = "Bit 4 - Tx Trigger when slave FSM is in Tx Mode"] # [inline (always)] # [must_use] pub fn sctr_txtrig_txmode (& mut self) -> SCTR_TXTRIG_TXMODE_W < SCTR_SPEC , 4 > { SCTR_TXTRIG_TXMODE_W :: new (self) } # [doc = "Bit 5 - Tx transfer waits when stale data in Tx FIFO. This prevents stale bytes left in the TX FIFO from automatically being sent on the next I2C packet. Note: this should be used with TXEMPTY_ON_TREQ set to prevent the Slave State Machine from waiting for TX FIFO data without an interrupt notification when the FIFO data is stale."] # [inline (always)] # [must_use] pub fn sctr_txwait_stale_txfifo (& mut self) -> SCTR_TXWAIT_STALE_TXFIFO_W <'_, SCTR_SPEC , 5 > { SCTR_TXWAIT_STALE_TXFIFO_W :: new (self) } # [doc = "Bit 6 - Rx full interrupt generated on RREQ condition as indicated in SSR"] # [inline (always)] # [must_use] pub fn sctr_rxfull_on_rreq (& mut self) -> SCTR_RXFULL_ON_RREQ_W < SCTR_SPEC , 6 > { SCTR_RXFULL_ON_RREQ_W :: new (self) } # [doc = "Bit 7 - Enable Default Host Address"] # [inline (always)] # [must_use] pub fn sctr_en_defhostadr (& mut self) -> SCTR_EN_DEFHOSTADR_W < SCTR_SPEC , 7 > { SCTR_EN_DEFHOSTADR_W :: new (self) } # [doc = "Bit 8 - Enable Alert Response Address"] # [inline (always)] # [must_use] pub fn sctr_en_alrespadr (& mut self) -> SCTR_EN_ALRESPADR_W < SCTR_SPEC , 8 > { SCTR_EN_ALRESPADR_W :: new (self) } # [doc = "Bit 9 - Enable Deault device address"] # [inline (always)] # [must_use] pub fn sctr_en_defdevadr (& mut self) -> SCTR_EN_DEFDEVADR_W < SCTR_SPEC , 9 > { SCTR_EN_DEFDEVADR_W :: new (self) } # [doc = "Bit 10 - Slave Wakeup Enable"] # [inline (always)] # [must_use] pub fn sctr_swuen (& mut self) -> SCTR_SWUEN_W < SCTR_SPEC , 10 > { SCTR_SWUEN_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "I2C Slave Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sctr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sctr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct SCTR_SPEC ; impl crate :: RegisterSpec for SCTR_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`sctr::R`](R) reader structure"] impl crate :: Readable for SCTR_SPEC { } # [doc = "`write(|w| ..)` method takes [`sctr::W`](W) writer structure"] impl crate :: Writable for SCTR_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets SCTR to value 0x0404"] impl crate :: Resettable for SCTR_SPEC { const RESET_VALUE : Self :: Ux = 0x0404 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/i2c1/pwren.rs:1:2941 [INFO] [stdout] | [INFO] [stdout] 1 | ...use] pub fn pwren_enable (& mut self) -> PWREN_ENABLE_W < PWREN_SPEC , 0 > { PWREN_ENABLE_W :: new (self) } # [doc = "Bits 24:31 - KEY... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `PWREN` reader"] pub type R = crate :: R < PWREN_SPEC > ; # [doc = "Register `PWREN` writer"] pub type W = crate :: W < PWREN_SPEC > ; # [doc = "Field `PWREN_ENABLE` reader - Enable the power"] pub type PWREN_ENABLE_R = crate :: BitReader < PWREN_ENABLE_A > ; # [doc = "Enable the power\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum PWREN_ENABLE_A { # [doc = "0: DISABLE"] PWREN_ENABLE_DISABLE = 0 , # [doc = "1: ENABLE"] PWREN_ENABLE_ENABLE = 1 , } impl From < PWREN_ENABLE_A > for bool { # [inline (always)] fn from (variant : PWREN_ENABLE_A) -> Self { variant as u8 != 0 } } impl PWREN_ENABLE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> PWREN_ENABLE_A { match self . bits { false => PWREN_ENABLE_A :: PWREN_ENABLE_DISABLE , true => PWREN_ENABLE_A :: PWREN_ENABLE_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_pwren_enable_disable (& self) -> bool { * self == PWREN_ENABLE_A :: PWREN_ENABLE_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_pwren_enable_enable (& self) -> bool { * self == PWREN_ENABLE_A :: PWREN_ENABLE_ENABLE } } # [doc = "Field `PWREN_ENABLE` writer - Enable the power"] pub type PWREN_ENABLE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , PWREN_ENABLE_A > ; impl < 'a , REG , const O : u8 > PWREN_ENABLE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn pwren_enable_disable (self) -> & 'a mut crate :: W < REG > { self . variant (PWREN_ENABLE_A :: PWREN_ENABLE_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn pwren_enable_enable (self) -> & 'a mut crate :: W < REG > { self . variant (PWREN_ENABLE_A :: PWREN_ENABLE_ENABLE) } } # [doc = "KEY to allow Power State Change\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum PWREN_KEY_AW { # [doc = "38: _TO_UNLOCK_W_"] PWREN_KEY_UNLOCK_W = 38 , } impl From < PWREN_KEY_AW > for u8 { # [inline (always)] fn from (variant : PWREN_KEY_AW) -> Self { variant as _ } } impl crate :: FieldSpec for PWREN_KEY_AW { type Ux = u8 ; } # [doc = "Field `PWREN_KEY` writer - KEY to allow Power State Change"] pub type PWREN_KEY_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 8 , O , PWREN_KEY_AW > ; impl < 'a , REG , const O : u8 > PWREN_KEY_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "_TO_UNLOCK_W_"] # [inline (always)] pub fn pwren_key_unlock_w (self) -> & 'a mut crate :: W < REG > { self . variant (PWREN_KEY_AW :: PWREN_KEY_UNLOCK_W) } } impl R { # [doc = "Bit 0 - Enable the power"] # [inline (always)] pub fn pwren_enable (& self) -> PWREN_ENABLE_R { PWREN_ENABLE_R :: new ((self . bits & 1) != 0) } } impl W { # [doc = "Bit 0 - Enable the power"] # [inline (always)] # [must_use] pub fn pwren_enable (& mut self) -> PWREN_ENABLE_W <'_, PWREN_SPEC , 0 > { PWREN_ENABLE_W :: new (self) } # [doc = "Bits 24:31 - KEY to allow Power State Change"] # [inline (always)] # [must_use] pub fn pwren_key (& mut self) -> PWREN_KEY_W < PWREN_SPEC , 24 > { PWREN_KEY_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Power enable\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pwren::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pwren::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PWREN_SPEC ; impl crate :: RegisterSpec for PWREN_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`pwren::R`](R) reader structure"] impl crate :: Readable for PWREN_SPEC { } # [doc = "`write(|w| ..)` method takes [`pwren::W`](W) writer structure"] impl crate :: Writable for PWREN_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets PWREN to value 0"] impl crate :: Resettable for PWREN_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/opa0/cfgbase.rs:1:5060 [INFO] [stdout] | [INFO] [stdout] 1 | ..._use] pub fn cfgbase_rri (& mut self) -> CFGBASE_RRI_W < CFGBASE_SPEC , 2 > { CFGBASE_RRI_W :: new (self) } # [doc = r" Writes raw bit... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `CFGBASE` reader"] pub type R = crate :: R < CFGBASE_SPEC > ; # [doc = "Register `CFGBASE` writer"] pub type W = crate :: W < CFGBASE_SPEC > ; # [doc = "Field `CFGBASE_GBW` reader - Select gain bandwidth which affects current as well the gain bandwidth. The lower gain bandwidth has lower current. See device specific datasheet for values. Can only be modified when STAT.BUSY=0."] pub type CFGBASE_GBW_R = crate :: BitReader < CFGBASE_GBW_A > ; # [doc = "Select gain bandwidth which affects current as well the gain bandwidth. The lower gain bandwidth has lower current. See device specific datasheet for values. Can only be modified when STAT.BUSY=0.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CFGBASE_GBW_A { # [doc = "0: LOWGAIN"] CFGBASE_GBW_LOWGAIN = 0 , # [doc = "1: HIGHGAIN"] CFGBASE_GBW_HIGHGAIN = 1 , } impl From < CFGBASE_GBW_A > for bool { # [inline (always)] fn from (variant : CFGBASE_GBW_A) -> Self { variant as u8 != 0 } } impl CFGBASE_GBW_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CFGBASE_GBW_A { match self . bits { false => CFGBASE_GBW_A :: CFGBASE_GBW_LOWGAIN , true => CFGBASE_GBW_A :: CFGBASE_GBW_HIGHGAIN , } } # [doc = "LOWGAIN"] # [inline (always)] pub fn is_cfgbase_gbw_lowgain (& self) -> bool { * self == CFGBASE_GBW_A :: CFGBASE_GBW_LOWGAIN } # [doc = "HIGHGAIN"] # [inline (always)] pub fn is_cfgbase_gbw_highgain (& self) -> bool { * self == CFGBASE_GBW_A :: CFGBASE_GBW_HIGHGAIN } } # [doc = "Field `CFGBASE_GBW` writer - Select gain bandwidth which affects current as well the gain bandwidth. The lower gain bandwidth has lower current. See device specific datasheet for values. Can only be modified when STAT.BUSY=0."] pub type CFGBASE_GBW_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CFGBASE_GBW_A > ; impl < 'a , REG , const O : u8 > CFGBASE_GBW_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "LOWGAIN"] # [inline (always)] pub fn cfgbase_gbw_lowgain (self) -> & 'a mut crate :: W < REG > { self . variant (CFGBASE_GBW_A :: CFGBASE_GBW_LOWGAIN) } # [doc = "HIGHGAIN"] # [inline (always)] pub fn cfgbase_gbw_highgain (self) -> & 'a mut crate :: W < REG > { self . variant (CFGBASE_GBW_A :: CFGBASE_GBW_HIGHGAIN) } } # [doc = "Field `CFGBASE_RRI` reader - Rail-to-rail input enable. Can only be modified when STAT.BUSY=0"] pub type CFGBASE_RRI_R = crate :: BitReader < CFGBASE_RRI_A > ; # [doc = "Rail-to-rail input enable. Can only be modified when STAT.BUSY=0\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CFGBASE_RRI_A { # [doc = "0: OFF"] CFGBASE_RRI_OFF = 0 , # [doc = "1: ON"] CFGBASE_RRI_ON = 1 , } impl From < CFGBASE_RRI_A > for bool { # [inline (always)] fn from (variant : CFGBASE_RRI_A) -> Self { variant as u8 != 0 } } impl CFGBASE_RRI_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CFGBASE_RRI_A { match self . bits { false => CFGBASE_RRI_A :: CFGBASE_RRI_OFF , true => CFGBASE_RRI_A :: CFGBASE_RRI_ON , } } # [doc = "OFF"] # [inline (always)] pub fn is_cfgbase_rri_off (& self) -> bool { * self == CFGBASE_RRI_A :: CFGBASE_RRI_OFF } # [doc = "ON"] # [inline (always)] pub fn is_cfgbase_rri_on (& self) -> bool { * self == CFGBASE_RRI_A :: CFGBASE_RRI_ON } } # [doc = "Field `CFGBASE_RRI` writer - Rail-to-rail input enable. Can only be modified when STAT.BUSY=0"] pub type CFGBASE_RRI_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CFGBASE_RRI_A > ; impl < 'a , REG , const O : u8 > CFGBASE_RRI_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "OFF"] # [inline (always)] pub fn cfgbase_rri_off (self) -> & 'a mut crate :: W < REG > { self . variant (CFGBASE_RRI_A :: CFGBASE_RRI_OFF) } # [doc = "ON"] # [inline (always)] pub fn cfgbase_rri_on (self) -> & 'a mut crate :: W < REG > { self . variant (CFGBASE_RRI_A :: CFGBASE_RRI_ON) } } impl R { # [doc = "Bit 0 - Select gain bandwidth which affects current as well the gain bandwidth. The lower gain bandwidth has lower current. See device specific datasheet for values. Can only be modified when STAT.BUSY=0."] # [inline (always)] pub fn cfgbase_gbw (& self) -> CFGBASE_GBW_R { CFGBASE_GBW_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 2 - Rail-to-rail input enable. Can only be modified when STAT.BUSY=0"] # [inline (always)] pub fn cfgbase_rri (& self) -> CFGBASE_RRI_R { CFGBASE_RRI_R :: new (((self . bits >> 2) & 1) != 0) } } impl W { # [doc = "Bit 0 - Select gain bandwidth which affects current as well the gain bandwidth. The lower gain bandwidth has lower current. See device specific datasheet for values. Can only be modified when STAT.BUSY=0."] # [inline (always)] # [must_use] pub fn cfgbase_gbw (& mut self) -> CFGBASE_GBW_W < CFGBASE_SPEC , 0 > { CFGBASE_GBW_W :: new (self) } # [doc = "Bit 2 - Rail-to-rail input enable. Can only be modified when STAT.BUSY=0"] # [inline (always)] # [must_use] pub fn cfgbase_rri (& mut self) -> CFGBASE_RRI_W <'_, CFGBASE_SPEC , 2 > { CFGBASE_RRI_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Configuration Base Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cfgbase::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cfgbase::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CFGBASE_SPEC ; impl crate :: RegisterSpec for CFGBASE_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`cfgbase::R`](R) reader structure"] impl crate :: Readable for CFGBASE_SPEC { } # [doc = "`write(|w| ..)` method takes [`cfgbase::W`](W) writer structure"] impl crate :: Writable for CFGBASE_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets CFGBASE to value 0"] impl crate :: Resettable for CFGBASE_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/i2c1/int_event2_imask.rs:1:9947 [INFO] [stdout] | [INFO] [stdout] 1 | ..._mrxfifotrg (& mut self) -> INT_EVENT2_IMASK_MRXFIFOTRG_W < INT_EVENT2_IMASK_SPEC , 0 > { INT_EVENT2_IMASK_MRXFIFOTRG_W :: new (self) ... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `INT_EVENT2_IMASK` reader"] pub type R = crate :: R < INT_EVENT2_IMASK_SPEC > ; # [doc = "Register `INT_EVENT2_IMASK` writer"] pub type W = crate :: W < INT_EVENT2_IMASK_SPEC > ; # [doc = "Field `INT_EVENT2_IMASK_MRXFIFOTRG` reader - Master Receive FIFO Trigger Trigger when RX FIFO contains &gt;= defined bytes"] pub type INT_EVENT2_IMASK_MRXFIFOTRG_R = crate :: BitReader < INT_EVENT2_IMASK_MRXFIFOTRG_A > ; # [doc = "Master Receive FIFO Trigger Trigger when RX FIFO contains &gt;= defined bytes\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT2_IMASK_MRXFIFOTRG_A { # [doc = "0: CLR"] INT_EVENT2_IMASK_MRXFIFOTRG_CLR = 0 , # [doc = "1: SET"] INT_EVENT2_IMASK_MRXFIFOTRG_SET = 1 , } impl From < INT_EVENT2_IMASK_MRXFIFOTRG_A > for bool { # [inline (always)] fn from (variant : INT_EVENT2_IMASK_MRXFIFOTRG_A) -> Self { variant as u8 != 0 } } impl INT_EVENT2_IMASK_MRXFIFOTRG_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT2_IMASK_MRXFIFOTRG_A { match self . bits { false => INT_EVENT2_IMASK_MRXFIFOTRG_A :: INT_EVENT2_IMASK_MRXFIFOTRG_CLR , true => INT_EVENT2_IMASK_MRXFIFOTRG_A :: INT_EVENT2_IMASK_MRXFIFOTRG_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event2_imask_mrxfifotrg_clr (& self) -> bool { * self == INT_EVENT2_IMASK_MRXFIFOTRG_A :: INT_EVENT2_IMASK_MRXFIFOTRG_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event2_imask_mrxfifotrg_set (& self) -> bool { * self == INT_EVENT2_IMASK_MRXFIFOTRG_A :: INT_EVENT2_IMASK_MRXFIFOTRG_SET } } # [doc = "Field `INT_EVENT2_IMASK_MRXFIFOTRG` writer - Master Receive FIFO Trigger Trigger when RX FIFO contains &gt;= defined bytes"] pub type INT_EVENT2_IMASK_MRXFIFOTRG_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT2_IMASK_MRXFIFOTRG_A > ; impl < 'a , REG , const O : u8 > INT_EVENT2_IMASK_MRXFIFOTRG_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event2_imask_mrxfifotrg_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT2_IMASK_MRXFIFOTRG_A :: INT_EVENT2_IMASK_MRXFIFOTRG_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event2_imask_mrxfifotrg_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT2_IMASK_MRXFIFOTRG_A :: INT_EVENT2_IMASK_MRXFIFOTRG_SET) } } # [doc = "Field `INT_EVENT2_IMASK_MTXFIFOTRG` reader - Master Transmit FIFO Trigger Trigger when Transmit FIFO contains &lt;= defined bytes"] pub type INT_EVENT2_IMASK_MTXFIFOTRG_R = crate :: BitReader < INT_EVENT2_IMASK_MTXFIFOTRG_A > ; # [doc = "Master Transmit FIFO Trigger Trigger when Transmit FIFO contains &lt;= defined bytes\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT2_IMASK_MTXFIFOTRG_A { # [doc = "0: CLR"] INT_EVENT2_IMASK_MTXFIFOTRG_CLR = 0 , # [doc = "1: SET"] INT_EVENT2_IMASK_MTXFIFOTRG_SET = 1 , } impl From < INT_EVENT2_IMASK_MTXFIFOTRG_A > for bool { # [inline (always)] fn from (variant : INT_EVENT2_IMASK_MTXFIFOTRG_A) -> Self { variant as u8 != 0 } } impl INT_EVENT2_IMASK_MTXFIFOTRG_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT2_IMASK_MTXFIFOTRG_A { match self . bits { false => INT_EVENT2_IMASK_MTXFIFOTRG_A :: INT_EVENT2_IMASK_MTXFIFOTRG_CLR , true => INT_EVENT2_IMASK_MTXFIFOTRG_A :: INT_EVENT2_IMASK_MTXFIFOTRG_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event2_imask_mtxfifotrg_clr (& self) -> bool { * self == INT_EVENT2_IMASK_MTXFIFOTRG_A :: INT_EVENT2_IMASK_MTXFIFOTRG_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event2_imask_mtxfifotrg_set (& self) -> bool { * self == INT_EVENT2_IMASK_MTXFIFOTRG_A :: INT_EVENT2_IMASK_MTXFIFOTRG_SET } } # [doc = "Field `INT_EVENT2_IMASK_MTXFIFOTRG` writer - Master Transmit FIFO Trigger Trigger when Transmit FIFO contains &lt;= defined bytes"] pub type INT_EVENT2_IMASK_MTXFIFOTRG_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT2_IMASK_MTXFIFOTRG_A > ; impl < 'a , REG , const O : u8 > INT_EVENT2_IMASK_MTXFIFOTRG_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event2_imask_mtxfifotrg_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT2_IMASK_MTXFIFOTRG_A :: INT_EVENT2_IMASK_MTXFIFOTRG_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event2_imask_mtxfifotrg_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT2_IMASK_MTXFIFOTRG_A :: INT_EVENT2_IMASK_MTXFIFOTRG_SET) } } # [doc = "Field `INT_EVENT2_IMASK_SRXFIFOTRG` reader - Slave Receive FIFO Trigger"] pub type INT_EVENT2_IMASK_SRXFIFOTRG_R = crate :: BitReader < INT_EVENT2_IMASK_SRXFIFOTRG_A > ; # [doc = "Slave Receive FIFO Trigger\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT2_IMASK_SRXFIFOTRG_A { # [doc = "0: CLR"] INT_EVENT2_IMASK_SRXFIFOTRG_CLR = 0 , # [doc = "1: SET"] INT_EVENT2_IMASK_SRXFIFOTRG_SET = 1 , } impl From < INT_EVENT2_IMASK_SRXFIFOTRG_A > for bool { # [inline (always)] fn from (variant : INT_EVENT2_IMASK_SRXFIFOTRG_A) -> Self { variant as u8 != 0 } } impl INT_EVENT2_IMASK_SRXFIFOTRG_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT2_IMASK_SRXFIFOTRG_A { match self . bits { false => INT_EVENT2_IMASK_SRXFIFOTRG_A :: INT_EVENT2_IMASK_SRXFIFOTRG_CLR , true => INT_EVENT2_IMASK_SRXFIFOTRG_A :: INT_EVENT2_IMASK_SRXFIFOTRG_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event2_imask_srxfifotrg_clr (& self) -> bool { * self == INT_EVENT2_IMASK_SRXFIFOTRG_A :: INT_EVENT2_IMASK_SRXFIFOTRG_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event2_imask_srxfifotrg_set (& self) -> bool { * self == INT_EVENT2_IMASK_SRXFIFOTRG_A :: INT_EVENT2_IMASK_SRXFIFOTRG_SET } } # [doc = "Field `INT_EVENT2_IMASK_SRXFIFOTRG` writer - Slave Receive FIFO Trigger"] pub type INT_EVENT2_IMASK_SRXFIFOTRG_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT2_IMASK_SRXFIFOTRG_A > ; impl < 'a , REG , const O : u8 > INT_EVENT2_IMASK_SRXFIFOTRG_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event2_imask_srxfifotrg_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT2_IMASK_SRXFIFOTRG_A :: INT_EVENT2_IMASK_SRXFIFOTRG_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event2_imask_srxfifotrg_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT2_IMASK_SRXFIFOTRG_A :: INT_EVENT2_IMASK_SRXFIFOTRG_SET) } } # [doc = "Field `INT_EVENT2_IMASK_STXFIFOTRG` reader - Slave Transmit FIFO Trigger"] pub type INT_EVENT2_IMASK_STXFIFOTRG_R = crate :: BitReader < INT_EVENT2_IMASK_STXFIFOTRG_A > ; # [doc = "Slave Transmit FIFO Trigger\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT2_IMASK_STXFIFOTRG_A { # [doc = "0: CLR"] INT_EVENT2_IMASK_STXFIFOTRG_CLR = 0 , # [doc = "1: SET"] INT_EVENT2_IMASK_STXFIFOTRG_SET = 1 , } impl From < INT_EVENT2_IMASK_STXFIFOTRG_A > for bool { # [inline (always)] fn from (variant : INT_EVENT2_IMASK_STXFIFOTRG_A) -> Self { variant as u8 != 0 } } impl INT_EVENT2_IMASK_STXFIFOTRG_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT2_IMASK_STXFIFOTRG_A { match self . bits { false => INT_EVENT2_IMASK_STXFIFOTRG_A :: INT_EVENT2_IMASK_STXFIFOTRG_CLR , true => INT_EVENT2_IMASK_STXFIFOTRG_A :: INT_EVENT2_IMASK_STXFIFOTRG_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event2_imask_stxfifotrg_clr (& self) -> bool { * self == INT_EVENT2_IMASK_STXFIFOTRG_A :: INT_EVENT2_IMASK_STXFIFOTRG_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event2_imask_stxfifotrg_set (& self) -> bool { * self == INT_EVENT2_IMASK_STXFIFOTRG_A :: INT_EVENT2_IMASK_STXFIFOTRG_SET } } # [doc = "Field `INT_EVENT2_IMASK_STXFIFOTRG` writer - Slave Transmit FIFO Trigger"] pub type INT_EVENT2_IMASK_STXFIFOTRG_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT2_IMASK_STXFIFOTRG_A > ; impl < 'a , REG , const O : u8 > INT_EVENT2_IMASK_STXFIFOTRG_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event2_imask_stxfifotrg_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT2_IMASK_STXFIFOTRG_A :: INT_EVENT2_IMASK_STXFIFOTRG_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event2_imask_stxfifotrg_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT2_IMASK_STXFIFOTRG_A :: INT_EVENT2_IMASK_STXFIFOTRG_SET) } } impl R { # [doc = "Bit 0 - Master Receive FIFO Trigger Trigger when RX FIFO contains &gt;= defined bytes"] # [inline (always)] pub fn int_event2_imask_mrxfifotrg (& self) -> INT_EVENT2_IMASK_MRXFIFOTRG_R { INT_EVENT2_IMASK_MRXFIFOTRG_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - Master Transmit FIFO Trigger Trigger when Transmit FIFO contains &lt;= defined bytes"] # [inline (always)] pub fn int_event2_imask_mtxfifotrg (& self) -> INT_EVENT2_IMASK_MTXFIFOTRG_R { INT_EVENT2_IMASK_MTXFIFOTRG_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - Slave Receive FIFO Trigger"] # [inline (always)] pub fn int_event2_imask_srxfifotrg (& self) -> INT_EVENT2_IMASK_SRXFIFOTRG_R { INT_EVENT2_IMASK_SRXFIFOTRG_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - Slave Transmit FIFO Trigger"] # [inline (always)] pub fn int_event2_imask_stxfifotrg (& self) -> INT_EVENT2_IMASK_STXFIFOTRG_R { INT_EVENT2_IMASK_STXFIFOTRG_R :: new (((self . bits >> 3) & 1) != 0) } } impl W { # [doc = "Bit 0 - Master Receive FIFO Trigger Trigger when RX FIFO contains &gt;= defined bytes"] # [inline (always)] # [must_use] pub fn int_event2_imask_mrxfifotrg (& mut self) -> INT_EVENT2_IMASK_MRXFIFOTRG_W <'_, INT_EVENT2_IMASK_SPEC , 0 > { INT_EVENT2_IMASK_MRXFIFOTRG_W :: new (self) } # [doc = "Bit 1 - Master Transmit FIFO Trigger Trigger when Transmit FIFO contains &lt;= defined bytes"] # [inline (always)] # [must_use] pub fn int_event2_imask_mtxfifotrg (& mut self) -> INT_EVENT2_IMASK_MTXFIFOTRG_W < INT_EVENT2_IMASK_SPEC , 1 > { INT_EVENT2_IMASK_MTXFIFOTRG_W :: new (self) } # [doc = "Bit 2 - Slave Receive FIFO Trigger"] # [inline (always)] # [must_use] pub fn int_event2_imask_srxfifotrg (& mut self) -> INT_EVENT2_IMASK_SRXFIFOTRG_W < INT_EVENT2_IMASK_SPEC , 2 > { INT_EVENT2_IMASK_SRXFIFOTRG_W :: new (self) } # [doc = "Bit 3 - Slave Transmit FIFO Trigger"] # [inline (always)] # [must_use] pub fn int_event2_imask_stxfifotrg (& mut self) -> INT_EVENT2_IMASK_STXFIFOTRG_W < INT_EVENT2_IMASK_SPEC , 3 > { INT_EVENT2_IMASK_STXFIFOTRG_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Interrupt mask\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_event2_imask::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_event2_imask::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct INT_EVENT2_IMASK_SPEC ; impl crate :: RegisterSpec for INT_EVENT2_IMASK_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`int_event2_imask::R`](R) reader structure"] impl crate :: Readable for INT_EVENT2_IMASK_SPEC { } # [doc = "`write(|w| ..)` method takes [`int_event2_imask::W`](W) writer structure"] impl crate :: Writable for INT_EVENT2_IMASK_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets INT_EVENT2_IMASK to value 0"] impl crate :: Resettable for INT_EVENT2_IMASK_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/i2c0/mfifoctl.rs:1:12308 [INFO] [stdout] | [INFO] [stdout] 1 | ...ub fn mfifoctl_txtrig (& mut self) -> MFIFOCTL_TXTRIG_W < MFIFOCTL_SPEC , 0 > { MFIFOCTL_TXTRIG_W :: new (self) } # [doc = "Bit 7 - TX... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `MFIFOCTL` reader"] pub type R = crate :: R < MFIFOCTL_SPEC > ; # [doc = "Register `MFIFOCTL` writer"] pub type W = crate :: W < MFIFOCTL_SPEC > ; # [doc = "Field `MFIFOCTL_TXTRIG` reader - TX FIFO Trigger Indicates at what fill level in the TX FIFO a trigger will be generated."] pub type MFIFOCTL_TXTRIG_R = crate :: FieldReader < MFIFOCTL_TXTRIG_A > ; # [doc = "TX FIFO Trigger Indicates at what fill level in the TX FIFO a trigger will be generated.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum MFIFOCTL_TXTRIG_A { # [doc = "4: LEVEL_4"] MFIFOCTL_TXTRIG_LEVEL_4 = 4 , # [doc = "5: LEVEL_5"] MFIFOCTL_TXTRIG_LEVEL_5 = 5 , # [doc = "6: LEVEL_6"] MFIFOCTL_TXTRIG_LEVEL_6 = 6 , # [doc = "7: LEVEL_7"] MFIFOCTL_TXTRIG_LEVEL_7 = 7 , } impl From < MFIFOCTL_TXTRIG_A > for u8 { # [inline (always)] fn from (variant : MFIFOCTL_TXTRIG_A) -> Self { variant as _ } } impl crate :: FieldSpec for MFIFOCTL_TXTRIG_A { type Ux = u8 ; } impl MFIFOCTL_TXTRIG_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < MFIFOCTL_TXTRIG_A > { match self . bits { 4 => Some (MFIFOCTL_TXTRIG_A :: MFIFOCTL_TXTRIG_LEVEL_4) , 5 => Some (MFIFOCTL_TXTRIG_A :: MFIFOCTL_TXTRIG_LEVEL_5) , 6 => Some (MFIFOCTL_TXTRIG_A :: MFIFOCTL_TXTRIG_LEVEL_6) , 7 => Some (MFIFOCTL_TXTRIG_A :: MFIFOCTL_TXTRIG_LEVEL_7) , _ => None , } } # [doc = "LEVEL_4"] # [inline (always)] pub fn is_mfifoctl_txtrig_level_4 (& self) -> bool { * self == MFIFOCTL_TXTRIG_A :: MFIFOCTL_TXTRIG_LEVEL_4 } # [doc = "LEVEL_5"] # [inline (always)] pub fn is_mfifoctl_txtrig_level_5 (& self) -> bool { * self == MFIFOCTL_TXTRIG_A :: MFIFOCTL_TXTRIG_LEVEL_5 } # [doc = "LEVEL_6"] # [inline (always)] pub fn is_mfifoctl_txtrig_level_6 (& self) -> bool { * self == MFIFOCTL_TXTRIG_A :: MFIFOCTL_TXTRIG_LEVEL_6 } # [doc = "LEVEL_7"] # [inline (always)] pub fn is_mfifoctl_txtrig_level_7 (& self) -> bool { * self == MFIFOCTL_TXTRIG_A :: MFIFOCTL_TXTRIG_LEVEL_7 } } # [doc = "Field `MFIFOCTL_TXTRIG` writer - TX FIFO Trigger Indicates at what fill level in the TX FIFO a trigger will be generated."] pub type MFIFOCTL_TXTRIG_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 3 , O , MFIFOCTL_TXTRIG_A > ; impl < 'a , REG , const O : u8 > MFIFOCTL_TXTRIG_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "LEVEL_4"] # [inline (always)] pub fn mfifoctl_txtrig_level_4 (self) -> & 'a mut crate :: W < REG > { self . variant (MFIFOCTL_TXTRIG_A :: MFIFOCTL_TXTRIG_LEVEL_4) } # [doc = "LEVEL_5"] # [inline (always)] pub fn mfifoctl_txtrig_level_5 (self) -> & 'a mut crate :: W < REG > { self . variant (MFIFOCTL_TXTRIG_A :: MFIFOCTL_TXTRIG_LEVEL_5) } # [doc = "LEVEL_6"] # [inline (always)] pub fn mfifoctl_txtrig_level_6 (self) -> & 'a mut crate :: W < REG > { self . variant (MFIFOCTL_TXTRIG_A :: MFIFOCTL_TXTRIG_LEVEL_6) } # [doc = "LEVEL_7"] # [inline (always)] pub fn mfifoctl_txtrig_level_7 (self) -> & 'a mut crate :: W < REG > { self . variant (MFIFOCTL_TXTRIG_A :: MFIFOCTL_TXTRIG_LEVEL_7) } } # [doc = "Field `MFIFOCTL_TXFLUSH` reader - TX FIFO Flush Setting this bit will Flush the TX FIFO. Before reseting this bit to stop Flush the TXFIFOCNT should be checked to be 8 and indicating that the Flush has completed."] pub type MFIFOCTL_TXFLUSH_R = crate :: BitReader < MFIFOCTL_TXFLUSH_A > ; # [doc = "TX FIFO Flush Setting this bit will Flush the TX FIFO. Before reseting this bit to stop Flush the TXFIFOCNT should be checked to be 8 and indicating that the Flush has completed.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum MFIFOCTL_TXFLUSH_A { # [doc = "0: NOFLUSH"] MFIFOCTL_TXFLUSH_NOFLUSH = 0 , # [doc = "1: FLUSH"] MFIFOCTL_TXFLUSH_FLUSH = 1 , } impl From < MFIFOCTL_TXFLUSH_A > for bool { # [inline (always)] fn from (variant : MFIFOCTL_TXFLUSH_A) -> Self { variant as u8 != 0 } } impl MFIFOCTL_TXFLUSH_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> MFIFOCTL_TXFLUSH_A { match self . bits { false => MFIFOCTL_TXFLUSH_A :: MFIFOCTL_TXFLUSH_NOFLUSH , true => MFIFOCTL_TXFLUSH_A :: MFIFOCTL_TXFLUSH_FLUSH , } } # [doc = "NOFLUSH"] # [inline (always)] pub fn is_mfifoctl_txflush_noflush (& self) -> bool { * self == MFIFOCTL_TXFLUSH_A :: MFIFOCTL_TXFLUSH_NOFLUSH } # [doc = "FLUSH"] # [inline (always)] pub fn is_mfifoctl_txflush_flush (& self) -> bool { * self == MFIFOCTL_TXFLUSH_A :: MFIFOCTL_TXFLUSH_FLUSH } } # [doc = "Field `MFIFOCTL_TXFLUSH` writer - TX FIFO Flush Setting this bit will Flush the TX FIFO. Before reseting this bit to stop Flush the TXFIFOCNT should be checked to be 8 and indicating that the Flush has completed."] pub type MFIFOCTL_TXFLUSH_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , MFIFOCTL_TXFLUSH_A > ; impl < 'a , REG , const O : u8 > MFIFOCTL_TXFLUSH_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NOFLUSH"] # [inline (always)] pub fn mfifoctl_txflush_noflush (self) -> & 'a mut crate :: W < REG > { self . variant (MFIFOCTL_TXFLUSH_A :: MFIFOCTL_TXFLUSH_NOFLUSH) } # [doc = "FLUSH"] # [inline (always)] pub fn mfifoctl_txflush_flush (self) -> & 'a mut crate :: W < REG > { self . variant (MFIFOCTL_TXFLUSH_A :: MFIFOCTL_TXFLUSH_FLUSH) } } # [doc = "Field `MFIFOCTL_RXTRIG` reader - RX FIFO Trigger Indicates at what fill level in the RX FIFO a trigger will be generated. Note: Programming RXTRIG to 0x0 has no effect since no data is present to transfer out of RX FIFO."] pub type MFIFOCTL_RXTRIG_R = crate :: FieldReader < MFIFOCTL_RXTRIG_A > ; # [doc = "RX FIFO Trigger Indicates at what fill level in the RX FIFO a trigger will be generated. Note: Programming RXTRIG to 0x0 has no effect since no data is present to transfer out of RX FIFO.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum MFIFOCTL_RXTRIG_A { # [doc = "4: LEVEL_5"] MFIFOCTL_RXTRIG_LEVEL_5 = 4 , # [doc = "5: LEVEL_6"] MFIFOCTL_RXTRIG_LEVEL_6 = 5 , # [doc = "6: LEVEL_7"] MFIFOCTL_RXTRIG_LEVEL_7 = 6 , # [doc = "7: LEVEL_8"] MFIFOCTL_RXTRIG_LEVEL_8 = 7 , } impl From < MFIFOCTL_RXTRIG_A > for u8 { # [inline (always)] fn from (variant : MFIFOCTL_RXTRIG_A) -> Self { variant as _ } } impl crate :: FieldSpec for MFIFOCTL_RXTRIG_A { type Ux = u8 ; } impl MFIFOCTL_RXTRIG_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < MFIFOCTL_RXTRIG_A > { match self . bits { 4 => Some (MFIFOCTL_RXTRIG_A :: MFIFOCTL_RXTRIG_LEVEL_5) , 5 => Some (MFIFOCTL_RXTRIG_A :: MFIFOCTL_RXTRIG_LEVEL_6) , 6 => Some (MFIFOCTL_RXTRIG_A :: MFIFOCTL_RXTRIG_LEVEL_7) , 7 => Some (MFIFOCTL_RXTRIG_A :: MFIFOCTL_RXTRIG_LEVEL_8) , _ => None , } } # [doc = "LEVEL_5"] # [inline (always)] pub fn is_mfifoctl_rxtrig_level_5 (& self) -> bool { * self == MFIFOCTL_RXTRIG_A :: MFIFOCTL_RXTRIG_LEVEL_5 } # [doc = "LEVEL_6"] # [inline (always)] pub fn is_mfifoctl_rxtrig_level_6 (& self) -> bool { * self == MFIFOCTL_RXTRIG_A :: MFIFOCTL_RXTRIG_LEVEL_6 } # [doc = "LEVEL_7"] # [inline (always)] pub fn is_mfifoctl_rxtrig_level_7 (& self) -> bool { * self == MFIFOCTL_RXTRIG_A :: MFIFOCTL_RXTRIG_LEVEL_7 } # [doc = "LEVEL_8"] # [inline (always)] pub fn is_mfifoctl_rxtrig_level_8 (& self) -> bool { * self == MFIFOCTL_RXTRIG_A :: MFIFOCTL_RXTRIG_LEVEL_8 } } # [doc = "Field `MFIFOCTL_RXTRIG` writer - RX FIFO Trigger Indicates at what fill level in the RX FIFO a trigger will be generated. Note: Programming RXTRIG to 0x0 has no effect since no data is present to transfer out of RX FIFO."] pub type MFIFOCTL_RXTRIG_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 3 , O , MFIFOCTL_RXTRIG_A > ; impl < 'a , REG , const O : u8 > MFIFOCTL_RXTRIG_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "LEVEL_5"] # [inline (always)] pub fn mfifoctl_rxtrig_level_5 (self) -> & 'a mut crate :: W < REG > { self . variant (MFIFOCTL_RXTRIG_A :: MFIFOCTL_RXTRIG_LEVEL_5) } # [doc = "LEVEL_6"] # [inline (always)] pub fn mfifoctl_rxtrig_level_6 (self) -> & 'a mut crate :: W < REG > { self . variant (MFIFOCTL_RXTRIG_A :: MFIFOCTL_RXTRIG_LEVEL_6) } # [doc = "LEVEL_7"] # [inline (always)] pub fn mfifoctl_rxtrig_level_7 (self) -> & 'a mut crate :: W < REG > { self . variant (MFIFOCTL_RXTRIG_A :: MFIFOCTL_RXTRIG_LEVEL_7) } # [doc = "LEVEL_8"] # [inline (always)] pub fn mfifoctl_rxtrig_level_8 (self) -> & 'a mut crate :: W < REG > { self . variant (MFIFOCTL_RXTRIG_A :: MFIFOCTL_RXTRIG_LEVEL_8) } } # [doc = "Field `MFIFOCTL_RXFLUSH` reader - RX FIFO Flush Setting this bit will Flush the RX FIFO. Before reseting this bit to stop Flush the RXFIFOCNT should be checked to be 0 and indicating that the Flush has completed."] pub type MFIFOCTL_RXFLUSH_R = crate :: BitReader < MFIFOCTL_RXFLUSH_A > ; # [doc = "RX FIFO Flush Setting this bit will Flush the RX FIFO. Before reseting this bit to stop Flush the RXFIFOCNT should be checked to be 0 and indicating that the Flush has completed.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum MFIFOCTL_RXFLUSH_A { # [doc = "0: NOFLUSH"] MFIFOCTL_RXFLUSH_NOFLUSH = 0 , # [doc = "1: FLUSH"] MFIFOCTL_RXFLUSH_FLUSH = 1 , } impl From < MFIFOCTL_RXFLUSH_A > for bool { # [inline (always)] fn from (variant : MFIFOCTL_RXFLUSH_A) -> Self { variant as u8 != 0 } } impl MFIFOCTL_RXFLUSH_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> MFIFOCTL_RXFLUSH_A { match self . bits { false => MFIFOCTL_RXFLUSH_A :: MFIFOCTL_RXFLUSH_NOFLUSH , true => MFIFOCTL_RXFLUSH_A :: MFIFOCTL_RXFLUSH_FLUSH , } } # [doc = "NOFLUSH"] # [inline (always)] pub fn is_mfifoctl_rxflush_noflush (& self) -> bool { * self == MFIFOCTL_RXFLUSH_A :: MFIFOCTL_RXFLUSH_NOFLUSH } # [doc = "FLUSH"] # [inline (always)] pub fn is_mfifoctl_rxflush_flush (& self) -> bool { * self == MFIFOCTL_RXFLUSH_A :: MFIFOCTL_RXFLUSH_FLUSH } } # [doc = "Field `MFIFOCTL_RXFLUSH` writer - RX FIFO Flush Setting this bit will Flush the RX FIFO. Before reseting this bit to stop Flush the RXFIFOCNT should be checked to be 0 and indicating that the Flush has completed."] pub type MFIFOCTL_RXFLUSH_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , MFIFOCTL_RXFLUSH_A > ; impl < 'a , REG , const O : u8 > MFIFOCTL_RXFLUSH_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NOFLUSH"] # [inline (always)] pub fn mfifoctl_rxflush_noflush (self) -> & 'a mut crate :: W < REG > { self . variant (MFIFOCTL_RXFLUSH_A :: MFIFOCTL_RXFLUSH_NOFLUSH) } # [doc = "FLUSH"] # [inline (always)] pub fn mfifoctl_rxflush_flush (self) -> & 'a mut crate :: W < REG > { self . variant (MFIFOCTL_RXFLUSH_A :: MFIFOCTL_RXFLUSH_FLUSH) } } impl R { # [doc = "Bits 0:2 - TX FIFO Trigger Indicates at what fill level in the TX FIFO a trigger will be generated."] # [inline (always)] pub fn mfifoctl_txtrig (& self) -> MFIFOCTL_TXTRIG_R { MFIFOCTL_TXTRIG_R :: new ((self . bits & 7) as u8) } # [doc = "Bit 7 - TX FIFO Flush Setting this bit will Flush the TX FIFO. Before reseting this bit to stop Flush the TXFIFOCNT should be checked to be 8 and indicating that the Flush has completed."] # [inline (always)] pub fn mfifoctl_txflush (& self) -> MFIFOCTL_TXFLUSH_R { MFIFOCTL_TXFLUSH_R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bits 8:10 - RX FIFO Trigger Indicates at what fill level in the RX FIFO a trigger will be generated. Note: Programming RXTRIG to 0x0 has no effect since no data is present to transfer out of RX FIFO."] # [inline (always)] pub fn mfifoctl_rxtrig (& self) -> MFIFOCTL_RXTRIG_R { MFIFOCTL_RXTRIG_R :: new (((self . bits >> 8) & 7) as u8) } # [doc = "Bit 15 - RX FIFO Flush Setting this bit will Flush the RX FIFO. Before reseting this bit to stop Flush the RXFIFOCNT should be checked to be 0 and indicating that the Flush has completed."] # [inline (always)] pub fn mfifoctl_rxflush (& self) -> MFIFOCTL_RXFLUSH_R { MFIFOCTL_RXFLUSH_R :: new (((self . bits >> 15) & 1) != 0) } } impl W { # [doc = "Bits 0:2 - TX FIFO Trigger Indicates at what fill level in the TX FIFO a trigger will be generated."] # [inline (always)] # [must_use] pub fn mfifoctl_txtrig (& mut self) -> MFIFOCTL_TXTRIG_W <'_, MFIFOCTL_SPEC , 0 > { MFIFOCTL_TXTRIG_W :: new (self) } # [doc = "Bit 7 - TX FIFO Flush Setting this bit will Flush the TX FIFO. Before reseting this bit to stop Flush the TXFIFOCNT should be checked to be 8 and indicating that the Flush has completed."] # [inline (always)] # [must_use] pub fn mfifoctl_txflush (& mut self) -> MFIFOCTL_TXFLUSH_W < MFIFOCTL_SPEC , 7 > { MFIFOCTL_TXFLUSH_W :: new (self) } # [doc = "Bits 8:10 - RX FIFO Trigger Indicates at what fill level in the RX FIFO a trigger will be generated. Note: Programming RXTRIG to 0x0 has no effect since no data is present to transfer out of RX FIFO."] # [inline (always)] # [must_use] pub fn mfifoctl_rxtrig (& mut self) -> MFIFOCTL_RXTRIG_W < MFIFOCTL_SPEC , 8 > { MFIFOCTL_RXTRIG_W :: new (self) } # [doc = "Bit 15 - RX FIFO Flush Setting this bit will Flush the RX FIFO. Before reseting this bit to stop Flush the RXFIFOCNT should be checked to be 0 and indicating that the Flush has completed."] # [inline (always)] # [must_use] pub fn mfifoctl_rxflush (& mut self) -> MFIFOCTL_RXFLUSH_W < MFIFOCTL_SPEC , 15 > { MFIFOCTL_RXFLUSH_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "I2C Master FIFO Control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mfifoctl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mfifoctl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct MFIFOCTL_SPEC ; impl crate :: RegisterSpec for MFIFOCTL_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`mfifoctl::R`](R) reader structure"] impl crate :: Readable for MFIFOCTL_SPEC { } # [doc = "`write(|w| ..)` method takes [`mfifoctl::W`](W) writer structure"] impl crate :: Writable for MFIFOCTL_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets MFIFOCTL to value 0"] impl crate :: Resettable for MFIFOCTL_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/i2c1/soar2.rs:1:4071 [INFO] [stdout] | [INFO] [stdout] 1 | ...st_use] pub fn soar2_oar2 (& mut self) -> SOAR2_OAR2_W < SOAR2_SPEC , 0 > { SOAR2_OAR2_W :: new (self) } # [doc = "Bit 7 - I2C Slave O... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `SOAR2` reader"] pub type R = crate :: R < SOAR2_SPEC > ; # [doc = "Register `SOAR2` writer"] pub type W = crate :: W < SOAR2_SPEC > ; # [doc = "Field `SOAR2_OAR2` reader - I2C Slave Own Address 2 This field specifies the alternate OAR2 address."] pub type SOAR2_OAR2_R = crate :: FieldReader ; # [doc = "Field `SOAR2_OAR2` writer - I2C Slave Own Address 2 This field specifies the alternate OAR2 address."] pub type SOAR2_OAR2_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 7 , O > ; # [doc = "Field `SOAR2_OAR2EN` reader - I2C Slave Own Address 2 Enable"] pub type SOAR2_OAR2EN_R = crate :: BitReader < SOAR2_OAR2EN_A > ; # [doc = "I2C Slave Own Address 2 Enable\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum SOAR2_OAR2EN_A { # [doc = "0: DISABLE"] SOAR2_OAR2EN_DISABLE = 0 , # [doc = "1: ENABLE"] SOAR2_OAR2EN_ENABLE = 1 , } impl From < SOAR2_OAR2EN_A > for bool { # [inline (always)] fn from (variant : SOAR2_OAR2EN_A) -> Self { variant as u8 != 0 } } impl SOAR2_OAR2EN_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> SOAR2_OAR2EN_A { match self . bits { false => SOAR2_OAR2EN_A :: SOAR2_OAR2EN_DISABLE , true => SOAR2_OAR2EN_A :: SOAR2_OAR2EN_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_soar2_oar2en_disable (& self) -> bool { * self == SOAR2_OAR2EN_A :: SOAR2_OAR2EN_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_soar2_oar2en_enable (& self) -> bool { * self == SOAR2_OAR2EN_A :: SOAR2_OAR2EN_ENABLE } } # [doc = "Field `SOAR2_OAR2EN` writer - I2C Slave Own Address 2 Enable"] pub type SOAR2_OAR2EN_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , SOAR2_OAR2EN_A > ; impl < 'a , REG , const O : u8 > SOAR2_OAR2EN_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn soar2_oar2en_disable (self) -> & 'a mut crate :: W < REG > { self . variant (SOAR2_OAR2EN_A :: SOAR2_OAR2EN_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn soar2_oar2en_enable (self) -> & 'a mut crate :: W < REG > { self . variant (SOAR2_OAR2EN_A :: SOAR2_OAR2EN_ENABLE) } } # [doc = "Field `SOAR2_OAR2_MASK` reader - I2C Slave Own Address 2 Mask: This field specifies bits A6 through A0 of the slave address. The bits with value 1 in SOAR2.OAR2_MASK field will make the corresponding incoming address bits to match by default regardless of the value inside SOAR2.OAR2 i.e. corresponding SOAR2.OAR2 bit is a dont care."] pub type SOAR2_OAR2_MASK_R = crate :: FieldReader ; # [doc = "Field `SOAR2_OAR2_MASK` writer - I2C Slave Own Address 2 Mask: This field specifies bits A6 through A0 of the slave address. The bits with value 1 in SOAR2.OAR2_MASK field will make the corresponding incoming address bits to match by default regardless of the value inside SOAR2.OAR2 i.e. corresponding SOAR2.OAR2 bit is a dont care."] pub type SOAR2_OAR2_MASK_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 7 , O > ; impl R { # [doc = "Bits 0:6 - I2C Slave Own Address 2 This field specifies the alternate OAR2 address."] # [inline (always)] pub fn soar2_oar2 (& self) -> SOAR2_OAR2_R { SOAR2_OAR2_R :: new ((self . bits & 0x7f) as u8) } # [doc = "Bit 7 - I2C Slave Own Address 2 Enable"] # [inline (always)] pub fn soar2_oar2en (& self) -> SOAR2_OAR2EN_R { SOAR2_OAR2EN_R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bits 16:22 - I2C Slave Own Address 2 Mask: This field specifies bits A6 through A0 of the slave address. The bits with value 1 in SOAR2.OAR2_MASK field will make the corresponding incoming address bits to match by default regardless of the value inside SOAR2.OAR2 i.e. corresponding SOAR2.OAR2 bit is a dont care."] # [inline (always)] pub fn soar2_oar2_mask (& self) -> SOAR2_OAR2_MASK_R { SOAR2_OAR2_MASK_R :: new (((self . bits >> 16) & 0x7f) as u8) } } impl W { # [doc = "Bits 0:6 - I2C Slave Own Address 2 This field specifies the alternate OAR2 address."] # [inline (always)] # [must_use] pub fn soar2_oar2 (& mut self) -> SOAR2_OAR2_W <'_, SOAR2_SPEC , 0 > { SOAR2_OAR2_W :: new (self) } # [doc = "Bit 7 - I2C Slave Own Address 2 Enable"] # [inline (always)] # [must_use] pub fn soar2_oar2en (& mut self) -> SOAR2_OAR2EN_W < SOAR2_SPEC , 7 > { SOAR2_OAR2EN_W :: new (self) } # [doc = "Bits 16:22 - I2C Slave Own Address 2 Mask: This field specifies bits A6 through A0 of the slave address. The bits with value 1 in SOAR2.OAR2_MASK field will make the corresponding incoming address bits to match by default regardless of the value inside SOAR2.OAR2 i.e. corresponding SOAR2.OAR2 bit is a dont care."] # [inline (always)] # [must_use] pub fn soar2_oar2_mask (& mut self) -> SOAR2_OAR2_MASK_W < SOAR2_SPEC , 16 > { SOAR2_OAR2_MASK_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "I2C Slave Own Address 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`soar2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`soar2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct SOAR2_SPEC ; impl crate :: RegisterSpec for SOAR2_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`soar2::R`](R) reader structure"] impl crate :: Readable for SOAR2_SPEC { } # [doc = "`write(|w| ..)` method takes [`soar2::W`](W) writer structure"] impl crate :: Writable for SOAR2_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets SOAR2 to value 0"] impl crate :: Resettable for SOAR2_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/i2c0/int_event0_iset.rs:1:39118 [INFO] [stdout] | [INFO] [stdout] 1 | ..._mrxfifofull (& mut self) -> INT_EVENT0_ISET_MRXFIFOFULL_W < INT_EVENT0_ISET_SPEC , 4 > { INT_EVENT0_ISET_MRXFIFOFULL_W :: new (self) ... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `INT_EVENT0_ISET` writer"] pub type W = crate :: W < INT_EVENT0_ISET_SPEC > ; # [doc = "Master Receive Data Interrupt Signals that a byte has been received\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_MRXDONE_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_MRXDONE_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_MRXDONE_SET = 1 , } impl From < INT_EVENT0_ISET_MRXDONE_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_MRXDONE_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_MRXDONE` writer - Master Receive Data Interrupt Signals that a byte has been received"] pub type INT_EVENT0_ISET_MRXDONE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_MRXDONE_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_MRXDONE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_mrxdone_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MRXDONE_AW :: INT_EVENT0_ISET_MRXDONE_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_mrxdone_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MRXDONE_AW :: INT_EVENT0_ISET_MRXDONE_SET) } } # [doc = "Master Transmit Transaction completed Interrupt\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_MTXDONE_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_MTXDONE_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_MTXDONE_SET = 1 , } impl From < INT_EVENT0_ISET_MTXDONE_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_MTXDONE_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_MTXDONE` writer - Master Transmit Transaction completed Interrupt"] pub type INT_EVENT0_ISET_MTXDONE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_MTXDONE_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_MTXDONE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_mtxdone_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MTXDONE_AW :: INT_EVENT0_ISET_MTXDONE_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_mtxdone_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MTXDONE_AW :: INT_EVENT0_ISET_MTXDONE_SET) } } # [doc = "Master Receive FIFO Trigger Trigger when RX FIFO contains &gt;= defined bytes\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_MRXFIFOTRG_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_MRXFIFOTRG_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_MRXFIFOTRG_SET = 1 , } impl From < INT_EVENT0_ISET_MRXFIFOTRG_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_MRXFIFOTRG_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_MRXFIFOTRG` writer - Master Receive FIFO Trigger Trigger when RX FIFO contains &gt;= defined bytes"] pub type INT_EVENT0_ISET_MRXFIFOTRG_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_MRXFIFOTRG_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_MRXFIFOTRG_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_mrxfifotrg_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MRXFIFOTRG_AW :: INT_EVENT0_ISET_MRXFIFOTRG_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_mrxfifotrg_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MRXFIFOTRG_AW :: INT_EVENT0_ISET_MRXFIFOTRG_SET) } } # [doc = "Master Transmit FIFO Trigger Trigger when Transmit FIFO contains &lt;= defined bytes\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_MTXFIFOTRG_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_MTXFIFOTRG_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_MTXFIFOTRG_SET = 1 , } impl From < INT_EVENT0_ISET_MTXFIFOTRG_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_MTXFIFOTRG_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_MTXFIFOTRG` writer - Master Transmit FIFO Trigger Trigger when Transmit FIFO contains &lt;= defined bytes"] pub type INT_EVENT0_ISET_MTXFIFOTRG_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_MTXFIFOTRG_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_MTXFIFOTRG_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_mtxfifotrg_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MTXFIFOTRG_AW :: INT_EVENT0_ISET_MTXFIFOTRG_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_mtxfifotrg_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MTXFIFOTRG_AW :: INT_EVENT0_ISET_MTXFIFOTRG_SET) } } # [doc = "RXFIFO full event.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_MRXFIFOFULL_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_MRXFIFOFULL_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_MRXFIFOFULL_SET = 1 , } impl From < INT_EVENT0_ISET_MRXFIFOFULL_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_MRXFIFOFULL_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_MRXFIFOFULL` writer - RXFIFO full event."] pub type INT_EVENT0_ISET_MRXFIFOFULL_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_MRXFIFOFULL_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_MRXFIFOFULL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_mrxfifofull_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MRXFIFOFULL_AW :: INT_EVENT0_ISET_MRXFIFOFULL_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_mrxfifofull_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MRXFIFOFULL_AW :: INT_EVENT0_ISET_MRXFIFOFULL_SET) } } # [doc = "Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_MTXEMPTY_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_MTXEMPTY_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_MTXEMPTY_SET = 1 , } impl From < INT_EVENT0_ISET_MTXEMPTY_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_MTXEMPTY_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_MTXEMPTY` writer - Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode."] pub type INT_EVENT0_ISET_MTXEMPTY_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_MTXEMPTY_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_MTXEMPTY_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_mtxempty_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MTXEMPTY_AW :: INT_EVENT0_ISET_MTXEMPTY_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_mtxempty_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MTXEMPTY_AW :: INT_EVENT0_ISET_MTXEMPTY_SET) } } # [doc = "Address/Data NACK Interrupt\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_MNACK_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_MNACK_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_MNACK_SET = 1 , } impl From < INT_EVENT0_ISET_MNACK_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_MNACK_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_MNACK` writer - Address/Data NACK Interrupt"] pub type INT_EVENT0_ISET_MNACK_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_MNACK_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_MNACK_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_mnack_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MNACK_AW :: INT_EVENT0_ISET_MNACK_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_mnack_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MNACK_AW :: INT_EVENT0_ISET_MNACK_SET) } } # [doc = "START Detection Interrupt\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_MSTART_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_MSTART_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_MSTART_SET = 1 , } impl From < INT_EVENT0_ISET_MSTART_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_MSTART_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_MSTART` writer - START Detection Interrupt"] pub type INT_EVENT0_ISET_MSTART_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_MSTART_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_MSTART_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_mstart_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MSTART_AW :: INT_EVENT0_ISET_MSTART_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_mstart_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MSTART_AW :: INT_EVENT0_ISET_MSTART_SET) } } # [doc = "STOP Detection Interrupt\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_MSTOP_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_MSTOP_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_MSTOP_SET = 1 , } impl From < INT_EVENT0_ISET_MSTOP_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_MSTOP_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_MSTOP` writer - STOP Detection Interrupt"] pub type INT_EVENT0_ISET_MSTOP_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_MSTOP_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_MSTOP_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_mstop_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MSTOP_AW :: INT_EVENT0_ISET_MSTOP_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_mstop_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MSTOP_AW :: INT_EVENT0_ISET_MSTOP_SET) } } # [doc = "Arbitration Lost Interrupt\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_MARBLOST_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_MARBLOST_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_MARBLOST_SET = 1 , } impl From < INT_EVENT0_ISET_MARBLOST_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_MARBLOST_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_MARBLOST` writer - Arbitration Lost Interrupt"] pub type INT_EVENT0_ISET_MARBLOST_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_MARBLOST_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_MARBLOST_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_marblost_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MARBLOST_AW :: INT_EVENT0_ISET_MARBLOST_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_marblost_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MARBLOST_AW :: INT_EVENT0_ISET_MARBLOST_SET) } } # [doc = "DMA Done 1 on Event Channel 2\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_MDMA_DONE1_2_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_MDMA_DONE1_2_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_MDMA_DONE1_2_SET = 1 , } impl From < INT_EVENT0_ISET_MDMA_DONE1_2_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_MDMA_DONE1_2_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_MDMA_DONE1_2` writer - DMA Done 1 on Event Channel 2"] pub type INT_EVENT0_ISET_MDMA_DONE1_2_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_MDMA_DONE1_2_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_MDMA_DONE1_2_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_mdma_done1_2_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MDMA_DONE1_2_AW :: INT_EVENT0_ISET_MDMA_DONE1_2_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_mdma_done1_2_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MDMA_DONE1_2_AW :: INT_EVENT0_ISET_MDMA_DONE1_2_SET) } } # [doc = "DMA Done 1 on Event Channel 3\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_MDMA_DONE1_3_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_MDMA_DONE1_3_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_MDMA_DONE1_3_SET = 1 , } impl From < INT_EVENT0_ISET_MDMA_DONE1_3_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_MDMA_DONE1_3_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_MDMA_DONE1_3` writer - DMA Done 1 on Event Channel 3"] pub type INT_EVENT0_ISET_MDMA_DONE1_3_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_MDMA_DONE1_3_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_MDMA_DONE1_3_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_mdma_done1_3_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MDMA_DONE1_3_AW :: INT_EVENT0_ISET_MDMA_DONE1_3_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_mdma_done1_3_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MDMA_DONE1_3_AW :: INT_EVENT0_ISET_MDMA_DONE1_3_SET) } } # [doc = "Master RX Pec Error Interrupt\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_MPEC_RX_ERR_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_MPEC_RX_ERR_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_MPEC_RX_ERR_SET = 1 , } impl From < INT_EVENT0_ISET_MPEC_RX_ERR_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_MPEC_RX_ERR_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_MPEC_RX_ERR` writer - Master RX Pec Error Interrupt"] pub type INT_EVENT0_ISET_MPEC_RX_ERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_MPEC_RX_ERR_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_MPEC_RX_ERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_mpec_rx_err_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MPEC_RX_ERR_AW :: INT_EVENT0_ISET_MPEC_RX_ERR_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_mpec_rx_err_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MPEC_RX_ERR_AW :: INT_EVENT0_ISET_MPEC_RX_ERR_SET) } } # [doc = "Timeout A interrupt\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_TIMEOUTA_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_TIMEOUTA_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_TIMEOUTA_SET = 1 , } impl From < INT_EVENT0_ISET_TIMEOUTA_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_TIMEOUTA_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_TIMEOUTA` writer - Timeout A interrupt"] pub type INT_EVENT0_ISET_TIMEOUTA_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_TIMEOUTA_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_TIMEOUTA_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_timeouta_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_TIMEOUTA_AW :: INT_EVENT0_ISET_TIMEOUTA_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_timeouta_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_TIMEOUTA_AW :: INT_EVENT0_ISET_TIMEOUTA_SET) } } # [doc = "Timeout B Interrupt\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_TIMEOUTB_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_TIMEOUTB_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_TIMEOUTB_SET = 1 , } impl From < INT_EVENT0_ISET_TIMEOUTB_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_TIMEOUTB_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_TIMEOUTB` writer - Timeout B Interrupt"] pub type INT_EVENT0_ISET_TIMEOUTB_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_TIMEOUTB_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_TIMEOUTB_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_timeoutb_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_TIMEOUTB_AW :: INT_EVENT0_ISET_TIMEOUTB_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_timeoutb_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_TIMEOUTB_AW :: INT_EVENT0_ISET_TIMEOUTB_SET) } } # [doc = "Slave Receive Data Interrupt Signals that a byte has been received\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_SRXDONE_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_SRXDONE_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_SRXDONE_SET = 1 , } impl From < INT_EVENT0_ISET_SRXDONE_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_SRXDONE_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_SRXDONE` writer - Slave Receive Data Interrupt Signals that a byte has been received"] pub type INT_EVENT0_ISET_SRXDONE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_SRXDONE_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_SRXDONE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_srxdone_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_SRXDONE_AW :: INT_EVENT0_ISET_SRXDONE_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_srxdone_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_SRXDONE_AW :: INT_EVENT0_ISET_SRXDONE_SET) } } # [doc = "Slave Transmit Transaction completed Interrupt\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_STXDONE_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_STXDONE_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_STXDONE_SET = 1 , } impl From < INT_EVENT0_ISET_STXDONE_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_STXDONE_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_STXDONE` writer - Slave Transmit Transaction completed Interrupt"] pub type INT_EVENT0_ISET_STXDONE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_STXDONE_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_STXDONE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_stxdone_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_STXDONE_AW :: INT_EVENT0_ISET_STXDONE_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_stxdone_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_STXDONE_AW :: INT_EVENT0_ISET_STXDONE_SET) } } # [doc = "Slave Receive FIFO Trigger\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_SRXFIFOTRG_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_SRXFIFOTRG_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_SRXFIFOTRG_SET = 1 , } impl From < INT_EVENT0_ISET_SRXFIFOTRG_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_SRXFIFOTRG_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_SRXFIFOTRG` writer - Slave Receive FIFO Trigger"] pub type INT_EVENT0_ISET_SRXFIFOTRG_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_SRXFIFOTRG_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_SRXFIFOTRG_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_srxfifotrg_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_SRXFIFOTRG_AW :: INT_EVENT0_ISET_SRXFIFOTRG_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_srxfifotrg_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_SRXFIFOTRG_AW :: INT_EVENT0_ISET_SRXFIFOTRG_SET) } } # [doc = "Slave Transmit FIFO Trigger\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_STXFIFOTRG_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_STXFIFOTRG_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_STXFIFOTRG_SET = 1 , } impl From < INT_EVENT0_ISET_STXFIFOTRG_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_STXFIFOTRG_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_STXFIFOTRG` writer - Slave Transmit FIFO Trigger"] pub type INT_EVENT0_ISET_STXFIFOTRG_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_STXFIFOTRG_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_STXFIFOTRG_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_stxfifotrg_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_STXFIFOTRG_AW :: INT_EVENT0_ISET_STXFIFOTRG_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_stxfifotrg_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_STXFIFOTRG_AW :: INT_EVENT0_ISET_STXFIFOTRG_SET) } } # [doc = "RXFIFO full event. This interrupt is set if an RX FIFO is full.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_SRXFIFOFULL_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_SRXFIFOFULL_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_SRXFIFOFULL_SET = 1 , } impl From < INT_EVENT0_ISET_SRXFIFOFULL_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_SRXFIFOFULL_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_SRXFIFOFULL` writer - RXFIFO full event. This interrupt is set if an RX FIFO is full."] pub type INT_EVENT0_ISET_SRXFIFOFULL_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_SRXFIFOFULL_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_SRXFIFOFULL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_srxfifofull_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_SRXFIFOFULL_AW :: INT_EVENT0_ISET_SRXFIFOFULL_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_srxfifofull_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_SRXFIFOFULL_AW :: INT_EVENT0_ISET_SRXFIFOFULL_SET) } } # [doc = "Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_STXEMPTY_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_STXEMPTY_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_STXEMPTY_SET = 1 , } impl From < INT_EVENT0_ISET_STXEMPTY_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_STXEMPTY_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_STXEMPTY` writer - Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode."] pub type INT_EVENT0_ISET_STXEMPTY_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_STXEMPTY_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_STXEMPTY_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_stxempty_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_STXEMPTY_AW :: INT_EVENT0_ISET_STXEMPTY_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_stxempty_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_STXEMPTY_AW :: INT_EVENT0_ISET_STXEMPTY_SET) } } # [doc = "Start Condition Interrupt\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_SSTART_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_SSTART_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_SSTART_SET = 1 , } impl From < INT_EVENT0_ISET_SSTART_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_SSTART_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_SSTART` writer - Start Condition Interrupt"] pub type INT_EVENT0_ISET_SSTART_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_SSTART_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_SSTART_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_sstart_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_SSTART_AW :: INT_EVENT0_ISET_SSTART_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_sstart_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_SSTART_AW :: INT_EVENT0_ISET_SSTART_SET) } } # [doc = "Stop Condition Interrupt\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_SSTOP_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_SSTOP_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_SSTOP_SET = 1 , } impl From < INT_EVENT0_ISET_SSTOP_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_SSTOP_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_SSTOP` writer - Stop Condition Interrupt"] pub type INT_EVENT0_ISET_SSTOP_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_SSTOP_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_SSTOP_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_sstop_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_SSTOP_AW :: INT_EVENT0_ISET_SSTOP_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_sstop_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_SSTOP_AW :: INT_EVENT0_ISET_SSTOP_SET) } } # [doc = "General Call Interrupt\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_SGENCALL_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_SGENCALL_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_SGENCALL_SET = 1 , } impl From < INT_EVENT0_ISET_SGENCALL_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_SGENCALL_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_SGENCALL` writer - General Call Interrupt"] pub type INT_EVENT0_ISET_SGENCALL_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_SGENCALL_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_SGENCALL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_sgencall_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_SGENCALL_AW :: INT_EVENT0_ISET_SGENCALL_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_sgencall_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_SGENCALL_AW :: INT_EVENT0_ISET_SGENCALL_SET) } } # [doc = "DMA Done 1 on Event Channel 2\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_SDMA_DONE1_2_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_SDMA_DONE1_2_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_SDMA_DONE1_2_SET = 1 , } impl From < INT_EVENT0_ISET_SDMA_DONE1_2_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_SDMA_DONE1_2_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_SDMA_DONE1_2` writer - DMA Done 1 on Event Channel 2"] pub type INT_EVENT0_ISET_SDMA_DONE1_2_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_SDMA_DONE1_2_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_SDMA_DONE1_2_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_sdma_done1_2_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_SDMA_DONE1_2_AW :: INT_EVENT0_ISET_SDMA_DONE1_2_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_sdma_done1_2_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_SDMA_DONE1_2_AW :: INT_EVENT0_ISET_SDMA_DONE1_2_SET) } } # [doc = "DMA Done 1 on Event Channel 3\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_SDMA_DONE1_3_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_SDMA_DONE1_3_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_SDMA_DONE1_3_SET = 1 , } impl From < INT_EVENT0_ISET_SDMA_DONE1_3_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_SDMA_DONE1_3_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_SDMA_DONE1_3` writer - DMA Done 1 on Event Channel 3"] pub type INT_EVENT0_ISET_SDMA_DONE1_3_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_SDMA_DONE1_3_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_SDMA_DONE1_3_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_sdma_done1_3_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_SDMA_DONE1_3_AW :: INT_EVENT0_ISET_SDMA_DONE1_3_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_sdma_done1_3_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_SDMA_DONE1_3_AW :: INT_EVENT0_ISET_SDMA_DONE1_3_SET) } } # [doc = "Slave RX Pec Error Interrupt\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_SPEC_RX_ERR_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_SPEC_RX_ERR_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_SPEC_RX_ERR_SET = 1 , } impl From < INT_EVENT0_ISET_SPEC_RX_ERR_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_SPEC_RX_ERR_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_SPEC_RX_ERR` writer - Slave RX Pec Error Interrupt"] pub type INT_EVENT0_ISET_SPEC_RX_ERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_SPEC_RX_ERR_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_SPEC_RX_ERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_spec_rx_err_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_SPEC_RX_ERR_AW :: INT_EVENT0_ISET_SPEC_RX_ERR_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_spec_rx_err_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_SPEC_RX_ERR_AW :: INT_EVENT0_ISET_SPEC_RX_ERR_SET) } } # [doc = "Slave TX FIFO underflow\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_STX_UNFL_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_STX_UNFL_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_STX_UNFL_SET = 1 , } impl From < INT_EVENT0_ISET_STX_UNFL_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_STX_UNFL_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_STX_UNFL` writer - Slave TX FIFO underflow"] pub type INT_EVENT0_ISET_STX_UNFL_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_STX_UNFL_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_STX_UNFL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_stx_unfl_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_STX_UNFL_AW :: INT_EVENT0_ISET_STX_UNFL_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_stx_unfl_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_STX_UNFL_AW :: INT_EVENT0_ISET_STX_UNFL_SET) } } # [doc = "Slave RX FIFO overflow\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_SRX_OVFL_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_SRX_OVFL_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_SRX_OVFL_SET = 1 , } impl From < INT_EVENT0_ISET_SRX_OVFL_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_SRX_OVFL_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_SRX_OVFL` writer - Slave RX FIFO overflow"] pub type INT_EVENT0_ISET_SRX_OVFL_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_SRX_OVFL_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_SRX_OVFL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_srx_ovfl_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_SRX_OVFL_AW :: INT_EVENT0_ISET_SRX_OVFL_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_srx_ovfl_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_SRX_OVFL_AW :: INT_EVENT0_ISET_SRX_OVFL_SET) } } # [doc = "Slave Arbitration Lost\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_SARBLOST_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_SARBLOST_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_SARBLOST_SET = 1 , } impl From < INT_EVENT0_ISET_SARBLOST_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_SARBLOST_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_SARBLOST` writer - Slave Arbitration Lost"] pub type INT_EVENT0_ISET_SARBLOST_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_SARBLOST_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_SARBLOST_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_sarblost_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_SARBLOST_AW :: INT_EVENT0_ISET_SARBLOST_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_sarblost_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_SARBLOST_AW :: INT_EVENT0_ISET_SARBLOST_SET) } } # [doc = "Interrupt overflow\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_INTR_OVFL_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_INTR_OVFL_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_INTR_OVFL_SET = 1 , } impl From < INT_EVENT0_ISET_INTR_OVFL_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_INTR_OVFL_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_INTR_OVFL` writer - Interrupt overflow"] pub type INT_EVENT0_ISET_INTR_OVFL_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_INTR_OVFL_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_INTR_OVFL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_intr_ovfl_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_INTR_OVFL_AW :: INT_EVENT0_ISET_INTR_OVFL_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_intr_ovfl_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_INTR_OVFL_AW :: INT_EVENT0_ISET_INTR_OVFL_SET) } } impl W { # [doc = "Bit 0 - Master Receive Data Interrupt Signals that a byte has been received"] # [inline (always)] # [must_use] pub fn int_event0_iset_mrxdone (& mut self) -> INT_EVENT0_ISET_MRXDONE_W < INT_EVENT0_ISET_SPEC , 0 > { INT_EVENT0_ISET_MRXDONE_W :: new (self) } # [doc = "Bit 1 - Master Transmit Transaction completed Interrupt"] # [inline (always)] # [must_use] pub fn int_event0_iset_mtxdone (& mut self) -> INT_EVENT0_ISET_MTXDONE_W < INT_EVENT0_ISET_SPEC , 1 > { INT_EVENT0_ISET_MTXDONE_W :: new (self) } # [doc = "Bit 2 - Master Receive FIFO Trigger Trigger when RX FIFO contains &gt;= defined bytes"] # [inline (always)] # [must_use] pub fn int_event0_iset_mrxfifotrg (& mut self) -> INT_EVENT0_ISET_MRXFIFOTRG_W < INT_EVENT0_ISET_SPEC , 2 > { INT_EVENT0_ISET_MRXFIFOTRG_W :: new (self) } # [doc = "Bit 3 - Master Transmit FIFO Trigger Trigger when Transmit FIFO contains &lt;= defined bytes"] # [inline (always)] # [must_use] pub fn int_event0_iset_mtxfifotrg (& mut self) -> INT_EVENT0_ISET_MTXFIFOTRG_W < INT_EVENT0_ISET_SPEC , 3 > { INT_EVENT0_ISET_MTXFIFOTRG_W :: new (self) } # [doc = "Bit 4 - RXFIFO full event."] # [inline (always)] # [must_use] pub fn int_event0_iset_mrxfifofull (& mut self) -> INT_EVENT0_ISET_MRXFIFOFULL_W <'_, INT_EVENT0_ISET_SPEC , 4 > { INT_EVENT0_ISET_MRXFIFOFULL_W :: new (self) } # [doc = "Bit 5 - Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode."] # [inline (always)] # [must_use] pub fn int_event0_iset_mtxempty (& mut self) -> INT_EVENT0_ISET_MTXEMPTY_W < INT_EVENT0_ISET_SPEC , 5 > { INT_EVENT0_ISET_MTXEMPTY_W :: new (self) } # [doc = "Bit 7 - Address/Data NACK Interrupt"] # [inline (always)] # [must_use] pub fn int_event0_iset_mnack (& mut self) -> INT_EVENT0_ISET_MNACK_W < INT_EVENT0_ISET_SPEC , 7 > { INT_EVENT0_ISET_MNACK_W :: new (self) } # [doc = "Bit 8 - START Detection Interrupt"] # [inline (always)] # [must_use] pub fn int_event0_iset_mstart (& mut self) -> INT_EVENT0_ISET_MSTART_W < INT_EVENT0_ISET_SPEC , 8 > { INT_EVENT0_ISET_MSTART_W :: new (self) } # [doc = "Bit 9 - STOP Detection Interrupt"] # [inline (always)] # [must_use] pub fn int_event0_iset_mstop (& mut self) -> INT_EVENT0_ISET_MSTOP_W < INT_EVENT0_ISET_SPEC , 9 > { INT_EVENT0_ISET_MSTOP_W :: new (self) } # [doc = "Bit 10 - Arbitration Lost Interrupt"] # [inline (always)] # [must_use] pub fn int_event0_iset_marblost (& mut self) -> INT_EVENT0_ISET_MARBLOST_W < INT_EVENT0_ISET_SPEC , 10 > { INT_EVENT0_ISET_MARBLOST_W :: new (self) } # [doc = "Bit 11 - DMA Done 1 on Event Channel 2"] # [inline (always)] # [must_use] pub fn int_event0_iset_mdma_done1_2 (& mut self) -> INT_EVENT0_ISET_MDMA_DONE1_2_W < INT_EVENT0_ISET_SPEC , 11 > { INT_EVENT0_ISET_MDMA_DONE1_2_W :: new (self) } # [doc = "Bit 12 - DMA Done 1 on Event Channel 3"] # [inline (always)] # [must_use] pub fn int_event0_iset_mdma_done1_3 (& mut self) -> INT_EVENT0_ISET_MDMA_DONE1_3_W < INT_EVENT0_ISET_SPEC , 12 > { INT_EVENT0_ISET_MDMA_DONE1_3_W :: new (self) } # [doc = "Bit 13 - Master RX Pec Error Interrupt"] # [inline (always)] # [must_use] pub fn int_event0_iset_mpec_rx_err (& mut self) -> INT_EVENT0_ISET_MPEC_RX_ERR_W < INT_EVENT0_ISET_SPEC , 13 > { INT_EVENT0_ISET_MPEC_RX_ERR_W :: new (self) } # [doc = "Bit 14 - Timeout A interrupt"] # [inline (always)] # [must_use] pub fn int_event0_iset_timeouta (& mut self) -> INT_EVENT0_ISET_TIMEOUTA_W < INT_EVENT0_ISET_SPEC , 14 > { INT_EVENT0_ISET_TIMEOUTA_W :: new (self) } # [doc = "Bit 15 - Timeout B Interrupt"] # [inline (always)] # [must_use] pub fn int_event0_iset_timeoutb (& mut self) -> INT_EVENT0_ISET_TIMEOUTB_W < INT_EVENT0_ISET_SPEC , 15 > { INT_EVENT0_ISET_TIMEOUTB_W :: new (self) } # [doc = "Bit 16 - Slave Receive Data Interrupt Signals that a byte has been received"] # [inline (always)] # [must_use] pub fn int_event0_iset_srxdone (& mut self) -> INT_EVENT0_ISET_SRXDONE_W < INT_EVENT0_ISET_SPEC , 16 > { INT_EVENT0_ISET_SRXDONE_W :: new (self) } # [doc = "Bit 17 - Slave Transmit Transaction completed Interrupt"] # [inline (always)] # [must_use] pub fn int_event0_iset_stxdone (& mut self) -> INT_EVENT0_ISET_STXDONE_W < INT_EVENT0_ISET_SPEC , 17 > { INT_EVENT0_ISET_STXDONE_W :: new (self) } # [doc = "Bit 18 - Slave Receive FIFO Trigger"] # [inline (always)] # [must_use] pub fn int_event0_iset_srxfifotrg (& mut self) -> INT_EVENT0_ISET_SRXFIFOTRG_W < INT_EVENT0_ISET_SPEC , 18 > { INT_EVENT0_ISET_SRXFIFOTRG_W :: new (self) } # [doc = "Bit 19 - Slave Transmit FIFO Trigger"] # [inline (always)] # [must_use] pub fn int_event0_iset_stxfifotrg (& mut self) -> INT_EVENT0_ISET_STXFIFOTRG_W < INT_EVENT0_ISET_SPEC , 19 > { INT_EVENT0_ISET_STXFIFOTRG_W :: new (self) } # [doc = "Bit 20 - RXFIFO full event. This interrupt is set if an RX FIFO is full."] # [inline (always)] # [must_use] pub fn int_event0_iset_srxfifofull (& mut self) -> INT_EVENT0_ISET_SRXFIFOFULL_W < INT_EVENT0_ISET_SPEC , 20 > { INT_EVENT0_ISET_SRXFIFOFULL_W :: new (self) } # [doc = "Bit 21 - Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode."] # [inline (always)] # [must_use] pub fn int_event0_iset_stxempty (& mut self) -> INT_EVENT0_ISET_STXEMPTY_W < INT_EVENT0_ISET_SPEC , 21 > { INT_EVENT0_ISET_STXEMPTY_W :: new (self) } # [doc = "Bit 22 - Start Condition Interrupt"] # [inline (always)] # [must_use] pub fn int_event0_iset_sstart (& mut self) -> INT_EVENT0_ISET_SSTART_W < INT_EVENT0_ISET_SPEC , 22 > { INT_EVENT0_ISET_SSTART_W :: new (self) } # [doc = "Bit 23 - Stop Condition Interrupt"] # [inline (always)] # [must_use] pub fn int_event0_iset_sstop (& mut self) -> INT_EVENT0_ISET_SSTOP_W < INT_EVENT0_ISET_SPEC , 23 > { INT_EVENT0_ISET_SSTOP_W :: new (self) } # [doc = "Bit 24 - General Call Interrupt"] # [inline (always)] # [must_use] pub fn int_event0_iset_sgencall (& mut self) -> INT_EVENT0_ISET_SGENCALL_W < INT_EVENT0_ISET_SPEC , 24 > { INT_EVENT0_ISET_SGENCALL_W :: new (self) } # [doc = "Bit 25 - DMA Done 1 on Event Channel 2"] # [inline (always)] # [must_use] pub fn int_event0_iset_sdma_done1_2 (& mut self) -> INT_EVENT0_ISET_SDMA_DONE1_2_W < INT_EVENT0_ISET_SPEC , 25 > { INT_EVENT0_ISET_SDMA_DONE1_2_W :: new (self) } # [doc = "Bit 26 - DMA Done 1 on Event Channel 3"] # [inline (always)] # [must_use] pub fn int_event0_iset_sdma_done1_3 (& mut self) -> INT_EVENT0_ISET_SDMA_DONE1_3_W < INT_EVENT0_ISET_SPEC , 26 > { INT_EVENT0_ISET_SDMA_DONE1_3_W :: new (self) } # [doc = "Bit 27 - Slave RX Pec Error Interrupt"] # [inline (always)] # [must_use] pub fn int_event0_iset_spec_rx_err (& mut self) -> INT_EVENT0_ISET_SPEC_RX_ERR_W < INT_EVENT0_ISET_SPEC , 27 > { INT_EVENT0_ISET_SPEC_RX_ERR_W :: new (self) } # [doc = "Bit 28 - Slave TX FIFO underflow"] # [inline (always)] # [must_use] pub fn int_event0_iset_stx_unfl (& mut self) -> INT_EVENT0_ISET_STX_UNFL_W < INT_EVENT0_ISET_SPEC , 28 > { INT_EVENT0_ISET_STX_UNFL_W :: new (self) } # [doc = "Bit 29 - Slave RX FIFO overflow"] # [inline (always)] # [must_use] pub fn int_event0_iset_srx_ovfl (& mut self) -> INT_EVENT0_ISET_SRX_OVFL_W < INT_EVENT0_ISET_SPEC , 29 > { INT_EVENT0_ISET_SRX_OVFL_W :: new (self) } # [doc = "Bit 30 - Slave Arbitration Lost"] # [inline (always)] # [must_use] pub fn int_event0_iset_sarblost (& mut self) -> INT_EVENT0_ISET_SARBLOST_W < INT_EVENT0_ISET_SPEC , 30 > { INT_EVENT0_ISET_SARBLOST_W :: new (self) } # [doc = "Bit 31 - Interrupt overflow"] # [inline (always)] # [must_use] pub fn int_event0_iset_intr_ovfl (& mut self) -> INT_EVENT0_ISET_INTR_OVFL_W < INT_EVENT0_ISET_SPEC , 31 > { INT_EVENT0_ISET_INTR_OVFL_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Interrupt set\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_event0_iset::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct INT_EVENT0_ISET_SPEC ; impl crate :: RegisterSpec for INT_EVENT0_ISET_SPEC { type Ux = u32 ; } # [doc = "`write(|w| ..)` method takes [`int_event0_iset::W`](W) writer structure"] impl crate :: Writable for INT_EVENT0_ISET_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets INT_EVENT0_ISET to value 0"] impl crate :: Resettable for INT_EVENT0_ISET_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/i2c1/int_event2_imask.rs:1:10248 [INFO] [stdout] | [INFO] [stdout] 1 | ..._mtxfifotrg (& mut self) -> INT_EVENT2_IMASK_MTXFIFOTRG_W < INT_EVENT2_IMASK_SPEC , 1 > { INT_EVENT2_IMASK_MTXFIFOTRG_W :: new (self) ... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `INT_EVENT2_IMASK` reader"] pub type R = crate :: R < INT_EVENT2_IMASK_SPEC > ; # [doc = "Register `INT_EVENT2_IMASK` writer"] pub type W = crate :: W < INT_EVENT2_IMASK_SPEC > ; # [doc = "Field `INT_EVENT2_IMASK_MRXFIFOTRG` reader - Master Receive FIFO Trigger Trigger when RX FIFO contains &gt;= defined bytes"] pub type INT_EVENT2_IMASK_MRXFIFOTRG_R = crate :: BitReader < INT_EVENT2_IMASK_MRXFIFOTRG_A > ; # [doc = "Master Receive FIFO Trigger Trigger when RX FIFO contains &gt;= defined bytes\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT2_IMASK_MRXFIFOTRG_A { # [doc = "0: CLR"] INT_EVENT2_IMASK_MRXFIFOTRG_CLR = 0 , # [doc = "1: SET"] INT_EVENT2_IMASK_MRXFIFOTRG_SET = 1 , } impl From < INT_EVENT2_IMASK_MRXFIFOTRG_A > for bool { # [inline (always)] fn from (variant : INT_EVENT2_IMASK_MRXFIFOTRG_A) -> Self { variant as u8 != 0 } } impl INT_EVENT2_IMASK_MRXFIFOTRG_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT2_IMASK_MRXFIFOTRG_A { match self . bits { false => INT_EVENT2_IMASK_MRXFIFOTRG_A :: INT_EVENT2_IMASK_MRXFIFOTRG_CLR , true => INT_EVENT2_IMASK_MRXFIFOTRG_A :: INT_EVENT2_IMASK_MRXFIFOTRG_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event2_imask_mrxfifotrg_clr (& self) -> bool { * self == INT_EVENT2_IMASK_MRXFIFOTRG_A :: INT_EVENT2_IMASK_MRXFIFOTRG_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event2_imask_mrxfifotrg_set (& self) -> bool { * self == INT_EVENT2_IMASK_MRXFIFOTRG_A :: INT_EVENT2_IMASK_MRXFIFOTRG_SET } } # [doc = "Field `INT_EVENT2_IMASK_MRXFIFOTRG` writer - Master Receive FIFO Trigger Trigger when RX FIFO contains &gt;= defined bytes"] pub type INT_EVENT2_IMASK_MRXFIFOTRG_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT2_IMASK_MRXFIFOTRG_A > ; impl < 'a , REG , const O : u8 > INT_EVENT2_IMASK_MRXFIFOTRG_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event2_imask_mrxfifotrg_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT2_IMASK_MRXFIFOTRG_A :: INT_EVENT2_IMASK_MRXFIFOTRG_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event2_imask_mrxfifotrg_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT2_IMASK_MRXFIFOTRG_A :: INT_EVENT2_IMASK_MRXFIFOTRG_SET) } } # [doc = "Field `INT_EVENT2_IMASK_MTXFIFOTRG` reader - Master Transmit FIFO Trigger Trigger when Transmit FIFO contains &lt;= defined bytes"] pub type INT_EVENT2_IMASK_MTXFIFOTRG_R = crate :: BitReader < INT_EVENT2_IMASK_MTXFIFOTRG_A > ; # [doc = "Master Transmit FIFO Trigger Trigger when Transmit FIFO contains &lt;= defined bytes\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT2_IMASK_MTXFIFOTRG_A { # [doc = "0: CLR"] INT_EVENT2_IMASK_MTXFIFOTRG_CLR = 0 , # [doc = "1: SET"] INT_EVENT2_IMASK_MTXFIFOTRG_SET = 1 , } impl From < INT_EVENT2_IMASK_MTXFIFOTRG_A > for bool { # [inline (always)] fn from (variant : INT_EVENT2_IMASK_MTXFIFOTRG_A) -> Self { variant as u8 != 0 } } impl INT_EVENT2_IMASK_MTXFIFOTRG_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT2_IMASK_MTXFIFOTRG_A { match self . bits { false => INT_EVENT2_IMASK_MTXFIFOTRG_A :: INT_EVENT2_IMASK_MTXFIFOTRG_CLR , true => INT_EVENT2_IMASK_MTXFIFOTRG_A :: INT_EVENT2_IMASK_MTXFIFOTRG_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event2_imask_mtxfifotrg_clr (& self) -> bool { * self == INT_EVENT2_IMASK_MTXFIFOTRG_A :: INT_EVENT2_IMASK_MTXFIFOTRG_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event2_imask_mtxfifotrg_set (& self) -> bool { * self == INT_EVENT2_IMASK_MTXFIFOTRG_A :: INT_EVENT2_IMASK_MTXFIFOTRG_SET } } # [doc = "Field `INT_EVENT2_IMASK_MTXFIFOTRG` writer - Master Transmit FIFO Trigger Trigger when Transmit FIFO contains &lt;= defined bytes"] pub type INT_EVENT2_IMASK_MTXFIFOTRG_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT2_IMASK_MTXFIFOTRG_A > ; impl < 'a , REG , const O : u8 > INT_EVENT2_IMASK_MTXFIFOTRG_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event2_imask_mtxfifotrg_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT2_IMASK_MTXFIFOTRG_A :: INT_EVENT2_IMASK_MTXFIFOTRG_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event2_imask_mtxfifotrg_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT2_IMASK_MTXFIFOTRG_A :: INT_EVENT2_IMASK_MTXFIFOTRG_SET) } } # [doc = "Field `INT_EVENT2_IMASK_SRXFIFOTRG` reader - Slave Receive FIFO Trigger"] pub type INT_EVENT2_IMASK_SRXFIFOTRG_R = crate :: BitReader < INT_EVENT2_IMASK_SRXFIFOTRG_A > ; # [doc = "Slave Receive FIFO Trigger\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT2_IMASK_SRXFIFOTRG_A { # [doc = "0: CLR"] INT_EVENT2_IMASK_SRXFIFOTRG_CLR = 0 , # [doc = "1: SET"] INT_EVENT2_IMASK_SRXFIFOTRG_SET = 1 , } impl From < INT_EVENT2_IMASK_SRXFIFOTRG_A > for bool { # [inline (always)] fn from (variant : INT_EVENT2_IMASK_SRXFIFOTRG_A) -> Self { variant as u8 != 0 } } impl INT_EVENT2_IMASK_SRXFIFOTRG_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT2_IMASK_SRXFIFOTRG_A { match self . bits { false => INT_EVENT2_IMASK_SRXFIFOTRG_A :: INT_EVENT2_IMASK_SRXFIFOTRG_CLR , true => INT_EVENT2_IMASK_SRXFIFOTRG_A :: INT_EVENT2_IMASK_SRXFIFOTRG_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event2_imask_srxfifotrg_clr (& self) -> bool { * self == INT_EVENT2_IMASK_SRXFIFOTRG_A :: INT_EVENT2_IMASK_SRXFIFOTRG_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event2_imask_srxfifotrg_set (& self) -> bool { * self == INT_EVENT2_IMASK_SRXFIFOTRG_A :: INT_EVENT2_IMASK_SRXFIFOTRG_SET } } # [doc = "Field `INT_EVENT2_IMASK_SRXFIFOTRG` writer - Slave Receive FIFO Trigger"] pub type INT_EVENT2_IMASK_SRXFIFOTRG_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT2_IMASK_SRXFIFOTRG_A > ; impl < 'a , REG , const O : u8 > INT_EVENT2_IMASK_SRXFIFOTRG_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event2_imask_srxfifotrg_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT2_IMASK_SRXFIFOTRG_A :: INT_EVENT2_IMASK_SRXFIFOTRG_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event2_imask_srxfifotrg_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT2_IMASK_SRXFIFOTRG_A :: INT_EVENT2_IMASK_SRXFIFOTRG_SET) } } # [doc = "Field `INT_EVENT2_IMASK_STXFIFOTRG` reader - Slave Transmit FIFO Trigger"] pub type INT_EVENT2_IMASK_STXFIFOTRG_R = crate :: BitReader < INT_EVENT2_IMASK_STXFIFOTRG_A > ; # [doc = "Slave Transmit FIFO Trigger\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT2_IMASK_STXFIFOTRG_A { # [doc = "0: CLR"] INT_EVENT2_IMASK_STXFIFOTRG_CLR = 0 , # [doc = "1: SET"] INT_EVENT2_IMASK_STXFIFOTRG_SET = 1 , } impl From < INT_EVENT2_IMASK_STXFIFOTRG_A > for bool { # [inline (always)] fn from (variant : INT_EVENT2_IMASK_STXFIFOTRG_A) -> Self { variant as u8 != 0 } } impl INT_EVENT2_IMASK_STXFIFOTRG_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT2_IMASK_STXFIFOTRG_A { match self . bits { false => INT_EVENT2_IMASK_STXFIFOTRG_A :: INT_EVENT2_IMASK_STXFIFOTRG_CLR , true => INT_EVENT2_IMASK_STXFIFOTRG_A :: INT_EVENT2_IMASK_STXFIFOTRG_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event2_imask_stxfifotrg_clr (& self) -> bool { * self == INT_EVENT2_IMASK_STXFIFOTRG_A :: INT_EVENT2_IMASK_STXFIFOTRG_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event2_imask_stxfifotrg_set (& self) -> bool { * self == INT_EVENT2_IMASK_STXFIFOTRG_A :: INT_EVENT2_IMASK_STXFIFOTRG_SET } } # [doc = "Field `INT_EVENT2_IMASK_STXFIFOTRG` writer - Slave Transmit FIFO Trigger"] pub type INT_EVENT2_IMASK_STXFIFOTRG_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT2_IMASK_STXFIFOTRG_A > ; impl < 'a , REG , const O : u8 > INT_EVENT2_IMASK_STXFIFOTRG_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event2_imask_stxfifotrg_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT2_IMASK_STXFIFOTRG_A :: INT_EVENT2_IMASK_STXFIFOTRG_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event2_imask_stxfifotrg_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT2_IMASK_STXFIFOTRG_A :: INT_EVENT2_IMASK_STXFIFOTRG_SET) } } impl R { # [doc = "Bit 0 - Master Receive FIFO Trigger Trigger when RX FIFO contains &gt;= defined bytes"] # [inline (always)] pub fn int_event2_imask_mrxfifotrg (& self) -> INT_EVENT2_IMASK_MRXFIFOTRG_R { INT_EVENT2_IMASK_MRXFIFOTRG_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - Master Transmit FIFO Trigger Trigger when Transmit FIFO contains &lt;= defined bytes"] # [inline (always)] pub fn int_event2_imask_mtxfifotrg (& self) -> INT_EVENT2_IMASK_MTXFIFOTRG_R { INT_EVENT2_IMASK_MTXFIFOTRG_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - Slave Receive FIFO Trigger"] # [inline (always)] pub fn int_event2_imask_srxfifotrg (& self) -> INT_EVENT2_IMASK_SRXFIFOTRG_R { INT_EVENT2_IMASK_SRXFIFOTRG_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - Slave Transmit FIFO Trigger"] # [inline (always)] pub fn int_event2_imask_stxfifotrg (& self) -> INT_EVENT2_IMASK_STXFIFOTRG_R { INT_EVENT2_IMASK_STXFIFOTRG_R :: new (((self . bits >> 3) & 1) != 0) } } impl W { # [doc = "Bit 0 - Master Receive FIFO Trigger Trigger when RX FIFO contains &gt;= defined bytes"] # [inline (always)] # [must_use] pub fn int_event2_imask_mrxfifotrg (& mut self) -> INT_EVENT2_IMASK_MRXFIFOTRG_W < INT_EVENT2_IMASK_SPEC , 0 > { INT_EVENT2_IMASK_MRXFIFOTRG_W :: new (self) } # [doc = "Bit 1 - Master Transmit FIFO Trigger Trigger when Transmit FIFO contains &lt;= defined bytes"] # [inline (always)] # [must_use] pub fn int_event2_imask_mtxfifotrg (& mut self) -> INT_EVENT2_IMASK_MTXFIFOTRG_W <'_, INT_EVENT2_IMASK_SPEC , 1 > { INT_EVENT2_IMASK_MTXFIFOTRG_W :: new (self) } # [doc = "Bit 2 - Slave Receive FIFO Trigger"] # [inline (always)] # [must_use] pub fn int_event2_imask_srxfifotrg (& mut self) -> INT_EVENT2_IMASK_SRXFIFOTRG_W < INT_EVENT2_IMASK_SPEC , 2 > { INT_EVENT2_IMASK_SRXFIFOTRG_W :: new (self) } # [doc = "Bit 3 - Slave Transmit FIFO Trigger"] # [inline (always)] # [must_use] pub fn int_event2_imask_stxfifotrg (& mut self) -> INT_EVENT2_IMASK_STXFIFOTRG_W < INT_EVENT2_IMASK_SPEC , 3 > { INT_EVENT2_IMASK_STXFIFOTRG_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Interrupt mask\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_event2_imask::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_event2_imask::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct INT_EVENT2_IMASK_SPEC ; impl crate :: RegisterSpec for INT_EVENT2_IMASK_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`int_event2_imask::R`](R) reader structure"] impl crate :: Readable for INT_EVENT2_IMASK_SPEC { } # [doc = "`write(|w| ..)` method takes [`int_event2_imask::W`](W) writer structure"] impl crate :: Writable for INT_EVENT2_IMASK_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets INT_EVENT2_IMASK to value 0"] impl crate :: Resettable for INT_EVENT2_IMASK_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/gpioa/fpub_0.rs:1:2067 [INFO] [stdout] | [INFO] [stdout] 1 | ...e] pub fn fpub_0_chanid (& mut self) -> FPUB_0_CHANID_W < FPUB_0_SPEC , 0 > { FPUB_0_CHANID_W :: new (self) } # [doc = r" Writes raw b... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `FPUB_0` reader"] pub type R = crate :: R < FPUB_0_SPEC > ; # [doc = "Register `FPUB_0` writer"] pub type W = crate :: W < FPUB_0_SPEC > ; # [doc = "Field `FPUB_0_CHANID` reader - 0 = disconnected. 1-15 = connected to channelID = CHANID."] pub type FPUB_0_CHANID_R = crate :: FieldReader < FPUB_0_CHANID_A > ; # [doc = "0 = disconnected. 1-15 = connected to channelID = CHANID.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum FPUB_0_CHANID_A { # [doc = "0: UNCONNECTED"] FPUB_0_CHANID_UNCONNECTED = 0 , } impl From < FPUB_0_CHANID_A > for u8 { # [inline (always)] fn from (variant : FPUB_0_CHANID_A) -> Self { variant as _ } } impl crate :: FieldSpec for FPUB_0_CHANID_A { type Ux = u8 ; } impl FPUB_0_CHANID_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < FPUB_0_CHANID_A > { match self . bits { 0 => Some (FPUB_0_CHANID_A :: FPUB_0_CHANID_UNCONNECTED) , _ => None , } } # [doc = "UNCONNECTED"] # [inline (always)] pub fn is_fpub_0_chanid_unconnected (& self) -> bool { * self == FPUB_0_CHANID_A :: FPUB_0_CHANID_UNCONNECTED } } # [doc = "Field `FPUB_0_CHANID` writer - 0 = disconnected. 1-15 = connected to channelID = CHANID."] pub type FPUB_0_CHANID_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 2 , O , FPUB_0_CHANID_A > ; impl < 'a , REG , const O : u8 > FPUB_0_CHANID_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "UNCONNECTED"] # [inline (always)] pub fn fpub_0_chanid_unconnected (self) -> & 'a mut crate :: W < REG > { self . variant (FPUB_0_CHANID_A :: FPUB_0_CHANID_UNCONNECTED) } } impl R { # [doc = "Bits 0:1 - 0 = disconnected. 1-15 = connected to channelID = CHANID."] # [inline (always)] pub fn fpub_0_chanid (& self) -> FPUB_0_CHANID_R { FPUB_0_CHANID_R :: new ((self . bits & 3) as u8) } } impl W { # [doc = "Bits 0:1 - 0 = disconnected. 1-15 = connected to channelID = CHANID."] # [inline (always)] # [must_use] pub fn fpub_0_chanid (& mut self) -> FPUB_0_CHANID_W <'_, FPUB_0_SPEC , 0 > { FPUB_0_CHANID_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Publisher Port 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fpub_0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fpub_0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct FPUB_0_SPEC ; impl crate :: RegisterSpec for FPUB_0_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`fpub_0::R`](R) reader structure"] impl crate :: Readable for FPUB_0_SPEC { } # [doc = "`write(|w| ..)` method takes [`fpub_0::W`](W) writer structure"] impl crate :: Writable for FPUB_0_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets FPUB_0 to value 0"] impl crate :: Resettable for FPUB_0_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/i2c1/timeout_ctl.rs:1:8127 [INFO] [stdout] | [INFO] [stdout] 1 | ...meout_ctl_tcntaen (& mut self) -> TIMEOUT_CTL_TCNTAEN_W < TIMEOUT_CTL_SPEC , 15 > { TIMEOUT_CTL_TCNTAEN_W :: new (self) } # [doc = "Bi... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `TIMEOUT_CTL` reader"] pub type R = crate :: R < TIMEOUT_CTL_SPEC > ; # [doc = "Register `TIMEOUT_CTL` writer"] pub type W = crate :: W < TIMEOUT_CTL_SPEC > ; # [doc = "Field `TIMEOUT_CTL_TCNTLA` reader - Timeout counter A load value Counter A is used for SCL low detection. This field contains the upper 8 bits of a 12-bit pre-load value for the Timeout A count. NOTE: The value of CNTLA must be greater than 1h. Each count is equal to 520 times the timeout period of functional clock. For example, with 8MHz functional clock and a 100KHz operating I2C clock, one timeout period will be equal to (1 / 8MHz) * 520 or 65 us."] pub type TIMEOUT_CTL_TCNTLA_R = crate :: FieldReader ; # [doc = "Field `TIMEOUT_CTL_TCNTLA` writer - Timeout counter A load value Counter A is used for SCL low detection. This field contains the upper 8 bits of a 12-bit pre-load value for the Timeout A count. NOTE: The value of CNTLA must be greater than 1h. Each count is equal to 520 times the timeout period of functional clock. For example, with 8MHz functional clock and a 100KHz operating I2C clock, one timeout period will be equal to (1 / 8MHz) * 520 or 65 us."] pub type TIMEOUT_CTL_TCNTLA_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 8 , O > ; # [doc = "Field `TIMEOUT_CTL_TCNTAEN` reader - Timeout Counter A Enable"] pub type TIMEOUT_CTL_TCNTAEN_R = crate :: BitReader < TIMEOUT_CTL_TCNTAEN_A > ; # [doc = "Timeout Counter A Enable\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum TIMEOUT_CTL_TCNTAEN_A { # [doc = "0: DISABLE"] TIMEOUT_CTL_TCNTAEN_DISABLE = 0 , # [doc = "1: ENABLE"] TIMEOUT_CTL_TCNTAEN_ENABLE = 1 , } impl From < TIMEOUT_CTL_TCNTAEN_A > for bool { # [inline (always)] fn from (variant : TIMEOUT_CTL_TCNTAEN_A) -> Self { variant as u8 != 0 } } impl TIMEOUT_CTL_TCNTAEN_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> TIMEOUT_CTL_TCNTAEN_A { match self . bits { false => TIMEOUT_CTL_TCNTAEN_A :: TIMEOUT_CTL_TCNTAEN_DISABLE , true => TIMEOUT_CTL_TCNTAEN_A :: TIMEOUT_CTL_TCNTAEN_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_timeout_ctl_tcntaen_disable (& self) -> bool { * self == TIMEOUT_CTL_TCNTAEN_A :: TIMEOUT_CTL_TCNTAEN_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_timeout_ctl_tcntaen_enable (& self) -> bool { * self == TIMEOUT_CTL_TCNTAEN_A :: TIMEOUT_CTL_TCNTAEN_ENABLE } } # [doc = "Field `TIMEOUT_CTL_TCNTAEN` writer - Timeout Counter A Enable"] pub type TIMEOUT_CTL_TCNTAEN_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , TIMEOUT_CTL_TCNTAEN_A > ; impl < 'a , REG , const O : u8 > TIMEOUT_CTL_TCNTAEN_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn timeout_ctl_tcntaen_disable (self) -> & 'a mut crate :: W < REG > { self . variant (TIMEOUT_CTL_TCNTAEN_A :: TIMEOUT_CTL_TCNTAEN_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn timeout_ctl_tcntaen_enable (self) -> & 'a mut crate :: W < REG > { self . variant (TIMEOUT_CTL_TCNTAEN_A :: TIMEOUT_CTL_TCNTAEN_ENABLE) } } # [doc = "Field `TIMEOUT_CTL_TCNTLB` reader - Timeout Count B Load: Counter B is used for SCL High Detection. This field contains the upper 8 bits of a 12-bit pre-load value for the Timeout B count. NOTE: The value of CNTLB must be greater than 1h. Each count is equal to 1* clock period. For example, with 10MHz functional clock one timeout period will be equal to1*100ns."] pub type TIMEOUT_CTL_TCNTLB_R = crate :: FieldReader ; # [doc = "Field `TIMEOUT_CTL_TCNTLB` writer - Timeout Count B Load: Counter B is used for SCL High Detection. This field contains the upper 8 bits of a 12-bit pre-load value for the Timeout B count. NOTE: The value of CNTLB must be greater than 1h. Each count is equal to 1* clock period. For example, with 10MHz functional clock one timeout period will be equal to1*100ns."] pub type TIMEOUT_CTL_TCNTLB_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 8 , O > ; # [doc = "Field `TIMEOUT_CTL_TCNTBEN` reader - Timeout Counter B Enable"] pub type TIMEOUT_CTL_TCNTBEN_R = crate :: BitReader < TIMEOUT_CTL_TCNTBEN_A > ; # [doc = "Timeout Counter B Enable\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum TIMEOUT_CTL_TCNTBEN_A { # [doc = "0: DISABLE"] TIMEOUT_CTL_TCNTBEN_DISABLE = 0 , # [doc = "1: ENABLE"] TIMEOUT_CTL_TCNTBEN_ENABLE = 1 , } impl From < TIMEOUT_CTL_TCNTBEN_A > for bool { # [inline (always)] fn from (variant : TIMEOUT_CTL_TCNTBEN_A) -> Self { variant as u8 != 0 } } impl TIMEOUT_CTL_TCNTBEN_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> TIMEOUT_CTL_TCNTBEN_A { match self . bits { false => TIMEOUT_CTL_TCNTBEN_A :: TIMEOUT_CTL_TCNTBEN_DISABLE , true => TIMEOUT_CTL_TCNTBEN_A :: TIMEOUT_CTL_TCNTBEN_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_timeout_ctl_tcntben_disable (& self) -> bool { * self == TIMEOUT_CTL_TCNTBEN_A :: TIMEOUT_CTL_TCNTBEN_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_timeout_ctl_tcntben_enable (& self) -> bool { * self == TIMEOUT_CTL_TCNTBEN_A :: TIMEOUT_CTL_TCNTBEN_ENABLE } } # [doc = "Field `TIMEOUT_CTL_TCNTBEN` writer - Timeout Counter B Enable"] pub type TIMEOUT_CTL_TCNTBEN_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , TIMEOUT_CTL_TCNTBEN_A > ; impl < 'a , REG , const O : u8 > TIMEOUT_CTL_TCNTBEN_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn timeout_ctl_tcntben_disable (self) -> & 'a mut crate :: W < REG > { self . variant (TIMEOUT_CTL_TCNTBEN_A :: TIMEOUT_CTL_TCNTBEN_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn timeout_ctl_tcntben_enable (self) -> & 'a mut crate :: W < REG > { self . variant (TIMEOUT_CTL_TCNTBEN_A :: TIMEOUT_CTL_TCNTBEN_ENABLE) } } impl R { # [doc = "Bits 0:7 - Timeout counter A load value Counter A is used for SCL low detection. This field contains the upper 8 bits of a 12-bit pre-load value for the Timeout A count. NOTE: The value of CNTLA must be greater than 1h. Each count is equal to 520 times the timeout period of functional clock. For example, with 8MHz functional clock and a 100KHz operating I2C clock, one timeout period will be equal to (1 / 8MHz) * 520 or 65 us."] # [inline (always)] pub fn timeout_ctl_tcntla (& self) -> TIMEOUT_CTL_TCNTLA_R { TIMEOUT_CTL_TCNTLA_R :: new ((self . bits & 0xff) as u8) } # [doc = "Bit 15 - Timeout Counter A Enable"] # [inline (always)] pub fn timeout_ctl_tcntaen (& self) -> TIMEOUT_CTL_TCNTAEN_R { TIMEOUT_CTL_TCNTAEN_R :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bits 16:23 - Timeout Count B Load: Counter B is used for SCL High Detection. This field contains the upper 8 bits of a 12-bit pre-load value for the Timeout B count. NOTE: The value of CNTLB must be greater than 1h. Each count is equal to 1* clock period. For example, with 10MHz functional clock one timeout period will be equal to1*100ns."] # [inline (always)] pub fn timeout_ctl_tcntlb (& self) -> TIMEOUT_CTL_TCNTLB_R { TIMEOUT_CTL_TCNTLB_R :: new (((self . bits >> 16) & 0xff) as u8) } # [doc = "Bit 31 - Timeout Counter B Enable"] # [inline (always)] pub fn timeout_ctl_tcntben (& self) -> TIMEOUT_CTL_TCNTBEN_R { TIMEOUT_CTL_TCNTBEN_R :: new (((self . bits >> 31) & 1) != 0) } } impl W { # [doc = "Bits 0:7 - Timeout counter A load value Counter A is used for SCL low detection. This field contains the upper 8 bits of a 12-bit pre-load value for the Timeout A count. NOTE: The value of CNTLA must be greater than 1h. Each count is equal to 520 times the timeout period of functional clock. For example, with 8MHz functional clock and a 100KHz operating I2C clock, one timeout period will be equal to (1 / 8MHz) * 520 or 65 us."] # [inline (always)] # [must_use] pub fn timeout_ctl_tcntla (& mut self) -> TIMEOUT_CTL_TCNTLA_W < TIMEOUT_CTL_SPEC , 0 > { TIMEOUT_CTL_TCNTLA_W :: new (self) } # [doc = "Bit 15 - Timeout Counter A Enable"] # [inline (always)] # [must_use] pub fn timeout_ctl_tcntaen (& mut self) -> TIMEOUT_CTL_TCNTAEN_W <'_, TIMEOUT_CTL_SPEC , 15 > { TIMEOUT_CTL_TCNTAEN_W :: new (self) } # [doc = "Bits 16:23 - Timeout Count B Load: Counter B is used for SCL High Detection. This field contains the upper 8 bits of a 12-bit pre-load value for the Timeout B count. NOTE: The value of CNTLB must be greater than 1h. Each count is equal to 1* clock period. For example, with 10MHz functional clock one timeout period will be equal to1*100ns."] # [inline (always)] # [must_use] pub fn timeout_ctl_tcntlb (& mut self) -> TIMEOUT_CTL_TCNTLB_W < TIMEOUT_CTL_SPEC , 16 > { TIMEOUT_CTL_TCNTLB_W :: new (self) } # [doc = "Bit 31 - Timeout Counter B Enable"] # [inline (always)] # [must_use] pub fn timeout_ctl_tcntben (& mut self) -> TIMEOUT_CTL_TCNTBEN_W < TIMEOUT_CTL_SPEC , 31 > { TIMEOUT_CTL_TCNTBEN_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "I2C Timeout Count Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`timeout_ctl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`timeout_ctl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct TIMEOUT_CTL_SPEC ; impl crate :: RegisterSpec for TIMEOUT_CTL_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`timeout_ctl::R`](R) reader structure"] impl crate :: Readable for TIMEOUT_CTL_SPEC { } # [doc = "`write(|w| ..)` method takes [`timeout_ctl::W`](W) writer structure"] impl crate :: Writable for TIMEOUT_CTL_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets TIMEOUT_CTL to value 0x0002_0002"] impl crate :: Resettable for TIMEOUT_CTL_SPEC { const RESET_VALUE : Self :: Ux = 0x0002_0002 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/i2c0/sackctl.rs:1:14408 [INFO] [stdout] | [INFO] [stdout] 1 | ...ackoen_on_pecdone (& mut self) -> SACKCTL_ACKOEN_ON_PECDONE_W < SACKCTL_SPEC , 4 > { SACKCTL_ACKOEN_ON_PECDONE_W :: new (self) } # [do... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `SACKCTL` reader"] pub type R = crate :: R < SACKCTL_SPEC > ; # [doc = "Register `SACKCTL` writer"] pub type W = crate :: W < SACKCTL_SPEC > ; # [doc = "Field `SACKCTL_ACKOEN` reader - I2C Slave ACK Override Enable"] pub type SACKCTL_ACKOEN_R = crate :: BitReader < SACKCTL_ACKOEN_A > ; # [doc = "I2C Slave ACK Override Enable\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum SACKCTL_ACKOEN_A { # [doc = "0: DISABLE"] SACKCTL_ACKOEN_DISABLE = 0 , # [doc = "1: ENABLE"] SACKCTL_ACKOEN_ENABLE = 1 , } impl From < SACKCTL_ACKOEN_A > for bool { # [inline (always)] fn from (variant : SACKCTL_ACKOEN_A) -> Self { variant as u8 != 0 } } impl SACKCTL_ACKOEN_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> SACKCTL_ACKOEN_A { match self . bits { false => SACKCTL_ACKOEN_A :: SACKCTL_ACKOEN_DISABLE , true => SACKCTL_ACKOEN_A :: SACKCTL_ACKOEN_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_sackctl_ackoen_disable (& self) -> bool { * self == SACKCTL_ACKOEN_A :: SACKCTL_ACKOEN_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_sackctl_ackoen_enable (& self) -> bool { * self == SACKCTL_ACKOEN_A :: SACKCTL_ACKOEN_ENABLE } } # [doc = "Field `SACKCTL_ACKOEN` writer - I2C Slave ACK Override Enable"] pub type SACKCTL_ACKOEN_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , SACKCTL_ACKOEN_A > ; impl < 'a , REG , const O : u8 > SACKCTL_ACKOEN_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn sackctl_ackoen_disable (self) -> & 'a mut crate :: W < REG > { self . variant (SACKCTL_ACKOEN_A :: SACKCTL_ACKOEN_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn sackctl_ackoen_enable (self) -> & 'a mut crate :: W < REG > { self . variant (SACKCTL_ACKOEN_A :: SACKCTL_ACKOEN_ENABLE) } } # [doc = "Field `SACKCTL_ACKOVAL` reader - I2C Slave ACK Override Value Note: for General Call this bit will be ignored if set to NACK and slave continues to receive data."] pub type SACKCTL_ACKOVAL_R = crate :: BitReader < SACKCTL_ACKOVAL_A > ; # [doc = "I2C Slave ACK Override Value Note: for General Call this bit will be ignored if set to NACK and slave continues to receive data.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum SACKCTL_ACKOVAL_A { # [doc = "0: DISABLE"] SACKCTL_ACKOVAL_DISABLE = 0 , # [doc = "1: ENABLE"] SACKCTL_ACKOVAL_ENABLE = 1 , } impl From < SACKCTL_ACKOVAL_A > for bool { # [inline (always)] fn from (variant : SACKCTL_ACKOVAL_A) -> Self { variant as u8 != 0 } } impl SACKCTL_ACKOVAL_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> SACKCTL_ACKOVAL_A { match self . bits { false => SACKCTL_ACKOVAL_A :: SACKCTL_ACKOVAL_DISABLE , true => SACKCTL_ACKOVAL_A :: SACKCTL_ACKOVAL_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_sackctl_ackoval_disable (& self) -> bool { * self == SACKCTL_ACKOVAL_A :: SACKCTL_ACKOVAL_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_sackctl_ackoval_enable (& self) -> bool { * self == SACKCTL_ACKOVAL_A :: SACKCTL_ACKOVAL_ENABLE } } # [doc = "Field `SACKCTL_ACKOVAL` writer - I2C Slave ACK Override Value Note: for General Call this bit will be ignored if set to NACK and slave continues to receive data."] pub type SACKCTL_ACKOVAL_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , SACKCTL_ACKOVAL_A > ; impl < 'a , REG , const O : u8 > SACKCTL_ACKOVAL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn sackctl_ackoval_disable (self) -> & 'a mut crate :: W < REG > { self . variant (SACKCTL_ACKOVAL_A :: SACKCTL_ACKOVAL_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn sackctl_ackoval_enable (self) -> & 'a mut crate :: W < REG > { self . variant (SACKCTL_ACKOVAL_A :: SACKCTL_ACKOVAL_ENABLE) } } # [doc = "Field `SACKCTL_ACKOEN_ON_START` reader - When set this bit will automatically turn on the Slave ACKOEN field following a Start Condition."] pub type SACKCTL_ACKOEN_ON_START_R = crate :: BitReader < SACKCTL_ACKOEN_ON_START_A > ; # [doc = "When set this bit will automatically turn on the Slave ACKOEN field following a Start Condition.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum SACKCTL_ACKOEN_ON_START_A { # [doc = "0: DISABLE"] SACKCTL_ACKOEN_ON_START_DISABLE = 0 , # [doc = "1: ENABLE"] SACKCTL_ACKOEN_ON_START_ENABLE = 1 , } impl From < SACKCTL_ACKOEN_ON_START_A > for bool { # [inline (always)] fn from (variant : SACKCTL_ACKOEN_ON_START_A) -> Self { variant as u8 != 0 } } impl SACKCTL_ACKOEN_ON_START_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> SACKCTL_ACKOEN_ON_START_A { match self . bits { false => SACKCTL_ACKOEN_ON_START_A :: SACKCTL_ACKOEN_ON_START_DISABLE , true => SACKCTL_ACKOEN_ON_START_A :: SACKCTL_ACKOEN_ON_START_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_sackctl_ackoen_on_start_disable (& self) -> bool { * self == SACKCTL_ACKOEN_ON_START_A :: SACKCTL_ACKOEN_ON_START_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_sackctl_ackoen_on_start_enable (& self) -> bool { * self == SACKCTL_ACKOEN_ON_START_A :: SACKCTL_ACKOEN_ON_START_ENABLE } } # [doc = "Field `SACKCTL_ACKOEN_ON_START` writer - When set this bit will automatically turn on the Slave ACKOEN field following a Start Condition."] pub type SACKCTL_ACKOEN_ON_START_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , SACKCTL_ACKOEN_ON_START_A > ; impl < 'a , REG , const O : u8 > SACKCTL_ACKOEN_ON_START_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn sackctl_ackoen_on_start_disable (self) -> & 'a mut crate :: W < REG > { self . variant (SACKCTL_ACKOEN_ON_START_A :: SACKCTL_ACKOEN_ON_START_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn sackctl_ackoen_on_start_enable (self) -> & 'a mut crate :: W < REG > { self . variant (SACKCTL_ACKOEN_ON_START_A :: SACKCTL_ACKOEN_ON_START_ENABLE) } } # [doc = "Field `SACKCTL_ACKOEN_ON_PECNEXT` reader - When set this bit will automatically turn on the Slave ACKOEN field following the ACK/NACK of the byte received just prior to the PEC byte. Note that when ACKOEN is set the PEC byte will not automatically be ACKed/NACKed by the State Machine and FW must perform this function by writing SLAVE_SACKCTL."] pub type SACKCTL_ACKOEN_ON_PECNEXT_R = crate :: BitReader < SACKCTL_ACKOEN_ON_PECNEXT_A > ; # [doc = "When set this bit will automatically turn on the Slave ACKOEN field following the ACK/NACK of the byte received just prior to the PEC byte. Note that when ACKOEN is set the PEC byte will not automatically be ACKed/NACKed by the State Machine and FW must perform this function by writing SLAVE_SACKCTL.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum SACKCTL_ACKOEN_ON_PECNEXT_A { # [doc = "0: DISABLE"] SACKCTL_ACKOEN_ON_PECNEXT_DISABLE = 0 , # [doc = "1: ENABLE"] SACKCTL_ACKOEN_ON_PECNEXT_ENABLE = 1 , } impl From < SACKCTL_ACKOEN_ON_PECNEXT_A > for bool { # [inline (always)] fn from (variant : SACKCTL_ACKOEN_ON_PECNEXT_A) -> Self { variant as u8 != 0 } } impl SACKCTL_ACKOEN_ON_PECNEXT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> SACKCTL_ACKOEN_ON_PECNEXT_A { match self . bits { false => SACKCTL_ACKOEN_ON_PECNEXT_A :: SACKCTL_ACKOEN_ON_PECNEXT_DISABLE , true => SACKCTL_ACKOEN_ON_PECNEXT_A :: SACKCTL_ACKOEN_ON_PECNEXT_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_sackctl_ackoen_on_pecnext_disable (& self) -> bool { * self == SACKCTL_ACKOEN_ON_PECNEXT_A :: SACKCTL_ACKOEN_ON_PECNEXT_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_sackctl_ackoen_on_pecnext_enable (& self) -> bool { * self == SACKCTL_ACKOEN_ON_PECNEXT_A :: SACKCTL_ACKOEN_ON_PECNEXT_ENABLE } } # [doc = "Field `SACKCTL_ACKOEN_ON_PECNEXT` writer - When set this bit will automatically turn on the Slave ACKOEN field following the ACK/NACK of the byte received just prior to the PEC byte. Note that when ACKOEN is set the PEC byte will not automatically be ACKed/NACKed by the State Machine and FW must perform this function by writing SLAVE_SACKCTL."] pub type SACKCTL_ACKOEN_ON_PECNEXT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , SACKCTL_ACKOEN_ON_PECNEXT_A > ; impl < 'a , REG , const O : u8 > SACKCTL_ACKOEN_ON_PECNEXT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn sackctl_ackoen_on_pecnext_disable (self) -> & 'a mut crate :: W < REG > { self . variant (SACKCTL_ACKOEN_ON_PECNEXT_A :: SACKCTL_ACKOEN_ON_PECNEXT_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn sackctl_ackoen_on_pecnext_enable (self) -> & 'a mut crate :: W < REG > { self . variant (SACKCTL_ACKOEN_ON_PECNEXT_A :: SACKCTL_ACKOEN_ON_PECNEXT_ENABLE) } } # [doc = "Field `SACKCTL_ACKOEN_ON_PECDONE` reader - When set this bit will automatically turn on the Slave ACKOEN field following the ACK/NACK of the received PEC byte."] pub type SACKCTL_ACKOEN_ON_PECDONE_R = crate :: BitReader < SACKCTL_ACKOEN_ON_PECDONE_A > ; # [doc = "When set this bit will automatically turn on the Slave ACKOEN field following the ACK/NACK of the received PEC byte.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum SACKCTL_ACKOEN_ON_PECDONE_A { # [doc = "0: DISABLE"] SACKCTL_ACKOEN_ON_PECDONE_DISABLE = 0 , # [doc = "1: ENABLE"] SACKCTL_ACKOEN_ON_PECDONE_ENABLE = 1 , } impl From < SACKCTL_ACKOEN_ON_PECDONE_A > for bool { # [inline (always)] fn from (variant : SACKCTL_ACKOEN_ON_PECDONE_A) -> Self { variant as u8 != 0 } } impl SACKCTL_ACKOEN_ON_PECDONE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> SACKCTL_ACKOEN_ON_PECDONE_A { match self . bits { false => SACKCTL_ACKOEN_ON_PECDONE_A :: SACKCTL_ACKOEN_ON_PECDONE_DISABLE , true => SACKCTL_ACKOEN_ON_PECDONE_A :: SACKCTL_ACKOEN_ON_PECDONE_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_sackctl_ackoen_on_pecdone_disable (& self) -> bool { * self == SACKCTL_ACKOEN_ON_PECDONE_A :: SACKCTL_ACKOEN_ON_PECDONE_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_sackctl_ackoen_on_pecdone_enable (& self) -> bool { * self == SACKCTL_ACKOEN_ON_PECDONE_A :: SACKCTL_ACKOEN_ON_PECDONE_ENABLE } } # [doc = "Field `SACKCTL_ACKOEN_ON_PECDONE` writer - When set this bit will automatically turn on the Slave ACKOEN field following the ACK/NACK of the received PEC byte."] pub type SACKCTL_ACKOEN_ON_PECDONE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , SACKCTL_ACKOEN_ON_PECDONE_A > ; impl < 'a , REG , const O : u8 > SACKCTL_ACKOEN_ON_PECDONE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn sackctl_ackoen_on_pecdone_disable (self) -> & 'a mut crate :: W < REG > { self . variant (SACKCTL_ACKOEN_ON_PECDONE_A :: SACKCTL_ACKOEN_ON_PECDONE_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn sackctl_ackoen_on_pecdone_enable (self) -> & 'a mut crate :: W < REG > { self . variant (SACKCTL_ACKOEN_ON_PECDONE_A :: SACKCTL_ACKOEN_ON_PECDONE_ENABLE) } } impl R { # [doc = "Bit 0 - I2C Slave ACK Override Enable"] # [inline (always)] pub fn sackctl_ackoen (& self) -> SACKCTL_ACKOEN_R { SACKCTL_ACKOEN_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - I2C Slave ACK Override Value Note: for General Call this bit will be ignored if set to NACK and slave continues to receive data."] # [inline (always)] pub fn sackctl_ackoval (& self) -> SACKCTL_ACKOVAL_R { SACKCTL_ACKOVAL_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - When set this bit will automatically turn on the Slave ACKOEN field following a Start Condition."] # [inline (always)] pub fn sackctl_ackoen_on_start (& self) -> SACKCTL_ACKOEN_ON_START_R { SACKCTL_ACKOEN_ON_START_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - When set this bit will automatically turn on the Slave ACKOEN field following the ACK/NACK of the byte received just prior to the PEC byte. Note that when ACKOEN is set the PEC byte will not automatically be ACKed/NACKed by the State Machine and FW must perform this function by writing SLAVE_SACKCTL."] # [inline (always)] pub fn sackctl_ackoen_on_pecnext (& self) -> SACKCTL_ACKOEN_ON_PECNEXT_R { SACKCTL_ACKOEN_ON_PECNEXT_R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - When set this bit will automatically turn on the Slave ACKOEN field following the ACK/NACK of the received PEC byte."] # [inline (always)] pub fn sackctl_ackoen_on_pecdone (& self) -> SACKCTL_ACKOEN_ON_PECDONE_R { SACKCTL_ACKOEN_ON_PECDONE_R :: new (((self . bits >> 4) & 1) != 0) } } impl W { # [doc = "Bit 0 - I2C Slave ACK Override Enable"] # [inline (always)] # [must_use] pub fn sackctl_ackoen (& mut self) -> SACKCTL_ACKOEN_W < SACKCTL_SPEC , 0 > { SACKCTL_ACKOEN_W :: new (self) } # [doc = "Bit 1 - I2C Slave ACK Override Value Note: for General Call this bit will be ignored if set to NACK and slave continues to receive data."] # [inline (always)] # [must_use] pub fn sackctl_ackoval (& mut self) -> SACKCTL_ACKOVAL_W < SACKCTL_SPEC , 1 > { SACKCTL_ACKOVAL_W :: new (self) } # [doc = "Bit 2 - When set this bit will automatically turn on the Slave ACKOEN field following a Start Condition."] # [inline (always)] # [must_use] pub fn sackctl_ackoen_on_start (& mut self) -> SACKCTL_ACKOEN_ON_START_W < SACKCTL_SPEC , 2 > { SACKCTL_ACKOEN_ON_START_W :: new (self) } # [doc = "Bit 3 - When set this bit will automatically turn on the Slave ACKOEN field following the ACK/NACK of the byte received just prior to the PEC byte. Note that when ACKOEN is set the PEC byte will not automatically be ACKed/NACKed by the State Machine and FW must perform this function by writing SLAVE_SACKCTL."] # [inline (always)] # [must_use] pub fn sackctl_ackoen_on_pecnext (& mut self) -> SACKCTL_ACKOEN_ON_PECNEXT_W < SACKCTL_SPEC , 3 > { SACKCTL_ACKOEN_ON_PECNEXT_W :: new (self) } # [doc = "Bit 4 - When set this bit will automatically turn on the Slave ACKOEN field following the ACK/NACK of the received PEC byte."] # [inline (always)] # [must_use] pub fn sackctl_ackoen_on_pecdone (& mut self) -> SACKCTL_ACKOEN_ON_PECDONE_W <'_, SACKCTL_SPEC , 4 > { SACKCTL_ACKOEN_ON_PECDONE_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "I2C Slave ACK Control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sackctl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sackctl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct SACKCTL_SPEC ; impl crate :: RegisterSpec for SACKCTL_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`sackctl::R`](R) reader structure"] impl crate :: Readable for SACKCTL_SPEC { } # [doc = "`write(|w| ..)` method takes [`sackctl::W`](W) writer structure"] impl crate :: Writable for SACKCTL_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets SACKCTL to value 0"] impl crate :: Resettable for SACKCTL_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/i2c1/pwren.rs:1:3131 [INFO] [stdout] | [INFO] [stdout] 1 | ...ust_use] pub fn pwren_key (& mut self) -> PWREN_KEY_W < PWREN_SPEC , 24 > { PWREN_KEY_W :: new (self) } # [doc = r" Writes raw bits to... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `PWREN` reader"] pub type R = crate :: R < PWREN_SPEC > ; # [doc = "Register `PWREN` writer"] pub type W = crate :: W < PWREN_SPEC > ; # [doc = "Field `PWREN_ENABLE` reader - Enable the power"] pub type PWREN_ENABLE_R = crate :: BitReader < PWREN_ENABLE_A > ; # [doc = "Enable the power\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum PWREN_ENABLE_A { # [doc = "0: DISABLE"] PWREN_ENABLE_DISABLE = 0 , # [doc = "1: ENABLE"] PWREN_ENABLE_ENABLE = 1 , } impl From < PWREN_ENABLE_A > for bool { # [inline (always)] fn from (variant : PWREN_ENABLE_A) -> Self { variant as u8 != 0 } } impl PWREN_ENABLE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> PWREN_ENABLE_A { match self . bits { false => PWREN_ENABLE_A :: PWREN_ENABLE_DISABLE , true => PWREN_ENABLE_A :: PWREN_ENABLE_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_pwren_enable_disable (& self) -> bool { * self == PWREN_ENABLE_A :: PWREN_ENABLE_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_pwren_enable_enable (& self) -> bool { * self == PWREN_ENABLE_A :: PWREN_ENABLE_ENABLE } } # [doc = "Field `PWREN_ENABLE` writer - Enable the power"] pub type PWREN_ENABLE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , PWREN_ENABLE_A > ; impl < 'a , REG , const O : u8 > PWREN_ENABLE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn pwren_enable_disable (self) -> & 'a mut crate :: W < REG > { self . variant (PWREN_ENABLE_A :: PWREN_ENABLE_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn pwren_enable_enable (self) -> & 'a mut crate :: W < REG > { self . variant (PWREN_ENABLE_A :: PWREN_ENABLE_ENABLE) } } # [doc = "KEY to allow Power State Change\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum PWREN_KEY_AW { # [doc = "38: _TO_UNLOCK_W_"] PWREN_KEY_UNLOCK_W = 38 , } impl From < PWREN_KEY_AW > for u8 { # [inline (always)] fn from (variant : PWREN_KEY_AW) -> Self { variant as _ } } impl crate :: FieldSpec for PWREN_KEY_AW { type Ux = u8 ; } # [doc = "Field `PWREN_KEY` writer - KEY to allow Power State Change"] pub type PWREN_KEY_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 8 , O , PWREN_KEY_AW > ; impl < 'a , REG , const O : u8 > PWREN_KEY_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "_TO_UNLOCK_W_"] # [inline (always)] pub fn pwren_key_unlock_w (self) -> & 'a mut crate :: W < REG > { self . variant (PWREN_KEY_AW :: PWREN_KEY_UNLOCK_W) } } impl R { # [doc = "Bit 0 - Enable the power"] # [inline (always)] pub fn pwren_enable (& self) -> PWREN_ENABLE_R { PWREN_ENABLE_R :: new ((self . bits & 1) != 0) } } impl W { # [doc = "Bit 0 - Enable the power"] # [inline (always)] # [must_use] pub fn pwren_enable (& mut self) -> PWREN_ENABLE_W < PWREN_SPEC , 0 > { PWREN_ENABLE_W :: new (self) } # [doc = "Bits 24:31 - KEY to allow Power State Change"] # [inline (always)] # [must_use] pub fn pwren_key (& mut self) -> PWREN_KEY_W <'_, PWREN_SPEC , 24 > { PWREN_KEY_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Power enable\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pwren::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pwren::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PWREN_SPEC ; impl crate :: RegisterSpec for PWREN_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`pwren::R`](R) reader structure"] impl crate :: Readable for PWREN_SPEC { } # [doc = "`write(|w| ..)` method takes [`pwren::W`](W) writer structure"] impl crate :: Writable for PWREN_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets PWREN to value 0"] impl crate :: Resettable for PWREN_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/timg4/octl_01.rs:1:10487 [INFO] [stdout] | [INFO] [stdout] 1 | ...e] pub fn octl_01_ccpiv (& mut self) -> OCTL_01_CCPIV_W < OCTL_01_SPEC , 5 > { OCTL_01_CCPIV_W :: new (self) } # [doc = r" Writes raw ... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `OCTL_01[%s]` reader"] pub type R = crate :: R < OCTL_01_SPEC > ; # [doc = "Register `OCTL_01[%s]` writer"] pub type W = crate :: W < OCTL_01_SPEC > ; # [doc = "Field `OCTL_01_CCPO` reader - CCP Output Source"] pub type OCTL_01_CCPO_R = crate :: FieldReader < OCTL_01_CCPO_A > ; # [doc = "CCP Output Source\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum OCTL_01_CCPO_A { # [doc = "0: FUNCVAL"] OCTL_01_CCPO_FUNCVAL = 0 , # [doc = "1: LOAD"] OCTL_01_CCPO_LOAD = 1 , # [doc = "2: CMPVAL"] OCTL_01_CCPO_CMPVAL = 2 , # [doc = "4: ZERO"] OCTL_01_CCPO_ZERO = 4 , # [doc = "5: CAPCOND"] OCTL_01_CCPO_CAPCOND = 5 , # [doc = "6: FAULTCOND"] OCTL_01_CCPO_FAULTCOND = 6 , # [doc = "8: CC0_MIRROR_ALL"] OCTL_01_CCPO_CC0_MIRROR_ALL = 8 , # [doc = "9: CC1_MIRROR_ALL"] OCTL_01_CCPO_CC1_MIRROR_ALL = 9 , # [doc = "12: DEADBAND"] OCTL_01_CCPO_DEADBAND = 12 , # [doc = "13: CNTDIR"] OCTL_01_CCPO_CNTDIR = 13 , } impl From < OCTL_01_CCPO_A > for u8 { # [inline (always)] fn from (variant : OCTL_01_CCPO_A) -> Self { variant as _ } } impl crate :: FieldSpec for OCTL_01_CCPO_A { type Ux = u8 ; } impl OCTL_01_CCPO_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < OCTL_01_CCPO_A > { match self . bits { 0 => Some (OCTL_01_CCPO_A :: OCTL_01_CCPO_FUNCVAL) , 1 => Some (OCTL_01_CCPO_A :: OCTL_01_CCPO_LOAD) , 2 => Some (OCTL_01_CCPO_A :: OCTL_01_CCPO_CMPVAL) , 4 => Some (OCTL_01_CCPO_A :: OCTL_01_CCPO_ZERO) , 5 => Some (OCTL_01_CCPO_A :: OCTL_01_CCPO_CAPCOND) , 6 => Some (OCTL_01_CCPO_A :: OCTL_01_CCPO_FAULTCOND) , 8 => Some (OCTL_01_CCPO_A :: OCTL_01_CCPO_CC0_MIRROR_ALL) , 9 => Some (OCTL_01_CCPO_A :: OCTL_01_CCPO_CC1_MIRROR_ALL) , 12 => Some (OCTL_01_CCPO_A :: OCTL_01_CCPO_DEADBAND) , 13 => Some (OCTL_01_CCPO_A :: OCTL_01_CCPO_CNTDIR) , _ => None , } } # [doc = "FUNCVAL"] # [inline (always)] pub fn is_octl_01_ccpo_funcval (& self) -> bool { * self == OCTL_01_CCPO_A :: OCTL_01_CCPO_FUNCVAL } # [doc = "LOAD"] # [inline (always)] pub fn is_octl_01_ccpo_load (& self) -> bool { * self == OCTL_01_CCPO_A :: OCTL_01_CCPO_LOAD } # [doc = "CMPVAL"] # [inline (always)] pub fn is_octl_01_ccpo_cmpval (& self) -> bool { * self == OCTL_01_CCPO_A :: OCTL_01_CCPO_CMPVAL } # [doc = "ZERO"] # [inline (always)] pub fn is_octl_01_ccpo_zero (& self) -> bool { * self == OCTL_01_CCPO_A :: OCTL_01_CCPO_ZERO } # [doc = "CAPCOND"] # [inline (always)] pub fn is_octl_01_ccpo_capcond (& self) -> bool { * self == OCTL_01_CCPO_A :: OCTL_01_CCPO_CAPCOND } # [doc = "FAULTCOND"] # [inline (always)] pub fn is_octl_01_ccpo_faultcond (& self) -> bool { * self == OCTL_01_CCPO_A :: OCTL_01_CCPO_FAULTCOND } # [doc = "CC0_MIRROR_ALL"] # [inline (always)] pub fn is_octl_01_ccpo_cc0_mirror_all (& self) -> bool { * self == OCTL_01_CCPO_A :: OCTL_01_CCPO_CC0_MIRROR_ALL } # [doc = "CC1_MIRROR_ALL"] # [inline (always)] pub fn is_octl_01_ccpo_cc1_mirror_all (& self) -> bool { * self == OCTL_01_CCPO_A :: OCTL_01_CCPO_CC1_MIRROR_ALL } # [doc = "DEADBAND"] # [inline (always)] pub fn is_octl_01_ccpo_deadband (& self) -> bool { * self == OCTL_01_CCPO_A :: OCTL_01_CCPO_DEADBAND } # [doc = "CNTDIR"] # [inline (always)] pub fn is_octl_01_ccpo_cntdir (& self) -> bool { * self == OCTL_01_CCPO_A :: OCTL_01_CCPO_CNTDIR } } # [doc = "Field `OCTL_01_CCPO` writer - CCP Output Source"] pub type OCTL_01_CCPO_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 4 , O , OCTL_01_CCPO_A > ; impl < 'a , REG , const O : u8 > OCTL_01_CCPO_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "FUNCVAL"] # [inline (always)] pub fn octl_01_ccpo_funcval (self) -> & 'a mut crate :: W < REG > { self . variant (OCTL_01_CCPO_A :: OCTL_01_CCPO_FUNCVAL) } # [doc = "LOAD"] # [inline (always)] pub fn octl_01_ccpo_load (self) -> & 'a mut crate :: W < REG > { self . variant (OCTL_01_CCPO_A :: OCTL_01_CCPO_LOAD) } # [doc = "CMPVAL"] # [inline (always)] pub fn octl_01_ccpo_cmpval (self) -> & 'a mut crate :: W < REG > { self . variant (OCTL_01_CCPO_A :: OCTL_01_CCPO_CMPVAL) } # [doc = "ZERO"] # [inline (always)] pub fn octl_01_ccpo_zero (self) -> & 'a mut crate :: W < REG > { self . variant (OCTL_01_CCPO_A :: OCTL_01_CCPO_ZERO) } # [doc = "CAPCOND"] # [inline (always)] pub fn octl_01_ccpo_capcond (self) -> & 'a mut crate :: W < REG > { self . variant (OCTL_01_CCPO_A :: OCTL_01_CCPO_CAPCOND) } # [doc = "FAULTCOND"] # [inline (always)] pub fn octl_01_ccpo_faultcond (self) -> & 'a mut crate :: W < REG > { self . variant (OCTL_01_CCPO_A :: OCTL_01_CCPO_FAULTCOND) } # [doc = "CC0_MIRROR_ALL"] # [inline (always)] pub fn octl_01_ccpo_cc0_mirror_all (self) -> & 'a mut crate :: W < REG > { self . variant (OCTL_01_CCPO_A :: OCTL_01_CCPO_CC0_MIRROR_ALL) } # [doc = "CC1_MIRROR_ALL"] # [inline (always)] pub fn octl_01_ccpo_cc1_mirror_all (self) -> & 'a mut crate :: W < REG > { self . variant (OCTL_01_CCPO_A :: OCTL_01_CCPO_CC1_MIRROR_ALL) } # [doc = "DEADBAND"] # [inline (always)] pub fn octl_01_ccpo_deadband (self) -> & 'a mut crate :: W < REG > { self . variant (OCTL_01_CCPO_A :: OCTL_01_CCPO_DEADBAND) } # [doc = "CNTDIR"] # [inline (always)] pub fn octl_01_ccpo_cntdir (self) -> & 'a mut crate :: W < REG > { self . variant (OCTL_01_CCPO_A :: OCTL_01_CCPO_CNTDIR) } } # [doc = "Field `OCTL_01_CCPOINV` reader - CCP Output Invert The output as selected by CCPO is conditionally inverted."] pub type OCTL_01_CCPOINV_R = crate :: BitReader < OCTL_01_CCPOINV_A > ; # [doc = "CCP Output Invert The output as selected by CCPO is conditionally inverted.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum OCTL_01_CCPOINV_A { # [doc = "0: NOINV"] OCTL_01_CCPOINV_NOINV = 0 , # [doc = "1: INV"] OCTL_01_CCPOINV_INV = 1 , } impl From < OCTL_01_CCPOINV_A > for bool { # [inline (always)] fn from (variant : OCTL_01_CCPOINV_A) -> Self { variant as u8 != 0 } } impl OCTL_01_CCPOINV_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> OCTL_01_CCPOINV_A { match self . bits { false => OCTL_01_CCPOINV_A :: OCTL_01_CCPOINV_NOINV , true => OCTL_01_CCPOINV_A :: OCTL_01_CCPOINV_INV , } } # [doc = "NOINV"] # [inline (always)] pub fn is_octl_01_ccpoinv_noinv (& self) -> bool { * self == OCTL_01_CCPOINV_A :: OCTL_01_CCPOINV_NOINV } # [doc = "INV"] # [inline (always)] pub fn is_octl_01_ccpoinv_inv (& self) -> bool { * self == OCTL_01_CCPOINV_A :: OCTL_01_CCPOINV_INV } } # [doc = "Field `OCTL_01_CCPOINV` writer - CCP Output Invert The output as selected by CCPO is conditionally inverted."] pub type OCTL_01_CCPOINV_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , OCTL_01_CCPOINV_A > ; impl < 'a , REG , const O : u8 > OCTL_01_CCPOINV_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NOINV"] # [inline (always)] pub fn octl_01_ccpoinv_noinv (self) -> & 'a mut crate :: W < REG > { self . variant (OCTL_01_CCPOINV_A :: OCTL_01_CCPOINV_NOINV) } # [doc = "INV"] # [inline (always)] pub fn octl_01_ccpoinv_inv (self) -> & 'a mut crate :: W < REG > { self . variant (OCTL_01_CCPOINV_A :: OCTL_01_CCPOINV_INV) } } # [doc = "Field `OCTL_01_CCPIV` reader - CCP Initial Value This bit specifies the logical value put on the signal generator state while the counter is disabled (CTRCTL.EN == 0)."] pub type OCTL_01_CCPIV_R = crate :: BitReader < OCTL_01_CCPIV_A > ; # [doc = "CCP Initial Value This bit specifies the logical value put on the signal generator state while the counter is disabled (CTRCTL.EN == 0).\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum OCTL_01_CCPIV_A { # [doc = "0: LOW"] OCTL_01_CCPIV_LOW = 0 , # [doc = "1: HIGH"] OCTL_01_CCPIV_HIGH = 1 , } impl From < OCTL_01_CCPIV_A > for bool { # [inline (always)] fn from (variant : OCTL_01_CCPIV_A) -> Self { variant as u8 != 0 } } impl OCTL_01_CCPIV_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> OCTL_01_CCPIV_A { match self . bits { false => OCTL_01_CCPIV_A :: OCTL_01_CCPIV_LOW , true => OCTL_01_CCPIV_A :: OCTL_01_CCPIV_HIGH , } } # [doc = "LOW"] # [inline (always)] pub fn is_octl_01_ccpiv_low (& self) -> bool { * self == OCTL_01_CCPIV_A :: OCTL_01_CCPIV_LOW } # [doc = "HIGH"] # [inline (always)] pub fn is_octl_01_ccpiv_high (& self) -> bool { * self == OCTL_01_CCPIV_A :: OCTL_01_CCPIV_HIGH } } # [doc = "Field `OCTL_01_CCPIV` writer - CCP Initial Value This bit specifies the logical value put on the signal generator state while the counter is disabled (CTRCTL.EN == 0)."] pub type OCTL_01_CCPIV_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , OCTL_01_CCPIV_A > ; impl < 'a , REG , const O : u8 > OCTL_01_CCPIV_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "LOW"] # [inline (always)] pub fn octl_01_ccpiv_low (self) -> & 'a mut crate :: W < REG > { self . variant (OCTL_01_CCPIV_A :: OCTL_01_CCPIV_LOW) } # [doc = "HIGH"] # [inline (always)] pub fn octl_01_ccpiv_high (self) -> & 'a mut crate :: W < REG > { self . variant (OCTL_01_CCPIV_A :: OCTL_01_CCPIV_HIGH) } } impl R { # [doc = "Bits 0:3 - CCP Output Source"] # [inline (always)] pub fn octl_01_ccpo (& self) -> OCTL_01_CCPO_R { OCTL_01_CCPO_R :: new ((self . bits & 0x0f) as u8) } # [doc = "Bit 4 - CCP Output Invert The output as selected by CCPO is conditionally inverted."] # [inline (always)] pub fn octl_01_ccpoinv (& self) -> OCTL_01_CCPOINV_R { OCTL_01_CCPOINV_R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - CCP Initial Value This bit specifies the logical value put on the signal generator state while the counter is disabled (CTRCTL.EN == 0)."] # [inline (always)] pub fn octl_01_ccpiv (& self) -> OCTL_01_CCPIV_R { OCTL_01_CCPIV_R :: new (((self . bits >> 5) & 1) != 0) } } impl W { # [doc = "Bits 0:3 - CCP Output Source"] # [inline (always)] # [must_use] pub fn octl_01_ccpo (& mut self) -> OCTL_01_CCPO_W < OCTL_01_SPEC , 0 > { OCTL_01_CCPO_W :: new (self) } # [doc = "Bit 4 - CCP Output Invert The output as selected by CCPO is conditionally inverted."] # [inline (always)] # [must_use] pub fn octl_01_ccpoinv (& mut self) -> OCTL_01_CCPOINV_W < OCTL_01_SPEC , 4 > { OCTL_01_CCPOINV_W :: new (self) } # [doc = "Bit 5 - CCP Initial Value This bit specifies the logical value put on the signal generator state while the counter is disabled (CTRCTL.EN == 0)."] # [inline (always)] # [must_use] pub fn octl_01_ccpiv (& mut self) -> OCTL_01_CCPIV_W <'_, OCTL_01_SPEC , 5 > { OCTL_01_CCPIV_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "CCP Output Control Registers\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`octl_01::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`octl_01::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct OCTL_01_SPEC ; impl crate :: RegisterSpec for OCTL_01_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`octl_01::R`](R) reader structure"] impl crate :: Readable for OCTL_01_SPEC { } # [doc = "`write(|w| ..)` method takes [`octl_01::W`](W) writer structure"] impl crate :: Writable for OCTL_01_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets OCTL_01[%s] [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/gpioa/fpub_1.rs:1:2067 [INFO] [stdout] | [INFO] [stdout] 1 | ...e] pub fn fpub_1_chanid (& mut self) -> FPUB_1_CHANID_W < FPUB_1_SPEC , 0 > { FPUB_1_CHANID_W :: new (self) } # [doc = r" Writes raw b... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `FPUB_1` reader"] pub type R = crate :: R < FPUB_1_SPEC > ; # [doc = "Register `FPUB_1` writer"] pub type W = crate :: W < FPUB_1_SPEC > ; # [doc = "Field `FPUB_1_CHANID` reader - 0 = disconnected. 1-15 = connected to channelID = CHANID."] pub type FPUB_1_CHANID_R = crate :: FieldReader < FPUB_1_CHANID_A > ; # [doc = "0 = disconnected. 1-15 = connected to channelID = CHANID.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum FPUB_1_CHANID_A { # [doc = "0: UNCONNECTED"] FPUB_1_CHANID_UNCONNECTED = 0 , } impl From < FPUB_1_CHANID_A > for u8 { # [inline (always)] fn from (variant : FPUB_1_CHANID_A) -> Self { variant as _ } } impl crate :: FieldSpec for FPUB_1_CHANID_A { type Ux = u8 ; } impl FPUB_1_CHANID_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < FPUB_1_CHANID_A > { match self . bits { 0 => Some (FPUB_1_CHANID_A :: FPUB_1_CHANID_UNCONNECTED) , _ => None , } } # [doc = "UNCONNECTED"] # [inline (always)] pub fn is_fpub_1_chanid_unconnected (& self) -> bool { * self == FPUB_1_CHANID_A :: FPUB_1_CHANID_UNCONNECTED } } # [doc = "Field `FPUB_1_CHANID` writer - 0 = disconnected. 1-15 = connected to channelID = CHANID."] pub type FPUB_1_CHANID_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 2 , O , FPUB_1_CHANID_A > ; impl < 'a , REG , const O : u8 > FPUB_1_CHANID_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "UNCONNECTED"] # [inline (always)] pub fn fpub_1_chanid_unconnected (self) -> & 'a mut crate :: W < REG > { self . variant (FPUB_1_CHANID_A :: FPUB_1_CHANID_UNCONNECTED) } } impl R { # [doc = "Bits 0:1 - 0 = disconnected. 1-15 = connected to channelID = CHANID."] # [inline (always)] pub fn fpub_1_chanid (& self) -> FPUB_1_CHANID_R { FPUB_1_CHANID_R :: new ((self . bits & 3) as u8) } } impl W { # [doc = "Bits 0:1 - 0 = disconnected. 1-15 = connected to channelID = CHANID."] # [inline (always)] # [must_use] pub fn fpub_1_chanid (& mut self) -> FPUB_1_CHANID_W <'_, FPUB_1_SPEC , 0 > { FPUB_1_CHANID_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Publisher Port 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fpub_1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fpub_1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct FPUB_1_SPEC ; impl crate :: RegisterSpec for FPUB_1_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`fpub_1::R`](R) reader structure"] impl crate :: Readable for FPUB_1_SPEC { } # [doc = "`write(|w| ..)` method takes [`fpub_1::W`](W) writer structure"] impl crate :: Writable for FPUB_1_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets FPUB_1 to value 0"] impl crate :: Resettable for FPUB_1_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/i2c1/timeout_ctl.rs:1:8643 [INFO] [stdout] | [INFO] [stdout] 1 | ...timeout_ctl_tcntlb (& mut self) -> TIMEOUT_CTL_TCNTLB_W < TIMEOUT_CTL_SPEC , 16 > { TIMEOUT_CTL_TCNTLB_W :: new (self) } # [doc = "Bit... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `TIMEOUT_CTL` reader"] pub type R = crate :: R < TIMEOUT_CTL_SPEC > ; # [doc = "Register `TIMEOUT_CTL` writer"] pub type W = crate :: W < TIMEOUT_CTL_SPEC > ; # [doc = "Field `TIMEOUT_CTL_TCNTLA` reader - Timeout counter A load value Counter A is used for SCL low detection. This field contains the upper 8 bits of a 12-bit pre-load value for the Timeout A count. NOTE: The value of CNTLA must be greater than 1h. Each count is equal to 520 times the timeout period of functional clock. For example, with 8MHz functional clock and a 100KHz operating I2C clock, one timeout period will be equal to (1 / 8MHz) * 520 or 65 us."] pub type TIMEOUT_CTL_TCNTLA_R = crate :: FieldReader ; # [doc = "Field `TIMEOUT_CTL_TCNTLA` writer - Timeout counter A load value Counter A is used for SCL low detection. This field contains the upper 8 bits of a 12-bit pre-load value for the Timeout A count. NOTE: The value of CNTLA must be greater than 1h. Each count is equal to 520 times the timeout period of functional clock. For example, with 8MHz functional clock and a 100KHz operating I2C clock, one timeout period will be equal to (1 / 8MHz) * 520 or 65 us."] pub type TIMEOUT_CTL_TCNTLA_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 8 , O > ; # [doc = "Field `TIMEOUT_CTL_TCNTAEN` reader - Timeout Counter A Enable"] pub type TIMEOUT_CTL_TCNTAEN_R = crate :: BitReader < TIMEOUT_CTL_TCNTAEN_A > ; # [doc = "Timeout Counter A Enable\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum TIMEOUT_CTL_TCNTAEN_A { # [doc = "0: DISABLE"] TIMEOUT_CTL_TCNTAEN_DISABLE = 0 , # [doc = "1: ENABLE"] TIMEOUT_CTL_TCNTAEN_ENABLE = 1 , } impl From < TIMEOUT_CTL_TCNTAEN_A > for bool { # [inline (always)] fn from (variant : TIMEOUT_CTL_TCNTAEN_A) -> Self { variant as u8 != 0 } } impl TIMEOUT_CTL_TCNTAEN_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> TIMEOUT_CTL_TCNTAEN_A { match self . bits { false => TIMEOUT_CTL_TCNTAEN_A :: TIMEOUT_CTL_TCNTAEN_DISABLE , true => TIMEOUT_CTL_TCNTAEN_A :: TIMEOUT_CTL_TCNTAEN_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_timeout_ctl_tcntaen_disable (& self) -> bool { * self == TIMEOUT_CTL_TCNTAEN_A :: TIMEOUT_CTL_TCNTAEN_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_timeout_ctl_tcntaen_enable (& self) -> bool { * self == TIMEOUT_CTL_TCNTAEN_A :: TIMEOUT_CTL_TCNTAEN_ENABLE } } # [doc = "Field `TIMEOUT_CTL_TCNTAEN` writer - Timeout Counter A Enable"] pub type TIMEOUT_CTL_TCNTAEN_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , TIMEOUT_CTL_TCNTAEN_A > ; impl < 'a , REG , const O : u8 > TIMEOUT_CTL_TCNTAEN_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn timeout_ctl_tcntaen_disable (self) -> & 'a mut crate :: W < REG > { self . variant (TIMEOUT_CTL_TCNTAEN_A :: TIMEOUT_CTL_TCNTAEN_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn timeout_ctl_tcntaen_enable (self) -> & 'a mut crate :: W < REG > { self . variant (TIMEOUT_CTL_TCNTAEN_A :: TIMEOUT_CTL_TCNTAEN_ENABLE) } } # [doc = "Field `TIMEOUT_CTL_TCNTLB` reader - Timeout Count B Load: Counter B is used for SCL High Detection. This field contains the upper 8 bits of a 12-bit pre-load value for the Timeout B count. NOTE: The value of CNTLB must be greater than 1h. Each count is equal to 1* clock period. For example, with 10MHz functional clock one timeout period will be equal to1*100ns."] pub type TIMEOUT_CTL_TCNTLB_R = crate :: FieldReader ; # [doc = "Field `TIMEOUT_CTL_TCNTLB` writer - Timeout Count B Load: Counter B is used for SCL High Detection. This field contains the upper 8 bits of a 12-bit pre-load value for the Timeout B count. NOTE: The value of CNTLB must be greater than 1h. Each count is equal to 1* clock period. For example, with 10MHz functional clock one timeout period will be equal to1*100ns."] pub type TIMEOUT_CTL_TCNTLB_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 8 , O > ; # [doc = "Field `TIMEOUT_CTL_TCNTBEN` reader - Timeout Counter B Enable"] pub type TIMEOUT_CTL_TCNTBEN_R = crate :: BitReader < TIMEOUT_CTL_TCNTBEN_A > ; # [doc = "Timeout Counter B Enable\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum TIMEOUT_CTL_TCNTBEN_A { # [doc = "0: DISABLE"] TIMEOUT_CTL_TCNTBEN_DISABLE = 0 , # [doc = "1: ENABLE"] TIMEOUT_CTL_TCNTBEN_ENABLE = 1 , } impl From < TIMEOUT_CTL_TCNTBEN_A > for bool { # [inline (always)] fn from (variant : TIMEOUT_CTL_TCNTBEN_A) -> Self { variant as u8 != 0 } } impl TIMEOUT_CTL_TCNTBEN_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> TIMEOUT_CTL_TCNTBEN_A { match self . bits { false => TIMEOUT_CTL_TCNTBEN_A :: TIMEOUT_CTL_TCNTBEN_DISABLE , true => TIMEOUT_CTL_TCNTBEN_A :: TIMEOUT_CTL_TCNTBEN_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_timeout_ctl_tcntben_disable (& self) -> bool { * self == TIMEOUT_CTL_TCNTBEN_A :: TIMEOUT_CTL_TCNTBEN_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_timeout_ctl_tcntben_enable (& self) -> bool { * self == TIMEOUT_CTL_TCNTBEN_A :: TIMEOUT_CTL_TCNTBEN_ENABLE } } # [doc = "Field `TIMEOUT_CTL_TCNTBEN` writer - Timeout Counter B Enable"] pub type TIMEOUT_CTL_TCNTBEN_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , TIMEOUT_CTL_TCNTBEN_A > ; impl < 'a , REG , const O : u8 > TIMEOUT_CTL_TCNTBEN_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn timeout_ctl_tcntben_disable (self) -> & 'a mut crate :: W < REG > { self . variant (TIMEOUT_CTL_TCNTBEN_A :: TIMEOUT_CTL_TCNTBEN_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn timeout_ctl_tcntben_enable (self) -> & 'a mut crate :: W < REG > { self . variant (TIMEOUT_CTL_TCNTBEN_A :: TIMEOUT_CTL_TCNTBEN_ENABLE) } } impl R { # [doc = "Bits 0:7 - Timeout counter A load value Counter A is used for SCL low detection. This field contains the upper 8 bits of a 12-bit pre-load value for the Timeout A count. NOTE: The value of CNTLA must be greater than 1h. Each count is equal to 520 times the timeout period of functional clock. For example, with 8MHz functional clock and a 100KHz operating I2C clock, one timeout period will be equal to (1 / 8MHz) * 520 or 65 us."] # [inline (always)] pub fn timeout_ctl_tcntla (& self) -> TIMEOUT_CTL_TCNTLA_R { TIMEOUT_CTL_TCNTLA_R :: new ((self . bits & 0xff) as u8) } # [doc = "Bit 15 - Timeout Counter A Enable"] # [inline (always)] pub fn timeout_ctl_tcntaen (& self) -> TIMEOUT_CTL_TCNTAEN_R { TIMEOUT_CTL_TCNTAEN_R :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bits 16:23 - Timeout Count B Load: Counter B is used for SCL High Detection. This field contains the upper 8 bits of a 12-bit pre-load value for the Timeout B count. NOTE: The value of CNTLB must be greater than 1h. Each count is equal to 1* clock period. For example, with 10MHz functional clock one timeout period will be equal to1*100ns."] # [inline (always)] pub fn timeout_ctl_tcntlb (& self) -> TIMEOUT_CTL_TCNTLB_R { TIMEOUT_CTL_TCNTLB_R :: new (((self . bits >> 16) & 0xff) as u8) } # [doc = "Bit 31 - Timeout Counter B Enable"] # [inline (always)] pub fn timeout_ctl_tcntben (& self) -> TIMEOUT_CTL_TCNTBEN_R { TIMEOUT_CTL_TCNTBEN_R :: new (((self . bits >> 31) & 1) != 0) } } impl W { # [doc = "Bits 0:7 - Timeout counter A load value Counter A is used for SCL low detection. This field contains the upper 8 bits of a 12-bit pre-load value for the Timeout A count. NOTE: The value of CNTLA must be greater than 1h. Each count is equal to 520 times the timeout period of functional clock. For example, with 8MHz functional clock and a 100KHz operating I2C clock, one timeout period will be equal to (1 / 8MHz) * 520 or 65 us."] # [inline (always)] # [must_use] pub fn timeout_ctl_tcntla (& mut self) -> TIMEOUT_CTL_TCNTLA_W < TIMEOUT_CTL_SPEC , 0 > { TIMEOUT_CTL_TCNTLA_W :: new (self) } # [doc = "Bit 15 - Timeout Counter A Enable"] # [inline (always)] # [must_use] pub fn timeout_ctl_tcntaen (& mut self) -> TIMEOUT_CTL_TCNTAEN_W < TIMEOUT_CTL_SPEC , 15 > { TIMEOUT_CTL_TCNTAEN_W :: new (self) } # [doc = "Bits 16:23 - Timeout Count B Load: Counter B is used for SCL High Detection. This field contains the upper 8 bits of a 12-bit pre-load value for the Timeout B count. NOTE: The value of CNTLB must be greater than 1h. Each count is equal to 1* clock period. For example, with 10MHz functional clock one timeout period will be equal to1*100ns."] # [inline (always)] # [must_use] pub fn timeout_ctl_tcntlb (& mut self) -> TIMEOUT_CTL_TCNTLB_W <'_, TIMEOUT_CTL_SPEC , 16 > { TIMEOUT_CTL_TCNTLB_W :: new (self) } # [doc = "Bit 31 - Timeout Counter B Enable"] # [inline (always)] # [must_use] pub fn timeout_ctl_tcntben (& mut self) -> TIMEOUT_CTL_TCNTBEN_W < TIMEOUT_CTL_SPEC , 31 > { TIMEOUT_CTL_TCNTBEN_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "I2C Timeout Count Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`timeout_ctl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`timeout_ctl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct TIMEOUT_CTL_SPEC ; impl crate :: RegisterSpec for TIMEOUT_CTL_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`timeout_ctl::R`](R) reader structure"] impl crate :: Readable for TIMEOUT_CTL_SPEC { } # [doc = "`write(|w| ..)` method takes [`timeout_ctl::W`](W) writer structure"] impl crate :: Writable for TIMEOUT_CTL_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets TIMEOUT_CTL to value 0x0002_0002"] impl crate :: Resettable for TIMEOUT_CTL_SPEC { const RESET_VALUE : Self :: Ux = 0x0002_0002 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/opa0/cfg.rs:1:16556 [INFO] [stdout] | [INFO] [stdout] 1 | ... [must_use] pub fn cfg_chop (& mut self) -> CFG_CHOP_W < CFG_SPEC , 0 > { CFG_CHOP_W :: new (self) } # [doc = "Bit 2 - Enable output p... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `CFG` reader"] pub type R = crate :: R < CFG_SPEC > ; # [doc = "Register `CFG` writer"] pub type W = crate :: W < CFG_SPEC > ; # [doc = "Field `CFG_CHOP` reader - Chopping enable."] pub type CFG_CHOP_R = crate :: FieldReader < CFG_CHOP_A > ; # [doc = "Chopping enable.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum CFG_CHOP_A { # [doc = "0: OFF"] CFG_CHOP_OFF = 0 , # [doc = "1: ON"] CFG_CHOP_ON = 1 , # [doc = "2: AVGON"] CFG_CHOP_AVGON = 2 , } impl From < CFG_CHOP_A > for u8 { # [inline (always)] fn from (variant : CFG_CHOP_A) -> Self { variant as _ } } impl crate :: FieldSpec for CFG_CHOP_A { type Ux = u8 ; } impl CFG_CHOP_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < CFG_CHOP_A > { match self . bits { 0 => Some (CFG_CHOP_A :: CFG_CHOP_OFF) , 1 => Some (CFG_CHOP_A :: CFG_CHOP_ON) , 2 => Some (CFG_CHOP_A :: CFG_CHOP_AVGON) , _ => None , } } # [doc = "OFF"] # [inline (always)] pub fn is_cfg_chop_off (& self) -> bool { * self == CFG_CHOP_A :: CFG_CHOP_OFF } # [doc = "ON"] # [inline (always)] pub fn is_cfg_chop_on (& self) -> bool { * self == CFG_CHOP_A :: CFG_CHOP_ON } # [doc = "AVGON"] # [inline (always)] pub fn is_cfg_chop_avgon (& self) -> bool { * self == CFG_CHOP_A :: CFG_CHOP_AVGON } } # [doc = "Field `CFG_CHOP` writer - Chopping enable."] pub type CFG_CHOP_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 2 , O , CFG_CHOP_A > ; impl < 'a , REG , const O : u8 > CFG_CHOP_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "OFF"] # [inline (always)] pub fn cfg_chop_off (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_CHOP_A :: CFG_CHOP_OFF) } # [doc = "ON"] # [inline (always)] pub fn cfg_chop_on (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_CHOP_A :: CFG_CHOP_ON) } # [doc = "AVGON"] # [inline (always)] pub fn cfg_chop_avgon (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_CHOP_A :: CFG_CHOP_AVGON) } } # [doc = "Field `CFG_OUTPIN` reader - Enable output pin"] pub type CFG_OUTPIN_R = crate :: BitReader < CFG_OUTPIN_A > ; # [doc = "Enable output pin\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CFG_OUTPIN_A { # [doc = "0: DISABLED"] CFG_OUTPIN_DISABLED = 0 , # [doc = "1: ENABLED"] CFG_OUTPIN_ENABLED = 1 , } impl From < CFG_OUTPIN_A > for bool { # [inline (always)] fn from (variant : CFG_OUTPIN_A) -> Self { variant as u8 != 0 } } impl CFG_OUTPIN_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CFG_OUTPIN_A { match self . bits { false => CFG_OUTPIN_A :: CFG_OUTPIN_DISABLED , true => CFG_OUTPIN_A :: CFG_OUTPIN_ENABLED , } } # [doc = "DISABLED"] # [inline (always)] pub fn is_cfg_outpin_disabled (& self) -> bool { * self == CFG_OUTPIN_A :: CFG_OUTPIN_DISABLED } # [doc = "ENABLED"] # [inline (always)] pub fn is_cfg_outpin_enabled (& self) -> bool { * self == CFG_OUTPIN_A :: CFG_OUTPIN_ENABLED } } # [doc = "Field `CFG_OUTPIN` writer - Enable output pin"] pub type CFG_OUTPIN_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CFG_OUTPIN_A > ; impl < 'a , REG , const O : u8 > CFG_OUTPIN_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLED"] # [inline (always)] pub fn cfg_outpin_disabled (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_OUTPIN_A :: CFG_OUTPIN_DISABLED) } # [doc = "ENABLED"] # [inline (always)] pub fn cfg_outpin_enabled (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_OUTPIN_A :: CFG_OUTPIN_ENABLED) } } # [doc = "Field `CFG_PSEL` reader - Positive OA input selection. Please refer to the device specific datasheet for exact channels available."] pub type CFG_PSEL_R = crate :: FieldReader < CFG_PSEL_A > ; # [doc = "Positive OA input selection. Please refer to the device specific datasheet for exact channels available.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum CFG_PSEL_A { # [doc = "0: NC"] CFG_PSEL_NC = 0 , # [doc = "1: EXTPIN0"] CFG_PSEL_EXTPIN0 = 1 , # [doc = "2: EXTPIN1"] CFG_PSEL_EXTPIN1 = 2 , # [doc = "3: DAC12OUT"] CFG_PSEL_DAC12OUT = 3 , # [doc = "4: DAC8OUT"] CFG_PSEL_DAC8OUT = 4 , # [doc = "5: VREF"] CFG_PSEL_VREF = 5 , # [doc = "6: OANM1RTOP"] CFG_PSEL_OANM1RTOP = 6 , # [doc = "7: GPAMP_OUT_INT"] CFG_PSEL_GPAMP_OUT_INT = 7 , # [doc = "8: VSS"] CFG_PSEL_VSS = 8 , } impl From < CFG_PSEL_A > for u8 { # [inline (always)] fn from (variant : CFG_PSEL_A) -> Self { variant as _ } } impl crate :: FieldSpec for CFG_PSEL_A { type Ux = u8 ; } impl CFG_PSEL_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < CFG_PSEL_A > { match self . bits { 0 => Some (CFG_PSEL_A :: CFG_PSEL_NC) , 1 => Some (CFG_PSEL_A :: CFG_PSEL_EXTPIN0) , 2 => Some (CFG_PSEL_A :: CFG_PSEL_EXTPIN1) , 3 => Some (CFG_PSEL_A :: CFG_PSEL_DAC12OUT) , 4 => Some (CFG_PSEL_A :: CFG_PSEL_DAC8OUT) , 5 => Some (CFG_PSEL_A :: CFG_PSEL_VREF) , 6 => Some (CFG_PSEL_A :: CFG_PSEL_OANM1RTOP) , 7 => Some (CFG_PSEL_A :: CFG_PSEL_GPAMP_OUT_INT) , 8 => Some (CFG_PSEL_A :: CFG_PSEL_VSS) , _ => None , } } # [doc = "NC"] # [inline (always)] pub fn is_cfg_psel_nc (& self) -> bool { * self == CFG_PSEL_A :: CFG_PSEL_NC } # [doc = "EXTPIN0"] # [inline (always)] pub fn is_cfg_psel_extpin0 (& self) -> bool { * self == CFG_PSEL_A :: CFG_PSEL_EXTPIN0 } # [doc = "EXTPIN1"] # [inline (always)] pub fn is_cfg_psel_extpin1 (& self) -> bool { * self == CFG_PSEL_A :: CFG_PSEL_EXTPIN1 } # [doc = "DAC12OUT"] # [inline (always)] pub fn is_cfg_psel_dac12out (& self) -> bool { * self == CFG_PSEL_A :: CFG_PSEL_DAC12OUT } # [doc = "DAC8OUT"] # [inline (always)] pub fn is_cfg_psel_dac8out (& self) -> bool { * self == CFG_PSEL_A :: CFG_PSEL_DAC8OUT } # [doc = "VREF"] # [inline (always)] pub fn is_cfg_psel_vref (& self) -> bool { * self == CFG_PSEL_A :: CFG_PSEL_VREF } # [doc = "OANM1RTOP"] # [inline (always)] pub fn is_cfg_psel_oanm1rtop (& self) -> bool { * self == CFG_PSEL_A :: CFG_PSEL_OANM1RTOP } # [doc = "GPAMP_OUT_INT"] # [inline (always)] pub fn is_cfg_psel_gpamp_out_int (& self) -> bool { * self == CFG_PSEL_A :: CFG_PSEL_GPAMP_OUT_INT } # [doc = "VSS"] # [inline (always)] pub fn is_cfg_psel_vss (& self) -> bool { * self == CFG_PSEL_A :: CFG_PSEL_VSS } } # [doc = "Field `CFG_PSEL` writer - Positive OA input selection. Please refer to the device specific datasheet for exact channels available."] pub type CFG_PSEL_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 4 , O , CFG_PSEL_A > ; impl < 'a , REG , const O : u8 > CFG_PSEL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "NC"] # [inline (always)] pub fn cfg_psel_nc (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_PSEL_A :: CFG_PSEL_NC) } # [doc = "EXTPIN0"] # [inline (always)] pub fn cfg_psel_extpin0 (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_PSEL_A :: CFG_PSEL_EXTPIN0) } # [doc = "EXTPIN1"] # [inline (always)] pub fn cfg_psel_extpin1 (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_PSEL_A :: CFG_PSEL_EXTPIN1) } # [doc = "DAC12OUT"] # [inline (always)] pub fn cfg_psel_dac12out (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_PSEL_A :: CFG_PSEL_DAC12OUT) } # [doc = "DAC8OUT"] # [inline (always)] pub fn cfg_psel_dac8out (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_PSEL_A :: CFG_PSEL_DAC8OUT) } # [doc = "VREF"] # [inline (always)] pub fn cfg_psel_vref (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_PSEL_A :: CFG_PSEL_VREF) } # [doc = "OANM1RTOP"] # [inline (always)] pub fn cfg_psel_oanm1rtop (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_PSEL_A :: CFG_PSEL_OANM1RTOP) } # [doc = "GPAMP_OUT_INT"] # [inline (always)] pub fn cfg_psel_gpamp_out_int (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_PSEL_A :: CFG_PSEL_GPAMP_OUT_INT) } # [doc = "VSS"] # [inline (always)] pub fn cfg_psel_vss (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_PSEL_A :: CFG_PSEL_VSS) } } # [doc = "Field `CFG_NSEL` reader - Negative OA input selection. Please refer to the device specific datasheet for exact channels available."] pub type CFG_NSEL_R = crate :: FieldReader < CFG_NSEL_A > ; # [doc = "Negative OA input selection. Please refer to the device specific datasheet for exact channels available.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum CFG_NSEL_A { # [doc = "0: NC"] CFG_NSEL_NC = 0 , # [doc = "1: EXTPIN0"] CFG_NSEL_EXTPIN0 = 1 , # [doc = "2: EXTPIN1"] CFG_NSEL_EXTPIN1 = 2 , # [doc = "3: OANP1RBOT"] CFG_NSEL_OANP1RBOT = 3 , # [doc = "4: OANRTAP"] CFG_NSEL_OANRTAP = 4 , # [doc = "5: OANRTOP"] CFG_NSEL_OANRTOP = 5 , # [doc = "6: SPARE"] CFG_NSEL_SPARE = 6 , } impl From < CFG_NSEL_A > for u8 { # [inline (always)] fn from (variant : CFG_NSEL_A) -> Self { variant as _ } } impl crate :: FieldSpec for CFG_NSEL_A { type Ux = u8 ; } impl CFG_NSEL_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < CFG_NSEL_A > { match self . bits { 0 => Some (CFG_NSEL_A :: CFG_NSEL_NC) , 1 => Some (CFG_NSEL_A :: CFG_NSEL_EXTPIN0) , 2 => Some (CFG_NSEL_A :: CFG_NSEL_EXTPIN1) , 3 => Some (CFG_NSEL_A :: CFG_NSEL_OANP1RBOT) , 4 => Some (CFG_NSEL_A :: CFG_NSEL_OANRTAP) , 5 => Some (CFG_NSEL_A :: CFG_NSEL_OANRTOP) , 6 => Some (CFG_NSEL_A :: CFG_NSEL_SPARE) , _ => None , } } # [doc = "NC"] # [inline (always)] pub fn is_cfg_nsel_nc (& self) -> bool { * self == CFG_NSEL_A :: CFG_NSEL_NC } # [doc = "EXTPIN0"] # [inline (always)] pub fn is_cfg_nsel_extpin0 (& self) -> bool { * self == CFG_NSEL_A :: CFG_NSEL_EXTPIN0 } # [doc = "EXTPIN1"] # [inline (always)] pub fn is_cfg_nsel_extpin1 (& self) -> bool { * self == CFG_NSEL_A :: CFG_NSEL_EXTPIN1 } # [doc = "OANP1RBOT"] # [inline (always)] pub fn is_cfg_nsel_oanp1rbot (& self) -> bool { * self == CFG_NSEL_A :: CFG_NSEL_OANP1RBOT } # [doc = "OANRTAP"] # [inline (always)] pub fn is_cfg_nsel_oanrtap (& self) -> bool { * self == CFG_NSEL_A :: CFG_NSEL_OANRTAP } # [doc = "OANRTOP"] # [inline (always)] pub fn is_cfg_nsel_oanrtop (& self) -> bool { * self == CFG_NSEL_A :: CFG_NSEL_OANRTOP } # [doc = "SPARE"] # [inline (always)] pub fn is_cfg_nsel_spare (& self) -> bool { * self == CFG_NSEL_A :: CFG_NSEL_SPARE } } # [doc = "Field `CFG_NSEL` writer - Negative OA input selection. Please refer to the device specific datasheet for exact channels available."] pub type CFG_NSEL_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 3 , O , CFG_NSEL_A > ; impl < 'a , REG , const O : u8 > CFG_NSEL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "NC"] # [inline (always)] pub fn cfg_nsel_nc (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_NSEL_A :: CFG_NSEL_NC) } # [doc = "EXTPIN0"] # [inline (always)] pub fn cfg_nsel_extpin0 (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_NSEL_A :: CFG_NSEL_EXTPIN0) } # [doc = "EXTPIN1"] # [inline (always)] pub fn cfg_nsel_extpin1 (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_NSEL_A :: CFG_NSEL_EXTPIN1) } # [doc = "OANP1RBOT"] # [inline (always)] pub fn cfg_nsel_oanp1rbot (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_NSEL_A :: CFG_NSEL_OANP1RBOT) } # [doc = "OANRTAP"] # [inline (always)] pub fn cfg_nsel_oanrtap (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_NSEL_A :: CFG_NSEL_OANRTAP) } # [doc = "OANRTOP"] # [inline (always)] pub fn cfg_nsel_oanrtop (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_NSEL_A :: CFG_NSEL_OANRTOP) } # [doc = "SPARE"] # [inline (always)] pub fn cfg_nsel_spare (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_NSEL_A :: CFG_NSEL_SPARE) } } # [doc = "Field `CFG_MSEL` reader - MSEL Mux selection. Please refer to the device specific datasheet for exact channels available."] pub type CFG_MSEL_R = crate :: FieldReader < CFG_MSEL_A > ; # [doc = "MSEL Mux selection. Please refer to the device specific datasheet for exact channels available.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum CFG_MSEL_A { # [doc = "0: NC"] CFG_MSEL_NC = 0 , # [doc = "1: EXTNPIN1"] CFG_MSEL_EXTNPIN1 = 1 , # [doc = "2: VSS"] CFG_MSEL_VSS = 2 , # [doc = "3: DAC12OUT"] CFG_MSEL_DAC12OUT = 3 , # [doc = "4: OANM1RTOP"] CFG_MSEL_OANM1RTOP = 4 , } impl From < CFG_MSEL_A > for u8 { # [inline (always)] fn from (variant : CFG_MSEL_A) -> Self { variant as _ } } impl crate :: FieldSpec for CFG_MSEL_A { type Ux = u8 ; } impl CFG_MSEL_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < CFG_MSEL_A > { match self . bits { 0 => Some (CFG_MSEL_A :: CFG_MSEL_NC) , 1 => Some (CFG_MSEL_A :: CFG_MSEL_EXTNPIN1) , 2 => Some (CFG_MSEL_A :: CFG_MSEL_VSS) , 3 => Some (CFG_MSEL_A :: CFG_MSEL_DAC12OUT) , 4 => Some (CFG_MSEL_A :: CFG_MSEL_OANM1RTOP) , _ => None , } } # [doc = "NC"] # [inline (always)] pub fn is_cfg_msel_nc (& self) -> bool { * self == CFG_MSEL_A :: CFG_MSEL_NC } # [doc = "EXTNPIN1"] # [inline (always)] pub fn is_cfg_msel_extnpin1 (& self) -> bool { * self == CFG_MSEL_A :: CFG_MSEL_EXTNPIN1 } # [doc = "VSS"] # [inline (always)] pub fn is_cfg_msel_vss (& self) -> bool { * self == CFG_MSEL_A :: CFG_MSEL_VSS } # [doc = "DAC12OUT"] # [inline (always)] pub fn is_cfg_msel_dac12out (& self) -> bool { * self == CFG_MSEL_A :: CFG_MSEL_DAC12OUT } # [doc = "OANM1RTOP"] # [inline (always)] pub fn is_cfg_msel_oanm1rtop (& self) -> bool { * self == CFG_MSEL_A :: CFG_MSEL_OANM1RTOP } } # [doc = "Field `CFG_MSEL` writer - MSEL Mux selection. Please refer to the device specific datasheet for exact channels available."] pub type CFG_MSEL_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 3 , O , CFG_MSEL_A > ; impl < 'a , REG , const O : u8 > CFG_MSEL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "NC"] # [inline (always)] pub fn cfg_msel_nc (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_MSEL_A :: CFG_MSEL_NC) } # [doc = "EXTNPIN1"] # [inline (always)] pub fn cfg_msel_extnpin1 (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_MSEL_A :: CFG_MSEL_EXTNPIN1) } # [doc = "VSS"] # [inline (always)] pub fn cfg_msel_vss (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_MSEL_A :: CFG_MSEL_VSS) } # [doc = "DAC12OUT"] # [inline (always)] pub fn cfg_msel_dac12out (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_MSEL_A :: CFG_MSEL_DAC12OUT) } # [doc = "OANM1RTOP"] # [inline (always)] pub fn cfg_msel_oanm1rtop (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_MSEL_A :: CFG_MSEL_OANM1RTOP) } } # [doc = "Field `CFG_GAIN` reader - Gain setting. Refer to TRM for enumeration information."] pub type CFG_GAIN_R = crate :: FieldReader ; # [doc = "Field `CFG_GAIN` writer - Gain setting. Refer to TRM for enumeration information."] pub type CFG_GAIN_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 3 , O > ; impl R { # [doc = "Bits 0:1 - Chopping enable."] # [inline (always)] pub fn cfg_chop (& self) -> CFG_CHOP_R { CFG_CHOP_R :: new ((self . bits & 3) as u8) } # [doc = "Bit 2 - Enable output pin"] # [inline (always)] pub fn cfg_outpin (& self) -> CFG_OUTPIN_R { CFG_OUTPIN_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bits 3:6 - Positive OA input selection. Please refer to the device specific datasheet for exact channels available."] # [inline (always)] pub fn cfg_psel (& self) -> CFG_PSEL_R { CFG_PSEL_R :: new (((self . bits >> 3) & 0x0f) as u8) } # [doc = "Bits 7:9 - Negative OA input selection. Please refer to the device specific datasheet for exact channels available."] # [inline (always)] pub fn cfg_nsel (& self) -> CFG_NSEL_R { CFG_NSEL_R :: new (((self . bits >> 7) & 7) as u8) } # [doc = "Bits 10:12 - MSEL Mux selection. Please refer to the device specific datasheet for exact channels available."] # [inline (always)] pub fn cfg_msel (& self) -> CFG_MSEL_R { CFG_MSEL_R :: new (((self . bits >> 10) & 7) as u8) } # [doc = "Bits 13:15 - Gain setting. Refer to TRM for enumeration information."] # [inline (always)] pub fn cfg_gain (& self) -> CFG_GAIN_R { CFG_GAIN_R :: new (((self . bits >> 13) & 7) as u8) } } impl W { # [doc = "Bits 0:1 - Chopping enable."] # [inline (always)] # [must_use] pub fn cfg_chop (& mut self) -> CFG_CHOP_W <'_, CFG_SPEC , 0 > { CFG_CHOP_W :: new (self) } # [doc = "Bit 2 - Enable output pin"] # [inline (always)] # [must_use] pub fn cfg_outpin (& mut self) -> CFG_OUTPIN_W < CFG_SPEC , 2 > { CFG_OUTPIN_W :: new (self) } # [doc = "Bits 3:6 - Positive OA input selection. Please refer to the device specific datasheet for exact channels available."] # [inline (always)] # [must_use] pub fn cfg_psel (& mut self) -> CFG_PSEL_W < CFG_SPEC , 3 > { CFG_PSEL_W :: new (self) } # [doc = "Bits 7:9 - Negative OA input selection. Please refer to the device specific datasheet for exact channels available."] # [inline (always)] # [must_use] pub fn cfg_nsel (& mut self) -> CFG_NSEL_W < CFG_SPEC , 7 > { CFG_NSEL_W :: new (self) } # [doc = "Bits 10:12 - MSEL Mux selection. Please refer to the device specific datasheet for exact channels available."] # [inline (always)] # [must_use] pub fn cfg_msel (& mut self) -> CFG_MSEL_W < CFG_SPEC , 10 > { CFG_MSEL_W :: new (self) } # [doc = "Bits 13:15 - Gain setting. Refer to TRM for enumeration information."] # [inline (always)] # [must_use] pub fn cfg_gain (& mut self) -> CFG_GAIN_W < CFG_SPEC , 13 > { CFG_GAIN_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Configuration Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CFG_SPEC ; impl crate :: RegisterSpec for CFG_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`cfg::R`](R) reader structure"] impl crate :: Readable for CFG_SPEC { } # [doc = "`write(|w| ..)` method takes [`cfg::W`](W) writer structure"] impl crate :: Writable for CFG_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets CFG to value 0"] impl crate :: Resettable for CFG_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/i2c0/sctr.rs:1:26010 [INFO] [stdout] | [INFO] [stdout] 1 | ...n sctr_rxfull_on_rreq (& mut self) -> SCTR_RXFULL_ON_RREQ_W < SCTR_SPEC , 6 > { SCTR_RXFULL_ON_RREQ_W :: new (self) } # [doc = "Bit 7 ... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `SCTR` reader"] pub type R = crate :: R < SCTR_SPEC > ; # [doc = "Register `SCTR` writer"] pub type W = crate :: W < SCTR_SPEC > ; # [doc = "Field `SCTR_ACTIVE` reader - Device Active. Setting this bit enables the slave functionality."] pub type SCTR_ACTIVE_R = crate :: BitReader < SCTR_ACTIVE_A > ; # [doc = "Device Active. Setting this bit enables the slave functionality.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum SCTR_ACTIVE_A { # [doc = "0: DISABLE"] SCTR_ACTIVE_DISABLE = 0 , # [doc = "1: ENABLE"] SCTR_ACTIVE_ENABLE = 1 , } impl From < SCTR_ACTIVE_A > for bool { # [inline (always)] fn from (variant : SCTR_ACTIVE_A) -> Self { variant as u8 != 0 } } impl SCTR_ACTIVE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> SCTR_ACTIVE_A { match self . bits { false => SCTR_ACTIVE_A :: SCTR_ACTIVE_DISABLE , true => SCTR_ACTIVE_A :: SCTR_ACTIVE_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_sctr_active_disable (& self) -> bool { * self == SCTR_ACTIVE_A :: SCTR_ACTIVE_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_sctr_active_enable (& self) -> bool { * self == SCTR_ACTIVE_A :: SCTR_ACTIVE_ENABLE } } # [doc = "Field `SCTR_ACTIVE` writer - Device Active. Setting this bit enables the slave functionality."] pub type SCTR_ACTIVE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , SCTR_ACTIVE_A > ; impl < 'a , REG , const O : u8 > SCTR_ACTIVE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn sctr_active_disable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_ACTIVE_A :: SCTR_ACTIVE_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn sctr_active_enable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_ACTIVE_A :: SCTR_ACTIVE_ENABLE) } } # [doc = "Field `SCTR_GENCALL` reader - General call response enable. This bit is only available in UCBxI2COA0. Modify only when UCSWRST = 1. 0b = Do not respond to a general call 1b = Respond to a general call"] pub type SCTR_GENCALL_R = crate :: BitReader < SCTR_GENCALL_A > ; # [doc = "General call response enable. This bit is only available in UCBxI2COA0. Modify only when UCSWRST = 1. 0b = Do not respond to a general call 1b = Respond to a general call\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum SCTR_GENCALL_A { # [doc = "0: DISABLE"] SCTR_GENCALL_DISABLE = 0 , # [doc = "1: ENABLE"] SCTR_GENCALL_ENABLE = 1 , } impl From < SCTR_GENCALL_A > for bool { # [inline (always)] fn from (variant : SCTR_GENCALL_A) -> Self { variant as u8 != 0 } } impl SCTR_GENCALL_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> SCTR_GENCALL_A { match self . bits { false => SCTR_GENCALL_A :: SCTR_GENCALL_DISABLE , true => SCTR_GENCALL_A :: SCTR_GENCALL_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_sctr_gencall_disable (& self) -> bool { * self == SCTR_GENCALL_A :: SCTR_GENCALL_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_sctr_gencall_enable (& self) -> bool { * self == SCTR_GENCALL_A :: SCTR_GENCALL_ENABLE } } # [doc = "Field `SCTR_GENCALL` writer - General call response enable. This bit is only available in UCBxI2COA0. Modify only when UCSWRST = 1. 0b = Do not respond to a general call 1b = Respond to a general call"] pub type SCTR_GENCALL_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , SCTR_GENCALL_A > ; impl < 'a , REG , const O : u8 > SCTR_GENCALL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn sctr_gencall_disable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_GENCALL_A :: SCTR_GENCALL_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn sctr_gencall_enable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_GENCALL_A :: SCTR_GENCALL_ENABLE) } } # [doc = "Field `SCTR_SCLKSTRETCH` reader - Slave Clock Stretch Enable"] pub type SCTR_SCLKSTRETCH_R = crate :: BitReader < SCTR_SCLKSTRETCH_A > ; # [doc = "Slave Clock Stretch Enable\n\nValue on reset: 1"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum SCTR_SCLKSTRETCH_A { # [doc = "0: DISABLE"] SCTR_SCLKSTRETCH_DISABLE = 0 , # [doc = "1: ENABLE"] SCTR_SCLKSTRETCH_ENABLE = 1 , } impl From < SCTR_SCLKSTRETCH_A > for bool { # [inline (always)] fn from (variant : SCTR_SCLKSTRETCH_A) -> Self { variant as u8 != 0 } } impl SCTR_SCLKSTRETCH_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> SCTR_SCLKSTRETCH_A { match self . bits { false => SCTR_SCLKSTRETCH_A :: SCTR_SCLKSTRETCH_DISABLE , true => SCTR_SCLKSTRETCH_A :: SCTR_SCLKSTRETCH_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_sctr_sclkstretch_disable (& self) -> bool { * self == SCTR_SCLKSTRETCH_A :: SCTR_SCLKSTRETCH_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_sctr_sclkstretch_enable (& self) -> bool { * self == SCTR_SCLKSTRETCH_A :: SCTR_SCLKSTRETCH_ENABLE } } # [doc = "Field `SCTR_SCLKSTRETCH` writer - Slave Clock Stretch Enable"] pub type SCTR_SCLKSTRETCH_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , SCTR_SCLKSTRETCH_A > ; impl < 'a , REG , const O : u8 > SCTR_SCLKSTRETCH_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn sctr_sclkstretch_disable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_SCLKSTRETCH_A :: SCTR_SCLKSTRETCH_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn sctr_sclkstretch_enable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_SCLKSTRETCH_A :: SCTR_SCLKSTRETCH_ENABLE) } } # [doc = "Field `SCTR_TXEMPTY_ON_TREQ` reader - Tx Empty Interrupt on TREQ"] pub type SCTR_TXEMPTY_ON_TREQ_R = crate :: BitReader < SCTR_TXEMPTY_ON_TREQ_A > ; # [doc = "Tx Empty Interrupt on TREQ\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum SCTR_TXEMPTY_ON_TREQ_A { # [doc = "0: DISABLE"] SCTR_TXEMPTY_ON_TREQ_DISABLE = 0 , # [doc = "1: ENABLE"] SCTR_TXEMPTY_ON_TREQ_ENABLE = 1 , } impl From < SCTR_TXEMPTY_ON_TREQ_A > for bool { # [inline (always)] fn from (variant : SCTR_TXEMPTY_ON_TREQ_A) -> Self { variant as u8 != 0 } } impl SCTR_TXEMPTY_ON_TREQ_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> SCTR_TXEMPTY_ON_TREQ_A { match self . bits { false => SCTR_TXEMPTY_ON_TREQ_A :: SCTR_TXEMPTY_ON_TREQ_DISABLE , true => SCTR_TXEMPTY_ON_TREQ_A :: SCTR_TXEMPTY_ON_TREQ_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_sctr_txempty_on_treq_disable (& self) -> bool { * self == SCTR_TXEMPTY_ON_TREQ_A :: SCTR_TXEMPTY_ON_TREQ_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_sctr_txempty_on_treq_enable (& self) -> bool { * self == SCTR_TXEMPTY_ON_TREQ_A :: SCTR_TXEMPTY_ON_TREQ_ENABLE } } # [doc = "Field `SCTR_TXEMPTY_ON_TREQ` writer - Tx Empty Interrupt on TREQ"] pub type SCTR_TXEMPTY_ON_TREQ_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , SCTR_TXEMPTY_ON_TREQ_A > ; impl < 'a , REG , const O : u8 > SCTR_TXEMPTY_ON_TREQ_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn sctr_txempty_on_treq_disable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_TXEMPTY_ON_TREQ_A :: SCTR_TXEMPTY_ON_TREQ_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn sctr_txempty_on_treq_enable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_TXEMPTY_ON_TREQ_A :: SCTR_TXEMPTY_ON_TREQ_ENABLE) } } # [doc = "Field `SCTR_TXTRIG_TXMODE` reader - Tx Trigger when slave FSM is in Tx Mode"] pub type SCTR_TXTRIG_TXMODE_R = crate :: BitReader < SCTR_TXTRIG_TXMODE_A > ; # [doc = "Tx Trigger when slave FSM is in Tx Mode\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum SCTR_TXTRIG_TXMODE_A { # [doc = "0: DISABLE"] SCTR_TXTRIG_TXMODE_DISABLE = 0 , # [doc = "1: ENABLE"] SCTR_TXTRIG_TXMODE_ENABLE = 1 , } impl From < SCTR_TXTRIG_TXMODE_A > for bool { # [inline (always)] fn from (variant : SCTR_TXTRIG_TXMODE_A) -> Self { variant as u8 != 0 } } impl SCTR_TXTRIG_TXMODE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> SCTR_TXTRIG_TXMODE_A { match self . bits { false => SCTR_TXTRIG_TXMODE_A :: SCTR_TXTRIG_TXMODE_DISABLE , true => SCTR_TXTRIG_TXMODE_A :: SCTR_TXTRIG_TXMODE_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_sctr_txtrig_txmode_disable (& self) -> bool { * self == SCTR_TXTRIG_TXMODE_A :: SCTR_TXTRIG_TXMODE_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_sctr_txtrig_txmode_enable (& self) -> bool { * self == SCTR_TXTRIG_TXMODE_A :: SCTR_TXTRIG_TXMODE_ENABLE } } # [doc = "Field `SCTR_TXTRIG_TXMODE` writer - Tx Trigger when slave FSM is in Tx Mode"] pub type SCTR_TXTRIG_TXMODE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , SCTR_TXTRIG_TXMODE_A > ; impl < 'a , REG , const O : u8 > SCTR_TXTRIG_TXMODE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn sctr_txtrig_txmode_disable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_TXTRIG_TXMODE_A :: SCTR_TXTRIG_TXMODE_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn sctr_txtrig_txmode_enable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_TXTRIG_TXMODE_A :: SCTR_TXTRIG_TXMODE_ENABLE) } } # [doc = "Field `SCTR_TXWAIT_STALE_TXFIFO` reader - Tx transfer waits when stale data in Tx FIFO. This prevents stale bytes left in the TX FIFO from automatically being sent on the next I2C packet. Note: this should be used with TXEMPTY_ON_TREQ set to prevent the Slave State Machine from waiting for TX FIFO data without an interrupt notification when the FIFO data is stale."] pub type SCTR_TXWAIT_STALE_TXFIFO_R = crate :: BitReader < SCTR_TXWAIT_STALE_TXFIFO_A > ; # [doc = "Tx transfer waits when stale data in Tx FIFO. This prevents stale bytes left in the TX FIFO from automatically being sent on the next I2C packet. Note: this should be used with TXEMPTY_ON_TREQ set to prevent the Slave State Machine from waiting for TX FIFO data without an interrupt notification when the FIFO data is stale.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum SCTR_TXWAIT_STALE_TXFIFO_A { # [doc = "0: DISABLE"] SCTR_TXWAIT_STALE_TXFIFO_DISABLE = 0 , # [doc = "1: ENABLE"] SCTR_TXWAIT_STALE_TXFIFO_ENABLE = 1 , } impl From < SCTR_TXWAIT_STALE_TXFIFO_A > for bool { # [inline (always)] fn from (variant : SCTR_TXWAIT_STALE_TXFIFO_A) -> Self { variant as u8 != 0 } } impl SCTR_TXWAIT_STALE_TXFIFO_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> SCTR_TXWAIT_STALE_TXFIFO_A { match self . bits { false => SCTR_TXWAIT_STALE_TXFIFO_A :: SCTR_TXWAIT_STALE_TXFIFO_DISABLE , true => SCTR_TXWAIT_STALE_TXFIFO_A :: SCTR_TXWAIT_STALE_TXFIFO_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_sctr_txwait_stale_txfifo_disable (& self) -> bool { * self == SCTR_TXWAIT_STALE_TXFIFO_A :: SCTR_TXWAIT_STALE_TXFIFO_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_sctr_txwait_stale_txfifo_enable (& self) -> bool { * self == SCTR_TXWAIT_STALE_TXFIFO_A :: SCTR_TXWAIT_STALE_TXFIFO_ENABLE } } # [doc = "Field `SCTR_TXWAIT_STALE_TXFIFO` writer - Tx transfer waits when stale data in Tx FIFO. This prevents stale bytes left in the TX FIFO from automatically being sent on the next I2C packet. Note: this should be used with TXEMPTY_ON_TREQ set to prevent the Slave State Machine from waiting for TX FIFO data without an interrupt notification when the FIFO data is stale."] pub type SCTR_TXWAIT_STALE_TXFIFO_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , SCTR_TXWAIT_STALE_TXFIFO_A > ; impl < 'a , REG , const O : u8 > SCTR_TXWAIT_STALE_TXFIFO_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn sctr_txwait_stale_txfifo_disable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_TXWAIT_STALE_TXFIFO_A :: SCTR_TXWAIT_STALE_TXFIFO_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn sctr_txwait_stale_txfifo_enable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_TXWAIT_STALE_TXFIFO_A :: SCTR_TXWAIT_STALE_TXFIFO_ENABLE) } } # [doc = "Field `SCTR_RXFULL_ON_RREQ` reader - Rx full interrupt generated on RREQ condition as indicated in SSR"] pub type SCTR_RXFULL_ON_RREQ_R = crate :: BitReader < SCTR_RXFULL_ON_RREQ_A > ; # [doc = "Rx full interrupt generated on RREQ condition as indicated in SSR\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum SCTR_RXFULL_ON_RREQ_A { # [doc = "0: DISABLE"] SCTR_RXFULL_ON_RREQ_DISABLE = 0 , # [doc = "1: ENABLE"] SCTR_RXFULL_ON_RREQ_ENABLE = 1 , } impl From < SCTR_RXFULL_ON_RREQ_A > for bool { # [inline (always)] fn from (variant : SCTR_RXFULL_ON_RREQ_A) -> Self { variant as u8 != 0 } } impl SCTR_RXFULL_ON_RREQ_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> SCTR_RXFULL_ON_RREQ_A { match self . bits { false => SCTR_RXFULL_ON_RREQ_A :: SCTR_RXFULL_ON_RREQ_DISABLE , true => SCTR_RXFULL_ON_RREQ_A :: SCTR_RXFULL_ON_RREQ_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_sctr_rxfull_on_rreq_disable (& self) -> bool { * self == SCTR_RXFULL_ON_RREQ_A :: SCTR_RXFULL_ON_RREQ_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_sctr_rxfull_on_rreq_enable (& self) -> bool { * self == SCTR_RXFULL_ON_RREQ_A :: SCTR_RXFULL_ON_RREQ_ENABLE } } # [doc = "Field `SCTR_RXFULL_ON_RREQ` writer - Rx full interrupt generated on RREQ condition as indicated in SSR"] pub type SCTR_RXFULL_ON_RREQ_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , SCTR_RXFULL_ON_RREQ_A > ; impl < 'a , REG , const O : u8 > SCTR_RXFULL_ON_RREQ_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn sctr_rxfull_on_rreq_disable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_RXFULL_ON_RREQ_A :: SCTR_RXFULL_ON_RREQ_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn sctr_rxfull_on_rreq_enable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_RXFULL_ON_RREQ_A :: SCTR_RXFULL_ON_RREQ_ENABLE) } } # [doc = "Field `SCTR_EN_DEFHOSTADR` reader - Enable Default Host Address"] pub type SCTR_EN_DEFHOSTADR_R = crate :: BitReader < SCTR_EN_DEFHOSTADR_A > ; # [doc = "Enable Default Host Address\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum SCTR_EN_DEFHOSTADR_A { # [doc = "0: DISABLE"] SCTR_EN_DEFHOSTADR_DISABLE = 0 , # [doc = "1: ENABLE"] SCTR_EN_DEFHOSTADR_ENABLE = 1 , } impl From < SCTR_EN_DEFHOSTADR_A > for bool { # [inline (always)] fn from (variant : SCTR_EN_DEFHOSTADR_A) -> Self { variant as u8 != 0 } } impl SCTR_EN_DEFHOSTADR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> SCTR_EN_DEFHOSTADR_A { match self . bits { false => SCTR_EN_DEFHOSTADR_A :: SCTR_EN_DEFHOSTADR_DISABLE , true => SCTR_EN_DEFHOSTADR_A :: SCTR_EN_DEFHOSTADR_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_sctr_en_defhostadr_disable (& self) -> bool { * self == SCTR_EN_DEFHOSTADR_A :: SCTR_EN_DEFHOSTADR_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_sctr_en_defhostadr_enable (& self) -> bool { * self == SCTR_EN_DEFHOSTADR_A :: SCTR_EN_DEFHOSTADR_ENABLE } } # [doc = "Field `SCTR_EN_DEFHOSTADR` writer - Enable Default Host Address"] pub type SCTR_EN_DEFHOSTADR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , SCTR_EN_DEFHOSTADR_A > ; impl < 'a , REG , const O : u8 > SCTR_EN_DEFHOSTADR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn sctr_en_defhostadr_disable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_EN_DEFHOSTADR_A :: SCTR_EN_DEFHOSTADR_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn sctr_en_defhostadr_enable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_EN_DEFHOSTADR_A :: SCTR_EN_DEFHOSTADR_ENABLE) } } # [doc = "Field `SCTR_EN_ALRESPADR` reader - Enable Alert Response Address"] pub type SCTR_EN_ALRESPADR_R = crate :: BitReader < SCTR_EN_ALRESPADR_A > ; # [doc = "Enable Alert Response Address\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum SCTR_EN_ALRESPADR_A { # [doc = "0: DISABLE"] SCTR_EN_ALRESPADR_DISABLE = 0 , # [doc = "1: ENABLE"] SCTR_EN_ALRESPADR_ENABLE = 1 , } impl From < SCTR_EN_ALRESPADR_A > for bool { # [inline (always)] fn from (variant : SCTR_EN_ALRESPADR_A) -> Self { variant as u8 != 0 } } impl SCTR_EN_ALRESPADR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> SCTR_EN_ALRESPADR_A { match self . bits { false => SCTR_EN_ALRESPADR_A :: SCTR_EN_ALRESPADR_DISABLE , true => SCTR_EN_ALRESPADR_A :: SCTR_EN_ALRESPADR_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_sctr_en_alrespadr_disable (& self) -> bool { * self == SCTR_EN_ALRESPADR_A :: SCTR_EN_ALRESPADR_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_sctr_en_alrespadr_enable (& self) -> bool { * self == SCTR_EN_ALRESPADR_A :: SCTR_EN_ALRESPADR_ENABLE } } # [doc = "Field `SCTR_EN_ALRESPADR` writer - Enable Alert Response Address"] pub type SCTR_EN_ALRESPADR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , SCTR_EN_ALRESPADR_A > ; impl < 'a , REG , const O : u8 > SCTR_EN_ALRESPADR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn sctr_en_alrespadr_disable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_EN_ALRESPADR_A :: SCTR_EN_ALRESPADR_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn sctr_en_alrespadr_enable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_EN_ALRESPADR_A :: SCTR_EN_ALRESPADR_ENABLE) } } # [doc = "Field `SCTR_EN_DEFDEVADR` reader - Enable Deault device address"] pub type SCTR_EN_DEFDEVADR_R = crate :: BitReader < SCTR_EN_DEFDEVADR_A > ; # [doc = "Enable Deault device address\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum SCTR_EN_DEFDEVADR_A { # [doc = "0: DISABLE"] SCTR_EN_DEFDEVADR_DISABLE = 0 , # [doc = "1: ENABLE"] SCTR_EN_DEFDEVADR_ENABLE = 1 , } impl From < SCTR_EN_DEFDEVADR_A > for bool { # [inline (always)] fn from (variant : SCTR_EN_DEFDEVADR_A) -> Self { variant as u8 != 0 } } impl SCTR_EN_DEFDEVADR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> SCTR_EN_DEFDEVADR_A { match self . bits { false => SCTR_EN_DEFDEVADR_A :: SCTR_EN_DEFDEVADR_DISABLE , true => SCTR_EN_DEFDEVADR_A :: SCTR_EN_DEFDEVADR_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_sctr_en_defdevadr_disable (& self) -> bool { * self == SCTR_EN_DEFDEVADR_A :: SCTR_EN_DEFDEVADR_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_sctr_en_defdevadr_enable (& self) -> bool { * self == SCTR_EN_DEFDEVADR_A :: SCTR_EN_DEFDEVADR_ENABLE } } # [doc = "Field `SCTR_EN_DEFDEVADR` writer - Enable Deault device address"] pub type SCTR_EN_DEFDEVADR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , SCTR_EN_DEFDEVADR_A > ; impl < 'a , REG , const O : u8 > SCTR_EN_DEFDEVADR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn sctr_en_defdevadr_disable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_EN_DEFDEVADR_A :: SCTR_EN_DEFDEVADR_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn sctr_en_defdevadr_enable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_EN_DEFDEVADR_A :: SCTR_EN_DEFDEVADR_ENABLE) } } # [doc = "Field `SCTR_SWUEN` reader - Slave Wakeup Enable"] pub type SCTR_SWUEN_R = crate :: BitReader < SCTR_SWUEN_A > ; # [doc = "Slave Wakeup Enable\n\nValue on reset: 1"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum SCTR_SWUEN_A { # [doc = "0: DISABLE"] SCTR_SWUEN_DISABLE = 0 , # [doc = "1: ENABLE"] SCTR_SWUEN_ENABLE = 1 , } impl From < SCTR_SWUEN_A > for bool { # [inline (always)] fn from (variant : SCTR_SWUEN_A) -> Self { variant as u8 != 0 } } impl SCTR_SWUEN_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> SCTR_SWUEN_A { match self . bits { false => SCTR_SWUEN_A :: SCTR_SWUEN_DISABLE , true => SCTR_SWUEN_A :: SCTR_SWUEN_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_sctr_swuen_disable (& self) -> bool { * self == SCTR_SWUEN_A :: SCTR_SWUEN_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_sctr_swuen_enable (& self) -> bool { * self == SCTR_SWUEN_A :: SCTR_SWUEN_ENABLE } } # [doc = "Field `SCTR_SWUEN` writer - Slave Wakeup Enable"] pub type SCTR_SWUEN_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , SCTR_SWUEN_A > ; impl < 'a , REG , const O : u8 > SCTR_SWUEN_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn sctr_swuen_disable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_SWUEN_A :: SCTR_SWUEN_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn sctr_swuen_enable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_SWUEN_A :: SCTR_SWUEN_ENABLE) } } impl R { # [doc = "Bit 0 - Device Active. Setting this bit enables the slave functionality."] # [inline (always)] pub fn sctr_active (& self) -> SCTR_ACTIVE_R { SCTR_ACTIVE_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - General call response enable. This bit is only available in UCBxI2COA0. Modify only when UCSWRST = 1. 0b = Do not respond to a general call 1b = Respond to a general call"] # [inline (always)] pub fn sctr_gencall (& self) -> SCTR_GENCALL_R { SCTR_GENCALL_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - Slave Clock Stretch Enable"] # [inline (always)] pub fn sctr_sclkstretch (& self) -> SCTR_SCLKSTRETCH_R { SCTR_SCLKSTRETCH_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - Tx Empty Interrupt on TREQ"] # [inline (always)] pub fn sctr_txempty_on_treq (& self) -> SCTR_TXEMPTY_ON_TREQ_R { SCTR_TXEMPTY_ON_TREQ_R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - Tx Trigger when slave FSM is in Tx Mode"] # [inline (always)] pub fn sctr_txtrig_txmode (& self) -> SCTR_TXTRIG_TXMODE_R { SCTR_TXTRIG_TXMODE_R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - Tx transfer waits when stale data in Tx FIFO. This prevents stale bytes left in the TX FIFO from automatically being sent on the next I2C packet. Note: this should be used with TXEMPTY_ON_TREQ set to prevent the Slave State Machine from waiting for TX FIFO data without an interrupt notification when the FIFO data is stale."] # [inline (always)] pub fn sctr_txwait_stale_txfifo (& self) -> SCTR_TXWAIT_STALE_TXFIFO_R { SCTR_TXWAIT_STALE_TXFIFO_R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - Rx full interrupt generated on RREQ condition as indicated in SSR"] # [inline (always)] pub fn sctr_rxfull_on_rreq (& self) -> SCTR_RXFULL_ON_RREQ_R { SCTR_RXFULL_ON_RREQ_R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - Enable Default Host Address"] # [inline (always)] pub fn sctr_en_defhostadr (& self) -> SCTR_EN_DEFHOSTADR_R { SCTR_EN_DEFHOSTADR_R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - Enable Alert Response Address"] # [inline (always)] pub fn sctr_en_alrespadr (& self) -> SCTR_EN_ALRESPADR_R { SCTR_EN_ALRESPADR_R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - Enable Deault device address"] # [inline (always)] pub fn sctr_en_defdevadr (& self) -> SCTR_EN_DEFDEVADR_R { SCTR_EN_DEFDEVADR_R :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - Slave Wakeup Enable"] # [inline (always)] pub fn sctr_swuen (& self) -> SCTR_SWUEN_R { SCTR_SWUEN_R :: new (((self . bits >> 10) & 1) != 0) } } impl W { # [doc = "Bit 0 - Device Active. Setting this bit enables the slave functionality."] # [inline (always)] # [must_use] pub fn sctr_active (& mut self) -> SCTR_ACTIVE_W < SCTR_SPEC , 0 > { SCTR_ACTIVE_W :: new (self) } # [doc = "Bit 1 - General call response enable. This bit is only available in UCBxI2COA0. Modify only when UCSWRST = 1. 0b = Do not respond to a general call 1b = Respond to a general call"] # [inline (always)] # [must_use] pub fn sctr_gencall (& mut self) -> SCTR_GENCALL_W < SCTR_SPEC , 1 > { SCTR_GENCALL_W :: new (self) } # [doc = "Bit 2 - Slave Clock Stretch Enable"] # [inline (always)] # [must_use] pub fn sctr_sclkstretch (& mut self) -> SCTR_SCLKSTRETCH_W < SCTR_SPEC , 2 > { SCTR_SCLKSTRETCH_W :: new (self) } # [doc = "Bit 3 - Tx Empty Interrupt on TREQ"] # [inline (always)] # [must_use] pub fn sctr_txempty_on_treq (& mut self) -> SCTR_TXEMPTY_ON_TREQ_W < SCTR_SPEC , 3 > { SCTR_TXEMPTY_ON_TREQ_W :: new (self) } # [doc = "Bit 4 - Tx Trigger when slave FSM is in Tx Mode"] # [inline (always)] # [must_use] pub fn sctr_txtrig_txmode (& mut self) -> SCTR_TXTRIG_TXMODE_W < SCTR_SPEC , 4 > { SCTR_TXTRIG_TXMODE_W :: new (self) } # [doc = "Bit 5 - Tx transfer waits when stale data in Tx FIFO. This prevents stale bytes left in the TX FIFO from automatically being sent on the next I2C packet. Note: this should be used with TXEMPTY_ON_TREQ set to prevent the Slave State Machine from waiting for TX FIFO data without an interrupt notification when the FIFO data is stale."] # [inline (always)] # [must_use] pub fn sctr_txwait_stale_txfifo (& mut self) -> SCTR_TXWAIT_STALE_TXFIFO_W < SCTR_SPEC , 5 > { SCTR_TXWAIT_STALE_TXFIFO_W :: new (self) } # [doc = "Bit 6 - Rx full interrupt generated on RREQ condition as indicated in SSR"] # [inline (always)] # [must_use] pub fn sctr_rxfull_on_rreq (& mut self) -> SCTR_RXFULL_ON_RREQ_W <'_, SCTR_SPEC , 6 > { SCTR_RXFULL_ON_RREQ_W :: new (self) } # [doc = "Bit 7 - Enable Default Host Address"] # [inline (always)] # [must_use] pub fn sctr_en_defhostadr (& mut self) -> SCTR_EN_DEFHOSTADR_W < SCTR_SPEC , 7 > { SCTR_EN_DEFHOSTADR_W :: new (self) } # [doc = "Bit 8 - Enable Alert Response Address"] # [inline (always)] # [must_use] pub fn sctr_en_alrespadr (& mut self) -> SCTR_EN_ALRESPADR_W < SCTR_SPEC , 8 > { SCTR_EN_ALRESPADR_W :: new (self) } # [doc = "Bit 9 - Enable Deault device address"] # [inline (always)] # [must_use] pub fn sctr_en_defdevadr (& mut self) -> SCTR_EN_DEFDEVADR_W < SCTR_SPEC , 9 > { SCTR_EN_DEFDEVADR_W :: new (self) } # [doc = "Bit 10 - Slave Wakeup Enable"] # [inline (always)] # [must_use] pub fn sctr_swuen (& mut self) -> SCTR_SWUEN_W < SCTR_SPEC , 10 > { SCTR_SWUEN_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "I2C Slave Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sctr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sctr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct SCTR_SPEC ; impl crate :: RegisterSpec for SCTR_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`sctr::R`](R) reader structure"] impl crate :: Readable for SCTR_SPEC { } # [doc = "`write(|w| ..)` method takes [`sctr::W`](W) writer structure"] impl crate :: Writable for SCTR_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets SCTR to value 0x0404"] impl crate :: Resettable for SCTR_SPEC { const RESET_VALUE : Self :: Ux = 0x0404 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/i2c0/mfifoctl.rs:1:12656 [INFO] [stdout] | [INFO] [stdout] 1 | ...b fn mfifoctl_txflush (& mut self) -> MFIFOCTL_TXFLUSH_W < MFIFOCTL_SPEC , 7 > { MFIFOCTL_TXFLUSH_W :: new (self) } # [doc = "Bits 8:1... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `MFIFOCTL` reader"] pub type R = crate :: R < MFIFOCTL_SPEC > ; # [doc = "Register `MFIFOCTL` writer"] pub type W = crate :: W < MFIFOCTL_SPEC > ; # [doc = "Field `MFIFOCTL_TXTRIG` reader - TX FIFO Trigger Indicates at what fill level in the TX FIFO a trigger will be generated."] pub type MFIFOCTL_TXTRIG_R = crate :: FieldReader < MFIFOCTL_TXTRIG_A > ; # [doc = "TX FIFO Trigger Indicates at what fill level in the TX FIFO a trigger will be generated.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum MFIFOCTL_TXTRIG_A { # [doc = "4: LEVEL_4"] MFIFOCTL_TXTRIG_LEVEL_4 = 4 , # [doc = "5: LEVEL_5"] MFIFOCTL_TXTRIG_LEVEL_5 = 5 , # [doc = "6: LEVEL_6"] MFIFOCTL_TXTRIG_LEVEL_6 = 6 , # [doc = "7: LEVEL_7"] MFIFOCTL_TXTRIG_LEVEL_7 = 7 , } impl From < MFIFOCTL_TXTRIG_A > for u8 { # [inline (always)] fn from (variant : MFIFOCTL_TXTRIG_A) -> Self { variant as _ } } impl crate :: FieldSpec for MFIFOCTL_TXTRIG_A { type Ux = u8 ; } impl MFIFOCTL_TXTRIG_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < MFIFOCTL_TXTRIG_A > { match self . bits { 4 => Some (MFIFOCTL_TXTRIG_A :: MFIFOCTL_TXTRIG_LEVEL_4) , 5 => Some (MFIFOCTL_TXTRIG_A :: MFIFOCTL_TXTRIG_LEVEL_5) , 6 => Some (MFIFOCTL_TXTRIG_A :: MFIFOCTL_TXTRIG_LEVEL_6) , 7 => Some (MFIFOCTL_TXTRIG_A :: MFIFOCTL_TXTRIG_LEVEL_7) , _ => None , } } # [doc = "LEVEL_4"] # [inline (always)] pub fn is_mfifoctl_txtrig_level_4 (& self) -> bool { * self == MFIFOCTL_TXTRIG_A :: MFIFOCTL_TXTRIG_LEVEL_4 } # [doc = "LEVEL_5"] # [inline (always)] pub fn is_mfifoctl_txtrig_level_5 (& self) -> bool { * self == MFIFOCTL_TXTRIG_A :: MFIFOCTL_TXTRIG_LEVEL_5 } # [doc = "LEVEL_6"] # [inline (always)] pub fn is_mfifoctl_txtrig_level_6 (& self) -> bool { * self == MFIFOCTL_TXTRIG_A :: MFIFOCTL_TXTRIG_LEVEL_6 } # [doc = "LEVEL_7"] # [inline (always)] pub fn is_mfifoctl_txtrig_level_7 (& self) -> bool { * self == MFIFOCTL_TXTRIG_A :: MFIFOCTL_TXTRIG_LEVEL_7 } } # [doc = "Field `MFIFOCTL_TXTRIG` writer - TX FIFO Trigger Indicates at what fill level in the TX FIFO a trigger will be generated."] pub type MFIFOCTL_TXTRIG_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 3 , O , MFIFOCTL_TXTRIG_A > ; impl < 'a , REG , const O : u8 > MFIFOCTL_TXTRIG_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "LEVEL_4"] # [inline (always)] pub fn mfifoctl_txtrig_level_4 (self) -> & 'a mut crate :: W < REG > { self . variant (MFIFOCTL_TXTRIG_A :: MFIFOCTL_TXTRIG_LEVEL_4) } # [doc = "LEVEL_5"] # [inline (always)] pub fn mfifoctl_txtrig_level_5 (self) -> & 'a mut crate :: W < REG > { self . variant (MFIFOCTL_TXTRIG_A :: MFIFOCTL_TXTRIG_LEVEL_5) } # [doc = "LEVEL_6"] # [inline (always)] pub fn mfifoctl_txtrig_level_6 (self) -> & 'a mut crate :: W < REG > { self . variant (MFIFOCTL_TXTRIG_A :: MFIFOCTL_TXTRIG_LEVEL_6) } # [doc = "LEVEL_7"] # [inline (always)] pub fn mfifoctl_txtrig_level_7 (self) -> & 'a mut crate :: W < REG > { self . variant (MFIFOCTL_TXTRIG_A :: MFIFOCTL_TXTRIG_LEVEL_7) } } # [doc = "Field `MFIFOCTL_TXFLUSH` reader - TX FIFO Flush Setting this bit will Flush the TX FIFO. Before reseting this bit to stop Flush the TXFIFOCNT should be checked to be 8 and indicating that the Flush has completed."] pub type MFIFOCTL_TXFLUSH_R = crate :: BitReader < MFIFOCTL_TXFLUSH_A > ; # [doc = "TX FIFO Flush Setting this bit will Flush the TX FIFO. Before reseting this bit to stop Flush the TXFIFOCNT should be checked to be 8 and indicating that the Flush has completed.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum MFIFOCTL_TXFLUSH_A { # [doc = "0: NOFLUSH"] MFIFOCTL_TXFLUSH_NOFLUSH = 0 , # [doc = "1: FLUSH"] MFIFOCTL_TXFLUSH_FLUSH = 1 , } impl From < MFIFOCTL_TXFLUSH_A > for bool { # [inline (always)] fn from (variant : MFIFOCTL_TXFLUSH_A) -> Self { variant as u8 != 0 } } impl MFIFOCTL_TXFLUSH_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> MFIFOCTL_TXFLUSH_A { match self . bits { false => MFIFOCTL_TXFLUSH_A :: MFIFOCTL_TXFLUSH_NOFLUSH , true => MFIFOCTL_TXFLUSH_A :: MFIFOCTL_TXFLUSH_FLUSH , } } # [doc = "NOFLUSH"] # [inline (always)] pub fn is_mfifoctl_txflush_noflush (& self) -> bool { * self == MFIFOCTL_TXFLUSH_A :: MFIFOCTL_TXFLUSH_NOFLUSH } # [doc = "FLUSH"] # [inline (always)] pub fn is_mfifoctl_txflush_flush (& self) -> bool { * self == MFIFOCTL_TXFLUSH_A :: MFIFOCTL_TXFLUSH_FLUSH } } # [doc = "Field `MFIFOCTL_TXFLUSH` writer - TX FIFO Flush Setting this bit will Flush the TX FIFO. Before reseting this bit to stop Flush the TXFIFOCNT should be checked to be 8 and indicating that the Flush has completed."] pub type MFIFOCTL_TXFLUSH_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , MFIFOCTL_TXFLUSH_A > ; impl < 'a , REG , const O : u8 > MFIFOCTL_TXFLUSH_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NOFLUSH"] # [inline (always)] pub fn mfifoctl_txflush_noflush (self) -> & 'a mut crate :: W < REG > { self . variant (MFIFOCTL_TXFLUSH_A :: MFIFOCTL_TXFLUSH_NOFLUSH) } # [doc = "FLUSH"] # [inline (always)] pub fn mfifoctl_txflush_flush (self) -> & 'a mut crate :: W < REG > { self . variant (MFIFOCTL_TXFLUSH_A :: MFIFOCTL_TXFLUSH_FLUSH) } } # [doc = "Field `MFIFOCTL_RXTRIG` reader - RX FIFO Trigger Indicates at what fill level in the RX FIFO a trigger will be generated. Note: Programming RXTRIG to 0x0 has no effect since no data is present to transfer out of RX FIFO."] pub type MFIFOCTL_RXTRIG_R = crate :: FieldReader < MFIFOCTL_RXTRIG_A > ; # [doc = "RX FIFO Trigger Indicates at what fill level in the RX FIFO a trigger will be generated. Note: Programming RXTRIG to 0x0 has no effect since no data is present to transfer out of RX FIFO.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum MFIFOCTL_RXTRIG_A { # [doc = "4: LEVEL_5"] MFIFOCTL_RXTRIG_LEVEL_5 = 4 , # [doc = "5: LEVEL_6"] MFIFOCTL_RXTRIG_LEVEL_6 = 5 , # [doc = "6: LEVEL_7"] MFIFOCTL_RXTRIG_LEVEL_7 = 6 , # [doc = "7: LEVEL_8"] MFIFOCTL_RXTRIG_LEVEL_8 = 7 , } impl From < MFIFOCTL_RXTRIG_A > for u8 { # [inline (always)] fn from (variant : MFIFOCTL_RXTRIG_A) -> Self { variant as _ } } impl crate :: FieldSpec for MFIFOCTL_RXTRIG_A { type Ux = u8 ; } impl MFIFOCTL_RXTRIG_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < MFIFOCTL_RXTRIG_A > { match self . bits { 4 => Some (MFIFOCTL_RXTRIG_A :: MFIFOCTL_RXTRIG_LEVEL_5) , 5 => Some (MFIFOCTL_RXTRIG_A :: MFIFOCTL_RXTRIG_LEVEL_6) , 6 => Some (MFIFOCTL_RXTRIG_A :: MFIFOCTL_RXTRIG_LEVEL_7) , 7 => Some (MFIFOCTL_RXTRIG_A :: MFIFOCTL_RXTRIG_LEVEL_8) , _ => None , } } # [doc = "LEVEL_5"] # [inline (always)] pub fn is_mfifoctl_rxtrig_level_5 (& self) -> bool { * self == MFIFOCTL_RXTRIG_A :: MFIFOCTL_RXTRIG_LEVEL_5 } # [doc = "LEVEL_6"] # [inline (always)] pub fn is_mfifoctl_rxtrig_level_6 (& self) -> bool { * self == MFIFOCTL_RXTRIG_A :: MFIFOCTL_RXTRIG_LEVEL_6 } # [doc = "LEVEL_7"] # [inline (always)] pub fn is_mfifoctl_rxtrig_level_7 (& self) -> bool { * self == MFIFOCTL_RXTRIG_A :: MFIFOCTL_RXTRIG_LEVEL_7 } # [doc = "LEVEL_8"] # [inline (always)] pub fn is_mfifoctl_rxtrig_level_8 (& self) -> bool { * self == MFIFOCTL_RXTRIG_A :: MFIFOCTL_RXTRIG_LEVEL_8 } } # [doc = "Field `MFIFOCTL_RXTRIG` writer - RX FIFO Trigger Indicates at what fill level in the RX FIFO a trigger will be generated. Note: Programming RXTRIG to 0x0 has no effect since no data is present to transfer out of RX FIFO."] pub type MFIFOCTL_RXTRIG_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 3 , O , MFIFOCTL_RXTRIG_A > ; impl < 'a , REG , const O : u8 > MFIFOCTL_RXTRIG_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "LEVEL_5"] # [inline (always)] pub fn mfifoctl_rxtrig_level_5 (self) -> & 'a mut crate :: W < REG > { self . variant (MFIFOCTL_RXTRIG_A :: MFIFOCTL_RXTRIG_LEVEL_5) } # [doc = "LEVEL_6"] # [inline (always)] pub fn mfifoctl_rxtrig_level_6 (self) -> & 'a mut crate :: W < REG > { self . variant (MFIFOCTL_RXTRIG_A :: MFIFOCTL_RXTRIG_LEVEL_6) } # [doc = "LEVEL_7"] # [inline (always)] pub fn mfifoctl_rxtrig_level_7 (self) -> & 'a mut crate :: W < REG > { self . variant (MFIFOCTL_RXTRIG_A :: MFIFOCTL_RXTRIG_LEVEL_7) } # [doc = "LEVEL_8"] # [inline (always)] pub fn mfifoctl_rxtrig_level_8 (self) -> & 'a mut crate :: W < REG > { self . variant (MFIFOCTL_RXTRIG_A :: MFIFOCTL_RXTRIG_LEVEL_8) } } # [doc = "Field `MFIFOCTL_RXFLUSH` reader - RX FIFO Flush Setting this bit will Flush the RX FIFO. Before reseting this bit to stop Flush the RXFIFOCNT should be checked to be 0 and indicating that the Flush has completed."] pub type MFIFOCTL_RXFLUSH_R = crate :: BitReader < MFIFOCTL_RXFLUSH_A > ; # [doc = "RX FIFO Flush Setting this bit will Flush the RX FIFO. Before reseting this bit to stop Flush the RXFIFOCNT should be checked to be 0 and indicating that the Flush has completed.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum MFIFOCTL_RXFLUSH_A { # [doc = "0: NOFLUSH"] MFIFOCTL_RXFLUSH_NOFLUSH = 0 , # [doc = "1: FLUSH"] MFIFOCTL_RXFLUSH_FLUSH = 1 , } impl From < MFIFOCTL_RXFLUSH_A > for bool { # [inline (always)] fn from (variant : MFIFOCTL_RXFLUSH_A) -> Self { variant as u8 != 0 } } impl MFIFOCTL_RXFLUSH_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> MFIFOCTL_RXFLUSH_A { match self . bits { false => MFIFOCTL_RXFLUSH_A :: MFIFOCTL_RXFLUSH_NOFLUSH , true => MFIFOCTL_RXFLUSH_A :: MFIFOCTL_RXFLUSH_FLUSH , } } # [doc = "NOFLUSH"] # [inline (always)] pub fn is_mfifoctl_rxflush_noflush (& self) -> bool { * self == MFIFOCTL_RXFLUSH_A :: MFIFOCTL_RXFLUSH_NOFLUSH } # [doc = "FLUSH"] # [inline (always)] pub fn is_mfifoctl_rxflush_flush (& self) -> bool { * self == MFIFOCTL_RXFLUSH_A :: MFIFOCTL_RXFLUSH_FLUSH } } # [doc = "Field `MFIFOCTL_RXFLUSH` writer - RX FIFO Flush Setting this bit will Flush the RX FIFO. Before reseting this bit to stop Flush the RXFIFOCNT should be checked to be 0 and indicating that the Flush has completed."] pub type MFIFOCTL_RXFLUSH_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , MFIFOCTL_RXFLUSH_A > ; impl < 'a , REG , const O : u8 > MFIFOCTL_RXFLUSH_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NOFLUSH"] # [inline (always)] pub fn mfifoctl_rxflush_noflush (self) -> & 'a mut crate :: W < REG > { self . variant (MFIFOCTL_RXFLUSH_A :: MFIFOCTL_RXFLUSH_NOFLUSH) } # [doc = "FLUSH"] # [inline (always)] pub fn mfifoctl_rxflush_flush (self) -> & 'a mut crate :: W < REG > { self . variant (MFIFOCTL_RXFLUSH_A :: MFIFOCTL_RXFLUSH_FLUSH) } } impl R { # [doc = "Bits 0:2 - TX FIFO Trigger Indicates at what fill level in the TX FIFO a trigger will be generated."] # [inline (always)] pub fn mfifoctl_txtrig (& self) -> MFIFOCTL_TXTRIG_R { MFIFOCTL_TXTRIG_R :: new ((self . bits & 7) as u8) } # [doc = "Bit 7 - TX FIFO Flush Setting this bit will Flush the TX FIFO. Before reseting this bit to stop Flush the TXFIFOCNT should be checked to be 8 and indicating that the Flush has completed."] # [inline (always)] pub fn mfifoctl_txflush (& self) -> MFIFOCTL_TXFLUSH_R { MFIFOCTL_TXFLUSH_R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bits 8:10 - RX FIFO Trigger Indicates at what fill level in the RX FIFO a trigger will be generated. Note: Programming RXTRIG to 0x0 has no effect since no data is present to transfer out of RX FIFO."] # [inline (always)] pub fn mfifoctl_rxtrig (& self) -> MFIFOCTL_RXTRIG_R { MFIFOCTL_RXTRIG_R :: new (((self . bits >> 8) & 7) as u8) } # [doc = "Bit 15 - RX FIFO Flush Setting this bit will Flush the RX FIFO. Before reseting this bit to stop Flush the RXFIFOCNT should be checked to be 0 and indicating that the Flush has completed."] # [inline (always)] pub fn mfifoctl_rxflush (& self) -> MFIFOCTL_RXFLUSH_R { MFIFOCTL_RXFLUSH_R :: new (((self . bits >> 15) & 1) != 0) } } impl W { # [doc = "Bits 0:2 - TX FIFO Trigger Indicates at what fill level in the TX FIFO a trigger will be generated."] # [inline (always)] # [must_use] pub fn mfifoctl_txtrig (& mut self) -> MFIFOCTL_TXTRIG_W < MFIFOCTL_SPEC , 0 > { MFIFOCTL_TXTRIG_W :: new (self) } # [doc = "Bit 7 - TX FIFO Flush Setting this bit will Flush the TX FIFO. Before reseting this bit to stop Flush the TXFIFOCNT should be checked to be 8 and indicating that the Flush has completed."] # [inline (always)] # [must_use] pub fn mfifoctl_txflush (& mut self) -> MFIFOCTL_TXFLUSH_W <'_, MFIFOCTL_SPEC , 7 > { MFIFOCTL_TXFLUSH_W :: new (self) } # [doc = "Bits 8:10 - RX FIFO Trigger Indicates at what fill level in the RX FIFO a trigger will be generated. Note: Programming RXTRIG to 0x0 has no effect since no data is present to transfer out of RX FIFO."] # [inline (always)] # [must_use] pub fn mfifoctl_rxtrig (& mut self) -> MFIFOCTL_RXTRIG_W < MFIFOCTL_SPEC , 8 > { MFIFOCTL_RXTRIG_W :: new (self) } # [doc = "Bit 15 - RX FIFO Flush Setting this bit will Flush the RX FIFO. Before reseting this bit to stop Flush the RXFIFOCNT should be checked to be 0 and indicating that the Flush has completed."] # [inline (always)] # [must_use] pub fn mfifoctl_rxflush (& mut self) -> MFIFOCTL_RXFLUSH_W < MFIFOCTL_SPEC , 15 > { MFIFOCTL_RXFLUSH_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "I2C Master FIFO Control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mfifoctl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mfifoctl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct MFIFOCTL_SPEC ; impl crate :: RegisterSpec for MFIFOCTL_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`mfifoctl::R`](R) reader structure"] impl crate :: Readable for MFIFOCTL_SPEC { } # [doc = "`write(|w| ..)` method takes [`mfifoctl::W`](W) writer structure"] impl crate :: Writable for MFIFOCTL_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets MFIFOCTL to value 0"] impl crate :: Resettable for MFIFOCTL_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/i2c1/int_event2_imask.rs:1:10487 [INFO] [stdout] | [INFO] [stdout] 1 | ..._srxfifotrg (& mut self) -> INT_EVENT2_IMASK_SRXFIFOTRG_W < INT_EVENT2_IMASK_SPEC , 2 > { INT_EVENT2_IMASK_SRXFIFOTRG_W :: new (self) ... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `INT_EVENT2_IMASK` reader"] pub type R = crate :: R < INT_EVENT2_IMASK_SPEC > ; # [doc = "Register `INT_EVENT2_IMASK` writer"] pub type W = crate :: W < INT_EVENT2_IMASK_SPEC > ; # [doc = "Field `INT_EVENT2_IMASK_MRXFIFOTRG` reader - Master Receive FIFO Trigger Trigger when RX FIFO contains &gt;= defined bytes"] pub type INT_EVENT2_IMASK_MRXFIFOTRG_R = crate :: BitReader < INT_EVENT2_IMASK_MRXFIFOTRG_A > ; # [doc = "Master Receive FIFO Trigger Trigger when RX FIFO contains &gt;= defined bytes\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT2_IMASK_MRXFIFOTRG_A { # [doc = "0: CLR"] INT_EVENT2_IMASK_MRXFIFOTRG_CLR = 0 , # [doc = "1: SET"] INT_EVENT2_IMASK_MRXFIFOTRG_SET = 1 , } impl From < INT_EVENT2_IMASK_MRXFIFOTRG_A > for bool { # [inline (always)] fn from (variant : INT_EVENT2_IMASK_MRXFIFOTRG_A) -> Self { variant as u8 != 0 } } impl INT_EVENT2_IMASK_MRXFIFOTRG_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT2_IMASK_MRXFIFOTRG_A { match self . bits { false => INT_EVENT2_IMASK_MRXFIFOTRG_A :: INT_EVENT2_IMASK_MRXFIFOTRG_CLR , true => INT_EVENT2_IMASK_MRXFIFOTRG_A :: INT_EVENT2_IMASK_MRXFIFOTRG_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event2_imask_mrxfifotrg_clr (& self) -> bool { * self == INT_EVENT2_IMASK_MRXFIFOTRG_A :: INT_EVENT2_IMASK_MRXFIFOTRG_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event2_imask_mrxfifotrg_set (& self) -> bool { * self == INT_EVENT2_IMASK_MRXFIFOTRG_A :: INT_EVENT2_IMASK_MRXFIFOTRG_SET } } # [doc = "Field `INT_EVENT2_IMASK_MRXFIFOTRG` writer - Master Receive FIFO Trigger Trigger when RX FIFO contains &gt;= defined bytes"] pub type INT_EVENT2_IMASK_MRXFIFOTRG_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT2_IMASK_MRXFIFOTRG_A > ; impl < 'a , REG , const O : u8 > INT_EVENT2_IMASK_MRXFIFOTRG_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event2_imask_mrxfifotrg_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT2_IMASK_MRXFIFOTRG_A :: INT_EVENT2_IMASK_MRXFIFOTRG_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event2_imask_mrxfifotrg_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT2_IMASK_MRXFIFOTRG_A :: INT_EVENT2_IMASK_MRXFIFOTRG_SET) } } # [doc = "Field `INT_EVENT2_IMASK_MTXFIFOTRG` reader - Master Transmit FIFO Trigger Trigger when Transmit FIFO contains &lt;= defined bytes"] pub type INT_EVENT2_IMASK_MTXFIFOTRG_R = crate :: BitReader < INT_EVENT2_IMASK_MTXFIFOTRG_A > ; # [doc = "Master Transmit FIFO Trigger Trigger when Transmit FIFO contains &lt;= defined bytes\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT2_IMASK_MTXFIFOTRG_A { # [doc = "0: CLR"] INT_EVENT2_IMASK_MTXFIFOTRG_CLR = 0 , # [doc = "1: SET"] INT_EVENT2_IMASK_MTXFIFOTRG_SET = 1 , } impl From < INT_EVENT2_IMASK_MTXFIFOTRG_A > for bool { # [inline (always)] fn from (variant : INT_EVENT2_IMASK_MTXFIFOTRG_A) -> Self { variant as u8 != 0 } } impl INT_EVENT2_IMASK_MTXFIFOTRG_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT2_IMASK_MTXFIFOTRG_A { match self . bits { false => INT_EVENT2_IMASK_MTXFIFOTRG_A :: INT_EVENT2_IMASK_MTXFIFOTRG_CLR , true => INT_EVENT2_IMASK_MTXFIFOTRG_A :: INT_EVENT2_IMASK_MTXFIFOTRG_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event2_imask_mtxfifotrg_clr (& self) -> bool { * self == INT_EVENT2_IMASK_MTXFIFOTRG_A :: INT_EVENT2_IMASK_MTXFIFOTRG_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event2_imask_mtxfifotrg_set (& self) -> bool { * self == INT_EVENT2_IMASK_MTXFIFOTRG_A :: INT_EVENT2_IMASK_MTXFIFOTRG_SET } } # [doc = "Field `INT_EVENT2_IMASK_MTXFIFOTRG` writer - Master Transmit FIFO Trigger Trigger when Transmit FIFO contains &lt;= defined bytes"] pub type INT_EVENT2_IMASK_MTXFIFOTRG_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT2_IMASK_MTXFIFOTRG_A > ; impl < 'a , REG , const O : u8 > INT_EVENT2_IMASK_MTXFIFOTRG_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event2_imask_mtxfifotrg_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT2_IMASK_MTXFIFOTRG_A :: INT_EVENT2_IMASK_MTXFIFOTRG_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event2_imask_mtxfifotrg_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT2_IMASK_MTXFIFOTRG_A :: INT_EVENT2_IMASK_MTXFIFOTRG_SET) } } # [doc = "Field `INT_EVENT2_IMASK_SRXFIFOTRG` reader - Slave Receive FIFO Trigger"] pub type INT_EVENT2_IMASK_SRXFIFOTRG_R = crate :: BitReader < INT_EVENT2_IMASK_SRXFIFOTRG_A > ; # [doc = "Slave Receive FIFO Trigger\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT2_IMASK_SRXFIFOTRG_A { # [doc = "0: CLR"] INT_EVENT2_IMASK_SRXFIFOTRG_CLR = 0 , # [doc = "1: SET"] INT_EVENT2_IMASK_SRXFIFOTRG_SET = 1 , } impl From < INT_EVENT2_IMASK_SRXFIFOTRG_A > for bool { # [inline (always)] fn from (variant : INT_EVENT2_IMASK_SRXFIFOTRG_A) -> Self { variant as u8 != 0 } } impl INT_EVENT2_IMASK_SRXFIFOTRG_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT2_IMASK_SRXFIFOTRG_A { match self . bits { false => INT_EVENT2_IMASK_SRXFIFOTRG_A :: INT_EVENT2_IMASK_SRXFIFOTRG_CLR , true => INT_EVENT2_IMASK_SRXFIFOTRG_A :: INT_EVENT2_IMASK_SRXFIFOTRG_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event2_imask_srxfifotrg_clr (& self) -> bool { * self == INT_EVENT2_IMASK_SRXFIFOTRG_A :: INT_EVENT2_IMASK_SRXFIFOTRG_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event2_imask_srxfifotrg_set (& self) -> bool { * self == INT_EVENT2_IMASK_SRXFIFOTRG_A :: INT_EVENT2_IMASK_SRXFIFOTRG_SET } } # [doc = "Field `INT_EVENT2_IMASK_SRXFIFOTRG` writer - Slave Receive FIFO Trigger"] pub type INT_EVENT2_IMASK_SRXFIFOTRG_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT2_IMASK_SRXFIFOTRG_A > ; impl < 'a , REG , const O : u8 > INT_EVENT2_IMASK_SRXFIFOTRG_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event2_imask_srxfifotrg_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT2_IMASK_SRXFIFOTRG_A :: INT_EVENT2_IMASK_SRXFIFOTRG_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event2_imask_srxfifotrg_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT2_IMASK_SRXFIFOTRG_A :: INT_EVENT2_IMASK_SRXFIFOTRG_SET) } } # [doc = "Field `INT_EVENT2_IMASK_STXFIFOTRG` reader - Slave Transmit FIFO Trigger"] pub type INT_EVENT2_IMASK_STXFIFOTRG_R = crate :: BitReader < INT_EVENT2_IMASK_STXFIFOTRG_A > ; # [doc = "Slave Transmit FIFO Trigger\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT2_IMASK_STXFIFOTRG_A { # [doc = "0: CLR"] INT_EVENT2_IMASK_STXFIFOTRG_CLR = 0 , # [doc = "1: SET"] INT_EVENT2_IMASK_STXFIFOTRG_SET = 1 , } impl From < INT_EVENT2_IMASK_STXFIFOTRG_A > for bool { # [inline (always)] fn from (variant : INT_EVENT2_IMASK_STXFIFOTRG_A) -> Self { variant as u8 != 0 } } impl INT_EVENT2_IMASK_STXFIFOTRG_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT2_IMASK_STXFIFOTRG_A { match self . bits { false => INT_EVENT2_IMASK_STXFIFOTRG_A :: INT_EVENT2_IMASK_STXFIFOTRG_CLR , true => INT_EVENT2_IMASK_STXFIFOTRG_A :: INT_EVENT2_IMASK_STXFIFOTRG_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event2_imask_stxfifotrg_clr (& self) -> bool { * self == INT_EVENT2_IMASK_STXFIFOTRG_A :: INT_EVENT2_IMASK_STXFIFOTRG_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event2_imask_stxfifotrg_set (& self) -> bool { * self == INT_EVENT2_IMASK_STXFIFOTRG_A :: INT_EVENT2_IMASK_STXFIFOTRG_SET } } # [doc = "Field `INT_EVENT2_IMASK_STXFIFOTRG` writer - Slave Transmit FIFO Trigger"] pub type INT_EVENT2_IMASK_STXFIFOTRG_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT2_IMASK_STXFIFOTRG_A > ; impl < 'a , REG , const O : u8 > INT_EVENT2_IMASK_STXFIFOTRG_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event2_imask_stxfifotrg_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT2_IMASK_STXFIFOTRG_A :: INT_EVENT2_IMASK_STXFIFOTRG_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event2_imask_stxfifotrg_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT2_IMASK_STXFIFOTRG_A :: INT_EVENT2_IMASK_STXFIFOTRG_SET) } } impl R { # [doc = "Bit 0 - Master Receive FIFO Trigger Trigger when RX FIFO contains &gt;= defined bytes"] # [inline (always)] pub fn int_event2_imask_mrxfifotrg (& self) -> INT_EVENT2_IMASK_MRXFIFOTRG_R { INT_EVENT2_IMASK_MRXFIFOTRG_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - Master Transmit FIFO Trigger Trigger when Transmit FIFO contains &lt;= defined bytes"] # [inline (always)] pub fn int_event2_imask_mtxfifotrg (& self) -> INT_EVENT2_IMASK_MTXFIFOTRG_R { INT_EVENT2_IMASK_MTXFIFOTRG_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - Slave Receive FIFO Trigger"] # [inline (always)] pub fn int_event2_imask_srxfifotrg (& self) -> INT_EVENT2_IMASK_SRXFIFOTRG_R { INT_EVENT2_IMASK_SRXFIFOTRG_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - Slave Transmit FIFO Trigger"] # [inline (always)] pub fn int_event2_imask_stxfifotrg (& self) -> INT_EVENT2_IMASK_STXFIFOTRG_R { INT_EVENT2_IMASK_STXFIFOTRG_R :: new (((self . bits >> 3) & 1) != 0) } } impl W { # [doc = "Bit 0 - Master Receive FIFO Trigger Trigger when RX FIFO contains &gt;= defined bytes"] # [inline (always)] # [must_use] pub fn int_event2_imask_mrxfifotrg (& mut self) -> INT_EVENT2_IMASK_MRXFIFOTRG_W < INT_EVENT2_IMASK_SPEC , 0 > { INT_EVENT2_IMASK_MRXFIFOTRG_W :: new (self) } # [doc = "Bit 1 - Master Transmit FIFO Trigger Trigger when Transmit FIFO contains &lt;= defined bytes"] # [inline (always)] # [must_use] pub fn int_event2_imask_mtxfifotrg (& mut self) -> INT_EVENT2_IMASK_MTXFIFOTRG_W < INT_EVENT2_IMASK_SPEC , 1 > { INT_EVENT2_IMASK_MTXFIFOTRG_W :: new (self) } # [doc = "Bit 2 - Slave Receive FIFO Trigger"] # [inline (always)] # [must_use] pub fn int_event2_imask_srxfifotrg (& mut self) -> INT_EVENT2_IMASK_SRXFIFOTRG_W <'_, INT_EVENT2_IMASK_SPEC , 2 > { INT_EVENT2_IMASK_SRXFIFOTRG_W :: new (self) } # [doc = "Bit 3 - Slave Transmit FIFO Trigger"] # [inline (always)] # [must_use] pub fn int_event2_imask_stxfifotrg (& mut self) -> INT_EVENT2_IMASK_STXFIFOTRG_W < INT_EVENT2_IMASK_SPEC , 3 > { INT_EVENT2_IMASK_STXFIFOTRG_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Interrupt mask\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_event2_imask::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_event2_imask::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct INT_EVENT2_IMASK_SPEC ; impl crate :: RegisterSpec for INT_EVENT2_IMASK_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`int_event2_imask::R`](R) reader structure"] impl crate :: Readable for INT_EVENT2_IMASK_SPEC { } # [doc = "`write(|w| ..)` method takes [`int_event2_imask::W`](W) writer structure"] impl crate :: Writable for INT_EVENT2_IMASK_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets INT_EVENT2_IMASK to value 0"] impl crate :: Resettable for INT_EVENT2_IMASK_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/sysctl/nmiiclr.rs:1:2193 [INFO] [stdout] | [INFO] [stdout] 1 | ... pub fn nmiiclr_borlvl (& mut self) -> NMIICLR_BORLVL_W < NMIICLR_SPEC , 0 > { NMIICLR_BORLVL_W :: new (self) } # [doc = "Bit 1 - Watc... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `NMIICLR` writer"] pub type W = crate :: W < NMIICLR_SPEC > ; # [doc = "Clr the BORLVL NMI\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum NMIICLR_BORLVL_AW { # [doc = "0: NO_EFFECT"] NMIICLR_BORLVL_NO_EFFECT = 0 , # [doc = "1: CLR"] NMIICLR_BORLVL_CLR = 1 , } impl From < NMIICLR_BORLVL_AW > for bool { # [inline (always)] fn from (variant : NMIICLR_BORLVL_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `NMIICLR_BORLVL` writer - Clr the BORLVL NMI"] pub type NMIICLR_BORLVL_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , NMIICLR_BORLVL_AW > ; impl < 'a , REG , const O : u8 > NMIICLR_BORLVL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn nmiiclr_borlvl_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (NMIICLR_BORLVL_AW :: NMIICLR_BORLVL_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn nmiiclr_borlvl_clr (self) -> & 'a mut crate :: W < REG > { self . variant (NMIICLR_BORLVL_AW :: NMIICLR_BORLVL_CLR) } } # [doc = "Watch Dog 0 Fault\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum NMIICLR_WWDT0_AW { # [doc = "0: NO_EFFECT"] NMIICLR_WWDT0_NO_EFFECT = 0 , # [doc = "1: CLR"] NMIICLR_WWDT0_CLR = 1 , } impl From < NMIICLR_WWDT0_AW > for bool { # [inline (always)] fn from (variant : NMIICLR_WWDT0_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `NMIICLR_WWDT0` writer - Watch Dog 0 Fault"] pub type NMIICLR_WWDT0_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , NMIICLR_WWDT0_AW > ; impl < 'a , REG , const O : u8 > NMIICLR_WWDT0_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn nmiiclr_wwdt0_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (NMIICLR_WWDT0_AW :: NMIICLR_WWDT0_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn nmiiclr_wwdt0_clr (self) -> & 'a mut crate :: W < REG > { self . variant (NMIICLR_WWDT0_AW :: NMIICLR_WWDT0_CLR) } } impl W { # [doc = "Bit 0 - Clr the BORLVL NMI"] # [inline (always)] # [must_use] pub fn nmiiclr_borlvl (& mut self) -> NMIICLR_BORLVL_W <'_, NMIICLR_SPEC , 0 > { NMIICLR_BORLVL_W :: new (self) } # [doc = "Bit 1 - Watch Dog 0 Fault"] # [inline (always)] # [must_use] pub fn nmiiclr_wwdt0 (& mut self) -> NMIICLR_WWDT0_W < NMIICLR_SPEC , 1 > { NMIICLR_WWDT0_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "NMI interrupt clear\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`nmiiclr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct NMIICLR_SPEC ; impl crate :: RegisterSpec for NMIICLR_SPEC { type Ux = u32 ; } # [doc = "`write(|w| ..)` method takes [`nmiiclr::W`](W) writer structure"] impl crate :: Writable for NMIICLR_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets NMIICLR to value 0"] impl crate :: Resettable for NMIICLR_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/i2c1/timeout_ctl.rs:1:8851 [INFO] [stdout] | [INFO] [stdout] 1 | ...meout_ctl_tcntben (& mut self) -> TIMEOUT_CTL_TCNTBEN_W < TIMEOUT_CTL_SPEC , 31 > { TIMEOUT_CTL_TCNTBEN_W :: new (self) } # [doc = r" ... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `TIMEOUT_CTL` reader"] pub type R = crate :: R < TIMEOUT_CTL_SPEC > ; # [doc = "Register `TIMEOUT_CTL` writer"] pub type W = crate :: W < TIMEOUT_CTL_SPEC > ; # [doc = "Field `TIMEOUT_CTL_TCNTLA` reader - Timeout counter A load value Counter A is used for SCL low detection. This field contains the upper 8 bits of a 12-bit pre-load value for the Timeout A count. NOTE: The value of CNTLA must be greater than 1h. Each count is equal to 520 times the timeout period of functional clock. For example, with 8MHz functional clock and a 100KHz operating I2C clock, one timeout period will be equal to (1 / 8MHz) * 520 or 65 us."] pub type TIMEOUT_CTL_TCNTLA_R = crate :: FieldReader ; # [doc = "Field `TIMEOUT_CTL_TCNTLA` writer - Timeout counter A load value Counter A is used for SCL low detection. This field contains the upper 8 bits of a 12-bit pre-load value for the Timeout A count. NOTE: The value of CNTLA must be greater than 1h. Each count is equal to 520 times the timeout period of functional clock. For example, with 8MHz functional clock and a 100KHz operating I2C clock, one timeout period will be equal to (1 / 8MHz) * 520 or 65 us."] pub type TIMEOUT_CTL_TCNTLA_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 8 , O > ; # [doc = "Field `TIMEOUT_CTL_TCNTAEN` reader - Timeout Counter A Enable"] pub type TIMEOUT_CTL_TCNTAEN_R = crate :: BitReader < TIMEOUT_CTL_TCNTAEN_A > ; # [doc = "Timeout Counter A Enable\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum TIMEOUT_CTL_TCNTAEN_A { # [doc = "0: DISABLE"] TIMEOUT_CTL_TCNTAEN_DISABLE = 0 , # [doc = "1: ENABLE"] TIMEOUT_CTL_TCNTAEN_ENABLE = 1 , } impl From < TIMEOUT_CTL_TCNTAEN_A > for bool { # [inline (always)] fn from (variant : TIMEOUT_CTL_TCNTAEN_A) -> Self { variant as u8 != 0 } } impl TIMEOUT_CTL_TCNTAEN_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> TIMEOUT_CTL_TCNTAEN_A { match self . bits { false => TIMEOUT_CTL_TCNTAEN_A :: TIMEOUT_CTL_TCNTAEN_DISABLE , true => TIMEOUT_CTL_TCNTAEN_A :: TIMEOUT_CTL_TCNTAEN_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_timeout_ctl_tcntaen_disable (& self) -> bool { * self == TIMEOUT_CTL_TCNTAEN_A :: TIMEOUT_CTL_TCNTAEN_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_timeout_ctl_tcntaen_enable (& self) -> bool { * self == TIMEOUT_CTL_TCNTAEN_A :: TIMEOUT_CTL_TCNTAEN_ENABLE } } # [doc = "Field `TIMEOUT_CTL_TCNTAEN` writer - Timeout Counter A Enable"] pub type TIMEOUT_CTL_TCNTAEN_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , TIMEOUT_CTL_TCNTAEN_A > ; impl < 'a , REG , const O : u8 > TIMEOUT_CTL_TCNTAEN_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn timeout_ctl_tcntaen_disable (self) -> & 'a mut crate :: W < REG > { self . variant (TIMEOUT_CTL_TCNTAEN_A :: TIMEOUT_CTL_TCNTAEN_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn timeout_ctl_tcntaen_enable (self) -> & 'a mut crate :: W < REG > { self . variant (TIMEOUT_CTL_TCNTAEN_A :: TIMEOUT_CTL_TCNTAEN_ENABLE) } } # [doc = "Field `TIMEOUT_CTL_TCNTLB` reader - Timeout Count B Load: Counter B is used for SCL High Detection. This field contains the upper 8 bits of a 12-bit pre-load value for the Timeout B count. NOTE: The value of CNTLB must be greater than 1h. Each count is equal to 1* clock period. For example, with 10MHz functional clock one timeout period will be equal to1*100ns."] pub type TIMEOUT_CTL_TCNTLB_R = crate :: FieldReader ; # [doc = "Field `TIMEOUT_CTL_TCNTLB` writer - Timeout Count B Load: Counter B is used for SCL High Detection. This field contains the upper 8 bits of a 12-bit pre-load value for the Timeout B count. NOTE: The value of CNTLB must be greater than 1h. Each count is equal to 1* clock period. For example, with 10MHz functional clock one timeout period will be equal to1*100ns."] pub type TIMEOUT_CTL_TCNTLB_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 8 , O > ; # [doc = "Field `TIMEOUT_CTL_TCNTBEN` reader - Timeout Counter B Enable"] pub type TIMEOUT_CTL_TCNTBEN_R = crate :: BitReader < TIMEOUT_CTL_TCNTBEN_A > ; # [doc = "Timeout Counter B Enable\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum TIMEOUT_CTL_TCNTBEN_A { # [doc = "0: DISABLE"] TIMEOUT_CTL_TCNTBEN_DISABLE = 0 , # [doc = "1: ENABLE"] TIMEOUT_CTL_TCNTBEN_ENABLE = 1 , } impl From < TIMEOUT_CTL_TCNTBEN_A > for bool { # [inline (always)] fn from (variant : TIMEOUT_CTL_TCNTBEN_A) -> Self { variant as u8 != 0 } } impl TIMEOUT_CTL_TCNTBEN_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> TIMEOUT_CTL_TCNTBEN_A { match self . bits { false => TIMEOUT_CTL_TCNTBEN_A :: TIMEOUT_CTL_TCNTBEN_DISABLE , true => TIMEOUT_CTL_TCNTBEN_A :: TIMEOUT_CTL_TCNTBEN_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_timeout_ctl_tcntben_disable (& self) -> bool { * self == TIMEOUT_CTL_TCNTBEN_A :: TIMEOUT_CTL_TCNTBEN_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_timeout_ctl_tcntben_enable (& self) -> bool { * self == TIMEOUT_CTL_TCNTBEN_A :: TIMEOUT_CTL_TCNTBEN_ENABLE } } # [doc = "Field `TIMEOUT_CTL_TCNTBEN` writer - Timeout Counter B Enable"] pub type TIMEOUT_CTL_TCNTBEN_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , TIMEOUT_CTL_TCNTBEN_A > ; impl < 'a , REG , const O : u8 > TIMEOUT_CTL_TCNTBEN_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn timeout_ctl_tcntben_disable (self) -> & 'a mut crate :: W < REG > { self . variant (TIMEOUT_CTL_TCNTBEN_A :: TIMEOUT_CTL_TCNTBEN_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn timeout_ctl_tcntben_enable (self) -> & 'a mut crate :: W < REG > { self . variant (TIMEOUT_CTL_TCNTBEN_A :: TIMEOUT_CTL_TCNTBEN_ENABLE) } } impl R { # [doc = "Bits 0:7 - Timeout counter A load value Counter A is used for SCL low detection. This field contains the upper 8 bits of a 12-bit pre-load value for the Timeout A count. NOTE: The value of CNTLA must be greater than 1h. Each count is equal to 520 times the timeout period of functional clock. For example, with 8MHz functional clock and a 100KHz operating I2C clock, one timeout period will be equal to (1 / 8MHz) * 520 or 65 us."] # [inline (always)] pub fn timeout_ctl_tcntla (& self) -> TIMEOUT_CTL_TCNTLA_R { TIMEOUT_CTL_TCNTLA_R :: new ((self . bits & 0xff) as u8) } # [doc = "Bit 15 - Timeout Counter A Enable"] # [inline (always)] pub fn timeout_ctl_tcntaen (& self) -> TIMEOUT_CTL_TCNTAEN_R { TIMEOUT_CTL_TCNTAEN_R :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bits 16:23 - Timeout Count B Load: Counter B is used for SCL High Detection. This field contains the upper 8 bits of a 12-bit pre-load value for the Timeout B count. NOTE: The value of CNTLB must be greater than 1h. Each count is equal to 1* clock period. For example, with 10MHz functional clock one timeout period will be equal to1*100ns."] # [inline (always)] pub fn timeout_ctl_tcntlb (& self) -> TIMEOUT_CTL_TCNTLB_R { TIMEOUT_CTL_TCNTLB_R :: new (((self . bits >> 16) & 0xff) as u8) } # [doc = "Bit 31 - Timeout Counter B Enable"] # [inline (always)] pub fn timeout_ctl_tcntben (& self) -> TIMEOUT_CTL_TCNTBEN_R { TIMEOUT_CTL_TCNTBEN_R :: new (((self . bits >> 31) & 1) != 0) } } impl W { # [doc = "Bits 0:7 - Timeout counter A load value Counter A is used for SCL low detection. This field contains the upper 8 bits of a 12-bit pre-load value for the Timeout A count. NOTE: The value of CNTLA must be greater than 1h. Each count is equal to 520 times the timeout period of functional clock. For example, with 8MHz functional clock and a 100KHz operating I2C clock, one timeout period will be equal to (1 / 8MHz) * 520 or 65 us."] # [inline (always)] # [must_use] pub fn timeout_ctl_tcntla (& mut self) -> TIMEOUT_CTL_TCNTLA_W < TIMEOUT_CTL_SPEC , 0 > { TIMEOUT_CTL_TCNTLA_W :: new (self) } # [doc = "Bit 15 - Timeout Counter A Enable"] # [inline (always)] # [must_use] pub fn timeout_ctl_tcntaen (& mut self) -> TIMEOUT_CTL_TCNTAEN_W < TIMEOUT_CTL_SPEC , 15 > { TIMEOUT_CTL_TCNTAEN_W :: new (self) } # [doc = "Bits 16:23 - Timeout Count B Load: Counter B is used for SCL High Detection. This field contains the upper 8 bits of a 12-bit pre-load value for the Timeout B count. NOTE: The value of CNTLB must be greater than 1h. Each count is equal to 1* clock period. For example, with 10MHz functional clock one timeout period will be equal to1*100ns."] # [inline (always)] # [must_use] pub fn timeout_ctl_tcntlb (& mut self) -> TIMEOUT_CTL_TCNTLB_W < TIMEOUT_CTL_SPEC , 16 > { TIMEOUT_CTL_TCNTLB_W :: new (self) } # [doc = "Bit 31 - Timeout Counter B Enable"] # [inline (always)] # [must_use] pub fn timeout_ctl_tcntben (& mut self) -> TIMEOUT_CTL_TCNTBEN_W <'_, TIMEOUT_CTL_SPEC , 31 > { TIMEOUT_CTL_TCNTBEN_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "I2C Timeout Count Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`timeout_ctl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`timeout_ctl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct TIMEOUT_CTL_SPEC ; impl crate :: RegisterSpec for TIMEOUT_CTL_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`timeout_ctl::R`](R) reader structure"] impl crate :: Readable for TIMEOUT_CTL_SPEC { } # [doc = "`write(|w| ..)` method takes [`timeout_ctl::W`](W) writer structure"] impl crate :: Writable for TIMEOUT_CTL_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets TIMEOUT_CTL to value 0x0002_0002"] impl crate :: Resettable for TIMEOUT_CTL_SPEC { const RESET_VALUE : Self :: Ux = 0x0002_0002 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/uart0/pdbgctl.rs:5:247 [INFO] [stdout] | [INFO] [stdout] 5 | ...se] pub fn pdbgctl_free (& mut self) -> PDBGCTL_FREE_W < PDBGCTL_SPEC , 0 > { PDBGCTL_FREE_W :: new (self) } # [doc = "Bit 1 - Soft ha... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 5 | is set to 'STOP'"] # [inline (always)] pub fn pdbgctl_soft (& self) -> PDBGCTL_SOFT_R { PDBGCTL_SOFT_R :: new (((self . bits >> 1) & 1) != 0) } } impl W { # [doc = "Bit 0 - Free run control"] # [inline (always)] # [must_use] pub fn pdbgctl_free (& mut self) -> PDBGCTL_FREE_W <'_, PDBGCTL_SPEC , 0 > { PDBGCTL_FREE_W :: new (self) } # [doc = "Bit 1 - Soft halt boundary control. This function is only available, if \\[FREE\\] [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/uart0/pdbgctl.rs:6:74 [INFO] [stdout] | [INFO] [stdout] 6 | ...se] pub fn pdbgctl_soft (& mut self) -> PDBGCTL_SOFT_W < PDBGCTL_SPEC , 1 > { PDBGCTL_SOFT_W :: new (self) } # [doc = r" Writes raw bi... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 6 | is set to 'STOP'"] # [inline (always)] # [must_use] pub fn pdbgctl_soft (& mut self) -> PDBGCTL_SOFT_W <'_, PDBGCTL_SPEC , 1 > { PDBGCTL_SOFT_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Peripheral Debug Control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pdbgctl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pdbgctl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PDBGCTL_SPEC ; impl crate :: RegisterSpec for PDBGCTL_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`pdbgctl::R`](R) reader structure"] impl crate :: Readable for PDBGCTL_SPEC { } # [doc = "`write(|w| ..)` method takes [`pdbgctl::W`](W) writer structure"] impl crate :: Writable for PDBGCTL_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets PDBGCTL to value 0"] impl crate :: Resettable for PDBGCTL_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/i2c0/mfifoctl.rs:1:13018 [INFO] [stdout] | [INFO] [stdout] 1 | ...ub fn mfifoctl_rxtrig (& mut self) -> MFIFOCTL_RXTRIG_W < MFIFOCTL_SPEC , 8 > { MFIFOCTL_RXTRIG_W :: new (self) } # [doc = "Bit 15 - R... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `MFIFOCTL` reader"] pub type R = crate :: R < MFIFOCTL_SPEC > ; # [doc = "Register `MFIFOCTL` writer"] pub type W = crate :: W < MFIFOCTL_SPEC > ; # [doc = "Field `MFIFOCTL_TXTRIG` reader - TX FIFO Trigger Indicates at what fill level in the TX FIFO a trigger will be generated."] pub type MFIFOCTL_TXTRIG_R = crate :: FieldReader < MFIFOCTL_TXTRIG_A > ; # [doc = "TX FIFO Trigger Indicates at what fill level in the TX FIFO a trigger will be generated.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum MFIFOCTL_TXTRIG_A { # [doc = "4: LEVEL_4"] MFIFOCTL_TXTRIG_LEVEL_4 = 4 , # [doc = "5: LEVEL_5"] MFIFOCTL_TXTRIG_LEVEL_5 = 5 , # [doc = "6: LEVEL_6"] MFIFOCTL_TXTRIG_LEVEL_6 = 6 , # [doc = "7: LEVEL_7"] MFIFOCTL_TXTRIG_LEVEL_7 = 7 , } impl From < MFIFOCTL_TXTRIG_A > for u8 { # [inline (always)] fn from (variant : MFIFOCTL_TXTRIG_A) -> Self { variant as _ } } impl crate :: FieldSpec for MFIFOCTL_TXTRIG_A { type Ux = u8 ; } impl MFIFOCTL_TXTRIG_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < MFIFOCTL_TXTRIG_A > { match self . bits { 4 => Some (MFIFOCTL_TXTRIG_A :: MFIFOCTL_TXTRIG_LEVEL_4) , 5 => Some (MFIFOCTL_TXTRIG_A :: MFIFOCTL_TXTRIG_LEVEL_5) , 6 => Some (MFIFOCTL_TXTRIG_A :: MFIFOCTL_TXTRIG_LEVEL_6) , 7 => Some (MFIFOCTL_TXTRIG_A :: MFIFOCTL_TXTRIG_LEVEL_7) , _ => None , } } # [doc = "LEVEL_4"] # [inline (always)] pub fn is_mfifoctl_txtrig_level_4 (& self) -> bool { * self == MFIFOCTL_TXTRIG_A :: MFIFOCTL_TXTRIG_LEVEL_4 } # [doc = "LEVEL_5"] # [inline (always)] pub fn is_mfifoctl_txtrig_level_5 (& self) -> bool { * self == MFIFOCTL_TXTRIG_A :: MFIFOCTL_TXTRIG_LEVEL_5 } # [doc = "LEVEL_6"] # [inline (always)] pub fn is_mfifoctl_txtrig_level_6 (& self) -> bool { * self == MFIFOCTL_TXTRIG_A :: MFIFOCTL_TXTRIG_LEVEL_6 } # [doc = "LEVEL_7"] # [inline (always)] pub fn is_mfifoctl_txtrig_level_7 (& self) -> bool { * self == MFIFOCTL_TXTRIG_A :: MFIFOCTL_TXTRIG_LEVEL_7 } } # [doc = "Field `MFIFOCTL_TXTRIG` writer - TX FIFO Trigger Indicates at what fill level in the TX FIFO a trigger will be generated."] pub type MFIFOCTL_TXTRIG_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 3 , O , MFIFOCTL_TXTRIG_A > ; impl < 'a , REG , const O : u8 > MFIFOCTL_TXTRIG_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "LEVEL_4"] # [inline (always)] pub fn mfifoctl_txtrig_level_4 (self) -> & 'a mut crate :: W < REG > { self . variant (MFIFOCTL_TXTRIG_A :: MFIFOCTL_TXTRIG_LEVEL_4) } # [doc = "LEVEL_5"] # [inline (always)] pub fn mfifoctl_txtrig_level_5 (self) -> & 'a mut crate :: W < REG > { self . variant (MFIFOCTL_TXTRIG_A :: MFIFOCTL_TXTRIG_LEVEL_5) } # [doc = "LEVEL_6"] # [inline (always)] pub fn mfifoctl_txtrig_level_6 (self) -> & 'a mut crate :: W < REG > { self . variant (MFIFOCTL_TXTRIG_A :: MFIFOCTL_TXTRIG_LEVEL_6) } # [doc = "LEVEL_7"] # [inline (always)] pub fn mfifoctl_txtrig_level_7 (self) -> & 'a mut crate :: W < REG > { self . variant (MFIFOCTL_TXTRIG_A :: MFIFOCTL_TXTRIG_LEVEL_7) } } # [doc = "Field `MFIFOCTL_TXFLUSH` reader - TX FIFO Flush Setting this bit will Flush the TX FIFO. Before reseting this bit to stop Flush the TXFIFOCNT should be checked to be 8 and indicating that the Flush has completed."] pub type MFIFOCTL_TXFLUSH_R = crate :: BitReader < MFIFOCTL_TXFLUSH_A > ; # [doc = "TX FIFO Flush Setting this bit will Flush the TX FIFO. Before reseting this bit to stop Flush the TXFIFOCNT should be checked to be 8 and indicating that the Flush has completed.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum MFIFOCTL_TXFLUSH_A { # [doc = "0: NOFLUSH"] MFIFOCTL_TXFLUSH_NOFLUSH = 0 , # [doc = "1: FLUSH"] MFIFOCTL_TXFLUSH_FLUSH = 1 , } impl From < MFIFOCTL_TXFLUSH_A > for bool { # [inline (always)] fn from (variant : MFIFOCTL_TXFLUSH_A) -> Self { variant as u8 != 0 } } impl MFIFOCTL_TXFLUSH_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> MFIFOCTL_TXFLUSH_A { match self . bits { false => MFIFOCTL_TXFLUSH_A :: MFIFOCTL_TXFLUSH_NOFLUSH , true => MFIFOCTL_TXFLUSH_A :: MFIFOCTL_TXFLUSH_FLUSH , } } # [doc = "NOFLUSH"] # [inline (always)] pub fn is_mfifoctl_txflush_noflush (& self) -> bool { * self == MFIFOCTL_TXFLUSH_A :: MFIFOCTL_TXFLUSH_NOFLUSH } # [doc = "FLUSH"] # [inline (always)] pub fn is_mfifoctl_txflush_flush (& self) -> bool { * self == MFIFOCTL_TXFLUSH_A :: MFIFOCTL_TXFLUSH_FLUSH } } # [doc = "Field `MFIFOCTL_TXFLUSH` writer - TX FIFO Flush Setting this bit will Flush the TX FIFO. Before reseting this bit to stop Flush the TXFIFOCNT should be checked to be 8 and indicating that the Flush has completed."] pub type MFIFOCTL_TXFLUSH_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , MFIFOCTL_TXFLUSH_A > ; impl < 'a , REG , const O : u8 > MFIFOCTL_TXFLUSH_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NOFLUSH"] # [inline (always)] pub fn mfifoctl_txflush_noflush (self) -> & 'a mut crate :: W < REG > { self . variant (MFIFOCTL_TXFLUSH_A :: MFIFOCTL_TXFLUSH_NOFLUSH) } # [doc = "FLUSH"] # [inline (always)] pub fn mfifoctl_txflush_flush (self) -> & 'a mut crate :: W < REG > { self . variant (MFIFOCTL_TXFLUSH_A :: MFIFOCTL_TXFLUSH_FLUSH) } } # [doc = "Field `MFIFOCTL_RXTRIG` reader - RX FIFO Trigger Indicates at what fill level in the RX FIFO a trigger will be generated. Note: Programming RXTRIG to 0x0 has no effect since no data is present to transfer out of RX FIFO."] pub type MFIFOCTL_RXTRIG_R = crate :: FieldReader < MFIFOCTL_RXTRIG_A > ; # [doc = "RX FIFO Trigger Indicates at what fill level in the RX FIFO a trigger will be generated. Note: Programming RXTRIG to 0x0 has no effect since no data is present to transfer out of RX FIFO.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum MFIFOCTL_RXTRIG_A { # [doc = "4: LEVEL_5"] MFIFOCTL_RXTRIG_LEVEL_5 = 4 , # [doc = "5: LEVEL_6"] MFIFOCTL_RXTRIG_LEVEL_6 = 5 , # [doc = "6: LEVEL_7"] MFIFOCTL_RXTRIG_LEVEL_7 = 6 , # [doc = "7: LEVEL_8"] MFIFOCTL_RXTRIG_LEVEL_8 = 7 , } impl From < MFIFOCTL_RXTRIG_A > for u8 { # [inline (always)] fn from (variant : MFIFOCTL_RXTRIG_A) -> Self { variant as _ } } impl crate :: FieldSpec for MFIFOCTL_RXTRIG_A { type Ux = u8 ; } impl MFIFOCTL_RXTRIG_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < MFIFOCTL_RXTRIG_A > { match self . bits { 4 => Some (MFIFOCTL_RXTRIG_A :: MFIFOCTL_RXTRIG_LEVEL_5) , 5 => Some (MFIFOCTL_RXTRIG_A :: MFIFOCTL_RXTRIG_LEVEL_6) , 6 => Some (MFIFOCTL_RXTRIG_A :: MFIFOCTL_RXTRIG_LEVEL_7) , 7 => Some (MFIFOCTL_RXTRIG_A :: MFIFOCTL_RXTRIG_LEVEL_8) , _ => None , } } # [doc = "LEVEL_5"] # [inline (always)] pub fn is_mfifoctl_rxtrig_level_5 (& self) -> bool { * self == MFIFOCTL_RXTRIG_A :: MFIFOCTL_RXTRIG_LEVEL_5 } # [doc = "LEVEL_6"] # [inline (always)] pub fn is_mfifoctl_rxtrig_level_6 (& self) -> bool { * self == MFIFOCTL_RXTRIG_A :: MFIFOCTL_RXTRIG_LEVEL_6 } # [doc = "LEVEL_7"] # [inline (always)] pub fn is_mfifoctl_rxtrig_level_7 (& self) -> bool { * self == MFIFOCTL_RXTRIG_A :: MFIFOCTL_RXTRIG_LEVEL_7 } # [doc = "LEVEL_8"] # [inline (always)] pub fn is_mfifoctl_rxtrig_level_8 (& self) -> bool { * self == MFIFOCTL_RXTRIG_A :: MFIFOCTL_RXTRIG_LEVEL_8 } } # [doc = "Field `MFIFOCTL_RXTRIG` writer - RX FIFO Trigger Indicates at what fill level in the RX FIFO a trigger will be generated. Note: Programming RXTRIG to 0x0 has no effect since no data is present to transfer out of RX FIFO."] pub type MFIFOCTL_RXTRIG_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 3 , O , MFIFOCTL_RXTRIG_A > ; impl < 'a , REG , const O : u8 > MFIFOCTL_RXTRIG_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "LEVEL_5"] # [inline (always)] pub fn mfifoctl_rxtrig_level_5 (self) -> & 'a mut crate :: W < REG > { self . variant (MFIFOCTL_RXTRIG_A :: MFIFOCTL_RXTRIG_LEVEL_5) } # [doc = "LEVEL_6"] # [inline (always)] pub fn mfifoctl_rxtrig_level_6 (self) -> & 'a mut crate :: W < REG > { self . variant (MFIFOCTL_RXTRIG_A :: MFIFOCTL_RXTRIG_LEVEL_6) } # [doc = "LEVEL_7"] # [inline (always)] pub fn mfifoctl_rxtrig_level_7 (self) -> & 'a mut crate :: W < REG > { self . variant (MFIFOCTL_RXTRIG_A :: MFIFOCTL_RXTRIG_LEVEL_7) } # [doc = "LEVEL_8"] # [inline (always)] pub fn mfifoctl_rxtrig_level_8 (self) -> & 'a mut crate :: W < REG > { self . variant (MFIFOCTL_RXTRIG_A :: MFIFOCTL_RXTRIG_LEVEL_8) } } # [doc = "Field `MFIFOCTL_RXFLUSH` reader - RX FIFO Flush Setting this bit will Flush the RX FIFO. Before reseting this bit to stop Flush the RXFIFOCNT should be checked to be 0 and indicating that the Flush has completed."] pub type MFIFOCTL_RXFLUSH_R = crate :: BitReader < MFIFOCTL_RXFLUSH_A > ; # [doc = "RX FIFO Flush Setting this bit will Flush the RX FIFO. Before reseting this bit to stop Flush the RXFIFOCNT should be checked to be 0 and indicating that the Flush has completed.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum MFIFOCTL_RXFLUSH_A { # [doc = "0: NOFLUSH"] MFIFOCTL_RXFLUSH_NOFLUSH = 0 , # [doc = "1: FLUSH"] MFIFOCTL_RXFLUSH_FLUSH = 1 , } impl From < MFIFOCTL_RXFLUSH_A > for bool { # [inline (always)] fn from (variant : MFIFOCTL_RXFLUSH_A) -> Self { variant as u8 != 0 } } impl MFIFOCTL_RXFLUSH_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> MFIFOCTL_RXFLUSH_A { match self . bits { false => MFIFOCTL_RXFLUSH_A :: MFIFOCTL_RXFLUSH_NOFLUSH , true => MFIFOCTL_RXFLUSH_A :: MFIFOCTL_RXFLUSH_FLUSH , } } # [doc = "NOFLUSH"] # [inline (always)] pub fn is_mfifoctl_rxflush_noflush (& self) -> bool { * self == MFIFOCTL_RXFLUSH_A :: MFIFOCTL_RXFLUSH_NOFLUSH } # [doc = "FLUSH"] # [inline (always)] pub fn is_mfifoctl_rxflush_flush (& self) -> bool { * self == MFIFOCTL_RXFLUSH_A :: MFIFOCTL_RXFLUSH_FLUSH } } # [doc = "Field `MFIFOCTL_RXFLUSH` writer - RX FIFO Flush Setting this bit will Flush the RX FIFO. Before reseting this bit to stop Flush the RXFIFOCNT should be checked to be 0 and indicating that the Flush has completed."] pub type MFIFOCTL_RXFLUSH_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , MFIFOCTL_RXFLUSH_A > ; impl < 'a , REG , const O : u8 > MFIFOCTL_RXFLUSH_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NOFLUSH"] # [inline (always)] pub fn mfifoctl_rxflush_noflush (self) -> & 'a mut crate :: W < REG > { self . variant (MFIFOCTL_RXFLUSH_A :: MFIFOCTL_RXFLUSH_NOFLUSH) } # [doc = "FLUSH"] # [inline (always)] pub fn mfifoctl_rxflush_flush (self) -> & 'a mut crate :: W < REG > { self . variant (MFIFOCTL_RXFLUSH_A :: MFIFOCTL_RXFLUSH_FLUSH) } } impl R { # [doc = "Bits 0:2 - TX FIFO Trigger Indicates at what fill level in the TX FIFO a trigger will be generated."] # [inline (always)] pub fn mfifoctl_txtrig (& self) -> MFIFOCTL_TXTRIG_R { MFIFOCTL_TXTRIG_R :: new ((self . bits & 7) as u8) } # [doc = "Bit 7 - TX FIFO Flush Setting this bit will Flush the TX FIFO. Before reseting this bit to stop Flush the TXFIFOCNT should be checked to be 8 and indicating that the Flush has completed."] # [inline (always)] pub fn mfifoctl_txflush (& self) -> MFIFOCTL_TXFLUSH_R { MFIFOCTL_TXFLUSH_R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bits 8:10 - RX FIFO Trigger Indicates at what fill level in the RX FIFO a trigger will be generated. Note: Programming RXTRIG to 0x0 has no effect since no data is present to transfer out of RX FIFO."] # [inline (always)] pub fn mfifoctl_rxtrig (& self) -> MFIFOCTL_RXTRIG_R { MFIFOCTL_RXTRIG_R :: new (((self . bits >> 8) & 7) as u8) } # [doc = "Bit 15 - RX FIFO Flush Setting this bit will Flush the RX FIFO. Before reseting this bit to stop Flush the RXFIFOCNT should be checked to be 0 and indicating that the Flush has completed."] # [inline (always)] pub fn mfifoctl_rxflush (& self) -> MFIFOCTL_RXFLUSH_R { MFIFOCTL_RXFLUSH_R :: new (((self . bits >> 15) & 1) != 0) } } impl W { # [doc = "Bits 0:2 - TX FIFO Trigger Indicates at what fill level in the TX FIFO a trigger will be generated."] # [inline (always)] # [must_use] pub fn mfifoctl_txtrig (& mut self) -> MFIFOCTL_TXTRIG_W < MFIFOCTL_SPEC , 0 > { MFIFOCTL_TXTRIG_W :: new (self) } # [doc = "Bit 7 - TX FIFO Flush Setting this bit will Flush the TX FIFO. Before reseting this bit to stop Flush the TXFIFOCNT should be checked to be 8 and indicating that the Flush has completed."] # [inline (always)] # [must_use] pub fn mfifoctl_txflush (& mut self) -> MFIFOCTL_TXFLUSH_W < MFIFOCTL_SPEC , 7 > { MFIFOCTL_TXFLUSH_W :: new (self) } # [doc = "Bits 8:10 - RX FIFO Trigger Indicates at what fill level in the RX FIFO a trigger will be generated. Note: Programming RXTRIG to 0x0 has no effect since no data is present to transfer out of RX FIFO."] # [inline (always)] # [must_use] pub fn mfifoctl_rxtrig (& mut self) -> MFIFOCTL_RXTRIG_W <'_, MFIFOCTL_SPEC , 8 > { MFIFOCTL_RXTRIG_W :: new (self) } # [doc = "Bit 15 - RX FIFO Flush Setting this bit will Flush the RX FIFO. Before reseting this bit to stop Flush the RXFIFOCNT should be checked to be 0 and indicating that the Flush has completed."] # [inline (always)] # [must_use] pub fn mfifoctl_rxflush (& mut self) -> MFIFOCTL_RXFLUSH_W < MFIFOCTL_SPEC , 15 > { MFIFOCTL_RXFLUSH_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "I2C Master FIFO Control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mfifoctl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mfifoctl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct MFIFOCTL_SPEC ; impl crate :: RegisterSpec for MFIFOCTL_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`mfifoctl::R`](R) reader structure"] impl crate :: Readable for MFIFOCTL_SPEC { } # [doc = "`write(|w| ..)` method takes [`mfifoctl::W`](W) writer structure"] impl crate :: Writable for MFIFOCTL_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets MFIFOCTL to value 0"] impl crate :: Resettable for MFIFOCTL_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/i2c1/soar2.rs:1:4254 [INFO] [stdout] | [INFO] [stdout] 1 | ...use] pub fn soar2_oar2en (& mut self) -> SOAR2_OAR2EN_W < SOAR2_SPEC , 7 > { SOAR2_OAR2EN_W :: new (self) } # [doc = "Bits 16:22 - I2C... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `SOAR2` reader"] pub type R = crate :: R < SOAR2_SPEC > ; # [doc = "Register `SOAR2` writer"] pub type W = crate :: W < SOAR2_SPEC > ; # [doc = "Field `SOAR2_OAR2` reader - I2C Slave Own Address 2 This field specifies the alternate OAR2 address."] pub type SOAR2_OAR2_R = crate :: FieldReader ; # [doc = "Field `SOAR2_OAR2` writer - I2C Slave Own Address 2 This field specifies the alternate OAR2 address."] pub type SOAR2_OAR2_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 7 , O > ; # [doc = "Field `SOAR2_OAR2EN` reader - I2C Slave Own Address 2 Enable"] pub type SOAR2_OAR2EN_R = crate :: BitReader < SOAR2_OAR2EN_A > ; # [doc = "I2C Slave Own Address 2 Enable\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum SOAR2_OAR2EN_A { # [doc = "0: DISABLE"] SOAR2_OAR2EN_DISABLE = 0 , # [doc = "1: ENABLE"] SOAR2_OAR2EN_ENABLE = 1 , } impl From < SOAR2_OAR2EN_A > for bool { # [inline (always)] fn from (variant : SOAR2_OAR2EN_A) -> Self { variant as u8 != 0 } } impl SOAR2_OAR2EN_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> SOAR2_OAR2EN_A { match self . bits { false => SOAR2_OAR2EN_A :: SOAR2_OAR2EN_DISABLE , true => SOAR2_OAR2EN_A :: SOAR2_OAR2EN_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_soar2_oar2en_disable (& self) -> bool { * self == SOAR2_OAR2EN_A :: SOAR2_OAR2EN_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_soar2_oar2en_enable (& self) -> bool { * self == SOAR2_OAR2EN_A :: SOAR2_OAR2EN_ENABLE } } # [doc = "Field `SOAR2_OAR2EN` writer - I2C Slave Own Address 2 Enable"] pub type SOAR2_OAR2EN_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , SOAR2_OAR2EN_A > ; impl < 'a , REG , const O : u8 > SOAR2_OAR2EN_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn soar2_oar2en_disable (self) -> & 'a mut crate :: W < REG > { self . variant (SOAR2_OAR2EN_A :: SOAR2_OAR2EN_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn soar2_oar2en_enable (self) -> & 'a mut crate :: W < REG > { self . variant (SOAR2_OAR2EN_A :: SOAR2_OAR2EN_ENABLE) } } # [doc = "Field `SOAR2_OAR2_MASK` reader - I2C Slave Own Address 2 Mask: This field specifies bits A6 through A0 of the slave address. The bits with value 1 in SOAR2.OAR2_MASK field will make the corresponding incoming address bits to match by default regardless of the value inside SOAR2.OAR2 i.e. corresponding SOAR2.OAR2 bit is a dont care."] pub type SOAR2_OAR2_MASK_R = crate :: FieldReader ; # [doc = "Field `SOAR2_OAR2_MASK` writer - I2C Slave Own Address 2 Mask: This field specifies bits A6 through A0 of the slave address. The bits with value 1 in SOAR2.OAR2_MASK field will make the corresponding incoming address bits to match by default regardless of the value inside SOAR2.OAR2 i.e. corresponding SOAR2.OAR2 bit is a dont care."] pub type SOAR2_OAR2_MASK_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 7 , O > ; impl R { # [doc = "Bits 0:6 - I2C Slave Own Address 2 This field specifies the alternate OAR2 address."] # [inline (always)] pub fn soar2_oar2 (& self) -> SOAR2_OAR2_R { SOAR2_OAR2_R :: new ((self . bits & 0x7f) as u8) } # [doc = "Bit 7 - I2C Slave Own Address 2 Enable"] # [inline (always)] pub fn soar2_oar2en (& self) -> SOAR2_OAR2EN_R { SOAR2_OAR2EN_R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bits 16:22 - I2C Slave Own Address 2 Mask: This field specifies bits A6 through A0 of the slave address. The bits with value 1 in SOAR2.OAR2_MASK field will make the corresponding incoming address bits to match by default regardless of the value inside SOAR2.OAR2 i.e. corresponding SOAR2.OAR2 bit is a dont care."] # [inline (always)] pub fn soar2_oar2_mask (& self) -> SOAR2_OAR2_MASK_R { SOAR2_OAR2_MASK_R :: new (((self . bits >> 16) & 0x7f) as u8) } } impl W { # [doc = "Bits 0:6 - I2C Slave Own Address 2 This field specifies the alternate OAR2 address."] # [inline (always)] # [must_use] pub fn soar2_oar2 (& mut self) -> SOAR2_OAR2_W < SOAR2_SPEC , 0 > { SOAR2_OAR2_W :: new (self) } # [doc = "Bit 7 - I2C Slave Own Address 2 Enable"] # [inline (always)] # [must_use] pub fn soar2_oar2en (& mut self) -> SOAR2_OAR2EN_W <'_, SOAR2_SPEC , 7 > { SOAR2_OAR2EN_W :: new (self) } # [doc = "Bits 16:22 - I2C Slave Own Address 2 Mask: This field specifies bits A6 through A0 of the slave address. The bits with value 1 in SOAR2.OAR2_MASK field will make the corresponding incoming address bits to match by default regardless of the value inside SOAR2.OAR2 i.e. corresponding SOAR2.OAR2 bit is a dont care."] # [inline (always)] # [must_use] pub fn soar2_oar2_mask (& mut self) -> SOAR2_OAR2_MASK_W < SOAR2_SPEC , 16 > { SOAR2_OAR2_MASK_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "I2C Slave Own Address 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`soar2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`soar2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct SOAR2_SPEC ; impl crate :: RegisterSpec for SOAR2_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`soar2::R`](R) reader structure"] impl crate :: Readable for SOAR2_SPEC { } # [doc = "`write(|w| ..)` method takes [`soar2::W`](W) writer structure"] impl crate :: Writable for SOAR2_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets SOAR2 to value 0"] impl crate :: Resettable for SOAR2_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/i2c1/mctr.rs:1:13518 [INFO] [stdout] | [INFO] [stdout] 1 | ...st_use] pub fn mctr_mblen (& mut self) -> MCTR_MBLEN_W < MCTR_SPEC , 16 > { MCTR_MBLEN_W :: new (self) } # [doc = r" Writes raw bits t... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `MCTR` reader"] pub type R = crate :: R < MCTR_SPEC > ; # [doc = "Register `MCTR` writer"] pub type W = crate :: W < MCTR_SPEC > ; # [doc = "Field `MCTR_BURSTRUN` reader - I2C Master Enable and start transaction"] pub type MCTR_BURSTRUN_R = crate :: BitReader < MCTR_BURSTRUN_A > ; # [doc = "I2C Master Enable and start transaction\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum MCTR_BURSTRUN_A { # [doc = "0: DISABLE"] MCTR_BURSTRUN_DISABLE = 0 , # [doc = "1: ENABLE"] MCTR_BURSTRUN_ENABLE = 1 , } impl From < MCTR_BURSTRUN_A > for bool { # [inline (always)] fn from (variant : MCTR_BURSTRUN_A) -> Self { variant as u8 != 0 } } impl MCTR_BURSTRUN_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> MCTR_BURSTRUN_A { match self . bits { false => MCTR_BURSTRUN_A :: MCTR_BURSTRUN_DISABLE , true => MCTR_BURSTRUN_A :: MCTR_BURSTRUN_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_mctr_burstrun_disable (& self) -> bool { * self == MCTR_BURSTRUN_A :: MCTR_BURSTRUN_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_mctr_burstrun_enable (& self) -> bool { * self == MCTR_BURSTRUN_A :: MCTR_BURSTRUN_ENABLE } } # [doc = "Field `MCTR_BURSTRUN` writer - I2C Master Enable and start transaction"] pub type MCTR_BURSTRUN_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , MCTR_BURSTRUN_A > ; impl < 'a , REG , const O : u8 > MCTR_BURSTRUN_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn mctr_burstrun_disable (self) -> & 'a mut crate :: W < REG > { self . variant (MCTR_BURSTRUN_A :: MCTR_BURSTRUN_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn mctr_burstrun_enable (self) -> & 'a mut crate :: W < REG > { self . variant (MCTR_BURSTRUN_A :: MCTR_BURSTRUN_ENABLE) } } # [doc = "Field `MCTR_START` reader - Generate START"] pub type MCTR_START_R = crate :: BitReader < MCTR_START_A > ; # [doc = "Generate START\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum MCTR_START_A { # [doc = "0: DISABLE"] MCTR_START_DISABLE = 0 , # [doc = "1: ENABLE"] MCTR_START_ENABLE = 1 , } impl From < MCTR_START_A > for bool { # [inline (always)] fn from (variant : MCTR_START_A) -> Self { variant as u8 != 0 } } impl MCTR_START_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> MCTR_START_A { match self . bits { false => MCTR_START_A :: MCTR_START_DISABLE , true => MCTR_START_A :: MCTR_START_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_mctr_start_disable (& self) -> bool { * self == MCTR_START_A :: MCTR_START_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_mctr_start_enable (& self) -> bool { * self == MCTR_START_A :: MCTR_START_ENABLE } } # [doc = "Field `MCTR_START` writer - Generate START"] pub type MCTR_START_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , MCTR_START_A > ; impl < 'a , REG , const O : u8 > MCTR_START_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn mctr_start_disable (self) -> & 'a mut crate :: W < REG > { self . variant (MCTR_START_A :: MCTR_START_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn mctr_start_enable (self) -> & 'a mut crate :: W < REG > { self . variant (MCTR_START_A :: MCTR_START_ENABLE) } } # [doc = "Field `MCTR_STOP` reader - Generate STOP"] pub type MCTR_STOP_R = crate :: BitReader < MCTR_STOP_A > ; # [doc = "Generate STOP\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum MCTR_STOP_A { # [doc = "0: DISABLE"] MCTR_STOP_DISABLE = 0 , # [doc = "1: ENABLE"] MCTR_STOP_ENABLE = 1 , } impl From < MCTR_STOP_A > for bool { # [inline (always)] fn from (variant : MCTR_STOP_A) -> Self { variant as u8 != 0 } } impl MCTR_STOP_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> MCTR_STOP_A { match self . bits { false => MCTR_STOP_A :: MCTR_STOP_DISABLE , true => MCTR_STOP_A :: MCTR_STOP_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_mctr_stop_disable (& self) -> bool { * self == MCTR_STOP_A :: MCTR_STOP_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_mctr_stop_enable (& self) -> bool { * self == MCTR_STOP_A :: MCTR_STOP_ENABLE } } # [doc = "Field `MCTR_STOP` writer - Generate STOP"] pub type MCTR_STOP_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , MCTR_STOP_A > ; impl < 'a , REG , const O : u8 > MCTR_STOP_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn mctr_stop_disable (self) -> & 'a mut crate :: W < REG > { self . variant (MCTR_STOP_A :: MCTR_STOP_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn mctr_stop_enable (self) -> & 'a mut crate :: W < REG > { self . variant (MCTR_STOP_A :: MCTR_STOP_ENABLE) } } # [doc = "Field `MCTR_ACK` reader - Data Acknowledge Enable. Software needs to configure this bit to send the ACK or NACK. See field decoding in Table: MCTR Field decoding."] pub type MCTR_ACK_R = crate :: BitReader < MCTR_ACK_A > ; # [doc = "Data Acknowledge Enable. Software needs to configure this bit to send the ACK or NACK. See field decoding in Table: MCTR Field decoding.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum MCTR_ACK_A { # [doc = "0: DISABLE"] MCTR_ACK_DISABLE = 0 , # [doc = "1: ENABLE"] MCTR_ACK_ENABLE = 1 , } impl From < MCTR_ACK_A > for bool { # [inline (always)] fn from (variant : MCTR_ACK_A) -> Self { variant as u8 != 0 } } impl MCTR_ACK_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> MCTR_ACK_A { match self . bits { false => MCTR_ACK_A :: MCTR_ACK_DISABLE , true => MCTR_ACK_A :: MCTR_ACK_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_mctr_ack_disable (& self) -> bool { * self == MCTR_ACK_A :: MCTR_ACK_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_mctr_ack_enable (& self) -> bool { * self == MCTR_ACK_A :: MCTR_ACK_ENABLE } } # [doc = "Field `MCTR_ACK` writer - Data Acknowledge Enable. Software needs to configure this bit to send the ACK or NACK. See field decoding in Table: MCTR Field decoding."] pub type MCTR_ACK_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , MCTR_ACK_A > ; impl < 'a , REG , const O : u8 > MCTR_ACK_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn mctr_ack_disable (self) -> & 'a mut crate :: W < REG > { self . variant (MCTR_ACK_A :: MCTR_ACK_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn mctr_ack_enable (self) -> & 'a mut crate :: W < REG > { self . variant (MCTR_ACK_A :: MCTR_ACK_ENABLE) } } # [doc = "Field `MCTR_MACKOEN` reader - Master ACK overrride Enable"] pub type MCTR_MACKOEN_R = crate :: BitReader < MCTR_MACKOEN_A > ; # [doc = "Master ACK overrride Enable\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum MCTR_MACKOEN_A { # [doc = "0: DISABLE"] MCTR_MACKOEN_DISABLE = 0 , # [doc = "1: ENABLE"] MCTR_MACKOEN_ENABLE = 1 , } impl From < MCTR_MACKOEN_A > for bool { # [inline (always)] fn from (variant : MCTR_MACKOEN_A) -> Self { variant as u8 != 0 } } impl MCTR_MACKOEN_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> MCTR_MACKOEN_A { match self . bits { false => MCTR_MACKOEN_A :: MCTR_MACKOEN_DISABLE , true => MCTR_MACKOEN_A :: MCTR_MACKOEN_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_mctr_mackoen_disable (& self) -> bool { * self == MCTR_MACKOEN_A :: MCTR_MACKOEN_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_mctr_mackoen_enable (& self) -> bool { * self == MCTR_MACKOEN_A :: MCTR_MACKOEN_ENABLE } } # [doc = "Field `MCTR_MACKOEN` writer - Master ACK overrride Enable"] pub type MCTR_MACKOEN_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , MCTR_MACKOEN_A > ; impl < 'a , REG , const O : u8 > MCTR_MACKOEN_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn mctr_mackoen_disable (self) -> & 'a mut crate :: W < REG > { self . variant (MCTR_MACKOEN_A :: MCTR_MACKOEN_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn mctr_mackoen_enable (self) -> & 'a mut crate :: W < REG > { self . variant (MCTR_MACKOEN_A :: MCTR_MACKOEN_ENABLE) } } # [doc = "Field `MCTR_RD_ON_TXEMPTY` reader - Read on TX Empty"] pub type MCTR_RD_ON_TXEMPTY_R = crate :: BitReader < MCTR_RD_ON_TXEMPTY_A > ; # [doc = "Read on TX Empty\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum MCTR_RD_ON_TXEMPTY_A { # [doc = "0: DISABLE"] MCTR_RD_ON_TXEMPTY_DISABLE = 0 , # [doc = "1: ENABLE"] MCTR_RD_ON_TXEMPTY_ENABLE = 1 , } impl From < MCTR_RD_ON_TXEMPTY_A > for bool { # [inline (always)] fn from (variant : MCTR_RD_ON_TXEMPTY_A) -> Self { variant as u8 != 0 } } impl MCTR_RD_ON_TXEMPTY_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> MCTR_RD_ON_TXEMPTY_A { match self . bits { false => MCTR_RD_ON_TXEMPTY_A :: MCTR_RD_ON_TXEMPTY_DISABLE , true => MCTR_RD_ON_TXEMPTY_A :: MCTR_RD_ON_TXEMPTY_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_mctr_rd_on_txempty_disable (& self) -> bool { * self == MCTR_RD_ON_TXEMPTY_A :: MCTR_RD_ON_TXEMPTY_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_mctr_rd_on_txempty_enable (& self) -> bool { * self == MCTR_RD_ON_TXEMPTY_A :: MCTR_RD_ON_TXEMPTY_ENABLE } } # [doc = "Field `MCTR_RD_ON_TXEMPTY` writer - Read on TX Empty"] pub type MCTR_RD_ON_TXEMPTY_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , MCTR_RD_ON_TXEMPTY_A > ; impl < 'a , REG , const O : u8 > MCTR_RD_ON_TXEMPTY_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn mctr_rd_on_txempty_disable (self) -> & 'a mut crate :: W < REG > { self . variant (MCTR_RD_ON_TXEMPTY_A :: MCTR_RD_ON_TXEMPTY_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn mctr_rd_on_txempty_enable (self) -> & 'a mut crate :: W < REG > { self . variant (MCTR_RD_ON_TXEMPTY_A :: MCTR_RD_ON_TXEMPTY_ENABLE) } } # [doc = "Field `MCTR_MBLEN` reader - I2C transaction length This field contains the programmed length of bytes of the Transaction."] pub type MCTR_MBLEN_R = crate :: FieldReader < u16 > ; # [doc = "Field `MCTR_MBLEN` writer - I2C transaction length This field contains the programmed length of bytes of the Transaction."] pub type MCTR_MBLEN_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 12 , O , u16 > ; impl R { # [doc = "Bit 0 - I2C Master Enable and start transaction"] # [inline (always)] pub fn mctr_burstrun (& self) -> MCTR_BURSTRUN_R { MCTR_BURSTRUN_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - Generate START"] # [inline (always)] pub fn mctr_start (& self) -> MCTR_START_R { MCTR_START_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - Generate STOP"] # [inline (always)] pub fn mctr_stop (& self) -> MCTR_STOP_R { MCTR_STOP_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - Data Acknowledge Enable. Software needs to configure this bit to send the ACK or NACK. See field decoding in Table: MCTR Field decoding."] # [inline (always)] pub fn mctr_ack (& self) -> MCTR_ACK_R { MCTR_ACK_R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - Master ACK overrride Enable"] # [inline (always)] pub fn mctr_mackoen (& self) -> MCTR_MACKOEN_R { MCTR_MACKOEN_R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - Read on TX Empty"] # [inline (always)] pub fn mctr_rd_on_txempty (& self) -> MCTR_RD_ON_TXEMPTY_R { MCTR_RD_ON_TXEMPTY_R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bits 16:27 - I2C transaction length This field contains the programmed length of bytes of the Transaction."] # [inline (always)] pub fn mctr_mblen (& self) -> MCTR_MBLEN_R { MCTR_MBLEN_R :: new (((self . bits >> 16) & 0x0fff) as u16) } } impl W { # [doc = "Bit 0 - I2C Master Enable and start transaction"] # [inline (always)] # [must_use] pub fn mctr_burstrun (& mut self) -> MCTR_BURSTRUN_W < MCTR_SPEC , 0 > { MCTR_BURSTRUN_W :: new (self) } # [doc = "Bit 1 - Generate START"] # [inline (always)] # [must_use] pub fn mctr_start (& mut self) -> MCTR_START_W < MCTR_SPEC , 1 > { MCTR_START_W :: new (self) } # [doc = "Bit 2 - Generate STOP"] # [inline (always)] # [must_use] pub fn mctr_stop (& mut self) -> MCTR_STOP_W < MCTR_SPEC , 2 > { MCTR_STOP_W :: new (self) } # [doc = "Bit 3 - Data Acknowledge Enable. Software needs to configure this bit to send the ACK or NACK. See field decoding in Table: MCTR Field decoding."] # [inline (always)] # [must_use] pub fn mctr_ack (& mut self) -> MCTR_ACK_W < MCTR_SPEC , 3 > { MCTR_ACK_W :: new (self) } # [doc = "Bit 4 - Master ACK overrride Enable"] # [inline (always)] # [must_use] pub fn mctr_mackoen (& mut self) -> MCTR_MACKOEN_W < MCTR_SPEC , 4 > { MCTR_MACKOEN_W :: new (self) } # [doc = "Bit 5 - Read on TX Empty"] # [inline (always)] # [must_use] pub fn mctr_rd_on_txempty (& mut self) -> MCTR_RD_ON_TXEMPTY_W < MCTR_SPEC , 5 > { MCTR_RD_ON_TXEMPTY_W :: new (self) } # [doc = "Bits 16:27 - I2C transaction length This field contains the programmed length of bytes of the Transaction."] # [inline (always)] # [must_use] pub fn mctr_mblen (& mut self) -> MCTR_MBLEN_W <'_, MCTR_SPEC , 16 > { MCTR_MBLEN_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "I2C Master Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mctr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mctr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct MCTR_SPEC ; impl crate :: RegisterSpec for MCTR_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`mctr::R`](R) reader structure"] impl crate :: Readable for MCTR_SPEC { } # [doc = "`write(|w| ..)` method takes [`mctr::W`](W) writer structure"] impl crate :: Writable for MCTR_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets MCTR to value 0"] impl crate :: Resettable for MCTR_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/i2c0/sctr.rs:1:26213 [INFO] [stdout] | [INFO] [stdout] 1 | ... fn sctr_en_defhostadr (& mut self) -> SCTR_EN_DEFHOSTADR_W < SCTR_SPEC , 7 > { SCTR_EN_DEFHOSTADR_W :: new (self) } # [doc = "Bit 8 -... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `SCTR` reader"] pub type R = crate :: R < SCTR_SPEC > ; # [doc = "Register `SCTR` writer"] pub type W = crate :: W < SCTR_SPEC > ; # [doc = "Field `SCTR_ACTIVE` reader - Device Active. Setting this bit enables the slave functionality."] pub type SCTR_ACTIVE_R = crate :: BitReader < SCTR_ACTIVE_A > ; # [doc = "Device Active. Setting this bit enables the slave functionality.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum SCTR_ACTIVE_A { # [doc = "0: DISABLE"] SCTR_ACTIVE_DISABLE = 0 , # [doc = "1: ENABLE"] SCTR_ACTIVE_ENABLE = 1 , } impl From < SCTR_ACTIVE_A > for bool { # [inline (always)] fn from (variant : SCTR_ACTIVE_A) -> Self { variant as u8 != 0 } } impl SCTR_ACTIVE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> SCTR_ACTIVE_A { match self . bits { false => SCTR_ACTIVE_A :: SCTR_ACTIVE_DISABLE , true => SCTR_ACTIVE_A :: SCTR_ACTIVE_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_sctr_active_disable (& self) -> bool { * self == SCTR_ACTIVE_A :: SCTR_ACTIVE_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_sctr_active_enable (& self) -> bool { * self == SCTR_ACTIVE_A :: SCTR_ACTIVE_ENABLE } } # [doc = "Field `SCTR_ACTIVE` writer - Device Active. Setting this bit enables the slave functionality."] pub type SCTR_ACTIVE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , SCTR_ACTIVE_A > ; impl < 'a , REG , const O : u8 > SCTR_ACTIVE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn sctr_active_disable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_ACTIVE_A :: SCTR_ACTIVE_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn sctr_active_enable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_ACTIVE_A :: SCTR_ACTIVE_ENABLE) } } # [doc = "Field `SCTR_GENCALL` reader - General call response enable. This bit is only available in UCBxI2COA0. Modify only when UCSWRST = 1. 0b = Do not respond to a general call 1b = Respond to a general call"] pub type SCTR_GENCALL_R = crate :: BitReader < SCTR_GENCALL_A > ; # [doc = "General call response enable. This bit is only available in UCBxI2COA0. Modify only when UCSWRST = 1. 0b = Do not respond to a general call 1b = Respond to a general call\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum SCTR_GENCALL_A { # [doc = "0: DISABLE"] SCTR_GENCALL_DISABLE = 0 , # [doc = "1: ENABLE"] SCTR_GENCALL_ENABLE = 1 , } impl From < SCTR_GENCALL_A > for bool { # [inline (always)] fn from (variant : SCTR_GENCALL_A) -> Self { variant as u8 != 0 } } impl SCTR_GENCALL_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> SCTR_GENCALL_A { match self . bits { false => SCTR_GENCALL_A :: SCTR_GENCALL_DISABLE , true => SCTR_GENCALL_A :: SCTR_GENCALL_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_sctr_gencall_disable (& self) -> bool { * self == SCTR_GENCALL_A :: SCTR_GENCALL_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_sctr_gencall_enable (& self) -> bool { * self == SCTR_GENCALL_A :: SCTR_GENCALL_ENABLE } } # [doc = "Field `SCTR_GENCALL` writer - General call response enable. This bit is only available in UCBxI2COA0. Modify only when UCSWRST = 1. 0b = Do not respond to a general call 1b = Respond to a general call"] pub type SCTR_GENCALL_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , SCTR_GENCALL_A > ; impl < 'a , REG , const O : u8 > SCTR_GENCALL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn sctr_gencall_disable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_GENCALL_A :: SCTR_GENCALL_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn sctr_gencall_enable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_GENCALL_A :: SCTR_GENCALL_ENABLE) } } # [doc = "Field `SCTR_SCLKSTRETCH` reader - Slave Clock Stretch Enable"] pub type SCTR_SCLKSTRETCH_R = crate :: BitReader < SCTR_SCLKSTRETCH_A > ; # [doc = "Slave Clock Stretch Enable\n\nValue on reset: 1"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum SCTR_SCLKSTRETCH_A { # [doc = "0: DISABLE"] SCTR_SCLKSTRETCH_DISABLE = 0 , # [doc = "1: ENABLE"] SCTR_SCLKSTRETCH_ENABLE = 1 , } impl From < SCTR_SCLKSTRETCH_A > for bool { # [inline (always)] fn from (variant : SCTR_SCLKSTRETCH_A) -> Self { variant as u8 != 0 } } impl SCTR_SCLKSTRETCH_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> SCTR_SCLKSTRETCH_A { match self . bits { false => SCTR_SCLKSTRETCH_A :: SCTR_SCLKSTRETCH_DISABLE , true => SCTR_SCLKSTRETCH_A :: SCTR_SCLKSTRETCH_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_sctr_sclkstretch_disable (& self) -> bool { * self == SCTR_SCLKSTRETCH_A :: SCTR_SCLKSTRETCH_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_sctr_sclkstretch_enable (& self) -> bool { * self == SCTR_SCLKSTRETCH_A :: SCTR_SCLKSTRETCH_ENABLE } } # [doc = "Field `SCTR_SCLKSTRETCH` writer - Slave Clock Stretch Enable"] pub type SCTR_SCLKSTRETCH_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , SCTR_SCLKSTRETCH_A > ; impl < 'a , REG , const O : u8 > SCTR_SCLKSTRETCH_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn sctr_sclkstretch_disable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_SCLKSTRETCH_A :: SCTR_SCLKSTRETCH_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn sctr_sclkstretch_enable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_SCLKSTRETCH_A :: SCTR_SCLKSTRETCH_ENABLE) } } # [doc = "Field `SCTR_TXEMPTY_ON_TREQ` reader - Tx Empty Interrupt on TREQ"] pub type SCTR_TXEMPTY_ON_TREQ_R = crate :: BitReader < SCTR_TXEMPTY_ON_TREQ_A > ; # [doc = "Tx Empty Interrupt on TREQ\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum SCTR_TXEMPTY_ON_TREQ_A { # [doc = "0: DISABLE"] SCTR_TXEMPTY_ON_TREQ_DISABLE = 0 , # [doc = "1: ENABLE"] SCTR_TXEMPTY_ON_TREQ_ENABLE = 1 , } impl From < SCTR_TXEMPTY_ON_TREQ_A > for bool { # [inline (always)] fn from (variant : SCTR_TXEMPTY_ON_TREQ_A) -> Self { variant as u8 != 0 } } impl SCTR_TXEMPTY_ON_TREQ_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> SCTR_TXEMPTY_ON_TREQ_A { match self . bits { false => SCTR_TXEMPTY_ON_TREQ_A :: SCTR_TXEMPTY_ON_TREQ_DISABLE , true => SCTR_TXEMPTY_ON_TREQ_A :: SCTR_TXEMPTY_ON_TREQ_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_sctr_txempty_on_treq_disable (& self) -> bool { * self == SCTR_TXEMPTY_ON_TREQ_A :: SCTR_TXEMPTY_ON_TREQ_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_sctr_txempty_on_treq_enable (& self) -> bool { * self == SCTR_TXEMPTY_ON_TREQ_A :: SCTR_TXEMPTY_ON_TREQ_ENABLE } } # [doc = "Field `SCTR_TXEMPTY_ON_TREQ` writer - Tx Empty Interrupt on TREQ"] pub type SCTR_TXEMPTY_ON_TREQ_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , SCTR_TXEMPTY_ON_TREQ_A > ; impl < 'a , REG , const O : u8 > SCTR_TXEMPTY_ON_TREQ_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn sctr_txempty_on_treq_disable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_TXEMPTY_ON_TREQ_A :: SCTR_TXEMPTY_ON_TREQ_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn sctr_txempty_on_treq_enable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_TXEMPTY_ON_TREQ_A :: SCTR_TXEMPTY_ON_TREQ_ENABLE) } } # [doc = "Field `SCTR_TXTRIG_TXMODE` reader - Tx Trigger when slave FSM is in Tx Mode"] pub type SCTR_TXTRIG_TXMODE_R = crate :: BitReader < SCTR_TXTRIG_TXMODE_A > ; # [doc = "Tx Trigger when slave FSM is in Tx Mode\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum SCTR_TXTRIG_TXMODE_A { # [doc = "0: DISABLE"] SCTR_TXTRIG_TXMODE_DISABLE = 0 , # [doc = "1: ENABLE"] SCTR_TXTRIG_TXMODE_ENABLE = 1 , } impl From < SCTR_TXTRIG_TXMODE_A > for bool { # [inline (always)] fn from (variant : SCTR_TXTRIG_TXMODE_A) -> Self { variant as u8 != 0 } } impl SCTR_TXTRIG_TXMODE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> SCTR_TXTRIG_TXMODE_A { match self . bits { false => SCTR_TXTRIG_TXMODE_A :: SCTR_TXTRIG_TXMODE_DISABLE , true => SCTR_TXTRIG_TXMODE_A :: SCTR_TXTRIG_TXMODE_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_sctr_txtrig_txmode_disable (& self) -> bool { * self == SCTR_TXTRIG_TXMODE_A :: SCTR_TXTRIG_TXMODE_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_sctr_txtrig_txmode_enable (& self) -> bool { * self == SCTR_TXTRIG_TXMODE_A :: SCTR_TXTRIG_TXMODE_ENABLE } } # [doc = "Field `SCTR_TXTRIG_TXMODE` writer - Tx Trigger when slave FSM is in Tx Mode"] pub type SCTR_TXTRIG_TXMODE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , SCTR_TXTRIG_TXMODE_A > ; impl < 'a , REG , const O : u8 > SCTR_TXTRIG_TXMODE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn sctr_txtrig_txmode_disable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_TXTRIG_TXMODE_A :: SCTR_TXTRIG_TXMODE_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn sctr_txtrig_txmode_enable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_TXTRIG_TXMODE_A :: SCTR_TXTRIG_TXMODE_ENABLE) } } # [doc = "Field `SCTR_TXWAIT_STALE_TXFIFO` reader - Tx transfer waits when stale data in Tx FIFO. This prevents stale bytes left in the TX FIFO from automatically being sent on the next I2C packet. Note: this should be used with TXEMPTY_ON_TREQ set to prevent the Slave State Machine from waiting for TX FIFO data without an interrupt notification when the FIFO data is stale."] pub type SCTR_TXWAIT_STALE_TXFIFO_R = crate :: BitReader < SCTR_TXWAIT_STALE_TXFIFO_A > ; # [doc = "Tx transfer waits when stale data in Tx FIFO. This prevents stale bytes left in the TX FIFO from automatically being sent on the next I2C packet. Note: this should be used with TXEMPTY_ON_TREQ set to prevent the Slave State Machine from waiting for TX FIFO data without an interrupt notification when the FIFO data is stale.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum SCTR_TXWAIT_STALE_TXFIFO_A { # [doc = "0: DISABLE"] SCTR_TXWAIT_STALE_TXFIFO_DISABLE = 0 , # [doc = "1: ENABLE"] SCTR_TXWAIT_STALE_TXFIFO_ENABLE = 1 , } impl From < SCTR_TXWAIT_STALE_TXFIFO_A > for bool { # [inline (always)] fn from (variant : SCTR_TXWAIT_STALE_TXFIFO_A) -> Self { variant as u8 != 0 } } impl SCTR_TXWAIT_STALE_TXFIFO_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> SCTR_TXWAIT_STALE_TXFIFO_A { match self . bits { false => SCTR_TXWAIT_STALE_TXFIFO_A :: SCTR_TXWAIT_STALE_TXFIFO_DISABLE , true => SCTR_TXWAIT_STALE_TXFIFO_A :: SCTR_TXWAIT_STALE_TXFIFO_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_sctr_txwait_stale_txfifo_disable (& self) -> bool { * self == SCTR_TXWAIT_STALE_TXFIFO_A :: SCTR_TXWAIT_STALE_TXFIFO_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_sctr_txwait_stale_txfifo_enable (& self) -> bool { * self == SCTR_TXWAIT_STALE_TXFIFO_A :: SCTR_TXWAIT_STALE_TXFIFO_ENABLE } } # [doc = "Field `SCTR_TXWAIT_STALE_TXFIFO` writer - Tx transfer waits when stale data in Tx FIFO. This prevents stale bytes left in the TX FIFO from automatically being sent on the next I2C packet. Note: this should be used with TXEMPTY_ON_TREQ set to prevent the Slave State Machine from waiting for TX FIFO data without an interrupt notification when the FIFO data is stale."] pub type SCTR_TXWAIT_STALE_TXFIFO_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , SCTR_TXWAIT_STALE_TXFIFO_A > ; impl < 'a , REG , const O : u8 > SCTR_TXWAIT_STALE_TXFIFO_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn sctr_txwait_stale_txfifo_disable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_TXWAIT_STALE_TXFIFO_A :: SCTR_TXWAIT_STALE_TXFIFO_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn sctr_txwait_stale_txfifo_enable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_TXWAIT_STALE_TXFIFO_A :: SCTR_TXWAIT_STALE_TXFIFO_ENABLE) } } # [doc = "Field `SCTR_RXFULL_ON_RREQ` reader - Rx full interrupt generated on RREQ condition as indicated in SSR"] pub type SCTR_RXFULL_ON_RREQ_R = crate :: BitReader < SCTR_RXFULL_ON_RREQ_A > ; # [doc = "Rx full interrupt generated on RREQ condition as indicated in SSR\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum SCTR_RXFULL_ON_RREQ_A { # [doc = "0: DISABLE"] SCTR_RXFULL_ON_RREQ_DISABLE = 0 , # [doc = "1: ENABLE"] SCTR_RXFULL_ON_RREQ_ENABLE = 1 , } impl From < SCTR_RXFULL_ON_RREQ_A > for bool { # [inline (always)] fn from (variant : SCTR_RXFULL_ON_RREQ_A) -> Self { variant as u8 != 0 } } impl SCTR_RXFULL_ON_RREQ_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> SCTR_RXFULL_ON_RREQ_A { match self . bits { false => SCTR_RXFULL_ON_RREQ_A :: SCTR_RXFULL_ON_RREQ_DISABLE , true => SCTR_RXFULL_ON_RREQ_A :: SCTR_RXFULL_ON_RREQ_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_sctr_rxfull_on_rreq_disable (& self) -> bool { * self == SCTR_RXFULL_ON_RREQ_A :: SCTR_RXFULL_ON_RREQ_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_sctr_rxfull_on_rreq_enable (& self) -> bool { * self == SCTR_RXFULL_ON_RREQ_A :: SCTR_RXFULL_ON_RREQ_ENABLE } } # [doc = "Field `SCTR_RXFULL_ON_RREQ` writer - Rx full interrupt generated on RREQ condition as indicated in SSR"] pub type SCTR_RXFULL_ON_RREQ_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , SCTR_RXFULL_ON_RREQ_A > ; impl < 'a , REG , const O : u8 > SCTR_RXFULL_ON_RREQ_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn sctr_rxfull_on_rreq_disable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_RXFULL_ON_RREQ_A :: SCTR_RXFULL_ON_RREQ_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn sctr_rxfull_on_rreq_enable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_RXFULL_ON_RREQ_A :: SCTR_RXFULL_ON_RREQ_ENABLE) } } # [doc = "Field `SCTR_EN_DEFHOSTADR` reader - Enable Default Host Address"] pub type SCTR_EN_DEFHOSTADR_R = crate :: BitReader < SCTR_EN_DEFHOSTADR_A > ; # [doc = "Enable Default Host Address\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum SCTR_EN_DEFHOSTADR_A { # [doc = "0: DISABLE"] SCTR_EN_DEFHOSTADR_DISABLE = 0 , # [doc = "1: ENABLE"] SCTR_EN_DEFHOSTADR_ENABLE = 1 , } impl From < SCTR_EN_DEFHOSTADR_A > for bool { # [inline (always)] fn from (variant : SCTR_EN_DEFHOSTADR_A) -> Self { variant as u8 != 0 } } impl SCTR_EN_DEFHOSTADR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> SCTR_EN_DEFHOSTADR_A { match self . bits { false => SCTR_EN_DEFHOSTADR_A :: SCTR_EN_DEFHOSTADR_DISABLE , true => SCTR_EN_DEFHOSTADR_A :: SCTR_EN_DEFHOSTADR_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_sctr_en_defhostadr_disable (& self) -> bool { * self == SCTR_EN_DEFHOSTADR_A :: SCTR_EN_DEFHOSTADR_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_sctr_en_defhostadr_enable (& self) -> bool { * self == SCTR_EN_DEFHOSTADR_A :: SCTR_EN_DEFHOSTADR_ENABLE } } # [doc = "Field `SCTR_EN_DEFHOSTADR` writer - Enable Default Host Address"] pub type SCTR_EN_DEFHOSTADR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , SCTR_EN_DEFHOSTADR_A > ; impl < 'a , REG , const O : u8 > SCTR_EN_DEFHOSTADR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn sctr_en_defhostadr_disable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_EN_DEFHOSTADR_A :: SCTR_EN_DEFHOSTADR_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn sctr_en_defhostadr_enable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_EN_DEFHOSTADR_A :: SCTR_EN_DEFHOSTADR_ENABLE) } } # [doc = "Field `SCTR_EN_ALRESPADR` reader - Enable Alert Response Address"] pub type SCTR_EN_ALRESPADR_R = crate :: BitReader < SCTR_EN_ALRESPADR_A > ; # [doc = "Enable Alert Response Address\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum SCTR_EN_ALRESPADR_A { # [doc = "0: DISABLE"] SCTR_EN_ALRESPADR_DISABLE = 0 , # [doc = "1: ENABLE"] SCTR_EN_ALRESPADR_ENABLE = 1 , } impl From < SCTR_EN_ALRESPADR_A > for bool { # [inline (always)] fn from (variant : SCTR_EN_ALRESPADR_A) -> Self { variant as u8 != 0 } } impl SCTR_EN_ALRESPADR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> SCTR_EN_ALRESPADR_A { match self . bits { false => SCTR_EN_ALRESPADR_A :: SCTR_EN_ALRESPADR_DISABLE , true => SCTR_EN_ALRESPADR_A :: SCTR_EN_ALRESPADR_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_sctr_en_alrespadr_disable (& self) -> bool { * self == SCTR_EN_ALRESPADR_A :: SCTR_EN_ALRESPADR_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_sctr_en_alrespadr_enable (& self) -> bool { * self == SCTR_EN_ALRESPADR_A :: SCTR_EN_ALRESPADR_ENABLE } } # [doc = "Field `SCTR_EN_ALRESPADR` writer - Enable Alert Response Address"] pub type SCTR_EN_ALRESPADR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , SCTR_EN_ALRESPADR_A > ; impl < 'a , REG , const O : u8 > SCTR_EN_ALRESPADR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn sctr_en_alrespadr_disable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_EN_ALRESPADR_A :: SCTR_EN_ALRESPADR_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn sctr_en_alrespadr_enable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_EN_ALRESPADR_A :: SCTR_EN_ALRESPADR_ENABLE) } } # [doc = "Field `SCTR_EN_DEFDEVADR` reader - Enable Deault device address"] pub type SCTR_EN_DEFDEVADR_R = crate :: BitReader < SCTR_EN_DEFDEVADR_A > ; # [doc = "Enable Deault device address\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum SCTR_EN_DEFDEVADR_A { # [doc = "0: DISABLE"] SCTR_EN_DEFDEVADR_DISABLE = 0 , # [doc = "1: ENABLE"] SCTR_EN_DEFDEVADR_ENABLE = 1 , } impl From < SCTR_EN_DEFDEVADR_A > for bool { # [inline (always)] fn from (variant : SCTR_EN_DEFDEVADR_A) -> Self { variant as u8 != 0 } } impl SCTR_EN_DEFDEVADR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> SCTR_EN_DEFDEVADR_A { match self . bits { false => SCTR_EN_DEFDEVADR_A :: SCTR_EN_DEFDEVADR_DISABLE , true => SCTR_EN_DEFDEVADR_A :: SCTR_EN_DEFDEVADR_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_sctr_en_defdevadr_disable (& self) -> bool { * self == SCTR_EN_DEFDEVADR_A :: SCTR_EN_DEFDEVADR_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_sctr_en_defdevadr_enable (& self) -> bool { * self == SCTR_EN_DEFDEVADR_A :: SCTR_EN_DEFDEVADR_ENABLE } } # [doc = "Field `SCTR_EN_DEFDEVADR` writer - Enable Deault device address"] pub type SCTR_EN_DEFDEVADR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , SCTR_EN_DEFDEVADR_A > ; impl < 'a , REG , const O : u8 > SCTR_EN_DEFDEVADR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn sctr_en_defdevadr_disable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_EN_DEFDEVADR_A :: SCTR_EN_DEFDEVADR_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn sctr_en_defdevadr_enable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_EN_DEFDEVADR_A :: SCTR_EN_DEFDEVADR_ENABLE) } } # [doc = "Field `SCTR_SWUEN` reader - Slave Wakeup Enable"] pub type SCTR_SWUEN_R = crate :: BitReader < SCTR_SWUEN_A > ; # [doc = "Slave Wakeup Enable\n\nValue on reset: 1"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum SCTR_SWUEN_A { # [doc = "0: DISABLE"] SCTR_SWUEN_DISABLE = 0 , # [doc = "1: ENABLE"] SCTR_SWUEN_ENABLE = 1 , } impl From < SCTR_SWUEN_A > for bool { # [inline (always)] fn from (variant : SCTR_SWUEN_A) -> Self { variant as u8 != 0 } } impl SCTR_SWUEN_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> SCTR_SWUEN_A { match self . bits { false => SCTR_SWUEN_A :: SCTR_SWUEN_DISABLE , true => SCTR_SWUEN_A :: SCTR_SWUEN_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_sctr_swuen_disable (& self) -> bool { * self == SCTR_SWUEN_A :: SCTR_SWUEN_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_sctr_swuen_enable (& self) -> bool { * self == SCTR_SWUEN_A :: SCTR_SWUEN_ENABLE } } # [doc = "Field `SCTR_SWUEN` writer - Slave Wakeup Enable"] pub type SCTR_SWUEN_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , SCTR_SWUEN_A > ; impl < 'a , REG , const O : u8 > SCTR_SWUEN_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn sctr_swuen_disable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_SWUEN_A :: SCTR_SWUEN_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn sctr_swuen_enable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_SWUEN_A :: SCTR_SWUEN_ENABLE) } } impl R { # [doc = "Bit 0 - Device Active. Setting this bit enables the slave functionality."] # [inline (always)] pub fn sctr_active (& self) -> SCTR_ACTIVE_R { SCTR_ACTIVE_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - General call response enable. This bit is only available in UCBxI2COA0. Modify only when UCSWRST = 1. 0b = Do not respond to a general call 1b = Respond to a general call"] # [inline (always)] pub fn sctr_gencall (& self) -> SCTR_GENCALL_R { SCTR_GENCALL_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - Slave Clock Stretch Enable"] # [inline (always)] pub fn sctr_sclkstretch (& self) -> SCTR_SCLKSTRETCH_R { SCTR_SCLKSTRETCH_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - Tx Empty Interrupt on TREQ"] # [inline (always)] pub fn sctr_txempty_on_treq (& self) -> SCTR_TXEMPTY_ON_TREQ_R { SCTR_TXEMPTY_ON_TREQ_R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - Tx Trigger when slave FSM is in Tx Mode"] # [inline (always)] pub fn sctr_txtrig_txmode (& self) -> SCTR_TXTRIG_TXMODE_R { SCTR_TXTRIG_TXMODE_R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - Tx transfer waits when stale data in Tx FIFO. This prevents stale bytes left in the TX FIFO from automatically being sent on the next I2C packet. Note: this should be used with TXEMPTY_ON_TREQ set to prevent the Slave State Machine from waiting for TX FIFO data without an interrupt notification when the FIFO data is stale."] # [inline (always)] pub fn sctr_txwait_stale_txfifo (& self) -> SCTR_TXWAIT_STALE_TXFIFO_R { SCTR_TXWAIT_STALE_TXFIFO_R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - Rx full interrupt generated on RREQ condition as indicated in SSR"] # [inline (always)] pub fn sctr_rxfull_on_rreq (& self) -> SCTR_RXFULL_ON_RREQ_R { SCTR_RXFULL_ON_RREQ_R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - Enable Default Host Address"] # [inline (always)] pub fn sctr_en_defhostadr (& self) -> SCTR_EN_DEFHOSTADR_R { SCTR_EN_DEFHOSTADR_R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - Enable Alert Response Address"] # [inline (always)] pub fn sctr_en_alrespadr (& self) -> SCTR_EN_ALRESPADR_R { SCTR_EN_ALRESPADR_R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - Enable Deault device address"] # [inline (always)] pub fn sctr_en_defdevadr (& self) -> SCTR_EN_DEFDEVADR_R { SCTR_EN_DEFDEVADR_R :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - Slave Wakeup Enable"] # [inline (always)] pub fn sctr_swuen (& self) -> SCTR_SWUEN_R { SCTR_SWUEN_R :: new (((self . bits >> 10) & 1) != 0) } } impl W { # [doc = "Bit 0 - Device Active. Setting this bit enables the slave functionality."] # [inline (always)] # [must_use] pub fn sctr_active (& mut self) -> SCTR_ACTIVE_W < SCTR_SPEC , 0 > { SCTR_ACTIVE_W :: new (self) } # [doc = "Bit 1 - General call response enable. This bit is only available in UCBxI2COA0. Modify only when UCSWRST = 1. 0b = Do not respond to a general call 1b = Respond to a general call"] # [inline (always)] # [must_use] pub fn sctr_gencall (& mut self) -> SCTR_GENCALL_W < SCTR_SPEC , 1 > { SCTR_GENCALL_W :: new (self) } # [doc = "Bit 2 - Slave Clock Stretch Enable"] # [inline (always)] # [must_use] pub fn sctr_sclkstretch (& mut self) -> SCTR_SCLKSTRETCH_W < SCTR_SPEC , 2 > { SCTR_SCLKSTRETCH_W :: new (self) } # [doc = "Bit 3 - Tx Empty Interrupt on TREQ"] # [inline (always)] # [must_use] pub fn sctr_txempty_on_treq (& mut self) -> SCTR_TXEMPTY_ON_TREQ_W < SCTR_SPEC , 3 > { SCTR_TXEMPTY_ON_TREQ_W :: new (self) } # [doc = "Bit 4 - Tx Trigger when slave FSM is in Tx Mode"] # [inline (always)] # [must_use] pub fn sctr_txtrig_txmode (& mut self) -> SCTR_TXTRIG_TXMODE_W < SCTR_SPEC , 4 > { SCTR_TXTRIG_TXMODE_W :: new (self) } # [doc = "Bit 5 - Tx transfer waits when stale data in Tx FIFO. This prevents stale bytes left in the TX FIFO from automatically being sent on the next I2C packet. Note: this should be used with TXEMPTY_ON_TREQ set to prevent the Slave State Machine from waiting for TX FIFO data without an interrupt notification when the FIFO data is stale."] # [inline (always)] # [must_use] pub fn sctr_txwait_stale_txfifo (& mut self) -> SCTR_TXWAIT_STALE_TXFIFO_W < SCTR_SPEC , 5 > { SCTR_TXWAIT_STALE_TXFIFO_W :: new (self) } # [doc = "Bit 6 - Rx full interrupt generated on RREQ condition as indicated in SSR"] # [inline (always)] # [must_use] pub fn sctr_rxfull_on_rreq (& mut self) -> SCTR_RXFULL_ON_RREQ_W < SCTR_SPEC , 6 > { SCTR_RXFULL_ON_RREQ_W :: new (self) } # [doc = "Bit 7 - Enable Default Host Address"] # [inline (always)] # [must_use] pub fn sctr_en_defhostadr (& mut self) -> SCTR_EN_DEFHOSTADR_W <'_, SCTR_SPEC , 7 > { SCTR_EN_DEFHOSTADR_W :: new (self) } # [doc = "Bit 8 - Enable Alert Response Address"] # [inline (always)] # [must_use] pub fn sctr_en_alrespadr (& mut self) -> SCTR_EN_ALRESPADR_W < SCTR_SPEC , 8 > { SCTR_EN_ALRESPADR_W :: new (self) } # [doc = "Bit 9 - Enable Deault device address"] # [inline (always)] # [must_use] pub fn sctr_en_defdevadr (& mut self) -> SCTR_EN_DEFDEVADR_W < SCTR_SPEC , 9 > { SCTR_EN_DEFDEVADR_W :: new (self) } # [doc = "Bit 10 - Slave Wakeup Enable"] # [inline (always)] # [must_use] pub fn sctr_swuen (& mut self) -> SCTR_SWUEN_W < SCTR_SPEC , 10 > { SCTR_SWUEN_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "I2C Slave Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sctr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sctr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct SCTR_SPEC ; impl crate :: RegisterSpec for SCTR_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`sctr::R`](R) reader structure"] impl crate :: Readable for SCTR_SPEC { } # [doc = "`write(|w| ..)` method takes [`sctr::W`](W) writer structure"] impl crate :: Writable for SCTR_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets SCTR to value 0x0404"] impl crate :: Resettable for SCTR_SPEC { const RESET_VALUE : Self :: Ux = 0x0404 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/timg4/ccact_01.rs:1:23195 [INFO] [stdout] | [INFO] [stdout] 1 | ...] pub fn ccact_01_zact (& mut self) -> CCACT_01_ZACT_W < CCACT_01_SPEC , 0 > { CCACT_01_ZACT_W :: new (self) } # [doc = "Bits 3:4 - CC... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `CCACT_01[%s]` reader"] pub type R = crate :: R < CCACT_01_SPEC > ; # [doc = "Register `CCACT_01[%s]` writer"] pub type W = crate :: W < CCACT_01_SPEC > ; # [doc = "Field `CCACT_01_ZACT` reader - CCP Output Action on Zero Specifies what changes occur to CCP output as the result of a zero event."] pub type CCACT_01_ZACT_R = crate :: FieldReader < CCACT_01_ZACT_A > ; # [doc = "CCP Output Action on Zero Specifies what changes occur to CCP output as the result of a zero event.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum CCACT_01_ZACT_A { # [doc = "0: DISABLED"] CCACT_01_ZACT_DISABLED = 0 , # [doc = "1: CCP_HIGH"] CCACT_01_ZACT_CCP_HIGH = 1 , # [doc = "2: CCP_LOW"] CCACT_01_ZACT_CCP_LOW = 2 , # [doc = "3: CCP_TOGGLE"] CCACT_01_ZACT_CCP_TOGGLE = 3 , } impl From < CCACT_01_ZACT_A > for u8 { # [inline (always)] fn from (variant : CCACT_01_ZACT_A) -> Self { variant as _ } } impl crate :: FieldSpec for CCACT_01_ZACT_A { type Ux = u8 ; } impl CCACT_01_ZACT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CCACT_01_ZACT_A { match self . bits { 0 => CCACT_01_ZACT_A :: CCACT_01_ZACT_DISABLED , 1 => CCACT_01_ZACT_A :: CCACT_01_ZACT_CCP_HIGH , 2 => CCACT_01_ZACT_A :: CCACT_01_ZACT_CCP_LOW , 3 => CCACT_01_ZACT_A :: CCACT_01_ZACT_CCP_TOGGLE , _ => unreachable ! () , } } # [doc = "DISABLED"] # [inline (always)] pub fn is_ccact_01_zact_disabled (& self) -> bool { * self == CCACT_01_ZACT_A :: CCACT_01_ZACT_DISABLED } # [doc = "CCP_HIGH"] # [inline (always)] pub fn is_ccact_01_zact_ccp_high (& self) -> bool { * self == CCACT_01_ZACT_A :: CCACT_01_ZACT_CCP_HIGH } # [doc = "CCP_LOW"] # [inline (always)] pub fn is_ccact_01_zact_ccp_low (& self) -> bool { * self == CCACT_01_ZACT_A :: CCACT_01_ZACT_CCP_LOW } # [doc = "CCP_TOGGLE"] # [inline (always)] pub fn is_ccact_01_zact_ccp_toggle (& self) -> bool { * self == CCACT_01_ZACT_A :: CCACT_01_ZACT_CCP_TOGGLE } } # [doc = "Field `CCACT_01_ZACT` writer - CCP Output Action on Zero Specifies what changes occur to CCP output as the result of a zero event."] pub type CCACT_01_ZACT_W < 'a , REG , const O : u8 > = crate :: FieldWriterSafe < 'a , REG , 2 , O , CCACT_01_ZACT_A > ; impl < 'a , REG , const O : u8 > CCACT_01_ZACT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "DISABLED"] # [inline (always)] pub fn ccact_01_zact_disabled (self) -> & 'a mut crate :: W < REG > { self . variant (CCACT_01_ZACT_A :: CCACT_01_ZACT_DISABLED) } # [doc = "CCP_HIGH"] # [inline (always)] pub fn ccact_01_zact_ccp_high (self) -> & 'a mut crate :: W < REG > { self . variant (CCACT_01_ZACT_A :: CCACT_01_ZACT_CCP_HIGH) } # [doc = "CCP_LOW"] # [inline (always)] pub fn ccact_01_zact_ccp_low (self) -> & 'a mut crate :: W < REG > { self . variant (CCACT_01_ZACT_A :: CCACT_01_ZACT_CCP_LOW) } # [doc = "CCP_TOGGLE"] # [inline (always)] pub fn ccact_01_zact_ccp_toggle (self) -> & 'a mut crate :: W < REG > { self . variant (CCACT_01_ZACT_A :: CCACT_01_ZACT_CCP_TOGGLE) } } # [doc = "Field `CCACT_01_LACT` reader - CCP Output Action on Load Specifies what changes occur to CCP output as the result of a load event."] pub type CCACT_01_LACT_R = crate :: FieldReader < CCACT_01_LACT_A > ; # [doc = "CCP Output Action on Load Specifies what changes occur to CCP output as the result of a load event.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum CCACT_01_LACT_A { # [doc = "0: DISABLED"] CCACT_01_LACT_DISABLED = 0 , # [doc = "1: CCP_HIGH"] CCACT_01_LACT_CCP_HIGH = 1 , # [doc = "2: CCP_LOW"] CCACT_01_LACT_CCP_LOW = 2 , # [doc = "3: CCP_TOGGLE"] CCACT_01_LACT_CCP_TOGGLE = 3 , } impl From < CCACT_01_LACT_A > for u8 { # [inline (always)] fn from (variant : CCACT_01_LACT_A) -> Self { variant as _ } } impl crate :: FieldSpec for CCACT_01_LACT_A { type Ux = u8 ; } impl CCACT_01_LACT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CCACT_01_LACT_A { match self . bits { 0 => CCACT_01_LACT_A :: CCACT_01_LACT_DISABLED , 1 => CCACT_01_LACT_A :: CCACT_01_LACT_CCP_HIGH , 2 => CCACT_01_LACT_A :: CCACT_01_LACT_CCP_LOW , 3 => CCACT_01_LACT_A :: CCACT_01_LACT_CCP_TOGGLE , _ => unreachable ! () , } } # [doc = "DISABLED"] # [inline (always)] pub fn is_ccact_01_lact_disabled (& self) -> bool { * self == CCACT_01_LACT_A :: CCACT_01_LACT_DISABLED } # [doc = "CCP_HIGH"] # [inline (always)] pub fn is_ccact_01_lact_ccp_high (& self) -> bool { * self == CCACT_01_LACT_A :: CCACT_01_LACT_CCP_HIGH } # [doc = "CCP_LOW"] # [inline (always)] pub fn is_ccact_01_lact_ccp_low (& self) -> bool { * self == CCACT_01_LACT_A :: CCACT_01_LACT_CCP_LOW } # [doc = "CCP_TOGGLE"] # [inline (always)] pub fn is_ccact_01_lact_ccp_toggle (& self) -> bool { * self == CCACT_01_LACT_A :: CCACT_01_LACT_CCP_TOGGLE } } # [doc = "Field `CCACT_01_LACT` writer - CCP Output Action on Load Specifies what changes occur to CCP output as the result of a load event."] pub type CCACT_01_LACT_W < 'a , REG , const O : u8 > = crate :: FieldWriterSafe < 'a , REG , 2 , O , CCACT_01_LACT_A > ; impl < 'a , REG , const O : u8 > CCACT_01_LACT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "DISABLED"] # [inline (always)] pub fn ccact_01_lact_disabled (self) -> & 'a mut crate :: W < REG > { self . variant (CCACT_01_LACT_A :: CCACT_01_LACT_DISABLED) } # [doc = "CCP_HIGH"] # [inline (always)] pub fn ccact_01_lact_ccp_high (self) -> & 'a mut crate :: W < REG > { self . variant (CCACT_01_LACT_A :: CCACT_01_LACT_CCP_HIGH) } # [doc = "CCP_LOW"] # [inline (always)] pub fn ccact_01_lact_ccp_low (self) -> & 'a mut crate :: W < REG > { self . variant (CCACT_01_LACT_A :: CCACT_01_LACT_CCP_LOW) } # [doc = "CCP_TOGGLE"] # [inline (always)] pub fn ccact_01_lact_ccp_toggle (self) -> & 'a mut crate :: W < REG > { self . variant (CCACT_01_LACT_A :: CCACT_01_LACT_CCP_TOGGLE) } } # [doc = "Field `CCACT_01_CDACT` reader - CCP Output Action on Compare (Down) This field describes the resulting action of the signal generator upon detecting a compare event while counting down."] pub type CCACT_01_CDACT_R = crate :: FieldReader < CCACT_01_CDACT_A > ; # [doc = "CCP Output Action on Compare (Down) This field describes the resulting action of the signal generator upon detecting a compare event while counting down.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum CCACT_01_CDACT_A { # [doc = "0: DISABLED"] CCACT_01_CDACT_DISABLED = 0 , # [doc = "1: CCP_HIGH"] CCACT_01_CDACT_CCP_HIGH = 1 , # [doc = "2: CCP_LOW"] CCACT_01_CDACT_CCP_LOW = 2 , # [doc = "3: CCP_TOGGLE"] CCACT_01_CDACT_CCP_TOGGLE = 3 , } impl From < CCACT_01_CDACT_A > for u8 { # [inline (always)] fn from (variant : CCACT_01_CDACT_A) -> Self { variant as _ } } impl crate :: FieldSpec for CCACT_01_CDACT_A { type Ux = u8 ; } impl CCACT_01_CDACT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CCACT_01_CDACT_A { match self . bits { 0 => CCACT_01_CDACT_A :: CCACT_01_CDACT_DISABLED , 1 => CCACT_01_CDACT_A :: CCACT_01_CDACT_CCP_HIGH , 2 => CCACT_01_CDACT_A :: CCACT_01_CDACT_CCP_LOW , 3 => CCACT_01_CDACT_A :: CCACT_01_CDACT_CCP_TOGGLE , _ => unreachable ! () , } } # [doc = "DISABLED"] # [inline (always)] pub fn is_ccact_01_cdact_disabled (& self) -> bool { * self == CCACT_01_CDACT_A :: CCACT_01_CDACT_DISABLED } # [doc = "CCP_HIGH"] # [inline (always)] pub fn is_ccact_01_cdact_ccp_high (& self) -> bool { * self == CCACT_01_CDACT_A :: CCACT_01_CDACT_CCP_HIGH } # [doc = "CCP_LOW"] # [inline (always)] pub fn is_ccact_01_cdact_ccp_low (& self) -> bool { * self == CCACT_01_CDACT_A :: CCACT_01_CDACT_CCP_LOW } # [doc = "CCP_TOGGLE"] # [inline (always)] pub fn is_ccact_01_cdact_ccp_toggle (& self) -> bool { * self == CCACT_01_CDACT_A :: CCACT_01_CDACT_CCP_TOGGLE } } # [doc = "Field `CCACT_01_CDACT` writer - CCP Output Action on Compare (Down) This field describes the resulting action of the signal generator upon detecting a compare event while counting down."] pub type CCACT_01_CDACT_W < 'a , REG , const O : u8 > = crate :: FieldWriterSafe < 'a , REG , 2 , O , CCACT_01_CDACT_A > ; impl < 'a , REG , const O : u8 > CCACT_01_CDACT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "DISABLED"] # [inline (always)] pub fn ccact_01_cdact_disabled (self) -> & 'a mut crate :: W < REG > { self . variant (CCACT_01_CDACT_A :: CCACT_01_CDACT_DISABLED) } # [doc = "CCP_HIGH"] # [inline (always)] pub fn ccact_01_cdact_ccp_high (self) -> & 'a mut crate :: W < REG > { self . variant (CCACT_01_CDACT_A :: CCACT_01_CDACT_CCP_HIGH) } # [doc = "CCP_LOW"] # [inline (always)] pub fn ccact_01_cdact_ccp_low (self) -> & 'a mut crate :: W < REG > { self . variant (CCACT_01_CDACT_A :: CCACT_01_CDACT_CCP_LOW) } # [doc = "CCP_TOGGLE"] # [inline (always)] pub fn ccact_01_cdact_ccp_toggle (self) -> & 'a mut crate :: W < REG > { self . variant (CCACT_01_CDACT_A :: CCACT_01_CDACT_CCP_TOGGLE) } } # [doc = "Field `CCACT_01_CUACT` reader - CCP Output Action on Compare (Up) This field describes the resulting action of the signal generator upon detecting a compare event while counting up."] pub type CCACT_01_CUACT_R = crate :: FieldReader < CCACT_01_CUACT_A > ; # [doc = "CCP Output Action on Compare (Up) This field describes the resulting action of the signal generator upon detecting a compare event while counting up.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum CCACT_01_CUACT_A { # [doc = "0: DISABLED"] CCACT_01_CUACT_DISABLED = 0 , # [doc = "1: CCP_HIGH"] CCACT_01_CUACT_CCP_HIGH = 1 , # [doc = "2: CCP_LOW"] CCACT_01_CUACT_CCP_LOW = 2 , # [doc = "3: CCP_TOGGLE"] CCACT_01_CUACT_CCP_TOGGLE = 3 , } impl From < CCACT_01_CUACT_A > for u8 { # [inline (always)] fn from (variant : CCACT_01_CUACT_A) -> Self { variant as _ } } impl crate :: FieldSpec for CCACT_01_CUACT_A { type Ux = u8 ; } impl CCACT_01_CUACT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CCACT_01_CUACT_A { match self . bits { 0 => CCACT_01_CUACT_A :: CCACT_01_CUACT_DISABLED , 1 => CCACT_01_CUACT_A :: CCACT_01_CUACT_CCP_HIGH , 2 => CCACT_01_CUACT_A :: CCACT_01_CUACT_CCP_LOW , 3 => CCACT_01_CUACT_A :: CCACT_01_CUACT_CCP_TOGGLE , _ => unreachable ! () , } } # [doc = "DISABLED"] # [inline (always)] pub fn is_ccact_01_cuact_disabled (& self) -> bool { * self == CCACT_01_CUACT_A :: CCACT_01_CUACT_DISABLED } # [doc = "CCP_HIGH"] # [inline (always)] pub fn is_ccact_01_cuact_ccp_high (& self) -> bool { * self == CCACT_01_CUACT_A :: CCACT_01_CUACT_CCP_HIGH } # [doc = "CCP_LOW"] # [inline (always)] pub fn is_ccact_01_cuact_ccp_low (& self) -> bool { * self == CCACT_01_CUACT_A :: CCACT_01_CUACT_CCP_LOW } # [doc = "CCP_TOGGLE"] # [inline (always)] pub fn is_ccact_01_cuact_ccp_toggle (& self) -> bool { * self == CCACT_01_CUACT_A :: CCACT_01_CUACT_CCP_TOGGLE } } # [doc = "Field `CCACT_01_CUACT` writer - CCP Output Action on Compare (Up) This field describes the resulting action of the signal generator upon detecting a compare event while counting up."] pub type CCACT_01_CUACT_W < 'a , REG , const O : u8 > = crate :: FieldWriterSafe < 'a , REG , 2 , O , CCACT_01_CUACT_A > ; impl < 'a , REG , const O : u8 > CCACT_01_CUACT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "DISABLED"] # [inline (always)] pub fn ccact_01_cuact_disabled (self) -> & 'a mut crate :: W < REG > { self . variant (CCACT_01_CUACT_A :: CCACT_01_CUACT_DISABLED) } # [doc = "CCP_HIGH"] # [inline (always)] pub fn ccact_01_cuact_ccp_high (self) -> & 'a mut crate :: W < REG > { self . variant (CCACT_01_CUACT_A :: CCACT_01_CUACT_CCP_HIGH) } # [doc = "CCP_LOW"] # [inline (always)] pub fn ccact_01_cuact_ccp_low (self) -> & 'a mut crate :: W < REG > { self . variant (CCACT_01_CUACT_A :: CCACT_01_CUACT_CCP_LOW) } # [doc = "CCP_TOGGLE"] # [inline (always)] pub fn ccact_01_cuact_ccp_toggle (self) -> & 'a mut crate :: W < REG > { self . variant (CCACT_01_CUACT_A :: CCACT_01_CUACT_CCP_TOGGLE) } } # [doc = "Field `CCACT_01_CC2DACT` reader - CCP Output Action on CC2D event."] pub type CCACT_01_CC2DACT_R = crate :: FieldReader < CCACT_01_CC2DACT_A > ; # [doc = "CCP Output Action on CC2D event.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum CCACT_01_CC2DACT_A { # [doc = "0: DISABLED"] CCACT_01_CC2DACT_DISABLED = 0 , # [doc = "1: CCP_HIGH"] CCACT_01_CC2DACT_CCP_HIGH = 1 , # [doc = "2: CCP_LOW"] CCACT_01_CC2DACT_CCP_LOW = 2 , # [doc = "3: CCP_TOGGLE"] CCACT_01_CC2DACT_CCP_TOGGLE = 3 , } impl From < CCACT_01_CC2DACT_A > for u8 { # [inline (always)] fn from (variant : CCACT_01_CC2DACT_A) -> Self { variant as _ } } impl crate :: FieldSpec for CCACT_01_CC2DACT_A { type Ux = u8 ; } impl CCACT_01_CC2DACT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CCACT_01_CC2DACT_A { match self . bits { 0 => CCACT_01_CC2DACT_A :: CCACT_01_CC2DACT_DISABLED , 1 => CCACT_01_CC2DACT_A :: CCACT_01_CC2DACT_CCP_HIGH , 2 => CCACT_01_CC2DACT_A :: CCACT_01_CC2DACT_CCP_LOW , 3 => CCACT_01_CC2DACT_A :: CCACT_01_CC2DACT_CCP_TOGGLE , _ => unreachable ! () , } } # [doc = "DISABLED"] # [inline (always)] pub fn is_ccact_01_cc2dact_disabled (& self) -> bool { * self == CCACT_01_CC2DACT_A :: CCACT_01_CC2DACT_DISABLED } # [doc = "CCP_HIGH"] # [inline (always)] pub fn is_ccact_01_cc2dact_ccp_high (& self) -> bool { * self == CCACT_01_CC2DACT_A :: CCACT_01_CC2DACT_CCP_HIGH } # [doc = "CCP_LOW"] # [inline (always)] pub fn is_ccact_01_cc2dact_ccp_low (& self) -> bool { * self == CCACT_01_CC2DACT_A :: CCACT_01_CC2DACT_CCP_LOW } # [doc = "CCP_TOGGLE"] # [inline (always)] pub fn is_ccact_01_cc2dact_ccp_toggle (& self) -> bool { * self == CCACT_01_CC2DACT_A :: CCACT_01_CC2DACT_CCP_TOGGLE } } # [doc = "Field `CCACT_01_CC2DACT` writer - CCP Output Action on CC2D event."] pub type CCACT_01_CC2DACT_W < 'a , REG , const O : u8 > = crate :: FieldWriterSafe < 'a , REG , 2 , O , CCACT_01_CC2DACT_A > ; impl < 'a , REG , const O : u8 > CCACT_01_CC2DACT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "DISABLED"] # [inline (always)] pub fn ccact_01_cc2dact_disabled (self) -> & 'a mut crate :: W < REG > { self . variant (CCACT_01_CC2DACT_A :: CCACT_01_CC2DACT_DISABLED) } # [doc = "CCP_HIGH"] # [inline (always)] pub fn ccact_01_cc2dact_ccp_high (self) -> & 'a mut crate :: W < REG > { self . variant (CCACT_01_CC2DACT_A :: CCACT_01_CC2DACT_CCP_HIGH) } # [doc = "CCP_LOW"] # [inline (always)] pub fn ccact_01_cc2dact_ccp_low (self) -> & 'a mut crate :: W < REG > { self . variant (CCACT_01_CC2DACT_A :: CCACT_01_CC2DACT_CCP_LOW) } # [doc = "CCP_TOGGLE"] # [inline (always)] pub fn ccact_01_cc2dact_ccp_toggle (self) -> & 'a mut crate :: W < REG > { self . variant (CCACT_01_CC2DACT_A :: CCACT_01_CC2DACT_CCP_TOGGLE) } } # [doc = "Field `CCACT_01_CC2UACT` reader - CCP Output Action on CC2U event."] pub type CCACT_01_CC2UACT_R = crate :: FieldReader < CCACT_01_CC2UACT_A > ; # [doc = "CCP Output Action on CC2U event.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum CCACT_01_CC2UACT_A { # [doc = "0: DISABLED"] CCACT_01_CC2UACT_DISABLED = 0 , # [doc = "1: CCP_HIGH"] CCACT_01_CC2UACT_CCP_HIGH = 1 , # [doc = "2: CCP_LOW"] CCACT_01_CC2UACT_CCP_LOW = 2 , # [doc = "3: CCP_TOGGLE"] CCACT_01_CC2UACT_CCP_TOGGLE = 3 , } impl From < CCACT_01_CC2UACT_A > for u8 { # [inline (always)] fn from (variant : CCACT_01_CC2UACT_A) -> Self { variant as _ } } impl crate :: FieldSpec for CCACT_01_CC2UACT_A { type Ux = u8 ; } impl CCACT_01_CC2UACT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CCACT_01_CC2UACT_A { match self . bits { 0 => CCACT_01_CC2UACT_A :: CCACT_01_CC2UACT_DISABLED , 1 => CCACT_01_CC2UACT_A :: CCACT_01_CC2UACT_CCP_HIGH , 2 => CCACT_01_CC2UACT_A :: CCACT_01_CC2UACT_CCP_LOW , 3 => CCACT_01_CC2UACT_A :: CCACT_01_CC2UACT_CCP_TOGGLE , _ => unreachable ! () , } } # [doc = "DISABLED"] # [inline (always)] pub fn is_ccact_01_cc2uact_disabled (& self) -> bool { * self == CCACT_01_CC2UACT_A :: CCACT_01_CC2UACT_DISABLED } # [doc = "CCP_HIGH"] # [inline (always)] pub fn is_ccact_01_cc2uact_ccp_high (& self) -> bool { * self == CCACT_01_CC2UACT_A :: CCACT_01_CC2UACT_CCP_HIGH } # [doc = "CCP_LOW"] # [inline (always)] pub fn is_ccact_01_cc2uact_ccp_low (& self) -> bool { * self == CCACT_01_CC2UACT_A :: CCACT_01_CC2UACT_CCP_LOW } # [doc = "CCP_TOGGLE"] # [inline (always)] pub fn is_ccact_01_cc2uact_ccp_toggle (& self) -> bool { * self == CCACT_01_CC2UACT_A :: CCACT_01_CC2UACT_CCP_TOGGLE } } # [doc = "Field `CCACT_01_CC2UACT` writer - CCP Output Action on CC2U event."] pub type CCACT_01_CC2UACT_W < 'a , REG , const O : u8 > = crate :: FieldWriterSafe < 'a , REG , 2 , O , CCACT_01_CC2UACT_A > ; impl < 'a , REG , const O : u8 > CCACT_01_CC2UACT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "DISABLED"] # [inline (always)] pub fn ccact_01_cc2uact_disabled (self) -> & 'a mut crate :: W < REG > { self . variant (CCACT_01_CC2UACT_A :: CCACT_01_CC2UACT_DISABLED) } # [doc = "CCP_HIGH"] # [inline (always)] pub fn ccact_01_cc2uact_ccp_high (self) -> & 'a mut crate :: W < REG > { self . variant (CCACT_01_CC2UACT_A :: CCACT_01_CC2UACT_CCP_HIGH) } # [doc = "CCP_LOW"] # [inline (always)] pub fn ccact_01_cc2uact_ccp_low (self) -> & 'a mut crate :: W < REG > { self . variant (CCACT_01_CC2UACT_A :: CCACT_01_CC2UACT_CCP_LOW) } # [doc = "CCP_TOGGLE"] # [inline (always)] pub fn ccact_01_cc2uact_ccp_toggle (self) -> & 'a mut crate :: W < REG > { self . variant (CCACT_01_CC2UACT_A :: CCACT_01_CC2UACT_CCP_TOGGLE) } } # [doc = "Field `CCACT_01_SWFRCACT` reader - CCP Output Action on Software Froce Output This field describes the resulting action of software force. This action has a shadow register, which will be updated under specific condition. So that this register cannot take into effect immediately."] pub type CCACT_01_SWFRCACT_R = crate :: FieldReader < CCACT_01_SWFRCACT_A > ; # [doc = "CCP Output Action on Software Froce Output This field describes the resulting action of software force. This action has a shadow register, which will be updated under specific condition. So that this register cannot take into effect immediately.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum CCACT_01_SWFRCACT_A { # [doc = "0: DISABLED"] CCACT_01_SWFRCACT_DISABLED = 0 , # [doc = "1: CCP_HIGH"] CCACT_01_SWFRCACT_CCP_HIGH = 1 , # [doc = "2: CCP_LOW"] CCACT_01_SWFRCACT_CCP_LOW = 2 , } impl From < CCACT_01_SWFRCACT_A > for u8 { # [inline (always)] fn from (variant : CCACT_01_SWFRCACT_A) -> Self { variant as _ } } impl crate :: FieldSpec for CCACT_01_SWFRCACT_A { type Ux = u8 ; } impl CCACT_01_SWFRCACT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < CCACT_01_SWFRCACT_A > { match self . bits { 0 => Some (CCACT_01_SWFRCACT_A :: CCACT_01_SWFRCACT_DISABLED) , 1 => Some (CCACT_01_SWFRCACT_A :: CCACT_01_SWFRCACT_CCP_HIGH) , 2 => Some (CCACT_01_SWFRCACT_A :: CCACT_01_SWFRCACT_CCP_LOW) , _ => None , } } # [doc = "DISABLED"] # [inline (always)] pub fn is_ccact_01_swfrcact_disabled (& self) -> bool { * self == CCACT_01_SWFRCACT_A :: CCACT_01_SWFRCACT_DISABLED } # [doc = "CCP_HIGH"] # [inline (always)] pub fn is_ccact_01_swfrcact_ccp_high (& self) -> bool { * self == CCACT_01_SWFRCACT_A :: CCACT_01_SWFRCACT_CCP_HIGH } # [doc = "CCP_LOW"] # [inline (always)] pub fn is_ccact_01_swfrcact_ccp_low (& self) -> bool { * self == CCACT_01_SWFRCACT_A :: CCACT_01_SWFRCACT_CCP_LOW } } # [doc = "Field `CCACT_01_SWFRCACT` writer - CCP Output Action on Software Froce Output This field describes the resulting action of software force. This action has a shadow register, which will be updated under specific condition. So that this register cannot take into effect immediately."] pub type CCACT_01_SWFRCACT_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 2 , O , CCACT_01_SWFRCACT_A > ; impl < 'a , REG , const O : u8 > CCACT_01_SWFRCACT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "DISABLED"] # [inline (always)] pub fn ccact_01_swfrcact_disabled (self) -> & 'a mut crate :: W < REG > { self . variant (CCACT_01_SWFRCACT_A :: CCACT_01_SWFRCACT_DISABLED) } # [doc = "CCP_HIGH"] # [inline (always)] pub fn ccact_01_swfrcact_ccp_high (self) -> & 'a mut crate :: W < REG > { self . variant (CCACT_01_SWFRCACT_A :: CCACT_01_SWFRCACT_CCP_HIGH) } # [doc = "CCP_LOW"] # [inline (always)] pub fn ccact_01_swfrcact_ccp_low (self) -> & 'a mut crate :: W < REG > { self . variant (CCACT_01_SWFRCACT_A :: CCACT_01_SWFRCACT_CCP_LOW) } } impl R { # [doc = "Bits 0:1 - CCP Output Action on Zero Specifies what changes occur to CCP output as the result of a zero event."] # [inline (always)] pub fn ccact_01_zact (& self) -> CCACT_01_ZACT_R { CCACT_01_ZACT_R :: new ((self . bits & 3) as u8) } # [doc = "Bits 3:4 - CCP Output Action on Load Specifies what changes occur to CCP output as the result of a load event."] # [inline (always)] pub fn ccact_01_lact (& self) -> CCACT_01_LACT_R { CCACT_01_LACT_R :: new (((self . bits >> 3) & 3) as u8) } # [doc = "Bits 6:7 - CCP Output Action on Compare (Down) This field describes the resulting action of the signal generator upon detecting a compare event while counting down."] # [inline (always)] pub fn ccact_01_cdact (& self) -> CCACT_01_CDACT_R { CCACT_01_CDACT_R :: new (((self . bits >> 6) & 3) as u8) } # [doc = "Bits 9:10 - CCP Output Action on Compare (Up) This field describes the resulting action of the signal generator upon detecting a compare event while counting up."] # [inline (always)] pub fn ccact_01_cuact (& self) -> CCACT_01_CUACT_R { CCACT_01_CUACT_R :: new (((self . bits >> 9) & 3) as u8) } # [doc = "Bits 12:13 - CCP Output Action on CC2D event."] # [inline (always)] pub fn ccact_01_cc2dact (& self) -> CCACT_01_CC2DACT_R { CCACT_01_CC2DACT_R :: new (((self . bits >> 12) & 3) as u8) } # [doc = "Bits 15:16 - CCP Output Action on CC2U event."] # [inline (always)] pub fn ccact_01_cc2uact (& self) -> CCACT_01_CC2UACT_R { CCACT_01_CC2UACT_R :: new (((self . bits >> 15) & 3) as u8) } # [doc = "Bits 28:29 - CCP Output Action on Software Froce Output This field describes the resulting action of software force. This action has a shadow register, which will be updated under specific condition. So that this register cannot take into effect immediately."] # [inline (always)] pub fn ccact_01_swfrcact (& self) -> CCACT_01_SWFRCACT_R { CCACT_01_SWFRCACT_R :: new (((self . bits >> 28) & 3) as u8) } } impl W { # [doc = "Bits 0:1 - CCP Output Action on Zero Specifies what changes occur to CCP output as the result of a zero event."] # [inline (always)] # [must_use] pub fn ccact_01_zact (& mut self) -> CCACT_01_ZACT_W <'_, CCACT_01_SPEC , 0 > { CCACT_01_ZACT_W :: new (self) } # [doc = "Bits 3:4 - CCP Output Action on Load Specifies what changes occur to CCP output as the result of a load event."] # [inline (always)] # [must_use] pub fn ccact_01_lact (& mut self) -> CCACT_01_LACT_W < CCACT_01_SPEC , 3 > { CCACT_01_LACT_W :: new (self) } # [doc = "Bits 6:7 - CCP Output Action on Compare (Down) This field describes the resulting action of the signal generator upon detecting a compare event while counting down."] # [inline (always)] # [must_use] pub fn ccact_01_cdact (& mut self) -> CCACT_01_CDACT_W < CCACT_01_SPEC , 6 > { CCACT_01_CDACT_W :: new (self) } # [doc = "Bits 9:10 - CCP Output Action on Compare (Up) This field describes the resulting action of the signal generator upon detecting a compare event while counting up."] # [inline (always)] # [must_use] pub fn ccact_01_cuact (& mut self) -> CCACT_01_CUACT_W < CCACT_01_SPEC , 9 > { CCACT_01_CUACT_W :: new (self) } # [doc = "Bits 12:13 - CCP Output Action on CC2D event."] # [inline (always)] # [must_use] pub fn ccact_01_cc2dact (& mut self) -> CCACT_01_CC2DACT_W < CCACT_01_SPEC , 12 > { CCACT_01_CC2DACT_W :: new (self) } # [doc = "Bits 15:16 - CCP Output Action on CC2U event."] # [inline (always)] # [must_use] pub fn ccact_01_cc2uact (& mut self) -> CCACT_01_CC2UACT_W < CCACT_01_SPEC , 15 > { CCACT_01_CC2UACT_W :: new (self) } # [doc = "Bits 28:29 - CCP Output Action on Software Froce Output This field describes the resulting action of software force. This action has a shadow register, which will be updated under specific condition. So that this register cannot take into effect immediately."] # [inline (always)] # [must_use] pub fn ccact_01_swfrcact (& mut self) -> CCACT_01_SWFRCACT_W < CCACT_01_SPEC , 28 > { CCACT_01_SWFRCACT_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Capture or Compare Action Registers\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ccact_01::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ccact_01::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CCACT_01_SPEC ; impl crate :: RegisterSpec for CCACT_01_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`ccact_01::R`](R) reader structure"] impl crate :: Readable for CCACT_01_SPEC { } # [doc = "`write(|w| ..)` method takes [`ccact_01::W`](W) writer structure"] impl crate :: Writable for CCACT_01_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets CCACT_01[%s] [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/sysctl/nmiiclr.rs:1:2374 [INFO] [stdout] | [INFO] [stdout] 1 | ...e] pub fn nmiiclr_wwdt0 (& mut self) -> NMIICLR_WWDT0_W < NMIICLR_SPEC , 1 > { NMIICLR_WWDT0_W :: new (self) } # [doc = r" Writes raw ... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `NMIICLR` writer"] pub type W = crate :: W < NMIICLR_SPEC > ; # [doc = "Clr the BORLVL NMI\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum NMIICLR_BORLVL_AW { # [doc = "0: NO_EFFECT"] NMIICLR_BORLVL_NO_EFFECT = 0 , # [doc = "1: CLR"] NMIICLR_BORLVL_CLR = 1 , } impl From < NMIICLR_BORLVL_AW > for bool { # [inline (always)] fn from (variant : NMIICLR_BORLVL_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `NMIICLR_BORLVL` writer - Clr the BORLVL NMI"] pub type NMIICLR_BORLVL_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , NMIICLR_BORLVL_AW > ; impl < 'a , REG , const O : u8 > NMIICLR_BORLVL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn nmiiclr_borlvl_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (NMIICLR_BORLVL_AW :: NMIICLR_BORLVL_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn nmiiclr_borlvl_clr (self) -> & 'a mut crate :: W < REG > { self . variant (NMIICLR_BORLVL_AW :: NMIICLR_BORLVL_CLR) } } # [doc = "Watch Dog 0 Fault\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum NMIICLR_WWDT0_AW { # [doc = "0: NO_EFFECT"] NMIICLR_WWDT0_NO_EFFECT = 0 , # [doc = "1: CLR"] NMIICLR_WWDT0_CLR = 1 , } impl From < NMIICLR_WWDT0_AW > for bool { # [inline (always)] fn from (variant : NMIICLR_WWDT0_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `NMIICLR_WWDT0` writer - Watch Dog 0 Fault"] pub type NMIICLR_WWDT0_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , NMIICLR_WWDT0_AW > ; impl < 'a , REG , const O : u8 > NMIICLR_WWDT0_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn nmiiclr_wwdt0_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (NMIICLR_WWDT0_AW :: NMIICLR_WWDT0_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn nmiiclr_wwdt0_clr (self) -> & 'a mut crate :: W < REG > { self . variant (NMIICLR_WWDT0_AW :: NMIICLR_WWDT0_CLR) } } impl W { # [doc = "Bit 0 - Clr the BORLVL NMI"] # [inline (always)] # [must_use] pub fn nmiiclr_borlvl (& mut self) -> NMIICLR_BORLVL_W < NMIICLR_SPEC , 0 > { NMIICLR_BORLVL_W :: new (self) } # [doc = "Bit 1 - Watch Dog 0 Fault"] # [inline (always)] # [must_use] pub fn nmiiclr_wwdt0 (& mut self) -> NMIICLR_WWDT0_W <'_, NMIICLR_SPEC , 1 > { NMIICLR_WWDT0_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "NMI interrupt clear\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`nmiiclr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct NMIICLR_SPEC ; impl crate :: RegisterSpec for NMIICLR_SPEC { type Ux = u32 ; } # [doc = "`write(|w| ..)` method takes [`nmiiclr::W`](W) writer structure"] impl crate :: Writable for NMIICLR_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets NMIICLR to value 0"] impl crate :: Resettable for NMIICLR_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/i2c0/int_event0_iset.rs:1:39477 [INFO] [stdout] | [INFO] [stdout] 1 | ...iset_mtxempty (& mut self) -> INT_EVENT0_ISET_MTXEMPTY_W < INT_EVENT0_ISET_SPEC , 5 > { INT_EVENT0_ISET_MTXEMPTY_W :: new (self) } # [... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `INT_EVENT0_ISET` writer"] pub type W = crate :: W < INT_EVENT0_ISET_SPEC > ; # [doc = "Master Receive Data Interrupt Signals that a byte has been received\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_MRXDONE_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_MRXDONE_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_MRXDONE_SET = 1 , } impl From < INT_EVENT0_ISET_MRXDONE_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_MRXDONE_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_MRXDONE` writer - Master Receive Data Interrupt Signals that a byte has been received"] pub type INT_EVENT0_ISET_MRXDONE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_MRXDONE_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_MRXDONE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_mrxdone_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MRXDONE_AW :: INT_EVENT0_ISET_MRXDONE_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_mrxdone_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MRXDONE_AW :: INT_EVENT0_ISET_MRXDONE_SET) } } # [doc = "Master Transmit Transaction completed Interrupt\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_MTXDONE_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_MTXDONE_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_MTXDONE_SET = 1 , } impl From < INT_EVENT0_ISET_MTXDONE_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_MTXDONE_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_MTXDONE` writer - Master Transmit Transaction completed Interrupt"] pub type INT_EVENT0_ISET_MTXDONE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_MTXDONE_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_MTXDONE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_mtxdone_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MTXDONE_AW :: INT_EVENT0_ISET_MTXDONE_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_mtxdone_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MTXDONE_AW :: INT_EVENT0_ISET_MTXDONE_SET) } } # [doc = "Master Receive FIFO Trigger Trigger when RX FIFO contains &gt;= defined bytes\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_MRXFIFOTRG_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_MRXFIFOTRG_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_MRXFIFOTRG_SET = 1 , } impl From < INT_EVENT0_ISET_MRXFIFOTRG_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_MRXFIFOTRG_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_MRXFIFOTRG` writer - Master Receive FIFO Trigger Trigger when RX FIFO contains &gt;= defined bytes"] pub type INT_EVENT0_ISET_MRXFIFOTRG_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_MRXFIFOTRG_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_MRXFIFOTRG_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_mrxfifotrg_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MRXFIFOTRG_AW :: INT_EVENT0_ISET_MRXFIFOTRG_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_mrxfifotrg_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MRXFIFOTRG_AW :: INT_EVENT0_ISET_MRXFIFOTRG_SET) } } # [doc = "Master Transmit FIFO Trigger Trigger when Transmit FIFO contains &lt;= defined bytes\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_MTXFIFOTRG_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_MTXFIFOTRG_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_MTXFIFOTRG_SET = 1 , } impl From < INT_EVENT0_ISET_MTXFIFOTRG_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_MTXFIFOTRG_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_MTXFIFOTRG` writer - Master Transmit FIFO Trigger Trigger when Transmit FIFO contains &lt;= defined bytes"] pub type INT_EVENT0_ISET_MTXFIFOTRG_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_MTXFIFOTRG_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_MTXFIFOTRG_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_mtxfifotrg_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MTXFIFOTRG_AW :: INT_EVENT0_ISET_MTXFIFOTRG_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_mtxfifotrg_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MTXFIFOTRG_AW :: INT_EVENT0_ISET_MTXFIFOTRG_SET) } } # [doc = "RXFIFO full event.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_MRXFIFOFULL_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_MRXFIFOFULL_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_MRXFIFOFULL_SET = 1 , } impl From < INT_EVENT0_ISET_MRXFIFOFULL_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_MRXFIFOFULL_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_MRXFIFOFULL` writer - RXFIFO full event."] pub type INT_EVENT0_ISET_MRXFIFOFULL_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_MRXFIFOFULL_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_MRXFIFOFULL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_mrxfifofull_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MRXFIFOFULL_AW :: INT_EVENT0_ISET_MRXFIFOFULL_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_mrxfifofull_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MRXFIFOFULL_AW :: INT_EVENT0_ISET_MRXFIFOFULL_SET) } } # [doc = "Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_MTXEMPTY_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_MTXEMPTY_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_MTXEMPTY_SET = 1 , } impl From < INT_EVENT0_ISET_MTXEMPTY_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_MTXEMPTY_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_MTXEMPTY` writer - Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode."] pub type INT_EVENT0_ISET_MTXEMPTY_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_MTXEMPTY_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_MTXEMPTY_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_mtxempty_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MTXEMPTY_AW :: INT_EVENT0_ISET_MTXEMPTY_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_mtxempty_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MTXEMPTY_AW :: INT_EVENT0_ISET_MTXEMPTY_SET) } } # [doc = "Address/Data NACK Interrupt\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_MNACK_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_MNACK_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_MNACK_SET = 1 , } impl From < INT_EVENT0_ISET_MNACK_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_MNACK_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_MNACK` writer - Address/Data NACK Interrupt"] pub type INT_EVENT0_ISET_MNACK_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_MNACK_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_MNACK_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_mnack_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MNACK_AW :: INT_EVENT0_ISET_MNACK_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_mnack_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MNACK_AW :: INT_EVENT0_ISET_MNACK_SET) } } # [doc = "START Detection Interrupt\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_MSTART_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_MSTART_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_MSTART_SET = 1 , } impl From < INT_EVENT0_ISET_MSTART_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_MSTART_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_MSTART` writer - START Detection Interrupt"] pub type INT_EVENT0_ISET_MSTART_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_MSTART_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_MSTART_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_mstart_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MSTART_AW :: INT_EVENT0_ISET_MSTART_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_mstart_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MSTART_AW :: INT_EVENT0_ISET_MSTART_SET) } } # [doc = "STOP Detection Interrupt\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_MSTOP_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_MSTOP_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_MSTOP_SET = 1 , } impl From < INT_EVENT0_ISET_MSTOP_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_MSTOP_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_MSTOP` writer - STOP Detection Interrupt"] pub type INT_EVENT0_ISET_MSTOP_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_MSTOP_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_MSTOP_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_mstop_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MSTOP_AW :: INT_EVENT0_ISET_MSTOP_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_mstop_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MSTOP_AW :: INT_EVENT0_ISET_MSTOP_SET) } } # [doc = "Arbitration Lost Interrupt\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_MARBLOST_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_MARBLOST_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_MARBLOST_SET = 1 , } impl From < INT_EVENT0_ISET_MARBLOST_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_MARBLOST_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_MARBLOST` writer - Arbitration Lost Interrupt"] pub type INT_EVENT0_ISET_MARBLOST_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_MARBLOST_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_MARBLOST_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_marblost_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MARBLOST_AW :: INT_EVENT0_ISET_MARBLOST_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_marblost_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MARBLOST_AW :: INT_EVENT0_ISET_MARBLOST_SET) } } # [doc = "DMA Done 1 on Event Channel 2\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_MDMA_DONE1_2_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_MDMA_DONE1_2_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_MDMA_DONE1_2_SET = 1 , } impl From < INT_EVENT0_ISET_MDMA_DONE1_2_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_MDMA_DONE1_2_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_MDMA_DONE1_2` writer - DMA Done 1 on Event Channel 2"] pub type INT_EVENT0_ISET_MDMA_DONE1_2_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_MDMA_DONE1_2_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_MDMA_DONE1_2_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_mdma_done1_2_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MDMA_DONE1_2_AW :: INT_EVENT0_ISET_MDMA_DONE1_2_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_mdma_done1_2_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MDMA_DONE1_2_AW :: INT_EVENT0_ISET_MDMA_DONE1_2_SET) } } # [doc = "DMA Done 1 on Event Channel 3\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_MDMA_DONE1_3_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_MDMA_DONE1_3_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_MDMA_DONE1_3_SET = 1 , } impl From < INT_EVENT0_ISET_MDMA_DONE1_3_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_MDMA_DONE1_3_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_MDMA_DONE1_3` writer - DMA Done 1 on Event Channel 3"] pub type INT_EVENT0_ISET_MDMA_DONE1_3_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_MDMA_DONE1_3_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_MDMA_DONE1_3_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_mdma_done1_3_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MDMA_DONE1_3_AW :: INT_EVENT0_ISET_MDMA_DONE1_3_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_mdma_done1_3_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MDMA_DONE1_3_AW :: INT_EVENT0_ISET_MDMA_DONE1_3_SET) } } # [doc = "Master RX Pec Error Interrupt\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_MPEC_RX_ERR_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_MPEC_RX_ERR_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_MPEC_RX_ERR_SET = 1 , } impl From < INT_EVENT0_ISET_MPEC_RX_ERR_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_MPEC_RX_ERR_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_MPEC_RX_ERR` writer - Master RX Pec Error Interrupt"] pub type INT_EVENT0_ISET_MPEC_RX_ERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_MPEC_RX_ERR_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_MPEC_RX_ERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_mpec_rx_err_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MPEC_RX_ERR_AW :: INT_EVENT0_ISET_MPEC_RX_ERR_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_mpec_rx_err_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MPEC_RX_ERR_AW :: INT_EVENT0_ISET_MPEC_RX_ERR_SET) } } # [doc = "Timeout A interrupt\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_TIMEOUTA_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_TIMEOUTA_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_TIMEOUTA_SET = 1 , } impl From < INT_EVENT0_ISET_TIMEOUTA_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_TIMEOUTA_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_TIMEOUTA` writer - Timeout A interrupt"] pub type INT_EVENT0_ISET_TIMEOUTA_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_TIMEOUTA_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_TIMEOUTA_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_timeouta_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_TIMEOUTA_AW :: INT_EVENT0_ISET_TIMEOUTA_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_timeouta_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_TIMEOUTA_AW :: INT_EVENT0_ISET_TIMEOUTA_SET) } } # [doc = "Timeout B Interrupt\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_TIMEOUTB_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_TIMEOUTB_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_TIMEOUTB_SET = 1 , } impl From < INT_EVENT0_ISET_TIMEOUTB_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_TIMEOUTB_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_TIMEOUTB` writer - Timeout B Interrupt"] pub type INT_EVENT0_ISET_TIMEOUTB_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_TIMEOUTB_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_TIMEOUTB_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_timeoutb_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_TIMEOUTB_AW :: INT_EVENT0_ISET_TIMEOUTB_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_timeoutb_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_TIMEOUTB_AW :: INT_EVENT0_ISET_TIMEOUTB_SET) } } # [doc = "Slave Receive Data Interrupt Signals that a byte has been received\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_SRXDONE_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_SRXDONE_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_SRXDONE_SET = 1 , } impl From < INT_EVENT0_ISET_SRXDONE_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_SRXDONE_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_SRXDONE` writer - Slave Receive Data Interrupt Signals that a byte has been received"] pub type INT_EVENT0_ISET_SRXDONE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_SRXDONE_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_SRXDONE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_srxdone_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_SRXDONE_AW :: INT_EVENT0_ISET_SRXDONE_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_srxdone_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_SRXDONE_AW :: INT_EVENT0_ISET_SRXDONE_SET) } } # [doc = "Slave Transmit Transaction completed Interrupt\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_STXDONE_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_STXDONE_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_STXDONE_SET = 1 , } impl From < INT_EVENT0_ISET_STXDONE_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_STXDONE_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_STXDONE` writer - Slave Transmit Transaction completed Interrupt"] pub type INT_EVENT0_ISET_STXDONE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_STXDONE_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_STXDONE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_stxdone_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_STXDONE_AW :: INT_EVENT0_ISET_STXDONE_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_stxdone_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_STXDONE_AW :: INT_EVENT0_ISET_STXDONE_SET) } } # [doc = "Slave Receive FIFO Trigger\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_SRXFIFOTRG_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_SRXFIFOTRG_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_SRXFIFOTRG_SET = 1 , } impl From < INT_EVENT0_ISET_SRXFIFOTRG_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_SRXFIFOTRG_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_SRXFIFOTRG` writer - Slave Receive FIFO Trigger"] pub type INT_EVENT0_ISET_SRXFIFOTRG_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_SRXFIFOTRG_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_SRXFIFOTRG_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_srxfifotrg_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_SRXFIFOTRG_AW :: INT_EVENT0_ISET_SRXFIFOTRG_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_srxfifotrg_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_SRXFIFOTRG_AW :: INT_EVENT0_ISET_SRXFIFOTRG_SET) } } # [doc = "Slave Transmit FIFO Trigger\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_STXFIFOTRG_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_STXFIFOTRG_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_STXFIFOTRG_SET = 1 , } impl From < INT_EVENT0_ISET_STXFIFOTRG_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_STXFIFOTRG_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_STXFIFOTRG` writer - Slave Transmit FIFO Trigger"] pub type INT_EVENT0_ISET_STXFIFOTRG_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_STXFIFOTRG_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_STXFIFOTRG_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_stxfifotrg_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_STXFIFOTRG_AW :: INT_EVENT0_ISET_STXFIFOTRG_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_stxfifotrg_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_STXFIFOTRG_AW :: INT_EVENT0_ISET_STXFIFOTRG_SET) } } # [doc = "RXFIFO full event. This interrupt is set if an RX FIFO is full.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_SRXFIFOFULL_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_SRXFIFOFULL_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_SRXFIFOFULL_SET = 1 , } impl From < INT_EVENT0_ISET_SRXFIFOFULL_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_SRXFIFOFULL_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_SRXFIFOFULL` writer - RXFIFO full event. This interrupt is set if an RX FIFO is full."] pub type INT_EVENT0_ISET_SRXFIFOFULL_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_SRXFIFOFULL_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_SRXFIFOFULL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_srxfifofull_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_SRXFIFOFULL_AW :: INT_EVENT0_ISET_SRXFIFOFULL_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_srxfifofull_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_SRXFIFOFULL_AW :: INT_EVENT0_ISET_SRXFIFOFULL_SET) } } # [doc = "Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_STXEMPTY_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_STXEMPTY_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_STXEMPTY_SET = 1 , } impl From < INT_EVENT0_ISET_STXEMPTY_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_STXEMPTY_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_STXEMPTY` writer - Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode."] pub type INT_EVENT0_ISET_STXEMPTY_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_STXEMPTY_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_STXEMPTY_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_stxempty_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_STXEMPTY_AW :: INT_EVENT0_ISET_STXEMPTY_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_stxempty_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_STXEMPTY_AW :: INT_EVENT0_ISET_STXEMPTY_SET) } } # [doc = "Start Condition Interrupt\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_SSTART_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_SSTART_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_SSTART_SET = 1 , } impl From < INT_EVENT0_ISET_SSTART_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_SSTART_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_SSTART` writer - Start Condition Interrupt"] pub type INT_EVENT0_ISET_SSTART_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_SSTART_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_SSTART_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_sstart_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_SSTART_AW :: INT_EVENT0_ISET_SSTART_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_sstart_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_SSTART_AW :: INT_EVENT0_ISET_SSTART_SET) } } # [doc = "Stop Condition Interrupt\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_SSTOP_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_SSTOP_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_SSTOP_SET = 1 , } impl From < INT_EVENT0_ISET_SSTOP_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_SSTOP_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_SSTOP` writer - Stop Condition Interrupt"] pub type INT_EVENT0_ISET_SSTOP_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_SSTOP_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_SSTOP_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_sstop_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_SSTOP_AW :: INT_EVENT0_ISET_SSTOP_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_sstop_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_SSTOP_AW :: INT_EVENT0_ISET_SSTOP_SET) } } # [doc = "General Call Interrupt\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_SGENCALL_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_SGENCALL_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_SGENCALL_SET = 1 , } impl From < INT_EVENT0_ISET_SGENCALL_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_SGENCALL_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_SGENCALL` writer - General Call Interrupt"] pub type INT_EVENT0_ISET_SGENCALL_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_SGENCALL_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_SGENCALL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_sgencall_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_SGENCALL_AW :: INT_EVENT0_ISET_SGENCALL_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_sgencall_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_SGENCALL_AW :: INT_EVENT0_ISET_SGENCALL_SET) } } # [doc = "DMA Done 1 on Event Channel 2\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_SDMA_DONE1_2_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_SDMA_DONE1_2_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_SDMA_DONE1_2_SET = 1 , } impl From < INT_EVENT0_ISET_SDMA_DONE1_2_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_SDMA_DONE1_2_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_SDMA_DONE1_2` writer - DMA Done 1 on Event Channel 2"] pub type INT_EVENT0_ISET_SDMA_DONE1_2_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_SDMA_DONE1_2_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_SDMA_DONE1_2_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_sdma_done1_2_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_SDMA_DONE1_2_AW :: INT_EVENT0_ISET_SDMA_DONE1_2_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_sdma_done1_2_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_SDMA_DONE1_2_AW :: INT_EVENT0_ISET_SDMA_DONE1_2_SET) } } # [doc = "DMA Done 1 on Event Channel 3\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_SDMA_DONE1_3_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_SDMA_DONE1_3_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_SDMA_DONE1_3_SET = 1 , } impl From < INT_EVENT0_ISET_SDMA_DONE1_3_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_SDMA_DONE1_3_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_SDMA_DONE1_3` writer - DMA Done 1 on Event Channel 3"] pub type INT_EVENT0_ISET_SDMA_DONE1_3_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_SDMA_DONE1_3_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_SDMA_DONE1_3_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_sdma_done1_3_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_SDMA_DONE1_3_AW :: INT_EVENT0_ISET_SDMA_DONE1_3_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_sdma_done1_3_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_SDMA_DONE1_3_AW :: INT_EVENT0_ISET_SDMA_DONE1_3_SET) } } # [doc = "Slave RX Pec Error Interrupt\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_SPEC_RX_ERR_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_SPEC_RX_ERR_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_SPEC_RX_ERR_SET = 1 , } impl From < INT_EVENT0_ISET_SPEC_RX_ERR_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_SPEC_RX_ERR_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_SPEC_RX_ERR` writer - Slave RX Pec Error Interrupt"] pub type INT_EVENT0_ISET_SPEC_RX_ERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_SPEC_RX_ERR_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_SPEC_RX_ERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_spec_rx_err_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_SPEC_RX_ERR_AW :: INT_EVENT0_ISET_SPEC_RX_ERR_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_spec_rx_err_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_SPEC_RX_ERR_AW :: INT_EVENT0_ISET_SPEC_RX_ERR_SET) } } # [doc = "Slave TX FIFO underflow\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_STX_UNFL_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_STX_UNFL_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_STX_UNFL_SET = 1 , } impl From < INT_EVENT0_ISET_STX_UNFL_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_STX_UNFL_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_STX_UNFL` writer - Slave TX FIFO underflow"] pub type INT_EVENT0_ISET_STX_UNFL_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_STX_UNFL_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_STX_UNFL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_stx_unfl_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_STX_UNFL_AW :: INT_EVENT0_ISET_STX_UNFL_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_stx_unfl_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_STX_UNFL_AW :: INT_EVENT0_ISET_STX_UNFL_SET) } } # [doc = "Slave RX FIFO overflow\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_SRX_OVFL_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_SRX_OVFL_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_SRX_OVFL_SET = 1 , } impl From < INT_EVENT0_ISET_SRX_OVFL_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_SRX_OVFL_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_SRX_OVFL` writer - Slave RX FIFO overflow"] pub type INT_EVENT0_ISET_SRX_OVFL_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_SRX_OVFL_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_SRX_OVFL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_srx_ovfl_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_SRX_OVFL_AW :: INT_EVENT0_ISET_SRX_OVFL_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_srx_ovfl_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_SRX_OVFL_AW :: INT_EVENT0_ISET_SRX_OVFL_SET) } } # [doc = "Slave Arbitration Lost\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_SARBLOST_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_SARBLOST_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_SARBLOST_SET = 1 , } impl From < INT_EVENT0_ISET_SARBLOST_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_SARBLOST_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_SARBLOST` writer - Slave Arbitration Lost"] pub type INT_EVENT0_ISET_SARBLOST_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_SARBLOST_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_SARBLOST_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_sarblost_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_SARBLOST_AW :: INT_EVENT0_ISET_SARBLOST_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_sarblost_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_SARBLOST_AW :: INT_EVENT0_ISET_SARBLOST_SET) } } # [doc = "Interrupt overflow\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_INTR_OVFL_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_INTR_OVFL_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_INTR_OVFL_SET = 1 , } impl From < INT_EVENT0_ISET_INTR_OVFL_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_INTR_OVFL_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_INTR_OVFL` writer - Interrupt overflow"] pub type INT_EVENT0_ISET_INTR_OVFL_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_INTR_OVFL_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_INTR_OVFL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_intr_ovfl_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_INTR_OVFL_AW :: INT_EVENT0_ISET_INTR_OVFL_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_intr_ovfl_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_INTR_OVFL_AW :: INT_EVENT0_ISET_INTR_OVFL_SET) } } impl W { # [doc = "Bit 0 - Master Receive Data Interrupt Signals that a byte has been received"] # [inline (always)] # [must_use] pub fn int_event0_iset_mrxdone (& mut self) -> INT_EVENT0_ISET_MRXDONE_W < INT_EVENT0_ISET_SPEC , 0 > { INT_EVENT0_ISET_MRXDONE_W :: new (self) } # [doc = "Bit 1 - Master Transmit Transaction completed Interrupt"] # [inline (always)] # [must_use] pub fn int_event0_iset_mtxdone (& mut self) -> INT_EVENT0_ISET_MTXDONE_W < INT_EVENT0_ISET_SPEC , 1 > { INT_EVENT0_ISET_MTXDONE_W :: new (self) } # [doc = "Bit 2 - Master Receive FIFO Trigger Trigger when RX FIFO contains &gt;= defined bytes"] # [inline (always)] # [must_use] pub fn int_event0_iset_mrxfifotrg (& mut self) -> INT_EVENT0_ISET_MRXFIFOTRG_W < INT_EVENT0_ISET_SPEC , 2 > { INT_EVENT0_ISET_MRXFIFOTRG_W :: new (self) } # [doc = "Bit 3 - Master Transmit FIFO Trigger Trigger when Transmit FIFO contains &lt;= defined bytes"] # [inline (always)] # [must_use] pub fn int_event0_iset_mtxfifotrg (& mut self) -> INT_EVENT0_ISET_MTXFIFOTRG_W < INT_EVENT0_ISET_SPEC , 3 > { INT_EVENT0_ISET_MTXFIFOTRG_W :: new (self) } # [doc = "Bit 4 - RXFIFO full event."] # [inline (always)] # [must_use] pub fn int_event0_iset_mrxfifofull (& mut self) -> INT_EVENT0_ISET_MRXFIFOFULL_W < INT_EVENT0_ISET_SPEC , 4 > { INT_EVENT0_ISET_MRXFIFOFULL_W :: new (self) } # [doc = "Bit 5 - Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode."] # [inline (always)] # [must_use] pub fn int_event0_iset_mtxempty (& mut self) -> INT_EVENT0_ISET_MTXEMPTY_W <'_, INT_EVENT0_ISET_SPEC , 5 > { INT_EVENT0_ISET_MTXEMPTY_W :: new (self) } # [doc = "Bit 7 - Address/Data NACK Interrupt"] # [inline (always)] # [must_use] pub fn int_event0_iset_mnack (& mut self) -> INT_EVENT0_ISET_MNACK_W < INT_EVENT0_ISET_SPEC , 7 > { INT_EVENT0_ISET_MNACK_W :: new (self) } # [doc = "Bit 8 - START Detection Interrupt"] # [inline (always)] # [must_use] pub fn int_event0_iset_mstart (& mut self) -> INT_EVENT0_ISET_MSTART_W < INT_EVENT0_ISET_SPEC , 8 > { INT_EVENT0_ISET_MSTART_W :: new (self) } # [doc = "Bit 9 - STOP Detection Interrupt"] # [inline (always)] # [must_use] pub fn int_event0_iset_mstop (& mut self) -> INT_EVENT0_ISET_MSTOP_W < INT_EVENT0_ISET_SPEC , 9 > { INT_EVENT0_ISET_MSTOP_W :: new (self) } # [doc = "Bit 10 - Arbitration Lost Interrupt"] # [inline (always)] # [must_use] pub fn int_event0_iset_marblost (& mut self) -> INT_EVENT0_ISET_MARBLOST_W < INT_EVENT0_ISET_SPEC , 10 > { INT_EVENT0_ISET_MARBLOST_W :: new (self) } # [doc = "Bit 11 - DMA Done 1 on Event Channel 2"] # [inline (always)] # [must_use] pub fn int_event0_iset_mdma_done1_2 (& mut self) -> INT_EVENT0_ISET_MDMA_DONE1_2_W < INT_EVENT0_ISET_SPEC , 11 > { INT_EVENT0_ISET_MDMA_DONE1_2_W :: new (self) } # [doc = "Bit 12 - DMA Done 1 on Event Channel 3"] # [inline (always)] # [must_use] pub fn int_event0_iset_mdma_done1_3 (& mut self) -> INT_EVENT0_ISET_MDMA_DONE1_3_W < INT_EVENT0_ISET_SPEC , 12 > { INT_EVENT0_ISET_MDMA_DONE1_3_W :: new (self) } # [doc = "Bit 13 - Master RX Pec Error Interrupt"] # [inline (always)] # [must_use] pub fn int_event0_iset_mpec_rx_err (& mut self) -> INT_EVENT0_ISET_MPEC_RX_ERR_W < INT_EVENT0_ISET_SPEC , 13 > { INT_EVENT0_ISET_MPEC_RX_ERR_W :: new (self) } # [doc = "Bit 14 - Timeout A interrupt"] # [inline (always)] # [must_use] pub fn int_event0_iset_timeouta (& mut self) -> INT_EVENT0_ISET_TIMEOUTA_W < INT_EVENT0_ISET_SPEC , 14 > { INT_EVENT0_ISET_TIMEOUTA_W :: new (self) } # [doc = "Bit 15 - Timeout B Interrupt"] # [inline (always)] # [must_use] pub fn int_event0_iset_timeoutb (& mut self) -> INT_EVENT0_ISET_TIMEOUTB_W < INT_EVENT0_ISET_SPEC , 15 > { INT_EVENT0_ISET_TIMEOUTB_W :: new (self) } # [doc = "Bit 16 - Slave Receive Data Interrupt Signals that a byte has been received"] # [inline (always)] # [must_use] pub fn int_event0_iset_srxdone (& mut self) -> INT_EVENT0_ISET_SRXDONE_W < INT_EVENT0_ISET_SPEC , 16 > { INT_EVENT0_ISET_SRXDONE_W :: new (self) } # [doc = "Bit 17 - Slave Transmit Transaction completed Interrupt"] # [inline (always)] # [must_use] pub fn int_event0_iset_stxdone (& mut self) -> INT_EVENT0_ISET_STXDONE_W < INT_EVENT0_ISET_SPEC , 17 > { INT_EVENT0_ISET_STXDONE_W :: new (self) } # [doc = "Bit 18 - Slave Receive FIFO Trigger"] # [inline (always)] # [must_use] pub fn int_event0_iset_srxfifotrg (& mut self) -> INT_EVENT0_ISET_SRXFIFOTRG_W < INT_EVENT0_ISET_SPEC , 18 > { INT_EVENT0_ISET_SRXFIFOTRG_W :: new (self) } # [doc = "Bit 19 - Slave Transmit FIFO Trigger"] # [inline (always)] # [must_use] pub fn int_event0_iset_stxfifotrg (& mut self) -> INT_EVENT0_ISET_STXFIFOTRG_W < INT_EVENT0_ISET_SPEC , 19 > { INT_EVENT0_ISET_STXFIFOTRG_W :: new (self) } # [doc = "Bit 20 - RXFIFO full event. This interrupt is set if an RX FIFO is full."] # [inline (always)] # [must_use] pub fn int_event0_iset_srxfifofull (& mut self) -> INT_EVENT0_ISET_SRXFIFOFULL_W < INT_EVENT0_ISET_SPEC , 20 > { INT_EVENT0_ISET_SRXFIFOFULL_W :: new (self) } # [doc = "Bit 21 - Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode."] # [inline (always)] # [must_use] pub fn int_event0_iset_stxempty (& mut self) -> INT_EVENT0_ISET_STXEMPTY_W < INT_EVENT0_ISET_SPEC , 21 > { INT_EVENT0_ISET_STXEMPTY_W :: new (self) } # [doc = "Bit 22 - Start Condition Interrupt"] # [inline (always)] # [must_use] pub fn int_event0_iset_sstart (& mut self) -> INT_EVENT0_ISET_SSTART_W < INT_EVENT0_ISET_SPEC , 22 > { INT_EVENT0_ISET_SSTART_W :: new (self) } # [doc = "Bit 23 - Stop Condition Interrupt"] # [inline (always)] # [must_use] pub fn int_event0_iset_sstop (& mut self) -> INT_EVENT0_ISET_SSTOP_W < INT_EVENT0_ISET_SPEC , 23 > { INT_EVENT0_ISET_SSTOP_W :: new (self) } # [doc = "Bit 24 - General Call Interrupt"] # [inline (always)] # [must_use] pub fn int_event0_iset_sgencall (& mut self) -> INT_EVENT0_ISET_SGENCALL_W < INT_EVENT0_ISET_SPEC , 24 > { INT_EVENT0_ISET_SGENCALL_W :: new (self) } # [doc = "Bit 25 - DMA Done 1 on Event Channel 2"] # [inline (always)] # [must_use] pub fn int_event0_iset_sdma_done1_2 (& mut self) -> INT_EVENT0_ISET_SDMA_DONE1_2_W < INT_EVENT0_ISET_SPEC , 25 > { INT_EVENT0_ISET_SDMA_DONE1_2_W :: new (self) } # [doc = "Bit 26 - DMA Done 1 on Event Channel 3"] # [inline (always)] # [must_use] pub fn int_event0_iset_sdma_done1_3 (& mut self) -> INT_EVENT0_ISET_SDMA_DONE1_3_W < INT_EVENT0_ISET_SPEC , 26 > { INT_EVENT0_ISET_SDMA_DONE1_3_W :: new (self) } # [doc = "Bit 27 - Slave RX Pec Error Interrupt"] # [inline (always)] # [must_use] pub fn int_event0_iset_spec_rx_err (& mut self) -> INT_EVENT0_ISET_SPEC_RX_ERR_W < INT_EVENT0_ISET_SPEC , 27 > { INT_EVENT0_ISET_SPEC_RX_ERR_W :: new (self) } # [doc = "Bit 28 - Slave TX FIFO underflow"] # [inline (always)] # [must_use] pub fn int_event0_iset_stx_unfl (& mut self) -> INT_EVENT0_ISET_STX_UNFL_W < INT_EVENT0_ISET_SPEC , 28 > { INT_EVENT0_ISET_STX_UNFL_W :: new (self) } # [doc = "Bit 29 - Slave RX FIFO overflow"] # [inline (always)] # [must_use] pub fn int_event0_iset_srx_ovfl (& mut self) -> INT_EVENT0_ISET_SRX_OVFL_W < INT_EVENT0_ISET_SPEC , 29 > { INT_EVENT0_ISET_SRX_OVFL_W :: new (self) } # [doc = "Bit 30 - Slave Arbitration Lost"] # [inline (always)] # [must_use] pub fn int_event0_iset_sarblost (& mut self) -> INT_EVENT0_ISET_SARBLOST_W < INT_EVENT0_ISET_SPEC , 30 > { INT_EVENT0_ISET_SARBLOST_W :: new (self) } # [doc = "Bit 31 - Interrupt overflow"] # [inline (always)] # [must_use] pub fn int_event0_iset_intr_ovfl (& mut self) -> INT_EVENT0_ISET_INTR_OVFL_W < INT_EVENT0_ISET_SPEC , 31 > { INT_EVENT0_ISET_INTR_OVFL_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Interrupt set\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_event0_iset::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct INT_EVENT0_ISET_SPEC ; impl crate :: RegisterSpec for INT_EVENT0_ISET_SPEC { type Ux = u32 ; } # [doc = "`write(|w| ..)` method takes [`int_event0_iset::W`](W) writer structure"] impl crate :: Writable for INT_EVENT0_ISET_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets INT_EVENT0_ISET to value 0"] impl crate :: Resettable for INT_EVENT0_ISET_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/i2c0/sctr.rs:1:26415 [INFO] [stdout] | [INFO] [stdout] 1 | ...b fn sctr_en_alrespadr (& mut self) -> SCTR_EN_ALRESPADR_W < SCTR_SPEC , 8 > { SCTR_EN_ALRESPADR_W :: new (self) } # [doc = "Bit 9 - E... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `SCTR` reader"] pub type R = crate :: R < SCTR_SPEC > ; # [doc = "Register `SCTR` writer"] pub type W = crate :: W < SCTR_SPEC > ; # [doc = "Field `SCTR_ACTIVE` reader - Device Active. Setting this bit enables the slave functionality."] pub type SCTR_ACTIVE_R = crate :: BitReader < SCTR_ACTIVE_A > ; # [doc = "Device Active. Setting this bit enables the slave functionality.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum SCTR_ACTIVE_A { # [doc = "0: DISABLE"] SCTR_ACTIVE_DISABLE = 0 , # [doc = "1: ENABLE"] SCTR_ACTIVE_ENABLE = 1 , } impl From < SCTR_ACTIVE_A > for bool { # [inline (always)] fn from (variant : SCTR_ACTIVE_A) -> Self { variant as u8 != 0 } } impl SCTR_ACTIVE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> SCTR_ACTIVE_A { match self . bits { false => SCTR_ACTIVE_A :: SCTR_ACTIVE_DISABLE , true => SCTR_ACTIVE_A :: SCTR_ACTIVE_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_sctr_active_disable (& self) -> bool { * self == SCTR_ACTIVE_A :: SCTR_ACTIVE_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_sctr_active_enable (& self) -> bool { * self == SCTR_ACTIVE_A :: SCTR_ACTIVE_ENABLE } } # [doc = "Field `SCTR_ACTIVE` writer - Device Active. Setting this bit enables the slave functionality."] pub type SCTR_ACTIVE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , SCTR_ACTIVE_A > ; impl < 'a , REG , const O : u8 > SCTR_ACTIVE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn sctr_active_disable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_ACTIVE_A :: SCTR_ACTIVE_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn sctr_active_enable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_ACTIVE_A :: SCTR_ACTIVE_ENABLE) } } # [doc = "Field `SCTR_GENCALL` reader - General call response enable. This bit is only available in UCBxI2COA0. Modify only when UCSWRST = 1. 0b = Do not respond to a general call 1b = Respond to a general call"] pub type SCTR_GENCALL_R = crate :: BitReader < SCTR_GENCALL_A > ; # [doc = "General call response enable. This bit is only available in UCBxI2COA0. Modify only when UCSWRST = 1. 0b = Do not respond to a general call 1b = Respond to a general call\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum SCTR_GENCALL_A { # [doc = "0: DISABLE"] SCTR_GENCALL_DISABLE = 0 , # [doc = "1: ENABLE"] SCTR_GENCALL_ENABLE = 1 , } impl From < SCTR_GENCALL_A > for bool { # [inline (always)] fn from (variant : SCTR_GENCALL_A) -> Self { variant as u8 != 0 } } impl SCTR_GENCALL_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> SCTR_GENCALL_A { match self . bits { false => SCTR_GENCALL_A :: SCTR_GENCALL_DISABLE , true => SCTR_GENCALL_A :: SCTR_GENCALL_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_sctr_gencall_disable (& self) -> bool { * self == SCTR_GENCALL_A :: SCTR_GENCALL_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_sctr_gencall_enable (& self) -> bool { * self == SCTR_GENCALL_A :: SCTR_GENCALL_ENABLE } } # [doc = "Field `SCTR_GENCALL` writer - General call response enable. This bit is only available in UCBxI2COA0. Modify only when UCSWRST = 1. 0b = Do not respond to a general call 1b = Respond to a general call"] pub type SCTR_GENCALL_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , SCTR_GENCALL_A > ; impl < 'a , REG , const O : u8 > SCTR_GENCALL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn sctr_gencall_disable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_GENCALL_A :: SCTR_GENCALL_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn sctr_gencall_enable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_GENCALL_A :: SCTR_GENCALL_ENABLE) } } # [doc = "Field `SCTR_SCLKSTRETCH` reader - Slave Clock Stretch Enable"] pub type SCTR_SCLKSTRETCH_R = crate :: BitReader < SCTR_SCLKSTRETCH_A > ; # [doc = "Slave Clock Stretch Enable\n\nValue on reset: 1"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum SCTR_SCLKSTRETCH_A { # [doc = "0: DISABLE"] SCTR_SCLKSTRETCH_DISABLE = 0 , # [doc = "1: ENABLE"] SCTR_SCLKSTRETCH_ENABLE = 1 , } impl From < SCTR_SCLKSTRETCH_A > for bool { # [inline (always)] fn from (variant : SCTR_SCLKSTRETCH_A) -> Self { variant as u8 != 0 } } impl SCTR_SCLKSTRETCH_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> SCTR_SCLKSTRETCH_A { match self . bits { false => SCTR_SCLKSTRETCH_A :: SCTR_SCLKSTRETCH_DISABLE , true => SCTR_SCLKSTRETCH_A :: SCTR_SCLKSTRETCH_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_sctr_sclkstretch_disable (& self) -> bool { * self == SCTR_SCLKSTRETCH_A :: SCTR_SCLKSTRETCH_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_sctr_sclkstretch_enable (& self) -> bool { * self == SCTR_SCLKSTRETCH_A :: SCTR_SCLKSTRETCH_ENABLE } } # [doc = "Field `SCTR_SCLKSTRETCH` writer - Slave Clock Stretch Enable"] pub type SCTR_SCLKSTRETCH_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , SCTR_SCLKSTRETCH_A > ; impl < 'a , REG , const O : u8 > SCTR_SCLKSTRETCH_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn sctr_sclkstretch_disable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_SCLKSTRETCH_A :: SCTR_SCLKSTRETCH_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn sctr_sclkstretch_enable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_SCLKSTRETCH_A :: SCTR_SCLKSTRETCH_ENABLE) } } # [doc = "Field `SCTR_TXEMPTY_ON_TREQ` reader - Tx Empty Interrupt on TREQ"] pub type SCTR_TXEMPTY_ON_TREQ_R = crate :: BitReader < SCTR_TXEMPTY_ON_TREQ_A > ; # [doc = "Tx Empty Interrupt on TREQ\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum SCTR_TXEMPTY_ON_TREQ_A { # [doc = "0: DISABLE"] SCTR_TXEMPTY_ON_TREQ_DISABLE = 0 , # [doc = "1: ENABLE"] SCTR_TXEMPTY_ON_TREQ_ENABLE = 1 , } impl From < SCTR_TXEMPTY_ON_TREQ_A > for bool { # [inline (always)] fn from (variant : SCTR_TXEMPTY_ON_TREQ_A) -> Self { variant as u8 != 0 } } impl SCTR_TXEMPTY_ON_TREQ_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> SCTR_TXEMPTY_ON_TREQ_A { match self . bits { false => SCTR_TXEMPTY_ON_TREQ_A :: SCTR_TXEMPTY_ON_TREQ_DISABLE , true => SCTR_TXEMPTY_ON_TREQ_A :: SCTR_TXEMPTY_ON_TREQ_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_sctr_txempty_on_treq_disable (& self) -> bool { * self == SCTR_TXEMPTY_ON_TREQ_A :: SCTR_TXEMPTY_ON_TREQ_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_sctr_txempty_on_treq_enable (& self) -> bool { * self == SCTR_TXEMPTY_ON_TREQ_A :: SCTR_TXEMPTY_ON_TREQ_ENABLE } } # [doc = "Field `SCTR_TXEMPTY_ON_TREQ` writer - Tx Empty Interrupt on TREQ"] pub type SCTR_TXEMPTY_ON_TREQ_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , SCTR_TXEMPTY_ON_TREQ_A > ; impl < 'a , REG , const O : u8 > SCTR_TXEMPTY_ON_TREQ_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn sctr_txempty_on_treq_disable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_TXEMPTY_ON_TREQ_A :: SCTR_TXEMPTY_ON_TREQ_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn sctr_txempty_on_treq_enable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_TXEMPTY_ON_TREQ_A :: SCTR_TXEMPTY_ON_TREQ_ENABLE) } } # [doc = "Field `SCTR_TXTRIG_TXMODE` reader - Tx Trigger when slave FSM is in Tx Mode"] pub type SCTR_TXTRIG_TXMODE_R = crate :: BitReader < SCTR_TXTRIG_TXMODE_A > ; # [doc = "Tx Trigger when slave FSM is in Tx Mode\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum SCTR_TXTRIG_TXMODE_A { # [doc = "0: DISABLE"] SCTR_TXTRIG_TXMODE_DISABLE = 0 , # [doc = "1: ENABLE"] SCTR_TXTRIG_TXMODE_ENABLE = 1 , } impl From < SCTR_TXTRIG_TXMODE_A > for bool { # [inline (always)] fn from (variant : SCTR_TXTRIG_TXMODE_A) -> Self { variant as u8 != 0 } } impl SCTR_TXTRIG_TXMODE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> SCTR_TXTRIG_TXMODE_A { match self . bits { false => SCTR_TXTRIG_TXMODE_A :: SCTR_TXTRIG_TXMODE_DISABLE , true => SCTR_TXTRIG_TXMODE_A :: SCTR_TXTRIG_TXMODE_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_sctr_txtrig_txmode_disable (& self) -> bool { * self == SCTR_TXTRIG_TXMODE_A :: SCTR_TXTRIG_TXMODE_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_sctr_txtrig_txmode_enable (& self) -> bool { * self == SCTR_TXTRIG_TXMODE_A :: SCTR_TXTRIG_TXMODE_ENABLE } } # [doc = "Field `SCTR_TXTRIG_TXMODE` writer - Tx Trigger when slave FSM is in Tx Mode"] pub type SCTR_TXTRIG_TXMODE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , SCTR_TXTRIG_TXMODE_A > ; impl < 'a , REG , const O : u8 > SCTR_TXTRIG_TXMODE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn sctr_txtrig_txmode_disable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_TXTRIG_TXMODE_A :: SCTR_TXTRIG_TXMODE_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn sctr_txtrig_txmode_enable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_TXTRIG_TXMODE_A :: SCTR_TXTRIG_TXMODE_ENABLE) } } # [doc = "Field `SCTR_TXWAIT_STALE_TXFIFO` reader - Tx transfer waits when stale data in Tx FIFO. This prevents stale bytes left in the TX FIFO from automatically being sent on the next I2C packet. Note: this should be used with TXEMPTY_ON_TREQ set to prevent the Slave State Machine from waiting for TX FIFO data without an interrupt notification when the FIFO data is stale."] pub type SCTR_TXWAIT_STALE_TXFIFO_R = crate :: BitReader < SCTR_TXWAIT_STALE_TXFIFO_A > ; # [doc = "Tx transfer waits when stale data in Tx FIFO. This prevents stale bytes left in the TX FIFO from automatically being sent on the next I2C packet. Note: this should be used with TXEMPTY_ON_TREQ set to prevent the Slave State Machine from waiting for TX FIFO data without an interrupt notification when the FIFO data is stale.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum SCTR_TXWAIT_STALE_TXFIFO_A { # [doc = "0: DISABLE"] SCTR_TXWAIT_STALE_TXFIFO_DISABLE = 0 , # [doc = "1: ENABLE"] SCTR_TXWAIT_STALE_TXFIFO_ENABLE = 1 , } impl From < SCTR_TXWAIT_STALE_TXFIFO_A > for bool { # [inline (always)] fn from (variant : SCTR_TXWAIT_STALE_TXFIFO_A) -> Self { variant as u8 != 0 } } impl SCTR_TXWAIT_STALE_TXFIFO_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> SCTR_TXWAIT_STALE_TXFIFO_A { match self . bits { false => SCTR_TXWAIT_STALE_TXFIFO_A :: SCTR_TXWAIT_STALE_TXFIFO_DISABLE , true => SCTR_TXWAIT_STALE_TXFIFO_A :: SCTR_TXWAIT_STALE_TXFIFO_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_sctr_txwait_stale_txfifo_disable (& self) -> bool { * self == SCTR_TXWAIT_STALE_TXFIFO_A :: SCTR_TXWAIT_STALE_TXFIFO_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_sctr_txwait_stale_txfifo_enable (& self) -> bool { * self == SCTR_TXWAIT_STALE_TXFIFO_A :: SCTR_TXWAIT_STALE_TXFIFO_ENABLE } } # [doc = "Field `SCTR_TXWAIT_STALE_TXFIFO` writer - Tx transfer waits when stale data in Tx FIFO. This prevents stale bytes left in the TX FIFO from automatically being sent on the next I2C packet. Note: this should be used with TXEMPTY_ON_TREQ set to prevent the Slave State Machine from waiting for TX FIFO data without an interrupt notification when the FIFO data is stale."] pub type SCTR_TXWAIT_STALE_TXFIFO_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , SCTR_TXWAIT_STALE_TXFIFO_A > ; impl < 'a , REG , const O : u8 > SCTR_TXWAIT_STALE_TXFIFO_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn sctr_txwait_stale_txfifo_disable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_TXWAIT_STALE_TXFIFO_A :: SCTR_TXWAIT_STALE_TXFIFO_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn sctr_txwait_stale_txfifo_enable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_TXWAIT_STALE_TXFIFO_A :: SCTR_TXWAIT_STALE_TXFIFO_ENABLE) } } # [doc = "Field `SCTR_RXFULL_ON_RREQ` reader - Rx full interrupt generated on RREQ condition as indicated in SSR"] pub type SCTR_RXFULL_ON_RREQ_R = crate :: BitReader < SCTR_RXFULL_ON_RREQ_A > ; # [doc = "Rx full interrupt generated on RREQ condition as indicated in SSR\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum SCTR_RXFULL_ON_RREQ_A { # [doc = "0: DISABLE"] SCTR_RXFULL_ON_RREQ_DISABLE = 0 , # [doc = "1: ENABLE"] SCTR_RXFULL_ON_RREQ_ENABLE = 1 , } impl From < SCTR_RXFULL_ON_RREQ_A > for bool { # [inline (always)] fn from (variant : SCTR_RXFULL_ON_RREQ_A) -> Self { variant as u8 != 0 } } impl SCTR_RXFULL_ON_RREQ_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> SCTR_RXFULL_ON_RREQ_A { match self . bits { false => SCTR_RXFULL_ON_RREQ_A :: SCTR_RXFULL_ON_RREQ_DISABLE , true => SCTR_RXFULL_ON_RREQ_A :: SCTR_RXFULL_ON_RREQ_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_sctr_rxfull_on_rreq_disable (& self) -> bool { * self == SCTR_RXFULL_ON_RREQ_A :: SCTR_RXFULL_ON_RREQ_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_sctr_rxfull_on_rreq_enable (& self) -> bool { * self == SCTR_RXFULL_ON_RREQ_A :: SCTR_RXFULL_ON_RREQ_ENABLE } } # [doc = "Field `SCTR_RXFULL_ON_RREQ` writer - Rx full interrupt generated on RREQ condition as indicated in SSR"] pub type SCTR_RXFULL_ON_RREQ_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , SCTR_RXFULL_ON_RREQ_A > ; impl < 'a , REG , const O : u8 > SCTR_RXFULL_ON_RREQ_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn sctr_rxfull_on_rreq_disable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_RXFULL_ON_RREQ_A :: SCTR_RXFULL_ON_RREQ_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn sctr_rxfull_on_rreq_enable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_RXFULL_ON_RREQ_A :: SCTR_RXFULL_ON_RREQ_ENABLE) } } # [doc = "Field `SCTR_EN_DEFHOSTADR` reader - Enable Default Host Address"] pub type SCTR_EN_DEFHOSTADR_R = crate :: BitReader < SCTR_EN_DEFHOSTADR_A > ; # [doc = "Enable Default Host Address\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum SCTR_EN_DEFHOSTADR_A { # [doc = "0: DISABLE"] SCTR_EN_DEFHOSTADR_DISABLE = 0 , # [doc = "1: ENABLE"] SCTR_EN_DEFHOSTADR_ENABLE = 1 , } impl From < SCTR_EN_DEFHOSTADR_A > for bool { # [inline (always)] fn from (variant : SCTR_EN_DEFHOSTADR_A) -> Self { variant as u8 != 0 } } impl SCTR_EN_DEFHOSTADR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> SCTR_EN_DEFHOSTADR_A { match self . bits { false => SCTR_EN_DEFHOSTADR_A :: SCTR_EN_DEFHOSTADR_DISABLE , true => SCTR_EN_DEFHOSTADR_A :: SCTR_EN_DEFHOSTADR_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_sctr_en_defhostadr_disable (& self) -> bool { * self == SCTR_EN_DEFHOSTADR_A :: SCTR_EN_DEFHOSTADR_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_sctr_en_defhostadr_enable (& self) -> bool { * self == SCTR_EN_DEFHOSTADR_A :: SCTR_EN_DEFHOSTADR_ENABLE } } # [doc = "Field `SCTR_EN_DEFHOSTADR` writer - Enable Default Host Address"] pub type SCTR_EN_DEFHOSTADR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , SCTR_EN_DEFHOSTADR_A > ; impl < 'a , REG , const O : u8 > SCTR_EN_DEFHOSTADR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn sctr_en_defhostadr_disable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_EN_DEFHOSTADR_A :: SCTR_EN_DEFHOSTADR_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn sctr_en_defhostadr_enable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_EN_DEFHOSTADR_A :: SCTR_EN_DEFHOSTADR_ENABLE) } } # [doc = "Field `SCTR_EN_ALRESPADR` reader - Enable Alert Response Address"] pub type SCTR_EN_ALRESPADR_R = crate :: BitReader < SCTR_EN_ALRESPADR_A > ; # [doc = "Enable Alert Response Address\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum SCTR_EN_ALRESPADR_A { # [doc = "0: DISABLE"] SCTR_EN_ALRESPADR_DISABLE = 0 , # [doc = "1: ENABLE"] SCTR_EN_ALRESPADR_ENABLE = 1 , } impl From < SCTR_EN_ALRESPADR_A > for bool { # [inline (always)] fn from (variant : SCTR_EN_ALRESPADR_A) -> Self { variant as u8 != 0 } } impl SCTR_EN_ALRESPADR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> SCTR_EN_ALRESPADR_A { match self . bits { false => SCTR_EN_ALRESPADR_A :: SCTR_EN_ALRESPADR_DISABLE , true => SCTR_EN_ALRESPADR_A :: SCTR_EN_ALRESPADR_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_sctr_en_alrespadr_disable (& self) -> bool { * self == SCTR_EN_ALRESPADR_A :: SCTR_EN_ALRESPADR_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_sctr_en_alrespadr_enable (& self) -> bool { * self == SCTR_EN_ALRESPADR_A :: SCTR_EN_ALRESPADR_ENABLE } } # [doc = "Field `SCTR_EN_ALRESPADR` writer - Enable Alert Response Address"] pub type SCTR_EN_ALRESPADR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , SCTR_EN_ALRESPADR_A > ; impl < 'a , REG , const O : u8 > SCTR_EN_ALRESPADR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn sctr_en_alrespadr_disable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_EN_ALRESPADR_A :: SCTR_EN_ALRESPADR_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn sctr_en_alrespadr_enable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_EN_ALRESPADR_A :: SCTR_EN_ALRESPADR_ENABLE) } } # [doc = "Field `SCTR_EN_DEFDEVADR` reader - Enable Deault device address"] pub type SCTR_EN_DEFDEVADR_R = crate :: BitReader < SCTR_EN_DEFDEVADR_A > ; # [doc = "Enable Deault device address\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum SCTR_EN_DEFDEVADR_A { # [doc = "0: DISABLE"] SCTR_EN_DEFDEVADR_DISABLE = 0 , # [doc = "1: ENABLE"] SCTR_EN_DEFDEVADR_ENABLE = 1 , } impl From < SCTR_EN_DEFDEVADR_A > for bool { # [inline (always)] fn from (variant : SCTR_EN_DEFDEVADR_A) -> Self { variant as u8 != 0 } } impl SCTR_EN_DEFDEVADR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> SCTR_EN_DEFDEVADR_A { match self . bits { false => SCTR_EN_DEFDEVADR_A :: SCTR_EN_DEFDEVADR_DISABLE , true => SCTR_EN_DEFDEVADR_A :: SCTR_EN_DEFDEVADR_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_sctr_en_defdevadr_disable (& self) -> bool { * self == SCTR_EN_DEFDEVADR_A :: SCTR_EN_DEFDEVADR_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_sctr_en_defdevadr_enable (& self) -> bool { * self == SCTR_EN_DEFDEVADR_A :: SCTR_EN_DEFDEVADR_ENABLE } } # [doc = "Field `SCTR_EN_DEFDEVADR` writer - Enable Deault device address"] pub type SCTR_EN_DEFDEVADR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , SCTR_EN_DEFDEVADR_A > ; impl < 'a , REG , const O : u8 > SCTR_EN_DEFDEVADR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn sctr_en_defdevadr_disable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_EN_DEFDEVADR_A :: SCTR_EN_DEFDEVADR_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn sctr_en_defdevadr_enable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_EN_DEFDEVADR_A :: SCTR_EN_DEFDEVADR_ENABLE) } } # [doc = "Field `SCTR_SWUEN` reader - Slave Wakeup Enable"] pub type SCTR_SWUEN_R = crate :: BitReader < SCTR_SWUEN_A > ; # [doc = "Slave Wakeup Enable\n\nValue on reset: 1"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum SCTR_SWUEN_A { # [doc = "0: DISABLE"] SCTR_SWUEN_DISABLE = 0 , # [doc = "1: ENABLE"] SCTR_SWUEN_ENABLE = 1 , } impl From < SCTR_SWUEN_A > for bool { # [inline (always)] fn from (variant : SCTR_SWUEN_A) -> Self { variant as u8 != 0 } } impl SCTR_SWUEN_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> SCTR_SWUEN_A { match self . bits { false => SCTR_SWUEN_A :: SCTR_SWUEN_DISABLE , true => SCTR_SWUEN_A :: SCTR_SWUEN_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_sctr_swuen_disable (& self) -> bool { * self == SCTR_SWUEN_A :: SCTR_SWUEN_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_sctr_swuen_enable (& self) -> bool { * self == SCTR_SWUEN_A :: SCTR_SWUEN_ENABLE } } # [doc = "Field `SCTR_SWUEN` writer - Slave Wakeup Enable"] pub type SCTR_SWUEN_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , SCTR_SWUEN_A > ; impl < 'a , REG , const O : u8 > SCTR_SWUEN_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn sctr_swuen_disable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_SWUEN_A :: SCTR_SWUEN_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn sctr_swuen_enable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_SWUEN_A :: SCTR_SWUEN_ENABLE) } } impl R { # [doc = "Bit 0 - Device Active. Setting this bit enables the slave functionality."] # [inline (always)] pub fn sctr_active (& self) -> SCTR_ACTIVE_R { SCTR_ACTIVE_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - General call response enable. This bit is only available in UCBxI2COA0. Modify only when UCSWRST = 1. 0b = Do not respond to a general call 1b = Respond to a general call"] # [inline (always)] pub fn sctr_gencall (& self) -> SCTR_GENCALL_R { SCTR_GENCALL_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - Slave Clock Stretch Enable"] # [inline (always)] pub fn sctr_sclkstretch (& self) -> SCTR_SCLKSTRETCH_R { SCTR_SCLKSTRETCH_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - Tx Empty Interrupt on TREQ"] # [inline (always)] pub fn sctr_txempty_on_treq (& self) -> SCTR_TXEMPTY_ON_TREQ_R { SCTR_TXEMPTY_ON_TREQ_R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - Tx Trigger when slave FSM is in Tx Mode"] # [inline (always)] pub fn sctr_txtrig_txmode (& self) -> SCTR_TXTRIG_TXMODE_R { SCTR_TXTRIG_TXMODE_R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - Tx transfer waits when stale data in Tx FIFO. This prevents stale bytes left in the TX FIFO from automatically being sent on the next I2C packet. Note: this should be used with TXEMPTY_ON_TREQ set to prevent the Slave State Machine from waiting for TX FIFO data without an interrupt notification when the FIFO data is stale."] # [inline (always)] pub fn sctr_txwait_stale_txfifo (& self) -> SCTR_TXWAIT_STALE_TXFIFO_R { SCTR_TXWAIT_STALE_TXFIFO_R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - Rx full interrupt generated on RREQ condition as indicated in SSR"] # [inline (always)] pub fn sctr_rxfull_on_rreq (& self) -> SCTR_RXFULL_ON_RREQ_R { SCTR_RXFULL_ON_RREQ_R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - Enable Default Host Address"] # [inline (always)] pub fn sctr_en_defhostadr (& self) -> SCTR_EN_DEFHOSTADR_R { SCTR_EN_DEFHOSTADR_R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - Enable Alert Response Address"] # [inline (always)] pub fn sctr_en_alrespadr (& self) -> SCTR_EN_ALRESPADR_R { SCTR_EN_ALRESPADR_R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - Enable Deault device address"] # [inline (always)] pub fn sctr_en_defdevadr (& self) -> SCTR_EN_DEFDEVADR_R { SCTR_EN_DEFDEVADR_R :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - Slave Wakeup Enable"] # [inline (always)] pub fn sctr_swuen (& self) -> SCTR_SWUEN_R { SCTR_SWUEN_R :: new (((self . bits >> 10) & 1) != 0) } } impl W { # [doc = "Bit 0 - Device Active. Setting this bit enables the slave functionality."] # [inline (always)] # [must_use] pub fn sctr_active (& mut self) -> SCTR_ACTIVE_W < SCTR_SPEC , 0 > { SCTR_ACTIVE_W :: new (self) } # [doc = "Bit 1 - General call response enable. This bit is only available in UCBxI2COA0. Modify only when UCSWRST = 1. 0b = Do not respond to a general call 1b = Respond to a general call"] # [inline (always)] # [must_use] pub fn sctr_gencall (& mut self) -> SCTR_GENCALL_W < SCTR_SPEC , 1 > { SCTR_GENCALL_W :: new (self) } # [doc = "Bit 2 - Slave Clock Stretch Enable"] # [inline (always)] # [must_use] pub fn sctr_sclkstretch (& mut self) -> SCTR_SCLKSTRETCH_W < SCTR_SPEC , 2 > { SCTR_SCLKSTRETCH_W :: new (self) } # [doc = "Bit 3 - Tx Empty Interrupt on TREQ"] # [inline (always)] # [must_use] pub fn sctr_txempty_on_treq (& mut self) -> SCTR_TXEMPTY_ON_TREQ_W < SCTR_SPEC , 3 > { SCTR_TXEMPTY_ON_TREQ_W :: new (self) } # [doc = "Bit 4 - Tx Trigger when slave FSM is in Tx Mode"] # [inline (always)] # [must_use] pub fn sctr_txtrig_txmode (& mut self) -> SCTR_TXTRIG_TXMODE_W < SCTR_SPEC , 4 > { SCTR_TXTRIG_TXMODE_W :: new (self) } # [doc = "Bit 5 - Tx transfer waits when stale data in Tx FIFO. This prevents stale bytes left in the TX FIFO from automatically being sent on the next I2C packet. Note: this should be used with TXEMPTY_ON_TREQ set to prevent the Slave State Machine from waiting for TX FIFO data without an interrupt notification when the FIFO data is stale."] # [inline (always)] # [must_use] pub fn sctr_txwait_stale_txfifo (& mut self) -> SCTR_TXWAIT_STALE_TXFIFO_W < SCTR_SPEC , 5 > { SCTR_TXWAIT_STALE_TXFIFO_W :: new (self) } # [doc = "Bit 6 - Rx full interrupt generated on RREQ condition as indicated in SSR"] # [inline (always)] # [must_use] pub fn sctr_rxfull_on_rreq (& mut self) -> SCTR_RXFULL_ON_RREQ_W < SCTR_SPEC , 6 > { SCTR_RXFULL_ON_RREQ_W :: new (self) } # [doc = "Bit 7 - Enable Default Host Address"] # [inline (always)] # [must_use] pub fn sctr_en_defhostadr (& mut self) -> SCTR_EN_DEFHOSTADR_W < SCTR_SPEC , 7 > { SCTR_EN_DEFHOSTADR_W :: new (self) } # [doc = "Bit 8 - Enable Alert Response Address"] # [inline (always)] # [must_use] pub fn sctr_en_alrespadr (& mut self) -> SCTR_EN_ALRESPADR_W <'_, SCTR_SPEC , 8 > { SCTR_EN_ALRESPADR_W :: new (self) } # [doc = "Bit 9 - Enable Deault device address"] # [inline (always)] # [must_use] pub fn sctr_en_defdevadr (& mut self) -> SCTR_EN_DEFDEVADR_W < SCTR_SPEC , 9 > { SCTR_EN_DEFDEVADR_W :: new (self) } # [doc = "Bit 10 - Slave Wakeup Enable"] # [inline (always)] # [must_use] pub fn sctr_swuen (& mut self) -> SCTR_SWUEN_W < SCTR_SPEC , 10 > { SCTR_SWUEN_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "I2C Slave Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sctr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sctr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct SCTR_SPEC ; impl crate :: RegisterSpec for SCTR_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`sctr::R`](R) reader structure"] impl crate :: Readable for SCTR_SPEC { } # [doc = "`write(|w| ..)` method takes [`sctr::W`](W) writer structure"] impl crate :: Writable for SCTR_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets SCTR to value 0x0404"] impl crate :: Resettable for SCTR_SPEC { const RESET_VALUE : Self :: Ux = 0x0404 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/i2c0/sfifoctl.rs:1:12308 [INFO] [stdout] | [INFO] [stdout] 1 | ...ub fn sfifoctl_txtrig (& mut self) -> SFIFOCTL_TXTRIG_W < SFIFOCTL_SPEC , 0 > { SFIFOCTL_TXTRIG_W :: new (self) } # [doc = "Bit 7 - TX... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `SFIFOCTL` reader"] pub type R = crate :: R < SFIFOCTL_SPEC > ; # [doc = "Register `SFIFOCTL` writer"] pub type W = crate :: W < SFIFOCTL_SPEC > ; # [doc = "Field `SFIFOCTL_TXTRIG` reader - TX FIFO Trigger Indicates at what fill level in the TX FIFO a trigger will be generated."] pub type SFIFOCTL_TXTRIG_R = crate :: FieldReader < SFIFOCTL_TXTRIG_A > ; # [doc = "TX FIFO Trigger Indicates at what fill level in the TX FIFO a trigger will be generated.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum SFIFOCTL_TXTRIG_A { # [doc = "4: LEVEL_4"] SFIFOCTL_TXTRIG_LEVEL_4 = 4 , # [doc = "5: LEVEL_5"] SFIFOCTL_TXTRIG_LEVEL_5 = 5 , # [doc = "6: LEVEL_6"] SFIFOCTL_TXTRIG_LEVEL_6 = 6 , # [doc = "7: LEVEL_7"] SFIFOCTL_TXTRIG_LEVEL_7 = 7 , } impl From < SFIFOCTL_TXTRIG_A > for u8 { # [inline (always)] fn from (variant : SFIFOCTL_TXTRIG_A) -> Self { variant as _ } } impl crate :: FieldSpec for SFIFOCTL_TXTRIG_A { type Ux = u8 ; } impl SFIFOCTL_TXTRIG_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < SFIFOCTL_TXTRIG_A > { match self . bits { 4 => Some (SFIFOCTL_TXTRIG_A :: SFIFOCTL_TXTRIG_LEVEL_4) , 5 => Some (SFIFOCTL_TXTRIG_A :: SFIFOCTL_TXTRIG_LEVEL_5) , 6 => Some (SFIFOCTL_TXTRIG_A :: SFIFOCTL_TXTRIG_LEVEL_6) , 7 => Some (SFIFOCTL_TXTRIG_A :: SFIFOCTL_TXTRIG_LEVEL_7) , _ => None , } } # [doc = "LEVEL_4"] # [inline (always)] pub fn is_sfifoctl_txtrig_level_4 (& self) -> bool { * self == SFIFOCTL_TXTRIG_A :: SFIFOCTL_TXTRIG_LEVEL_4 } # [doc = "LEVEL_5"] # [inline (always)] pub fn is_sfifoctl_txtrig_level_5 (& self) -> bool { * self == SFIFOCTL_TXTRIG_A :: SFIFOCTL_TXTRIG_LEVEL_5 } # [doc = "LEVEL_6"] # [inline (always)] pub fn is_sfifoctl_txtrig_level_6 (& self) -> bool { * self == SFIFOCTL_TXTRIG_A :: SFIFOCTL_TXTRIG_LEVEL_6 } # [doc = "LEVEL_7"] # [inline (always)] pub fn is_sfifoctl_txtrig_level_7 (& self) -> bool { * self == SFIFOCTL_TXTRIG_A :: SFIFOCTL_TXTRIG_LEVEL_7 } } # [doc = "Field `SFIFOCTL_TXTRIG` writer - TX FIFO Trigger Indicates at what fill level in the TX FIFO a trigger will be generated."] pub type SFIFOCTL_TXTRIG_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 3 , O , SFIFOCTL_TXTRIG_A > ; impl < 'a , REG , const O : u8 > SFIFOCTL_TXTRIG_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "LEVEL_4"] # [inline (always)] pub fn sfifoctl_txtrig_level_4 (self) -> & 'a mut crate :: W < REG > { self . variant (SFIFOCTL_TXTRIG_A :: SFIFOCTL_TXTRIG_LEVEL_4) } # [doc = "LEVEL_5"] # [inline (always)] pub fn sfifoctl_txtrig_level_5 (self) -> & 'a mut crate :: W < REG > { self . variant (SFIFOCTL_TXTRIG_A :: SFIFOCTL_TXTRIG_LEVEL_5) } # [doc = "LEVEL_6"] # [inline (always)] pub fn sfifoctl_txtrig_level_6 (self) -> & 'a mut crate :: W < REG > { self . variant (SFIFOCTL_TXTRIG_A :: SFIFOCTL_TXTRIG_LEVEL_6) } # [doc = "LEVEL_7"] # [inline (always)] pub fn sfifoctl_txtrig_level_7 (self) -> & 'a mut crate :: W < REG > { self . variant (SFIFOCTL_TXTRIG_A :: SFIFOCTL_TXTRIG_LEVEL_7) } } # [doc = "Field `SFIFOCTL_TXFLUSH` reader - TX FIFO Flush Setting this bit will Flush the TX FIFO. Before reseting this bit to stop Flush the TXFIFOCNT should be checked to be 8 and indicating that the Flush has completed."] pub type SFIFOCTL_TXFLUSH_R = crate :: BitReader < SFIFOCTL_TXFLUSH_A > ; # [doc = "TX FIFO Flush Setting this bit will Flush the TX FIFO. Before reseting this bit to stop Flush the TXFIFOCNT should be checked to be 8 and indicating that the Flush has completed.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum SFIFOCTL_TXFLUSH_A { # [doc = "0: NOFLUSH"] SFIFOCTL_TXFLUSH_NOFLUSH = 0 , # [doc = "1: FLUSH"] SFIFOCTL_TXFLUSH_FLUSH = 1 , } impl From < SFIFOCTL_TXFLUSH_A > for bool { # [inline (always)] fn from (variant : SFIFOCTL_TXFLUSH_A) -> Self { variant as u8 != 0 } } impl SFIFOCTL_TXFLUSH_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> SFIFOCTL_TXFLUSH_A { match self . bits { false => SFIFOCTL_TXFLUSH_A :: SFIFOCTL_TXFLUSH_NOFLUSH , true => SFIFOCTL_TXFLUSH_A :: SFIFOCTL_TXFLUSH_FLUSH , } } # [doc = "NOFLUSH"] # [inline (always)] pub fn is_sfifoctl_txflush_noflush (& self) -> bool { * self == SFIFOCTL_TXFLUSH_A :: SFIFOCTL_TXFLUSH_NOFLUSH } # [doc = "FLUSH"] # [inline (always)] pub fn is_sfifoctl_txflush_flush (& self) -> bool { * self == SFIFOCTL_TXFLUSH_A :: SFIFOCTL_TXFLUSH_FLUSH } } # [doc = "Field `SFIFOCTL_TXFLUSH` writer - TX FIFO Flush Setting this bit will Flush the TX FIFO. Before reseting this bit to stop Flush the TXFIFOCNT should be checked to be 8 and indicating that the Flush has completed."] pub type SFIFOCTL_TXFLUSH_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , SFIFOCTL_TXFLUSH_A > ; impl < 'a , REG , const O : u8 > SFIFOCTL_TXFLUSH_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NOFLUSH"] # [inline (always)] pub fn sfifoctl_txflush_noflush (self) -> & 'a mut crate :: W < REG > { self . variant (SFIFOCTL_TXFLUSH_A :: SFIFOCTL_TXFLUSH_NOFLUSH) } # [doc = "FLUSH"] # [inline (always)] pub fn sfifoctl_txflush_flush (self) -> & 'a mut crate :: W < REG > { self . variant (SFIFOCTL_TXFLUSH_A :: SFIFOCTL_TXFLUSH_FLUSH) } } # [doc = "Field `SFIFOCTL_RXTRIG` reader - RX FIFO Trigger Indicates at what fill level in the RX FIFO a trigger will be generated. Note: Programming RXTRIG to 0x0 has no effect since no data is present to transfer out of RX FIFO."] pub type SFIFOCTL_RXTRIG_R = crate :: FieldReader < SFIFOCTL_RXTRIG_A > ; # [doc = "RX FIFO Trigger Indicates at what fill level in the RX FIFO a trigger will be generated. Note: Programming RXTRIG to 0x0 has no effect since no data is present to transfer out of RX FIFO.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum SFIFOCTL_RXTRIG_A { # [doc = "4: LEVEL_5"] SFIFOCTL_RXTRIG_LEVEL_5 = 4 , # [doc = "5: LEVEL_6"] SFIFOCTL_RXTRIG_LEVEL_6 = 5 , # [doc = "6: LEVEL_7"] SFIFOCTL_RXTRIG_LEVEL_7 = 6 , # [doc = "7: LEVEL_8"] SFIFOCTL_RXTRIG_LEVEL_8 = 7 , } impl From < SFIFOCTL_RXTRIG_A > for u8 { # [inline (always)] fn from (variant : SFIFOCTL_RXTRIG_A) -> Self { variant as _ } } impl crate :: FieldSpec for SFIFOCTL_RXTRIG_A { type Ux = u8 ; } impl SFIFOCTL_RXTRIG_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < SFIFOCTL_RXTRIG_A > { match self . bits { 4 => Some (SFIFOCTL_RXTRIG_A :: SFIFOCTL_RXTRIG_LEVEL_5) , 5 => Some (SFIFOCTL_RXTRIG_A :: SFIFOCTL_RXTRIG_LEVEL_6) , 6 => Some (SFIFOCTL_RXTRIG_A :: SFIFOCTL_RXTRIG_LEVEL_7) , 7 => Some (SFIFOCTL_RXTRIG_A :: SFIFOCTL_RXTRIG_LEVEL_8) , _ => None , } } # [doc = "LEVEL_5"] # [inline (always)] pub fn is_sfifoctl_rxtrig_level_5 (& self) -> bool { * self == SFIFOCTL_RXTRIG_A :: SFIFOCTL_RXTRIG_LEVEL_5 } # [doc = "LEVEL_6"] # [inline (always)] pub fn is_sfifoctl_rxtrig_level_6 (& self) -> bool { * self == SFIFOCTL_RXTRIG_A :: SFIFOCTL_RXTRIG_LEVEL_6 } # [doc = "LEVEL_7"] # [inline (always)] pub fn is_sfifoctl_rxtrig_level_7 (& self) -> bool { * self == SFIFOCTL_RXTRIG_A :: SFIFOCTL_RXTRIG_LEVEL_7 } # [doc = "LEVEL_8"] # [inline (always)] pub fn is_sfifoctl_rxtrig_level_8 (& self) -> bool { * self == SFIFOCTL_RXTRIG_A :: SFIFOCTL_RXTRIG_LEVEL_8 } } # [doc = "Field `SFIFOCTL_RXTRIG` writer - RX FIFO Trigger Indicates at what fill level in the RX FIFO a trigger will be generated. Note: Programming RXTRIG to 0x0 has no effect since no data is present to transfer out of RX FIFO."] pub type SFIFOCTL_RXTRIG_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 3 , O , SFIFOCTL_RXTRIG_A > ; impl < 'a , REG , const O : u8 > SFIFOCTL_RXTRIG_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "LEVEL_5"] # [inline (always)] pub fn sfifoctl_rxtrig_level_5 (self) -> & 'a mut crate :: W < REG > { self . variant (SFIFOCTL_RXTRIG_A :: SFIFOCTL_RXTRIG_LEVEL_5) } # [doc = "LEVEL_6"] # [inline (always)] pub fn sfifoctl_rxtrig_level_6 (self) -> & 'a mut crate :: W < REG > { self . variant (SFIFOCTL_RXTRIG_A :: SFIFOCTL_RXTRIG_LEVEL_6) } # [doc = "LEVEL_7"] # [inline (always)] pub fn sfifoctl_rxtrig_level_7 (self) -> & 'a mut crate :: W < REG > { self . variant (SFIFOCTL_RXTRIG_A :: SFIFOCTL_RXTRIG_LEVEL_7) } # [doc = "LEVEL_8"] # [inline (always)] pub fn sfifoctl_rxtrig_level_8 (self) -> & 'a mut crate :: W < REG > { self . variant (SFIFOCTL_RXTRIG_A :: SFIFOCTL_RXTRIG_LEVEL_8) } } # [doc = "Field `SFIFOCTL_RXFLUSH` reader - RX FIFO Flush Setting this bit will Flush the RX FIFO. Before reseting this bit to stop Flush the RXFIFOCNT should be checked to be 0 and indicating that the Flush has completed."] pub type SFIFOCTL_RXFLUSH_R = crate :: BitReader < SFIFOCTL_RXFLUSH_A > ; # [doc = "RX FIFO Flush Setting this bit will Flush the RX FIFO. Before reseting this bit to stop Flush the RXFIFOCNT should be checked to be 0 and indicating that the Flush has completed.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum SFIFOCTL_RXFLUSH_A { # [doc = "0: NOFLUSH"] SFIFOCTL_RXFLUSH_NOFLUSH = 0 , # [doc = "1: FLUSH"] SFIFOCTL_RXFLUSH_FLUSH = 1 , } impl From < SFIFOCTL_RXFLUSH_A > for bool { # [inline (always)] fn from (variant : SFIFOCTL_RXFLUSH_A) -> Self { variant as u8 != 0 } } impl SFIFOCTL_RXFLUSH_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> SFIFOCTL_RXFLUSH_A { match self . bits { false => SFIFOCTL_RXFLUSH_A :: SFIFOCTL_RXFLUSH_NOFLUSH , true => SFIFOCTL_RXFLUSH_A :: SFIFOCTL_RXFLUSH_FLUSH , } } # [doc = "NOFLUSH"] # [inline (always)] pub fn is_sfifoctl_rxflush_noflush (& self) -> bool { * self == SFIFOCTL_RXFLUSH_A :: SFIFOCTL_RXFLUSH_NOFLUSH } # [doc = "FLUSH"] # [inline (always)] pub fn is_sfifoctl_rxflush_flush (& self) -> bool { * self == SFIFOCTL_RXFLUSH_A :: SFIFOCTL_RXFLUSH_FLUSH } } # [doc = "Field `SFIFOCTL_RXFLUSH` writer - RX FIFO Flush Setting this bit will Flush the RX FIFO. Before reseting this bit to stop Flush the RXFIFOCNT should be checked to be 0 and indicating that the Flush has completed."] pub type SFIFOCTL_RXFLUSH_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , SFIFOCTL_RXFLUSH_A > ; impl < 'a , REG , const O : u8 > SFIFOCTL_RXFLUSH_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NOFLUSH"] # [inline (always)] pub fn sfifoctl_rxflush_noflush (self) -> & 'a mut crate :: W < REG > { self . variant (SFIFOCTL_RXFLUSH_A :: SFIFOCTL_RXFLUSH_NOFLUSH) } # [doc = "FLUSH"] # [inline (always)] pub fn sfifoctl_rxflush_flush (self) -> & 'a mut crate :: W < REG > { self . variant (SFIFOCTL_RXFLUSH_A :: SFIFOCTL_RXFLUSH_FLUSH) } } impl R { # [doc = "Bits 0:2 - TX FIFO Trigger Indicates at what fill level in the TX FIFO a trigger will be generated."] # [inline (always)] pub fn sfifoctl_txtrig (& self) -> SFIFOCTL_TXTRIG_R { SFIFOCTL_TXTRIG_R :: new ((self . bits & 7) as u8) } # [doc = "Bit 7 - TX FIFO Flush Setting this bit will Flush the TX FIFO. Before reseting this bit to stop Flush the TXFIFOCNT should be checked to be 8 and indicating that the Flush has completed."] # [inline (always)] pub fn sfifoctl_txflush (& self) -> SFIFOCTL_TXFLUSH_R { SFIFOCTL_TXFLUSH_R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bits 8:10 - RX FIFO Trigger Indicates at what fill level in the RX FIFO a trigger will be generated. Note: Programming RXTRIG to 0x0 has no effect since no data is present to transfer out of RX FIFO."] # [inline (always)] pub fn sfifoctl_rxtrig (& self) -> SFIFOCTL_RXTRIG_R { SFIFOCTL_RXTRIG_R :: new (((self . bits >> 8) & 7) as u8) } # [doc = "Bit 15 - RX FIFO Flush Setting this bit will Flush the RX FIFO. Before reseting this bit to stop Flush the RXFIFOCNT should be checked to be 0 and indicating that the Flush has completed."] # [inline (always)] pub fn sfifoctl_rxflush (& self) -> SFIFOCTL_RXFLUSH_R { SFIFOCTL_RXFLUSH_R :: new (((self . bits >> 15) & 1) != 0) } } impl W { # [doc = "Bits 0:2 - TX FIFO Trigger Indicates at what fill level in the TX FIFO a trigger will be generated."] # [inline (always)] # [must_use] pub fn sfifoctl_txtrig (& mut self) -> SFIFOCTL_TXTRIG_W <'_, SFIFOCTL_SPEC , 0 > { SFIFOCTL_TXTRIG_W :: new (self) } # [doc = "Bit 7 - TX FIFO Flush Setting this bit will Flush the TX FIFO. Before reseting this bit to stop Flush the TXFIFOCNT should be checked to be 8 and indicating that the Flush has completed."] # [inline (always)] # [must_use] pub fn sfifoctl_txflush (& mut self) -> SFIFOCTL_TXFLUSH_W < SFIFOCTL_SPEC , 7 > { SFIFOCTL_TXFLUSH_W :: new (self) } # [doc = "Bits 8:10 - RX FIFO Trigger Indicates at what fill level in the RX FIFO a trigger will be generated. Note: Programming RXTRIG to 0x0 has no effect since no data is present to transfer out of RX FIFO."] # [inline (always)] # [must_use] pub fn sfifoctl_rxtrig (& mut self) -> SFIFOCTL_RXTRIG_W < SFIFOCTL_SPEC , 8 > { SFIFOCTL_RXTRIG_W :: new (self) } # [doc = "Bit 15 - RX FIFO Flush Setting this bit will Flush the RX FIFO. Before reseting this bit to stop Flush the RXFIFOCNT should be checked to be 0 and indicating that the Flush has completed."] # [inline (always)] # [must_use] pub fn sfifoctl_rxflush (& mut self) -> SFIFOCTL_RXFLUSH_W < SFIFOCTL_SPEC , 15 > { SFIFOCTL_RXFLUSH_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "I2C Slave FIFO Control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sfifoctl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sfifoctl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct SFIFOCTL_SPEC ; impl crate :: RegisterSpec for SFIFOCTL_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`sfifoctl::R`](R) reader structure"] impl crate :: Readable for SFIFOCTL_SPEC { } # [doc = "`write(|w| ..)` method takes [`sfifoctl::W`](W) writer structure"] impl crate :: Writable for SFIFOCTL_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets SFIFOCTL to value 0"] impl crate :: Resettable for SFIFOCTL_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/gpioa/pwren.rs:1:2941 [INFO] [stdout] | [INFO] [stdout] 1 | ...use] pub fn pwren_enable (& mut self) -> PWREN_ENABLE_W < PWREN_SPEC , 0 > { PWREN_ENABLE_W :: new (self) } # [doc = "Bits 24:31 - KEY... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `PWREN` reader"] pub type R = crate :: R < PWREN_SPEC > ; # [doc = "Register `PWREN` writer"] pub type W = crate :: W < PWREN_SPEC > ; # [doc = "Field `PWREN_ENABLE` reader - Enable the power"] pub type PWREN_ENABLE_R = crate :: BitReader < PWREN_ENABLE_A > ; # [doc = "Enable the power\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum PWREN_ENABLE_A { # [doc = "0: DISABLE"] PWREN_ENABLE_DISABLE = 0 , # [doc = "1: ENABLE"] PWREN_ENABLE_ENABLE = 1 , } impl From < PWREN_ENABLE_A > for bool { # [inline (always)] fn from (variant : PWREN_ENABLE_A) -> Self { variant as u8 != 0 } } impl PWREN_ENABLE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> PWREN_ENABLE_A { match self . bits { false => PWREN_ENABLE_A :: PWREN_ENABLE_DISABLE , true => PWREN_ENABLE_A :: PWREN_ENABLE_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_pwren_enable_disable (& self) -> bool { * self == PWREN_ENABLE_A :: PWREN_ENABLE_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_pwren_enable_enable (& self) -> bool { * self == PWREN_ENABLE_A :: PWREN_ENABLE_ENABLE } } # [doc = "Field `PWREN_ENABLE` writer - Enable the power"] pub type PWREN_ENABLE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , PWREN_ENABLE_A > ; impl < 'a , REG , const O : u8 > PWREN_ENABLE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn pwren_enable_disable (self) -> & 'a mut crate :: W < REG > { self . variant (PWREN_ENABLE_A :: PWREN_ENABLE_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn pwren_enable_enable (self) -> & 'a mut crate :: W < REG > { self . variant (PWREN_ENABLE_A :: PWREN_ENABLE_ENABLE) } } # [doc = "KEY to allow Power State Change\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum PWREN_KEY_AW { # [doc = "38: _TO_UNLOCK_W_"] PWREN_KEY_UNLOCK_W = 38 , } impl From < PWREN_KEY_AW > for u8 { # [inline (always)] fn from (variant : PWREN_KEY_AW) -> Self { variant as _ } } impl crate :: FieldSpec for PWREN_KEY_AW { type Ux = u8 ; } # [doc = "Field `PWREN_KEY` writer - KEY to allow Power State Change"] pub type PWREN_KEY_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 8 , O , PWREN_KEY_AW > ; impl < 'a , REG , const O : u8 > PWREN_KEY_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "_TO_UNLOCK_W_"] # [inline (always)] pub fn pwren_key_unlock_w (self) -> & 'a mut crate :: W < REG > { self . variant (PWREN_KEY_AW :: PWREN_KEY_UNLOCK_W) } } impl R { # [doc = "Bit 0 - Enable the power"] # [inline (always)] pub fn pwren_enable (& self) -> PWREN_ENABLE_R { PWREN_ENABLE_R :: new ((self . bits & 1) != 0) } } impl W { # [doc = "Bit 0 - Enable the power"] # [inline (always)] # [must_use] pub fn pwren_enable (& mut self) -> PWREN_ENABLE_W <'_, PWREN_SPEC , 0 > { PWREN_ENABLE_W :: new (self) } # [doc = "Bits 24:31 - KEY to allow Power State Change"] # [inline (always)] # [must_use] pub fn pwren_key (& mut self) -> PWREN_KEY_W < PWREN_SPEC , 24 > { PWREN_KEY_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Power enable\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pwren::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pwren::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PWREN_SPEC ; impl crate :: RegisterSpec for PWREN_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`pwren::R`](R) reader structure"] impl crate :: Readable for PWREN_SPEC { } # [doc = "`write(|w| ..)` method takes [`pwren::W`](W) writer structure"] impl crate :: Writable for PWREN_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets PWREN to value 0"] impl crate :: Resettable for PWREN_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/i2c1/soar2.rs:1:4719 [INFO] [stdout] | [INFO] [stdout] 1 | ...pub fn soar2_oar2_mask (& mut self) -> SOAR2_OAR2_MASK_W < SOAR2_SPEC , 16 > { SOAR2_OAR2_MASK_W :: new (self) } # [doc = r" Writes ra... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `SOAR2` reader"] pub type R = crate :: R < SOAR2_SPEC > ; # [doc = "Register `SOAR2` writer"] pub type W = crate :: W < SOAR2_SPEC > ; # [doc = "Field `SOAR2_OAR2` reader - I2C Slave Own Address 2 This field specifies the alternate OAR2 address."] pub type SOAR2_OAR2_R = crate :: FieldReader ; # [doc = "Field `SOAR2_OAR2` writer - I2C Slave Own Address 2 This field specifies the alternate OAR2 address."] pub type SOAR2_OAR2_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 7 , O > ; # [doc = "Field `SOAR2_OAR2EN` reader - I2C Slave Own Address 2 Enable"] pub type SOAR2_OAR2EN_R = crate :: BitReader < SOAR2_OAR2EN_A > ; # [doc = "I2C Slave Own Address 2 Enable\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum SOAR2_OAR2EN_A { # [doc = "0: DISABLE"] SOAR2_OAR2EN_DISABLE = 0 , # [doc = "1: ENABLE"] SOAR2_OAR2EN_ENABLE = 1 , } impl From < SOAR2_OAR2EN_A > for bool { # [inline (always)] fn from (variant : SOAR2_OAR2EN_A) -> Self { variant as u8 != 0 } } impl SOAR2_OAR2EN_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> SOAR2_OAR2EN_A { match self . bits { false => SOAR2_OAR2EN_A :: SOAR2_OAR2EN_DISABLE , true => SOAR2_OAR2EN_A :: SOAR2_OAR2EN_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_soar2_oar2en_disable (& self) -> bool { * self == SOAR2_OAR2EN_A :: SOAR2_OAR2EN_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_soar2_oar2en_enable (& self) -> bool { * self == SOAR2_OAR2EN_A :: SOAR2_OAR2EN_ENABLE } } # [doc = "Field `SOAR2_OAR2EN` writer - I2C Slave Own Address 2 Enable"] pub type SOAR2_OAR2EN_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , SOAR2_OAR2EN_A > ; impl < 'a , REG , const O : u8 > SOAR2_OAR2EN_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn soar2_oar2en_disable (self) -> & 'a mut crate :: W < REG > { self . variant (SOAR2_OAR2EN_A :: SOAR2_OAR2EN_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn soar2_oar2en_enable (self) -> & 'a mut crate :: W < REG > { self . variant (SOAR2_OAR2EN_A :: SOAR2_OAR2EN_ENABLE) } } # [doc = "Field `SOAR2_OAR2_MASK` reader - I2C Slave Own Address 2 Mask: This field specifies bits A6 through A0 of the slave address. The bits with value 1 in SOAR2.OAR2_MASK field will make the corresponding incoming address bits to match by default regardless of the value inside SOAR2.OAR2 i.e. corresponding SOAR2.OAR2 bit is a dont care."] pub type SOAR2_OAR2_MASK_R = crate :: FieldReader ; # [doc = "Field `SOAR2_OAR2_MASK` writer - I2C Slave Own Address 2 Mask: This field specifies bits A6 through A0 of the slave address. The bits with value 1 in SOAR2.OAR2_MASK field will make the corresponding incoming address bits to match by default regardless of the value inside SOAR2.OAR2 i.e. corresponding SOAR2.OAR2 bit is a dont care."] pub type SOAR2_OAR2_MASK_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 7 , O > ; impl R { # [doc = "Bits 0:6 - I2C Slave Own Address 2 This field specifies the alternate OAR2 address."] # [inline (always)] pub fn soar2_oar2 (& self) -> SOAR2_OAR2_R { SOAR2_OAR2_R :: new ((self . bits & 0x7f) as u8) } # [doc = "Bit 7 - I2C Slave Own Address 2 Enable"] # [inline (always)] pub fn soar2_oar2en (& self) -> SOAR2_OAR2EN_R { SOAR2_OAR2EN_R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bits 16:22 - I2C Slave Own Address 2 Mask: This field specifies bits A6 through A0 of the slave address. The bits with value 1 in SOAR2.OAR2_MASK field will make the corresponding incoming address bits to match by default regardless of the value inside SOAR2.OAR2 i.e. corresponding SOAR2.OAR2 bit is a dont care."] # [inline (always)] pub fn soar2_oar2_mask (& self) -> SOAR2_OAR2_MASK_R { SOAR2_OAR2_MASK_R :: new (((self . bits >> 16) & 0x7f) as u8) } } impl W { # [doc = "Bits 0:6 - I2C Slave Own Address 2 This field specifies the alternate OAR2 address."] # [inline (always)] # [must_use] pub fn soar2_oar2 (& mut self) -> SOAR2_OAR2_W < SOAR2_SPEC , 0 > { SOAR2_OAR2_W :: new (self) } # [doc = "Bit 7 - I2C Slave Own Address 2 Enable"] # [inline (always)] # [must_use] pub fn soar2_oar2en (& mut self) -> SOAR2_OAR2EN_W < SOAR2_SPEC , 7 > { SOAR2_OAR2EN_W :: new (self) } # [doc = "Bits 16:22 - I2C Slave Own Address 2 Mask: This field specifies bits A6 through A0 of the slave address. The bits with value 1 in SOAR2.OAR2_MASK field will make the corresponding incoming address bits to match by default regardless of the value inside SOAR2.OAR2 i.e. corresponding SOAR2.OAR2 bit is a dont care."] # [inline (always)] # [must_use] pub fn soar2_oar2_mask (& mut self) -> SOAR2_OAR2_MASK_W <'_, SOAR2_SPEC , 16 > { SOAR2_OAR2_MASK_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "I2C Slave Own Address 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`soar2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`soar2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct SOAR2_SPEC ; impl crate :: RegisterSpec for SOAR2_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`soar2::R`](R) reader structure"] impl crate :: Readable for SOAR2_SPEC { } # [doc = "`write(|w| ..)` method takes [`soar2::W`](W) writer structure"] impl crate :: Writable for SOAR2_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets SOAR2 to value 0"] impl crate :: Resettable for SOAR2_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/i2c1/msa.rs:1:5480 [INFO] [stdout] | [INFO] [stdout] 1 | ... # [must_use] pub fn msa_dir (& mut self) -> MSA_DIR_W < MSA_SPEC , 0 > { MSA_DIR_W :: new (self) } # [doc = "Bits 1:10 - I2C Slave Ad... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `MSA` reader"] pub type R = crate :: R < MSA_SPEC > ; # [doc = "Register `MSA` writer"] pub type W = crate :: W < MSA_SPEC > ; # [doc = "Field `MSA_DIR` reader - Receive/Send The DIR bit specifies if the next master operation is a Receive (High) or Transmit (Low). 0h = Transmit 1h = Receive"] pub type MSA_DIR_R = crate :: BitReader < MSA_DIR_A > ; # [doc = "Receive/Send The DIR bit specifies if the next master operation is a Receive (High) or Transmit (Low). 0h = Transmit 1h = Receive\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum MSA_DIR_A { # [doc = "0: TRANSMIT"] MSA_DIR_TRANSMIT = 0 , # [doc = "1: RECEIVE"] MSA_DIR_RECEIVE = 1 , } impl From < MSA_DIR_A > for bool { # [inline (always)] fn from (variant : MSA_DIR_A) -> Self { variant as u8 != 0 } } impl MSA_DIR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> MSA_DIR_A { match self . bits { false => MSA_DIR_A :: MSA_DIR_TRANSMIT , true => MSA_DIR_A :: MSA_DIR_RECEIVE , } } # [doc = "TRANSMIT"] # [inline (always)] pub fn is_msa_dir_transmit (& self) -> bool { * self == MSA_DIR_A :: MSA_DIR_TRANSMIT } # [doc = "RECEIVE"] # [inline (always)] pub fn is_msa_dir_receive (& self) -> bool { * self == MSA_DIR_A :: MSA_DIR_RECEIVE } } # [doc = "Field `MSA_DIR` writer - Receive/Send The DIR bit specifies if the next master operation is a Receive (High) or Transmit (Low). 0h = Transmit 1h = Receive"] pub type MSA_DIR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , MSA_DIR_A > ; impl < 'a , REG , const O : u8 > MSA_DIR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "TRANSMIT"] # [inline (always)] pub fn msa_dir_transmit (self) -> & 'a mut crate :: W < REG > { self . variant (MSA_DIR_A :: MSA_DIR_TRANSMIT) } # [doc = "RECEIVE"] # [inline (always)] pub fn msa_dir_receive (self) -> & 'a mut crate :: W < REG > { self . variant (MSA_DIR_A :: MSA_DIR_RECEIVE) } } # [doc = "Field `MSA_SADDR` reader - I2C Slave Address This field specifies bits A9 through A0 of the slave address. In 7-bit addressing mode as selected by MSA.MODE bit, the top 3 bits are don't care"] pub type MSA_SADDR_R = crate :: FieldReader < u16 > ; # [doc = "Field `MSA_SADDR` writer - I2C Slave Address This field specifies bits A9 through A0 of the slave address. In 7-bit addressing mode as selected by MSA.MODE bit, the top 3 bits are don't care"] pub type MSA_SADDR_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 10 , O , u16 > ; # [doc = "Field `MSA_MMODE` reader - This bit selects the adressing mode to be used in master mode When 0, 7-bit addressing is used. When 1, 10-bit addressing is used."] pub type MSA_MMODE_R = crate :: BitReader < MSA_MMODE_A > ; # [doc = "This bit selects the adressing mode to be used in master mode When 0, 7-bit addressing is used. When 1, 10-bit addressing is used.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum MSA_MMODE_A { # [doc = "0: MODE7"] MSA_MMODE_MODE7 = 0 , # [doc = "1: MODE10"] MSA_MMODE_MODE10 = 1 , } impl From < MSA_MMODE_A > for bool { # [inline (always)] fn from (variant : MSA_MMODE_A) -> Self { variant as u8 != 0 } } impl MSA_MMODE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> MSA_MMODE_A { match self . bits { false => MSA_MMODE_A :: MSA_MMODE_MODE7 , true => MSA_MMODE_A :: MSA_MMODE_MODE10 , } } # [doc = "MODE7"] # [inline (always)] pub fn is_msa_mmode_mode7 (& self) -> bool { * self == MSA_MMODE_A :: MSA_MMODE_MODE7 } # [doc = "MODE10"] # [inline (always)] pub fn is_msa_mmode_mode10 (& self) -> bool { * self == MSA_MMODE_A :: MSA_MMODE_MODE10 } } # [doc = "Field `MSA_MMODE` writer - This bit selects the adressing mode to be used in master mode When 0, 7-bit addressing is used. When 1, 10-bit addressing is used."] pub type MSA_MMODE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , MSA_MMODE_A > ; impl < 'a , REG , const O : u8 > MSA_MMODE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "MODE7"] # [inline (always)] pub fn msa_mmode_mode7 (self) -> & 'a mut crate :: W < REG > { self . variant (MSA_MMODE_A :: MSA_MMODE_MODE7) } # [doc = "MODE10"] # [inline (always)] pub fn msa_mmode_mode10 (self) -> & 'a mut crate :: W < REG > { self . variant (MSA_MMODE_A :: MSA_MMODE_MODE10) } } impl R { # [doc = "Bit 0 - Receive/Send The DIR bit specifies if the next master operation is a Receive (High) or Transmit (Low). 0h = Transmit 1h = Receive"] # [inline (always)] pub fn msa_dir (& self) -> MSA_DIR_R { MSA_DIR_R :: new ((self . bits & 1) != 0) } # [doc = "Bits 1:10 - I2C Slave Address This field specifies bits A9 through A0 of the slave address. In 7-bit addressing mode as selected by MSA.MODE bit, the top 3 bits are don't care"] # [inline (always)] pub fn msa_saddr (& self) -> MSA_SADDR_R { MSA_SADDR_R :: new (((self . bits >> 1) & 0x03ff) as u16) } # [doc = "Bit 15 - This bit selects the adressing mode to be used in master mode When 0, 7-bit addressing is used. When 1, 10-bit addressing is used."] # [inline (always)] pub fn msa_mmode (& self) -> MSA_MMODE_R { MSA_MMODE_R :: new (((self . bits >> 15) & 1) != 0) } } impl W { # [doc = "Bit 0 - Receive/Send The DIR bit specifies if the next master operation is a Receive (High) or Transmit (Low). 0h = Transmit 1h = Receive"] # [inline (always)] # [must_use] pub fn msa_dir (& mut self) -> MSA_DIR_W <'_, MSA_SPEC , 0 > { MSA_DIR_W :: new (self) } # [doc = "Bits 1:10 - I2C Slave Address This field specifies bits A9 through A0 of the slave address. In 7-bit addressing mode as selected by MSA.MODE bit, the top 3 bits are don't care"] # [inline (always)] # [must_use] pub fn msa_saddr (& mut self) -> MSA_SADDR_W < MSA_SPEC , 1 > { MSA_SADDR_W :: new (self) } # [doc = "Bit 15 - This bit selects the adressing mode to be used in master mode When 0, 7-bit addressing is used. When 1, 10-bit addressing is used."] # [inline (always)] # [must_use] pub fn msa_mmode (& mut self) -> MSA_MMODE_W < MSA_SPEC , 15 > { MSA_MMODE_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "I2C Master Slave Address Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`msa::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`msa::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct MSA_SPEC ; impl crate :: RegisterSpec for MSA_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`msa::R`](R) reader structure"] impl crate :: Readable for MSA_SPEC { } # [doc = "`write(|w| ..)` method takes [`msa::W`](W) writer structure"] impl crate :: Writable for MSA_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets MSA to value 0"] impl crate :: Resettable for MSA_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/i2c1/int_event2_imask.rs:1:10727 [INFO] [stdout] | [INFO] [stdout] 1 | ..._stxfifotrg (& mut self) -> INT_EVENT2_IMASK_STXFIFOTRG_W < INT_EVENT2_IMASK_SPEC , 3 > { INT_EVENT2_IMASK_STXFIFOTRG_W :: new (self) ... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `INT_EVENT2_IMASK` reader"] pub type R = crate :: R < INT_EVENT2_IMASK_SPEC > ; # [doc = "Register `INT_EVENT2_IMASK` writer"] pub type W = crate :: W < INT_EVENT2_IMASK_SPEC > ; # [doc = "Field `INT_EVENT2_IMASK_MRXFIFOTRG` reader - Master Receive FIFO Trigger Trigger when RX FIFO contains &gt;= defined bytes"] pub type INT_EVENT2_IMASK_MRXFIFOTRG_R = crate :: BitReader < INT_EVENT2_IMASK_MRXFIFOTRG_A > ; # [doc = "Master Receive FIFO Trigger Trigger when RX FIFO contains &gt;= defined bytes\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT2_IMASK_MRXFIFOTRG_A { # [doc = "0: CLR"] INT_EVENT2_IMASK_MRXFIFOTRG_CLR = 0 , # [doc = "1: SET"] INT_EVENT2_IMASK_MRXFIFOTRG_SET = 1 , } impl From < INT_EVENT2_IMASK_MRXFIFOTRG_A > for bool { # [inline (always)] fn from (variant : INT_EVENT2_IMASK_MRXFIFOTRG_A) -> Self { variant as u8 != 0 } } impl INT_EVENT2_IMASK_MRXFIFOTRG_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT2_IMASK_MRXFIFOTRG_A { match self . bits { false => INT_EVENT2_IMASK_MRXFIFOTRG_A :: INT_EVENT2_IMASK_MRXFIFOTRG_CLR , true => INT_EVENT2_IMASK_MRXFIFOTRG_A :: INT_EVENT2_IMASK_MRXFIFOTRG_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event2_imask_mrxfifotrg_clr (& self) -> bool { * self == INT_EVENT2_IMASK_MRXFIFOTRG_A :: INT_EVENT2_IMASK_MRXFIFOTRG_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event2_imask_mrxfifotrg_set (& self) -> bool { * self == INT_EVENT2_IMASK_MRXFIFOTRG_A :: INT_EVENT2_IMASK_MRXFIFOTRG_SET } } # [doc = "Field `INT_EVENT2_IMASK_MRXFIFOTRG` writer - Master Receive FIFO Trigger Trigger when RX FIFO contains &gt;= defined bytes"] pub type INT_EVENT2_IMASK_MRXFIFOTRG_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT2_IMASK_MRXFIFOTRG_A > ; impl < 'a , REG , const O : u8 > INT_EVENT2_IMASK_MRXFIFOTRG_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event2_imask_mrxfifotrg_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT2_IMASK_MRXFIFOTRG_A :: INT_EVENT2_IMASK_MRXFIFOTRG_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event2_imask_mrxfifotrg_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT2_IMASK_MRXFIFOTRG_A :: INT_EVENT2_IMASK_MRXFIFOTRG_SET) } } # [doc = "Field `INT_EVENT2_IMASK_MTXFIFOTRG` reader - Master Transmit FIFO Trigger Trigger when Transmit FIFO contains &lt;= defined bytes"] pub type INT_EVENT2_IMASK_MTXFIFOTRG_R = crate :: BitReader < INT_EVENT2_IMASK_MTXFIFOTRG_A > ; # [doc = "Master Transmit FIFO Trigger Trigger when Transmit FIFO contains &lt;= defined bytes\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT2_IMASK_MTXFIFOTRG_A { # [doc = "0: CLR"] INT_EVENT2_IMASK_MTXFIFOTRG_CLR = 0 , # [doc = "1: SET"] INT_EVENT2_IMASK_MTXFIFOTRG_SET = 1 , } impl From < INT_EVENT2_IMASK_MTXFIFOTRG_A > for bool { # [inline (always)] fn from (variant : INT_EVENT2_IMASK_MTXFIFOTRG_A) -> Self { variant as u8 != 0 } } impl INT_EVENT2_IMASK_MTXFIFOTRG_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT2_IMASK_MTXFIFOTRG_A { match self . bits { false => INT_EVENT2_IMASK_MTXFIFOTRG_A :: INT_EVENT2_IMASK_MTXFIFOTRG_CLR , true => INT_EVENT2_IMASK_MTXFIFOTRG_A :: INT_EVENT2_IMASK_MTXFIFOTRG_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event2_imask_mtxfifotrg_clr (& self) -> bool { * self == INT_EVENT2_IMASK_MTXFIFOTRG_A :: INT_EVENT2_IMASK_MTXFIFOTRG_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event2_imask_mtxfifotrg_set (& self) -> bool { * self == INT_EVENT2_IMASK_MTXFIFOTRG_A :: INT_EVENT2_IMASK_MTXFIFOTRG_SET } } # [doc = "Field `INT_EVENT2_IMASK_MTXFIFOTRG` writer - Master Transmit FIFO Trigger Trigger when Transmit FIFO contains &lt;= defined bytes"] pub type INT_EVENT2_IMASK_MTXFIFOTRG_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT2_IMASK_MTXFIFOTRG_A > ; impl < 'a , REG , const O : u8 > INT_EVENT2_IMASK_MTXFIFOTRG_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event2_imask_mtxfifotrg_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT2_IMASK_MTXFIFOTRG_A :: INT_EVENT2_IMASK_MTXFIFOTRG_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event2_imask_mtxfifotrg_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT2_IMASK_MTXFIFOTRG_A :: INT_EVENT2_IMASK_MTXFIFOTRG_SET) } } # [doc = "Field `INT_EVENT2_IMASK_SRXFIFOTRG` reader - Slave Receive FIFO Trigger"] pub type INT_EVENT2_IMASK_SRXFIFOTRG_R = crate :: BitReader < INT_EVENT2_IMASK_SRXFIFOTRG_A > ; # [doc = "Slave Receive FIFO Trigger\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT2_IMASK_SRXFIFOTRG_A { # [doc = "0: CLR"] INT_EVENT2_IMASK_SRXFIFOTRG_CLR = 0 , # [doc = "1: SET"] INT_EVENT2_IMASK_SRXFIFOTRG_SET = 1 , } impl From < INT_EVENT2_IMASK_SRXFIFOTRG_A > for bool { # [inline (always)] fn from (variant : INT_EVENT2_IMASK_SRXFIFOTRG_A) -> Self { variant as u8 != 0 } } impl INT_EVENT2_IMASK_SRXFIFOTRG_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT2_IMASK_SRXFIFOTRG_A { match self . bits { false => INT_EVENT2_IMASK_SRXFIFOTRG_A :: INT_EVENT2_IMASK_SRXFIFOTRG_CLR , true => INT_EVENT2_IMASK_SRXFIFOTRG_A :: INT_EVENT2_IMASK_SRXFIFOTRG_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event2_imask_srxfifotrg_clr (& self) -> bool { * self == INT_EVENT2_IMASK_SRXFIFOTRG_A :: INT_EVENT2_IMASK_SRXFIFOTRG_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event2_imask_srxfifotrg_set (& self) -> bool { * self == INT_EVENT2_IMASK_SRXFIFOTRG_A :: INT_EVENT2_IMASK_SRXFIFOTRG_SET } } # [doc = "Field `INT_EVENT2_IMASK_SRXFIFOTRG` writer - Slave Receive FIFO Trigger"] pub type INT_EVENT2_IMASK_SRXFIFOTRG_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT2_IMASK_SRXFIFOTRG_A > ; impl < 'a , REG , const O : u8 > INT_EVENT2_IMASK_SRXFIFOTRG_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event2_imask_srxfifotrg_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT2_IMASK_SRXFIFOTRG_A :: INT_EVENT2_IMASK_SRXFIFOTRG_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event2_imask_srxfifotrg_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT2_IMASK_SRXFIFOTRG_A :: INT_EVENT2_IMASK_SRXFIFOTRG_SET) } } # [doc = "Field `INT_EVENT2_IMASK_STXFIFOTRG` reader - Slave Transmit FIFO Trigger"] pub type INT_EVENT2_IMASK_STXFIFOTRG_R = crate :: BitReader < INT_EVENT2_IMASK_STXFIFOTRG_A > ; # [doc = "Slave Transmit FIFO Trigger\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT2_IMASK_STXFIFOTRG_A { # [doc = "0: CLR"] INT_EVENT2_IMASK_STXFIFOTRG_CLR = 0 , # [doc = "1: SET"] INT_EVENT2_IMASK_STXFIFOTRG_SET = 1 , } impl From < INT_EVENT2_IMASK_STXFIFOTRG_A > for bool { # [inline (always)] fn from (variant : INT_EVENT2_IMASK_STXFIFOTRG_A) -> Self { variant as u8 != 0 } } impl INT_EVENT2_IMASK_STXFIFOTRG_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT2_IMASK_STXFIFOTRG_A { match self . bits { false => INT_EVENT2_IMASK_STXFIFOTRG_A :: INT_EVENT2_IMASK_STXFIFOTRG_CLR , true => INT_EVENT2_IMASK_STXFIFOTRG_A :: INT_EVENT2_IMASK_STXFIFOTRG_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event2_imask_stxfifotrg_clr (& self) -> bool { * self == INT_EVENT2_IMASK_STXFIFOTRG_A :: INT_EVENT2_IMASK_STXFIFOTRG_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event2_imask_stxfifotrg_set (& self) -> bool { * self == INT_EVENT2_IMASK_STXFIFOTRG_A :: INT_EVENT2_IMASK_STXFIFOTRG_SET } } # [doc = "Field `INT_EVENT2_IMASK_STXFIFOTRG` writer - Slave Transmit FIFO Trigger"] pub type INT_EVENT2_IMASK_STXFIFOTRG_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT2_IMASK_STXFIFOTRG_A > ; impl < 'a , REG , const O : u8 > INT_EVENT2_IMASK_STXFIFOTRG_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event2_imask_stxfifotrg_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT2_IMASK_STXFIFOTRG_A :: INT_EVENT2_IMASK_STXFIFOTRG_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event2_imask_stxfifotrg_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT2_IMASK_STXFIFOTRG_A :: INT_EVENT2_IMASK_STXFIFOTRG_SET) } } impl R { # [doc = "Bit 0 - Master Receive FIFO Trigger Trigger when RX FIFO contains &gt;= defined bytes"] # [inline (always)] pub fn int_event2_imask_mrxfifotrg (& self) -> INT_EVENT2_IMASK_MRXFIFOTRG_R { INT_EVENT2_IMASK_MRXFIFOTRG_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - Master Transmit FIFO Trigger Trigger when Transmit FIFO contains &lt;= defined bytes"] # [inline (always)] pub fn int_event2_imask_mtxfifotrg (& self) -> INT_EVENT2_IMASK_MTXFIFOTRG_R { INT_EVENT2_IMASK_MTXFIFOTRG_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - Slave Receive FIFO Trigger"] # [inline (always)] pub fn int_event2_imask_srxfifotrg (& self) -> INT_EVENT2_IMASK_SRXFIFOTRG_R { INT_EVENT2_IMASK_SRXFIFOTRG_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - Slave Transmit FIFO Trigger"] # [inline (always)] pub fn int_event2_imask_stxfifotrg (& self) -> INT_EVENT2_IMASK_STXFIFOTRG_R { INT_EVENT2_IMASK_STXFIFOTRG_R :: new (((self . bits >> 3) & 1) != 0) } } impl W { # [doc = "Bit 0 - Master Receive FIFO Trigger Trigger when RX FIFO contains &gt;= defined bytes"] # [inline (always)] # [must_use] pub fn int_event2_imask_mrxfifotrg (& mut self) -> INT_EVENT2_IMASK_MRXFIFOTRG_W < INT_EVENT2_IMASK_SPEC , 0 > { INT_EVENT2_IMASK_MRXFIFOTRG_W :: new (self) } # [doc = "Bit 1 - Master Transmit FIFO Trigger Trigger when Transmit FIFO contains &lt;= defined bytes"] # [inline (always)] # [must_use] pub fn int_event2_imask_mtxfifotrg (& mut self) -> INT_EVENT2_IMASK_MTXFIFOTRG_W < INT_EVENT2_IMASK_SPEC , 1 > { INT_EVENT2_IMASK_MTXFIFOTRG_W :: new (self) } # [doc = "Bit 2 - Slave Receive FIFO Trigger"] # [inline (always)] # [must_use] pub fn int_event2_imask_srxfifotrg (& mut self) -> INT_EVENT2_IMASK_SRXFIFOTRG_W < INT_EVENT2_IMASK_SPEC , 2 > { INT_EVENT2_IMASK_SRXFIFOTRG_W :: new (self) } # [doc = "Bit 3 - Slave Transmit FIFO Trigger"] # [inline (always)] # [must_use] pub fn int_event2_imask_stxfifotrg (& mut self) -> INT_EVENT2_IMASK_STXFIFOTRG_W <'_, INT_EVENT2_IMASK_SPEC , 3 > { INT_EVENT2_IMASK_STXFIFOTRG_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Interrupt mask\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_event2_imask::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_event2_imask::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct INT_EVENT2_IMASK_SPEC ; impl crate :: RegisterSpec for INT_EVENT2_IMASK_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`int_event2_imask::R`](R) reader structure"] impl crate :: Readable for INT_EVENT2_IMASK_SPEC { } # [doc = "`write(|w| ..)` method takes [`int_event2_imask::W`](W) writer structure"] impl crate :: Writable for INT_EVENT2_IMASK_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets INT_EVENT2_IMASK to value 0"] impl crate :: Resettable for INT_EVENT2_IMASK_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/spi0/int_event0_imask.rs:1:25415 [INFO] [stdout] | [INFO] [stdout] 1 | ...event0_imask_tx (& mut self) -> INT_EVENT0_IMASK_TX_W < INT_EVENT0_IMASK_SPEC , 4 > { INT_EVENT0_IMASK_TX_W :: new (self) } # [doc = "... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `INT_EVENT0_IMASK` reader"] pub type R = crate :: R < INT_EVENT0_IMASK_SPEC > ; # [doc = "Register `INT_EVENT0_IMASK` writer"] pub type W = crate :: W < INT_EVENT0_IMASK_SPEC > ; # [doc = "Field `INT_EVENT0_IMASK_RXFIFO_OVF` reader - RXFIFO overflow event mask."] pub type INT_EVENT0_IMASK_RXFIFO_OVF_R = crate :: BitReader < INT_EVENT0_IMASK_RXFIFO_OVF_A > ; # [doc = "RXFIFO overflow event mask.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_RXFIFO_OVF_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_RXFIFO_OVF_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_RXFIFO_OVF_SET = 1 , } impl From < INT_EVENT0_IMASK_RXFIFO_OVF_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_RXFIFO_OVF_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_RXFIFO_OVF_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_RXFIFO_OVF_A { match self . bits { false => INT_EVENT0_IMASK_RXFIFO_OVF_A :: INT_EVENT0_IMASK_RXFIFO_OVF_CLR , true => INT_EVENT0_IMASK_RXFIFO_OVF_A :: INT_EVENT0_IMASK_RXFIFO_OVF_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_rxfifo_ovf_clr (& self) -> bool { * self == INT_EVENT0_IMASK_RXFIFO_OVF_A :: INT_EVENT0_IMASK_RXFIFO_OVF_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_rxfifo_ovf_set (& self) -> bool { * self == INT_EVENT0_IMASK_RXFIFO_OVF_A :: INT_EVENT0_IMASK_RXFIFO_OVF_SET } } # [doc = "Field `INT_EVENT0_IMASK_RXFIFO_OVF` writer - RXFIFO overflow event mask."] pub type INT_EVENT0_IMASK_RXFIFO_OVF_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_RXFIFO_OVF_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_RXFIFO_OVF_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_rxfifo_ovf_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXFIFO_OVF_A :: INT_EVENT0_IMASK_RXFIFO_OVF_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_rxfifo_ovf_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXFIFO_OVF_A :: INT_EVENT0_IMASK_RXFIFO_OVF_SET) } } # [doc = "Field `INT_EVENT0_IMASK_PER` reader - Parity error event mask."] pub type INT_EVENT0_IMASK_PER_R = crate :: BitReader < INT_EVENT0_IMASK_PER_A > ; # [doc = "Parity error event mask.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_PER_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_PER_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_PER_SET = 1 , } impl From < INT_EVENT0_IMASK_PER_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_PER_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_PER_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_PER_A { match self . bits { false => INT_EVENT0_IMASK_PER_A :: INT_EVENT0_IMASK_PER_CLR , true => INT_EVENT0_IMASK_PER_A :: INT_EVENT0_IMASK_PER_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_per_clr (& self) -> bool { * self == INT_EVENT0_IMASK_PER_A :: INT_EVENT0_IMASK_PER_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_per_set (& self) -> bool { * self == INT_EVENT0_IMASK_PER_A :: INT_EVENT0_IMASK_PER_SET } } # [doc = "Field `INT_EVENT0_IMASK_PER` writer - Parity error event mask."] pub type INT_EVENT0_IMASK_PER_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_PER_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_PER_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_per_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_PER_A :: INT_EVENT0_IMASK_PER_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_per_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_PER_A :: INT_EVENT0_IMASK_PER_SET) } } # [doc = "Field `INT_EVENT0_IMASK_RTOUT` reader - Enable SPI Receive Time-Out event mask."] pub type INT_EVENT0_IMASK_RTOUT_R = crate :: BitReader < INT_EVENT0_IMASK_RTOUT_A > ; # [doc = "Enable SPI Receive Time-Out event mask.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_RTOUT_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_RTOUT_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_RTOUT_SET = 1 , } impl From < INT_EVENT0_IMASK_RTOUT_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_RTOUT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_RTOUT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_RTOUT_A { match self . bits { false => INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_CLR , true => INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_rtout_clr (& self) -> bool { * self == INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_rtout_set (& self) -> bool { * self == INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_SET } } # [doc = "Field `INT_EVENT0_IMASK_RTOUT` writer - Enable SPI Receive Time-Out event mask."] pub type INT_EVENT0_IMASK_RTOUT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_RTOUT_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_RTOUT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_rtout_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_rtout_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_SET) } } # [doc = "Field `INT_EVENT0_IMASK_RX` reader - Receive FIFO event.This interrupt is set if the selected Receive FIFO level has been reached"] pub type INT_EVENT0_IMASK_RX_R = crate :: BitReader < INT_EVENT0_IMASK_RX_A > ; # [doc = "Receive FIFO event.This interrupt is set if the selected Receive FIFO level has been reached\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_RX_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_RX_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_RX_SET = 1 , } impl From < INT_EVENT0_IMASK_RX_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_RX_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_RX_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_RX_A { match self . bits { false => INT_EVENT0_IMASK_RX_A :: INT_EVENT0_IMASK_RX_CLR , true => INT_EVENT0_IMASK_RX_A :: INT_EVENT0_IMASK_RX_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_rx_clr (& self) -> bool { * self == INT_EVENT0_IMASK_RX_A :: INT_EVENT0_IMASK_RX_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_rx_set (& self) -> bool { * self == INT_EVENT0_IMASK_RX_A :: INT_EVENT0_IMASK_RX_SET } } # [doc = "Field `INT_EVENT0_IMASK_RX` writer - Receive FIFO event.This interrupt is set if the selected Receive FIFO level has been reached"] pub type INT_EVENT0_IMASK_RX_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_RX_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_RX_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_rx_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RX_A :: INT_EVENT0_IMASK_RX_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_rx_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RX_A :: INT_EVENT0_IMASK_RX_SET) } } # [doc = "Field `INT_EVENT0_IMASK_TX` reader - Transmit FIFO event mask."] pub type INT_EVENT0_IMASK_TX_R = crate :: BitReader < INT_EVENT0_IMASK_TX_A > ; # [doc = "Transmit FIFO event mask.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_TX_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_TX_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_TX_SET = 1 , } impl From < INT_EVENT0_IMASK_TX_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_TX_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_TX_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_TX_A { match self . bits { false => INT_EVENT0_IMASK_TX_A :: INT_EVENT0_IMASK_TX_CLR , true => INT_EVENT0_IMASK_TX_A :: INT_EVENT0_IMASK_TX_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_tx_clr (& self) -> bool { * self == INT_EVENT0_IMASK_TX_A :: INT_EVENT0_IMASK_TX_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_tx_set (& self) -> bool { * self == INT_EVENT0_IMASK_TX_A :: INT_EVENT0_IMASK_TX_SET } } # [doc = "Field `INT_EVENT0_IMASK_TX` writer - Transmit FIFO event mask."] pub type INT_EVENT0_IMASK_TX_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_TX_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_TX_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_tx_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_TX_A :: INT_EVENT0_IMASK_TX_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_tx_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_TX_A :: INT_EVENT0_IMASK_TX_SET) } } # [doc = "Field `INT_EVENT0_IMASK_TXEMPTY` reader - Transmit FIFO Empty event mask."] pub type INT_EVENT0_IMASK_TXEMPTY_R = crate :: BitReader < INT_EVENT0_IMASK_TXEMPTY_A > ; # [doc = "Transmit FIFO Empty event mask.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_TXEMPTY_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_TXEMPTY_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_TXEMPTY_SET = 1 , } impl From < INT_EVENT0_IMASK_TXEMPTY_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_TXEMPTY_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_TXEMPTY_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_TXEMPTY_A { match self . bits { false => INT_EVENT0_IMASK_TXEMPTY_A :: INT_EVENT0_IMASK_TXEMPTY_CLR , true => INT_EVENT0_IMASK_TXEMPTY_A :: INT_EVENT0_IMASK_TXEMPTY_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_txempty_clr (& self) -> bool { * self == INT_EVENT0_IMASK_TXEMPTY_A :: INT_EVENT0_IMASK_TXEMPTY_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_txempty_set (& self) -> bool { * self == INT_EVENT0_IMASK_TXEMPTY_A :: INT_EVENT0_IMASK_TXEMPTY_SET } } # [doc = "Field `INT_EVENT0_IMASK_TXEMPTY` writer - Transmit FIFO Empty event mask."] pub type INT_EVENT0_IMASK_TXEMPTY_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_TXEMPTY_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_TXEMPTY_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_txempty_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_TXEMPTY_A :: INT_EVENT0_IMASK_TXEMPTY_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_txempty_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_TXEMPTY_A :: INT_EVENT0_IMASK_TXEMPTY_SET) } } # [doc = "Field `INT_EVENT0_IMASK_IDLE` reader - SPI Idle event mask."] pub type INT_EVENT0_IMASK_IDLE_R = crate :: BitReader < INT_EVENT0_IMASK_IDLE_A > ; # [doc = "SPI Idle event mask.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_IDLE_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_IDLE_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_IDLE_SET = 1 , } impl From < INT_EVENT0_IMASK_IDLE_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_IDLE_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_IDLE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_IDLE_A { match self . bits { false => INT_EVENT0_IMASK_IDLE_A :: INT_EVENT0_IMASK_IDLE_CLR , true => INT_EVENT0_IMASK_IDLE_A :: INT_EVENT0_IMASK_IDLE_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_idle_clr (& self) -> bool { * self == INT_EVENT0_IMASK_IDLE_A :: INT_EVENT0_IMASK_IDLE_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_idle_set (& self) -> bool { * self == INT_EVENT0_IMASK_IDLE_A :: INT_EVENT0_IMASK_IDLE_SET } } # [doc = "Field `INT_EVENT0_IMASK_IDLE` writer - SPI Idle event mask."] pub type INT_EVENT0_IMASK_IDLE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_IDLE_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_IDLE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_idle_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_IDLE_A :: INT_EVENT0_IMASK_IDLE_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_idle_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_IDLE_A :: INT_EVENT0_IMASK_IDLE_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DMA_DONE_RX` reader - DMA Done 1 event for RX event mask."] pub type INT_EVENT0_IMASK_DMA_DONE_RX_R = crate :: BitReader < INT_EVENT0_IMASK_DMA_DONE_RX_A > ; # [doc = "DMA Done 1 event for RX event mask.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DMA_DONE_RX_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DMA_DONE_RX_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DMA_DONE_RX_SET = 1 , } impl From < INT_EVENT0_IMASK_DMA_DONE_RX_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DMA_DONE_RX_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DMA_DONE_RX_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DMA_DONE_RX_A { match self . bits { false => INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_CLR , true => INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dma_done_rx_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dma_done_rx_set (& self) -> bool { * self == INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_SET } } # [doc = "Field `INT_EVENT0_IMASK_DMA_DONE_RX` writer - DMA Done 1 event for RX event mask."] pub type INT_EVENT0_IMASK_DMA_DONE_RX_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DMA_DONE_RX_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DMA_DONE_RX_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dma_done_rx_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dma_done_rx_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DMA_DONE_TX` reader - DMA Done 1 event for TX event mask."] pub type INT_EVENT0_IMASK_DMA_DONE_TX_R = crate :: BitReader < INT_EVENT0_IMASK_DMA_DONE_TX_A > ; # [doc = "DMA Done 1 event for TX event mask.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DMA_DONE_TX_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DMA_DONE_TX_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DMA_DONE_TX_SET = 1 , } impl From < INT_EVENT0_IMASK_DMA_DONE_TX_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DMA_DONE_TX_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DMA_DONE_TX_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DMA_DONE_TX_A { match self . bits { false => INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_CLR , true => INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dma_done_tx_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dma_done_tx_set (& self) -> bool { * self == INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_SET } } # [doc = "Field `INT_EVENT0_IMASK_DMA_DONE_TX` writer - DMA Done 1 event for TX event mask."] pub type INT_EVENT0_IMASK_DMA_DONE_TX_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DMA_DONE_TX_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DMA_DONE_TX_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dma_done_tx_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dma_done_tx_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_SET) } } # [doc = "Field `INT_EVENT0_IMASK_TXFIFO_UNF` reader - TX FIFO underflow interrupt mask"] pub type INT_EVENT0_IMASK_TXFIFO_UNF_R = crate :: BitReader < INT_EVENT0_IMASK_TXFIFO_UNF_A > ; # [doc = "TX FIFO underflow interrupt mask\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_TXFIFO_UNF_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_TXFIFO_UNF_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_TXFIFO_UNF_SET = 1 , } impl From < INT_EVENT0_IMASK_TXFIFO_UNF_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_TXFIFO_UNF_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_TXFIFO_UNF_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_TXFIFO_UNF_A { match self . bits { false => INT_EVENT0_IMASK_TXFIFO_UNF_A :: INT_EVENT0_IMASK_TXFIFO_UNF_CLR , true => INT_EVENT0_IMASK_TXFIFO_UNF_A :: INT_EVENT0_IMASK_TXFIFO_UNF_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_txfifo_unf_clr (& self) -> bool { * self == INT_EVENT0_IMASK_TXFIFO_UNF_A :: INT_EVENT0_IMASK_TXFIFO_UNF_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_txfifo_unf_set (& self) -> bool { * self == INT_EVENT0_IMASK_TXFIFO_UNF_A :: INT_EVENT0_IMASK_TXFIFO_UNF_SET } } # [doc = "Field `INT_EVENT0_IMASK_TXFIFO_UNF` writer - TX FIFO underflow interrupt mask"] pub type INT_EVENT0_IMASK_TXFIFO_UNF_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_TXFIFO_UNF_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_TXFIFO_UNF_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_txfifo_unf_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_TXFIFO_UNF_A :: INT_EVENT0_IMASK_TXFIFO_UNF_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_txfifo_unf_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_TXFIFO_UNF_A :: INT_EVENT0_IMASK_TXFIFO_UNF_SET) } } # [doc = "Field `INT_EVENT0_IMASK_RXFULL` reader - RX FIFO Full Interrupt Mask"] pub type INT_EVENT0_IMASK_RXFULL_R = crate :: BitReader < INT_EVENT0_IMASK_RXFULL_A > ; # [doc = "RX FIFO Full Interrupt Mask\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_RXFULL_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_RXFULL_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_RXFULL_SET = 1 , } impl From < INT_EVENT0_IMASK_RXFULL_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_RXFULL_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_RXFULL_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_RXFULL_A { match self . bits { false => INT_EVENT0_IMASK_RXFULL_A :: INT_EVENT0_IMASK_RXFULL_CLR , true => INT_EVENT0_IMASK_RXFULL_A :: INT_EVENT0_IMASK_RXFULL_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_rxfull_clr (& self) -> bool { * self == INT_EVENT0_IMASK_RXFULL_A :: INT_EVENT0_IMASK_RXFULL_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_rxfull_set (& self) -> bool { * self == INT_EVENT0_IMASK_RXFULL_A :: INT_EVENT0_IMASK_RXFULL_SET } } # [doc = "Field `INT_EVENT0_IMASK_RXFULL` writer - RX FIFO Full Interrupt Mask"] pub type INT_EVENT0_IMASK_RXFULL_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_RXFULL_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_RXFULL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_rxfull_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXFULL_A :: INT_EVENT0_IMASK_RXFULL_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_rxfull_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXFULL_A :: INT_EVENT0_IMASK_RXFULL_SET) } } impl R { # [doc = "Bit 0 - RXFIFO overflow event mask."] # [inline (always)] pub fn int_event0_imask_rxfifo_ovf (& self) -> INT_EVENT0_IMASK_RXFIFO_OVF_R { INT_EVENT0_IMASK_RXFIFO_OVF_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - Parity error event mask."] # [inline (always)] pub fn int_event0_imask_per (& self) -> INT_EVENT0_IMASK_PER_R { INT_EVENT0_IMASK_PER_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - Enable SPI Receive Time-Out event mask."] # [inline (always)] pub fn int_event0_imask_rtout (& self) -> INT_EVENT0_IMASK_RTOUT_R { INT_EVENT0_IMASK_RTOUT_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - Receive FIFO event.This interrupt is set if the selected Receive FIFO level has been reached"] # [inline (always)] pub fn int_event0_imask_rx (& self) -> INT_EVENT0_IMASK_RX_R { INT_EVENT0_IMASK_RX_R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - Transmit FIFO event mask."] # [inline (always)] pub fn int_event0_imask_tx (& self) -> INT_EVENT0_IMASK_TX_R { INT_EVENT0_IMASK_TX_R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - Transmit FIFO Empty event mask."] # [inline (always)] pub fn int_event0_imask_txempty (& self) -> INT_EVENT0_IMASK_TXEMPTY_R { INT_EVENT0_IMASK_TXEMPTY_R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - SPI Idle event mask."] # [inline (always)] pub fn int_event0_imask_idle (& self) -> INT_EVENT0_IMASK_IDLE_R { INT_EVENT0_IMASK_IDLE_R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - DMA Done 1 event for RX event mask."] # [inline (always)] pub fn int_event0_imask_dma_done_rx (& self) -> INT_EVENT0_IMASK_DMA_DONE_RX_R { INT_EVENT0_IMASK_DMA_DONE_RX_R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - DMA Done 1 event for TX event mask."] # [inline (always)] pub fn int_event0_imask_dma_done_tx (& self) -> INT_EVENT0_IMASK_DMA_DONE_TX_R { INT_EVENT0_IMASK_DMA_DONE_TX_R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - TX FIFO underflow interrupt mask"] # [inline (always)] pub fn int_event0_imask_txfifo_unf (& self) -> INT_EVENT0_IMASK_TXFIFO_UNF_R { INT_EVENT0_IMASK_TXFIFO_UNF_R :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - RX FIFO Full Interrupt Mask"] # [inline (always)] pub fn int_event0_imask_rxfull (& self) -> INT_EVENT0_IMASK_RXFULL_R { INT_EVENT0_IMASK_RXFULL_R :: new (((self . bits >> 10) & 1) != 0) } } impl W { # [doc = "Bit 0 - RXFIFO overflow event mask."] # [inline (always)] # [must_use] pub fn int_event0_imask_rxfifo_ovf (& mut self) -> INT_EVENT0_IMASK_RXFIFO_OVF_W < INT_EVENT0_IMASK_SPEC , 0 > { INT_EVENT0_IMASK_RXFIFO_OVF_W :: new (self) } # [doc = "Bit 1 - Parity error event mask."] # [inline (always)] # [must_use] pub fn int_event0_imask_per (& mut self) -> INT_EVENT0_IMASK_PER_W < INT_EVENT0_IMASK_SPEC , 1 > { INT_EVENT0_IMASK_PER_W :: new (self) } # [doc = "Bit 2 - Enable SPI Receive Time-Out event mask."] # [inline (always)] # [must_use] pub fn int_event0_imask_rtout (& mut self) -> INT_EVENT0_IMASK_RTOUT_W < INT_EVENT0_IMASK_SPEC , 2 > { INT_EVENT0_IMASK_RTOUT_W :: new (self) } # [doc = "Bit 3 - Receive FIFO event.This interrupt is set if the selected Receive FIFO level has been reached"] # [inline (always)] # [must_use] pub fn int_event0_imask_rx (& mut self) -> INT_EVENT0_IMASK_RX_W < INT_EVENT0_IMASK_SPEC , 3 > { INT_EVENT0_IMASK_RX_W :: new (self) } # [doc = "Bit 4 - Transmit FIFO event mask."] # [inline (always)] # [must_use] pub fn int_event0_imask_tx (& mut self) -> INT_EVENT0_IMASK_TX_W <'_, INT_EVENT0_IMASK_SPEC , 4 > { INT_EVENT0_IMASK_TX_W :: new (self) } # [doc = "Bit 5 - Transmit FIFO Empty event mask."] # [inline (always)] # [must_use] pub fn int_event0_imask_txempty (& mut self) -> INT_EVENT0_IMASK_TXEMPTY_W < INT_EVENT0_IMASK_SPEC , 5 > { INT_EVENT0_IMASK_TXEMPTY_W :: new (self) } # [doc = "Bit 6 - SPI Idle event mask."] # [inline (always)] # [must_use] pub fn int_event0_imask_idle (& mut self) -> INT_EVENT0_IMASK_IDLE_W < INT_EVENT0_IMASK_SPEC , 6 > { INT_EVENT0_IMASK_IDLE_W :: new (self) } # [doc = "Bit 7 - DMA Done 1 event for RX event mask."] # [inline (always)] # [must_use] pub fn int_event0_imask_dma_done_rx (& mut self) -> INT_EVENT0_IMASK_DMA_DONE_RX_W < INT_EVENT0_IMASK_SPEC , 7 > { INT_EVENT0_IMASK_DMA_DONE_RX_W :: new (self) } # [doc = "Bit 8 - DMA Done 1 event for TX event mask."] # [inline (always)] # [must_use] pub fn int_event0_imask_dma_done_tx (& mut self) -> INT_EVENT0_IMASK_DMA_DONE_TX_W < INT_EVENT0_IMASK_SPEC , 8 > { INT_EVENT0_IMASK_DMA_DONE_TX_W :: new (self) } # [doc = "Bit 9 - TX FIFO underflow interrupt mask"] # [inline (always)] # [must_use] pub fn int_event0_imask_txfifo_unf (& mut self) -> INT_EVENT0_IMASK_TXFIFO_UNF_W < INT_EVENT0_IMASK_SPEC , 9 > { INT_EVENT0_IMASK_TXFIFO_UNF_W :: new (self) } # [doc = "Bit 10 - RX FIFO Full Interrupt Mask"] # [inline (always)] # [must_use] pub fn int_event0_imask_rxfull (& mut self) -> INT_EVENT0_IMASK_RXFULL_W < INT_EVENT0_IMASK_SPEC , 10 > { INT_EVENT0_IMASK_RXFULL_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Interrupt mask\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_event0_imask::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_event0_imask::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct INT_EVENT0_IMASK_SPEC ; impl crate :: RegisterSpec for INT_EVENT0_IMASK_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`int_event0_imask::R`](R) reader structure"] impl crate :: Readable for INT_EVENT0_IMASK_SPEC { } # [doc = "`write(|w| ..)` method takes [`int_event0_imask::W`](W) writer structure"] impl crate :: Writable for INT_EVENT0_IMASK_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets INT_EVENT0_IMASK to value 0"] impl crate :: Resettable for INT_EVENT0_IMASK_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/i2c1/rstctl.rs:1:3243 [INFO] [stdout] | [INFO] [stdout] 1 | ...fn rstctl_resetassert (& mut self) -> RSTCTL_RESETASSERT_W < RSTCTL_SPEC , 0 > { RSTCTL_RESETASSERT_W :: new (self) } # [doc = "Bit 1 ... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `RSTCTL` writer"] pub type W = crate :: W < RSTCTL_SPEC > ; # [doc = "Assert reset to the peripheral\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum RSTCTL_RESETASSERT_AW { # [doc = "0: NOP"] RSTCTL_RESETASSERT_NOP = 0 , # [doc = "1: ASSERT"] RSTCTL_RESETASSERT_ASSERT = 1 , } impl From < RSTCTL_RESETASSERT_AW > for bool { # [inline (always)] fn from (variant : RSTCTL_RESETASSERT_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `RSTCTL_RESETASSERT` writer - Assert reset to the peripheral"] pub type RSTCTL_RESETASSERT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , RSTCTL_RESETASSERT_AW > ; impl < 'a , REG , const O : u8 > RSTCTL_RESETASSERT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NOP"] # [inline (always)] pub fn rstctl_resetassert_nop (self) -> & 'a mut crate :: W < REG > { self . variant (RSTCTL_RESETASSERT_AW :: RSTCTL_RESETASSERT_NOP) } # [doc = "ASSERT"] # [inline (always)] pub fn rstctl_resetassert_assert (self) -> & 'a mut crate :: W < REG > { self . variant (RSTCTL_RESETASSERT_AW :: RSTCTL_RESETASSERT_ASSERT) } } # [doc = "Clear the RESETSTKY bit in the STAT register\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum RSTCTL_RESETSTKYCLR_AW { # [doc = "0: NOP"] RSTCTL_RESETSTKYCLR_NOP = 0 , # [doc = "1: CLR"] RSTCTL_RESETSTKYCLR_CLR = 1 , } impl From < RSTCTL_RESETSTKYCLR_AW > for bool { # [inline (always)] fn from (variant : RSTCTL_RESETSTKYCLR_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `RSTCTL_RESETSTKYCLR` writer - Clear the RESETSTKY bit in the STAT register"] pub type RSTCTL_RESETSTKYCLR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , RSTCTL_RESETSTKYCLR_AW > ; impl < 'a , REG , const O : u8 > RSTCTL_RESETSTKYCLR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NOP"] # [inline (always)] pub fn rstctl_resetstkyclr_nop (self) -> & 'a mut crate :: W < REG > { self . variant (RSTCTL_RESETSTKYCLR_AW :: RSTCTL_RESETSTKYCLR_NOP) } # [doc = "CLR"] # [inline (always)] pub fn rstctl_resetstkyclr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (RSTCTL_RESETSTKYCLR_AW :: RSTCTL_RESETSTKYCLR_CLR) } } # [doc = "Unlock key\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum RSTCTL_KEY_AW { # [doc = "177: _TO_UNLOCK_W_"] RSTCTL_KEY_UNLOCK_W = 177 , } impl From < RSTCTL_KEY_AW > for u8 { # [inline (always)] fn from (variant : RSTCTL_KEY_AW) -> Self { variant as _ } } impl crate :: FieldSpec for RSTCTL_KEY_AW { type Ux = u8 ; } # [doc = "Field `RSTCTL_KEY` writer - Unlock key"] pub type RSTCTL_KEY_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 8 , O , RSTCTL_KEY_AW > ; impl < 'a , REG , const O : u8 > RSTCTL_KEY_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "_TO_UNLOCK_W_"] # [inline (always)] pub fn rstctl_key_unlock_w (self) -> & 'a mut crate :: W < REG > { self . variant (RSTCTL_KEY_AW :: RSTCTL_KEY_UNLOCK_W) } } impl W { # [doc = "Bit 0 - Assert reset to the peripheral"] # [inline (always)] # [must_use] pub fn rstctl_resetassert (& mut self) -> RSTCTL_RESETASSERT_W <'_, RSTCTL_SPEC , 0 > { RSTCTL_RESETASSERT_W :: new (self) } # [doc = "Bit 1 - Clear the RESETSTKY bit in the STAT register"] # [inline (always)] # [must_use] pub fn rstctl_resetstkyclr (& mut self) -> RSTCTL_RESETSTKYCLR_W < RSTCTL_SPEC , 1 > { RSTCTL_RESETSTKYCLR_W :: new (self) } # [doc = "Bits 24:31 - Unlock key"] # [inline (always)] # [must_use] pub fn rstctl_key (& mut self) -> RSTCTL_KEY_W < RSTCTL_SPEC , 24 > { RSTCTL_KEY_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Reset Control\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rstctl::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct RSTCTL_SPEC ; impl crate :: RegisterSpec for RSTCTL_SPEC { type Ux = u32 ; } # [doc = "`write(|w| ..)` method takes [`rstctl::W`](W) writer structure"] impl crate :: Writable for RSTCTL_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets RSTCTL to value 0"] impl crate :: Resettable for RSTCTL_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/gpioa/pwren.rs:1:3131 [INFO] [stdout] | [INFO] [stdout] 1 | ...ust_use] pub fn pwren_key (& mut self) -> PWREN_KEY_W < PWREN_SPEC , 24 > { PWREN_KEY_W :: new (self) } # [doc = r" Writes raw bits to... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `PWREN` reader"] pub type R = crate :: R < PWREN_SPEC > ; # [doc = "Register `PWREN` writer"] pub type W = crate :: W < PWREN_SPEC > ; # [doc = "Field `PWREN_ENABLE` reader - Enable the power"] pub type PWREN_ENABLE_R = crate :: BitReader < PWREN_ENABLE_A > ; # [doc = "Enable the power\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum PWREN_ENABLE_A { # [doc = "0: DISABLE"] PWREN_ENABLE_DISABLE = 0 , # [doc = "1: ENABLE"] PWREN_ENABLE_ENABLE = 1 , } impl From < PWREN_ENABLE_A > for bool { # [inline (always)] fn from (variant : PWREN_ENABLE_A) -> Self { variant as u8 != 0 } } impl PWREN_ENABLE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> PWREN_ENABLE_A { match self . bits { false => PWREN_ENABLE_A :: PWREN_ENABLE_DISABLE , true => PWREN_ENABLE_A :: PWREN_ENABLE_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_pwren_enable_disable (& self) -> bool { * self == PWREN_ENABLE_A :: PWREN_ENABLE_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_pwren_enable_enable (& self) -> bool { * self == PWREN_ENABLE_A :: PWREN_ENABLE_ENABLE } } # [doc = "Field `PWREN_ENABLE` writer - Enable the power"] pub type PWREN_ENABLE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , PWREN_ENABLE_A > ; impl < 'a , REG , const O : u8 > PWREN_ENABLE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn pwren_enable_disable (self) -> & 'a mut crate :: W < REG > { self . variant (PWREN_ENABLE_A :: PWREN_ENABLE_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn pwren_enable_enable (self) -> & 'a mut crate :: W < REG > { self . variant (PWREN_ENABLE_A :: PWREN_ENABLE_ENABLE) } } # [doc = "KEY to allow Power State Change\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum PWREN_KEY_AW { # [doc = "38: _TO_UNLOCK_W_"] PWREN_KEY_UNLOCK_W = 38 , } impl From < PWREN_KEY_AW > for u8 { # [inline (always)] fn from (variant : PWREN_KEY_AW) -> Self { variant as _ } } impl crate :: FieldSpec for PWREN_KEY_AW { type Ux = u8 ; } # [doc = "Field `PWREN_KEY` writer - KEY to allow Power State Change"] pub type PWREN_KEY_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 8 , O , PWREN_KEY_AW > ; impl < 'a , REG , const O : u8 > PWREN_KEY_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "_TO_UNLOCK_W_"] # [inline (always)] pub fn pwren_key_unlock_w (self) -> & 'a mut crate :: W < REG > { self . variant (PWREN_KEY_AW :: PWREN_KEY_UNLOCK_W) } } impl R { # [doc = "Bit 0 - Enable the power"] # [inline (always)] pub fn pwren_enable (& self) -> PWREN_ENABLE_R { PWREN_ENABLE_R :: new ((self . bits & 1) != 0) } } impl W { # [doc = "Bit 0 - Enable the power"] # [inline (always)] # [must_use] pub fn pwren_enable (& mut self) -> PWREN_ENABLE_W < PWREN_SPEC , 0 > { PWREN_ENABLE_W :: new (self) } # [doc = "Bits 24:31 - KEY to allow Power State Change"] # [inline (always)] # [must_use] pub fn pwren_key (& mut self) -> PWREN_KEY_W <'_, PWREN_SPEC , 24 > { PWREN_KEY_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Power enable\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pwren::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pwren::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PWREN_SPEC ; impl crate :: RegisterSpec for PWREN_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`pwren::R`](R) reader structure"] impl crate :: Readable for PWREN_SPEC { } # [doc = "`write(|w| ..)` method takes [`pwren::W`](W) writer structure"] impl crate :: Writable for PWREN_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets PWREN to value 0"] impl crate :: Resettable for PWREN_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/uart0/int_event0_imask.rs:1:40498 [INFO] [stdout] | [INFO] [stdout] 1 | ...t0_imask_rtout (& mut self) -> INT_EVENT0_IMASK_RTOUT_W < INT_EVENT0_IMASK_SPEC , 0 > { INT_EVENT0_IMASK_RTOUT_W :: new (self) } # [do... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `INT_EVENT0_IMASK` reader"] pub type R = crate :: R < INT_EVENT0_IMASK_SPEC > ; # [doc = "Register `INT_EVENT0_IMASK` writer"] pub type W = crate :: W < INT_EVENT0_IMASK_SPEC > ; # [doc = "Field `INT_EVENT0_IMASK_RTOUT` reader - Enable UARTOUT Receive Time-Out Interrupt."] pub type INT_EVENT0_IMASK_RTOUT_R = crate :: BitReader < INT_EVENT0_IMASK_RTOUT_A > ; # [doc = "Enable UARTOUT Receive Time-Out Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_RTOUT_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_RTOUT_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_RTOUT_SET = 1 , } impl From < INT_EVENT0_IMASK_RTOUT_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_RTOUT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_RTOUT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_RTOUT_A { match self . bits { false => INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_CLR , true => INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_rtout_clr (& self) -> bool { * self == INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_rtout_set (& self) -> bool { * self == INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_SET } } # [doc = "Field `INT_EVENT0_IMASK_RTOUT` writer - Enable UARTOUT Receive Time-Out Interrupt."] pub type INT_EVENT0_IMASK_RTOUT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_RTOUT_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_RTOUT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_rtout_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_rtout_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_SET) } } # [doc = "Field `INT_EVENT0_IMASK_FRMERR` reader - Enable UART Framing Error Interrupt."] pub type INT_EVENT0_IMASK_FRMERR_R = crate :: BitReader < INT_EVENT0_IMASK_FRMERR_A > ; # [doc = "Enable UART Framing Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_FRMERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_FRMERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_FRMERR_SET = 1 , } impl From < INT_EVENT0_IMASK_FRMERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_FRMERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_FRMERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_FRMERR_A { match self . bits { false => INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_CLR , true => INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_frmerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_frmerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_FRMERR` writer - Enable UART Framing Error Interrupt."] pub type INT_EVENT0_IMASK_FRMERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_FRMERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_FRMERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_frmerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_frmerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_SET) } } # [doc = "Field `INT_EVENT0_IMASK_PARERR` reader - Enable UART Parity Error Interrupt."] pub type INT_EVENT0_IMASK_PARERR_R = crate :: BitReader < INT_EVENT0_IMASK_PARERR_A > ; # [doc = "Enable UART Parity Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_PARERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_PARERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_PARERR_SET = 1 , } impl From < INT_EVENT0_IMASK_PARERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_PARERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_PARERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_PARERR_A { match self . bits { false => INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_CLR , true => INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_parerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_parerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_PARERR` writer - Enable UART Parity Error Interrupt."] pub type INT_EVENT0_IMASK_PARERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_PARERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_PARERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_parerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_parerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_SET) } } # [doc = "Field `INT_EVENT0_IMASK_BRKERR` reader - Enable UART Break Error Interrupt."] pub type INT_EVENT0_IMASK_BRKERR_R = crate :: BitReader < INT_EVENT0_IMASK_BRKERR_A > ; # [doc = "Enable UART Break Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_BRKERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_BRKERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_BRKERR_SET = 1 , } impl From < INT_EVENT0_IMASK_BRKERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_BRKERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_BRKERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_BRKERR_A { match self . bits { false => INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_CLR , true => INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_brkerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_brkerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_BRKERR` writer - Enable UART Break Error Interrupt."] pub type INT_EVENT0_IMASK_BRKERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_BRKERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_BRKERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_brkerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_brkerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_SET) } } # [doc = "Field `INT_EVENT0_IMASK_OVRERR` reader - Enable UART Receive Overrun Error Interrupt."] pub type INT_EVENT0_IMASK_OVRERR_R = crate :: BitReader < INT_EVENT0_IMASK_OVRERR_A > ; # [doc = "Enable UART Receive Overrun Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_OVRERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_OVRERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_OVRERR_SET = 1 , } impl From < INT_EVENT0_IMASK_OVRERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_OVRERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_OVRERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_OVRERR_A { match self . bits { false => INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_CLR , true => INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_ovrerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_ovrerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_OVRERR` writer - Enable UART Receive Overrun Error Interrupt."] pub type INT_EVENT0_IMASK_OVRERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_OVRERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_OVRERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_ovrerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_ovrerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_SET) } } # [doc = "Field `INT_EVENT0_IMASK_RXNE` reader - Enable Negative Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_IMASK_RXNE_R = crate :: BitReader < INT_EVENT0_IMASK_RXNE_A > ; # [doc = "Enable Negative Edge on UARTxRXD Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_RXNE_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_RXNE_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_RXNE_SET = 1 , } impl From < INT_EVENT0_IMASK_RXNE_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_RXNE_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_RXNE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_RXNE_A { match self . bits { false => INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_CLR , true => INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_rxne_clr (& self) -> bool { * self == INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_rxne_set (& self) -> bool { * self == INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_SET } } # [doc = "Field `INT_EVENT0_IMASK_RXNE` writer - Enable Negative Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_IMASK_RXNE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_RXNE_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_RXNE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_rxne_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_rxne_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_SET) } } # [doc = "Field `INT_EVENT0_IMASK_RXPE` reader - Enable Positive Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_IMASK_RXPE_R = crate :: BitReader < INT_EVENT0_IMASK_RXPE_A > ; # [doc = "Enable Positive Edge on UARTxRXD Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_RXPE_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_RXPE_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_RXPE_SET = 1 , } impl From < INT_EVENT0_IMASK_RXPE_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_RXPE_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_RXPE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_RXPE_A { match self . bits { false => INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_CLR , true => INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_rxpe_clr (& self) -> bool { * self == INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_rxpe_set (& self) -> bool { * self == INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_SET } } # [doc = "Field `INT_EVENT0_IMASK_RXPE` writer - Enable Positive Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_IMASK_RXPE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_RXPE_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_RXPE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_rxpe_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_rxpe_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_SET) } } # [doc = "Field `INT_EVENT0_IMASK_LINC0` reader - Enable LIN Capture 0 / Match Interrupt ."] pub type INT_EVENT0_IMASK_LINC0_R = crate :: BitReader < INT_EVENT0_IMASK_LINC0_A > ; # [doc = "Enable LIN Capture 0 / Match Interrupt .\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_LINC0_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_LINC0_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_LINC0_SET = 1 , } impl From < INT_EVENT0_IMASK_LINC0_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_LINC0_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_LINC0_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_LINC0_A { match self . bits { false => INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_CLR , true => INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_linc0_clr (& self) -> bool { * self == INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_linc0_set (& self) -> bool { * self == INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_SET } } # [doc = "Field `INT_EVENT0_IMASK_LINC0` writer - Enable LIN Capture 0 / Match Interrupt ."] pub type INT_EVENT0_IMASK_LINC0_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_LINC0_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_LINC0_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_linc0_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_linc0_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_SET) } } # [doc = "Field `INT_EVENT0_IMASK_LINC1` reader - Enable LIN Capture 1 Interrupt."] pub type INT_EVENT0_IMASK_LINC1_R = crate :: BitReader < INT_EVENT0_IMASK_LINC1_A > ; # [doc = "Enable LIN Capture 1 Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_LINC1_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_LINC1_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_LINC1_SET = 1 , } impl From < INT_EVENT0_IMASK_LINC1_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_LINC1_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_LINC1_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_LINC1_A { match self . bits { false => INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_CLR , true => INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_linc1_clr (& self) -> bool { * self == INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_linc1_set (& self) -> bool { * self == INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_SET } } # [doc = "Field `INT_EVENT0_IMASK_LINC1` writer - Enable LIN Capture 1 Interrupt."] pub type INT_EVENT0_IMASK_LINC1_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_LINC1_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_LINC1_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_linc1_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_linc1_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_SET) } } # [doc = "Field `INT_EVENT0_IMASK_LINOVF` reader - Enable LIN Hardware Counter Overflow Interrupt."] pub type INT_EVENT0_IMASK_LINOVF_R = crate :: BitReader < INT_EVENT0_IMASK_LINOVF_A > ; # [doc = "Enable LIN Hardware Counter Overflow Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_LINOVF_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_LINOVF_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_LINOVF_SET = 1 , } impl From < INT_EVENT0_IMASK_LINOVF_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_LINOVF_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_LINOVF_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_LINOVF_A { match self . bits { false => INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_CLR , true => INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_linovf_clr (& self) -> bool { * self == INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_linovf_set (& self) -> bool { * self == INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_SET } } # [doc = "Field `INT_EVENT0_IMASK_LINOVF` writer - Enable LIN Hardware Counter Overflow Interrupt."] pub type INT_EVENT0_IMASK_LINOVF_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_LINOVF_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_LINOVF_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_linovf_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_linovf_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_SET) } } # [doc = "Field `INT_EVENT0_IMASK_RXINT` reader - Enable UART Receive Interrupt."] pub type INT_EVENT0_IMASK_RXINT_R = crate :: BitReader < INT_EVENT0_IMASK_RXINT_A > ; # [doc = "Enable UART Receive Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_RXINT_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_RXINT_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_RXINT_SET = 1 , } impl From < INT_EVENT0_IMASK_RXINT_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_RXINT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_RXINT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_RXINT_A { match self . bits { false => INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_CLR , true => INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_rxint_clr (& self) -> bool { * self == INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_rxint_set (& self) -> bool { * self == INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_SET } } # [doc = "Field `INT_EVENT0_IMASK_RXINT` writer - Enable UART Receive Interrupt."] pub type INT_EVENT0_IMASK_RXINT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_RXINT_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_RXINT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_rxint_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_rxint_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_SET) } } # [doc = "Field `INT_EVENT0_IMASK_TXINT` reader - Enable UART Transmit Interrupt."] pub type INT_EVENT0_IMASK_TXINT_R = crate :: BitReader < INT_EVENT0_IMASK_TXINT_A > ; # [doc = "Enable UART Transmit Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_TXINT_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_TXINT_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_TXINT_SET = 1 , } impl From < INT_EVENT0_IMASK_TXINT_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_TXINT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_TXINT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_TXINT_A { match self . bits { false => INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_CLR , true => INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_txint_clr (& self) -> bool { * self == INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_txint_set (& self) -> bool { * self == INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_SET } } # [doc = "Field `INT_EVENT0_IMASK_TXINT` writer - Enable UART Transmit Interrupt."] pub type INT_EVENT0_IMASK_TXINT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_TXINT_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_TXINT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_txint_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_txint_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_SET) } } # [doc = "Field `INT_EVENT0_IMASK_EOT` reader - Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] pub type INT_EVENT0_IMASK_EOT_R = crate :: BitReader < INT_EVENT0_IMASK_EOT_A > ; # [doc = "Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_EOT_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_EOT_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_EOT_SET = 1 , } impl From < INT_EVENT0_IMASK_EOT_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_EOT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_EOT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_EOT_A { match self . bits { false => INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_CLR , true => INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_eot_clr (& self) -> bool { * self == INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_eot_set (& self) -> bool { * self == INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_SET } } # [doc = "Field `INT_EVENT0_IMASK_EOT` writer - Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] pub type INT_EVENT0_IMASK_EOT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_EOT_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_EOT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_eot_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_eot_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_SET) } } # [doc = "Field `INT_EVENT0_IMASK_ADDR_MATCH` reader - Enable Address Match Interrupt."] pub type INT_EVENT0_IMASK_ADDR_MATCH_R = crate :: BitReader < INT_EVENT0_IMASK_ADDR_MATCH_A > ; # [doc = "Enable Address Match Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_ADDR_MATCH_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_ADDR_MATCH_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_ADDR_MATCH_SET = 1 , } impl From < INT_EVENT0_IMASK_ADDR_MATCH_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_ADDR_MATCH_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_ADDR_MATCH_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_ADDR_MATCH_A { match self . bits { false => INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_CLR , true => INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_addr_match_clr (& self) -> bool { * self == INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_addr_match_set (& self) -> bool { * self == INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_SET } } # [doc = "Field `INT_EVENT0_IMASK_ADDR_MATCH` writer - Enable Address Match Interrupt."] pub type INT_EVENT0_IMASK_ADDR_MATCH_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_ADDR_MATCH_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_ADDR_MATCH_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_addr_match_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_addr_match_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_SET) } } # [doc = "Field `INT_EVENT0_IMASK_CTS` reader - Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] pub type INT_EVENT0_IMASK_CTS_R = crate :: BitReader < INT_EVENT0_IMASK_CTS_A > ; # [doc = "Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_CTS_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_CTS_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_CTS_SET = 1 , } impl From < INT_EVENT0_IMASK_CTS_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_CTS_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_CTS_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_CTS_A { match self . bits { false => INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_CLR , true => INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_cts_clr (& self) -> bool { * self == INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_cts_set (& self) -> bool { * self == INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_SET } } # [doc = "Field `INT_EVENT0_IMASK_CTS` writer - Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] pub type INT_EVENT0_IMASK_CTS_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_CTS_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_CTS_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_cts_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_cts_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DMA_DONE_RX` reader - Enable DMA Done on RX Event Channel"] pub type INT_EVENT0_IMASK_DMA_DONE_RX_R = crate :: BitReader < INT_EVENT0_IMASK_DMA_DONE_RX_A > ; # [doc = "Enable DMA Done on RX Event Channel\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DMA_DONE_RX_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DMA_DONE_RX_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DMA_DONE_RX_SET = 1 , } impl From < INT_EVENT0_IMASK_DMA_DONE_RX_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DMA_DONE_RX_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DMA_DONE_RX_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DMA_DONE_RX_A { match self . bits { false => INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_CLR , true => INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dma_done_rx_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dma_done_rx_set (& self) -> bool { * self == INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_SET } } # [doc = "Field `INT_EVENT0_IMASK_DMA_DONE_RX` writer - Enable DMA Done on RX Event Channel"] pub type INT_EVENT0_IMASK_DMA_DONE_RX_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DMA_DONE_RX_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DMA_DONE_RX_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dma_done_rx_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dma_done_rx_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DMA_DONE_TX` reader - Enable DMA Done on TX Event Channel"] pub type INT_EVENT0_IMASK_DMA_DONE_TX_R = crate :: BitReader < INT_EVENT0_IMASK_DMA_DONE_TX_A > ; # [doc = "Enable DMA Done on TX Event Channel\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DMA_DONE_TX_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DMA_DONE_TX_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DMA_DONE_TX_SET = 1 , } impl From < INT_EVENT0_IMASK_DMA_DONE_TX_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DMA_DONE_TX_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DMA_DONE_TX_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DMA_DONE_TX_A { match self . bits { false => INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_CLR , true => INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dma_done_tx_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dma_done_tx_set (& self) -> bool { * self == INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_SET } } # [doc = "Field `INT_EVENT0_IMASK_DMA_DONE_TX` writer - Enable DMA Done on TX Event Channel"] pub type INT_EVENT0_IMASK_DMA_DONE_TX_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DMA_DONE_TX_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DMA_DONE_TX_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dma_done_tx_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dma_done_tx_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_SET) } } # [doc = "Field `INT_EVENT0_IMASK_NERR` reader - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] pub type INT_EVENT0_IMASK_NERR_R = crate :: BitReader < INT_EVENT0_IMASK_NERR_A > ; # [doc = "Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_NERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_NERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_NERR_SET = 1 , } impl From < INT_EVENT0_IMASK_NERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_NERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_NERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_NERR_A { match self . bits { false => INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_CLR , true => INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_nerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_nerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_NERR` writer - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] pub type INT_EVENT0_IMASK_NERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_NERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_NERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_nerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_nerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_SET) } } impl R { # [doc = "Bit 0 - Enable UARTOUT Receive Time-Out Interrupt."] # [inline (always)] pub fn int_event0_imask_rtout (& self) -> INT_EVENT0_IMASK_RTOUT_R { INT_EVENT0_IMASK_RTOUT_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - Enable UART Framing Error Interrupt."] # [inline (always)] pub fn int_event0_imask_frmerr (& self) -> INT_EVENT0_IMASK_FRMERR_R { INT_EVENT0_IMASK_FRMERR_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - Enable UART Parity Error Interrupt."] # [inline (always)] pub fn int_event0_imask_parerr (& self) -> INT_EVENT0_IMASK_PARERR_R { INT_EVENT0_IMASK_PARERR_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - Enable UART Break Error Interrupt."] # [inline (always)] pub fn int_event0_imask_brkerr (& self) -> INT_EVENT0_IMASK_BRKERR_R { INT_EVENT0_IMASK_BRKERR_R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - Enable UART Receive Overrun Error Interrupt."] # [inline (always)] pub fn int_event0_imask_ovrerr (& self) -> INT_EVENT0_IMASK_OVRERR_R { INT_EVENT0_IMASK_OVRERR_R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - Enable Negative Edge on UARTxRXD Interrupt."] # [inline (always)] pub fn int_event0_imask_rxne (& self) -> INT_EVENT0_IMASK_RXNE_R { INT_EVENT0_IMASK_RXNE_R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - Enable Positive Edge on UARTxRXD Interrupt."] # [inline (always)] pub fn int_event0_imask_rxpe (& self) -> INT_EVENT0_IMASK_RXPE_R { INT_EVENT0_IMASK_RXPE_R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - Enable LIN Capture 0 / Match Interrupt ."] # [inline (always)] pub fn int_event0_imask_linc0 (& self) -> INT_EVENT0_IMASK_LINC0_R { INT_EVENT0_IMASK_LINC0_R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - Enable LIN Capture 1 Interrupt."] # [inline (always)] pub fn int_event0_imask_linc1 (& self) -> INT_EVENT0_IMASK_LINC1_R { INT_EVENT0_IMASK_LINC1_R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - Enable LIN Hardware Counter Overflow Interrupt."] # [inline (always)] pub fn int_event0_imask_linovf (& self) -> INT_EVENT0_IMASK_LINOVF_R { INT_EVENT0_IMASK_LINOVF_R :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - Enable UART Receive Interrupt."] # [inline (always)] pub fn int_event0_imask_rxint (& self) -> INT_EVENT0_IMASK_RXINT_R { INT_EVENT0_IMASK_RXINT_R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - Enable UART Transmit Interrupt."] # [inline (always)] pub fn int_event0_imask_txint (& self) -> INT_EVENT0_IMASK_TXINT_R { INT_EVENT0_IMASK_TXINT_R :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] # [inline (always)] pub fn int_event0_imask_eot (& self) -> INT_EVENT0_IMASK_EOT_R { INT_EVENT0_IMASK_EOT_R :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - Enable Address Match Interrupt."] # [inline (always)] pub fn int_event0_imask_addr_match (& self) -> INT_EVENT0_IMASK_ADDR_MATCH_R { INT_EVENT0_IMASK_ADDR_MATCH_R :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 14 - Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] # [inline (always)] pub fn int_event0_imask_cts (& self) -> INT_EVENT0_IMASK_CTS_R { INT_EVENT0_IMASK_CTS_R :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - Enable DMA Done on RX Event Channel"] # [inline (always)] pub fn int_event0_imask_dma_done_rx (& self) -> INT_EVENT0_IMASK_DMA_DONE_RX_R { INT_EVENT0_IMASK_DMA_DONE_RX_R :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bit 16 - Enable DMA Done on TX Event Channel"] # [inline (always)] pub fn int_event0_imask_dma_done_tx (& self) -> INT_EVENT0_IMASK_DMA_DONE_TX_R { INT_EVENT0_IMASK_DMA_DONE_TX_R :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] # [inline (always)] pub fn int_event0_imask_nerr (& self) -> INT_EVENT0_IMASK_NERR_R { INT_EVENT0_IMASK_NERR_R :: new (((self . bits >> 17) & 1) != 0) } } impl W { # [doc = "Bit 0 - Enable UARTOUT Receive Time-Out Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_rtout (& mut self) -> INT_EVENT0_IMASK_RTOUT_W <'_, INT_EVENT0_IMASK_SPEC , 0 > { INT_EVENT0_IMASK_RTOUT_W :: new (self) } # [doc = "Bit 1 - Enable UART Framing Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_frmerr (& mut self) -> INT_EVENT0_IMASK_FRMERR_W < INT_EVENT0_IMASK_SPEC , 1 > { INT_EVENT0_IMASK_FRMERR_W :: new (self) } # [doc = "Bit 2 - Enable UART Parity Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_parerr (& mut self) -> INT_EVENT0_IMASK_PARERR_W < INT_EVENT0_IMASK_SPEC , 2 > { INT_EVENT0_IMASK_PARERR_W :: new (self) } # [doc = "Bit 3 - Enable UART Break Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_brkerr (& mut self) -> INT_EVENT0_IMASK_BRKERR_W < INT_EVENT0_IMASK_SPEC , 3 > { INT_EVENT0_IMASK_BRKERR_W :: new (self) } # [doc = "Bit 4 - Enable UART Receive Overrun Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_ovrerr (& mut self) -> INT_EVENT0_IMASK_OVRERR_W < INT_EVENT0_IMASK_SPEC , 4 > { INT_EVENT0_IMASK_OVRERR_W :: new (self) } # [doc = "Bit 5 - Enable Negative Edge on UARTxRXD Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_rxne (& mut self) -> INT_EVENT0_IMASK_RXNE_W < INT_EVENT0_IMASK_SPEC , 5 > { INT_EVENT0_IMASK_RXNE_W :: new (self) } # [doc = "Bit 6 - Enable Positive Edge on UARTxRXD Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_rxpe (& mut self) -> INT_EVENT0_IMASK_RXPE_W < INT_EVENT0_IMASK_SPEC , 6 > { INT_EVENT0_IMASK_RXPE_W :: new (self) } # [doc = "Bit 7 - Enable LIN Capture 0 / Match Interrupt ."] # [inline (always)] # [must_use] pub fn int_event0_imask_linc0 (& mut self) -> INT_EVENT0_IMASK_LINC0_W < INT_EVENT0_IMASK_SPEC , 7 > { INT_EVENT0_IMASK_LINC0_W :: new (self) } # [doc = "Bit 8 - Enable LIN Capture 1 Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_linc1 (& mut self) -> INT_EVENT0_IMASK_LINC1_W < INT_EVENT0_IMASK_SPEC , 8 > { INT_EVENT0_IMASK_LINC1_W :: new (self) } # [doc = "Bit 9 - Enable LIN Hardware Counter Overflow Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_linovf (& mut self) -> INT_EVENT0_IMASK_LINOVF_W < INT_EVENT0_IMASK_SPEC , 9 > { INT_EVENT0_IMASK_LINOVF_W :: new (self) } # [doc = "Bit 10 - Enable UART Receive Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_rxint (& mut self) -> INT_EVENT0_IMASK_RXINT_W < INT_EVENT0_IMASK_SPEC , 10 > { INT_EVENT0_IMASK_RXINT_W :: new (self) } # [doc = "Bit 11 - Enable UART Transmit Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_txint (& mut self) -> INT_EVENT0_IMASK_TXINT_W < INT_EVENT0_IMASK_SPEC , 11 > { INT_EVENT0_IMASK_TXINT_W :: new (self) } # [doc = "Bit 12 - Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] # [inline (always)] # [must_use] pub fn int_event0_imask_eot (& mut self) -> INT_EVENT0_IMASK_EOT_W < INT_EVENT0_IMASK_SPEC , 12 > { INT_EVENT0_IMASK_EOT_W :: new (self) } # [doc = "Bit 13 - Enable Address Match Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_addr_match (& mut self) -> INT_EVENT0_IMASK_ADDR_MATCH_W < INT_EVENT0_IMASK_SPEC , 13 > { INT_EVENT0_IMASK_ADDR_MATCH_W :: new (self) } # [doc = "Bit 14 - Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] # [inline (always)] # [must_use] pub fn int_event0_imask_cts (& mut self) -> INT_EVENT0_IMASK_CTS_W < INT_EVENT0_IMASK_SPEC , 14 > { INT_EVENT0_IMASK_CTS_W :: new (self) } # [doc = "Bit 15 - Enable DMA Done on RX Event Channel"] # [inline (always)] # [must_use] pub fn int_event0_imask_dma_done_rx (& mut self) -> INT_EVENT0_IMASK_DMA_DONE_RX_W < INT_EVENT0_IMASK_SPEC , 15 > { INT_EVENT0_IMASK_DMA_DONE_RX_W :: new (self) } # [doc = "Bit 16 - Enable DMA Done on TX Event Channel"] # [inline (always)] # [must_use] pub fn int_event0_imask_dma_done_tx (& mut self) -> INT_EVENT0_IMASK_DMA_DONE_TX_W < INT_EVENT0_IMASK_SPEC , 16 > { INT_EVENT0_IMASK_DMA_DONE_TX_W :: new (self) } # [doc = "Bit 17 - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] # [inline (always)] # [must_use] pub fn int_event0_imask_nerr (& mut self) -> INT_EVENT0_IMASK_NERR_W < INT_EVENT0_IMASK_SPEC , 17 > { INT_EVENT0_IMASK_NERR_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Interrupt mask\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_event0_imask::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_event0_imask::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct INT_EVENT0_IMASK_SPEC ; impl crate :: RegisterSpec for INT_EVENT0_IMASK_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`int_event0_imask::R`](R) reader structure"] impl crate :: Readable for INT_EVENT0_IMASK_SPEC { } # [doc = "`write(|w| ..)` method takes [`int_event0_imask::W`](W) writer structure"] impl crate :: Writable for INT_EVENT0_IMASK_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets INT_EVENT0_IMASK to value 0"] impl crate :: Resettable for INT_EVENT0_IMASK_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/uart0/int_event0_imask.rs:1:40733 [INFO] [stdout] | [INFO] [stdout] 1 | ..._imask_frmerr (& mut self) -> INT_EVENT0_IMASK_FRMERR_W < INT_EVENT0_IMASK_SPEC , 1 > { INT_EVENT0_IMASK_FRMERR_W :: new (self) } # [d... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `INT_EVENT0_IMASK` reader"] pub type R = crate :: R < INT_EVENT0_IMASK_SPEC > ; # [doc = "Register `INT_EVENT0_IMASK` writer"] pub type W = crate :: W < INT_EVENT0_IMASK_SPEC > ; # [doc = "Field `INT_EVENT0_IMASK_RTOUT` reader - Enable UARTOUT Receive Time-Out Interrupt."] pub type INT_EVENT0_IMASK_RTOUT_R = crate :: BitReader < INT_EVENT0_IMASK_RTOUT_A > ; # [doc = "Enable UARTOUT Receive Time-Out Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_RTOUT_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_RTOUT_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_RTOUT_SET = 1 , } impl From < INT_EVENT0_IMASK_RTOUT_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_RTOUT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_RTOUT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_RTOUT_A { match self . bits { false => INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_CLR , true => INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_rtout_clr (& self) -> bool { * self == INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_rtout_set (& self) -> bool { * self == INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_SET } } # [doc = "Field `INT_EVENT0_IMASK_RTOUT` writer - Enable UARTOUT Receive Time-Out Interrupt."] pub type INT_EVENT0_IMASK_RTOUT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_RTOUT_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_RTOUT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_rtout_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_rtout_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_SET) } } # [doc = "Field `INT_EVENT0_IMASK_FRMERR` reader - Enable UART Framing Error Interrupt."] pub type INT_EVENT0_IMASK_FRMERR_R = crate :: BitReader < INT_EVENT0_IMASK_FRMERR_A > ; # [doc = "Enable UART Framing Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_FRMERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_FRMERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_FRMERR_SET = 1 , } impl From < INT_EVENT0_IMASK_FRMERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_FRMERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_FRMERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_FRMERR_A { match self . bits { false => INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_CLR , true => INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_frmerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_frmerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_FRMERR` writer - Enable UART Framing Error Interrupt."] pub type INT_EVENT0_IMASK_FRMERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_FRMERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_FRMERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_frmerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_frmerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_SET) } } # [doc = "Field `INT_EVENT0_IMASK_PARERR` reader - Enable UART Parity Error Interrupt."] pub type INT_EVENT0_IMASK_PARERR_R = crate :: BitReader < INT_EVENT0_IMASK_PARERR_A > ; # [doc = "Enable UART Parity Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_PARERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_PARERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_PARERR_SET = 1 , } impl From < INT_EVENT0_IMASK_PARERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_PARERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_PARERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_PARERR_A { match self . bits { false => INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_CLR , true => INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_parerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_parerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_PARERR` writer - Enable UART Parity Error Interrupt."] pub type INT_EVENT0_IMASK_PARERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_PARERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_PARERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_parerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_parerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_SET) } } # [doc = "Field `INT_EVENT0_IMASK_BRKERR` reader - Enable UART Break Error Interrupt."] pub type INT_EVENT0_IMASK_BRKERR_R = crate :: BitReader < INT_EVENT0_IMASK_BRKERR_A > ; # [doc = "Enable UART Break Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_BRKERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_BRKERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_BRKERR_SET = 1 , } impl From < INT_EVENT0_IMASK_BRKERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_BRKERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_BRKERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_BRKERR_A { match self . bits { false => INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_CLR , true => INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_brkerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_brkerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_BRKERR` writer - Enable UART Break Error Interrupt."] pub type INT_EVENT0_IMASK_BRKERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_BRKERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_BRKERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_brkerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_brkerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_SET) } } # [doc = "Field `INT_EVENT0_IMASK_OVRERR` reader - Enable UART Receive Overrun Error Interrupt."] pub type INT_EVENT0_IMASK_OVRERR_R = crate :: BitReader < INT_EVENT0_IMASK_OVRERR_A > ; # [doc = "Enable UART Receive Overrun Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_OVRERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_OVRERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_OVRERR_SET = 1 , } impl From < INT_EVENT0_IMASK_OVRERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_OVRERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_OVRERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_OVRERR_A { match self . bits { false => INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_CLR , true => INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_ovrerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_ovrerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_OVRERR` writer - Enable UART Receive Overrun Error Interrupt."] pub type INT_EVENT0_IMASK_OVRERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_OVRERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_OVRERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_ovrerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_ovrerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_SET) } } # [doc = "Field `INT_EVENT0_IMASK_RXNE` reader - Enable Negative Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_IMASK_RXNE_R = crate :: BitReader < INT_EVENT0_IMASK_RXNE_A > ; # [doc = "Enable Negative Edge on UARTxRXD Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_RXNE_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_RXNE_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_RXNE_SET = 1 , } impl From < INT_EVENT0_IMASK_RXNE_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_RXNE_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_RXNE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_RXNE_A { match self . bits { false => INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_CLR , true => INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_rxne_clr (& self) -> bool { * self == INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_rxne_set (& self) -> bool { * self == INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_SET } } # [doc = "Field `INT_EVENT0_IMASK_RXNE` writer - Enable Negative Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_IMASK_RXNE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_RXNE_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_RXNE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_rxne_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_rxne_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_SET) } } # [doc = "Field `INT_EVENT0_IMASK_RXPE` reader - Enable Positive Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_IMASK_RXPE_R = crate :: BitReader < INT_EVENT0_IMASK_RXPE_A > ; # [doc = "Enable Positive Edge on UARTxRXD Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_RXPE_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_RXPE_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_RXPE_SET = 1 , } impl From < INT_EVENT0_IMASK_RXPE_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_RXPE_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_RXPE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_RXPE_A { match self . bits { false => INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_CLR , true => INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_rxpe_clr (& self) -> bool { * self == INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_rxpe_set (& self) -> bool { * self == INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_SET } } # [doc = "Field `INT_EVENT0_IMASK_RXPE` writer - Enable Positive Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_IMASK_RXPE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_RXPE_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_RXPE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_rxpe_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_rxpe_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_SET) } } # [doc = "Field `INT_EVENT0_IMASK_LINC0` reader - Enable LIN Capture 0 / Match Interrupt ."] pub type INT_EVENT0_IMASK_LINC0_R = crate :: BitReader < INT_EVENT0_IMASK_LINC0_A > ; # [doc = "Enable LIN Capture 0 / Match Interrupt .\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_LINC0_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_LINC0_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_LINC0_SET = 1 , } impl From < INT_EVENT0_IMASK_LINC0_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_LINC0_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_LINC0_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_LINC0_A { match self . bits { false => INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_CLR , true => INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_linc0_clr (& self) -> bool { * self == INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_linc0_set (& self) -> bool { * self == INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_SET } } # [doc = "Field `INT_EVENT0_IMASK_LINC0` writer - Enable LIN Capture 0 / Match Interrupt ."] pub type INT_EVENT0_IMASK_LINC0_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_LINC0_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_LINC0_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_linc0_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_linc0_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_SET) } } # [doc = "Field `INT_EVENT0_IMASK_LINC1` reader - Enable LIN Capture 1 Interrupt."] pub type INT_EVENT0_IMASK_LINC1_R = crate :: BitReader < INT_EVENT0_IMASK_LINC1_A > ; # [doc = "Enable LIN Capture 1 Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_LINC1_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_LINC1_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_LINC1_SET = 1 , } impl From < INT_EVENT0_IMASK_LINC1_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_LINC1_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_LINC1_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_LINC1_A { match self . bits { false => INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_CLR , true => INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_linc1_clr (& self) -> bool { * self == INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_linc1_set (& self) -> bool { * self == INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_SET } } # [doc = "Field `INT_EVENT0_IMASK_LINC1` writer - Enable LIN Capture 1 Interrupt."] pub type INT_EVENT0_IMASK_LINC1_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_LINC1_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_LINC1_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_linc1_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_linc1_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_SET) } } # [doc = "Field `INT_EVENT0_IMASK_LINOVF` reader - Enable LIN Hardware Counter Overflow Interrupt."] pub type INT_EVENT0_IMASK_LINOVF_R = crate :: BitReader < INT_EVENT0_IMASK_LINOVF_A > ; # [doc = "Enable LIN Hardware Counter Overflow Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_LINOVF_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_LINOVF_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_LINOVF_SET = 1 , } impl From < INT_EVENT0_IMASK_LINOVF_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_LINOVF_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_LINOVF_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_LINOVF_A { match self . bits { false => INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_CLR , true => INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_linovf_clr (& self) -> bool { * self == INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_linovf_set (& self) -> bool { * self == INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_SET } } # [doc = "Field `INT_EVENT0_IMASK_LINOVF` writer - Enable LIN Hardware Counter Overflow Interrupt."] pub type INT_EVENT0_IMASK_LINOVF_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_LINOVF_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_LINOVF_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_linovf_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_linovf_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_SET) } } # [doc = "Field `INT_EVENT0_IMASK_RXINT` reader - Enable UART Receive Interrupt."] pub type INT_EVENT0_IMASK_RXINT_R = crate :: BitReader < INT_EVENT0_IMASK_RXINT_A > ; # [doc = "Enable UART Receive Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_RXINT_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_RXINT_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_RXINT_SET = 1 , } impl From < INT_EVENT0_IMASK_RXINT_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_RXINT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_RXINT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_RXINT_A { match self . bits { false => INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_CLR , true => INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_rxint_clr (& self) -> bool { * self == INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_rxint_set (& self) -> bool { * self == INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_SET } } # [doc = "Field `INT_EVENT0_IMASK_RXINT` writer - Enable UART Receive Interrupt."] pub type INT_EVENT0_IMASK_RXINT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_RXINT_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_RXINT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_rxint_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_rxint_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_SET) } } # [doc = "Field `INT_EVENT0_IMASK_TXINT` reader - Enable UART Transmit Interrupt."] pub type INT_EVENT0_IMASK_TXINT_R = crate :: BitReader < INT_EVENT0_IMASK_TXINT_A > ; # [doc = "Enable UART Transmit Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_TXINT_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_TXINT_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_TXINT_SET = 1 , } impl From < INT_EVENT0_IMASK_TXINT_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_TXINT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_TXINT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_TXINT_A { match self . bits { false => INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_CLR , true => INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_txint_clr (& self) -> bool { * self == INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_txint_set (& self) -> bool { * self == INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_SET } } # [doc = "Field `INT_EVENT0_IMASK_TXINT` writer - Enable UART Transmit Interrupt."] pub type INT_EVENT0_IMASK_TXINT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_TXINT_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_TXINT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_txint_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_txint_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_SET) } } # [doc = "Field `INT_EVENT0_IMASK_EOT` reader - Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] pub type INT_EVENT0_IMASK_EOT_R = crate :: BitReader < INT_EVENT0_IMASK_EOT_A > ; # [doc = "Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_EOT_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_EOT_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_EOT_SET = 1 , } impl From < INT_EVENT0_IMASK_EOT_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_EOT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_EOT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_EOT_A { match self . bits { false => INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_CLR , true => INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_eot_clr (& self) -> bool { * self == INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_eot_set (& self) -> bool { * self == INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_SET } } # [doc = "Field `INT_EVENT0_IMASK_EOT` writer - Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] pub type INT_EVENT0_IMASK_EOT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_EOT_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_EOT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_eot_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_eot_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_SET) } } # [doc = "Field `INT_EVENT0_IMASK_ADDR_MATCH` reader - Enable Address Match Interrupt."] pub type INT_EVENT0_IMASK_ADDR_MATCH_R = crate :: BitReader < INT_EVENT0_IMASK_ADDR_MATCH_A > ; # [doc = "Enable Address Match Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_ADDR_MATCH_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_ADDR_MATCH_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_ADDR_MATCH_SET = 1 , } impl From < INT_EVENT0_IMASK_ADDR_MATCH_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_ADDR_MATCH_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_ADDR_MATCH_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_ADDR_MATCH_A { match self . bits { false => INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_CLR , true => INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_addr_match_clr (& self) -> bool { * self == INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_addr_match_set (& self) -> bool { * self == INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_SET } } # [doc = "Field `INT_EVENT0_IMASK_ADDR_MATCH` writer - Enable Address Match Interrupt."] pub type INT_EVENT0_IMASK_ADDR_MATCH_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_ADDR_MATCH_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_ADDR_MATCH_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_addr_match_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_addr_match_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_SET) } } # [doc = "Field `INT_EVENT0_IMASK_CTS` reader - Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] pub type INT_EVENT0_IMASK_CTS_R = crate :: BitReader < INT_EVENT0_IMASK_CTS_A > ; # [doc = "Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_CTS_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_CTS_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_CTS_SET = 1 , } impl From < INT_EVENT0_IMASK_CTS_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_CTS_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_CTS_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_CTS_A { match self . bits { false => INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_CLR , true => INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_cts_clr (& self) -> bool { * self == INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_cts_set (& self) -> bool { * self == INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_SET } } # [doc = "Field `INT_EVENT0_IMASK_CTS` writer - Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] pub type INT_EVENT0_IMASK_CTS_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_CTS_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_CTS_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_cts_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_cts_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DMA_DONE_RX` reader - Enable DMA Done on RX Event Channel"] pub type INT_EVENT0_IMASK_DMA_DONE_RX_R = crate :: BitReader < INT_EVENT0_IMASK_DMA_DONE_RX_A > ; # [doc = "Enable DMA Done on RX Event Channel\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DMA_DONE_RX_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DMA_DONE_RX_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DMA_DONE_RX_SET = 1 , } impl From < INT_EVENT0_IMASK_DMA_DONE_RX_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DMA_DONE_RX_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DMA_DONE_RX_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DMA_DONE_RX_A { match self . bits { false => INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_CLR , true => INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dma_done_rx_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dma_done_rx_set (& self) -> bool { * self == INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_SET } } # [doc = "Field `INT_EVENT0_IMASK_DMA_DONE_RX` writer - Enable DMA Done on RX Event Channel"] pub type INT_EVENT0_IMASK_DMA_DONE_RX_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DMA_DONE_RX_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DMA_DONE_RX_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dma_done_rx_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dma_done_rx_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DMA_DONE_TX` reader - Enable DMA Done on TX Event Channel"] pub type INT_EVENT0_IMASK_DMA_DONE_TX_R = crate :: BitReader < INT_EVENT0_IMASK_DMA_DONE_TX_A > ; # [doc = "Enable DMA Done on TX Event Channel\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DMA_DONE_TX_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DMA_DONE_TX_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DMA_DONE_TX_SET = 1 , } impl From < INT_EVENT0_IMASK_DMA_DONE_TX_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DMA_DONE_TX_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DMA_DONE_TX_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DMA_DONE_TX_A { match self . bits { false => INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_CLR , true => INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dma_done_tx_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dma_done_tx_set (& self) -> bool { * self == INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_SET } } # [doc = "Field `INT_EVENT0_IMASK_DMA_DONE_TX` writer - Enable DMA Done on TX Event Channel"] pub type INT_EVENT0_IMASK_DMA_DONE_TX_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DMA_DONE_TX_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DMA_DONE_TX_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dma_done_tx_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dma_done_tx_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_SET) } } # [doc = "Field `INT_EVENT0_IMASK_NERR` reader - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] pub type INT_EVENT0_IMASK_NERR_R = crate :: BitReader < INT_EVENT0_IMASK_NERR_A > ; # [doc = "Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_NERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_NERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_NERR_SET = 1 , } impl From < INT_EVENT0_IMASK_NERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_NERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_NERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_NERR_A { match self . bits { false => INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_CLR , true => INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_nerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_nerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_NERR` writer - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] pub type INT_EVENT0_IMASK_NERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_NERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_NERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_nerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_nerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_SET) } } impl R { # [doc = "Bit 0 - Enable UARTOUT Receive Time-Out Interrupt."] # [inline (always)] pub fn int_event0_imask_rtout (& self) -> INT_EVENT0_IMASK_RTOUT_R { INT_EVENT0_IMASK_RTOUT_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - Enable UART Framing Error Interrupt."] # [inline (always)] pub fn int_event0_imask_frmerr (& self) -> INT_EVENT0_IMASK_FRMERR_R { INT_EVENT0_IMASK_FRMERR_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - Enable UART Parity Error Interrupt."] # [inline (always)] pub fn int_event0_imask_parerr (& self) -> INT_EVENT0_IMASK_PARERR_R { INT_EVENT0_IMASK_PARERR_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - Enable UART Break Error Interrupt."] # [inline (always)] pub fn int_event0_imask_brkerr (& self) -> INT_EVENT0_IMASK_BRKERR_R { INT_EVENT0_IMASK_BRKERR_R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - Enable UART Receive Overrun Error Interrupt."] # [inline (always)] pub fn int_event0_imask_ovrerr (& self) -> INT_EVENT0_IMASK_OVRERR_R { INT_EVENT0_IMASK_OVRERR_R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - Enable Negative Edge on UARTxRXD Interrupt."] # [inline (always)] pub fn int_event0_imask_rxne (& self) -> INT_EVENT0_IMASK_RXNE_R { INT_EVENT0_IMASK_RXNE_R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - Enable Positive Edge on UARTxRXD Interrupt."] # [inline (always)] pub fn int_event0_imask_rxpe (& self) -> INT_EVENT0_IMASK_RXPE_R { INT_EVENT0_IMASK_RXPE_R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - Enable LIN Capture 0 / Match Interrupt ."] # [inline (always)] pub fn int_event0_imask_linc0 (& self) -> INT_EVENT0_IMASK_LINC0_R { INT_EVENT0_IMASK_LINC0_R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - Enable LIN Capture 1 Interrupt."] # [inline (always)] pub fn int_event0_imask_linc1 (& self) -> INT_EVENT0_IMASK_LINC1_R { INT_EVENT0_IMASK_LINC1_R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - Enable LIN Hardware Counter Overflow Interrupt."] # [inline (always)] pub fn int_event0_imask_linovf (& self) -> INT_EVENT0_IMASK_LINOVF_R { INT_EVENT0_IMASK_LINOVF_R :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - Enable UART Receive Interrupt."] # [inline (always)] pub fn int_event0_imask_rxint (& self) -> INT_EVENT0_IMASK_RXINT_R { INT_EVENT0_IMASK_RXINT_R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - Enable UART Transmit Interrupt."] # [inline (always)] pub fn int_event0_imask_txint (& self) -> INT_EVENT0_IMASK_TXINT_R { INT_EVENT0_IMASK_TXINT_R :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] # [inline (always)] pub fn int_event0_imask_eot (& self) -> INT_EVENT0_IMASK_EOT_R { INT_EVENT0_IMASK_EOT_R :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - Enable Address Match Interrupt."] # [inline (always)] pub fn int_event0_imask_addr_match (& self) -> INT_EVENT0_IMASK_ADDR_MATCH_R { INT_EVENT0_IMASK_ADDR_MATCH_R :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 14 - Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] # [inline (always)] pub fn int_event0_imask_cts (& self) -> INT_EVENT0_IMASK_CTS_R { INT_EVENT0_IMASK_CTS_R :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - Enable DMA Done on RX Event Channel"] # [inline (always)] pub fn int_event0_imask_dma_done_rx (& self) -> INT_EVENT0_IMASK_DMA_DONE_RX_R { INT_EVENT0_IMASK_DMA_DONE_RX_R :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bit 16 - Enable DMA Done on TX Event Channel"] # [inline (always)] pub fn int_event0_imask_dma_done_tx (& self) -> INT_EVENT0_IMASK_DMA_DONE_TX_R { INT_EVENT0_IMASK_DMA_DONE_TX_R :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] # [inline (always)] pub fn int_event0_imask_nerr (& self) -> INT_EVENT0_IMASK_NERR_R { INT_EVENT0_IMASK_NERR_R :: new (((self . bits >> 17) & 1) != 0) } } impl W { # [doc = "Bit 0 - Enable UARTOUT Receive Time-Out Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_rtout (& mut self) -> INT_EVENT0_IMASK_RTOUT_W < INT_EVENT0_IMASK_SPEC , 0 > { INT_EVENT0_IMASK_RTOUT_W :: new (self) } # [doc = "Bit 1 - Enable UART Framing Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_frmerr (& mut self) -> INT_EVENT0_IMASK_FRMERR_W <'_, INT_EVENT0_IMASK_SPEC , 1 > { INT_EVENT0_IMASK_FRMERR_W :: new (self) } # [doc = "Bit 2 - Enable UART Parity Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_parerr (& mut self) -> INT_EVENT0_IMASK_PARERR_W < INT_EVENT0_IMASK_SPEC , 2 > { INT_EVENT0_IMASK_PARERR_W :: new (self) } # [doc = "Bit 3 - Enable UART Break Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_brkerr (& mut self) -> INT_EVENT0_IMASK_BRKERR_W < INT_EVENT0_IMASK_SPEC , 3 > { INT_EVENT0_IMASK_BRKERR_W :: new (self) } # [doc = "Bit 4 - Enable UART Receive Overrun Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_ovrerr (& mut self) -> INT_EVENT0_IMASK_OVRERR_W < INT_EVENT0_IMASK_SPEC , 4 > { INT_EVENT0_IMASK_OVRERR_W :: new (self) } # [doc = "Bit 5 - Enable Negative Edge on UARTxRXD Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_rxne (& mut self) -> INT_EVENT0_IMASK_RXNE_W < INT_EVENT0_IMASK_SPEC , 5 > { INT_EVENT0_IMASK_RXNE_W :: new (self) } # [doc = "Bit 6 - Enable Positive Edge on UARTxRXD Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_rxpe (& mut self) -> INT_EVENT0_IMASK_RXPE_W < INT_EVENT0_IMASK_SPEC , 6 > { INT_EVENT0_IMASK_RXPE_W :: new (self) } # [doc = "Bit 7 - Enable LIN Capture 0 / Match Interrupt ."] # [inline (always)] # [must_use] pub fn int_event0_imask_linc0 (& mut self) -> INT_EVENT0_IMASK_LINC0_W < INT_EVENT0_IMASK_SPEC , 7 > { INT_EVENT0_IMASK_LINC0_W :: new (self) } # [doc = "Bit 8 - Enable LIN Capture 1 Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_linc1 (& mut self) -> INT_EVENT0_IMASK_LINC1_W < INT_EVENT0_IMASK_SPEC , 8 > { INT_EVENT0_IMASK_LINC1_W :: new (self) } # [doc = "Bit 9 - Enable LIN Hardware Counter Overflow Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_linovf (& mut self) -> INT_EVENT0_IMASK_LINOVF_W < INT_EVENT0_IMASK_SPEC , 9 > { INT_EVENT0_IMASK_LINOVF_W :: new (self) } # [doc = "Bit 10 - Enable UART Receive Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_rxint (& mut self) -> INT_EVENT0_IMASK_RXINT_W < INT_EVENT0_IMASK_SPEC , 10 > { INT_EVENT0_IMASK_RXINT_W :: new (self) } # [doc = "Bit 11 - Enable UART Transmit Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_txint (& mut self) -> INT_EVENT0_IMASK_TXINT_W < INT_EVENT0_IMASK_SPEC , 11 > { INT_EVENT0_IMASK_TXINT_W :: new (self) } # [doc = "Bit 12 - Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] # [inline (always)] # [must_use] pub fn int_event0_imask_eot (& mut self) -> INT_EVENT0_IMASK_EOT_W < INT_EVENT0_IMASK_SPEC , 12 > { INT_EVENT0_IMASK_EOT_W :: new (self) } # [doc = "Bit 13 - Enable Address Match Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_addr_match (& mut self) -> INT_EVENT0_IMASK_ADDR_MATCH_W < INT_EVENT0_IMASK_SPEC , 13 > { INT_EVENT0_IMASK_ADDR_MATCH_W :: new (self) } # [doc = "Bit 14 - Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] # [inline (always)] # [must_use] pub fn int_event0_imask_cts (& mut self) -> INT_EVENT0_IMASK_CTS_W < INT_EVENT0_IMASK_SPEC , 14 > { INT_EVENT0_IMASK_CTS_W :: new (self) } # [doc = "Bit 15 - Enable DMA Done on RX Event Channel"] # [inline (always)] # [must_use] pub fn int_event0_imask_dma_done_rx (& mut self) -> INT_EVENT0_IMASK_DMA_DONE_RX_W < INT_EVENT0_IMASK_SPEC , 15 > { INT_EVENT0_IMASK_DMA_DONE_RX_W :: new (self) } # [doc = "Bit 16 - Enable DMA Done on TX Event Channel"] # [inline (always)] # [must_use] pub fn int_event0_imask_dma_done_tx (& mut self) -> INT_EVENT0_IMASK_DMA_DONE_TX_W < INT_EVENT0_IMASK_SPEC , 16 > { INT_EVENT0_IMASK_DMA_DONE_TX_W :: new (self) } # [doc = "Bit 17 - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] # [inline (always)] # [must_use] pub fn int_event0_imask_nerr (& mut self) -> INT_EVENT0_IMASK_NERR_W < INT_EVENT0_IMASK_SPEC , 17 > { INT_EVENT0_IMASK_NERR_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Interrupt mask\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_event0_imask::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_event0_imask::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct INT_EVENT0_IMASK_SPEC ; impl crate :: RegisterSpec for INT_EVENT0_IMASK_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`int_event0_imask::R`](R) reader structure"] impl crate :: Readable for INT_EVENT0_IMASK_SPEC { } # [doc = "`write(|w| ..)` method takes [`int_event0_imask::W`](W) writer structure"] impl crate :: Writable for INT_EVENT0_IMASK_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets INT_EVENT0_IMASK to value 0"] impl crate :: Resettable for INT_EVENT0_IMASK_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/opa0/cfg.rs:1:16718 [INFO] [stdout] | [INFO] [stdout] 1 | ...ust_use] pub fn cfg_outpin (& mut self) -> CFG_OUTPIN_W < CFG_SPEC , 2 > { CFG_OUTPIN_W :: new (self) } # [doc = "Bits 3:6 - Positive ... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `CFG` reader"] pub type R = crate :: R < CFG_SPEC > ; # [doc = "Register `CFG` writer"] pub type W = crate :: W < CFG_SPEC > ; # [doc = "Field `CFG_CHOP` reader - Chopping enable."] pub type CFG_CHOP_R = crate :: FieldReader < CFG_CHOP_A > ; # [doc = "Chopping enable.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum CFG_CHOP_A { # [doc = "0: OFF"] CFG_CHOP_OFF = 0 , # [doc = "1: ON"] CFG_CHOP_ON = 1 , # [doc = "2: AVGON"] CFG_CHOP_AVGON = 2 , } impl From < CFG_CHOP_A > for u8 { # [inline (always)] fn from (variant : CFG_CHOP_A) -> Self { variant as _ } } impl crate :: FieldSpec for CFG_CHOP_A { type Ux = u8 ; } impl CFG_CHOP_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < CFG_CHOP_A > { match self . bits { 0 => Some (CFG_CHOP_A :: CFG_CHOP_OFF) , 1 => Some (CFG_CHOP_A :: CFG_CHOP_ON) , 2 => Some (CFG_CHOP_A :: CFG_CHOP_AVGON) , _ => None , } } # [doc = "OFF"] # [inline (always)] pub fn is_cfg_chop_off (& self) -> bool { * self == CFG_CHOP_A :: CFG_CHOP_OFF } # [doc = "ON"] # [inline (always)] pub fn is_cfg_chop_on (& self) -> bool { * self == CFG_CHOP_A :: CFG_CHOP_ON } # [doc = "AVGON"] # [inline (always)] pub fn is_cfg_chop_avgon (& self) -> bool { * self == CFG_CHOP_A :: CFG_CHOP_AVGON } } # [doc = "Field `CFG_CHOP` writer - Chopping enable."] pub type CFG_CHOP_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 2 , O , CFG_CHOP_A > ; impl < 'a , REG , const O : u8 > CFG_CHOP_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "OFF"] # [inline (always)] pub fn cfg_chop_off (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_CHOP_A :: CFG_CHOP_OFF) } # [doc = "ON"] # [inline (always)] pub fn cfg_chop_on (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_CHOP_A :: CFG_CHOP_ON) } # [doc = "AVGON"] # [inline (always)] pub fn cfg_chop_avgon (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_CHOP_A :: CFG_CHOP_AVGON) } } # [doc = "Field `CFG_OUTPIN` reader - Enable output pin"] pub type CFG_OUTPIN_R = crate :: BitReader < CFG_OUTPIN_A > ; # [doc = "Enable output pin\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CFG_OUTPIN_A { # [doc = "0: DISABLED"] CFG_OUTPIN_DISABLED = 0 , # [doc = "1: ENABLED"] CFG_OUTPIN_ENABLED = 1 , } impl From < CFG_OUTPIN_A > for bool { # [inline (always)] fn from (variant : CFG_OUTPIN_A) -> Self { variant as u8 != 0 } } impl CFG_OUTPIN_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CFG_OUTPIN_A { match self . bits { false => CFG_OUTPIN_A :: CFG_OUTPIN_DISABLED , true => CFG_OUTPIN_A :: CFG_OUTPIN_ENABLED , } } # [doc = "DISABLED"] # [inline (always)] pub fn is_cfg_outpin_disabled (& self) -> bool { * self == CFG_OUTPIN_A :: CFG_OUTPIN_DISABLED } # [doc = "ENABLED"] # [inline (always)] pub fn is_cfg_outpin_enabled (& self) -> bool { * self == CFG_OUTPIN_A :: CFG_OUTPIN_ENABLED } } # [doc = "Field `CFG_OUTPIN` writer - Enable output pin"] pub type CFG_OUTPIN_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CFG_OUTPIN_A > ; impl < 'a , REG , const O : u8 > CFG_OUTPIN_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLED"] # [inline (always)] pub fn cfg_outpin_disabled (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_OUTPIN_A :: CFG_OUTPIN_DISABLED) } # [doc = "ENABLED"] # [inline (always)] pub fn cfg_outpin_enabled (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_OUTPIN_A :: CFG_OUTPIN_ENABLED) } } # [doc = "Field `CFG_PSEL` reader - Positive OA input selection. Please refer to the device specific datasheet for exact channels available."] pub type CFG_PSEL_R = crate :: FieldReader < CFG_PSEL_A > ; # [doc = "Positive OA input selection. Please refer to the device specific datasheet for exact channels available.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum CFG_PSEL_A { # [doc = "0: NC"] CFG_PSEL_NC = 0 , # [doc = "1: EXTPIN0"] CFG_PSEL_EXTPIN0 = 1 , # [doc = "2: EXTPIN1"] CFG_PSEL_EXTPIN1 = 2 , # [doc = "3: DAC12OUT"] CFG_PSEL_DAC12OUT = 3 , # [doc = "4: DAC8OUT"] CFG_PSEL_DAC8OUT = 4 , # [doc = "5: VREF"] CFG_PSEL_VREF = 5 , # [doc = "6: OANM1RTOP"] CFG_PSEL_OANM1RTOP = 6 , # [doc = "7: GPAMP_OUT_INT"] CFG_PSEL_GPAMP_OUT_INT = 7 , # [doc = "8: VSS"] CFG_PSEL_VSS = 8 , } impl From < CFG_PSEL_A > for u8 { # [inline (always)] fn from (variant : CFG_PSEL_A) -> Self { variant as _ } } impl crate :: FieldSpec for CFG_PSEL_A { type Ux = u8 ; } impl CFG_PSEL_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < CFG_PSEL_A > { match self . bits { 0 => Some (CFG_PSEL_A :: CFG_PSEL_NC) , 1 => Some (CFG_PSEL_A :: CFG_PSEL_EXTPIN0) , 2 => Some (CFG_PSEL_A :: CFG_PSEL_EXTPIN1) , 3 => Some (CFG_PSEL_A :: CFG_PSEL_DAC12OUT) , 4 => Some (CFG_PSEL_A :: CFG_PSEL_DAC8OUT) , 5 => Some (CFG_PSEL_A :: CFG_PSEL_VREF) , 6 => Some (CFG_PSEL_A :: CFG_PSEL_OANM1RTOP) , 7 => Some (CFG_PSEL_A :: CFG_PSEL_GPAMP_OUT_INT) , 8 => Some (CFG_PSEL_A :: CFG_PSEL_VSS) , _ => None , } } # [doc = "NC"] # [inline (always)] pub fn is_cfg_psel_nc (& self) -> bool { * self == CFG_PSEL_A :: CFG_PSEL_NC } # [doc = "EXTPIN0"] # [inline (always)] pub fn is_cfg_psel_extpin0 (& self) -> bool { * self == CFG_PSEL_A :: CFG_PSEL_EXTPIN0 } # [doc = "EXTPIN1"] # [inline (always)] pub fn is_cfg_psel_extpin1 (& self) -> bool { * self == CFG_PSEL_A :: CFG_PSEL_EXTPIN1 } # [doc = "DAC12OUT"] # [inline (always)] pub fn is_cfg_psel_dac12out (& self) -> bool { * self == CFG_PSEL_A :: CFG_PSEL_DAC12OUT } # [doc = "DAC8OUT"] # [inline (always)] pub fn is_cfg_psel_dac8out (& self) -> bool { * self == CFG_PSEL_A :: CFG_PSEL_DAC8OUT } # [doc = "VREF"] # [inline (always)] pub fn is_cfg_psel_vref (& self) -> bool { * self == CFG_PSEL_A :: CFG_PSEL_VREF } # [doc = "OANM1RTOP"] # [inline (always)] pub fn is_cfg_psel_oanm1rtop (& self) -> bool { * self == CFG_PSEL_A :: CFG_PSEL_OANM1RTOP } # [doc = "GPAMP_OUT_INT"] # [inline (always)] pub fn is_cfg_psel_gpamp_out_int (& self) -> bool { * self == CFG_PSEL_A :: CFG_PSEL_GPAMP_OUT_INT } # [doc = "VSS"] # [inline (always)] pub fn is_cfg_psel_vss (& self) -> bool { * self == CFG_PSEL_A :: CFG_PSEL_VSS } } # [doc = "Field `CFG_PSEL` writer - Positive OA input selection. Please refer to the device specific datasheet for exact channels available."] pub type CFG_PSEL_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 4 , O , CFG_PSEL_A > ; impl < 'a , REG , const O : u8 > CFG_PSEL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "NC"] # [inline (always)] pub fn cfg_psel_nc (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_PSEL_A :: CFG_PSEL_NC) } # [doc = "EXTPIN0"] # [inline (always)] pub fn cfg_psel_extpin0 (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_PSEL_A :: CFG_PSEL_EXTPIN0) } # [doc = "EXTPIN1"] # [inline (always)] pub fn cfg_psel_extpin1 (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_PSEL_A :: CFG_PSEL_EXTPIN1) } # [doc = "DAC12OUT"] # [inline (always)] pub fn cfg_psel_dac12out (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_PSEL_A :: CFG_PSEL_DAC12OUT) } # [doc = "DAC8OUT"] # [inline (always)] pub fn cfg_psel_dac8out (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_PSEL_A :: CFG_PSEL_DAC8OUT) } # [doc = "VREF"] # [inline (always)] pub fn cfg_psel_vref (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_PSEL_A :: CFG_PSEL_VREF) } # [doc = "OANM1RTOP"] # [inline (always)] pub fn cfg_psel_oanm1rtop (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_PSEL_A :: CFG_PSEL_OANM1RTOP) } # [doc = "GPAMP_OUT_INT"] # [inline (always)] pub fn cfg_psel_gpamp_out_int (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_PSEL_A :: CFG_PSEL_GPAMP_OUT_INT) } # [doc = "VSS"] # [inline (always)] pub fn cfg_psel_vss (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_PSEL_A :: CFG_PSEL_VSS) } } # [doc = "Field `CFG_NSEL` reader - Negative OA input selection. Please refer to the device specific datasheet for exact channels available."] pub type CFG_NSEL_R = crate :: FieldReader < CFG_NSEL_A > ; # [doc = "Negative OA input selection. Please refer to the device specific datasheet for exact channels available.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum CFG_NSEL_A { # [doc = "0: NC"] CFG_NSEL_NC = 0 , # [doc = "1: EXTPIN0"] CFG_NSEL_EXTPIN0 = 1 , # [doc = "2: EXTPIN1"] CFG_NSEL_EXTPIN1 = 2 , # [doc = "3: OANP1RBOT"] CFG_NSEL_OANP1RBOT = 3 , # [doc = "4: OANRTAP"] CFG_NSEL_OANRTAP = 4 , # [doc = "5: OANRTOP"] CFG_NSEL_OANRTOP = 5 , # [doc = "6: SPARE"] CFG_NSEL_SPARE = 6 , } impl From < CFG_NSEL_A > for u8 { # [inline (always)] fn from (variant : CFG_NSEL_A) -> Self { variant as _ } } impl crate :: FieldSpec for CFG_NSEL_A { type Ux = u8 ; } impl CFG_NSEL_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < CFG_NSEL_A > { match self . bits { 0 => Some (CFG_NSEL_A :: CFG_NSEL_NC) , 1 => Some (CFG_NSEL_A :: CFG_NSEL_EXTPIN0) , 2 => Some (CFG_NSEL_A :: CFG_NSEL_EXTPIN1) , 3 => Some (CFG_NSEL_A :: CFG_NSEL_OANP1RBOT) , 4 => Some (CFG_NSEL_A :: CFG_NSEL_OANRTAP) , 5 => Some (CFG_NSEL_A :: CFG_NSEL_OANRTOP) , 6 => Some (CFG_NSEL_A :: CFG_NSEL_SPARE) , _ => None , } } # [doc = "NC"] # [inline (always)] pub fn is_cfg_nsel_nc (& self) -> bool { * self == CFG_NSEL_A :: CFG_NSEL_NC } # [doc = "EXTPIN0"] # [inline (always)] pub fn is_cfg_nsel_extpin0 (& self) -> bool { * self == CFG_NSEL_A :: CFG_NSEL_EXTPIN0 } # [doc = "EXTPIN1"] # [inline (always)] pub fn is_cfg_nsel_extpin1 (& self) -> bool { * self == CFG_NSEL_A :: CFG_NSEL_EXTPIN1 } # [doc = "OANP1RBOT"] # [inline (always)] pub fn is_cfg_nsel_oanp1rbot (& self) -> bool { * self == CFG_NSEL_A :: CFG_NSEL_OANP1RBOT } # [doc = "OANRTAP"] # [inline (always)] pub fn is_cfg_nsel_oanrtap (& self) -> bool { * self == CFG_NSEL_A :: CFG_NSEL_OANRTAP } # [doc = "OANRTOP"] # [inline (always)] pub fn is_cfg_nsel_oanrtop (& self) -> bool { * self == CFG_NSEL_A :: CFG_NSEL_OANRTOP } # [doc = "SPARE"] # [inline (always)] pub fn is_cfg_nsel_spare (& self) -> bool { * self == CFG_NSEL_A :: CFG_NSEL_SPARE } } # [doc = "Field `CFG_NSEL` writer - Negative OA input selection. Please refer to the device specific datasheet for exact channels available."] pub type CFG_NSEL_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 3 , O , CFG_NSEL_A > ; impl < 'a , REG , const O : u8 > CFG_NSEL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "NC"] # [inline (always)] pub fn cfg_nsel_nc (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_NSEL_A :: CFG_NSEL_NC) } # [doc = "EXTPIN0"] # [inline (always)] pub fn cfg_nsel_extpin0 (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_NSEL_A :: CFG_NSEL_EXTPIN0) } # [doc = "EXTPIN1"] # [inline (always)] pub fn cfg_nsel_extpin1 (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_NSEL_A :: CFG_NSEL_EXTPIN1) } # [doc = "OANP1RBOT"] # [inline (always)] pub fn cfg_nsel_oanp1rbot (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_NSEL_A :: CFG_NSEL_OANP1RBOT) } # [doc = "OANRTAP"] # [inline (always)] pub fn cfg_nsel_oanrtap (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_NSEL_A :: CFG_NSEL_OANRTAP) } # [doc = "OANRTOP"] # [inline (always)] pub fn cfg_nsel_oanrtop (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_NSEL_A :: CFG_NSEL_OANRTOP) } # [doc = "SPARE"] # [inline (always)] pub fn cfg_nsel_spare (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_NSEL_A :: CFG_NSEL_SPARE) } } # [doc = "Field `CFG_MSEL` reader - MSEL Mux selection. Please refer to the device specific datasheet for exact channels available."] pub type CFG_MSEL_R = crate :: FieldReader < CFG_MSEL_A > ; # [doc = "MSEL Mux selection. Please refer to the device specific datasheet for exact channels available.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum CFG_MSEL_A { # [doc = "0: NC"] CFG_MSEL_NC = 0 , # [doc = "1: EXTNPIN1"] CFG_MSEL_EXTNPIN1 = 1 , # [doc = "2: VSS"] CFG_MSEL_VSS = 2 , # [doc = "3: DAC12OUT"] CFG_MSEL_DAC12OUT = 3 , # [doc = "4: OANM1RTOP"] CFG_MSEL_OANM1RTOP = 4 , } impl From < CFG_MSEL_A > for u8 { # [inline (always)] fn from (variant : CFG_MSEL_A) -> Self { variant as _ } } impl crate :: FieldSpec for CFG_MSEL_A { type Ux = u8 ; } impl CFG_MSEL_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < CFG_MSEL_A > { match self . bits { 0 => Some (CFG_MSEL_A :: CFG_MSEL_NC) , 1 => Some (CFG_MSEL_A :: CFG_MSEL_EXTNPIN1) , 2 => Some (CFG_MSEL_A :: CFG_MSEL_VSS) , 3 => Some (CFG_MSEL_A :: CFG_MSEL_DAC12OUT) , 4 => Some (CFG_MSEL_A :: CFG_MSEL_OANM1RTOP) , _ => None , } } # [doc = "NC"] # [inline (always)] pub fn is_cfg_msel_nc (& self) -> bool { * self == CFG_MSEL_A :: CFG_MSEL_NC } # [doc = "EXTNPIN1"] # [inline (always)] pub fn is_cfg_msel_extnpin1 (& self) -> bool { * self == CFG_MSEL_A :: CFG_MSEL_EXTNPIN1 } # [doc = "VSS"] # [inline (always)] pub fn is_cfg_msel_vss (& self) -> bool { * self == CFG_MSEL_A :: CFG_MSEL_VSS } # [doc = "DAC12OUT"] # [inline (always)] pub fn is_cfg_msel_dac12out (& self) -> bool { * self == CFG_MSEL_A :: CFG_MSEL_DAC12OUT } # [doc = "OANM1RTOP"] # [inline (always)] pub fn is_cfg_msel_oanm1rtop (& self) -> bool { * self == CFG_MSEL_A :: CFG_MSEL_OANM1RTOP } } # [doc = "Field `CFG_MSEL` writer - MSEL Mux selection. Please refer to the device specific datasheet for exact channels available."] pub type CFG_MSEL_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 3 , O , CFG_MSEL_A > ; impl < 'a , REG , const O : u8 > CFG_MSEL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "NC"] # [inline (always)] pub fn cfg_msel_nc (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_MSEL_A :: CFG_MSEL_NC) } # [doc = "EXTNPIN1"] # [inline (always)] pub fn cfg_msel_extnpin1 (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_MSEL_A :: CFG_MSEL_EXTNPIN1) } # [doc = "VSS"] # [inline (always)] pub fn cfg_msel_vss (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_MSEL_A :: CFG_MSEL_VSS) } # [doc = "DAC12OUT"] # [inline (always)] pub fn cfg_msel_dac12out (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_MSEL_A :: CFG_MSEL_DAC12OUT) } # [doc = "OANM1RTOP"] # [inline (always)] pub fn cfg_msel_oanm1rtop (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_MSEL_A :: CFG_MSEL_OANM1RTOP) } } # [doc = "Field `CFG_GAIN` reader - Gain setting. Refer to TRM for enumeration information."] pub type CFG_GAIN_R = crate :: FieldReader ; # [doc = "Field `CFG_GAIN` writer - Gain setting. Refer to TRM for enumeration information."] pub type CFG_GAIN_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 3 , O > ; impl R { # [doc = "Bits 0:1 - Chopping enable."] # [inline (always)] pub fn cfg_chop (& self) -> CFG_CHOP_R { CFG_CHOP_R :: new ((self . bits & 3) as u8) } # [doc = "Bit 2 - Enable output pin"] # [inline (always)] pub fn cfg_outpin (& self) -> CFG_OUTPIN_R { CFG_OUTPIN_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bits 3:6 - Positive OA input selection. Please refer to the device specific datasheet for exact channels available."] # [inline (always)] pub fn cfg_psel (& self) -> CFG_PSEL_R { CFG_PSEL_R :: new (((self . bits >> 3) & 0x0f) as u8) } # [doc = "Bits 7:9 - Negative OA input selection. Please refer to the device specific datasheet for exact channels available."] # [inline (always)] pub fn cfg_nsel (& self) -> CFG_NSEL_R { CFG_NSEL_R :: new (((self . bits >> 7) & 7) as u8) } # [doc = "Bits 10:12 - MSEL Mux selection. Please refer to the device specific datasheet for exact channels available."] # [inline (always)] pub fn cfg_msel (& self) -> CFG_MSEL_R { CFG_MSEL_R :: new (((self . bits >> 10) & 7) as u8) } # [doc = "Bits 13:15 - Gain setting. Refer to TRM for enumeration information."] # [inline (always)] pub fn cfg_gain (& self) -> CFG_GAIN_R { CFG_GAIN_R :: new (((self . bits >> 13) & 7) as u8) } } impl W { # [doc = "Bits 0:1 - Chopping enable."] # [inline (always)] # [must_use] pub fn cfg_chop (& mut self) -> CFG_CHOP_W < CFG_SPEC , 0 > { CFG_CHOP_W :: new (self) } # [doc = "Bit 2 - Enable output pin"] # [inline (always)] # [must_use] pub fn cfg_outpin (& mut self) -> CFG_OUTPIN_W <'_, CFG_SPEC , 2 > { CFG_OUTPIN_W :: new (self) } # [doc = "Bits 3:6 - Positive OA input selection. Please refer to the device specific datasheet for exact channels available."] # [inline (always)] # [must_use] pub fn cfg_psel (& mut self) -> CFG_PSEL_W < CFG_SPEC , 3 > { CFG_PSEL_W :: new (self) } # [doc = "Bits 7:9 - Negative OA input selection. Please refer to the device specific datasheet for exact channels available."] # [inline (always)] # [must_use] pub fn cfg_nsel (& mut self) -> CFG_NSEL_W < CFG_SPEC , 7 > { CFG_NSEL_W :: new (self) } # [doc = "Bits 10:12 - MSEL Mux selection. Please refer to the device specific datasheet for exact channels available."] # [inline (always)] # [must_use] pub fn cfg_msel (& mut self) -> CFG_MSEL_W < CFG_SPEC , 10 > { CFG_MSEL_W :: new (self) } # [doc = "Bits 13:15 - Gain setting. Refer to TRM for enumeration information."] # [inline (always)] # [must_use] pub fn cfg_gain (& mut self) -> CFG_GAIN_W < CFG_SPEC , 13 > { CFG_GAIN_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Configuration Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CFG_SPEC ; impl crate :: RegisterSpec for CFG_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`cfg::R`](R) reader structure"] impl crate :: Readable for CFG_SPEC { } # [doc = "`write(|w| ..)` method takes [`cfg::W`](W) writer structure"] impl crate :: Writable for CFG_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets CFG to value 0"] impl crate :: Resettable for CFG_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/i2c0/mfifoctl.rs:1:13367 [INFO] [stdout] | [INFO] [stdout] 1 | ... fn mfifoctl_rxflush (& mut self) -> MFIFOCTL_RXFLUSH_W < MFIFOCTL_SPEC , 15 > { MFIFOCTL_RXFLUSH_W :: new (self) } # [doc = r" Writes... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `MFIFOCTL` reader"] pub type R = crate :: R < MFIFOCTL_SPEC > ; # [doc = "Register `MFIFOCTL` writer"] pub type W = crate :: W < MFIFOCTL_SPEC > ; # [doc = "Field `MFIFOCTL_TXTRIG` reader - TX FIFO Trigger Indicates at what fill level in the TX FIFO a trigger will be generated."] pub type MFIFOCTL_TXTRIG_R = crate :: FieldReader < MFIFOCTL_TXTRIG_A > ; # [doc = "TX FIFO Trigger Indicates at what fill level in the TX FIFO a trigger will be generated.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum MFIFOCTL_TXTRIG_A { # [doc = "4: LEVEL_4"] MFIFOCTL_TXTRIG_LEVEL_4 = 4 , # [doc = "5: LEVEL_5"] MFIFOCTL_TXTRIG_LEVEL_5 = 5 , # [doc = "6: LEVEL_6"] MFIFOCTL_TXTRIG_LEVEL_6 = 6 , # [doc = "7: LEVEL_7"] MFIFOCTL_TXTRIG_LEVEL_7 = 7 , } impl From < MFIFOCTL_TXTRIG_A > for u8 { # [inline (always)] fn from (variant : MFIFOCTL_TXTRIG_A) -> Self { variant as _ } } impl crate :: FieldSpec for MFIFOCTL_TXTRIG_A { type Ux = u8 ; } impl MFIFOCTL_TXTRIG_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < MFIFOCTL_TXTRIG_A > { match self . bits { 4 => Some (MFIFOCTL_TXTRIG_A :: MFIFOCTL_TXTRIG_LEVEL_4) , 5 => Some (MFIFOCTL_TXTRIG_A :: MFIFOCTL_TXTRIG_LEVEL_5) , 6 => Some (MFIFOCTL_TXTRIG_A :: MFIFOCTL_TXTRIG_LEVEL_6) , 7 => Some (MFIFOCTL_TXTRIG_A :: MFIFOCTL_TXTRIG_LEVEL_7) , _ => None , } } # [doc = "LEVEL_4"] # [inline (always)] pub fn is_mfifoctl_txtrig_level_4 (& self) -> bool { * self == MFIFOCTL_TXTRIG_A :: MFIFOCTL_TXTRIG_LEVEL_4 } # [doc = "LEVEL_5"] # [inline (always)] pub fn is_mfifoctl_txtrig_level_5 (& self) -> bool { * self == MFIFOCTL_TXTRIG_A :: MFIFOCTL_TXTRIG_LEVEL_5 } # [doc = "LEVEL_6"] # [inline (always)] pub fn is_mfifoctl_txtrig_level_6 (& self) -> bool { * self == MFIFOCTL_TXTRIG_A :: MFIFOCTL_TXTRIG_LEVEL_6 } # [doc = "LEVEL_7"] # [inline (always)] pub fn is_mfifoctl_txtrig_level_7 (& self) -> bool { * self == MFIFOCTL_TXTRIG_A :: MFIFOCTL_TXTRIG_LEVEL_7 } } # [doc = "Field `MFIFOCTL_TXTRIG` writer - TX FIFO Trigger Indicates at what fill level in the TX FIFO a trigger will be generated."] pub type MFIFOCTL_TXTRIG_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 3 , O , MFIFOCTL_TXTRIG_A > ; impl < 'a , REG , const O : u8 > MFIFOCTL_TXTRIG_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "LEVEL_4"] # [inline (always)] pub fn mfifoctl_txtrig_level_4 (self) -> & 'a mut crate :: W < REG > { self . variant (MFIFOCTL_TXTRIG_A :: MFIFOCTL_TXTRIG_LEVEL_4) } # [doc = "LEVEL_5"] # [inline (always)] pub fn mfifoctl_txtrig_level_5 (self) -> & 'a mut crate :: W < REG > { self . variant (MFIFOCTL_TXTRIG_A :: MFIFOCTL_TXTRIG_LEVEL_5) } # [doc = "LEVEL_6"] # [inline (always)] pub fn mfifoctl_txtrig_level_6 (self) -> & 'a mut crate :: W < REG > { self . variant (MFIFOCTL_TXTRIG_A :: MFIFOCTL_TXTRIG_LEVEL_6) } # [doc = "LEVEL_7"] # [inline (always)] pub fn mfifoctl_txtrig_level_7 (self) -> & 'a mut crate :: W < REG > { self . variant (MFIFOCTL_TXTRIG_A :: MFIFOCTL_TXTRIG_LEVEL_7) } } # [doc = "Field `MFIFOCTL_TXFLUSH` reader - TX FIFO Flush Setting this bit will Flush the TX FIFO. Before reseting this bit to stop Flush the TXFIFOCNT should be checked to be 8 and indicating that the Flush has completed."] pub type MFIFOCTL_TXFLUSH_R = crate :: BitReader < MFIFOCTL_TXFLUSH_A > ; # [doc = "TX FIFO Flush Setting this bit will Flush the TX FIFO. Before reseting this bit to stop Flush the TXFIFOCNT should be checked to be 8 and indicating that the Flush has completed.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum MFIFOCTL_TXFLUSH_A { # [doc = "0: NOFLUSH"] MFIFOCTL_TXFLUSH_NOFLUSH = 0 , # [doc = "1: FLUSH"] MFIFOCTL_TXFLUSH_FLUSH = 1 , } impl From < MFIFOCTL_TXFLUSH_A > for bool { # [inline (always)] fn from (variant : MFIFOCTL_TXFLUSH_A) -> Self { variant as u8 != 0 } } impl MFIFOCTL_TXFLUSH_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> MFIFOCTL_TXFLUSH_A { match self . bits { false => MFIFOCTL_TXFLUSH_A :: MFIFOCTL_TXFLUSH_NOFLUSH , true => MFIFOCTL_TXFLUSH_A :: MFIFOCTL_TXFLUSH_FLUSH , } } # [doc = "NOFLUSH"] # [inline (always)] pub fn is_mfifoctl_txflush_noflush (& self) -> bool { * self == MFIFOCTL_TXFLUSH_A :: MFIFOCTL_TXFLUSH_NOFLUSH } # [doc = "FLUSH"] # [inline (always)] pub fn is_mfifoctl_txflush_flush (& self) -> bool { * self == MFIFOCTL_TXFLUSH_A :: MFIFOCTL_TXFLUSH_FLUSH } } # [doc = "Field `MFIFOCTL_TXFLUSH` writer - TX FIFO Flush Setting this bit will Flush the TX FIFO. Before reseting this bit to stop Flush the TXFIFOCNT should be checked to be 8 and indicating that the Flush has completed."] pub type MFIFOCTL_TXFLUSH_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , MFIFOCTL_TXFLUSH_A > ; impl < 'a , REG , const O : u8 > MFIFOCTL_TXFLUSH_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NOFLUSH"] # [inline (always)] pub fn mfifoctl_txflush_noflush (self) -> & 'a mut crate :: W < REG > { self . variant (MFIFOCTL_TXFLUSH_A :: MFIFOCTL_TXFLUSH_NOFLUSH) } # [doc = "FLUSH"] # [inline (always)] pub fn mfifoctl_txflush_flush (self) -> & 'a mut crate :: W < REG > { self . variant (MFIFOCTL_TXFLUSH_A :: MFIFOCTL_TXFLUSH_FLUSH) } } # [doc = "Field `MFIFOCTL_RXTRIG` reader - RX FIFO Trigger Indicates at what fill level in the RX FIFO a trigger will be generated. Note: Programming RXTRIG to 0x0 has no effect since no data is present to transfer out of RX FIFO."] pub type MFIFOCTL_RXTRIG_R = crate :: FieldReader < MFIFOCTL_RXTRIG_A > ; # [doc = "RX FIFO Trigger Indicates at what fill level in the RX FIFO a trigger will be generated. Note: Programming RXTRIG to 0x0 has no effect since no data is present to transfer out of RX FIFO.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum MFIFOCTL_RXTRIG_A { # [doc = "4: LEVEL_5"] MFIFOCTL_RXTRIG_LEVEL_5 = 4 , # [doc = "5: LEVEL_6"] MFIFOCTL_RXTRIG_LEVEL_6 = 5 , # [doc = "6: LEVEL_7"] MFIFOCTL_RXTRIG_LEVEL_7 = 6 , # [doc = "7: LEVEL_8"] MFIFOCTL_RXTRIG_LEVEL_8 = 7 , } impl From < MFIFOCTL_RXTRIG_A > for u8 { # [inline (always)] fn from (variant : MFIFOCTL_RXTRIG_A) -> Self { variant as _ } } impl crate :: FieldSpec for MFIFOCTL_RXTRIG_A { type Ux = u8 ; } impl MFIFOCTL_RXTRIG_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < MFIFOCTL_RXTRIG_A > { match self . bits { 4 => Some (MFIFOCTL_RXTRIG_A :: MFIFOCTL_RXTRIG_LEVEL_5) , 5 => Some (MFIFOCTL_RXTRIG_A :: MFIFOCTL_RXTRIG_LEVEL_6) , 6 => Some (MFIFOCTL_RXTRIG_A :: MFIFOCTL_RXTRIG_LEVEL_7) , 7 => Some (MFIFOCTL_RXTRIG_A :: MFIFOCTL_RXTRIG_LEVEL_8) , _ => None , } } # [doc = "LEVEL_5"] # [inline (always)] pub fn is_mfifoctl_rxtrig_level_5 (& self) -> bool { * self == MFIFOCTL_RXTRIG_A :: MFIFOCTL_RXTRIG_LEVEL_5 } # [doc = "LEVEL_6"] # [inline (always)] pub fn is_mfifoctl_rxtrig_level_6 (& self) -> bool { * self == MFIFOCTL_RXTRIG_A :: MFIFOCTL_RXTRIG_LEVEL_6 } # [doc = "LEVEL_7"] # [inline (always)] pub fn is_mfifoctl_rxtrig_level_7 (& self) -> bool { * self == MFIFOCTL_RXTRIG_A :: MFIFOCTL_RXTRIG_LEVEL_7 } # [doc = "LEVEL_8"] # [inline (always)] pub fn is_mfifoctl_rxtrig_level_8 (& self) -> bool { * self == MFIFOCTL_RXTRIG_A :: MFIFOCTL_RXTRIG_LEVEL_8 } } # [doc = "Field `MFIFOCTL_RXTRIG` writer - RX FIFO Trigger Indicates at what fill level in the RX FIFO a trigger will be generated. Note: Programming RXTRIG to 0x0 has no effect since no data is present to transfer out of RX FIFO."] pub type MFIFOCTL_RXTRIG_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 3 , O , MFIFOCTL_RXTRIG_A > ; impl < 'a , REG , const O : u8 > MFIFOCTL_RXTRIG_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "LEVEL_5"] # [inline (always)] pub fn mfifoctl_rxtrig_level_5 (self) -> & 'a mut crate :: W < REG > { self . variant (MFIFOCTL_RXTRIG_A :: MFIFOCTL_RXTRIG_LEVEL_5) } # [doc = "LEVEL_6"] # [inline (always)] pub fn mfifoctl_rxtrig_level_6 (self) -> & 'a mut crate :: W < REG > { self . variant (MFIFOCTL_RXTRIG_A :: MFIFOCTL_RXTRIG_LEVEL_6) } # [doc = "LEVEL_7"] # [inline (always)] pub fn mfifoctl_rxtrig_level_7 (self) -> & 'a mut crate :: W < REG > { self . variant (MFIFOCTL_RXTRIG_A :: MFIFOCTL_RXTRIG_LEVEL_7) } # [doc = "LEVEL_8"] # [inline (always)] pub fn mfifoctl_rxtrig_level_8 (self) -> & 'a mut crate :: W < REG > { self . variant (MFIFOCTL_RXTRIG_A :: MFIFOCTL_RXTRIG_LEVEL_8) } } # [doc = "Field `MFIFOCTL_RXFLUSH` reader - RX FIFO Flush Setting this bit will Flush the RX FIFO. Before reseting this bit to stop Flush the RXFIFOCNT should be checked to be 0 and indicating that the Flush has completed."] pub type MFIFOCTL_RXFLUSH_R = crate :: BitReader < MFIFOCTL_RXFLUSH_A > ; # [doc = "RX FIFO Flush Setting this bit will Flush the RX FIFO. Before reseting this bit to stop Flush the RXFIFOCNT should be checked to be 0 and indicating that the Flush has completed.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum MFIFOCTL_RXFLUSH_A { # [doc = "0: NOFLUSH"] MFIFOCTL_RXFLUSH_NOFLUSH = 0 , # [doc = "1: FLUSH"] MFIFOCTL_RXFLUSH_FLUSH = 1 , } impl From < MFIFOCTL_RXFLUSH_A > for bool { # [inline (always)] fn from (variant : MFIFOCTL_RXFLUSH_A) -> Self { variant as u8 != 0 } } impl MFIFOCTL_RXFLUSH_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> MFIFOCTL_RXFLUSH_A { match self . bits { false => MFIFOCTL_RXFLUSH_A :: MFIFOCTL_RXFLUSH_NOFLUSH , true => MFIFOCTL_RXFLUSH_A :: MFIFOCTL_RXFLUSH_FLUSH , } } # [doc = "NOFLUSH"] # [inline (always)] pub fn is_mfifoctl_rxflush_noflush (& self) -> bool { * self == MFIFOCTL_RXFLUSH_A :: MFIFOCTL_RXFLUSH_NOFLUSH } # [doc = "FLUSH"] # [inline (always)] pub fn is_mfifoctl_rxflush_flush (& self) -> bool { * self == MFIFOCTL_RXFLUSH_A :: MFIFOCTL_RXFLUSH_FLUSH } } # [doc = "Field `MFIFOCTL_RXFLUSH` writer - RX FIFO Flush Setting this bit will Flush the RX FIFO. Before reseting this bit to stop Flush the RXFIFOCNT should be checked to be 0 and indicating that the Flush has completed."] pub type MFIFOCTL_RXFLUSH_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , MFIFOCTL_RXFLUSH_A > ; impl < 'a , REG , const O : u8 > MFIFOCTL_RXFLUSH_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NOFLUSH"] # [inline (always)] pub fn mfifoctl_rxflush_noflush (self) -> & 'a mut crate :: W < REG > { self . variant (MFIFOCTL_RXFLUSH_A :: MFIFOCTL_RXFLUSH_NOFLUSH) } # [doc = "FLUSH"] # [inline (always)] pub fn mfifoctl_rxflush_flush (self) -> & 'a mut crate :: W < REG > { self . variant (MFIFOCTL_RXFLUSH_A :: MFIFOCTL_RXFLUSH_FLUSH) } } impl R { # [doc = "Bits 0:2 - TX FIFO Trigger Indicates at what fill level in the TX FIFO a trigger will be generated."] # [inline (always)] pub fn mfifoctl_txtrig (& self) -> MFIFOCTL_TXTRIG_R { MFIFOCTL_TXTRIG_R :: new ((self . bits & 7) as u8) } # [doc = "Bit 7 - TX FIFO Flush Setting this bit will Flush the TX FIFO. Before reseting this bit to stop Flush the TXFIFOCNT should be checked to be 8 and indicating that the Flush has completed."] # [inline (always)] pub fn mfifoctl_txflush (& self) -> MFIFOCTL_TXFLUSH_R { MFIFOCTL_TXFLUSH_R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bits 8:10 - RX FIFO Trigger Indicates at what fill level in the RX FIFO a trigger will be generated. Note: Programming RXTRIG to 0x0 has no effect since no data is present to transfer out of RX FIFO."] # [inline (always)] pub fn mfifoctl_rxtrig (& self) -> MFIFOCTL_RXTRIG_R { MFIFOCTL_RXTRIG_R :: new (((self . bits >> 8) & 7) as u8) } # [doc = "Bit 15 - RX FIFO Flush Setting this bit will Flush the RX FIFO. Before reseting this bit to stop Flush the RXFIFOCNT should be checked to be 0 and indicating that the Flush has completed."] # [inline (always)] pub fn mfifoctl_rxflush (& self) -> MFIFOCTL_RXFLUSH_R { MFIFOCTL_RXFLUSH_R :: new (((self . bits >> 15) & 1) != 0) } } impl W { # [doc = "Bits 0:2 - TX FIFO Trigger Indicates at what fill level in the TX FIFO a trigger will be generated."] # [inline (always)] # [must_use] pub fn mfifoctl_txtrig (& mut self) -> MFIFOCTL_TXTRIG_W < MFIFOCTL_SPEC , 0 > { MFIFOCTL_TXTRIG_W :: new (self) } # [doc = "Bit 7 - TX FIFO Flush Setting this bit will Flush the TX FIFO. Before reseting this bit to stop Flush the TXFIFOCNT should be checked to be 8 and indicating that the Flush has completed."] # [inline (always)] # [must_use] pub fn mfifoctl_txflush (& mut self) -> MFIFOCTL_TXFLUSH_W < MFIFOCTL_SPEC , 7 > { MFIFOCTL_TXFLUSH_W :: new (self) } # [doc = "Bits 8:10 - RX FIFO Trigger Indicates at what fill level in the RX FIFO a trigger will be generated. Note: Programming RXTRIG to 0x0 has no effect since no data is present to transfer out of RX FIFO."] # [inline (always)] # [must_use] pub fn mfifoctl_rxtrig (& mut self) -> MFIFOCTL_RXTRIG_W < MFIFOCTL_SPEC , 8 > { MFIFOCTL_RXTRIG_W :: new (self) } # [doc = "Bit 15 - RX FIFO Flush Setting this bit will Flush the RX FIFO. Before reseting this bit to stop Flush the RXFIFOCNT should be checked to be 0 and indicating that the Flush has completed."] # [inline (always)] # [must_use] pub fn mfifoctl_rxflush (& mut self) -> MFIFOCTL_RXFLUSH_W <'_, MFIFOCTL_SPEC , 15 > { MFIFOCTL_RXFLUSH_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "I2C Master FIFO Control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mfifoctl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mfifoctl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct MFIFOCTL_SPEC ; impl crate :: RegisterSpec for MFIFOCTL_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`mfifoctl::R`](R) reader structure"] impl crate :: Readable for MFIFOCTL_SPEC { } # [doc = "`write(|w| ..)` method takes [`mfifoctl::W`](W) writer structure"] impl crate :: Writable for MFIFOCTL_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets MFIFOCTL to value 0"] impl crate :: Resettable for MFIFOCTL_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/timg4/ccact_01.rs:1:23460 [INFO] [stdout] | [INFO] [stdout] 1 | ...] pub fn ccact_01_lact (& mut self) -> CCACT_01_LACT_W < CCACT_01_SPEC , 3 > { CCACT_01_LACT_W :: new (self) } # [doc = "Bits 6:7 - CC... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `CCACT_01[%s]` reader"] pub type R = crate :: R < CCACT_01_SPEC > ; # [doc = "Register `CCACT_01[%s]` writer"] pub type W = crate :: W < CCACT_01_SPEC > ; # [doc = "Field `CCACT_01_ZACT` reader - CCP Output Action on Zero Specifies what changes occur to CCP output as the result of a zero event."] pub type CCACT_01_ZACT_R = crate :: FieldReader < CCACT_01_ZACT_A > ; # [doc = "CCP Output Action on Zero Specifies what changes occur to CCP output as the result of a zero event.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum CCACT_01_ZACT_A { # [doc = "0: DISABLED"] CCACT_01_ZACT_DISABLED = 0 , # [doc = "1: CCP_HIGH"] CCACT_01_ZACT_CCP_HIGH = 1 , # [doc = "2: CCP_LOW"] CCACT_01_ZACT_CCP_LOW = 2 , # [doc = "3: CCP_TOGGLE"] CCACT_01_ZACT_CCP_TOGGLE = 3 , } impl From < CCACT_01_ZACT_A > for u8 { # [inline (always)] fn from (variant : CCACT_01_ZACT_A) -> Self { variant as _ } } impl crate :: FieldSpec for CCACT_01_ZACT_A { type Ux = u8 ; } impl CCACT_01_ZACT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CCACT_01_ZACT_A { match self . bits { 0 => CCACT_01_ZACT_A :: CCACT_01_ZACT_DISABLED , 1 => CCACT_01_ZACT_A :: CCACT_01_ZACT_CCP_HIGH , 2 => CCACT_01_ZACT_A :: CCACT_01_ZACT_CCP_LOW , 3 => CCACT_01_ZACT_A :: CCACT_01_ZACT_CCP_TOGGLE , _ => unreachable ! () , } } # [doc = "DISABLED"] # [inline (always)] pub fn is_ccact_01_zact_disabled (& self) -> bool { * self == CCACT_01_ZACT_A :: CCACT_01_ZACT_DISABLED } # [doc = "CCP_HIGH"] # [inline (always)] pub fn is_ccact_01_zact_ccp_high (& self) -> bool { * self == CCACT_01_ZACT_A :: CCACT_01_ZACT_CCP_HIGH } # [doc = "CCP_LOW"] # [inline (always)] pub fn is_ccact_01_zact_ccp_low (& self) -> bool { * self == CCACT_01_ZACT_A :: CCACT_01_ZACT_CCP_LOW } # [doc = "CCP_TOGGLE"] # [inline (always)] pub fn is_ccact_01_zact_ccp_toggle (& self) -> bool { * self == CCACT_01_ZACT_A :: CCACT_01_ZACT_CCP_TOGGLE } } # [doc = "Field `CCACT_01_ZACT` writer - CCP Output Action on Zero Specifies what changes occur to CCP output as the result of a zero event."] pub type CCACT_01_ZACT_W < 'a , REG , const O : u8 > = crate :: FieldWriterSafe < 'a , REG , 2 , O , CCACT_01_ZACT_A > ; impl < 'a , REG , const O : u8 > CCACT_01_ZACT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "DISABLED"] # [inline (always)] pub fn ccact_01_zact_disabled (self) -> & 'a mut crate :: W < REG > { self . variant (CCACT_01_ZACT_A :: CCACT_01_ZACT_DISABLED) } # [doc = "CCP_HIGH"] # [inline (always)] pub fn ccact_01_zact_ccp_high (self) -> & 'a mut crate :: W < REG > { self . variant (CCACT_01_ZACT_A :: CCACT_01_ZACT_CCP_HIGH) } # [doc = "CCP_LOW"] # [inline (always)] pub fn ccact_01_zact_ccp_low (self) -> & 'a mut crate :: W < REG > { self . variant (CCACT_01_ZACT_A :: CCACT_01_ZACT_CCP_LOW) } # [doc = "CCP_TOGGLE"] # [inline (always)] pub fn ccact_01_zact_ccp_toggle (self) -> & 'a mut crate :: W < REG > { self . variant (CCACT_01_ZACT_A :: CCACT_01_ZACT_CCP_TOGGLE) } } # [doc = "Field `CCACT_01_LACT` reader - CCP Output Action on Load Specifies what changes occur to CCP output as the result of a load event."] pub type CCACT_01_LACT_R = crate :: FieldReader < CCACT_01_LACT_A > ; # [doc = "CCP Output Action on Load Specifies what changes occur to CCP output as the result of a load event.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum CCACT_01_LACT_A { # [doc = "0: DISABLED"] CCACT_01_LACT_DISABLED = 0 , # [doc = "1: CCP_HIGH"] CCACT_01_LACT_CCP_HIGH = 1 , # [doc = "2: CCP_LOW"] CCACT_01_LACT_CCP_LOW = 2 , # [doc = "3: CCP_TOGGLE"] CCACT_01_LACT_CCP_TOGGLE = 3 , } impl From < CCACT_01_LACT_A > for u8 { # [inline (always)] fn from (variant : CCACT_01_LACT_A) -> Self { variant as _ } } impl crate :: FieldSpec for CCACT_01_LACT_A { type Ux = u8 ; } impl CCACT_01_LACT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CCACT_01_LACT_A { match self . bits { 0 => CCACT_01_LACT_A :: CCACT_01_LACT_DISABLED , 1 => CCACT_01_LACT_A :: CCACT_01_LACT_CCP_HIGH , 2 => CCACT_01_LACT_A :: CCACT_01_LACT_CCP_LOW , 3 => CCACT_01_LACT_A :: CCACT_01_LACT_CCP_TOGGLE , _ => unreachable ! () , } } # [doc = "DISABLED"] # [inline (always)] pub fn is_ccact_01_lact_disabled (& self) -> bool { * self == CCACT_01_LACT_A :: CCACT_01_LACT_DISABLED } # [doc = "CCP_HIGH"] # [inline (always)] pub fn is_ccact_01_lact_ccp_high (& self) -> bool { * self == CCACT_01_LACT_A :: CCACT_01_LACT_CCP_HIGH } # [doc = "CCP_LOW"] # [inline (always)] pub fn is_ccact_01_lact_ccp_low (& self) -> bool { * self == CCACT_01_LACT_A :: CCACT_01_LACT_CCP_LOW } # [doc = "CCP_TOGGLE"] # [inline (always)] pub fn is_ccact_01_lact_ccp_toggle (& self) -> bool { * self == CCACT_01_LACT_A :: CCACT_01_LACT_CCP_TOGGLE } } # [doc = "Field `CCACT_01_LACT` writer - CCP Output Action on Load Specifies what changes occur to CCP output as the result of a load event."] pub type CCACT_01_LACT_W < 'a , REG , const O : u8 > = crate :: FieldWriterSafe < 'a , REG , 2 , O , CCACT_01_LACT_A > ; impl < 'a , REG , const O : u8 > CCACT_01_LACT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "DISABLED"] # [inline (always)] pub fn ccact_01_lact_disabled (self) -> & 'a mut crate :: W < REG > { self . variant (CCACT_01_LACT_A :: CCACT_01_LACT_DISABLED) } # [doc = "CCP_HIGH"] # [inline (always)] pub fn ccact_01_lact_ccp_high (self) -> & 'a mut crate :: W < REG > { self . variant (CCACT_01_LACT_A :: CCACT_01_LACT_CCP_HIGH) } # [doc = "CCP_LOW"] # [inline (always)] pub fn ccact_01_lact_ccp_low (self) -> & 'a mut crate :: W < REG > { self . variant (CCACT_01_LACT_A :: CCACT_01_LACT_CCP_LOW) } # [doc = "CCP_TOGGLE"] # [inline (always)] pub fn ccact_01_lact_ccp_toggle (self) -> & 'a mut crate :: W < REG > { self . variant (CCACT_01_LACT_A :: CCACT_01_LACT_CCP_TOGGLE) } } # [doc = "Field `CCACT_01_CDACT` reader - CCP Output Action on Compare (Down) This field describes the resulting action of the signal generator upon detecting a compare event while counting down."] pub type CCACT_01_CDACT_R = crate :: FieldReader < CCACT_01_CDACT_A > ; # [doc = "CCP Output Action on Compare (Down) This field describes the resulting action of the signal generator upon detecting a compare event while counting down.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum CCACT_01_CDACT_A { # [doc = "0: DISABLED"] CCACT_01_CDACT_DISABLED = 0 , # [doc = "1: CCP_HIGH"] CCACT_01_CDACT_CCP_HIGH = 1 , # [doc = "2: CCP_LOW"] CCACT_01_CDACT_CCP_LOW = 2 , # [doc = "3: CCP_TOGGLE"] CCACT_01_CDACT_CCP_TOGGLE = 3 , } impl From < CCACT_01_CDACT_A > for u8 { # [inline (always)] fn from (variant : CCACT_01_CDACT_A) -> Self { variant as _ } } impl crate :: FieldSpec for CCACT_01_CDACT_A { type Ux = u8 ; } impl CCACT_01_CDACT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CCACT_01_CDACT_A { match self . bits { 0 => CCACT_01_CDACT_A :: CCACT_01_CDACT_DISABLED , 1 => CCACT_01_CDACT_A :: CCACT_01_CDACT_CCP_HIGH , 2 => CCACT_01_CDACT_A :: CCACT_01_CDACT_CCP_LOW , 3 => CCACT_01_CDACT_A :: CCACT_01_CDACT_CCP_TOGGLE , _ => unreachable ! () , } } # [doc = "DISABLED"] # [inline (always)] pub fn is_ccact_01_cdact_disabled (& self) -> bool { * self == CCACT_01_CDACT_A :: CCACT_01_CDACT_DISABLED } # [doc = "CCP_HIGH"] # [inline (always)] pub fn is_ccact_01_cdact_ccp_high (& self) -> bool { * self == CCACT_01_CDACT_A :: CCACT_01_CDACT_CCP_HIGH } # [doc = "CCP_LOW"] # [inline (always)] pub fn is_ccact_01_cdact_ccp_low (& self) -> bool { * self == CCACT_01_CDACT_A :: CCACT_01_CDACT_CCP_LOW } # [doc = "CCP_TOGGLE"] # [inline (always)] pub fn is_ccact_01_cdact_ccp_toggle (& self) -> bool { * self == CCACT_01_CDACT_A :: CCACT_01_CDACT_CCP_TOGGLE } } # [doc = "Field `CCACT_01_CDACT` writer - CCP Output Action on Compare (Down) This field describes the resulting action of the signal generator upon detecting a compare event while counting down."] pub type CCACT_01_CDACT_W < 'a , REG , const O : u8 > = crate :: FieldWriterSafe < 'a , REG , 2 , O , CCACT_01_CDACT_A > ; impl < 'a , REG , const O : u8 > CCACT_01_CDACT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "DISABLED"] # [inline (always)] pub fn ccact_01_cdact_disabled (self) -> & 'a mut crate :: W < REG > { self . variant (CCACT_01_CDACT_A :: CCACT_01_CDACT_DISABLED) } # [doc = "CCP_HIGH"] # [inline (always)] pub fn ccact_01_cdact_ccp_high (self) -> & 'a mut crate :: W < REG > { self . variant (CCACT_01_CDACT_A :: CCACT_01_CDACT_CCP_HIGH) } # [doc = "CCP_LOW"] # [inline (always)] pub fn ccact_01_cdact_ccp_low (self) -> & 'a mut crate :: W < REG > { self . variant (CCACT_01_CDACT_A :: CCACT_01_CDACT_CCP_LOW) } # [doc = "CCP_TOGGLE"] # [inline (always)] pub fn ccact_01_cdact_ccp_toggle (self) -> & 'a mut crate :: W < REG > { self . variant (CCACT_01_CDACT_A :: CCACT_01_CDACT_CCP_TOGGLE) } } # [doc = "Field `CCACT_01_CUACT` reader - CCP Output Action on Compare (Up) This field describes the resulting action of the signal generator upon detecting a compare event while counting up."] pub type CCACT_01_CUACT_R = crate :: FieldReader < CCACT_01_CUACT_A > ; # [doc = "CCP Output Action on Compare (Up) This field describes the resulting action of the signal generator upon detecting a compare event while counting up.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum CCACT_01_CUACT_A { # [doc = "0: DISABLED"] CCACT_01_CUACT_DISABLED = 0 , # [doc = "1: CCP_HIGH"] CCACT_01_CUACT_CCP_HIGH = 1 , # [doc = "2: CCP_LOW"] CCACT_01_CUACT_CCP_LOW = 2 , # [doc = "3: CCP_TOGGLE"] CCACT_01_CUACT_CCP_TOGGLE = 3 , } impl From < CCACT_01_CUACT_A > for u8 { # [inline (always)] fn from (variant : CCACT_01_CUACT_A) -> Self { variant as _ } } impl crate :: FieldSpec for CCACT_01_CUACT_A { type Ux = u8 ; } impl CCACT_01_CUACT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CCACT_01_CUACT_A { match self . bits { 0 => CCACT_01_CUACT_A :: CCACT_01_CUACT_DISABLED , 1 => CCACT_01_CUACT_A :: CCACT_01_CUACT_CCP_HIGH , 2 => CCACT_01_CUACT_A :: CCACT_01_CUACT_CCP_LOW , 3 => CCACT_01_CUACT_A :: CCACT_01_CUACT_CCP_TOGGLE , _ => unreachable ! () , } } # [doc = "DISABLED"] # [inline (always)] pub fn is_ccact_01_cuact_disabled (& self) -> bool { * self == CCACT_01_CUACT_A :: CCACT_01_CUACT_DISABLED } # [doc = "CCP_HIGH"] # [inline (always)] pub fn is_ccact_01_cuact_ccp_high (& self) -> bool { * self == CCACT_01_CUACT_A :: CCACT_01_CUACT_CCP_HIGH } # [doc = "CCP_LOW"] # [inline (always)] pub fn is_ccact_01_cuact_ccp_low (& self) -> bool { * self == CCACT_01_CUACT_A :: CCACT_01_CUACT_CCP_LOW } # [doc = "CCP_TOGGLE"] # [inline (always)] pub fn is_ccact_01_cuact_ccp_toggle (& self) -> bool { * self == CCACT_01_CUACT_A :: CCACT_01_CUACT_CCP_TOGGLE } } # [doc = "Field `CCACT_01_CUACT` writer - CCP Output Action on Compare (Up) This field describes the resulting action of the signal generator upon detecting a compare event while counting up."] pub type CCACT_01_CUACT_W < 'a , REG , const O : u8 > = crate :: FieldWriterSafe < 'a , REG , 2 , O , CCACT_01_CUACT_A > ; impl < 'a , REG , const O : u8 > CCACT_01_CUACT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "DISABLED"] # [inline (always)] pub fn ccact_01_cuact_disabled (self) -> & 'a mut crate :: W < REG > { self . variant (CCACT_01_CUACT_A :: CCACT_01_CUACT_DISABLED) } # [doc = "CCP_HIGH"] # [inline (always)] pub fn ccact_01_cuact_ccp_high (self) -> & 'a mut crate :: W < REG > { self . variant (CCACT_01_CUACT_A :: CCACT_01_CUACT_CCP_HIGH) } # [doc = "CCP_LOW"] # [inline (always)] pub fn ccact_01_cuact_ccp_low (self) -> & 'a mut crate :: W < REG > { self . variant (CCACT_01_CUACT_A :: CCACT_01_CUACT_CCP_LOW) } # [doc = "CCP_TOGGLE"] # [inline (always)] pub fn ccact_01_cuact_ccp_toggle (self) -> & 'a mut crate :: W < REG > { self . variant (CCACT_01_CUACT_A :: CCACT_01_CUACT_CCP_TOGGLE) } } # [doc = "Field `CCACT_01_CC2DACT` reader - CCP Output Action on CC2D event."] pub type CCACT_01_CC2DACT_R = crate :: FieldReader < CCACT_01_CC2DACT_A > ; # [doc = "CCP Output Action on CC2D event.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum CCACT_01_CC2DACT_A { # [doc = "0: DISABLED"] CCACT_01_CC2DACT_DISABLED = 0 , # [doc = "1: CCP_HIGH"] CCACT_01_CC2DACT_CCP_HIGH = 1 , # [doc = "2: CCP_LOW"] CCACT_01_CC2DACT_CCP_LOW = 2 , # [doc = "3: CCP_TOGGLE"] CCACT_01_CC2DACT_CCP_TOGGLE = 3 , } impl From < CCACT_01_CC2DACT_A > for u8 { # [inline (always)] fn from (variant : CCACT_01_CC2DACT_A) -> Self { variant as _ } } impl crate :: FieldSpec for CCACT_01_CC2DACT_A { type Ux = u8 ; } impl CCACT_01_CC2DACT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CCACT_01_CC2DACT_A { match self . bits { 0 => CCACT_01_CC2DACT_A :: CCACT_01_CC2DACT_DISABLED , 1 => CCACT_01_CC2DACT_A :: CCACT_01_CC2DACT_CCP_HIGH , 2 => CCACT_01_CC2DACT_A :: CCACT_01_CC2DACT_CCP_LOW , 3 => CCACT_01_CC2DACT_A :: CCACT_01_CC2DACT_CCP_TOGGLE , _ => unreachable ! () , } } # [doc = "DISABLED"] # [inline (always)] pub fn is_ccact_01_cc2dact_disabled (& self) -> bool { * self == CCACT_01_CC2DACT_A :: CCACT_01_CC2DACT_DISABLED } # [doc = "CCP_HIGH"] # [inline (always)] pub fn is_ccact_01_cc2dact_ccp_high (& self) -> bool { * self == CCACT_01_CC2DACT_A :: CCACT_01_CC2DACT_CCP_HIGH } # [doc = "CCP_LOW"] # [inline (always)] pub fn is_ccact_01_cc2dact_ccp_low (& self) -> bool { * self == CCACT_01_CC2DACT_A :: CCACT_01_CC2DACT_CCP_LOW } # [doc = "CCP_TOGGLE"] # [inline (always)] pub fn is_ccact_01_cc2dact_ccp_toggle (& self) -> bool { * self == CCACT_01_CC2DACT_A :: CCACT_01_CC2DACT_CCP_TOGGLE } } # [doc = "Field `CCACT_01_CC2DACT` writer - CCP Output Action on CC2D event."] pub type CCACT_01_CC2DACT_W < 'a , REG , const O : u8 > = crate :: FieldWriterSafe < 'a , REG , 2 , O , CCACT_01_CC2DACT_A > ; impl < 'a , REG , const O : u8 > CCACT_01_CC2DACT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "DISABLED"] # [inline (always)] pub fn ccact_01_cc2dact_disabled (self) -> & 'a mut crate :: W < REG > { self . variant (CCACT_01_CC2DACT_A :: CCACT_01_CC2DACT_DISABLED) } # [doc = "CCP_HIGH"] # [inline (always)] pub fn ccact_01_cc2dact_ccp_high (self) -> & 'a mut crate :: W < REG > { self . variant (CCACT_01_CC2DACT_A :: CCACT_01_CC2DACT_CCP_HIGH) } # [doc = "CCP_LOW"] # [inline (always)] pub fn ccact_01_cc2dact_ccp_low (self) -> & 'a mut crate :: W < REG > { self . variant (CCACT_01_CC2DACT_A :: CCACT_01_CC2DACT_CCP_LOW) } # [doc = "CCP_TOGGLE"] # [inline (always)] pub fn ccact_01_cc2dact_ccp_toggle (self) -> & 'a mut crate :: W < REG > { self . variant (CCACT_01_CC2DACT_A :: CCACT_01_CC2DACT_CCP_TOGGLE) } } # [doc = "Field `CCACT_01_CC2UACT` reader - CCP Output Action on CC2U event."] pub type CCACT_01_CC2UACT_R = crate :: FieldReader < CCACT_01_CC2UACT_A > ; # [doc = "CCP Output Action on CC2U event.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum CCACT_01_CC2UACT_A { # [doc = "0: DISABLED"] CCACT_01_CC2UACT_DISABLED = 0 , # [doc = "1: CCP_HIGH"] CCACT_01_CC2UACT_CCP_HIGH = 1 , # [doc = "2: CCP_LOW"] CCACT_01_CC2UACT_CCP_LOW = 2 , # [doc = "3: CCP_TOGGLE"] CCACT_01_CC2UACT_CCP_TOGGLE = 3 , } impl From < CCACT_01_CC2UACT_A > for u8 { # [inline (always)] fn from (variant : CCACT_01_CC2UACT_A) -> Self { variant as _ } } impl crate :: FieldSpec for CCACT_01_CC2UACT_A { type Ux = u8 ; } impl CCACT_01_CC2UACT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CCACT_01_CC2UACT_A { match self . bits { 0 => CCACT_01_CC2UACT_A :: CCACT_01_CC2UACT_DISABLED , 1 => CCACT_01_CC2UACT_A :: CCACT_01_CC2UACT_CCP_HIGH , 2 => CCACT_01_CC2UACT_A :: CCACT_01_CC2UACT_CCP_LOW , 3 => CCACT_01_CC2UACT_A :: CCACT_01_CC2UACT_CCP_TOGGLE , _ => unreachable ! () , } } # [doc = "DISABLED"] # [inline (always)] pub fn is_ccact_01_cc2uact_disabled (& self) -> bool { * self == CCACT_01_CC2UACT_A :: CCACT_01_CC2UACT_DISABLED } # [doc = "CCP_HIGH"] # [inline (always)] pub fn is_ccact_01_cc2uact_ccp_high (& self) -> bool { * self == CCACT_01_CC2UACT_A :: CCACT_01_CC2UACT_CCP_HIGH } # [doc = "CCP_LOW"] # [inline (always)] pub fn is_ccact_01_cc2uact_ccp_low (& self) -> bool { * self == CCACT_01_CC2UACT_A :: CCACT_01_CC2UACT_CCP_LOW } # [doc = "CCP_TOGGLE"] # [inline (always)] pub fn is_ccact_01_cc2uact_ccp_toggle (& self) -> bool { * self == CCACT_01_CC2UACT_A :: CCACT_01_CC2UACT_CCP_TOGGLE } } # [doc = "Field `CCACT_01_CC2UACT` writer - CCP Output Action on CC2U event."] pub type CCACT_01_CC2UACT_W < 'a , REG , const O : u8 > = crate :: FieldWriterSafe < 'a , REG , 2 , O , CCACT_01_CC2UACT_A > ; impl < 'a , REG , const O : u8 > CCACT_01_CC2UACT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "DISABLED"] # [inline (always)] pub fn ccact_01_cc2uact_disabled (self) -> & 'a mut crate :: W < REG > { self . variant (CCACT_01_CC2UACT_A :: CCACT_01_CC2UACT_DISABLED) } # [doc = "CCP_HIGH"] # [inline (always)] pub fn ccact_01_cc2uact_ccp_high (self) -> & 'a mut crate :: W < REG > { self . variant (CCACT_01_CC2UACT_A :: CCACT_01_CC2UACT_CCP_HIGH) } # [doc = "CCP_LOW"] # [inline (always)] pub fn ccact_01_cc2uact_ccp_low (self) -> & 'a mut crate :: W < REG > { self . variant (CCACT_01_CC2UACT_A :: CCACT_01_CC2UACT_CCP_LOW) } # [doc = "CCP_TOGGLE"] # [inline (always)] pub fn ccact_01_cc2uact_ccp_toggle (self) -> & 'a mut crate :: W < REG > { self . variant (CCACT_01_CC2UACT_A :: CCACT_01_CC2UACT_CCP_TOGGLE) } } # [doc = "Field `CCACT_01_SWFRCACT` reader - CCP Output Action on Software Froce Output This field describes the resulting action of software force. This action has a shadow register, which will be updated under specific condition. So that this register cannot take into effect immediately."] pub type CCACT_01_SWFRCACT_R = crate :: FieldReader < CCACT_01_SWFRCACT_A > ; # [doc = "CCP Output Action on Software Froce Output This field describes the resulting action of software force. This action has a shadow register, which will be updated under specific condition. So that this register cannot take into effect immediately.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum CCACT_01_SWFRCACT_A { # [doc = "0: DISABLED"] CCACT_01_SWFRCACT_DISABLED = 0 , # [doc = "1: CCP_HIGH"] CCACT_01_SWFRCACT_CCP_HIGH = 1 , # [doc = "2: CCP_LOW"] CCACT_01_SWFRCACT_CCP_LOW = 2 , } impl From < CCACT_01_SWFRCACT_A > for u8 { # [inline (always)] fn from (variant : CCACT_01_SWFRCACT_A) -> Self { variant as _ } } impl crate :: FieldSpec for CCACT_01_SWFRCACT_A { type Ux = u8 ; } impl CCACT_01_SWFRCACT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < CCACT_01_SWFRCACT_A > { match self . bits { 0 => Some (CCACT_01_SWFRCACT_A :: CCACT_01_SWFRCACT_DISABLED) , 1 => Some (CCACT_01_SWFRCACT_A :: CCACT_01_SWFRCACT_CCP_HIGH) , 2 => Some (CCACT_01_SWFRCACT_A :: CCACT_01_SWFRCACT_CCP_LOW) , _ => None , } } # [doc = "DISABLED"] # [inline (always)] pub fn is_ccact_01_swfrcact_disabled (& self) -> bool { * self == CCACT_01_SWFRCACT_A :: CCACT_01_SWFRCACT_DISABLED } # [doc = "CCP_HIGH"] # [inline (always)] pub fn is_ccact_01_swfrcact_ccp_high (& self) -> bool { * self == CCACT_01_SWFRCACT_A :: CCACT_01_SWFRCACT_CCP_HIGH } # [doc = "CCP_LOW"] # [inline (always)] pub fn is_ccact_01_swfrcact_ccp_low (& self) -> bool { * self == CCACT_01_SWFRCACT_A :: CCACT_01_SWFRCACT_CCP_LOW } } # [doc = "Field `CCACT_01_SWFRCACT` writer - CCP Output Action on Software Froce Output This field describes the resulting action of software force. This action has a shadow register, which will be updated under specific condition. So that this register cannot take into effect immediately."] pub type CCACT_01_SWFRCACT_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 2 , O , CCACT_01_SWFRCACT_A > ; impl < 'a , REG , const O : u8 > CCACT_01_SWFRCACT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "DISABLED"] # [inline (always)] pub fn ccact_01_swfrcact_disabled (self) -> & 'a mut crate :: W < REG > { self . variant (CCACT_01_SWFRCACT_A :: CCACT_01_SWFRCACT_DISABLED) } # [doc = "CCP_HIGH"] # [inline (always)] pub fn ccact_01_swfrcact_ccp_high (self) -> & 'a mut crate :: W < REG > { self . variant (CCACT_01_SWFRCACT_A :: CCACT_01_SWFRCACT_CCP_HIGH) } # [doc = "CCP_LOW"] # [inline (always)] pub fn ccact_01_swfrcact_ccp_low (self) -> & 'a mut crate :: W < REG > { self . variant (CCACT_01_SWFRCACT_A :: CCACT_01_SWFRCACT_CCP_LOW) } } impl R { # [doc = "Bits 0:1 - CCP Output Action on Zero Specifies what changes occur to CCP output as the result of a zero event."] # [inline (always)] pub fn ccact_01_zact (& self) -> CCACT_01_ZACT_R { CCACT_01_ZACT_R :: new ((self . bits & 3) as u8) } # [doc = "Bits 3:4 - CCP Output Action on Load Specifies what changes occur to CCP output as the result of a load event."] # [inline (always)] pub fn ccact_01_lact (& self) -> CCACT_01_LACT_R { CCACT_01_LACT_R :: new (((self . bits >> 3) & 3) as u8) } # [doc = "Bits 6:7 - CCP Output Action on Compare (Down) This field describes the resulting action of the signal generator upon detecting a compare event while counting down."] # [inline (always)] pub fn ccact_01_cdact (& self) -> CCACT_01_CDACT_R { CCACT_01_CDACT_R :: new (((self . bits >> 6) & 3) as u8) } # [doc = "Bits 9:10 - CCP Output Action on Compare (Up) This field describes the resulting action of the signal generator upon detecting a compare event while counting up."] # [inline (always)] pub fn ccact_01_cuact (& self) -> CCACT_01_CUACT_R { CCACT_01_CUACT_R :: new (((self . bits >> 9) & 3) as u8) } # [doc = "Bits 12:13 - CCP Output Action on CC2D event."] # [inline (always)] pub fn ccact_01_cc2dact (& self) -> CCACT_01_CC2DACT_R { CCACT_01_CC2DACT_R :: new (((self . bits >> 12) & 3) as u8) } # [doc = "Bits 15:16 - CCP Output Action on CC2U event."] # [inline (always)] pub fn ccact_01_cc2uact (& self) -> CCACT_01_CC2UACT_R { CCACT_01_CC2UACT_R :: new (((self . bits >> 15) & 3) as u8) } # [doc = "Bits 28:29 - CCP Output Action on Software Froce Output This field describes the resulting action of software force. This action has a shadow register, which will be updated under specific condition. So that this register cannot take into effect immediately."] # [inline (always)] pub fn ccact_01_swfrcact (& self) -> CCACT_01_SWFRCACT_R { CCACT_01_SWFRCACT_R :: new (((self . bits >> 28) & 3) as u8) } } impl W { # [doc = "Bits 0:1 - CCP Output Action on Zero Specifies what changes occur to CCP output as the result of a zero event."] # [inline (always)] # [must_use] pub fn ccact_01_zact (& mut self) -> CCACT_01_ZACT_W < CCACT_01_SPEC , 0 > { CCACT_01_ZACT_W :: new (self) } # [doc = "Bits 3:4 - CCP Output Action on Load Specifies what changes occur to CCP output as the result of a load event."] # [inline (always)] # [must_use] pub fn ccact_01_lact (& mut self) -> CCACT_01_LACT_W <'_, CCACT_01_SPEC , 3 > { CCACT_01_LACT_W :: new (self) } # [doc = "Bits 6:7 - CCP Output Action on Compare (Down) This field describes the resulting action of the signal generator upon detecting a compare event while counting down."] # [inline (always)] # [must_use] pub fn ccact_01_cdact (& mut self) -> CCACT_01_CDACT_W < CCACT_01_SPEC , 6 > { CCACT_01_CDACT_W :: new (self) } # [doc = "Bits 9:10 - CCP Output Action on Compare (Up) This field describes the resulting action of the signal generator upon detecting a compare event while counting up."] # [inline (always)] # [must_use] pub fn ccact_01_cuact (& mut self) -> CCACT_01_CUACT_W < CCACT_01_SPEC , 9 > { CCACT_01_CUACT_W :: new (self) } # [doc = "Bits 12:13 - CCP Output Action on CC2D event."] # [inline (always)] # [must_use] pub fn ccact_01_cc2dact (& mut self) -> CCACT_01_CC2DACT_W < CCACT_01_SPEC , 12 > { CCACT_01_CC2DACT_W :: new (self) } # [doc = "Bits 15:16 - CCP Output Action on CC2U event."] # [inline (always)] # [must_use] pub fn ccact_01_cc2uact (& mut self) -> CCACT_01_CC2UACT_W < CCACT_01_SPEC , 15 > { CCACT_01_CC2UACT_W :: new (self) } # [doc = "Bits 28:29 - CCP Output Action on Software Froce Output This field describes the resulting action of software force. This action has a shadow register, which will be updated under specific condition. So that this register cannot take into effect immediately."] # [inline (always)] # [must_use] pub fn ccact_01_swfrcact (& mut self) -> CCACT_01_SWFRCACT_W < CCACT_01_SPEC , 28 > { CCACT_01_SWFRCACT_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Capture or Compare Action Registers\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ccact_01::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ccact_01::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CCACT_01_SPEC ; impl crate :: RegisterSpec for CCACT_01_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`ccact_01::R`](R) reader structure"] impl crate :: Readable for CCACT_01_SPEC { } # [doc = "`write(|w| ..)` method takes [`ccact_01::W`](W) writer structure"] impl crate :: Writable for CCACT_01_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets CCACT_01[%s] [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/i2c1/int_event2_iset.rs:1:5345 [INFO] [stdout] | [INFO] [stdout] 1 | ...t_mrxfifotrg (& mut self) -> INT_EVENT2_ISET_MRXFIFOTRG_W < INT_EVENT2_ISET_SPEC , 0 > { INT_EVENT2_ISET_MRXFIFOTRG_W :: new (self) } ... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `INT_EVENT2_ISET` writer"] pub type W = crate :: W < INT_EVENT2_ISET_SPEC > ; # [doc = "Master Receive FIFO Trigger Trigger when RX FIFO contains &gt;= defined bytes\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT2_ISET_MRXFIFOTRG_AW { # [doc = "0: NO_EFFECT"] INT_EVENT2_ISET_MRXFIFOTRG_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT2_ISET_MRXFIFOTRG_SET = 1 , } impl From < INT_EVENT2_ISET_MRXFIFOTRG_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT2_ISET_MRXFIFOTRG_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT2_ISET_MRXFIFOTRG` writer - Master Receive FIFO Trigger Trigger when RX FIFO contains &gt;= defined bytes"] pub type INT_EVENT2_ISET_MRXFIFOTRG_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT2_ISET_MRXFIFOTRG_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT2_ISET_MRXFIFOTRG_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event2_iset_mrxfifotrg_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT2_ISET_MRXFIFOTRG_AW :: INT_EVENT2_ISET_MRXFIFOTRG_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event2_iset_mrxfifotrg_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT2_ISET_MRXFIFOTRG_AW :: INT_EVENT2_ISET_MRXFIFOTRG_SET) } } # [doc = "Master Transmit FIFO Trigger Trigger when Transmit FIFO contains &lt;= defined bytes\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT2_ISET_MTXFIFOTRG_AW { # [doc = "0: NO_EFFECT"] INT_EVENT2_ISET_MTXFIFOTRG_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT2_ISET_MTXFIFOTRG_SET = 1 , } impl From < INT_EVENT2_ISET_MTXFIFOTRG_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT2_ISET_MTXFIFOTRG_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT2_ISET_MTXFIFOTRG` writer - Master Transmit FIFO Trigger Trigger when Transmit FIFO contains &lt;= defined bytes"] pub type INT_EVENT2_ISET_MTXFIFOTRG_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT2_ISET_MTXFIFOTRG_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT2_ISET_MTXFIFOTRG_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event2_iset_mtxfifotrg_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT2_ISET_MTXFIFOTRG_AW :: INT_EVENT2_ISET_MTXFIFOTRG_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event2_iset_mtxfifotrg_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT2_ISET_MTXFIFOTRG_AW :: INT_EVENT2_ISET_MTXFIFOTRG_SET) } } # [doc = "Slave Receive FIFO Trigger\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT2_ISET_SRXFIFOTRG_AW { # [doc = "0: NO_EFFECT"] INT_EVENT2_ISET_SRXFIFOTRG_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT2_ISET_SRXFIFOTRG_SET = 1 , } impl From < INT_EVENT2_ISET_SRXFIFOTRG_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT2_ISET_SRXFIFOTRG_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT2_ISET_SRXFIFOTRG` writer - Slave Receive FIFO Trigger"] pub type INT_EVENT2_ISET_SRXFIFOTRG_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT2_ISET_SRXFIFOTRG_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT2_ISET_SRXFIFOTRG_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event2_iset_srxfifotrg_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT2_ISET_SRXFIFOTRG_AW :: INT_EVENT2_ISET_SRXFIFOTRG_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event2_iset_srxfifotrg_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT2_ISET_SRXFIFOTRG_AW :: INT_EVENT2_ISET_SRXFIFOTRG_SET) } } # [doc = "Slave Transmit FIFO Trigger\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT2_ISET_STXFIFOTRG_AW { # [doc = "0: NO_EFFECT"] INT_EVENT2_ISET_STXFIFOTRG_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT2_ISET_STXFIFOTRG_SET = 1 , } impl From < INT_EVENT2_ISET_STXFIFOTRG_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT2_ISET_STXFIFOTRG_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT2_ISET_STXFIFOTRG` writer - Slave Transmit FIFO Trigger"] pub type INT_EVENT2_ISET_STXFIFOTRG_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT2_ISET_STXFIFOTRG_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT2_ISET_STXFIFOTRG_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event2_iset_stxfifotrg_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT2_ISET_STXFIFOTRG_AW :: INT_EVENT2_ISET_STXFIFOTRG_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event2_iset_stxfifotrg_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT2_ISET_STXFIFOTRG_AW :: INT_EVENT2_ISET_STXFIFOTRG_SET) } } impl W { # [doc = "Bit 0 - Master Receive FIFO Trigger Trigger when RX FIFO contains &gt;= defined bytes"] # [inline (always)] # [must_use] pub fn int_event2_iset_mrxfifotrg (& mut self) -> INT_EVENT2_ISET_MRXFIFOTRG_W <'_, INT_EVENT2_ISET_SPEC , 0 > { INT_EVENT2_ISET_MRXFIFOTRG_W :: new (self) } # [doc = "Bit 1 - Master Transmit FIFO Trigger Trigger when Transmit FIFO contains &lt;= defined bytes"] # [inline (always)] # [must_use] pub fn int_event2_iset_mtxfifotrg (& mut self) -> INT_EVENT2_ISET_MTXFIFOTRG_W < INT_EVENT2_ISET_SPEC , 1 > { INT_EVENT2_ISET_MTXFIFOTRG_W :: new (self) } # [doc = "Bit 2 - Slave Receive FIFO Trigger"] # [inline (always)] # [must_use] pub fn int_event2_iset_srxfifotrg (& mut self) -> INT_EVENT2_ISET_SRXFIFOTRG_W < INT_EVENT2_ISET_SPEC , 2 > { INT_EVENT2_ISET_SRXFIFOTRG_W :: new (self) } # [doc = "Bit 3 - Slave Transmit FIFO Trigger"] # [inline (always)] # [must_use] pub fn int_event2_iset_stxfifotrg (& mut self) -> INT_EVENT2_ISET_STXFIFOTRG_W < INT_EVENT2_ISET_SPEC , 3 > { INT_EVENT2_ISET_STXFIFOTRG_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Interrupt set\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_event2_iset::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct INT_EVENT2_ISET_SPEC ; impl crate :: RegisterSpec for INT_EVENT2_ISET_SPEC { type Ux = u32 ; } # [doc = "`write(|w| ..)` method takes [`int_event2_iset::W`](W) writer structure"] impl crate :: Writable for INT_EVENT2_ISET_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets INT_EVENT2_ISET to value 0"] impl crate :: Resettable for INT_EVENT2_ISET_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/i2c0/int_event0_iset.rs:1:39704 [INFO] [stdout] | [INFO] [stdout] 1 | ...ent0_iset_mnack (& mut self) -> INT_EVENT0_ISET_MNACK_W < INT_EVENT0_ISET_SPEC , 7 > { INT_EVENT0_ISET_MNACK_W :: new (self) } # [doc ... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `INT_EVENT0_ISET` writer"] pub type W = crate :: W < INT_EVENT0_ISET_SPEC > ; # [doc = "Master Receive Data Interrupt Signals that a byte has been received\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_MRXDONE_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_MRXDONE_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_MRXDONE_SET = 1 , } impl From < INT_EVENT0_ISET_MRXDONE_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_MRXDONE_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_MRXDONE` writer - Master Receive Data Interrupt Signals that a byte has been received"] pub type INT_EVENT0_ISET_MRXDONE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_MRXDONE_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_MRXDONE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_mrxdone_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MRXDONE_AW :: INT_EVENT0_ISET_MRXDONE_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_mrxdone_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MRXDONE_AW :: INT_EVENT0_ISET_MRXDONE_SET) } } # [doc = "Master Transmit Transaction completed Interrupt\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_MTXDONE_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_MTXDONE_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_MTXDONE_SET = 1 , } impl From < INT_EVENT0_ISET_MTXDONE_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_MTXDONE_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_MTXDONE` writer - Master Transmit Transaction completed Interrupt"] pub type INT_EVENT0_ISET_MTXDONE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_MTXDONE_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_MTXDONE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_mtxdone_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MTXDONE_AW :: INT_EVENT0_ISET_MTXDONE_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_mtxdone_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MTXDONE_AW :: INT_EVENT0_ISET_MTXDONE_SET) } } # [doc = "Master Receive FIFO Trigger Trigger when RX FIFO contains &gt;= defined bytes\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_MRXFIFOTRG_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_MRXFIFOTRG_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_MRXFIFOTRG_SET = 1 , } impl From < INT_EVENT0_ISET_MRXFIFOTRG_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_MRXFIFOTRG_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_MRXFIFOTRG` writer - Master Receive FIFO Trigger Trigger when RX FIFO contains &gt;= defined bytes"] pub type INT_EVENT0_ISET_MRXFIFOTRG_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_MRXFIFOTRG_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_MRXFIFOTRG_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_mrxfifotrg_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MRXFIFOTRG_AW :: INT_EVENT0_ISET_MRXFIFOTRG_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_mrxfifotrg_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MRXFIFOTRG_AW :: INT_EVENT0_ISET_MRXFIFOTRG_SET) } } # [doc = "Master Transmit FIFO Trigger Trigger when Transmit FIFO contains &lt;= defined bytes\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_MTXFIFOTRG_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_MTXFIFOTRG_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_MTXFIFOTRG_SET = 1 , } impl From < INT_EVENT0_ISET_MTXFIFOTRG_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_MTXFIFOTRG_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_MTXFIFOTRG` writer - Master Transmit FIFO Trigger Trigger when Transmit FIFO contains &lt;= defined bytes"] pub type INT_EVENT0_ISET_MTXFIFOTRG_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_MTXFIFOTRG_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_MTXFIFOTRG_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_mtxfifotrg_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MTXFIFOTRG_AW :: INT_EVENT0_ISET_MTXFIFOTRG_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_mtxfifotrg_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MTXFIFOTRG_AW :: INT_EVENT0_ISET_MTXFIFOTRG_SET) } } # [doc = "RXFIFO full event.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_MRXFIFOFULL_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_MRXFIFOFULL_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_MRXFIFOFULL_SET = 1 , } impl From < INT_EVENT0_ISET_MRXFIFOFULL_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_MRXFIFOFULL_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_MRXFIFOFULL` writer - RXFIFO full event."] pub type INT_EVENT0_ISET_MRXFIFOFULL_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_MRXFIFOFULL_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_MRXFIFOFULL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_mrxfifofull_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MRXFIFOFULL_AW :: INT_EVENT0_ISET_MRXFIFOFULL_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_mrxfifofull_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MRXFIFOFULL_AW :: INT_EVENT0_ISET_MRXFIFOFULL_SET) } } # [doc = "Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_MTXEMPTY_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_MTXEMPTY_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_MTXEMPTY_SET = 1 , } impl From < INT_EVENT0_ISET_MTXEMPTY_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_MTXEMPTY_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_MTXEMPTY` writer - Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode."] pub type INT_EVENT0_ISET_MTXEMPTY_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_MTXEMPTY_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_MTXEMPTY_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_mtxempty_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MTXEMPTY_AW :: INT_EVENT0_ISET_MTXEMPTY_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_mtxempty_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MTXEMPTY_AW :: INT_EVENT0_ISET_MTXEMPTY_SET) } } # [doc = "Address/Data NACK Interrupt\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_MNACK_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_MNACK_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_MNACK_SET = 1 , } impl From < INT_EVENT0_ISET_MNACK_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_MNACK_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_MNACK` writer - Address/Data NACK Interrupt"] pub type INT_EVENT0_ISET_MNACK_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_MNACK_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_MNACK_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_mnack_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MNACK_AW :: INT_EVENT0_ISET_MNACK_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_mnack_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MNACK_AW :: INT_EVENT0_ISET_MNACK_SET) } } # [doc = "START Detection Interrupt\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_MSTART_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_MSTART_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_MSTART_SET = 1 , } impl From < INT_EVENT0_ISET_MSTART_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_MSTART_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_MSTART` writer - START Detection Interrupt"] pub type INT_EVENT0_ISET_MSTART_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_MSTART_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_MSTART_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_mstart_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MSTART_AW :: INT_EVENT0_ISET_MSTART_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_mstart_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MSTART_AW :: INT_EVENT0_ISET_MSTART_SET) } } # [doc = "STOP Detection Interrupt\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_MSTOP_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_MSTOP_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_MSTOP_SET = 1 , } impl From < INT_EVENT0_ISET_MSTOP_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_MSTOP_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_MSTOP` writer - STOP Detection Interrupt"] pub type INT_EVENT0_ISET_MSTOP_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_MSTOP_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_MSTOP_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_mstop_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MSTOP_AW :: INT_EVENT0_ISET_MSTOP_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_mstop_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MSTOP_AW :: INT_EVENT0_ISET_MSTOP_SET) } } # [doc = "Arbitration Lost Interrupt\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_MARBLOST_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_MARBLOST_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_MARBLOST_SET = 1 , } impl From < INT_EVENT0_ISET_MARBLOST_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_MARBLOST_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_MARBLOST` writer - Arbitration Lost Interrupt"] pub type INT_EVENT0_ISET_MARBLOST_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_MARBLOST_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_MARBLOST_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_marblost_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MARBLOST_AW :: INT_EVENT0_ISET_MARBLOST_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_marblost_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MARBLOST_AW :: INT_EVENT0_ISET_MARBLOST_SET) } } # [doc = "DMA Done 1 on Event Channel 2\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_MDMA_DONE1_2_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_MDMA_DONE1_2_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_MDMA_DONE1_2_SET = 1 , } impl From < INT_EVENT0_ISET_MDMA_DONE1_2_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_MDMA_DONE1_2_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_MDMA_DONE1_2` writer - DMA Done 1 on Event Channel 2"] pub type INT_EVENT0_ISET_MDMA_DONE1_2_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_MDMA_DONE1_2_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_MDMA_DONE1_2_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_mdma_done1_2_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MDMA_DONE1_2_AW :: INT_EVENT0_ISET_MDMA_DONE1_2_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_mdma_done1_2_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MDMA_DONE1_2_AW :: INT_EVENT0_ISET_MDMA_DONE1_2_SET) } } # [doc = "DMA Done 1 on Event Channel 3\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_MDMA_DONE1_3_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_MDMA_DONE1_3_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_MDMA_DONE1_3_SET = 1 , } impl From < INT_EVENT0_ISET_MDMA_DONE1_3_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_MDMA_DONE1_3_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_MDMA_DONE1_3` writer - DMA Done 1 on Event Channel 3"] pub type INT_EVENT0_ISET_MDMA_DONE1_3_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_MDMA_DONE1_3_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_MDMA_DONE1_3_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_mdma_done1_3_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MDMA_DONE1_3_AW :: INT_EVENT0_ISET_MDMA_DONE1_3_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_mdma_done1_3_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MDMA_DONE1_3_AW :: INT_EVENT0_ISET_MDMA_DONE1_3_SET) } } # [doc = "Master RX Pec Error Interrupt\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_MPEC_RX_ERR_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_MPEC_RX_ERR_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_MPEC_RX_ERR_SET = 1 , } impl From < INT_EVENT0_ISET_MPEC_RX_ERR_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_MPEC_RX_ERR_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_MPEC_RX_ERR` writer - Master RX Pec Error Interrupt"] pub type INT_EVENT0_ISET_MPEC_RX_ERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_MPEC_RX_ERR_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_MPEC_RX_ERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_mpec_rx_err_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MPEC_RX_ERR_AW :: INT_EVENT0_ISET_MPEC_RX_ERR_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_mpec_rx_err_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MPEC_RX_ERR_AW :: INT_EVENT0_ISET_MPEC_RX_ERR_SET) } } # [doc = "Timeout A interrupt\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_TIMEOUTA_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_TIMEOUTA_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_TIMEOUTA_SET = 1 , } impl From < INT_EVENT0_ISET_TIMEOUTA_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_TIMEOUTA_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_TIMEOUTA` writer - Timeout A interrupt"] pub type INT_EVENT0_ISET_TIMEOUTA_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_TIMEOUTA_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_TIMEOUTA_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_timeouta_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_TIMEOUTA_AW :: INT_EVENT0_ISET_TIMEOUTA_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_timeouta_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_TIMEOUTA_AW :: INT_EVENT0_ISET_TIMEOUTA_SET) } } # [doc = "Timeout B Interrupt\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_TIMEOUTB_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_TIMEOUTB_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_TIMEOUTB_SET = 1 , } impl From < INT_EVENT0_ISET_TIMEOUTB_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_TIMEOUTB_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_TIMEOUTB` writer - Timeout B Interrupt"] pub type INT_EVENT0_ISET_TIMEOUTB_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_TIMEOUTB_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_TIMEOUTB_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_timeoutb_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_TIMEOUTB_AW :: INT_EVENT0_ISET_TIMEOUTB_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_timeoutb_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_TIMEOUTB_AW :: INT_EVENT0_ISET_TIMEOUTB_SET) } } # [doc = "Slave Receive Data Interrupt Signals that a byte has been received\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_SRXDONE_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_SRXDONE_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_SRXDONE_SET = 1 , } impl From < INT_EVENT0_ISET_SRXDONE_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_SRXDONE_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_SRXDONE` writer - Slave Receive Data Interrupt Signals that a byte has been received"] pub type INT_EVENT0_ISET_SRXDONE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_SRXDONE_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_SRXDONE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_srxdone_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_SRXDONE_AW :: INT_EVENT0_ISET_SRXDONE_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_srxdone_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_SRXDONE_AW :: INT_EVENT0_ISET_SRXDONE_SET) } } # [doc = "Slave Transmit Transaction completed Interrupt\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_STXDONE_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_STXDONE_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_STXDONE_SET = 1 , } impl From < INT_EVENT0_ISET_STXDONE_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_STXDONE_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_STXDONE` writer - Slave Transmit Transaction completed Interrupt"] pub type INT_EVENT0_ISET_STXDONE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_STXDONE_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_STXDONE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_stxdone_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_STXDONE_AW :: INT_EVENT0_ISET_STXDONE_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_stxdone_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_STXDONE_AW :: INT_EVENT0_ISET_STXDONE_SET) } } # [doc = "Slave Receive FIFO Trigger\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_SRXFIFOTRG_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_SRXFIFOTRG_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_SRXFIFOTRG_SET = 1 , } impl From < INT_EVENT0_ISET_SRXFIFOTRG_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_SRXFIFOTRG_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_SRXFIFOTRG` writer - Slave Receive FIFO Trigger"] pub type INT_EVENT0_ISET_SRXFIFOTRG_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_SRXFIFOTRG_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_SRXFIFOTRG_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_srxfifotrg_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_SRXFIFOTRG_AW :: INT_EVENT0_ISET_SRXFIFOTRG_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_srxfifotrg_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_SRXFIFOTRG_AW :: INT_EVENT0_ISET_SRXFIFOTRG_SET) } } # [doc = "Slave Transmit FIFO Trigger\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_STXFIFOTRG_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_STXFIFOTRG_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_STXFIFOTRG_SET = 1 , } impl From < INT_EVENT0_ISET_STXFIFOTRG_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_STXFIFOTRG_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_STXFIFOTRG` writer - Slave Transmit FIFO Trigger"] pub type INT_EVENT0_ISET_STXFIFOTRG_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_STXFIFOTRG_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_STXFIFOTRG_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_stxfifotrg_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_STXFIFOTRG_AW :: INT_EVENT0_ISET_STXFIFOTRG_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_stxfifotrg_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_STXFIFOTRG_AW :: INT_EVENT0_ISET_STXFIFOTRG_SET) } } # [doc = "RXFIFO full event. This interrupt is set if an RX FIFO is full.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_SRXFIFOFULL_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_SRXFIFOFULL_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_SRXFIFOFULL_SET = 1 , } impl From < INT_EVENT0_ISET_SRXFIFOFULL_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_SRXFIFOFULL_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_SRXFIFOFULL` writer - RXFIFO full event. This interrupt is set if an RX FIFO is full."] pub type INT_EVENT0_ISET_SRXFIFOFULL_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_SRXFIFOFULL_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_SRXFIFOFULL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_srxfifofull_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_SRXFIFOFULL_AW :: INT_EVENT0_ISET_SRXFIFOFULL_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_srxfifofull_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_SRXFIFOFULL_AW :: INT_EVENT0_ISET_SRXFIFOFULL_SET) } } # [doc = "Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_STXEMPTY_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_STXEMPTY_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_STXEMPTY_SET = 1 , } impl From < INT_EVENT0_ISET_STXEMPTY_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_STXEMPTY_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_STXEMPTY` writer - Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode."] pub type INT_EVENT0_ISET_STXEMPTY_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_STXEMPTY_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_STXEMPTY_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_stxempty_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_STXEMPTY_AW :: INT_EVENT0_ISET_STXEMPTY_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_stxempty_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_STXEMPTY_AW :: INT_EVENT0_ISET_STXEMPTY_SET) } } # [doc = "Start Condition Interrupt\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_SSTART_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_SSTART_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_SSTART_SET = 1 , } impl From < INT_EVENT0_ISET_SSTART_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_SSTART_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_SSTART` writer - Start Condition Interrupt"] pub type INT_EVENT0_ISET_SSTART_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_SSTART_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_SSTART_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_sstart_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_SSTART_AW :: INT_EVENT0_ISET_SSTART_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_sstart_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_SSTART_AW :: INT_EVENT0_ISET_SSTART_SET) } } # [doc = "Stop Condition Interrupt\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_SSTOP_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_SSTOP_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_SSTOP_SET = 1 , } impl From < INT_EVENT0_ISET_SSTOP_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_SSTOP_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_SSTOP` writer - Stop Condition Interrupt"] pub type INT_EVENT0_ISET_SSTOP_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_SSTOP_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_SSTOP_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_sstop_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_SSTOP_AW :: INT_EVENT0_ISET_SSTOP_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_sstop_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_SSTOP_AW :: INT_EVENT0_ISET_SSTOP_SET) } } # [doc = "General Call Interrupt\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_SGENCALL_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_SGENCALL_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_SGENCALL_SET = 1 , } impl From < INT_EVENT0_ISET_SGENCALL_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_SGENCALL_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_SGENCALL` writer - General Call Interrupt"] pub type INT_EVENT0_ISET_SGENCALL_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_SGENCALL_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_SGENCALL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_sgencall_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_SGENCALL_AW :: INT_EVENT0_ISET_SGENCALL_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_sgencall_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_SGENCALL_AW :: INT_EVENT0_ISET_SGENCALL_SET) } } # [doc = "DMA Done 1 on Event Channel 2\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_SDMA_DONE1_2_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_SDMA_DONE1_2_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_SDMA_DONE1_2_SET = 1 , } impl From < INT_EVENT0_ISET_SDMA_DONE1_2_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_SDMA_DONE1_2_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_SDMA_DONE1_2` writer - DMA Done 1 on Event Channel 2"] pub type INT_EVENT0_ISET_SDMA_DONE1_2_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_SDMA_DONE1_2_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_SDMA_DONE1_2_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_sdma_done1_2_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_SDMA_DONE1_2_AW :: INT_EVENT0_ISET_SDMA_DONE1_2_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_sdma_done1_2_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_SDMA_DONE1_2_AW :: INT_EVENT0_ISET_SDMA_DONE1_2_SET) } } # [doc = "DMA Done 1 on Event Channel 3\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_SDMA_DONE1_3_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_SDMA_DONE1_3_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_SDMA_DONE1_3_SET = 1 , } impl From < INT_EVENT0_ISET_SDMA_DONE1_3_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_SDMA_DONE1_3_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_SDMA_DONE1_3` writer - DMA Done 1 on Event Channel 3"] pub type INT_EVENT0_ISET_SDMA_DONE1_3_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_SDMA_DONE1_3_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_SDMA_DONE1_3_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_sdma_done1_3_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_SDMA_DONE1_3_AW :: INT_EVENT0_ISET_SDMA_DONE1_3_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_sdma_done1_3_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_SDMA_DONE1_3_AW :: INT_EVENT0_ISET_SDMA_DONE1_3_SET) } } # [doc = "Slave RX Pec Error Interrupt\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_SPEC_RX_ERR_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_SPEC_RX_ERR_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_SPEC_RX_ERR_SET = 1 , } impl From < INT_EVENT0_ISET_SPEC_RX_ERR_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_SPEC_RX_ERR_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_SPEC_RX_ERR` writer - Slave RX Pec Error Interrupt"] pub type INT_EVENT0_ISET_SPEC_RX_ERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_SPEC_RX_ERR_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_SPEC_RX_ERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_spec_rx_err_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_SPEC_RX_ERR_AW :: INT_EVENT0_ISET_SPEC_RX_ERR_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_spec_rx_err_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_SPEC_RX_ERR_AW :: INT_EVENT0_ISET_SPEC_RX_ERR_SET) } } # [doc = "Slave TX FIFO underflow\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_STX_UNFL_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_STX_UNFL_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_STX_UNFL_SET = 1 , } impl From < INT_EVENT0_ISET_STX_UNFL_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_STX_UNFL_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_STX_UNFL` writer - Slave TX FIFO underflow"] pub type INT_EVENT0_ISET_STX_UNFL_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_STX_UNFL_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_STX_UNFL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_stx_unfl_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_STX_UNFL_AW :: INT_EVENT0_ISET_STX_UNFL_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_stx_unfl_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_STX_UNFL_AW :: INT_EVENT0_ISET_STX_UNFL_SET) } } # [doc = "Slave RX FIFO overflow\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_SRX_OVFL_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_SRX_OVFL_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_SRX_OVFL_SET = 1 , } impl From < INT_EVENT0_ISET_SRX_OVFL_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_SRX_OVFL_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_SRX_OVFL` writer - Slave RX FIFO overflow"] pub type INT_EVENT0_ISET_SRX_OVFL_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_SRX_OVFL_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_SRX_OVFL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_srx_ovfl_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_SRX_OVFL_AW :: INT_EVENT0_ISET_SRX_OVFL_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_srx_ovfl_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_SRX_OVFL_AW :: INT_EVENT0_ISET_SRX_OVFL_SET) } } # [doc = "Slave Arbitration Lost\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_SARBLOST_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_SARBLOST_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_SARBLOST_SET = 1 , } impl From < INT_EVENT0_ISET_SARBLOST_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_SARBLOST_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_SARBLOST` writer - Slave Arbitration Lost"] pub type INT_EVENT0_ISET_SARBLOST_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_SARBLOST_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_SARBLOST_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_sarblost_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_SARBLOST_AW :: INT_EVENT0_ISET_SARBLOST_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_sarblost_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_SARBLOST_AW :: INT_EVENT0_ISET_SARBLOST_SET) } } # [doc = "Interrupt overflow\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_INTR_OVFL_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_INTR_OVFL_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_INTR_OVFL_SET = 1 , } impl From < INT_EVENT0_ISET_INTR_OVFL_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_INTR_OVFL_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_INTR_OVFL` writer - Interrupt overflow"] pub type INT_EVENT0_ISET_INTR_OVFL_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_INTR_OVFL_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_INTR_OVFL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_intr_ovfl_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_INTR_OVFL_AW :: INT_EVENT0_ISET_INTR_OVFL_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_intr_ovfl_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_INTR_OVFL_AW :: INT_EVENT0_ISET_INTR_OVFL_SET) } } impl W { # [doc = "Bit 0 - Master Receive Data Interrupt Signals that a byte has been received"] # [inline (always)] # [must_use] pub fn int_event0_iset_mrxdone (& mut self) -> INT_EVENT0_ISET_MRXDONE_W < INT_EVENT0_ISET_SPEC , 0 > { INT_EVENT0_ISET_MRXDONE_W :: new (self) } # [doc = "Bit 1 - Master Transmit Transaction completed Interrupt"] # [inline (always)] # [must_use] pub fn int_event0_iset_mtxdone (& mut self) -> INT_EVENT0_ISET_MTXDONE_W < INT_EVENT0_ISET_SPEC , 1 > { INT_EVENT0_ISET_MTXDONE_W :: new (self) } # [doc = "Bit 2 - Master Receive FIFO Trigger Trigger when RX FIFO contains &gt;= defined bytes"] # [inline (always)] # [must_use] pub fn int_event0_iset_mrxfifotrg (& mut self) -> INT_EVENT0_ISET_MRXFIFOTRG_W < INT_EVENT0_ISET_SPEC , 2 > { INT_EVENT0_ISET_MRXFIFOTRG_W :: new (self) } # [doc = "Bit 3 - Master Transmit FIFO Trigger Trigger when Transmit FIFO contains &lt;= defined bytes"] # [inline (always)] # [must_use] pub fn int_event0_iset_mtxfifotrg (& mut self) -> INT_EVENT0_ISET_MTXFIFOTRG_W < INT_EVENT0_ISET_SPEC , 3 > { INT_EVENT0_ISET_MTXFIFOTRG_W :: new (self) } # [doc = "Bit 4 - RXFIFO full event."] # [inline (always)] # [must_use] pub fn int_event0_iset_mrxfifofull (& mut self) -> INT_EVENT0_ISET_MRXFIFOFULL_W < INT_EVENT0_ISET_SPEC , 4 > { INT_EVENT0_ISET_MRXFIFOFULL_W :: new (self) } # [doc = "Bit 5 - Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode."] # [inline (always)] # [must_use] pub fn int_event0_iset_mtxempty (& mut self) -> INT_EVENT0_ISET_MTXEMPTY_W < INT_EVENT0_ISET_SPEC , 5 > { INT_EVENT0_ISET_MTXEMPTY_W :: new (self) } # [doc = "Bit 7 - Address/Data NACK Interrupt"] # [inline (always)] # [must_use] pub fn int_event0_iset_mnack (& mut self) -> INT_EVENT0_ISET_MNACK_W <'_, INT_EVENT0_ISET_SPEC , 7 > { INT_EVENT0_ISET_MNACK_W :: new (self) } # [doc = "Bit 8 - START Detection Interrupt"] # [inline (always)] # [must_use] pub fn int_event0_iset_mstart (& mut self) -> INT_EVENT0_ISET_MSTART_W < INT_EVENT0_ISET_SPEC , 8 > { INT_EVENT0_ISET_MSTART_W :: new (self) } # [doc = "Bit 9 - STOP Detection Interrupt"] # [inline (always)] # [must_use] pub fn int_event0_iset_mstop (& mut self) -> INT_EVENT0_ISET_MSTOP_W < INT_EVENT0_ISET_SPEC , 9 > { INT_EVENT0_ISET_MSTOP_W :: new (self) } # [doc = "Bit 10 - Arbitration Lost Interrupt"] # [inline (always)] # [must_use] pub fn int_event0_iset_marblost (& mut self) -> INT_EVENT0_ISET_MARBLOST_W < INT_EVENT0_ISET_SPEC , 10 > { INT_EVENT0_ISET_MARBLOST_W :: new (self) } # [doc = "Bit 11 - DMA Done 1 on Event Channel 2"] # [inline (always)] # [must_use] pub fn int_event0_iset_mdma_done1_2 (& mut self) -> INT_EVENT0_ISET_MDMA_DONE1_2_W < INT_EVENT0_ISET_SPEC , 11 > { INT_EVENT0_ISET_MDMA_DONE1_2_W :: new (self) } # [doc = "Bit 12 - DMA Done 1 on Event Channel 3"] # [inline (always)] # [must_use] pub fn int_event0_iset_mdma_done1_3 (& mut self) -> INT_EVENT0_ISET_MDMA_DONE1_3_W < INT_EVENT0_ISET_SPEC , 12 > { INT_EVENT0_ISET_MDMA_DONE1_3_W :: new (self) } # [doc = "Bit 13 - Master RX Pec Error Interrupt"] # [inline (always)] # [must_use] pub fn int_event0_iset_mpec_rx_err (& mut self) -> INT_EVENT0_ISET_MPEC_RX_ERR_W < INT_EVENT0_ISET_SPEC , 13 > { INT_EVENT0_ISET_MPEC_RX_ERR_W :: new (self) } # [doc = "Bit 14 - Timeout A interrupt"] # [inline (always)] # [must_use] pub fn int_event0_iset_timeouta (& mut self) -> INT_EVENT0_ISET_TIMEOUTA_W < INT_EVENT0_ISET_SPEC , 14 > { INT_EVENT0_ISET_TIMEOUTA_W :: new (self) } # [doc = "Bit 15 - Timeout B Interrupt"] # [inline (always)] # [must_use] pub fn int_event0_iset_timeoutb (& mut self) -> INT_EVENT0_ISET_TIMEOUTB_W < INT_EVENT0_ISET_SPEC , 15 > { INT_EVENT0_ISET_TIMEOUTB_W :: new (self) } # [doc = "Bit 16 - Slave Receive Data Interrupt Signals that a byte has been received"] # [inline (always)] # [must_use] pub fn int_event0_iset_srxdone (& mut self) -> INT_EVENT0_ISET_SRXDONE_W < INT_EVENT0_ISET_SPEC , 16 > { INT_EVENT0_ISET_SRXDONE_W :: new (self) } # [doc = "Bit 17 - Slave Transmit Transaction completed Interrupt"] # [inline (always)] # [must_use] pub fn int_event0_iset_stxdone (& mut self) -> INT_EVENT0_ISET_STXDONE_W < INT_EVENT0_ISET_SPEC , 17 > { INT_EVENT0_ISET_STXDONE_W :: new (self) } # [doc = "Bit 18 - Slave Receive FIFO Trigger"] # [inline (always)] # [must_use] pub fn int_event0_iset_srxfifotrg (& mut self) -> INT_EVENT0_ISET_SRXFIFOTRG_W < INT_EVENT0_ISET_SPEC , 18 > { INT_EVENT0_ISET_SRXFIFOTRG_W :: new (self) } # [doc = "Bit 19 - Slave Transmit FIFO Trigger"] # [inline (always)] # [must_use] pub fn int_event0_iset_stxfifotrg (& mut self) -> INT_EVENT0_ISET_STXFIFOTRG_W < INT_EVENT0_ISET_SPEC , 19 > { INT_EVENT0_ISET_STXFIFOTRG_W :: new (self) } # [doc = "Bit 20 - RXFIFO full event. This interrupt is set if an RX FIFO is full."] # [inline (always)] # [must_use] pub fn int_event0_iset_srxfifofull (& mut self) -> INT_EVENT0_ISET_SRXFIFOFULL_W < INT_EVENT0_ISET_SPEC , 20 > { INT_EVENT0_ISET_SRXFIFOFULL_W :: new (self) } # [doc = "Bit 21 - Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode."] # [inline (always)] # [must_use] pub fn int_event0_iset_stxempty (& mut self) -> INT_EVENT0_ISET_STXEMPTY_W < INT_EVENT0_ISET_SPEC , 21 > { INT_EVENT0_ISET_STXEMPTY_W :: new (self) } # [doc = "Bit 22 - Start Condition Interrupt"] # [inline (always)] # [must_use] pub fn int_event0_iset_sstart (& mut self) -> INT_EVENT0_ISET_SSTART_W < INT_EVENT0_ISET_SPEC , 22 > { INT_EVENT0_ISET_SSTART_W :: new (self) } # [doc = "Bit 23 - Stop Condition Interrupt"] # [inline (always)] # [must_use] pub fn int_event0_iset_sstop (& mut self) -> INT_EVENT0_ISET_SSTOP_W < INT_EVENT0_ISET_SPEC , 23 > { INT_EVENT0_ISET_SSTOP_W :: new (self) } # [doc = "Bit 24 - General Call Interrupt"] # [inline (always)] # [must_use] pub fn int_event0_iset_sgencall (& mut self) -> INT_EVENT0_ISET_SGENCALL_W < INT_EVENT0_ISET_SPEC , 24 > { INT_EVENT0_ISET_SGENCALL_W :: new (self) } # [doc = "Bit 25 - DMA Done 1 on Event Channel 2"] # [inline (always)] # [must_use] pub fn int_event0_iset_sdma_done1_2 (& mut self) -> INT_EVENT0_ISET_SDMA_DONE1_2_W < INT_EVENT0_ISET_SPEC , 25 > { INT_EVENT0_ISET_SDMA_DONE1_2_W :: new (self) } # [doc = "Bit 26 - DMA Done 1 on Event Channel 3"] # [inline (always)] # [must_use] pub fn int_event0_iset_sdma_done1_3 (& mut self) -> INT_EVENT0_ISET_SDMA_DONE1_3_W < INT_EVENT0_ISET_SPEC , 26 > { INT_EVENT0_ISET_SDMA_DONE1_3_W :: new (self) } # [doc = "Bit 27 - Slave RX Pec Error Interrupt"] # [inline (always)] # [must_use] pub fn int_event0_iset_spec_rx_err (& mut self) -> INT_EVENT0_ISET_SPEC_RX_ERR_W < INT_EVENT0_ISET_SPEC , 27 > { INT_EVENT0_ISET_SPEC_RX_ERR_W :: new (self) } # [doc = "Bit 28 - Slave TX FIFO underflow"] # [inline (always)] # [must_use] pub fn int_event0_iset_stx_unfl (& mut self) -> INT_EVENT0_ISET_STX_UNFL_W < INT_EVENT0_ISET_SPEC , 28 > { INT_EVENT0_ISET_STX_UNFL_W :: new (self) } # [doc = "Bit 29 - Slave RX FIFO overflow"] # [inline (always)] # [must_use] pub fn int_event0_iset_srx_ovfl (& mut self) -> INT_EVENT0_ISET_SRX_OVFL_W < INT_EVENT0_ISET_SPEC , 29 > { INT_EVENT0_ISET_SRX_OVFL_W :: new (self) } # [doc = "Bit 30 - Slave Arbitration Lost"] # [inline (always)] # [must_use] pub fn int_event0_iset_sarblost (& mut self) -> INT_EVENT0_ISET_SARBLOST_W < INT_EVENT0_ISET_SPEC , 30 > { INT_EVENT0_ISET_SARBLOST_W :: new (self) } # [doc = "Bit 31 - Interrupt overflow"] # [inline (always)] # [must_use] pub fn int_event0_iset_intr_ovfl (& mut self) -> INT_EVENT0_ISET_INTR_OVFL_W < INT_EVENT0_ISET_SPEC , 31 > { INT_EVENT0_ISET_INTR_OVFL_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Interrupt set\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_event0_iset::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct INT_EVENT0_ISET_SPEC ; impl crate :: RegisterSpec for INT_EVENT0_ISET_SPEC { type Ux = u32 ; } # [doc = "`write(|w| ..)` method takes [`int_event0_iset::W`](W) writer structure"] impl crate :: Writable for INT_EVENT0_ISET_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets INT_EVENT0_ISET to value 0"] impl crate :: Resettable for INT_EVENT0_ISET_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/i2c1/rstctl.rs:1:3464 [INFO] [stdout] | [INFO] [stdout] 1 | ... rstctl_resetstkyclr (& mut self) -> RSTCTL_RESETSTKYCLR_W < RSTCTL_SPEC , 1 > { RSTCTL_RESETSTKYCLR_W :: new (self) } # [doc = "Bits ... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `RSTCTL` writer"] pub type W = crate :: W < RSTCTL_SPEC > ; # [doc = "Assert reset to the peripheral\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum RSTCTL_RESETASSERT_AW { # [doc = "0: NOP"] RSTCTL_RESETASSERT_NOP = 0 , # [doc = "1: ASSERT"] RSTCTL_RESETASSERT_ASSERT = 1 , } impl From < RSTCTL_RESETASSERT_AW > for bool { # [inline (always)] fn from (variant : RSTCTL_RESETASSERT_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `RSTCTL_RESETASSERT` writer - Assert reset to the peripheral"] pub type RSTCTL_RESETASSERT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , RSTCTL_RESETASSERT_AW > ; impl < 'a , REG , const O : u8 > RSTCTL_RESETASSERT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NOP"] # [inline (always)] pub fn rstctl_resetassert_nop (self) -> & 'a mut crate :: W < REG > { self . variant (RSTCTL_RESETASSERT_AW :: RSTCTL_RESETASSERT_NOP) } # [doc = "ASSERT"] # [inline (always)] pub fn rstctl_resetassert_assert (self) -> & 'a mut crate :: W < REG > { self . variant (RSTCTL_RESETASSERT_AW :: RSTCTL_RESETASSERT_ASSERT) } } # [doc = "Clear the RESETSTKY bit in the STAT register\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum RSTCTL_RESETSTKYCLR_AW { # [doc = "0: NOP"] RSTCTL_RESETSTKYCLR_NOP = 0 , # [doc = "1: CLR"] RSTCTL_RESETSTKYCLR_CLR = 1 , } impl From < RSTCTL_RESETSTKYCLR_AW > for bool { # [inline (always)] fn from (variant : RSTCTL_RESETSTKYCLR_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `RSTCTL_RESETSTKYCLR` writer - Clear the RESETSTKY bit in the STAT register"] pub type RSTCTL_RESETSTKYCLR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , RSTCTL_RESETSTKYCLR_AW > ; impl < 'a , REG , const O : u8 > RSTCTL_RESETSTKYCLR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NOP"] # [inline (always)] pub fn rstctl_resetstkyclr_nop (self) -> & 'a mut crate :: W < REG > { self . variant (RSTCTL_RESETSTKYCLR_AW :: RSTCTL_RESETSTKYCLR_NOP) } # [doc = "CLR"] # [inline (always)] pub fn rstctl_resetstkyclr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (RSTCTL_RESETSTKYCLR_AW :: RSTCTL_RESETSTKYCLR_CLR) } } # [doc = "Unlock key\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum RSTCTL_KEY_AW { # [doc = "177: _TO_UNLOCK_W_"] RSTCTL_KEY_UNLOCK_W = 177 , } impl From < RSTCTL_KEY_AW > for u8 { # [inline (always)] fn from (variant : RSTCTL_KEY_AW) -> Self { variant as _ } } impl crate :: FieldSpec for RSTCTL_KEY_AW { type Ux = u8 ; } # [doc = "Field `RSTCTL_KEY` writer - Unlock key"] pub type RSTCTL_KEY_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 8 , O , RSTCTL_KEY_AW > ; impl < 'a , REG , const O : u8 > RSTCTL_KEY_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "_TO_UNLOCK_W_"] # [inline (always)] pub fn rstctl_key_unlock_w (self) -> & 'a mut crate :: W < REG > { self . variant (RSTCTL_KEY_AW :: RSTCTL_KEY_UNLOCK_W) } } impl W { # [doc = "Bit 0 - Assert reset to the peripheral"] # [inline (always)] # [must_use] pub fn rstctl_resetassert (& mut self) -> RSTCTL_RESETASSERT_W < RSTCTL_SPEC , 0 > { RSTCTL_RESETASSERT_W :: new (self) } # [doc = "Bit 1 - Clear the RESETSTKY bit in the STAT register"] # [inline (always)] # [must_use] pub fn rstctl_resetstkyclr (& mut self) -> RSTCTL_RESETSTKYCLR_W <'_, RSTCTL_SPEC , 1 > { RSTCTL_RESETSTKYCLR_W :: new (self) } # [doc = "Bits 24:31 - Unlock key"] # [inline (always)] # [must_use] pub fn rstctl_key (& mut self) -> RSTCTL_KEY_W < RSTCTL_SPEC , 24 > { RSTCTL_KEY_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Reset Control\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rstctl::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct RSTCTL_SPEC ; impl crate :: RegisterSpec for RSTCTL_SPEC { type Ux = u32 ; } # [doc = "`write(|w| ..)` method takes [`rstctl::W`](W) writer structure"] impl crate :: Writable for RSTCTL_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets RSTCTL to value 0"] impl crate :: Resettable for RSTCTL_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/i2c0/sctr.rs:1:26614 [INFO] [stdout] | [INFO] [stdout] 1 | ...b fn sctr_en_defdevadr (& mut self) -> SCTR_EN_DEFDEVADR_W < SCTR_SPEC , 9 > { SCTR_EN_DEFDEVADR_W :: new (self) } # [doc = "Bit 10 - ... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `SCTR` reader"] pub type R = crate :: R < SCTR_SPEC > ; # [doc = "Register `SCTR` writer"] pub type W = crate :: W < SCTR_SPEC > ; # [doc = "Field `SCTR_ACTIVE` reader - Device Active. Setting this bit enables the slave functionality."] pub type SCTR_ACTIVE_R = crate :: BitReader < SCTR_ACTIVE_A > ; # [doc = "Device Active. Setting this bit enables the slave functionality.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum SCTR_ACTIVE_A { # [doc = "0: DISABLE"] SCTR_ACTIVE_DISABLE = 0 , # [doc = "1: ENABLE"] SCTR_ACTIVE_ENABLE = 1 , } impl From < SCTR_ACTIVE_A > for bool { # [inline (always)] fn from (variant : SCTR_ACTIVE_A) -> Self { variant as u8 != 0 } } impl SCTR_ACTIVE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> SCTR_ACTIVE_A { match self . bits { false => SCTR_ACTIVE_A :: SCTR_ACTIVE_DISABLE , true => SCTR_ACTIVE_A :: SCTR_ACTIVE_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_sctr_active_disable (& self) -> bool { * self == SCTR_ACTIVE_A :: SCTR_ACTIVE_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_sctr_active_enable (& self) -> bool { * self == SCTR_ACTIVE_A :: SCTR_ACTIVE_ENABLE } } # [doc = "Field `SCTR_ACTIVE` writer - Device Active. Setting this bit enables the slave functionality."] pub type SCTR_ACTIVE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , SCTR_ACTIVE_A > ; impl < 'a , REG , const O : u8 > SCTR_ACTIVE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn sctr_active_disable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_ACTIVE_A :: SCTR_ACTIVE_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn sctr_active_enable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_ACTIVE_A :: SCTR_ACTIVE_ENABLE) } } # [doc = "Field `SCTR_GENCALL` reader - General call response enable. This bit is only available in UCBxI2COA0. Modify only when UCSWRST = 1. 0b = Do not respond to a general call 1b = Respond to a general call"] pub type SCTR_GENCALL_R = crate :: BitReader < SCTR_GENCALL_A > ; # [doc = "General call response enable. This bit is only available in UCBxI2COA0. Modify only when UCSWRST = 1. 0b = Do not respond to a general call 1b = Respond to a general call\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum SCTR_GENCALL_A { # [doc = "0: DISABLE"] SCTR_GENCALL_DISABLE = 0 , # [doc = "1: ENABLE"] SCTR_GENCALL_ENABLE = 1 , } impl From < SCTR_GENCALL_A > for bool { # [inline (always)] fn from (variant : SCTR_GENCALL_A) -> Self { variant as u8 != 0 } } impl SCTR_GENCALL_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> SCTR_GENCALL_A { match self . bits { false => SCTR_GENCALL_A :: SCTR_GENCALL_DISABLE , true => SCTR_GENCALL_A :: SCTR_GENCALL_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_sctr_gencall_disable (& self) -> bool { * self == SCTR_GENCALL_A :: SCTR_GENCALL_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_sctr_gencall_enable (& self) -> bool { * self == SCTR_GENCALL_A :: SCTR_GENCALL_ENABLE } } # [doc = "Field `SCTR_GENCALL` writer - General call response enable. This bit is only available in UCBxI2COA0. Modify only when UCSWRST = 1. 0b = Do not respond to a general call 1b = Respond to a general call"] pub type SCTR_GENCALL_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , SCTR_GENCALL_A > ; impl < 'a , REG , const O : u8 > SCTR_GENCALL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn sctr_gencall_disable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_GENCALL_A :: SCTR_GENCALL_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn sctr_gencall_enable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_GENCALL_A :: SCTR_GENCALL_ENABLE) } } # [doc = "Field `SCTR_SCLKSTRETCH` reader - Slave Clock Stretch Enable"] pub type SCTR_SCLKSTRETCH_R = crate :: BitReader < SCTR_SCLKSTRETCH_A > ; # [doc = "Slave Clock Stretch Enable\n\nValue on reset: 1"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum SCTR_SCLKSTRETCH_A { # [doc = "0: DISABLE"] SCTR_SCLKSTRETCH_DISABLE = 0 , # [doc = "1: ENABLE"] SCTR_SCLKSTRETCH_ENABLE = 1 , } impl From < SCTR_SCLKSTRETCH_A > for bool { # [inline (always)] fn from (variant : SCTR_SCLKSTRETCH_A) -> Self { variant as u8 != 0 } } impl SCTR_SCLKSTRETCH_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> SCTR_SCLKSTRETCH_A { match self . bits { false => SCTR_SCLKSTRETCH_A :: SCTR_SCLKSTRETCH_DISABLE , true => SCTR_SCLKSTRETCH_A :: SCTR_SCLKSTRETCH_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_sctr_sclkstretch_disable (& self) -> bool { * self == SCTR_SCLKSTRETCH_A :: SCTR_SCLKSTRETCH_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_sctr_sclkstretch_enable (& self) -> bool { * self == SCTR_SCLKSTRETCH_A :: SCTR_SCLKSTRETCH_ENABLE } } # [doc = "Field `SCTR_SCLKSTRETCH` writer - Slave Clock Stretch Enable"] pub type SCTR_SCLKSTRETCH_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , SCTR_SCLKSTRETCH_A > ; impl < 'a , REG , const O : u8 > SCTR_SCLKSTRETCH_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn sctr_sclkstretch_disable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_SCLKSTRETCH_A :: SCTR_SCLKSTRETCH_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn sctr_sclkstretch_enable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_SCLKSTRETCH_A :: SCTR_SCLKSTRETCH_ENABLE) } } # [doc = "Field `SCTR_TXEMPTY_ON_TREQ` reader - Tx Empty Interrupt on TREQ"] pub type SCTR_TXEMPTY_ON_TREQ_R = crate :: BitReader < SCTR_TXEMPTY_ON_TREQ_A > ; # [doc = "Tx Empty Interrupt on TREQ\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum SCTR_TXEMPTY_ON_TREQ_A { # [doc = "0: DISABLE"] SCTR_TXEMPTY_ON_TREQ_DISABLE = 0 , # [doc = "1: ENABLE"] SCTR_TXEMPTY_ON_TREQ_ENABLE = 1 , } impl From < SCTR_TXEMPTY_ON_TREQ_A > for bool { # [inline (always)] fn from (variant : SCTR_TXEMPTY_ON_TREQ_A) -> Self { variant as u8 != 0 } } impl SCTR_TXEMPTY_ON_TREQ_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> SCTR_TXEMPTY_ON_TREQ_A { match self . bits { false => SCTR_TXEMPTY_ON_TREQ_A :: SCTR_TXEMPTY_ON_TREQ_DISABLE , true => SCTR_TXEMPTY_ON_TREQ_A :: SCTR_TXEMPTY_ON_TREQ_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_sctr_txempty_on_treq_disable (& self) -> bool { * self == SCTR_TXEMPTY_ON_TREQ_A :: SCTR_TXEMPTY_ON_TREQ_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_sctr_txempty_on_treq_enable (& self) -> bool { * self == SCTR_TXEMPTY_ON_TREQ_A :: SCTR_TXEMPTY_ON_TREQ_ENABLE } } # [doc = "Field `SCTR_TXEMPTY_ON_TREQ` writer - Tx Empty Interrupt on TREQ"] pub type SCTR_TXEMPTY_ON_TREQ_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , SCTR_TXEMPTY_ON_TREQ_A > ; impl < 'a , REG , const O : u8 > SCTR_TXEMPTY_ON_TREQ_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn sctr_txempty_on_treq_disable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_TXEMPTY_ON_TREQ_A :: SCTR_TXEMPTY_ON_TREQ_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn sctr_txempty_on_treq_enable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_TXEMPTY_ON_TREQ_A :: SCTR_TXEMPTY_ON_TREQ_ENABLE) } } # [doc = "Field `SCTR_TXTRIG_TXMODE` reader - Tx Trigger when slave FSM is in Tx Mode"] pub type SCTR_TXTRIG_TXMODE_R = crate :: BitReader < SCTR_TXTRIG_TXMODE_A > ; # [doc = "Tx Trigger when slave FSM is in Tx Mode\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum SCTR_TXTRIG_TXMODE_A { # [doc = "0: DISABLE"] SCTR_TXTRIG_TXMODE_DISABLE = 0 , # [doc = "1: ENABLE"] SCTR_TXTRIG_TXMODE_ENABLE = 1 , } impl From < SCTR_TXTRIG_TXMODE_A > for bool { # [inline (always)] fn from (variant : SCTR_TXTRIG_TXMODE_A) -> Self { variant as u8 != 0 } } impl SCTR_TXTRIG_TXMODE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> SCTR_TXTRIG_TXMODE_A { match self . bits { false => SCTR_TXTRIG_TXMODE_A :: SCTR_TXTRIG_TXMODE_DISABLE , true => SCTR_TXTRIG_TXMODE_A :: SCTR_TXTRIG_TXMODE_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_sctr_txtrig_txmode_disable (& self) -> bool { * self == SCTR_TXTRIG_TXMODE_A :: SCTR_TXTRIG_TXMODE_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_sctr_txtrig_txmode_enable (& self) -> bool { * self == SCTR_TXTRIG_TXMODE_A :: SCTR_TXTRIG_TXMODE_ENABLE } } # [doc = "Field `SCTR_TXTRIG_TXMODE` writer - Tx Trigger when slave FSM is in Tx Mode"] pub type SCTR_TXTRIG_TXMODE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , SCTR_TXTRIG_TXMODE_A > ; impl < 'a , REG , const O : u8 > SCTR_TXTRIG_TXMODE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn sctr_txtrig_txmode_disable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_TXTRIG_TXMODE_A :: SCTR_TXTRIG_TXMODE_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn sctr_txtrig_txmode_enable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_TXTRIG_TXMODE_A :: SCTR_TXTRIG_TXMODE_ENABLE) } } # [doc = "Field `SCTR_TXWAIT_STALE_TXFIFO` reader - Tx transfer waits when stale data in Tx FIFO. This prevents stale bytes left in the TX FIFO from automatically being sent on the next I2C packet. Note: this should be used with TXEMPTY_ON_TREQ set to prevent the Slave State Machine from waiting for TX FIFO data without an interrupt notification when the FIFO data is stale."] pub type SCTR_TXWAIT_STALE_TXFIFO_R = crate :: BitReader < SCTR_TXWAIT_STALE_TXFIFO_A > ; # [doc = "Tx transfer waits when stale data in Tx FIFO. This prevents stale bytes left in the TX FIFO from automatically being sent on the next I2C packet. Note: this should be used with TXEMPTY_ON_TREQ set to prevent the Slave State Machine from waiting for TX FIFO data without an interrupt notification when the FIFO data is stale.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum SCTR_TXWAIT_STALE_TXFIFO_A { # [doc = "0: DISABLE"] SCTR_TXWAIT_STALE_TXFIFO_DISABLE = 0 , # [doc = "1: ENABLE"] SCTR_TXWAIT_STALE_TXFIFO_ENABLE = 1 , } impl From < SCTR_TXWAIT_STALE_TXFIFO_A > for bool { # [inline (always)] fn from (variant : SCTR_TXWAIT_STALE_TXFIFO_A) -> Self { variant as u8 != 0 } } impl SCTR_TXWAIT_STALE_TXFIFO_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> SCTR_TXWAIT_STALE_TXFIFO_A { match self . bits { false => SCTR_TXWAIT_STALE_TXFIFO_A :: SCTR_TXWAIT_STALE_TXFIFO_DISABLE , true => SCTR_TXWAIT_STALE_TXFIFO_A :: SCTR_TXWAIT_STALE_TXFIFO_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_sctr_txwait_stale_txfifo_disable (& self) -> bool { * self == SCTR_TXWAIT_STALE_TXFIFO_A :: SCTR_TXWAIT_STALE_TXFIFO_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_sctr_txwait_stale_txfifo_enable (& self) -> bool { * self == SCTR_TXWAIT_STALE_TXFIFO_A :: SCTR_TXWAIT_STALE_TXFIFO_ENABLE } } # [doc = "Field `SCTR_TXWAIT_STALE_TXFIFO` writer - Tx transfer waits when stale data in Tx FIFO. This prevents stale bytes left in the TX FIFO from automatically being sent on the next I2C packet. Note: this should be used with TXEMPTY_ON_TREQ set to prevent the Slave State Machine from waiting for TX FIFO data without an interrupt notification when the FIFO data is stale."] pub type SCTR_TXWAIT_STALE_TXFIFO_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , SCTR_TXWAIT_STALE_TXFIFO_A > ; impl < 'a , REG , const O : u8 > SCTR_TXWAIT_STALE_TXFIFO_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn sctr_txwait_stale_txfifo_disable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_TXWAIT_STALE_TXFIFO_A :: SCTR_TXWAIT_STALE_TXFIFO_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn sctr_txwait_stale_txfifo_enable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_TXWAIT_STALE_TXFIFO_A :: SCTR_TXWAIT_STALE_TXFIFO_ENABLE) } } # [doc = "Field `SCTR_RXFULL_ON_RREQ` reader - Rx full interrupt generated on RREQ condition as indicated in SSR"] pub type SCTR_RXFULL_ON_RREQ_R = crate :: BitReader < SCTR_RXFULL_ON_RREQ_A > ; # [doc = "Rx full interrupt generated on RREQ condition as indicated in SSR\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum SCTR_RXFULL_ON_RREQ_A { # [doc = "0: DISABLE"] SCTR_RXFULL_ON_RREQ_DISABLE = 0 , # [doc = "1: ENABLE"] SCTR_RXFULL_ON_RREQ_ENABLE = 1 , } impl From < SCTR_RXFULL_ON_RREQ_A > for bool { # [inline (always)] fn from (variant : SCTR_RXFULL_ON_RREQ_A) -> Self { variant as u8 != 0 } } impl SCTR_RXFULL_ON_RREQ_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> SCTR_RXFULL_ON_RREQ_A { match self . bits { false => SCTR_RXFULL_ON_RREQ_A :: SCTR_RXFULL_ON_RREQ_DISABLE , true => SCTR_RXFULL_ON_RREQ_A :: SCTR_RXFULL_ON_RREQ_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_sctr_rxfull_on_rreq_disable (& self) -> bool { * self == SCTR_RXFULL_ON_RREQ_A :: SCTR_RXFULL_ON_RREQ_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_sctr_rxfull_on_rreq_enable (& self) -> bool { * self == SCTR_RXFULL_ON_RREQ_A :: SCTR_RXFULL_ON_RREQ_ENABLE } } # [doc = "Field `SCTR_RXFULL_ON_RREQ` writer - Rx full interrupt generated on RREQ condition as indicated in SSR"] pub type SCTR_RXFULL_ON_RREQ_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , SCTR_RXFULL_ON_RREQ_A > ; impl < 'a , REG , const O : u8 > SCTR_RXFULL_ON_RREQ_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn sctr_rxfull_on_rreq_disable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_RXFULL_ON_RREQ_A :: SCTR_RXFULL_ON_RREQ_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn sctr_rxfull_on_rreq_enable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_RXFULL_ON_RREQ_A :: SCTR_RXFULL_ON_RREQ_ENABLE) } } # [doc = "Field `SCTR_EN_DEFHOSTADR` reader - Enable Default Host Address"] pub type SCTR_EN_DEFHOSTADR_R = crate :: BitReader < SCTR_EN_DEFHOSTADR_A > ; # [doc = "Enable Default Host Address\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum SCTR_EN_DEFHOSTADR_A { # [doc = "0: DISABLE"] SCTR_EN_DEFHOSTADR_DISABLE = 0 , # [doc = "1: ENABLE"] SCTR_EN_DEFHOSTADR_ENABLE = 1 , } impl From < SCTR_EN_DEFHOSTADR_A > for bool { # [inline (always)] fn from (variant : SCTR_EN_DEFHOSTADR_A) -> Self { variant as u8 != 0 } } impl SCTR_EN_DEFHOSTADR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> SCTR_EN_DEFHOSTADR_A { match self . bits { false => SCTR_EN_DEFHOSTADR_A :: SCTR_EN_DEFHOSTADR_DISABLE , true => SCTR_EN_DEFHOSTADR_A :: SCTR_EN_DEFHOSTADR_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_sctr_en_defhostadr_disable (& self) -> bool { * self == SCTR_EN_DEFHOSTADR_A :: SCTR_EN_DEFHOSTADR_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_sctr_en_defhostadr_enable (& self) -> bool { * self == SCTR_EN_DEFHOSTADR_A :: SCTR_EN_DEFHOSTADR_ENABLE } } # [doc = "Field `SCTR_EN_DEFHOSTADR` writer - Enable Default Host Address"] pub type SCTR_EN_DEFHOSTADR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , SCTR_EN_DEFHOSTADR_A > ; impl < 'a , REG , const O : u8 > SCTR_EN_DEFHOSTADR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn sctr_en_defhostadr_disable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_EN_DEFHOSTADR_A :: SCTR_EN_DEFHOSTADR_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn sctr_en_defhostadr_enable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_EN_DEFHOSTADR_A :: SCTR_EN_DEFHOSTADR_ENABLE) } } # [doc = "Field `SCTR_EN_ALRESPADR` reader - Enable Alert Response Address"] pub type SCTR_EN_ALRESPADR_R = crate :: BitReader < SCTR_EN_ALRESPADR_A > ; # [doc = "Enable Alert Response Address\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum SCTR_EN_ALRESPADR_A { # [doc = "0: DISABLE"] SCTR_EN_ALRESPADR_DISABLE = 0 , # [doc = "1: ENABLE"] SCTR_EN_ALRESPADR_ENABLE = 1 , } impl From < SCTR_EN_ALRESPADR_A > for bool { # [inline (always)] fn from (variant : SCTR_EN_ALRESPADR_A) -> Self { variant as u8 != 0 } } impl SCTR_EN_ALRESPADR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> SCTR_EN_ALRESPADR_A { match self . bits { false => SCTR_EN_ALRESPADR_A :: SCTR_EN_ALRESPADR_DISABLE , true => SCTR_EN_ALRESPADR_A :: SCTR_EN_ALRESPADR_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_sctr_en_alrespadr_disable (& self) -> bool { * self == SCTR_EN_ALRESPADR_A :: SCTR_EN_ALRESPADR_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_sctr_en_alrespadr_enable (& self) -> bool { * self == SCTR_EN_ALRESPADR_A :: SCTR_EN_ALRESPADR_ENABLE } } # [doc = "Field `SCTR_EN_ALRESPADR` writer - Enable Alert Response Address"] pub type SCTR_EN_ALRESPADR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , SCTR_EN_ALRESPADR_A > ; impl < 'a , REG , const O : u8 > SCTR_EN_ALRESPADR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn sctr_en_alrespadr_disable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_EN_ALRESPADR_A :: SCTR_EN_ALRESPADR_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn sctr_en_alrespadr_enable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_EN_ALRESPADR_A :: SCTR_EN_ALRESPADR_ENABLE) } } # [doc = "Field `SCTR_EN_DEFDEVADR` reader - Enable Deault device address"] pub type SCTR_EN_DEFDEVADR_R = crate :: BitReader < SCTR_EN_DEFDEVADR_A > ; # [doc = "Enable Deault device address\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum SCTR_EN_DEFDEVADR_A { # [doc = "0: DISABLE"] SCTR_EN_DEFDEVADR_DISABLE = 0 , # [doc = "1: ENABLE"] SCTR_EN_DEFDEVADR_ENABLE = 1 , } impl From < SCTR_EN_DEFDEVADR_A > for bool { # [inline (always)] fn from (variant : SCTR_EN_DEFDEVADR_A) -> Self { variant as u8 != 0 } } impl SCTR_EN_DEFDEVADR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> SCTR_EN_DEFDEVADR_A { match self . bits { false => SCTR_EN_DEFDEVADR_A :: SCTR_EN_DEFDEVADR_DISABLE , true => SCTR_EN_DEFDEVADR_A :: SCTR_EN_DEFDEVADR_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_sctr_en_defdevadr_disable (& self) -> bool { * self == SCTR_EN_DEFDEVADR_A :: SCTR_EN_DEFDEVADR_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_sctr_en_defdevadr_enable (& self) -> bool { * self == SCTR_EN_DEFDEVADR_A :: SCTR_EN_DEFDEVADR_ENABLE } } # [doc = "Field `SCTR_EN_DEFDEVADR` writer - Enable Deault device address"] pub type SCTR_EN_DEFDEVADR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , SCTR_EN_DEFDEVADR_A > ; impl < 'a , REG , const O : u8 > SCTR_EN_DEFDEVADR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn sctr_en_defdevadr_disable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_EN_DEFDEVADR_A :: SCTR_EN_DEFDEVADR_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn sctr_en_defdevadr_enable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_EN_DEFDEVADR_A :: SCTR_EN_DEFDEVADR_ENABLE) } } # [doc = "Field `SCTR_SWUEN` reader - Slave Wakeup Enable"] pub type SCTR_SWUEN_R = crate :: BitReader < SCTR_SWUEN_A > ; # [doc = "Slave Wakeup Enable\n\nValue on reset: 1"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum SCTR_SWUEN_A { # [doc = "0: DISABLE"] SCTR_SWUEN_DISABLE = 0 , # [doc = "1: ENABLE"] SCTR_SWUEN_ENABLE = 1 , } impl From < SCTR_SWUEN_A > for bool { # [inline (always)] fn from (variant : SCTR_SWUEN_A) -> Self { variant as u8 != 0 } } impl SCTR_SWUEN_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> SCTR_SWUEN_A { match self . bits { false => SCTR_SWUEN_A :: SCTR_SWUEN_DISABLE , true => SCTR_SWUEN_A :: SCTR_SWUEN_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_sctr_swuen_disable (& self) -> bool { * self == SCTR_SWUEN_A :: SCTR_SWUEN_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_sctr_swuen_enable (& self) -> bool { * self == SCTR_SWUEN_A :: SCTR_SWUEN_ENABLE } } # [doc = "Field `SCTR_SWUEN` writer - Slave Wakeup Enable"] pub type SCTR_SWUEN_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , SCTR_SWUEN_A > ; impl < 'a , REG , const O : u8 > SCTR_SWUEN_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn sctr_swuen_disable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_SWUEN_A :: SCTR_SWUEN_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn sctr_swuen_enable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_SWUEN_A :: SCTR_SWUEN_ENABLE) } } impl R { # [doc = "Bit 0 - Device Active. Setting this bit enables the slave functionality."] # [inline (always)] pub fn sctr_active (& self) -> SCTR_ACTIVE_R { SCTR_ACTIVE_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - General call response enable. This bit is only available in UCBxI2COA0. Modify only when UCSWRST = 1. 0b = Do not respond to a general call 1b = Respond to a general call"] # [inline (always)] pub fn sctr_gencall (& self) -> SCTR_GENCALL_R { SCTR_GENCALL_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - Slave Clock Stretch Enable"] # [inline (always)] pub fn sctr_sclkstretch (& self) -> SCTR_SCLKSTRETCH_R { SCTR_SCLKSTRETCH_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - Tx Empty Interrupt on TREQ"] # [inline (always)] pub fn sctr_txempty_on_treq (& self) -> SCTR_TXEMPTY_ON_TREQ_R { SCTR_TXEMPTY_ON_TREQ_R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - Tx Trigger when slave FSM is in Tx Mode"] # [inline (always)] pub fn sctr_txtrig_txmode (& self) -> SCTR_TXTRIG_TXMODE_R { SCTR_TXTRIG_TXMODE_R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - Tx transfer waits when stale data in Tx FIFO. This prevents stale bytes left in the TX FIFO from automatically being sent on the next I2C packet. Note: this should be used with TXEMPTY_ON_TREQ set to prevent the Slave State Machine from waiting for TX FIFO data without an interrupt notification when the FIFO data is stale."] # [inline (always)] pub fn sctr_txwait_stale_txfifo (& self) -> SCTR_TXWAIT_STALE_TXFIFO_R { SCTR_TXWAIT_STALE_TXFIFO_R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - Rx full interrupt generated on RREQ condition as indicated in SSR"] # [inline (always)] pub fn sctr_rxfull_on_rreq (& self) -> SCTR_RXFULL_ON_RREQ_R { SCTR_RXFULL_ON_RREQ_R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - Enable Default Host Address"] # [inline (always)] pub fn sctr_en_defhostadr (& self) -> SCTR_EN_DEFHOSTADR_R { SCTR_EN_DEFHOSTADR_R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - Enable Alert Response Address"] # [inline (always)] pub fn sctr_en_alrespadr (& self) -> SCTR_EN_ALRESPADR_R { SCTR_EN_ALRESPADR_R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - Enable Deault device address"] # [inline (always)] pub fn sctr_en_defdevadr (& self) -> SCTR_EN_DEFDEVADR_R { SCTR_EN_DEFDEVADR_R :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - Slave Wakeup Enable"] # [inline (always)] pub fn sctr_swuen (& self) -> SCTR_SWUEN_R { SCTR_SWUEN_R :: new (((self . bits >> 10) & 1) != 0) } } impl W { # [doc = "Bit 0 - Device Active. Setting this bit enables the slave functionality."] # [inline (always)] # [must_use] pub fn sctr_active (& mut self) -> SCTR_ACTIVE_W < SCTR_SPEC , 0 > { SCTR_ACTIVE_W :: new (self) } # [doc = "Bit 1 - General call response enable. This bit is only available in UCBxI2COA0. Modify only when UCSWRST = 1. 0b = Do not respond to a general call 1b = Respond to a general call"] # [inline (always)] # [must_use] pub fn sctr_gencall (& mut self) -> SCTR_GENCALL_W < SCTR_SPEC , 1 > { SCTR_GENCALL_W :: new (self) } # [doc = "Bit 2 - Slave Clock Stretch Enable"] # [inline (always)] # [must_use] pub fn sctr_sclkstretch (& mut self) -> SCTR_SCLKSTRETCH_W < SCTR_SPEC , 2 > { SCTR_SCLKSTRETCH_W :: new (self) } # [doc = "Bit 3 - Tx Empty Interrupt on TREQ"] # [inline (always)] # [must_use] pub fn sctr_txempty_on_treq (& mut self) -> SCTR_TXEMPTY_ON_TREQ_W < SCTR_SPEC , 3 > { SCTR_TXEMPTY_ON_TREQ_W :: new (self) } # [doc = "Bit 4 - Tx Trigger when slave FSM is in Tx Mode"] # [inline (always)] # [must_use] pub fn sctr_txtrig_txmode (& mut self) -> SCTR_TXTRIG_TXMODE_W < SCTR_SPEC , 4 > { SCTR_TXTRIG_TXMODE_W :: new (self) } # [doc = "Bit 5 - Tx transfer waits when stale data in Tx FIFO. This prevents stale bytes left in the TX FIFO from automatically being sent on the next I2C packet. Note: this should be used with TXEMPTY_ON_TREQ set to prevent the Slave State Machine from waiting for TX FIFO data without an interrupt notification when the FIFO data is stale."] # [inline (always)] # [must_use] pub fn sctr_txwait_stale_txfifo (& mut self) -> SCTR_TXWAIT_STALE_TXFIFO_W < SCTR_SPEC , 5 > { SCTR_TXWAIT_STALE_TXFIFO_W :: new (self) } # [doc = "Bit 6 - Rx full interrupt generated on RREQ condition as indicated in SSR"] # [inline (always)] # [must_use] pub fn sctr_rxfull_on_rreq (& mut self) -> SCTR_RXFULL_ON_RREQ_W < SCTR_SPEC , 6 > { SCTR_RXFULL_ON_RREQ_W :: new (self) } # [doc = "Bit 7 - Enable Default Host Address"] # [inline (always)] # [must_use] pub fn sctr_en_defhostadr (& mut self) -> SCTR_EN_DEFHOSTADR_W < SCTR_SPEC , 7 > { SCTR_EN_DEFHOSTADR_W :: new (self) } # [doc = "Bit 8 - Enable Alert Response Address"] # [inline (always)] # [must_use] pub fn sctr_en_alrespadr (& mut self) -> SCTR_EN_ALRESPADR_W < SCTR_SPEC , 8 > { SCTR_EN_ALRESPADR_W :: new (self) } # [doc = "Bit 9 - Enable Deault device address"] # [inline (always)] # [must_use] pub fn sctr_en_defdevadr (& mut self) -> SCTR_EN_DEFDEVADR_W <'_, SCTR_SPEC , 9 > { SCTR_EN_DEFDEVADR_W :: new (self) } # [doc = "Bit 10 - Slave Wakeup Enable"] # [inline (always)] # [must_use] pub fn sctr_swuen (& mut self) -> SCTR_SWUEN_W < SCTR_SPEC , 10 > { SCTR_SWUEN_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "I2C Slave Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sctr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sctr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct SCTR_SPEC ; impl crate :: RegisterSpec for SCTR_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`sctr::R`](R) reader structure"] impl crate :: Readable for SCTR_SPEC { } # [doc = "`write(|w| ..)` method takes [`sctr::W`](W) writer structure"] impl crate :: Writable for SCTR_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets SCTR to value 0x0404"] impl crate :: Resettable for SCTR_SPEC { const RESET_VALUE : Self :: Ux = 0x0404 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/opa0/cfg.rs:1:16972 [INFO] [stdout] | [INFO] [stdout] 1 | ... [must_use] pub fn cfg_psel (& mut self) -> CFG_PSEL_W < CFG_SPEC , 3 > { CFG_PSEL_W :: new (self) } # [doc = "Bits 7:9 - Negative OA ... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `CFG` reader"] pub type R = crate :: R < CFG_SPEC > ; # [doc = "Register `CFG` writer"] pub type W = crate :: W < CFG_SPEC > ; # [doc = "Field `CFG_CHOP` reader - Chopping enable."] pub type CFG_CHOP_R = crate :: FieldReader < CFG_CHOP_A > ; # [doc = "Chopping enable.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum CFG_CHOP_A { # [doc = "0: OFF"] CFG_CHOP_OFF = 0 , # [doc = "1: ON"] CFG_CHOP_ON = 1 , # [doc = "2: AVGON"] CFG_CHOP_AVGON = 2 , } impl From < CFG_CHOP_A > for u8 { # [inline (always)] fn from (variant : CFG_CHOP_A) -> Self { variant as _ } } impl crate :: FieldSpec for CFG_CHOP_A { type Ux = u8 ; } impl CFG_CHOP_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < CFG_CHOP_A > { match self . bits { 0 => Some (CFG_CHOP_A :: CFG_CHOP_OFF) , 1 => Some (CFG_CHOP_A :: CFG_CHOP_ON) , 2 => Some (CFG_CHOP_A :: CFG_CHOP_AVGON) , _ => None , } } # [doc = "OFF"] # [inline (always)] pub fn is_cfg_chop_off (& self) -> bool { * self == CFG_CHOP_A :: CFG_CHOP_OFF } # [doc = "ON"] # [inline (always)] pub fn is_cfg_chop_on (& self) -> bool { * self == CFG_CHOP_A :: CFG_CHOP_ON } # [doc = "AVGON"] # [inline (always)] pub fn is_cfg_chop_avgon (& self) -> bool { * self == CFG_CHOP_A :: CFG_CHOP_AVGON } } # [doc = "Field `CFG_CHOP` writer - Chopping enable."] pub type CFG_CHOP_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 2 , O , CFG_CHOP_A > ; impl < 'a , REG , const O : u8 > CFG_CHOP_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "OFF"] # [inline (always)] pub fn cfg_chop_off (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_CHOP_A :: CFG_CHOP_OFF) } # [doc = "ON"] # [inline (always)] pub fn cfg_chop_on (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_CHOP_A :: CFG_CHOP_ON) } # [doc = "AVGON"] # [inline (always)] pub fn cfg_chop_avgon (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_CHOP_A :: CFG_CHOP_AVGON) } } # [doc = "Field `CFG_OUTPIN` reader - Enable output pin"] pub type CFG_OUTPIN_R = crate :: BitReader < CFG_OUTPIN_A > ; # [doc = "Enable output pin\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CFG_OUTPIN_A { # [doc = "0: DISABLED"] CFG_OUTPIN_DISABLED = 0 , # [doc = "1: ENABLED"] CFG_OUTPIN_ENABLED = 1 , } impl From < CFG_OUTPIN_A > for bool { # [inline (always)] fn from (variant : CFG_OUTPIN_A) -> Self { variant as u8 != 0 } } impl CFG_OUTPIN_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CFG_OUTPIN_A { match self . bits { false => CFG_OUTPIN_A :: CFG_OUTPIN_DISABLED , true => CFG_OUTPIN_A :: CFG_OUTPIN_ENABLED , } } # [doc = "DISABLED"] # [inline (always)] pub fn is_cfg_outpin_disabled (& self) -> bool { * self == CFG_OUTPIN_A :: CFG_OUTPIN_DISABLED } # [doc = "ENABLED"] # [inline (always)] pub fn is_cfg_outpin_enabled (& self) -> bool { * self == CFG_OUTPIN_A :: CFG_OUTPIN_ENABLED } } # [doc = "Field `CFG_OUTPIN` writer - Enable output pin"] pub type CFG_OUTPIN_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CFG_OUTPIN_A > ; impl < 'a , REG , const O : u8 > CFG_OUTPIN_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLED"] # [inline (always)] pub fn cfg_outpin_disabled (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_OUTPIN_A :: CFG_OUTPIN_DISABLED) } # [doc = "ENABLED"] # [inline (always)] pub fn cfg_outpin_enabled (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_OUTPIN_A :: CFG_OUTPIN_ENABLED) } } # [doc = "Field `CFG_PSEL` reader - Positive OA input selection. Please refer to the device specific datasheet for exact channels available."] pub type CFG_PSEL_R = crate :: FieldReader < CFG_PSEL_A > ; # [doc = "Positive OA input selection. Please refer to the device specific datasheet for exact channels available.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum CFG_PSEL_A { # [doc = "0: NC"] CFG_PSEL_NC = 0 , # [doc = "1: EXTPIN0"] CFG_PSEL_EXTPIN0 = 1 , # [doc = "2: EXTPIN1"] CFG_PSEL_EXTPIN1 = 2 , # [doc = "3: DAC12OUT"] CFG_PSEL_DAC12OUT = 3 , # [doc = "4: DAC8OUT"] CFG_PSEL_DAC8OUT = 4 , # [doc = "5: VREF"] CFG_PSEL_VREF = 5 , # [doc = "6: OANM1RTOP"] CFG_PSEL_OANM1RTOP = 6 , # [doc = "7: GPAMP_OUT_INT"] CFG_PSEL_GPAMP_OUT_INT = 7 , # [doc = "8: VSS"] CFG_PSEL_VSS = 8 , } impl From < CFG_PSEL_A > for u8 { # [inline (always)] fn from (variant : CFG_PSEL_A) -> Self { variant as _ } } impl crate :: FieldSpec for CFG_PSEL_A { type Ux = u8 ; } impl CFG_PSEL_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < CFG_PSEL_A > { match self . bits { 0 => Some (CFG_PSEL_A :: CFG_PSEL_NC) , 1 => Some (CFG_PSEL_A :: CFG_PSEL_EXTPIN0) , 2 => Some (CFG_PSEL_A :: CFG_PSEL_EXTPIN1) , 3 => Some (CFG_PSEL_A :: CFG_PSEL_DAC12OUT) , 4 => Some (CFG_PSEL_A :: CFG_PSEL_DAC8OUT) , 5 => Some (CFG_PSEL_A :: CFG_PSEL_VREF) , 6 => Some (CFG_PSEL_A :: CFG_PSEL_OANM1RTOP) , 7 => Some (CFG_PSEL_A :: CFG_PSEL_GPAMP_OUT_INT) , 8 => Some (CFG_PSEL_A :: CFG_PSEL_VSS) , _ => None , } } # [doc = "NC"] # [inline (always)] pub fn is_cfg_psel_nc (& self) -> bool { * self == CFG_PSEL_A :: CFG_PSEL_NC } # [doc = "EXTPIN0"] # [inline (always)] pub fn is_cfg_psel_extpin0 (& self) -> bool { * self == CFG_PSEL_A :: CFG_PSEL_EXTPIN0 } # [doc = "EXTPIN1"] # [inline (always)] pub fn is_cfg_psel_extpin1 (& self) -> bool { * self == CFG_PSEL_A :: CFG_PSEL_EXTPIN1 } # [doc = "DAC12OUT"] # [inline (always)] pub fn is_cfg_psel_dac12out (& self) -> bool { * self == CFG_PSEL_A :: CFG_PSEL_DAC12OUT } # [doc = "DAC8OUT"] # [inline (always)] pub fn is_cfg_psel_dac8out (& self) -> bool { * self == CFG_PSEL_A :: CFG_PSEL_DAC8OUT } # [doc = "VREF"] # [inline (always)] pub fn is_cfg_psel_vref (& self) -> bool { * self == CFG_PSEL_A :: CFG_PSEL_VREF } # [doc = "OANM1RTOP"] # [inline (always)] pub fn is_cfg_psel_oanm1rtop (& self) -> bool { * self == CFG_PSEL_A :: CFG_PSEL_OANM1RTOP } # [doc = "GPAMP_OUT_INT"] # [inline (always)] pub fn is_cfg_psel_gpamp_out_int (& self) -> bool { * self == CFG_PSEL_A :: CFG_PSEL_GPAMP_OUT_INT } # [doc = "VSS"] # [inline (always)] pub fn is_cfg_psel_vss (& self) -> bool { * self == CFG_PSEL_A :: CFG_PSEL_VSS } } # [doc = "Field `CFG_PSEL` writer - Positive OA input selection. Please refer to the device specific datasheet for exact channels available."] pub type CFG_PSEL_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 4 , O , CFG_PSEL_A > ; impl < 'a , REG , const O : u8 > CFG_PSEL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "NC"] # [inline (always)] pub fn cfg_psel_nc (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_PSEL_A :: CFG_PSEL_NC) } # [doc = "EXTPIN0"] # [inline (always)] pub fn cfg_psel_extpin0 (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_PSEL_A :: CFG_PSEL_EXTPIN0) } # [doc = "EXTPIN1"] # [inline (always)] pub fn cfg_psel_extpin1 (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_PSEL_A :: CFG_PSEL_EXTPIN1) } # [doc = "DAC12OUT"] # [inline (always)] pub fn cfg_psel_dac12out (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_PSEL_A :: CFG_PSEL_DAC12OUT) } # [doc = "DAC8OUT"] # [inline (always)] pub fn cfg_psel_dac8out (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_PSEL_A :: CFG_PSEL_DAC8OUT) } # [doc = "VREF"] # [inline (always)] pub fn cfg_psel_vref (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_PSEL_A :: CFG_PSEL_VREF) } # [doc = "OANM1RTOP"] # [inline (always)] pub fn cfg_psel_oanm1rtop (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_PSEL_A :: CFG_PSEL_OANM1RTOP) } # [doc = "GPAMP_OUT_INT"] # [inline (always)] pub fn cfg_psel_gpamp_out_int (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_PSEL_A :: CFG_PSEL_GPAMP_OUT_INT) } # [doc = "VSS"] # [inline (always)] pub fn cfg_psel_vss (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_PSEL_A :: CFG_PSEL_VSS) } } # [doc = "Field `CFG_NSEL` reader - Negative OA input selection. Please refer to the device specific datasheet for exact channels available."] pub type CFG_NSEL_R = crate :: FieldReader < CFG_NSEL_A > ; # [doc = "Negative OA input selection. Please refer to the device specific datasheet for exact channels available.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum CFG_NSEL_A { # [doc = "0: NC"] CFG_NSEL_NC = 0 , # [doc = "1: EXTPIN0"] CFG_NSEL_EXTPIN0 = 1 , # [doc = "2: EXTPIN1"] CFG_NSEL_EXTPIN1 = 2 , # [doc = "3: OANP1RBOT"] CFG_NSEL_OANP1RBOT = 3 , # [doc = "4: OANRTAP"] CFG_NSEL_OANRTAP = 4 , # [doc = "5: OANRTOP"] CFG_NSEL_OANRTOP = 5 , # [doc = "6: SPARE"] CFG_NSEL_SPARE = 6 , } impl From < CFG_NSEL_A > for u8 { # [inline (always)] fn from (variant : CFG_NSEL_A) -> Self { variant as _ } } impl crate :: FieldSpec for CFG_NSEL_A { type Ux = u8 ; } impl CFG_NSEL_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < CFG_NSEL_A > { match self . bits { 0 => Some (CFG_NSEL_A :: CFG_NSEL_NC) , 1 => Some (CFG_NSEL_A :: CFG_NSEL_EXTPIN0) , 2 => Some (CFG_NSEL_A :: CFG_NSEL_EXTPIN1) , 3 => Some (CFG_NSEL_A :: CFG_NSEL_OANP1RBOT) , 4 => Some (CFG_NSEL_A :: CFG_NSEL_OANRTAP) , 5 => Some (CFG_NSEL_A :: CFG_NSEL_OANRTOP) , 6 => Some (CFG_NSEL_A :: CFG_NSEL_SPARE) , _ => None , } } # [doc = "NC"] # [inline (always)] pub fn is_cfg_nsel_nc (& self) -> bool { * self == CFG_NSEL_A :: CFG_NSEL_NC } # [doc = "EXTPIN0"] # [inline (always)] pub fn is_cfg_nsel_extpin0 (& self) -> bool { * self == CFG_NSEL_A :: CFG_NSEL_EXTPIN0 } # [doc = "EXTPIN1"] # [inline (always)] pub fn is_cfg_nsel_extpin1 (& self) -> bool { * self == CFG_NSEL_A :: CFG_NSEL_EXTPIN1 } # [doc = "OANP1RBOT"] # [inline (always)] pub fn is_cfg_nsel_oanp1rbot (& self) -> bool { * self == CFG_NSEL_A :: CFG_NSEL_OANP1RBOT } # [doc = "OANRTAP"] # [inline (always)] pub fn is_cfg_nsel_oanrtap (& self) -> bool { * self == CFG_NSEL_A :: CFG_NSEL_OANRTAP } # [doc = "OANRTOP"] # [inline (always)] pub fn is_cfg_nsel_oanrtop (& self) -> bool { * self == CFG_NSEL_A :: CFG_NSEL_OANRTOP } # [doc = "SPARE"] # [inline (always)] pub fn is_cfg_nsel_spare (& self) -> bool { * self == CFG_NSEL_A :: CFG_NSEL_SPARE } } # [doc = "Field `CFG_NSEL` writer - Negative OA input selection. Please refer to the device specific datasheet for exact channels available."] pub type CFG_NSEL_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 3 , O , CFG_NSEL_A > ; impl < 'a , REG , const O : u8 > CFG_NSEL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "NC"] # [inline (always)] pub fn cfg_nsel_nc (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_NSEL_A :: CFG_NSEL_NC) } # [doc = "EXTPIN0"] # [inline (always)] pub fn cfg_nsel_extpin0 (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_NSEL_A :: CFG_NSEL_EXTPIN0) } # [doc = "EXTPIN1"] # [inline (always)] pub fn cfg_nsel_extpin1 (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_NSEL_A :: CFG_NSEL_EXTPIN1) } # [doc = "OANP1RBOT"] # [inline (always)] pub fn cfg_nsel_oanp1rbot (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_NSEL_A :: CFG_NSEL_OANP1RBOT) } # [doc = "OANRTAP"] # [inline (always)] pub fn cfg_nsel_oanrtap (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_NSEL_A :: CFG_NSEL_OANRTAP) } # [doc = "OANRTOP"] # [inline (always)] pub fn cfg_nsel_oanrtop (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_NSEL_A :: CFG_NSEL_OANRTOP) } # [doc = "SPARE"] # [inline (always)] pub fn cfg_nsel_spare (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_NSEL_A :: CFG_NSEL_SPARE) } } # [doc = "Field `CFG_MSEL` reader - MSEL Mux selection. Please refer to the device specific datasheet for exact channels available."] pub type CFG_MSEL_R = crate :: FieldReader < CFG_MSEL_A > ; # [doc = "MSEL Mux selection. Please refer to the device specific datasheet for exact channels available.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum CFG_MSEL_A { # [doc = "0: NC"] CFG_MSEL_NC = 0 , # [doc = "1: EXTNPIN1"] CFG_MSEL_EXTNPIN1 = 1 , # [doc = "2: VSS"] CFG_MSEL_VSS = 2 , # [doc = "3: DAC12OUT"] CFG_MSEL_DAC12OUT = 3 , # [doc = "4: OANM1RTOP"] CFG_MSEL_OANM1RTOP = 4 , } impl From < CFG_MSEL_A > for u8 { # [inline (always)] fn from (variant : CFG_MSEL_A) -> Self { variant as _ } } impl crate :: FieldSpec for CFG_MSEL_A { type Ux = u8 ; } impl CFG_MSEL_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < CFG_MSEL_A > { match self . bits { 0 => Some (CFG_MSEL_A :: CFG_MSEL_NC) , 1 => Some (CFG_MSEL_A :: CFG_MSEL_EXTNPIN1) , 2 => Some (CFG_MSEL_A :: CFG_MSEL_VSS) , 3 => Some (CFG_MSEL_A :: CFG_MSEL_DAC12OUT) , 4 => Some (CFG_MSEL_A :: CFG_MSEL_OANM1RTOP) , _ => None , } } # [doc = "NC"] # [inline (always)] pub fn is_cfg_msel_nc (& self) -> bool { * self == CFG_MSEL_A :: CFG_MSEL_NC } # [doc = "EXTNPIN1"] # [inline (always)] pub fn is_cfg_msel_extnpin1 (& self) -> bool { * self == CFG_MSEL_A :: CFG_MSEL_EXTNPIN1 } # [doc = "VSS"] # [inline (always)] pub fn is_cfg_msel_vss (& self) -> bool { * self == CFG_MSEL_A :: CFG_MSEL_VSS } # [doc = "DAC12OUT"] # [inline (always)] pub fn is_cfg_msel_dac12out (& self) -> bool { * self == CFG_MSEL_A :: CFG_MSEL_DAC12OUT } # [doc = "OANM1RTOP"] # [inline (always)] pub fn is_cfg_msel_oanm1rtop (& self) -> bool { * self == CFG_MSEL_A :: CFG_MSEL_OANM1RTOP } } # [doc = "Field `CFG_MSEL` writer - MSEL Mux selection. Please refer to the device specific datasheet for exact channels available."] pub type CFG_MSEL_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 3 , O , CFG_MSEL_A > ; impl < 'a , REG , const O : u8 > CFG_MSEL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "NC"] # [inline (always)] pub fn cfg_msel_nc (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_MSEL_A :: CFG_MSEL_NC) } # [doc = "EXTNPIN1"] # [inline (always)] pub fn cfg_msel_extnpin1 (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_MSEL_A :: CFG_MSEL_EXTNPIN1) } # [doc = "VSS"] # [inline (always)] pub fn cfg_msel_vss (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_MSEL_A :: CFG_MSEL_VSS) } # [doc = "DAC12OUT"] # [inline (always)] pub fn cfg_msel_dac12out (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_MSEL_A :: CFG_MSEL_DAC12OUT) } # [doc = "OANM1RTOP"] # [inline (always)] pub fn cfg_msel_oanm1rtop (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_MSEL_A :: CFG_MSEL_OANM1RTOP) } } # [doc = "Field `CFG_GAIN` reader - Gain setting. Refer to TRM for enumeration information."] pub type CFG_GAIN_R = crate :: FieldReader ; # [doc = "Field `CFG_GAIN` writer - Gain setting. Refer to TRM for enumeration information."] pub type CFG_GAIN_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 3 , O > ; impl R { # [doc = "Bits 0:1 - Chopping enable."] # [inline (always)] pub fn cfg_chop (& self) -> CFG_CHOP_R { CFG_CHOP_R :: new ((self . bits & 3) as u8) } # [doc = "Bit 2 - Enable output pin"] # [inline (always)] pub fn cfg_outpin (& self) -> CFG_OUTPIN_R { CFG_OUTPIN_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bits 3:6 - Positive OA input selection. Please refer to the device specific datasheet for exact channels available."] # [inline (always)] pub fn cfg_psel (& self) -> CFG_PSEL_R { CFG_PSEL_R :: new (((self . bits >> 3) & 0x0f) as u8) } # [doc = "Bits 7:9 - Negative OA input selection. Please refer to the device specific datasheet for exact channels available."] # [inline (always)] pub fn cfg_nsel (& self) -> CFG_NSEL_R { CFG_NSEL_R :: new (((self . bits >> 7) & 7) as u8) } # [doc = "Bits 10:12 - MSEL Mux selection. Please refer to the device specific datasheet for exact channels available."] # [inline (always)] pub fn cfg_msel (& self) -> CFG_MSEL_R { CFG_MSEL_R :: new (((self . bits >> 10) & 7) as u8) } # [doc = "Bits 13:15 - Gain setting. Refer to TRM for enumeration information."] # [inline (always)] pub fn cfg_gain (& self) -> CFG_GAIN_R { CFG_GAIN_R :: new (((self . bits >> 13) & 7) as u8) } } impl W { # [doc = "Bits 0:1 - Chopping enable."] # [inline (always)] # [must_use] pub fn cfg_chop (& mut self) -> CFG_CHOP_W < CFG_SPEC , 0 > { CFG_CHOP_W :: new (self) } # [doc = "Bit 2 - Enable output pin"] # [inline (always)] # [must_use] pub fn cfg_outpin (& mut self) -> CFG_OUTPIN_W < CFG_SPEC , 2 > { CFG_OUTPIN_W :: new (self) } # [doc = "Bits 3:6 - Positive OA input selection. Please refer to the device specific datasheet for exact channels available."] # [inline (always)] # [must_use] pub fn cfg_psel (& mut self) -> CFG_PSEL_W <'_, CFG_SPEC , 3 > { CFG_PSEL_W :: new (self) } # [doc = "Bits 7:9 - Negative OA input selection. Please refer to the device specific datasheet for exact channels available."] # [inline (always)] # [must_use] pub fn cfg_nsel (& mut self) -> CFG_NSEL_W < CFG_SPEC , 7 > { CFG_NSEL_W :: new (self) } # [doc = "Bits 10:12 - MSEL Mux selection. Please refer to the device specific datasheet for exact channels available."] # [inline (always)] # [must_use] pub fn cfg_msel (& mut self) -> CFG_MSEL_W < CFG_SPEC , 10 > { CFG_MSEL_W :: new (self) } # [doc = "Bits 13:15 - Gain setting. Refer to TRM for enumeration information."] # [inline (always)] # [must_use] pub fn cfg_gain (& mut self) -> CFG_GAIN_W < CFG_SPEC , 13 > { CFG_GAIN_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Configuration Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CFG_SPEC ; impl crate :: RegisterSpec for CFG_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`cfg::R`](R) reader structure"] impl crate :: Readable for CFG_SPEC { } # [doc = "`write(|w| ..)` method takes [`cfg::W`](W) writer structure"] impl crate :: Writable for CFG_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets CFG to value 0"] impl crate :: Resettable for CFG_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/i2c1/mtxdata.rs:1:1000 [INFO] [stdout] | [INFO] [stdout] 1 | ...e] pub fn mtxdata_value (& mut self) -> MTXDATA_VALUE_W < MTXDATA_SPEC , 0 > { MTXDATA_VALUE_W :: new (self) } # [doc = r" Writes raw ... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `MTXDATA` reader"] pub type R = crate :: R < MTXDATA_SPEC > ; # [doc = "Register `MTXDATA` writer"] pub type W = crate :: W < MTXDATA_SPEC > ; # [doc = "Field `MTXDATA_VALUE` reader - Transmit Data This byte contains the data to be transferred during the next transaction."] pub type MTXDATA_VALUE_R = crate :: FieldReader ; # [doc = "Field `MTXDATA_VALUE` writer - Transmit Data This byte contains the data to be transferred during the next transaction."] pub type MTXDATA_VALUE_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 8 , O > ; impl R { # [doc = "Bits 0:7 - Transmit Data This byte contains the data to be transferred during the next transaction."] # [inline (always)] pub fn mtxdata_value (& self) -> MTXDATA_VALUE_R { MTXDATA_VALUE_R :: new ((self . bits & 0xff) as u8) } } impl W { # [doc = "Bits 0:7 - Transmit Data This byte contains the data to be transferred during the next transaction."] # [inline (always)] # [must_use] pub fn mtxdata_value (& mut self) -> MTXDATA_VALUE_W <'_, MTXDATA_SPEC , 0 > { MTXDATA_VALUE_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "I2C Master TXData\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mtxdata::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mtxdata::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct MTXDATA_SPEC ; impl crate :: RegisterSpec for MTXDATA_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`mtxdata::R`](R) reader structure"] impl crate :: Readable for MTXDATA_SPEC { } # [doc = "`write(|w| ..)` method takes [`mtxdata::W`](W) writer structure"] impl crate :: Writable for MTXDATA_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets MTXDATA to value 0"] impl crate :: Resettable for MTXDATA_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/gpioa/rstctl.rs:1:3243 [INFO] [stdout] | [INFO] [stdout] 1 | ...fn rstctl_resetassert (& mut self) -> RSTCTL_RESETASSERT_W < RSTCTL_SPEC , 0 > { RSTCTL_RESETASSERT_W :: new (self) } # [doc = "Bit 1 ... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `RSTCTL` writer"] pub type W = crate :: W < RSTCTL_SPEC > ; # [doc = "Assert reset to the peripheral\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum RSTCTL_RESETASSERT_AW { # [doc = "0: NOP"] RSTCTL_RESETASSERT_NOP = 0 , # [doc = "1: ASSERT"] RSTCTL_RESETASSERT_ASSERT = 1 , } impl From < RSTCTL_RESETASSERT_AW > for bool { # [inline (always)] fn from (variant : RSTCTL_RESETASSERT_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `RSTCTL_RESETASSERT` writer - Assert reset to the peripheral"] pub type RSTCTL_RESETASSERT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , RSTCTL_RESETASSERT_AW > ; impl < 'a , REG , const O : u8 > RSTCTL_RESETASSERT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NOP"] # [inline (always)] pub fn rstctl_resetassert_nop (self) -> & 'a mut crate :: W < REG > { self . variant (RSTCTL_RESETASSERT_AW :: RSTCTL_RESETASSERT_NOP) } # [doc = "ASSERT"] # [inline (always)] pub fn rstctl_resetassert_assert (self) -> & 'a mut crate :: W < REG > { self . variant (RSTCTL_RESETASSERT_AW :: RSTCTL_RESETASSERT_ASSERT) } } # [doc = "Clear the RESETSTKY bit in the STAT register\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum RSTCTL_RESETSTKYCLR_AW { # [doc = "0: NOP"] RSTCTL_RESETSTKYCLR_NOP = 0 , # [doc = "1: CLR"] RSTCTL_RESETSTKYCLR_CLR = 1 , } impl From < RSTCTL_RESETSTKYCLR_AW > for bool { # [inline (always)] fn from (variant : RSTCTL_RESETSTKYCLR_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `RSTCTL_RESETSTKYCLR` writer - Clear the RESETSTKY bit in the STAT register"] pub type RSTCTL_RESETSTKYCLR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , RSTCTL_RESETSTKYCLR_AW > ; impl < 'a , REG , const O : u8 > RSTCTL_RESETSTKYCLR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NOP"] # [inline (always)] pub fn rstctl_resetstkyclr_nop (self) -> & 'a mut crate :: W < REG > { self . variant (RSTCTL_RESETSTKYCLR_AW :: RSTCTL_RESETSTKYCLR_NOP) } # [doc = "CLR"] # [inline (always)] pub fn rstctl_resetstkyclr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (RSTCTL_RESETSTKYCLR_AW :: RSTCTL_RESETSTKYCLR_CLR) } } # [doc = "Unlock key\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum RSTCTL_KEY_AW { # [doc = "177: _TO_UNLOCK_W_"] RSTCTL_KEY_UNLOCK_W = 177 , } impl From < RSTCTL_KEY_AW > for u8 { # [inline (always)] fn from (variant : RSTCTL_KEY_AW) -> Self { variant as _ } } impl crate :: FieldSpec for RSTCTL_KEY_AW { type Ux = u8 ; } # [doc = "Field `RSTCTL_KEY` writer - Unlock key"] pub type RSTCTL_KEY_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 8 , O , RSTCTL_KEY_AW > ; impl < 'a , REG , const O : u8 > RSTCTL_KEY_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "_TO_UNLOCK_W_"] # [inline (always)] pub fn rstctl_key_unlock_w (self) -> & 'a mut crate :: W < REG > { self . variant (RSTCTL_KEY_AW :: RSTCTL_KEY_UNLOCK_W) } } impl W { # [doc = "Bit 0 - Assert reset to the peripheral"] # [inline (always)] # [must_use] pub fn rstctl_resetassert (& mut self) -> RSTCTL_RESETASSERT_W <'_, RSTCTL_SPEC , 0 > { RSTCTL_RESETASSERT_W :: new (self) } # [doc = "Bit 1 - Clear the RESETSTKY bit in the STAT register"] # [inline (always)] # [must_use] pub fn rstctl_resetstkyclr (& mut self) -> RSTCTL_RESETSTKYCLR_W < RSTCTL_SPEC , 1 > { RSTCTL_RESETSTKYCLR_W :: new (self) } # [doc = "Bits 24:31 - Unlock key"] # [inline (always)] # [must_use] pub fn rstctl_key (& mut self) -> RSTCTL_KEY_W < RSTCTL_SPEC , 24 > { RSTCTL_KEY_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Reset Control\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rstctl::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct RSTCTL_SPEC ; impl crate :: RegisterSpec for RSTCTL_SPEC { type Ux = u32 ; } # [doc = "`write(|w| ..)` method takes [`rstctl::W`](W) writer structure"] impl crate :: Writable for RSTCTL_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets RSTCTL to value 0"] impl crate :: Resettable for RSTCTL_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/i2c1/int_event2_iset.rs:1:5642 [INFO] [stdout] | [INFO] [stdout] 1 | ...t_mtxfifotrg (& mut self) -> INT_EVENT2_ISET_MTXFIFOTRG_W < INT_EVENT2_ISET_SPEC , 1 > { INT_EVENT2_ISET_MTXFIFOTRG_W :: new (self) } ... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `INT_EVENT2_ISET` writer"] pub type W = crate :: W < INT_EVENT2_ISET_SPEC > ; # [doc = "Master Receive FIFO Trigger Trigger when RX FIFO contains &gt;= defined bytes\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT2_ISET_MRXFIFOTRG_AW { # [doc = "0: NO_EFFECT"] INT_EVENT2_ISET_MRXFIFOTRG_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT2_ISET_MRXFIFOTRG_SET = 1 , } impl From < INT_EVENT2_ISET_MRXFIFOTRG_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT2_ISET_MRXFIFOTRG_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT2_ISET_MRXFIFOTRG` writer - Master Receive FIFO Trigger Trigger when RX FIFO contains &gt;= defined bytes"] pub type INT_EVENT2_ISET_MRXFIFOTRG_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT2_ISET_MRXFIFOTRG_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT2_ISET_MRXFIFOTRG_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event2_iset_mrxfifotrg_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT2_ISET_MRXFIFOTRG_AW :: INT_EVENT2_ISET_MRXFIFOTRG_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event2_iset_mrxfifotrg_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT2_ISET_MRXFIFOTRG_AW :: INT_EVENT2_ISET_MRXFIFOTRG_SET) } } # [doc = "Master Transmit FIFO Trigger Trigger when Transmit FIFO contains &lt;= defined bytes\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT2_ISET_MTXFIFOTRG_AW { # [doc = "0: NO_EFFECT"] INT_EVENT2_ISET_MTXFIFOTRG_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT2_ISET_MTXFIFOTRG_SET = 1 , } impl From < INT_EVENT2_ISET_MTXFIFOTRG_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT2_ISET_MTXFIFOTRG_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT2_ISET_MTXFIFOTRG` writer - Master Transmit FIFO Trigger Trigger when Transmit FIFO contains &lt;= defined bytes"] pub type INT_EVENT2_ISET_MTXFIFOTRG_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT2_ISET_MTXFIFOTRG_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT2_ISET_MTXFIFOTRG_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event2_iset_mtxfifotrg_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT2_ISET_MTXFIFOTRG_AW :: INT_EVENT2_ISET_MTXFIFOTRG_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event2_iset_mtxfifotrg_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT2_ISET_MTXFIFOTRG_AW :: INT_EVENT2_ISET_MTXFIFOTRG_SET) } } # [doc = "Slave Receive FIFO Trigger\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT2_ISET_SRXFIFOTRG_AW { # [doc = "0: NO_EFFECT"] INT_EVENT2_ISET_SRXFIFOTRG_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT2_ISET_SRXFIFOTRG_SET = 1 , } impl From < INT_EVENT2_ISET_SRXFIFOTRG_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT2_ISET_SRXFIFOTRG_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT2_ISET_SRXFIFOTRG` writer - Slave Receive FIFO Trigger"] pub type INT_EVENT2_ISET_SRXFIFOTRG_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT2_ISET_SRXFIFOTRG_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT2_ISET_SRXFIFOTRG_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event2_iset_srxfifotrg_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT2_ISET_SRXFIFOTRG_AW :: INT_EVENT2_ISET_SRXFIFOTRG_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event2_iset_srxfifotrg_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT2_ISET_SRXFIFOTRG_AW :: INT_EVENT2_ISET_SRXFIFOTRG_SET) } } # [doc = "Slave Transmit FIFO Trigger\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT2_ISET_STXFIFOTRG_AW { # [doc = "0: NO_EFFECT"] INT_EVENT2_ISET_STXFIFOTRG_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT2_ISET_STXFIFOTRG_SET = 1 , } impl From < INT_EVENT2_ISET_STXFIFOTRG_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT2_ISET_STXFIFOTRG_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT2_ISET_STXFIFOTRG` writer - Slave Transmit FIFO Trigger"] pub type INT_EVENT2_ISET_STXFIFOTRG_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT2_ISET_STXFIFOTRG_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT2_ISET_STXFIFOTRG_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event2_iset_stxfifotrg_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT2_ISET_STXFIFOTRG_AW :: INT_EVENT2_ISET_STXFIFOTRG_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event2_iset_stxfifotrg_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT2_ISET_STXFIFOTRG_AW :: INT_EVENT2_ISET_STXFIFOTRG_SET) } } impl W { # [doc = "Bit 0 - Master Receive FIFO Trigger Trigger when RX FIFO contains &gt;= defined bytes"] # [inline (always)] # [must_use] pub fn int_event2_iset_mrxfifotrg (& mut self) -> INT_EVENT2_ISET_MRXFIFOTRG_W < INT_EVENT2_ISET_SPEC , 0 > { INT_EVENT2_ISET_MRXFIFOTRG_W :: new (self) } # [doc = "Bit 1 - Master Transmit FIFO Trigger Trigger when Transmit FIFO contains &lt;= defined bytes"] # [inline (always)] # [must_use] pub fn int_event2_iset_mtxfifotrg (& mut self) -> INT_EVENT2_ISET_MTXFIFOTRG_W <'_, INT_EVENT2_ISET_SPEC , 1 > { INT_EVENT2_ISET_MTXFIFOTRG_W :: new (self) } # [doc = "Bit 2 - Slave Receive FIFO Trigger"] # [inline (always)] # [must_use] pub fn int_event2_iset_srxfifotrg (& mut self) -> INT_EVENT2_ISET_SRXFIFOTRG_W < INT_EVENT2_ISET_SPEC , 2 > { INT_EVENT2_ISET_SRXFIFOTRG_W :: new (self) } # [doc = "Bit 3 - Slave Transmit FIFO Trigger"] # [inline (always)] # [must_use] pub fn int_event2_iset_stxfifotrg (& mut self) -> INT_EVENT2_ISET_STXFIFOTRG_W < INT_EVENT2_ISET_SPEC , 3 > { INT_EVENT2_ISET_STXFIFOTRG_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Interrupt set\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_event2_iset::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct INT_EVENT2_ISET_SPEC ; impl crate :: RegisterSpec for INT_EVENT2_ISET_SPEC { type Ux = u32 ; } # [doc = "`write(|w| ..)` method takes [`int_event2_iset::W`](W) writer structure"] impl crate :: Writable for INT_EVENT2_ISET_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets INT_EVENT2_ISET to value 0"] impl crate :: Resettable for INT_EVENT2_ISET_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/i2c1/rstctl.rs:1:3649 [INFO] [stdout] | [INFO] [stdout] 1 | ...t_use] pub fn rstctl_key (& mut self) -> RSTCTL_KEY_W < RSTCTL_SPEC , 24 > { RSTCTL_KEY_W :: new (self) } # [doc = r" Writes raw bits ... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `RSTCTL` writer"] pub type W = crate :: W < RSTCTL_SPEC > ; # [doc = "Assert reset to the peripheral\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum RSTCTL_RESETASSERT_AW { # [doc = "0: NOP"] RSTCTL_RESETASSERT_NOP = 0 , # [doc = "1: ASSERT"] RSTCTL_RESETASSERT_ASSERT = 1 , } impl From < RSTCTL_RESETASSERT_AW > for bool { # [inline (always)] fn from (variant : RSTCTL_RESETASSERT_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `RSTCTL_RESETASSERT` writer - Assert reset to the peripheral"] pub type RSTCTL_RESETASSERT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , RSTCTL_RESETASSERT_AW > ; impl < 'a , REG , const O : u8 > RSTCTL_RESETASSERT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NOP"] # [inline (always)] pub fn rstctl_resetassert_nop (self) -> & 'a mut crate :: W < REG > { self . variant (RSTCTL_RESETASSERT_AW :: RSTCTL_RESETASSERT_NOP) } # [doc = "ASSERT"] # [inline (always)] pub fn rstctl_resetassert_assert (self) -> & 'a mut crate :: W < REG > { self . variant (RSTCTL_RESETASSERT_AW :: RSTCTL_RESETASSERT_ASSERT) } } # [doc = "Clear the RESETSTKY bit in the STAT register\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum RSTCTL_RESETSTKYCLR_AW { # [doc = "0: NOP"] RSTCTL_RESETSTKYCLR_NOP = 0 , # [doc = "1: CLR"] RSTCTL_RESETSTKYCLR_CLR = 1 , } impl From < RSTCTL_RESETSTKYCLR_AW > for bool { # [inline (always)] fn from (variant : RSTCTL_RESETSTKYCLR_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `RSTCTL_RESETSTKYCLR` writer - Clear the RESETSTKY bit in the STAT register"] pub type RSTCTL_RESETSTKYCLR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , RSTCTL_RESETSTKYCLR_AW > ; impl < 'a , REG , const O : u8 > RSTCTL_RESETSTKYCLR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NOP"] # [inline (always)] pub fn rstctl_resetstkyclr_nop (self) -> & 'a mut crate :: W < REG > { self . variant (RSTCTL_RESETSTKYCLR_AW :: RSTCTL_RESETSTKYCLR_NOP) } # [doc = "CLR"] # [inline (always)] pub fn rstctl_resetstkyclr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (RSTCTL_RESETSTKYCLR_AW :: RSTCTL_RESETSTKYCLR_CLR) } } # [doc = "Unlock key\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum RSTCTL_KEY_AW { # [doc = "177: _TO_UNLOCK_W_"] RSTCTL_KEY_UNLOCK_W = 177 , } impl From < RSTCTL_KEY_AW > for u8 { # [inline (always)] fn from (variant : RSTCTL_KEY_AW) -> Self { variant as _ } } impl crate :: FieldSpec for RSTCTL_KEY_AW { type Ux = u8 ; } # [doc = "Field `RSTCTL_KEY` writer - Unlock key"] pub type RSTCTL_KEY_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 8 , O , RSTCTL_KEY_AW > ; impl < 'a , REG , const O : u8 > RSTCTL_KEY_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "_TO_UNLOCK_W_"] # [inline (always)] pub fn rstctl_key_unlock_w (self) -> & 'a mut crate :: W < REG > { self . variant (RSTCTL_KEY_AW :: RSTCTL_KEY_UNLOCK_W) } } impl W { # [doc = "Bit 0 - Assert reset to the peripheral"] # [inline (always)] # [must_use] pub fn rstctl_resetassert (& mut self) -> RSTCTL_RESETASSERT_W < RSTCTL_SPEC , 0 > { RSTCTL_RESETASSERT_W :: new (self) } # [doc = "Bit 1 - Clear the RESETSTKY bit in the STAT register"] # [inline (always)] # [must_use] pub fn rstctl_resetstkyclr (& mut self) -> RSTCTL_RESETSTKYCLR_W < RSTCTL_SPEC , 1 > { RSTCTL_RESETSTKYCLR_W :: new (self) } # [doc = "Bits 24:31 - Unlock key"] # [inline (always)] # [must_use] pub fn rstctl_key (& mut self) -> RSTCTL_KEY_W <'_, RSTCTL_SPEC , 24 > { RSTCTL_KEY_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Reset Control\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rstctl::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct RSTCTL_SPEC ; impl crate :: RegisterSpec for RSTCTL_SPEC { type Ux = u32 ; } # [doc = "`write(|w| ..)` method takes [`rstctl::W`](W) writer structure"] impl crate :: Writable for RSTCTL_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets RSTCTL to value 0"] impl crate :: Resettable for RSTCTL_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/i2c0/master_i2cpecctl.rs:1:9830 [INFO] [stdout] | [INFO] [stdout] 1 | ...pecctl_peccnt (& mut self) -> MASTER_I2CPECCTL_PECCNT_W < MASTER_I2CPECCTL_SPEC , 0 > { MASTER_I2CPECCTL_PECCNT_W :: new (self) } # [d... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `MASTER_I2CPECCTL` reader"] pub type R = crate :: R < MASTER_I2CPECCTL_SPEC > ; # [doc = "Register `MASTER_I2CPECCTL` writer"] pub type W = crate :: W < MASTER_I2CPECCTL_SPEC > ; # [doc = "Field `MASTER_I2CPECCTL_PECCNT` reader - PEC Count When this field is non zero, the number of I2C bytes are counted (Note that although the PEC is calculated on the I2C address it is not counted at a byte). When the byte count = PECCNT and the state machine is transmitting, the contents of the LSFR is loaded into the shift register instead of the byte received from the Tx FIFO. When the state machine is receiving, after the last bit of this byte is received the LSFR is checked and if it is non-zero, a PEC RX Error interrupt is generated. The I2C packet must be padded to include the PEC byte for both transmit and receive. In transmit mode the FIFO must be loaded with a dummy PEC byte. In receive mode the PEC byte will be passed to the Rx FIFO. In the normal Master use case, FW would set PECEN=1 and PECCNT=SMB packet length (Not including Slave Address byte, but including the PEC byte). FW would then configure DMA to allow the packet to complete unassisted and write MCTR to initiate the transaction. Note that when the byte count = PEC CNT, the byte count is reset to 0 and multiple PEC calculation can automatically occur within a single I2C transaction. Note that any write to the MASTER_I2CPECCTL Register will clear the current PEC Byte Count in the Master State Machine."] pub type MASTER_I2CPECCTL_PECCNT_R = crate :: FieldReader < u16 > ; # [doc = "Field `MASTER_I2CPECCTL_PECCNT` writer - PEC Count When this field is non zero, the number of I2C bytes are counted (Note that although the PEC is calculated on the I2C address it is not counted at a byte). When the byte count = PECCNT and the state machine is transmitting, the contents of the LSFR is loaded into the shift register instead of the byte received from the Tx FIFO. When the state machine is receiving, after the last bit of this byte is received the LSFR is checked and if it is non-zero, a PEC RX Error interrupt is generated. The I2C packet must be padded to include the PEC byte for both transmit and receive. In transmit mode the FIFO must be loaded with a dummy PEC byte. In receive mode the PEC byte will be passed to the Rx FIFO. In the normal Master use case, FW would set PECEN=1 and PECCNT=SMB packet length (Not including Slave Address byte, but including the PEC byte). FW would then configure DMA to allow the packet to complete unassisted and write MCTR to initiate the transaction. Note that when the byte count = PEC CNT, the byte count is reset to 0 and multiple PEC calculation can automatically occur within a single I2C transaction. Note that any write to the MASTER_I2CPECCTL Register will clear the current PEC Byte Count in the Master State Machine."] pub type MASTER_I2CPECCTL_PECCNT_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 9 , O , u16 > ; # [doc = "Field `MASTER_I2CPECCTL_PECEN` reader - PEC Enable This bit enables the SMB Packet Error Checking (PEC). When enabled the PEC is calculated on all bits accept the Start, Stop, Ack and Nack. The PEC LSFR and the Byte Counter is set to 0 when the State Machine is in the IDLE state, which occur following a Stop or when a timeout occurs. The Counter is also set to 0 after the PEC byte is sent or received. Note that the NACK is automatically send following a PEC byte that results in a PEC error. The PEC Polynomial is x^8 + x^2 + x^1 + 1."] pub type MASTER_I2CPECCTL_PECEN_R = crate :: BitReader < MASTER_I2CPECCTL_PECEN_A > ; # [doc = "PEC Enable This bit enables the SMB Packet Error Checking (PEC). When enabled the PEC is calculated on all bits accept the Start, Stop, Ack and Nack. The PEC LSFR and the Byte Counter is set to 0 when the State Machine is in the IDLE state, which occur following a Stop or when a timeout occurs. The Counter is also set to 0 after the PEC byte is sent or received. Note that the NACK is automatically send following a PEC byte that results in a PEC error. The PEC Polynomial is x^8 + x^2 + x^1 + 1.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum MASTER_I2CPECCTL_PECEN_A { # [doc = "0: DISABLE"] MASTER_I2CPECCTL_PECEN_DISABLE = 0 , # [doc = "1: ENABLE"] MASTER_I2CPECCTL_PECEN_ENABLE = 1 , } impl From < MASTER_I2CPECCTL_PECEN_A > for bool { # [inline (always)] fn from (variant : MASTER_I2CPECCTL_PECEN_A) -> Self { variant as u8 != 0 } } impl MASTER_I2CPECCTL_PECEN_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> MASTER_I2CPECCTL_PECEN_A { match self . bits { false => MASTER_I2CPECCTL_PECEN_A :: MASTER_I2CPECCTL_PECEN_DISABLE , true => MASTER_I2CPECCTL_PECEN_A :: MASTER_I2CPECCTL_PECEN_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_master_i2cpecctl_pecen_disable (& self) -> bool { * self == MASTER_I2CPECCTL_PECEN_A :: MASTER_I2CPECCTL_PECEN_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_master_i2cpecctl_pecen_enable (& self) -> bool { * self == MASTER_I2CPECCTL_PECEN_A :: MASTER_I2CPECCTL_PECEN_ENABLE } } # [doc = "Field `MASTER_I2CPECCTL_PECEN` writer - PEC Enable This bit enables the SMB Packet Error Checking (PEC). When enabled the PEC is calculated on all bits accept the Start, Stop, Ack and Nack. The PEC LSFR and the Byte Counter is set to 0 when the State Machine is in the IDLE state, which occur following a Stop or when a timeout occurs. The Counter is also set to 0 after the PEC byte is sent or received. Note that the NACK is automatically send following a PEC byte that results in a PEC error. The PEC Polynomial is x^8 + x^2 + x^1 + 1."] pub type MASTER_I2CPECCTL_PECEN_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , MASTER_I2CPECCTL_PECEN_A > ; impl < 'a , REG , const O : u8 > MASTER_I2CPECCTL_PECEN_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn master_i2cpecctl_pecen_disable (self) -> & 'a mut crate :: W < REG > { self . variant (MASTER_I2CPECCTL_PECEN_A :: MASTER_I2CPECCTL_PECEN_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn master_i2cpecctl_pecen_enable (self) -> & 'a mut crate :: W < REG > { self . variant (MASTER_I2CPECCTL_PECEN_A :: MASTER_I2CPECCTL_PECEN_ENABLE) } } impl R { # [doc = "Bits 0:8 - PEC Count When this field is non zero, the number of I2C bytes are counted (Note that although the PEC is calculated on the I2C address it is not counted at a byte). When the byte count = PECCNT and the state machine is transmitting, the contents of the LSFR is loaded into the shift register instead of the byte received from the Tx FIFO. When the state machine is receiving, after the last bit of this byte is received the LSFR is checked and if it is non-zero, a PEC RX Error interrupt is generated. The I2C packet must be padded to include the PEC byte for both transmit and receive. In transmit mode the FIFO must be loaded with a dummy PEC byte. In receive mode the PEC byte will be passed to the Rx FIFO. In the normal Master use case, FW would set PECEN=1 and PECCNT=SMB packet length (Not including Slave Address byte, but including the PEC byte). FW would then configure DMA to allow the packet to complete unassisted and write MCTR to initiate the transaction. Note that when the byte count = PEC CNT, the byte count is reset to 0 and multiple PEC calculation can automatically occur within a single I2C transaction. Note that any write to the MASTER_I2CPECCTL Register will clear the current PEC Byte Count in the Master State Machine."] # [inline (always)] pub fn master_i2cpecctl_peccnt (& self) -> MASTER_I2CPECCTL_PECCNT_R { MASTER_I2CPECCTL_PECCNT_R :: new ((self . bits & 0x01ff) as u16) } # [doc = "Bit 12 - PEC Enable This bit enables the SMB Packet Error Checking (PEC). When enabled the PEC is calculated on all bits accept the Start, Stop, Ack and Nack. The PEC LSFR and the Byte Counter is set to 0 when the State Machine is in the IDLE state, which occur following a Stop or when a timeout occurs. The Counter is also set to 0 after the PEC byte is sent or received. Note that the NACK is automatically send following a PEC byte that results in a PEC error. The PEC Polynomial is x^8 + x^2 + x^1 + 1."] # [inline (always)] pub fn master_i2cpecctl_pecen (& self) -> MASTER_I2CPECCTL_PECEN_R { MASTER_I2CPECCTL_PECEN_R :: new (((self . bits >> 12) & 1) != 0) } } impl W { # [doc = "Bits 0:8 - PEC Count When this field is non zero, the number of I2C bytes are counted (Note that although the PEC is calculated on the I2C address it is not counted at a byte). When the byte count = PECCNT and the state machine is transmitting, the contents of the LSFR is loaded into the shift register instead of the byte received from the Tx FIFO. When the state machine is receiving, after the last bit of this byte is received the LSFR is checked and if it is non-zero, a PEC RX Error interrupt is generated. The I2C packet must be padded to include the PEC byte for both transmit and receive. In transmit mode the FIFO must be loaded with a dummy PEC byte. In receive mode the PEC byte will be passed to the Rx FIFO. In the normal Master use case, FW would set PECEN=1 and PECCNT=SMB packet length (Not including Slave Address byte, but including the PEC byte). FW would then configure DMA to allow the packet to complete unassisted and write MCTR to initiate the transaction. Note that when the byte count = PEC CNT, the byte count is reset to 0 and multiple PEC calculation can automatically occur within a single I2C transaction. Note that any write to the MASTER_I2CPECCTL Register will clear the current PEC Byte Count in the Master State Machine."] # [inline (always)] # [must_use] pub fn master_i2cpecctl_peccnt (& mut self) -> MASTER_I2CPECCTL_PECCNT_W <'_, MASTER_I2CPECCTL_SPEC , 0 > { MASTER_I2CPECCTL_PECCNT_W :: new (self) } # [doc = "Bit 12 - PEC Enable This bit enables the SMB Packet Error Checking (PEC). When enabled the PEC is calculated on all bits accept the Start, Stop, Ack and Nack. The PEC LSFR and the Byte Counter is set to 0 when the State Machine is in the IDLE state, which occur following a Stop or when a timeout occurs. The Counter is also set to 0 after the PEC byte is sent or received. Note that the NACK is automatically send following a PEC byte that results in a PEC error. The PEC Polynomial is x^8 + x^2 + x^1 + 1."] # [inline (always)] # [must_use] pub fn master_i2cpecctl_pecen (& mut self) -> MASTER_I2CPECCTL_PECEN_W < MASTER_I2CPECCTL_SPEC , 12 > { MASTER_I2CPECCTL_PECEN_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "I2C master PEC control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`master_i2cpecctl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`master_i2cpecctl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct MASTER_I2CPECCTL_SPEC ; impl crate :: RegisterSpec for MASTER_I2CPECCTL_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`master_i2cpecctl::R`](R) reader structure"] impl crate :: Readable for MASTER_I2CPECCTL_SPEC { } # [doc = "`write(|w| ..)` method takes [`master_i2cpecctl::W`](W) writer structure"] impl crate :: Writable for MASTER_I2CPECCTL_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets MASTER_I2CPECCTL to value 0"] impl crate :: Resettable for MASTER_I2CPECCTL_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/timg4/ccact_01.rs:1:23780 [INFO] [stdout] | [INFO] [stdout] 1 | ... pub fn ccact_01_cdact (& mut self) -> CCACT_01_CDACT_W < CCACT_01_SPEC , 6 > { CCACT_01_CDACT_W :: new (self) } # [doc = "Bits 9:10 -... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `CCACT_01[%s]` reader"] pub type R = crate :: R < CCACT_01_SPEC > ; # [doc = "Register `CCACT_01[%s]` writer"] pub type W = crate :: W < CCACT_01_SPEC > ; # [doc = "Field `CCACT_01_ZACT` reader - CCP Output Action on Zero Specifies what changes occur to CCP output as the result of a zero event."] pub type CCACT_01_ZACT_R = crate :: FieldReader < CCACT_01_ZACT_A > ; # [doc = "CCP Output Action on Zero Specifies what changes occur to CCP output as the result of a zero event.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum CCACT_01_ZACT_A { # [doc = "0: DISABLED"] CCACT_01_ZACT_DISABLED = 0 , # [doc = "1: CCP_HIGH"] CCACT_01_ZACT_CCP_HIGH = 1 , # [doc = "2: CCP_LOW"] CCACT_01_ZACT_CCP_LOW = 2 , # [doc = "3: CCP_TOGGLE"] CCACT_01_ZACT_CCP_TOGGLE = 3 , } impl From < CCACT_01_ZACT_A > for u8 { # [inline (always)] fn from (variant : CCACT_01_ZACT_A) -> Self { variant as _ } } impl crate :: FieldSpec for CCACT_01_ZACT_A { type Ux = u8 ; } impl CCACT_01_ZACT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CCACT_01_ZACT_A { match self . bits { 0 => CCACT_01_ZACT_A :: CCACT_01_ZACT_DISABLED , 1 => CCACT_01_ZACT_A :: CCACT_01_ZACT_CCP_HIGH , 2 => CCACT_01_ZACT_A :: CCACT_01_ZACT_CCP_LOW , 3 => CCACT_01_ZACT_A :: CCACT_01_ZACT_CCP_TOGGLE , _ => unreachable ! () , } } # [doc = "DISABLED"] # [inline (always)] pub fn is_ccact_01_zact_disabled (& self) -> bool { * self == CCACT_01_ZACT_A :: CCACT_01_ZACT_DISABLED } # [doc = "CCP_HIGH"] # [inline (always)] pub fn is_ccact_01_zact_ccp_high (& self) -> bool { * self == CCACT_01_ZACT_A :: CCACT_01_ZACT_CCP_HIGH } # [doc = "CCP_LOW"] # [inline (always)] pub fn is_ccact_01_zact_ccp_low (& self) -> bool { * self == CCACT_01_ZACT_A :: CCACT_01_ZACT_CCP_LOW } # [doc = "CCP_TOGGLE"] # [inline (always)] pub fn is_ccact_01_zact_ccp_toggle (& self) -> bool { * self == CCACT_01_ZACT_A :: CCACT_01_ZACT_CCP_TOGGLE } } # [doc = "Field `CCACT_01_ZACT` writer - CCP Output Action on Zero Specifies what changes occur to CCP output as the result of a zero event."] pub type CCACT_01_ZACT_W < 'a , REG , const O : u8 > = crate :: FieldWriterSafe < 'a , REG , 2 , O , CCACT_01_ZACT_A > ; impl < 'a , REG , const O : u8 > CCACT_01_ZACT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "DISABLED"] # [inline (always)] pub fn ccact_01_zact_disabled (self) -> & 'a mut crate :: W < REG > { self . variant (CCACT_01_ZACT_A :: CCACT_01_ZACT_DISABLED) } # [doc = "CCP_HIGH"] # [inline (always)] pub fn ccact_01_zact_ccp_high (self) -> & 'a mut crate :: W < REG > { self . variant (CCACT_01_ZACT_A :: CCACT_01_ZACT_CCP_HIGH) } # [doc = "CCP_LOW"] # [inline (always)] pub fn ccact_01_zact_ccp_low (self) -> & 'a mut crate :: W < REG > { self . variant (CCACT_01_ZACT_A :: CCACT_01_ZACT_CCP_LOW) } # [doc = "CCP_TOGGLE"] # [inline (always)] pub fn ccact_01_zact_ccp_toggle (self) -> & 'a mut crate :: W < REG > { self . variant (CCACT_01_ZACT_A :: CCACT_01_ZACT_CCP_TOGGLE) } } # [doc = "Field `CCACT_01_LACT` reader - CCP Output Action on Load Specifies what changes occur to CCP output as the result of a load event."] pub type CCACT_01_LACT_R = crate :: FieldReader < CCACT_01_LACT_A > ; # [doc = "CCP Output Action on Load Specifies what changes occur to CCP output as the result of a load event.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum CCACT_01_LACT_A { # [doc = "0: DISABLED"] CCACT_01_LACT_DISABLED = 0 , # [doc = "1: CCP_HIGH"] CCACT_01_LACT_CCP_HIGH = 1 , # [doc = "2: CCP_LOW"] CCACT_01_LACT_CCP_LOW = 2 , # [doc = "3: CCP_TOGGLE"] CCACT_01_LACT_CCP_TOGGLE = 3 , } impl From < CCACT_01_LACT_A > for u8 { # [inline (always)] fn from (variant : CCACT_01_LACT_A) -> Self { variant as _ } } impl crate :: FieldSpec for CCACT_01_LACT_A { type Ux = u8 ; } impl CCACT_01_LACT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CCACT_01_LACT_A { match self . bits { 0 => CCACT_01_LACT_A :: CCACT_01_LACT_DISABLED , 1 => CCACT_01_LACT_A :: CCACT_01_LACT_CCP_HIGH , 2 => CCACT_01_LACT_A :: CCACT_01_LACT_CCP_LOW , 3 => CCACT_01_LACT_A :: CCACT_01_LACT_CCP_TOGGLE , _ => unreachable ! () , } } # [doc = "DISABLED"] # [inline (always)] pub fn is_ccact_01_lact_disabled (& self) -> bool { * self == CCACT_01_LACT_A :: CCACT_01_LACT_DISABLED } # [doc = "CCP_HIGH"] # [inline (always)] pub fn is_ccact_01_lact_ccp_high (& self) -> bool { * self == CCACT_01_LACT_A :: CCACT_01_LACT_CCP_HIGH } # [doc = "CCP_LOW"] # [inline (always)] pub fn is_ccact_01_lact_ccp_low (& self) -> bool { * self == CCACT_01_LACT_A :: CCACT_01_LACT_CCP_LOW } # [doc = "CCP_TOGGLE"] # [inline (always)] pub fn is_ccact_01_lact_ccp_toggle (& self) -> bool { * self == CCACT_01_LACT_A :: CCACT_01_LACT_CCP_TOGGLE } } # [doc = "Field `CCACT_01_LACT` writer - CCP Output Action on Load Specifies what changes occur to CCP output as the result of a load event."] pub type CCACT_01_LACT_W < 'a , REG , const O : u8 > = crate :: FieldWriterSafe < 'a , REG , 2 , O , CCACT_01_LACT_A > ; impl < 'a , REG , const O : u8 > CCACT_01_LACT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "DISABLED"] # [inline (always)] pub fn ccact_01_lact_disabled (self) -> & 'a mut crate :: W < REG > { self . variant (CCACT_01_LACT_A :: CCACT_01_LACT_DISABLED) } # [doc = "CCP_HIGH"] # [inline (always)] pub fn ccact_01_lact_ccp_high (self) -> & 'a mut crate :: W < REG > { self . variant (CCACT_01_LACT_A :: CCACT_01_LACT_CCP_HIGH) } # [doc = "CCP_LOW"] # [inline (always)] pub fn ccact_01_lact_ccp_low (self) -> & 'a mut crate :: W < REG > { self . variant (CCACT_01_LACT_A :: CCACT_01_LACT_CCP_LOW) } # [doc = "CCP_TOGGLE"] # [inline (always)] pub fn ccact_01_lact_ccp_toggle (self) -> & 'a mut crate :: W < REG > { self . variant (CCACT_01_LACT_A :: CCACT_01_LACT_CCP_TOGGLE) } } # [doc = "Field `CCACT_01_CDACT` reader - CCP Output Action on Compare (Down) This field describes the resulting action of the signal generator upon detecting a compare event while counting down."] pub type CCACT_01_CDACT_R = crate :: FieldReader < CCACT_01_CDACT_A > ; # [doc = "CCP Output Action on Compare (Down) This field describes the resulting action of the signal generator upon detecting a compare event while counting down.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum CCACT_01_CDACT_A { # [doc = "0: DISABLED"] CCACT_01_CDACT_DISABLED = 0 , # [doc = "1: CCP_HIGH"] CCACT_01_CDACT_CCP_HIGH = 1 , # [doc = "2: CCP_LOW"] CCACT_01_CDACT_CCP_LOW = 2 , # [doc = "3: CCP_TOGGLE"] CCACT_01_CDACT_CCP_TOGGLE = 3 , } impl From < CCACT_01_CDACT_A > for u8 { # [inline (always)] fn from (variant : CCACT_01_CDACT_A) -> Self { variant as _ } } impl crate :: FieldSpec for CCACT_01_CDACT_A { type Ux = u8 ; } impl CCACT_01_CDACT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CCACT_01_CDACT_A { match self . bits { 0 => CCACT_01_CDACT_A :: CCACT_01_CDACT_DISABLED , 1 => CCACT_01_CDACT_A :: CCACT_01_CDACT_CCP_HIGH , 2 => CCACT_01_CDACT_A :: CCACT_01_CDACT_CCP_LOW , 3 => CCACT_01_CDACT_A :: CCACT_01_CDACT_CCP_TOGGLE , _ => unreachable ! () , } } # [doc = "DISABLED"] # [inline (always)] pub fn is_ccact_01_cdact_disabled (& self) -> bool { * self == CCACT_01_CDACT_A :: CCACT_01_CDACT_DISABLED } # [doc = "CCP_HIGH"] # [inline (always)] pub fn is_ccact_01_cdact_ccp_high (& self) -> bool { * self == CCACT_01_CDACT_A :: CCACT_01_CDACT_CCP_HIGH } # [doc = "CCP_LOW"] # [inline (always)] pub fn is_ccact_01_cdact_ccp_low (& self) -> bool { * self == CCACT_01_CDACT_A :: CCACT_01_CDACT_CCP_LOW } # [doc = "CCP_TOGGLE"] # [inline (always)] pub fn is_ccact_01_cdact_ccp_toggle (& self) -> bool { * self == CCACT_01_CDACT_A :: CCACT_01_CDACT_CCP_TOGGLE } } # [doc = "Field `CCACT_01_CDACT` writer - CCP Output Action on Compare (Down) This field describes the resulting action of the signal generator upon detecting a compare event while counting down."] pub type CCACT_01_CDACT_W < 'a , REG , const O : u8 > = crate :: FieldWriterSafe < 'a , REG , 2 , O , CCACT_01_CDACT_A > ; impl < 'a , REG , const O : u8 > CCACT_01_CDACT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "DISABLED"] # [inline (always)] pub fn ccact_01_cdact_disabled (self) -> & 'a mut crate :: W < REG > { self . variant (CCACT_01_CDACT_A :: CCACT_01_CDACT_DISABLED) } # [doc = "CCP_HIGH"] # [inline (always)] pub fn ccact_01_cdact_ccp_high (self) -> & 'a mut crate :: W < REG > { self . variant (CCACT_01_CDACT_A :: CCACT_01_CDACT_CCP_HIGH) } # [doc = "CCP_LOW"] # [inline (always)] pub fn ccact_01_cdact_ccp_low (self) -> & 'a mut crate :: W < REG > { self . variant (CCACT_01_CDACT_A :: CCACT_01_CDACT_CCP_LOW) } # [doc = "CCP_TOGGLE"] # [inline (always)] pub fn ccact_01_cdact_ccp_toggle (self) -> & 'a mut crate :: W < REG > { self . variant (CCACT_01_CDACT_A :: CCACT_01_CDACT_CCP_TOGGLE) } } # [doc = "Field `CCACT_01_CUACT` reader - CCP Output Action on Compare (Up) This field describes the resulting action of the signal generator upon detecting a compare event while counting up."] pub type CCACT_01_CUACT_R = crate :: FieldReader < CCACT_01_CUACT_A > ; # [doc = "CCP Output Action on Compare (Up) This field describes the resulting action of the signal generator upon detecting a compare event while counting up.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum CCACT_01_CUACT_A { # [doc = "0: DISABLED"] CCACT_01_CUACT_DISABLED = 0 , # [doc = "1: CCP_HIGH"] CCACT_01_CUACT_CCP_HIGH = 1 , # [doc = "2: CCP_LOW"] CCACT_01_CUACT_CCP_LOW = 2 , # [doc = "3: CCP_TOGGLE"] CCACT_01_CUACT_CCP_TOGGLE = 3 , } impl From < CCACT_01_CUACT_A > for u8 { # [inline (always)] fn from (variant : CCACT_01_CUACT_A) -> Self { variant as _ } } impl crate :: FieldSpec for CCACT_01_CUACT_A { type Ux = u8 ; } impl CCACT_01_CUACT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CCACT_01_CUACT_A { match self . bits { 0 => CCACT_01_CUACT_A :: CCACT_01_CUACT_DISABLED , 1 => CCACT_01_CUACT_A :: CCACT_01_CUACT_CCP_HIGH , 2 => CCACT_01_CUACT_A :: CCACT_01_CUACT_CCP_LOW , 3 => CCACT_01_CUACT_A :: CCACT_01_CUACT_CCP_TOGGLE , _ => unreachable ! () , } } # [doc = "DISABLED"] # [inline (always)] pub fn is_ccact_01_cuact_disabled (& self) -> bool { * self == CCACT_01_CUACT_A :: CCACT_01_CUACT_DISABLED } # [doc = "CCP_HIGH"] # [inline (always)] pub fn is_ccact_01_cuact_ccp_high (& self) -> bool { * self == CCACT_01_CUACT_A :: CCACT_01_CUACT_CCP_HIGH } # [doc = "CCP_LOW"] # [inline (always)] pub fn is_ccact_01_cuact_ccp_low (& self) -> bool { * self == CCACT_01_CUACT_A :: CCACT_01_CUACT_CCP_LOW } # [doc = "CCP_TOGGLE"] # [inline (always)] pub fn is_ccact_01_cuact_ccp_toggle (& self) -> bool { * self == CCACT_01_CUACT_A :: CCACT_01_CUACT_CCP_TOGGLE } } # [doc = "Field `CCACT_01_CUACT` writer - CCP Output Action on Compare (Up) This field describes the resulting action of the signal generator upon detecting a compare event while counting up."] pub type CCACT_01_CUACT_W < 'a , REG , const O : u8 > = crate :: FieldWriterSafe < 'a , REG , 2 , O , CCACT_01_CUACT_A > ; impl < 'a , REG , const O : u8 > CCACT_01_CUACT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "DISABLED"] # [inline (always)] pub fn ccact_01_cuact_disabled (self) -> & 'a mut crate :: W < REG > { self . variant (CCACT_01_CUACT_A :: CCACT_01_CUACT_DISABLED) } # [doc = "CCP_HIGH"] # [inline (always)] pub fn ccact_01_cuact_ccp_high (self) -> & 'a mut crate :: W < REG > { self . variant (CCACT_01_CUACT_A :: CCACT_01_CUACT_CCP_HIGH) } # [doc = "CCP_LOW"] # [inline (always)] pub fn ccact_01_cuact_ccp_low (self) -> & 'a mut crate :: W < REG > { self . variant (CCACT_01_CUACT_A :: CCACT_01_CUACT_CCP_LOW) } # [doc = "CCP_TOGGLE"] # [inline (always)] pub fn ccact_01_cuact_ccp_toggle (self) -> & 'a mut crate :: W < REG > { self . variant (CCACT_01_CUACT_A :: CCACT_01_CUACT_CCP_TOGGLE) } } # [doc = "Field `CCACT_01_CC2DACT` reader - CCP Output Action on CC2D event."] pub type CCACT_01_CC2DACT_R = crate :: FieldReader < CCACT_01_CC2DACT_A > ; # [doc = "CCP Output Action on CC2D event.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum CCACT_01_CC2DACT_A { # [doc = "0: DISABLED"] CCACT_01_CC2DACT_DISABLED = 0 , # [doc = "1: CCP_HIGH"] CCACT_01_CC2DACT_CCP_HIGH = 1 , # [doc = "2: CCP_LOW"] CCACT_01_CC2DACT_CCP_LOW = 2 , # [doc = "3: CCP_TOGGLE"] CCACT_01_CC2DACT_CCP_TOGGLE = 3 , } impl From < CCACT_01_CC2DACT_A > for u8 { # [inline (always)] fn from (variant : CCACT_01_CC2DACT_A) -> Self { variant as _ } } impl crate :: FieldSpec for CCACT_01_CC2DACT_A { type Ux = u8 ; } impl CCACT_01_CC2DACT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CCACT_01_CC2DACT_A { match self . bits { 0 => CCACT_01_CC2DACT_A :: CCACT_01_CC2DACT_DISABLED , 1 => CCACT_01_CC2DACT_A :: CCACT_01_CC2DACT_CCP_HIGH , 2 => CCACT_01_CC2DACT_A :: CCACT_01_CC2DACT_CCP_LOW , 3 => CCACT_01_CC2DACT_A :: CCACT_01_CC2DACT_CCP_TOGGLE , _ => unreachable ! () , } } # [doc = "DISABLED"] # [inline (always)] pub fn is_ccact_01_cc2dact_disabled (& self) -> bool { * self == CCACT_01_CC2DACT_A :: CCACT_01_CC2DACT_DISABLED } # [doc = "CCP_HIGH"] # [inline (always)] pub fn is_ccact_01_cc2dact_ccp_high (& self) -> bool { * self == CCACT_01_CC2DACT_A :: CCACT_01_CC2DACT_CCP_HIGH } # [doc = "CCP_LOW"] # [inline (always)] pub fn is_ccact_01_cc2dact_ccp_low (& self) -> bool { * self == CCACT_01_CC2DACT_A :: CCACT_01_CC2DACT_CCP_LOW } # [doc = "CCP_TOGGLE"] # [inline (always)] pub fn is_ccact_01_cc2dact_ccp_toggle (& self) -> bool { * self == CCACT_01_CC2DACT_A :: CCACT_01_CC2DACT_CCP_TOGGLE } } # [doc = "Field `CCACT_01_CC2DACT` writer - CCP Output Action on CC2D event."] pub type CCACT_01_CC2DACT_W < 'a , REG , const O : u8 > = crate :: FieldWriterSafe < 'a , REG , 2 , O , CCACT_01_CC2DACT_A > ; impl < 'a , REG , const O : u8 > CCACT_01_CC2DACT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "DISABLED"] # [inline (always)] pub fn ccact_01_cc2dact_disabled (self) -> & 'a mut crate :: W < REG > { self . variant (CCACT_01_CC2DACT_A :: CCACT_01_CC2DACT_DISABLED) } # [doc = "CCP_HIGH"] # [inline (always)] pub fn ccact_01_cc2dact_ccp_high (self) -> & 'a mut crate :: W < REG > { self . variant (CCACT_01_CC2DACT_A :: CCACT_01_CC2DACT_CCP_HIGH) } # [doc = "CCP_LOW"] # [inline (always)] pub fn ccact_01_cc2dact_ccp_low (self) -> & 'a mut crate :: W < REG > { self . variant (CCACT_01_CC2DACT_A :: CCACT_01_CC2DACT_CCP_LOW) } # [doc = "CCP_TOGGLE"] # [inline (always)] pub fn ccact_01_cc2dact_ccp_toggle (self) -> & 'a mut crate :: W < REG > { self . variant (CCACT_01_CC2DACT_A :: CCACT_01_CC2DACT_CCP_TOGGLE) } } # [doc = "Field `CCACT_01_CC2UACT` reader - CCP Output Action on CC2U event."] pub type CCACT_01_CC2UACT_R = crate :: FieldReader < CCACT_01_CC2UACT_A > ; # [doc = "CCP Output Action on CC2U event.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum CCACT_01_CC2UACT_A { # [doc = "0: DISABLED"] CCACT_01_CC2UACT_DISABLED = 0 , # [doc = "1: CCP_HIGH"] CCACT_01_CC2UACT_CCP_HIGH = 1 , # [doc = "2: CCP_LOW"] CCACT_01_CC2UACT_CCP_LOW = 2 , # [doc = "3: CCP_TOGGLE"] CCACT_01_CC2UACT_CCP_TOGGLE = 3 , } impl From < CCACT_01_CC2UACT_A > for u8 { # [inline (always)] fn from (variant : CCACT_01_CC2UACT_A) -> Self { variant as _ } } impl crate :: FieldSpec for CCACT_01_CC2UACT_A { type Ux = u8 ; } impl CCACT_01_CC2UACT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CCACT_01_CC2UACT_A { match self . bits { 0 => CCACT_01_CC2UACT_A :: CCACT_01_CC2UACT_DISABLED , 1 => CCACT_01_CC2UACT_A :: CCACT_01_CC2UACT_CCP_HIGH , 2 => CCACT_01_CC2UACT_A :: CCACT_01_CC2UACT_CCP_LOW , 3 => CCACT_01_CC2UACT_A :: CCACT_01_CC2UACT_CCP_TOGGLE , _ => unreachable ! () , } } # [doc = "DISABLED"] # [inline (always)] pub fn is_ccact_01_cc2uact_disabled (& self) -> bool { * self == CCACT_01_CC2UACT_A :: CCACT_01_CC2UACT_DISABLED } # [doc = "CCP_HIGH"] # [inline (always)] pub fn is_ccact_01_cc2uact_ccp_high (& self) -> bool { * self == CCACT_01_CC2UACT_A :: CCACT_01_CC2UACT_CCP_HIGH } # [doc = "CCP_LOW"] # [inline (always)] pub fn is_ccact_01_cc2uact_ccp_low (& self) -> bool { * self == CCACT_01_CC2UACT_A :: CCACT_01_CC2UACT_CCP_LOW } # [doc = "CCP_TOGGLE"] # [inline (always)] pub fn is_ccact_01_cc2uact_ccp_toggle (& self) -> bool { * self == CCACT_01_CC2UACT_A :: CCACT_01_CC2UACT_CCP_TOGGLE } } # [doc = "Field `CCACT_01_CC2UACT` writer - CCP Output Action on CC2U event."] pub type CCACT_01_CC2UACT_W < 'a , REG , const O : u8 > = crate :: FieldWriterSafe < 'a , REG , 2 , O , CCACT_01_CC2UACT_A > ; impl < 'a , REG , const O : u8 > CCACT_01_CC2UACT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "DISABLED"] # [inline (always)] pub fn ccact_01_cc2uact_disabled (self) -> & 'a mut crate :: W < REG > { self . variant (CCACT_01_CC2UACT_A :: CCACT_01_CC2UACT_DISABLED) } # [doc = "CCP_HIGH"] # [inline (always)] pub fn ccact_01_cc2uact_ccp_high (self) -> & 'a mut crate :: W < REG > { self . variant (CCACT_01_CC2UACT_A :: CCACT_01_CC2UACT_CCP_HIGH) } # [doc = "CCP_LOW"] # [inline (always)] pub fn ccact_01_cc2uact_ccp_low (self) -> & 'a mut crate :: W < REG > { self . variant (CCACT_01_CC2UACT_A :: CCACT_01_CC2UACT_CCP_LOW) } # [doc = "CCP_TOGGLE"] # [inline (always)] pub fn ccact_01_cc2uact_ccp_toggle (self) -> & 'a mut crate :: W < REG > { self . variant (CCACT_01_CC2UACT_A :: CCACT_01_CC2UACT_CCP_TOGGLE) } } # [doc = "Field `CCACT_01_SWFRCACT` reader - CCP Output Action on Software Froce Output This field describes the resulting action of software force. This action has a shadow register, which will be updated under specific condition. So that this register cannot take into effect immediately."] pub type CCACT_01_SWFRCACT_R = crate :: FieldReader < CCACT_01_SWFRCACT_A > ; # [doc = "CCP Output Action on Software Froce Output This field describes the resulting action of software force. This action has a shadow register, which will be updated under specific condition. So that this register cannot take into effect immediately.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum CCACT_01_SWFRCACT_A { # [doc = "0: DISABLED"] CCACT_01_SWFRCACT_DISABLED = 0 , # [doc = "1: CCP_HIGH"] CCACT_01_SWFRCACT_CCP_HIGH = 1 , # [doc = "2: CCP_LOW"] CCACT_01_SWFRCACT_CCP_LOW = 2 , } impl From < CCACT_01_SWFRCACT_A > for u8 { # [inline (always)] fn from (variant : CCACT_01_SWFRCACT_A) -> Self { variant as _ } } impl crate :: FieldSpec for CCACT_01_SWFRCACT_A { type Ux = u8 ; } impl CCACT_01_SWFRCACT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < CCACT_01_SWFRCACT_A > { match self . bits { 0 => Some (CCACT_01_SWFRCACT_A :: CCACT_01_SWFRCACT_DISABLED) , 1 => Some (CCACT_01_SWFRCACT_A :: CCACT_01_SWFRCACT_CCP_HIGH) , 2 => Some (CCACT_01_SWFRCACT_A :: CCACT_01_SWFRCACT_CCP_LOW) , _ => None , } } # [doc = "DISABLED"] # [inline (always)] pub fn is_ccact_01_swfrcact_disabled (& self) -> bool { * self == CCACT_01_SWFRCACT_A :: CCACT_01_SWFRCACT_DISABLED } # [doc = "CCP_HIGH"] # [inline (always)] pub fn is_ccact_01_swfrcact_ccp_high (& self) -> bool { * self == CCACT_01_SWFRCACT_A :: CCACT_01_SWFRCACT_CCP_HIGH } # [doc = "CCP_LOW"] # [inline (always)] pub fn is_ccact_01_swfrcact_ccp_low (& self) -> bool { * self == CCACT_01_SWFRCACT_A :: CCACT_01_SWFRCACT_CCP_LOW } } # [doc = "Field `CCACT_01_SWFRCACT` writer - CCP Output Action on Software Froce Output This field describes the resulting action of software force. This action has a shadow register, which will be updated under specific condition. So that this register cannot take into effect immediately."] pub type CCACT_01_SWFRCACT_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 2 , O , CCACT_01_SWFRCACT_A > ; impl < 'a , REG , const O : u8 > CCACT_01_SWFRCACT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "DISABLED"] # [inline (always)] pub fn ccact_01_swfrcact_disabled (self) -> & 'a mut crate :: W < REG > { self . variant (CCACT_01_SWFRCACT_A :: CCACT_01_SWFRCACT_DISABLED) } # [doc = "CCP_HIGH"] # [inline (always)] pub fn ccact_01_swfrcact_ccp_high (self) -> & 'a mut crate :: W < REG > { self . variant (CCACT_01_SWFRCACT_A :: CCACT_01_SWFRCACT_CCP_HIGH) } # [doc = "CCP_LOW"] # [inline (always)] pub fn ccact_01_swfrcact_ccp_low (self) -> & 'a mut crate :: W < REG > { self . variant (CCACT_01_SWFRCACT_A :: CCACT_01_SWFRCACT_CCP_LOW) } } impl R { # [doc = "Bits 0:1 - CCP Output Action on Zero Specifies what changes occur to CCP output as the result of a zero event."] # [inline (always)] pub fn ccact_01_zact (& self) -> CCACT_01_ZACT_R { CCACT_01_ZACT_R :: new ((self . bits & 3) as u8) } # [doc = "Bits 3:4 - CCP Output Action on Load Specifies what changes occur to CCP output as the result of a load event."] # [inline (always)] pub fn ccact_01_lact (& self) -> CCACT_01_LACT_R { CCACT_01_LACT_R :: new (((self . bits >> 3) & 3) as u8) } # [doc = "Bits 6:7 - CCP Output Action on Compare (Down) This field describes the resulting action of the signal generator upon detecting a compare event while counting down."] # [inline (always)] pub fn ccact_01_cdact (& self) -> CCACT_01_CDACT_R { CCACT_01_CDACT_R :: new (((self . bits >> 6) & 3) as u8) } # [doc = "Bits 9:10 - CCP Output Action on Compare (Up) This field describes the resulting action of the signal generator upon detecting a compare event while counting up."] # [inline (always)] pub fn ccact_01_cuact (& self) -> CCACT_01_CUACT_R { CCACT_01_CUACT_R :: new (((self . bits >> 9) & 3) as u8) } # [doc = "Bits 12:13 - CCP Output Action on CC2D event."] # [inline (always)] pub fn ccact_01_cc2dact (& self) -> CCACT_01_CC2DACT_R { CCACT_01_CC2DACT_R :: new (((self . bits >> 12) & 3) as u8) } # [doc = "Bits 15:16 - CCP Output Action on CC2U event."] # [inline (always)] pub fn ccact_01_cc2uact (& self) -> CCACT_01_CC2UACT_R { CCACT_01_CC2UACT_R :: new (((self . bits >> 15) & 3) as u8) } # [doc = "Bits 28:29 - CCP Output Action on Software Froce Output This field describes the resulting action of software force. This action has a shadow register, which will be updated under specific condition. So that this register cannot take into effect immediately."] # [inline (always)] pub fn ccact_01_swfrcact (& self) -> CCACT_01_SWFRCACT_R { CCACT_01_SWFRCACT_R :: new (((self . bits >> 28) & 3) as u8) } } impl W { # [doc = "Bits 0:1 - CCP Output Action on Zero Specifies what changes occur to CCP output as the result of a zero event."] # [inline (always)] # [must_use] pub fn ccact_01_zact (& mut self) -> CCACT_01_ZACT_W < CCACT_01_SPEC , 0 > { CCACT_01_ZACT_W :: new (self) } # [doc = "Bits 3:4 - CCP Output Action on Load Specifies what changes occur to CCP output as the result of a load event."] # [inline (always)] # [must_use] pub fn ccact_01_lact (& mut self) -> CCACT_01_LACT_W < CCACT_01_SPEC , 3 > { CCACT_01_LACT_W :: new (self) } # [doc = "Bits 6:7 - CCP Output Action on Compare (Down) This field describes the resulting action of the signal generator upon detecting a compare event while counting down."] # [inline (always)] # [must_use] pub fn ccact_01_cdact (& mut self) -> CCACT_01_CDACT_W <'_, CCACT_01_SPEC , 6 > { CCACT_01_CDACT_W :: new (self) } # [doc = "Bits 9:10 - CCP Output Action on Compare (Up) This field describes the resulting action of the signal generator upon detecting a compare event while counting up."] # [inline (always)] # [must_use] pub fn ccact_01_cuact (& mut self) -> CCACT_01_CUACT_W < CCACT_01_SPEC , 9 > { CCACT_01_CUACT_W :: new (self) } # [doc = "Bits 12:13 - CCP Output Action on CC2D event."] # [inline (always)] # [must_use] pub fn ccact_01_cc2dact (& mut self) -> CCACT_01_CC2DACT_W < CCACT_01_SPEC , 12 > { CCACT_01_CC2DACT_W :: new (self) } # [doc = "Bits 15:16 - CCP Output Action on CC2U event."] # [inline (always)] # [must_use] pub fn ccact_01_cc2uact (& mut self) -> CCACT_01_CC2UACT_W < CCACT_01_SPEC , 15 > { CCACT_01_CC2UACT_W :: new (self) } # [doc = "Bits 28:29 - CCP Output Action on Software Froce Output This field describes the resulting action of software force. This action has a shadow register, which will be updated under specific condition. So that this register cannot take into effect immediately."] # [inline (always)] # [must_use] pub fn ccact_01_swfrcact (& mut self) -> CCACT_01_SWFRCACT_W < CCACT_01_SPEC , 28 > { CCACT_01_SWFRCACT_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Capture or Compare Action Registers\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ccact_01::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ccact_01::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CCACT_01_SPEC ; impl crate :: RegisterSpec for CCACT_01_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`ccact_01::R`](R) reader structure"] impl crate :: Readable for CCACT_01_SPEC { } # [doc = "`write(|w| ..)` method takes [`ccact_01::W`](W) writer structure"] impl crate :: Writable for CCACT_01_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets CCACT_01[%s] [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/sysctl/sysosccfg.rs:1:17272 [INFO] [stdout] | [INFO] [stdout] 1 | ...pub fn sysosccfg_freq (& mut self) -> SYSOSCCFG_FREQ_W < SYSOSCCFG_SPEC , 0 > { SYSOSCCFG_FREQ_W :: new (self) } # [doc = "Bit 8 - USE... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `SYSOSCCFG` reader"] pub type R = crate :: R < SYSOSCCFG_SPEC > ; # [doc = "Register `SYSOSCCFG` writer"] pub type W = crate :: W < SYSOSCCFG_SPEC > ; # [doc = "Field `SYSOSCCFG_FREQ` reader - Target operating frequency for the system oscillator (SYSOSC)"] pub type SYSOSCCFG_FREQ_R = crate :: FieldReader < SYSOSCCFG_FREQ_A > ; # [doc = "Target operating frequency for the system oscillator (SYSOSC)\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum SYSOSCCFG_FREQ_A { # [doc = "0: SYSOSCBASE"] SYSOSCCFG_FREQ_SYSOSCBASE = 0 , # [doc = "1: SYSOSC4M"] SYSOSCCFG_FREQ_SYSOSC4M = 1 , # [doc = "2: SYSOSCUSER"] SYSOSCCFG_FREQ_SYSOSCUSER = 2 , # [doc = "3: SYSOSCTURBO"] SYSOSCCFG_FREQ_SYSOSCTURBO = 3 , } impl From < SYSOSCCFG_FREQ_A > for u8 { # [inline (always)] fn from (variant : SYSOSCCFG_FREQ_A) -> Self { variant as _ } } impl crate :: FieldSpec for SYSOSCCFG_FREQ_A { type Ux = u8 ; } impl SYSOSCCFG_FREQ_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> SYSOSCCFG_FREQ_A { match self . bits { 0 => SYSOSCCFG_FREQ_A :: SYSOSCCFG_FREQ_SYSOSCBASE , 1 => SYSOSCCFG_FREQ_A :: SYSOSCCFG_FREQ_SYSOSC4M , 2 => SYSOSCCFG_FREQ_A :: SYSOSCCFG_FREQ_SYSOSCUSER , 3 => SYSOSCCFG_FREQ_A :: SYSOSCCFG_FREQ_SYSOSCTURBO , _ => unreachable ! () , } } # [doc = "SYSOSCBASE"] # [inline (always)] pub fn is_sysosccfg_freq_sysoscbase (& self) -> bool { * self == SYSOSCCFG_FREQ_A :: SYSOSCCFG_FREQ_SYSOSCBASE } # [doc = "SYSOSC4M"] # [inline (always)] pub fn is_sysosccfg_freq_sysosc4m (& self) -> bool { * self == SYSOSCCFG_FREQ_A :: SYSOSCCFG_FREQ_SYSOSC4M } # [doc = "SYSOSCUSER"] # [inline (always)] pub fn is_sysosccfg_freq_sysoscuser (& self) -> bool { * self == SYSOSCCFG_FREQ_A :: SYSOSCCFG_FREQ_SYSOSCUSER } # [doc = "SYSOSCTURBO"] # [inline (always)] pub fn is_sysosccfg_freq_sysoscturbo (& self) -> bool { * self == SYSOSCCFG_FREQ_A :: SYSOSCCFG_FREQ_SYSOSCTURBO } } # [doc = "Field `SYSOSCCFG_FREQ` writer - Target operating frequency for the system oscillator (SYSOSC)"] pub type SYSOSCCFG_FREQ_W < 'a , REG , const O : u8 > = crate :: FieldWriterSafe < 'a , REG , 2 , O , SYSOSCCFG_FREQ_A > ; impl < 'a , REG , const O : u8 > SYSOSCCFG_FREQ_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "SYSOSCBASE"] # [inline (always)] pub fn sysosccfg_freq_sysoscbase (self) -> & 'a mut crate :: W < REG > { self . variant (SYSOSCCFG_FREQ_A :: SYSOSCCFG_FREQ_SYSOSCBASE) } # [doc = "SYSOSC4M"] # [inline (always)] pub fn sysosccfg_freq_sysosc4m (self) -> & 'a mut crate :: W < REG > { self . variant (SYSOSCCFG_FREQ_A :: SYSOSCCFG_FREQ_SYSOSC4M) } # [doc = "SYSOSCUSER"] # [inline (always)] pub fn sysosccfg_freq_sysoscuser (self) -> & 'a mut crate :: W < REG > { self . variant (SYSOSCCFG_FREQ_A :: SYSOSCCFG_FREQ_SYSOSCUSER) } # [doc = "SYSOSCTURBO"] # [inline (always)] pub fn sysosccfg_freq_sysoscturbo (self) -> & 'a mut crate :: W < REG > { self . variant (SYSOSCCFG_FREQ_A :: SYSOSCCFG_FREQ_SYSOSCTURBO) } } # [doc = "Field `SYSOSCCFG_USE4MHZSTOP` reader - USE4MHZSTOP sets the SYSOSC stop mode frequency policy. When entering STOP mode, the SYSOSC frequency may be automatically switched to 4MHz to reduce SYSOSC power consumption."] pub type SYSOSCCFG_USE4MHZSTOP_R = crate :: BitReader < SYSOSCCFG_USE4MHZSTOP_A > ; # [doc = "USE4MHZSTOP sets the SYSOSC stop mode frequency policy. When entering STOP mode, the SYSOSC frequency may be automatically switched to 4MHz to reduce SYSOSC power consumption.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum SYSOSCCFG_USE4MHZSTOP_A { # [doc = "0: DISABLE"] SYSOSCCFG_USE4MHZSTOP_DISABLE = 0 , # [doc = "1: ENABLE"] SYSOSCCFG_USE4MHZSTOP_ENABLE = 1 , } impl From < SYSOSCCFG_USE4MHZSTOP_A > for bool { # [inline (always)] fn from (variant : SYSOSCCFG_USE4MHZSTOP_A) -> Self { variant as u8 != 0 } } impl SYSOSCCFG_USE4MHZSTOP_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> SYSOSCCFG_USE4MHZSTOP_A { match self . bits { false => SYSOSCCFG_USE4MHZSTOP_A :: SYSOSCCFG_USE4MHZSTOP_DISABLE , true => SYSOSCCFG_USE4MHZSTOP_A :: SYSOSCCFG_USE4MHZSTOP_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_sysosccfg_use4mhzstop_disable (& self) -> bool { * self == SYSOSCCFG_USE4MHZSTOP_A :: SYSOSCCFG_USE4MHZSTOP_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_sysosccfg_use4mhzstop_enable (& self) -> bool { * self == SYSOSCCFG_USE4MHZSTOP_A :: SYSOSCCFG_USE4MHZSTOP_ENABLE } } # [doc = "Field `SYSOSCCFG_USE4MHZSTOP` writer - USE4MHZSTOP sets the SYSOSC stop mode frequency policy. When entering STOP mode, the SYSOSC frequency may be automatically switched to 4MHz to reduce SYSOSC power consumption."] pub type SYSOSCCFG_USE4MHZSTOP_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , SYSOSCCFG_USE4MHZSTOP_A > ; impl < 'a , REG , const O : u8 > SYSOSCCFG_USE4MHZSTOP_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn sysosccfg_use4mhzstop_disable (self) -> & 'a mut crate :: W < REG > { self . variant (SYSOSCCFG_USE4MHZSTOP_A :: SYSOSCCFG_USE4MHZSTOP_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn sysosccfg_use4mhzstop_enable (self) -> & 'a mut crate :: W < REG > { self . variant (SYSOSCCFG_USE4MHZSTOP_A :: SYSOSCCFG_USE4MHZSTOP_ENABLE) } } # [doc = "Field `SYSOSCCFG_DISABLESTOP` reader - DISABLESTOP sets the SYSOSC stop mode enable/disable policy. When operating in STOP mode, the SYSOSC may be automatically disabled. When set, ULPCLK will run from LFCLK in STOP mode and SYSOSC will be disabled to reduce power consumption."] pub type SYSOSCCFG_DISABLESTOP_R = crate :: BitReader < SYSOSCCFG_DISABLESTOP_A > ; # [doc = "DISABLESTOP sets the SYSOSC stop mode enable/disable policy. When operating in STOP mode, the SYSOSC may be automatically disabled. When set, ULPCLK will run from LFCLK in STOP mode and SYSOSC will be disabled to reduce power consumption.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum SYSOSCCFG_DISABLESTOP_A { # [doc = "0: DISABLE"] SYSOSCCFG_DISABLESTOP_DISABLE = 0 , # [doc = "1: ENABLE"] SYSOSCCFG_DISABLESTOP_ENABLE = 1 , } impl From < SYSOSCCFG_DISABLESTOP_A > for bool { # [inline (always)] fn from (variant : SYSOSCCFG_DISABLESTOP_A) -> Self { variant as u8 != 0 } } impl SYSOSCCFG_DISABLESTOP_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> SYSOSCCFG_DISABLESTOP_A { match self . bits { false => SYSOSCCFG_DISABLESTOP_A :: SYSOSCCFG_DISABLESTOP_DISABLE , true => SYSOSCCFG_DISABLESTOP_A :: SYSOSCCFG_DISABLESTOP_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_sysosccfg_disablestop_disable (& self) -> bool { * self == SYSOSCCFG_DISABLESTOP_A :: SYSOSCCFG_DISABLESTOP_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_sysosccfg_disablestop_enable (& self) -> bool { * self == SYSOSCCFG_DISABLESTOP_A :: SYSOSCCFG_DISABLESTOP_ENABLE } } # [doc = "Field `SYSOSCCFG_DISABLESTOP` writer - DISABLESTOP sets the SYSOSC stop mode enable/disable policy. When operating in STOP mode, the SYSOSC may be automatically disabled. When set, ULPCLK will run from LFCLK in STOP mode and SYSOSC will be disabled to reduce power consumption."] pub type SYSOSCCFG_DISABLESTOP_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , SYSOSCCFG_DISABLESTOP_A > ; impl < 'a , REG , const O : u8 > SYSOSCCFG_DISABLESTOP_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn sysosccfg_disablestop_disable (self) -> & 'a mut crate :: W < REG > { self . variant (SYSOSCCFG_DISABLESTOP_A :: SYSOSCCFG_DISABLESTOP_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn sysosccfg_disablestop_enable (self) -> & 'a mut crate :: W < REG > { self . variant (SYSOSCCFG_DISABLESTOP_A :: SYSOSCCFG_DISABLESTOP_ENABLE) } } # [doc = "Field `SYSOSCCFG_DISABLE` reader - DISABLE sets the SYSOSC enable/disable policy. SYSOSC may be powered off in RUN, SLEEP, and STOP modes to reduce power consumption. When SYSOSC is disabled, MCLK and ULPCLK are sourced from LFCLK."] pub type SYSOSCCFG_DISABLE_R = crate :: BitReader < SYSOSCCFG_DISABLE_A > ; # [doc = "DISABLE sets the SYSOSC enable/disable policy. SYSOSC may be powered off in RUN, SLEEP, and STOP modes to reduce power consumption. When SYSOSC is disabled, MCLK and ULPCLK are sourced from LFCLK.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum SYSOSCCFG_DISABLE_A { # [doc = "0: DISABLE"] SYSOSCCFG_DISABLE_DISABLE = 0 , # [doc = "1: ENABLE"] SYSOSCCFG_DISABLE_ENABLE = 1 , } impl From < SYSOSCCFG_DISABLE_A > for bool { # [inline (always)] fn from (variant : SYSOSCCFG_DISABLE_A) -> Self { variant as u8 != 0 } } impl SYSOSCCFG_DISABLE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> SYSOSCCFG_DISABLE_A { match self . bits { false => SYSOSCCFG_DISABLE_A :: SYSOSCCFG_DISABLE_DISABLE , true => SYSOSCCFG_DISABLE_A :: SYSOSCCFG_DISABLE_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_sysosccfg_disable_disable (& self) -> bool { * self == SYSOSCCFG_DISABLE_A :: SYSOSCCFG_DISABLE_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_sysosccfg_disable_enable (& self) -> bool { * self == SYSOSCCFG_DISABLE_A :: SYSOSCCFG_DISABLE_ENABLE } } # [doc = "Field `SYSOSCCFG_DISABLE` writer - DISABLE sets the SYSOSC enable/disable policy. SYSOSC may be powered off in RUN, SLEEP, and STOP modes to reduce power consumption. When SYSOSC is disabled, MCLK and ULPCLK are sourced from LFCLK."] pub type SYSOSCCFG_DISABLE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , SYSOSCCFG_DISABLE_A > ; impl < 'a , REG , const O : u8 > SYSOSCCFG_DISABLE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn sysosccfg_disable_disable (self) -> & 'a mut crate :: W < REG > { self . variant (SYSOSCCFG_DISABLE_A :: SYSOSCCFG_DISABLE_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn sysosccfg_disable_enable (self) -> & 'a mut crate :: W < REG > { self . variant (SYSOSCCFG_DISABLE_A :: SYSOSCCFG_DISABLE_ENABLE) } } # [doc = "Field `SYSOSCCFG_BLOCKASYNCALL` reader - BLOCKASYNCALL may be used to mask block all asynchronous fast clock requests, preventing hardware from dynamically changing the active clock configuration when operating in a given mode."] pub type SYSOSCCFG_BLOCKASYNCALL_R = crate :: BitReader < SYSOSCCFG_BLOCKASYNCALL_A > ; # [doc = "BLOCKASYNCALL may be used to mask block all asynchronous fast clock requests, preventing hardware from dynamically changing the active clock configuration when operating in a given mode.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum SYSOSCCFG_BLOCKASYNCALL_A { # [doc = "0: DISABLE"] SYSOSCCFG_BLOCKASYNCALL_DISABLE = 0 , # [doc = "1: ENABLE"] SYSOSCCFG_BLOCKASYNCALL_ENABLE = 1 , } impl From < SYSOSCCFG_BLOCKASYNCALL_A > for bool { # [inline (always)] fn from (variant : SYSOSCCFG_BLOCKASYNCALL_A) -> Self { variant as u8 != 0 } } impl SYSOSCCFG_BLOCKASYNCALL_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> SYSOSCCFG_BLOCKASYNCALL_A { match self . bits { false => SYSOSCCFG_BLOCKASYNCALL_A :: SYSOSCCFG_BLOCKASYNCALL_DISABLE , true => SYSOSCCFG_BLOCKASYNCALL_A :: SYSOSCCFG_BLOCKASYNCALL_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_sysosccfg_blockasyncall_disable (& self) -> bool { * self == SYSOSCCFG_BLOCKASYNCALL_A :: SYSOSCCFG_BLOCKASYNCALL_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_sysosccfg_blockasyncall_enable (& self) -> bool { * self == SYSOSCCFG_BLOCKASYNCALL_A :: SYSOSCCFG_BLOCKASYNCALL_ENABLE } } # [doc = "Field `SYSOSCCFG_BLOCKASYNCALL` writer - BLOCKASYNCALL may be used to mask block all asynchronous fast clock requests, preventing hardware from dynamically changing the active clock configuration when operating in a given mode."] pub type SYSOSCCFG_BLOCKASYNCALL_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , SYSOSCCFG_BLOCKASYNCALL_A > ; impl < 'a , REG , const O : u8 > SYSOSCCFG_BLOCKASYNCALL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn sysosccfg_blockasyncall_disable (self) -> & 'a mut crate :: W < REG > { self . variant (SYSOSCCFG_BLOCKASYNCALL_A :: SYSOSCCFG_BLOCKASYNCALL_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn sysosccfg_blockasyncall_enable (self) -> & 'a mut crate :: W < REG > { self . variant (SYSOSCCFG_BLOCKASYNCALL_A :: SYSOSCCFG_BLOCKASYNCALL_ENABLE) } } # [doc = "Field `SYSOSCCFG_FASTCPUEVENT` reader - FASTCPUEVENT may be used to assert a fast clock request when an interrupt is asserted to the CPU, reducing interrupt latency."] pub type SYSOSCCFG_FASTCPUEVENT_R = crate :: BitReader < SYSOSCCFG_FASTCPUEVENT_A > ; # [doc = "FASTCPUEVENT may be used to assert a fast clock request when an interrupt is asserted to the CPU, reducing interrupt latency.\n\nValue on reset: 1"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum SYSOSCCFG_FASTCPUEVENT_A { # [doc = "0: DISABLE"] SYSOSCCFG_FASTCPUEVENT_DISABLE = 0 , # [doc = "1: ENABLE"] SYSOSCCFG_FASTCPUEVENT_ENABLE = 1 , } impl From < SYSOSCCFG_FASTCPUEVENT_A > for bool { # [inline (always)] fn from (variant : SYSOSCCFG_FASTCPUEVENT_A) -> Self { variant as u8 != 0 } } impl SYSOSCCFG_FASTCPUEVENT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> SYSOSCCFG_FASTCPUEVENT_A { match self . bits { false => SYSOSCCFG_FASTCPUEVENT_A :: SYSOSCCFG_FASTCPUEVENT_DISABLE , true => SYSOSCCFG_FASTCPUEVENT_A :: SYSOSCCFG_FASTCPUEVENT_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_sysosccfg_fastcpuevent_disable (& self) -> bool { * self == SYSOSCCFG_FASTCPUEVENT_A :: SYSOSCCFG_FASTCPUEVENT_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_sysosccfg_fastcpuevent_enable (& self) -> bool { * self == SYSOSCCFG_FASTCPUEVENT_A :: SYSOSCCFG_FASTCPUEVENT_ENABLE } } # [doc = "Field `SYSOSCCFG_FASTCPUEVENT` writer - FASTCPUEVENT may be used to assert a fast clock request when an interrupt is asserted to the CPU, reducing interrupt latency."] pub type SYSOSCCFG_FASTCPUEVENT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , SYSOSCCFG_FASTCPUEVENT_A > ; impl < 'a , REG , const O : u8 > SYSOSCCFG_FASTCPUEVENT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn sysosccfg_fastcpuevent_disable (self) -> & 'a mut crate :: W < REG > { self . variant (SYSOSCCFG_FASTCPUEVENT_A :: SYSOSCCFG_FASTCPUEVENT_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn sysosccfg_fastcpuevent_enable (self) -> & 'a mut crate :: W < REG > { self . variant (SYSOSCCFG_FASTCPUEVENT_A :: SYSOSCCFG_FASTCPUEVENT_ENABLE) } } impl R { # [doc = "Bits 0:1 - Target operating frequency for the system oscillator (SYSOSC)"] # [inline (always)] pub fn sysosccfg_freq (& self) -> SYSOSCCFG_FREQ_R { SYSOSCCFG_FREQ_R :: new ((self . bits & 3) as u8) } # [doc = "Bit 8 - USE4MHZSTOP sets the SYSOSC stop mode frequency policy. When entering STOP mode, the SYSOSC frequency may be automatically switched to 4MHz to reduce SYSOSC power consumption."] # [inline (always)] pub fn sysosccfg_use4mhzstop (& self) -> SYSOSCCFG_USE4MHZSTOP_R { SYSOSCCFG_USE4MHZSTOP_R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - DISABLESTOP sets the SYSOSC stop mode enable/disable policy. When operating in STOP mode, the SYSOSC may be automatically disabled. When set, ULPCLK will run from LFCLK in STOP mode and SYSOSC will be disabled to reduce power consumption."] # [inline (always)] pub fn sysosccfg_disablestop (& self) -> SYSOSCCFG_DISABLESTOP_R { SYSOSCCFG_DISABLESTOP_R :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - DISABLE sets the SYSOSC enable/disable policy. SYSOSC may be powered off in RUN, SLEEP, and STOP modes to reduce power consumption. When SYSOSC is disabled, MCLK and ULPCLK are sourced from LFCLK."] # [inline (always)] pub fn sysosccfg_disable (& self) -> SYSOSCCFG_DISABLE_R { SYSOSCCFG_DISABLE_R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 16 - BLOCKASYNCALL may be used to mask block all asynchronous fast clock requests, preventing hardware from dynamically changing the active clock configuration when operating in a given mode."] # [inline (always)] pub fn sysosccfg_blockasyncall (& self) -> SYSOSCCFG_BLOCKASYNCALL_R { SYSOSCCFG_BLOCKASYNCALL_R :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - FASTCPUEVENT may be used to assert a fast clock request when an interrupt is asserted to the CPU, reducing interrupt latency."] # [inline (always)] pub fn sysosccfg_fastcpuevent (& self) -> SYSOSCCFG_FASTCPUEVENT_R { SYSOSCCFG_FASTCPUEVENT_R :: new (((self . bits >> 17) & 1) != 0) } } impl W { # [doc = "Bits 0:1 - Target operating frequency for the system oscillator (SYSOSC)"] # [inline (always)] # [must_use] pub fn sysosccfg_freq (& mut self) -> SYSOSCCFG_FREQ_W <'_, SYSOSCCFG_SPEC , 0 > { SYSOSCCFG_FREQ_W :: new (self) } # [doc = "Bit 8 - USE4MHZSTOP sets the SYSOSC stop mode frequency policy. When entering STOP mode, the SYSOSC frequency may be automatically switched to 4MHz to reduce SYSOSC power consumption."] # [inline (always)] # [must_use] pub fn sysosccfg_use4mhzstop (& mut self) -> SYSOSCCFG_USE4MHZSTOP_W < SYSOSCCFG_SPEC , 8 > { SYSOSCCFG_USE4MHZSTOP_W :: new (self) } # [doc = "Bit 9 - DISABLESTOP sets the SYSOSC stop mode enable/disable policy. When operating in STOP mode, the SYSOSC may be automatically disabled. When set, ULPCLK will run from LFCLK in STOP mode and SYSOSC will be disabled to reduce power consumption."] # [inline (always)] # [must_use] pub fn sysosccfg_disablestop (& mut self) -> SYSOSCCFG_DISABLESTOP_W < SYSOSCCFG_SPEC , 9 > { SYSOSCCFG_DISABLESTOP_W :: new (self) } # [doc = "Bit 10 - DISABLE sets the SYSOSC enable/disable policy. SYSOSC may be powered off in RUN, SLEEP, and STOP modes to reduce power consumption. When SYSOSC is disabled, MCLK and ULPCLK are sourced from LFCLK."] # [inline (always)] # [must_use] pub fn sysosccfg_disable (& mut self) -> SYSOSCCFG_DISABLE_W < SYSOSCCFG_SPEC , 10 > { SYSOSCCFG_DISABLE_W :: new (self) } # [doc = "Bit 16 - BLOCKASYNCALL may be used to mask block all asynchronous fast clock requests, preventing hardware from dynamically changing the active clock configuration when operating in a given mode."] # [inline (always)] # [must_use] pub fn sysosccfg_blockasyncall (& mut self) -> SYSOSCCFG_BLOCKASYNCALL_W < SYSOSCCFG_SPEC , 16 > { SYSOSCCFG_BLOCKASYNCALL_W :: new (self) } # [doc = "Bit 17 - FASTCPUEVENT may be used to assert a fast clock request when an interrupt is asserted to the CPU, reducing interrupt latency."] # [inline (always)] # [must_use] pub fn sysosccfg_fastcpuevent (& mut self) -> SYSOSCCFG_FASTCPUEVENT_W < SYSOSCCFG_SPEC , 17 > { SYSOSCCFG_FASTCPUEVENT_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "SYSOSC configuration\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sysosccfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sysosccfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct SYSOSCCFG_SPEC ; impl crate :: RegisterSpec for SYSOSCCFG_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`sysosccfg::R`](R) reader structure"] impl crate :: Readable for SYSOSCCFG_SPEC { } # [doc = "`write(|w| ..)` method takes [`sysosccfg::W`](W) writer structure"] impl crate :: Writable for SYSOSCCFG_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets SYSOSCCFG to value 0x0002_0000"] impl crate :: Resettable for SYSOSCCFG_SPEC { const RESET_VALUE : Self :: Ux = 0x0002_0000 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/i2c0/int_event0_iset.rs:1:39924 [INFO] [stdout] | [INFO] [stdout] 1 | ...t0_iset_mstart (& mut self) -> INT_EVENT0_ISET_MSTART_W < INT_EVENT0_ISET_SPEC , 8 > { INT_EVENT0_ISET_MSTART_W :: new (self) } # [doc... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `INT_EVENT0_ISET` writer"] pub type W = crate :: W < INT_EVENT0_ISET_SPEC > ; # [doc = "Master Receive Data Interrupt Signals that a byte has been received\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_MRXDONE_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_MRXDONE_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_MRXDONE_SET = 1 , } impl From < INT_EVENT0_ISET_MRXDONE_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_MRXDONE_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_MRXDONE` writer - Master Receive Data Interrupt Signals that a byte has been received"] pub type INT_EVENT0_ISET_MRXDONE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_MRXDONE_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_MRXDONE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_mrxdone_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MRXDONE_AW :: INT_EVENT0_ISET_MRXDONE_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_mrxdone_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MRXDONE_AW :: INT_EVENT0_ISET_MRXDONE_SET) } } # [doc = "Master Transmit Transaction completed Interrupt\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_MTXDONE_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_MTXDONE_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_MTXDONE_SET = 1 , } impl From < INT_EVENT0_ISET_MTXDONE_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_MTXDONE_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_MTXDONE` writer - Master Transmit Transaction completed Interrupt"] pub type INT_EVENT0_ISET_MTXDONE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_MTXDONE_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_MTXDONE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_mtxdone_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MTXDONE_AW :: INT_EVENT0_ISET_MTXDONE_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_mtxdone_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MTXDONE_AW :: INT_EVENT0_ISET_MTXDONE_SET) } } # [doc = "Master Receive FIFO Trigger Trigger when RX FIFO contains &gt;= defined bytes\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_MRXFIFOTRG_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_MRXFIFOTRG_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_MRXFIFOTRG_SET = 1 , } impl From < INT_EVENT0_ISET_MRXFIFOTRG_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_MRXFIFOTRG_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_MRXFIFOTRG` writer - Master Receive FIFO Trigger Trigger when RX FIFO contains &gt;= defined bytes"] pub type INT_EVENT0_ISET_MRXFIFOTRG_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_MRXFIFOTRG_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_MRXFIFOTRG_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_mrxfifotrg_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MRXFIFOTRG_AW :: INT_EVENT0_ISET_MRXFIFOTRG_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_mrxfifotrg_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MRXFIFOTRG_AW :: INT_EVENT0_ISET_MRXFIFOTRG_SET) } } # [doc = "Master Transmit FIFO Trigger Trigger when Transmit FIFO contains &lt;= defined bytes\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_MTXFIFOTRG_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_MTXFIFOTRG_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_MTXFIFOTRG_SET = 1 , } impl From < INT_EVENT0_ISET_MTXFIFOTRG_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_MTXFIFOTRG_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_MTXFIFOTRG` writer - Master Transmit FIFO Trigger Trigger when Transmit FIFO contains &lt;= defined bytes"] pub type INT_EVENT0_ISET_MTXFIFOTRG_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_MTXFIFOTRG_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_MTXFIFOTRG_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_mtxfifotrg_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MTXFIFOTRG_AW :: INT_EVENT0_ISET_MTXFIFOTRG_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_mtxfifotrg_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MTXFIFOTRG_AW :: INT_EVENT0_ISET_MTXFIFOTRG_SET) } } # [doc = "RXFIFO full event.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_MRXFIFOFULL_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_MRXFIFOFULL_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_MRXFIFOFULL_SET = 1 , } impl From < INT_EVENT0_ISET_MRXFIFOFULL_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_MRXFIFOFULL_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_MRXFIFOFULL` writer - RXFIFO full event."] pub type INT_EVENT0_ISET_MRXFIFOFULL_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_MRXFIFOFULL_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_MRXFIFOFULL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_mrxfifofull_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MRXFIFOFULL_AW :: INT_EVENT0_ISET_MRXFIFOFULL_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_mrxfifofull_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MRXFIFOFULL_AW :: INT_EVENT0_ISET_MRXFIFOFULL_SET) } } # [doc = "Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_MTXEMPTY_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_MTXEMPTY_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_MTXEMPTY_SET = 1 , } impl From < INT_EVENT0_ISET_MTXEMPTY_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_MTXEMPTY_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_MTXEMPTY` writer - Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode."] pub type INT_EVENT0_ISET_MTXEMPTY_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_MTXEMPTY_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_MTXEMPTY_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_mtxempty_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MTXEMPTY_AW :: INT_EVENT0_ISET_MTXEMPTY_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_mtxempty_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MTXEMPTY_AW :: INT_EVENT0_ISET_MTXEMPTY_SET) } } # [doc = "Address/Data NACK Interrupt\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_MNACK_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_MNACK_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_MNACK_SET = 1 , } impl From < INT_EVENT0_ISET_MNACK_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_MNACK_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_MNACK` writer - Address/Data NACK Interrupt"] pub type INT_EVENT0_ISET_MNACK_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_MNACK_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_MNACK_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_mnack_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MNACK_AW :: INT_EVENT0_ISET_MNACK_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_mnack_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MNACK_AW :: INT_EVENT0_ISET_MNACK_SET) } } # [doc = "START Detection Interrupt\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_MSTART_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_MSTART_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_MSTART_SET = 1 , } impl From < INT_EVENT0_ISET_MSTART_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_MSTART_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_MSTART` writer - START Detection Interrupt"] pub type INT_EVENT0_ISET_MSTART_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_MSTART_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_MSTART_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_mstart_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MSTART_AW :: INT_EVENT0_ISET_MSTART_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_mstart_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MSTART_AW :: INT_EVENT0_ISET_MSTART_SET) } } # [doc = "STOP Detection Interrupt\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_MSTOP_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_MSTOP_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_MSTOP_SET = 1 , } impl From < INT_EVENT0_ISET_MSTOP_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_MSTOP_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_MSTOP` writer - STOP Detection Interrupt"] pub type INT_EVENT0_ISET_MSTOP_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_MSTOP_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_MSTOP_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_mstop_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MSTOP_AW :: INT_EVENT0_ISET_MSTOP_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_mstop_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MSTOP_AW :: INT_EVENT0_ISET_MSTOP_SET) } } # [doc = "Arbitration Lost Interrupt\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_MARBLOST_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_MARBLOST_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_MARBLOST_SET = 1 , } impl From < INT_EVENT0_ISET_MARBLOST_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_MARBLOST_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_MARBLOST` writer - Arbitration Lost Interrupt"] pub type INT_EVENT0_ISET_MARBLOST_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_MARBLOST_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_MARBLOST_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_marblost_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MARBLOST_AW :: INT_EVENT0_ISET_MARBLOST_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_marblost_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MARBLOST_AW :: INT_EVENT0_ISET_MARBLOST_SET) } } # [doc = "DMA Done 1 on Event Channel 2\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_MDMA_DONE1_2_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_MDMA_DONE1_2_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_MDMA_DONE1_2_SET = 1 , } impl From < INT_EVENT0_ISET_MDMA_DONE1_2_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_MDMA_DONE1_2_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_MDMA_DONE1_2` writer - DMA Done 1 on Event Channel 2"] pub type INT_EVENT0_ISET_MDMA_DONE1_2_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_MDMA_DONE1_2_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_MDMA_DONE1_2_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_mdma_done1_2_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MDMA_DONE1_2_AW :: INT_EVENT0_ISET_MDMA_DONE1_2_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_mdma_done1_2_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MDMA_DONE1_2_AW :: INT_EVENT0_ISET_MDMA_DONE1_2_SET) } } # [doc = "DMA Done 1 on Event Channel 3\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_MDMA_DONE1_3_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_MDMA_DONE1_3_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_MDMA_DONE1_3_SET = 1 , } impl From < INT_EVENT0_ISET_MDMA_DONE1_3_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_MDMA_DONE1_3_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_MDMA_DONE1_3` writer - DMA Done 1 on Event Channel 3"] pub type INT_EVENT0_ISET_MDMA_DONE1_3_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_MDMA_DONE1_3_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_MDMA_DONE1_3_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_mdma_done1_3_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MDMA_DONE1_3_AW :: INT_EVENT0_ISET_MDMA_DONE1_3_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_mdma_done1_3_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MDMA_DONE1_3_AW :: INT_EVENT0_ISET_MDMA_DONE1_3_SET) } } # [doc = "Master RX Pec Error Interrupt\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_MPEC_RX_ERR_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_MPEC_RX_ERR_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_MPEC_RX_ERR_SET = 1 , } impl From < INT_EVENT0_ISET_MPEC_RX_ERR_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_MPEC_RX_ERR_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_MPEC_RX_ERR` writer - Master RX Pec Error Interrupt"] pub type INT_EVENT0_ISET_MPEC_RX_ERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_MPEC_RX_ERR_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_MPEC_RX_ERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_mpec_rx_err_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MPEC_RX_ERR_AW :: INT_EVENT0_ISET_MPEC_RX_ERR_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_mpec_rx_err_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MPEC_RX_ERR_AW :: INT_EVENT0_ISET_MPEC_RX_ERR_SET) } } # [doc = "Timeout A interrupt\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_TIMEOUTA_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_TIMEOUTA_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_TIMEOUTA_SET = 1 , } impl From < INT_EVENT0_ISET_TIMEOUTA_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_TIMEOUTA_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_TIMEOUTA` writer - Timeout A interrupt"] pub type INT_EVENT0_ISET_TIMEOUTA_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_TIMEOUTA_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_TIMEOUTA_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_timeouta_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_TIMEOUTA_AW :: INT_EVENT0_ISET_TIMEOUTA_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_timeouta_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_TIMEOUTA_AW :: INT_EVENT0_ISET_TIMEOUTA_SET) } } # [doc = "Timeout B Interrupt\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_TIMEOUTB_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_TIMEOUTB_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_TIMEOUTB_SET = 1 , } impl From < INT_EVENT0_ISET_TIMEOUTB_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_TIMEOUTB_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_TIMEOUTB` writer - Timeout B Interrupt"] pub type INT_EVENT0_ISET_TIMEOUTB_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_TIMEOUTB_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_TIMEOUTB_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_timeoutb_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_TIMEOUTB_AW :: INT_EVENT0_ISET_TIMEOUTB_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_timeoutb_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_TIMEOUTB_AW :: INT_EVENT0_ISET_TIMEOUTB_SET) } } # [doc = "Slave Receive Data Interrupt Signals that a byte has been received\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_SRXDONE_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_SRXDONE_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_SRXDONE_SET = 1 , } impl From < INT_EVENT0_ISET_SRXDONE_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_SRXDONE_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_SRXDONE` writer - Slave Receive Data Interrupt Signals that a byte has been received"] pub type INT_EVENT0_ISET_SRXDONE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_SRXDONE_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_SRXDONE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_srxdone_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_SRXDONE_AW :: INT_EVENT0_ISET_SRXDONE_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_srxdone_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_SRXDONE_AW :: INT_EVENT0_ISET_SRXDONE_SET) } } # [doc = "Slave Transmit Transaction completed Interrupt\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_STXDONE_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_STXDONE_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_STXDONE_SET = 1 , } impl From < INT_EVENT0_ISET_STXDONE_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_STXDONE_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_STXDONE` writer - Slave Transmit Transaction completed Interrupt"] pub type INT_EVENT0_ISET_STXDONE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_STXDONE_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_STXDONE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_stxdone_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_STXDONE_AW :: INT_EVENT0_ISET_STXDONE_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_stxdone_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_STXDONE_AW :: INT_EVENT0_ISET_STXDONE_SET) } } # [doc = "Slave Receive FIFO Trigger\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_SRXFIFOTRG_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_SRXFIFOTRG_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_SRXFIFOTRG_SET = 1 , } impl From < INT_EVENT0_ISET_SRXFIFOTRG_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_SRXFIFOTRG_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_SRXFIFOTRG` writer - Slave Receive FIFO Trigger"] pub type INT_EVENT0_ISET_SRXFIFOTRG_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_SRXFIFOTRG_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_SRXFIFOTRG_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_srxfifotrg_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_SRXFIFOTRG_AW :: INT_EVENT0_ISET_SRXFIFOTRG_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_srxfifotrg_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_SRXFIFOTRG_AW :: INT_EVENT0_ISET_SRXFIFOTRG_SET) } } # [doc = "Slave Transmit FIFO Trigger\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_STXFIFOTRG_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_STXFIFOTRG_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_STXFIFOTRG_SET = 1 , } impl From < INT_EVENT0_ISET_STXFIFOTRG_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_STXFIFOTRG_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_STXFIFOTRG` writer - Slave Transmit FIFO Trigger"] pub type INT_EVENT0_ISET_STXFIFOTRG_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_STXFIFOTRG_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_STXFIFOTRG_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_stxfifotrg_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_STXFIFOTRG_AW :: INT_EVENT0_ISET_STXFIFOTRG_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_stxfifotrg_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_STXFIFOTRG_AW :: INT_EVENT0_ISET_STXFIFOTRG_SET) } } # [doc = "RXFIFO full event. This interrupt is set if an RX FIFO is full.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_SRXFIFOFULL_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_SRXFIFOFULL_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_SRXFIFOFULL_SET = 1 , } impl From < INT_EVENT0_ISET_SRXFIFOFULL_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_SRXFIFOFULL_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_SRXFIFOFULL` writer - RXFIFO full event. This interrupt is set if an RX FIFO is full."] pub type INT_EVENT0_ISET_SRXFIFOFULL_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_SRXFIFOFULL_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_SRXFIFOFULL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_srxfifofull_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_SRXFIFOFULL_AW :: INT_EVENT0_ISET_SRXFIFOFULL_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_srxfifofull_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_SRXFIFOFULL_AW :: INT_EVENT0_ISET_SRXFIFOFULL_SET) } } # [doc = "Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_STXEMPTY_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_STXEMPTY_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_STXEMPTY_SET = 1 , } impl From < INT_EVENT0_ISET_STXEMPTY_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_STXEMPTY_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_STXEMPTY` writer - Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode."] pub type INT_EVENT0_ISET_STXEMPTY_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_STXEMPTY_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_STXEMPTY_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_stxempty_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_STXEMPTY_AW :: INT_EVENT0_ISET_STXEMPTY_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_stxempty_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_STXEMPTY_AW :: INT_EVENT0_ISET_STXEMPTY_SET) } } # [doc = "Start Condition Interrupt\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_SSTART_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_SSTART_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_SSTART_SET = 1 , } impl From < INT_EVENT0_ISET_SSTART_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_SSTART_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_SSTART` writer - Start Condition Interrupt"] pub type INT_EVENT0_ISET_SSTART_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_SSTART_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_SSTART_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_sstart_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_SSTART_AW :: INT_EVENT0_ISET_SSTART_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_sstart_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_SSTART_AW :: INT_EVENT0_ISET_SSTART_SET) } } # [doc = "Stop Condition Interrupt\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_SSTOP_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_SSTOP_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_SSTOP_SET = 1 , } impl From < INT_EVENT0_ISET_SSTOP_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_SSTOP_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_SSTOP` writer - Stop Condition Interrupt"] pub type INT_EVENT0_ISET_SSTOP_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_SSTOP_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_SSTOP_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_sstop_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_SSTOP_AW :: INT_EVENT0_ISET_SSTOP_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_sstop_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_SSTOP_AW :: INT_EVENT0_ISET_SSTOP_SET) } } # [doc = "General Call Interrupt\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_SGENCALL_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_SGENCALL_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_SGENCALL_SET = 1 , } impl From < INT_EVENT0_ISET_SGENCALL_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_SGENCALL_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_SGENCALL` writer - General Call Interrupt"] pub type INT_EVENT0_ISET_SGENCALL_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_SGENCALL_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_SGENCALL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_sgencall_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_SGENCALL_AW :: INT_EVENT0_ISET_SGENCALL_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_sgencall_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_SGENCALL_AW :: INT_EVENT0_ISET_SGENCALL_SET) } } # [doc = "DMA Done 1 on Event Channel 2\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_SDMA_DONE1_2_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_SDMA_DONE1_2_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_SDMA_DONE1_2_SET = 1 , } impl From < INT_EVENT0_ISET_SDMA_DONE1_2_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_SDMA_DONE1_2_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_SDMA_DONE1_2` writer - DMA Done 1 on Event Channel 2"] pub type INT_EVENT0_ISET_SDMA_DONE1_2_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_SDMA_DONE1_2_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_SDMA_DONE1_2_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_sdma_done1_2_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_SDMA_DONE1_2_AW :: INT_EVENT0_ISET_SDMA_DONE1_2_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_sdma_done1_2_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_SDMA_DONE1_2_AW :: INT_EVENT0_ISET_SDMA_DONE1_2_SET) } } # [doc = "DMA Done 1 on Event Channel 3\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_SDMA_DONE1_3_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_SDMA_DONE1_3_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_SDMA_DONE1_3_SET = 1 , } impl From < INT_EVENT0_ISET_SDMA_DONE1_3_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_SDMA_DONE1_3_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_SDMA_DONE1_3` writer - DMA Done 1 on Event Channel 3"] pub type INT_EVENT0_ISET_SDMA_DONE1_3_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_SDMA_DONE1_3_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_SDMA_DONE1_3_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_sdma_done1_3_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_SDMA_DONE1_3_AW :: INT_EVENT0_ISET_SDMA_DONE1_3_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_sdma_done1_3_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_SDMA_DONE1_3_AW :: INT_EVENT0_ISET_SDMA_DONE1_3_SET) } } # [doc = "Slave RX Pec Error Interrupt\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_SPEC_RX_ERR_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_SPEC_RX_ERR_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_SPEC_RX_ERR_SET = 1 , } impl From < INT_EVENT0_ISET_SPEC_RX_ERR_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_SPEC_RX_ERR_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_SPEC_RX_ERR` writer - Slave RX Pec Error Interrupt"] pub type INT_EVENT0_ISET_SPEC_RX_ERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_SPEC_RX_ERR_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_SPEC_RX_ERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_spec_rx_err_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_SPEC_RX_ERR_AW :: INT_EVENT0_ISET_SPEC_RX_ERR_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_spec_rx_err_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_SPEC_RX_ERR_AW :: INT_EVENT0_ISET_SPEC_RX_ERR_SET) } } # [doc = "Slave TX FIFO underflow\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_STX_UNFL_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_STX_UNFL_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_STX_UNFL_SET = 1 , } impl From < INT_EVENT0_ISET_STX_UNFL_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_STX_UNFL_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_STX_UNFL` writer - Slave TX FIFO underflow"] pub type INT_EVENT0_ISET_STX_UNFL_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_STX_UNFL_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_STX_UNFL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_stx_unfl_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_STX_UNFL_AW :: INT_EVENT0_ISET_STX_UNFL_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_stx_unfl_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_STX_UNFL_AW :: INT_EVENT0_ISET_STX_UNFL_SET) } } # [doc = "Slave RX FIFO overflow\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_SRX_OVFL_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_SRX_OVFL_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_SRX_OVFL_SET = 1 , } impl From < INT_EVENT0_ISET_SRX_OVFL_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_SRX_OVFL_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_SRX_OVFL` writer - Slave RX FIFO overflow"] pub type INT_EVENT0_ISET_SRX_OVFL_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_SRX_OVFL_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_SRX_OVFL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_srx_ovfl_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_SRX_OVFL_AW :: INT_EVENT0_ISET_SRX_OVFL_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_srx_ovfl_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_SRX_OVFL_AW :: INT_EVENT0_ISET_SRX_OVFL_SET) } } # [doc = "Slave Arbitration Lost\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_SARBLOST_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_SARBLOST_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_SARBLOST_SET = 1 , } impl From < INT_EVENT0_ISET_SARBLOST_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_SARBLOST_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_SARBLOST` writer - Slave Arbitration Lost"] pub type INT_EVENT0_ISET_SARBLOST_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_SARBLOST_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_SARBLOST_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_sarblost_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_SARBLOST_AW :: INT_EVENT0_ISET_SARBLOST_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_sarblost_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_SARBLOST_AW :: INT_EVENT0_ISET_SARBLOST_SET) } } # [doc = "Interrupt overflow\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_INTR_OVFL_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_INTR_OVFL_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_INTR_OVFL_SET = 1 , } impl From < INT_EVENT0_ISET_INTR_OVFL_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_INTR_OVFL_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_INTR_OVFL` writer - Interrupt overflow"] pub type INT_EVENT0_ISET_INTR_OVFL_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_INTR_OVFL_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_INTR_OVFL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_intr_ovfl_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_INTR_OVFL_AW :: INT_EVENT0_ISET_INTR_OVFL_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_intr_ovfl_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_INTR_OVFL_AW :: INT_EVENT0_ISET_INTR_OVFL_SET) } } impl W { # [doc = "Bit 0 - Master Receive Data Interrupt Signals that a byte has been received"] # [inline (always)] # [must_use] pub fn int_event0_iset_mrxdone (& mut self) -> INT_EVENT0_ISET_MRXDONE_W < INT_EVENT0_ISET_SPEC , 0 > { INT_EVENT0_ISET_MRXDONE_W :: new (self) } # [doc = "Bit 1 - Master Transmit Transaction completed Interrupt"] # [inline (always)] # [must_use] pub fn int_event0_iset_mtxdone (& mut self) -> INT_EVENT0_ISET_MTXDONE_W < INT_EVENT0_ISET_SPEC , 1 > { INT_EVENT0_ISET_MTXDONE_W :: new (self) } # [doc = "Bit 2 - Master Receive FIFO Trigger Trigger when RX FIFO contains &gt;= defined bytes"] # [inline (always)] # [must_use] pub fn int_event0_iset_mrxfifotrg (& mut self) -> INT_EVENT0_ISET_MRXFIFOTRG_W < INT_EVENT0_ISET_SPEC , 2 > { INT_EVENT0_ISET_MRXFIFOTRG_W :: new (self) } # [doc = "Bit 3 - Master Transmit FIFO Trigger Trigger when Transmit FIFO contains &lt;= defined bytes"] # [inline (always)] # [must_use] pub fn int_event0_iset_mtxfifotrg (& mut self) -> INT_EVENT0_ISET_MTXFIFOTRG_W < INT_EVENT0_ISET_SPEC , 3 > { INT_EVENT0_ISET_MTXFIFOTRG_W :: new (self) } # [doc = "Bit 4 - RXFIFO full event."] # [inline (always)] # [must_use] pub fn int_event0_iset_mrxfifofull (& mut self) -> INT_EVENT0_ISET_MRXFIFOFULL_W < INT_EVENT0_ISET_SPEC , 4 > { INT_EVENT0_ISET_MRXFIFOFULL_W :: new (self) } # [doc = "Bit 5 - Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode."] # [inline (always)] # [must_use] pub fn int_event0_iset_mtxempty (& mut self) -> INT_EVENT0_ISET_MTXEMPTY_W < INT_EVENT0_ISET_SPEC , 5 > { INT_EVENT0_ISET_MTXEMPTY_W :: new (self) } # [doc = "Bit 7 - Address/Data NACK Interrupt"] # [inline (always)] # [must_use] pub fn int_event0_iset_mnack (& mut self) -> INT_EVENT0_ISET_MNACK_W < INT_EVENT0_ISET_SPEC , 7 > { INT_EVENT0_ISET_MNACK_W :: new (self) } # [doc = "Bit 8 - START Detection Interrupt"] # [inline (always)] # [must_use] pub fn int_event0_iset_mstart (& mut self) -> INT_EVENT0_ISET_MSTART_W <'_, INT_EVENT0_ISET_SPEC , 8 > { INT_EVENT0_ISET_MSTART_W :: new (self) } # [doc = "Bit 9 - STOP Detection Interrupt"] # [inline (always)] # [must_use] pub fn int_event0_iset_mstop (& mut self) -> INT_EVENT0_ISET_MSTOP_W < INT_EVENT0_ISET_SPEC , 9 > { INT_EVENT0_ISET_MSTOP_W :: new (self) } # [doc = "Bit 10 - Arbitration Lost Interrupt"] # [inline (always)] # [must_use] pub fn int_event0_iset_marblost (& mut self) -> INT_EVENT0_ISET_MARBLOST_W < INT_EVENT0_ISET_SPEC , 10 > { INT_EVENT0_ISET_MARBLOST_W :: new (self) } # [doc = "Bit 11 - DMA Done 1 on Event Channel 2"] # [inline (always)] # [must_use] pub fn int_event0_iset_mdma_done1_2 (& mut self) -> INT_EVENT0_ISET_MDMA_DONE1_2_W < INT_EVENT0_ISET_SPEC , 11 > { INT_EVENT0_ISET_MDMA_DONE1_2_W :: new (self) } # [doc = "Bit 12 - DMA Done 1 on Event Channel 3"] # [inline (always)] # [must_use] pub fn int_event0_iset_mdma_done1_3 (& mut self) -> INT_EVENT0_ISET_MDMA_DONE1_3_W < INT_EVENT0_ISET_SPEC , 12 > { INT_EVENT0_ISET_MDMA_DONE1_3_W :: new (self) } # [doc = "Bit 13 - Master RX Pec Error Interrupt"] # [inline (always)] # [must_use] pub fn int_event0_iset_mpec_rx_err (& mut self) -> INT_EVENT0_ISET_MPEC_RX_ERR_W < INT_EVENT0_ISET_SPEC , 13 > { INT_EVENT0_ISET_MPEC_RX_ERR_W :: new (self) } # [doc = "Bit 14 - Timeout A interrupt"] # [inline (always)] # [must_use] pub fn int_event0_iset_timeouta (& mut self) -> INT_EVENT0_ISET_TIMEOUTA_W < INT_EVENT0_ISET_SPEC , 14 > { INT_EVENT0_ISET_TIMEOUTA_W :: new (self) } # [doc = "Bit 15 - Timeout B Interrupt"] # [inline (always)] # [must_use] pub fn int_event0_iset_timeoutb (& mut self) -> INT_EVENT0_ISET_TIMEOUTB_W < INT_EVENT0_ISET_SPEC , 15 > { INT_EVENT0_ISET_TIMEOUTB_W :: new (self) } # [doc = "Bit 16 - Slave Receive Data Interrupt Signals that a byte has been received"] # [inline (always)] # [must_use] pub fn int_event0_iset_srxdone (& mut self) -> INT_EVENT0_ISET_SRXDONE_W < INT_EVENT0_ISET_SPEC , 16 > { INT_EVENT0_ISET_SRXDONE_W :: new (self) } # [doc = "Bit 17 - Slave Transmit Transaction completed Interrupt"] # [inline (always)] # [must_use] pub fn int_event0_iset_stxdone (& mut self) -> INT_EVENT0_ISET_STXDONE_W < INT_EVENT0_ISET_SPEC , 17 > { INT_EVENT0_ISET_STXDONE_W :: new (self) } # [doc = "Bit 18 - Slave Receive FIFO Trigger"] # [inline (always)] # [must_use] pub fn int_event0_iset_srxfifotrg (& mut self) -> INT_EVENT0_ISET_SRXFIFOTRG_W < INT_EVENT0_ISET_SPEC , 18 > { INT_EVENT0_ISET_SRXFIFOTRG_W :: new (self) } # [doc = "Bit 19 - Slave Transmit FIFO Trigger"] # [inline (always)] # [must_use] pub fn int_event0_iset_stxfifotrg (& mut self) -> INT_EVENT0_ISET_STXFIFOTRG_W < INT_EVENT0_ISET_SPEC , 19 > { INT_EVENT0_ISET_STXFIFOTRG_W :: new (self) } # [doc = "Bit 20 - RXFIFO full event. This interrupt is set if an RX FIFO is full."] # [inline (always)] # [must_use] pub fn int_event0_iset_srxfifofull (& mut self) -> INT_EVENT0_ISET_SRXFIFOFULL_W < INT_EVENT0_ISET_SPEC , 20 > { INT_EVENT0_ISET_SRXFIFOFULL_W :: new (self) } # [doc = "Bit 21 - Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode."] # [inline (always)] # [must_use] pub fn int_event0_iset_stxempty (& mut self) -> INT_EVENT0_ISET_STXEMPTY_W < INT_EVENT0_ISET_SPEC , 21 > { INT_EVENT0_ISET_STXEMPTY_W :: new (self) } # [doc = "Bit 22 - Start Condition Interrupt"] # [inline (always)] # [must_use] pub fn int_event0_iset_sstart (& mut self) -> INT_EVENT0_ISET_SSTART_W < INT_EVENT0_ISET_SPEC , 22 > { INT_EVENT0_ISET_SSTART_W :: new (self) } # [doc = "Bit 23 - Stop Condition Interrupt"] # [inline (always)] # [must_use] pub fn int_event0_iset_sstop (& mut self) -> INT_EVENT0_ISET_SSTOP_W < INT_EVENT0_ISET_SPEC , 23 > { INT_EVENT0_ISET_SSTOP_W :: new (self) } # [doc = "Bit 24 - General Call Interrupt"] # [inline (always)] # [must_use] pub fn int_event0_iset_sgencall (& mut self) -> INT_EVENT0_ISET_SGENCALL_W < INT_EVENT0_ISET_SPEC , 24 > { INT_EVENT0_ISET_SGENCALL_W :: new (self) } # [doc = "Bit 25 - DMA Done 1 on Event Channel 2"] # [inline (always)] # [must_use] pub fn int_event0_iset_sdma_done1_2 (& mut self) -> INT_EVENT0_ISET_SDMA_DONE1_2_W < INT_EVENT0_ISET_SPEC , 25 > { INT_EVENT0_ISET_SDMA_DONE1_2_W :: new (self) } # [doc = "Bit 26 - DMA Done 1 on Event Channel 3"] # [inline (always)] # [must_use] pub fn int_event0_iset_sdma_done1_3 (& mut self) -> INT_EVENT0_ISET_SDMA_DONE1_3_W < INT_EVENT0_ISET_SPEC , 26 > { INT_EVENT0_ISET_SDMA_DONE1_3_W :: new (self) } # [doc = "Bit 27 - Slave RX Pec Error Interrupt"] # [inline (always)] # [must_use] pub fn int_event0_iset_spec_rx_err (& mut self) -> INT_EVENT0_ISET_SPEC_RX_ERR_W < INT_EVENT0_ISET_SPEC , 27 > { INT_EVENT0_ISET_SPEC_RX_ERR_W :: new (self) } # [doc = "Bit 28 - Slave TX FIFO underflow"] # [inline (always)] # [must_use] pub fn int_event0_iset_stx_unfl (& mut self) -> INT_EVENT0_ISET_STX_UNFL_W < INT_EVENT0_ISET_SPEC , 28 > { INT_EVENT0_ISET_STX_UNFL_W :: new (self) } # [doc = "Bit 29 - Slave RX FIFO overflow"] # [inline (always)] # [must_use] pub fn int_event0_iset_srx_ovfl (& mut self) -> INT_EVENT0_ISET_SRX_OVFL_W < INT_EVENT0_ISET_SPEC , 29 > { INT_EVENT0_ISET_SRX_OVFL_W :: new (self) } # [doc = "Bit 30 - Slave Arbitration Lost"] # [inline (always)] # [must_use] pub fn int_event0_iset_sarblost (& mut self) -> INT_EVENT0_ISET_SARBLOST_W < INT_EVENT0_ISET_SPEC , 30 > { INT_EVENT0_ISET_SARBLOST_W :: new (self) } # [doc = "Bit 31 - Interrupt overflow"] # [inline (always)] # [must_use] pub fn int_event0_iset_intr_ovfl (& mut self) -> INT_EVENT0_ISET_INTR_OVFL_W < INT_EVENT0_ISET_SPEC , 31 > { INT_EVENT0_ISET_INTR_OVFL_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Interrupt set\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_event0_iset::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct INT_EVENT0_ISET_SPEC ; impl crate :: RegisterSpec for INT_EVENT0_ISET_SPEC { type Ux = u32 ; } # [doc = "`write(|w| ..)` method takes [`int_event0_iset::W`](W) writer structure"] impl crate :: Writable for INT_EVENT0_ISET_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets INT_EVENT0_ISET to value 0"] impl crate :: Resettable for INT_EVENT0_ISET_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/i2c0/sctr.rs:1:26798 [INFO] [stdout] | [INFO] [stdout] 1 | ...st_use] pub fn sctr_swuen (& mut self) -> SCTR_SWUEN_W < SCTR_SPEC , 10 > { SCTR_SWUEN_W :: new (self) } # [doc = r" Writes raw bits t... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `SCTR` reader"] pub type R = crate :: R < SCTR_SPEC > ; # [doc = "Register `SCTR` writer"] pub type W = crate :: W < SCTR_SPEC > ; # [doc = "Field `SCTR_ACTIVE` reader - Device Active. Setting this bit enables the slave functionality."] pub type SCTR_ACTIVE_R = crate :: BitReader < SCTR_ACTIVE_A > ; # [doc = "Device Active. Setting this bit enables the slave functionality.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum SCTR_ACTIVE_A { # [doc = "0: DISABLE"] SCTR_ACTIVE_DISABLE = 0 , # [doc = "1: ENABLE"] SCTR_ACTIVE_ENABLE = 1 , } impl From < SCTR_ACTIVE_A > for bool { # [inline (always)] fn from (variant : SCTR_ACTIVE_A) -> Self { variant as u8 != 0 } } impl SCTR_ACTIVE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> SCTR_ACTIVE_A { match self . bits { false => SCTR_ACTIVE_A :: SCTR_ACTIVE_DISABLE , true => SCTR_ACTIVE_A :: SCTR_ACTIVE_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_sctr_active_disable (& self) -> bool { * self == SCTR_ACTIVE_A :: SCTR_ACTIVE_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_sctr_active_enable (& self) -> bool { * self == SCTR_ACTIVE_A :: SCTR_ACTIVE_ENABLE } } # [doc = "Field `SCTR_ACTIVE` writer - Device Active. Setting this bit enables the slave functionality."] pub type SCTR_ACTIVE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , SCTR_ACTIVE_A > ; impl < 'a , REG , const O : u8 > SCTR_ACTIVE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn sctr_active_disable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_ACTIVE_A :: SCTR_ACTIVE_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn sctr_active_enable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_ACTIVE_A :: SCTR_ACTIVE_ENABLE) } } # [doc = "Field `SCTR_GENCALL` reader - General call response enable. This bit is only available in UCBxI2COA0. Modify only when UCSWRST = 1. 0b = Do not respond to a general call 1b = Respond to a general call"] pub type SCTR_GENCALL_R = crate :: BitReader < SCTR_GENCALL_A > ; # [doc = "General call response enable. This bit is only available in UCBxI2COA0. Modify only when UCSWRST = 1. 0b = Do not respond to a general call 1b = Respond to a general call\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum SCTR_GENCALL_A { # [doc = "0: DISABLE"] SCTR_GENCALL_DISABLE = 0 , # [doc = "1: ENABLE"] SCTR_GENCALL_ENABLE = 1 , } impl From < SCTR_GENCALL_A > for bool { # [inline (always)] fn from (variant : SCTR_GENCALL_A) -> Self { variant as u8 != 0 } } impl SCTR_GENCALL_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> SCTR_GENCALL_A { match self . bits { false => SCTR_GENCALL_A :: SCTR_GENCALL_DISABLE , true => SCTR_GENCALL_A :: SCTR_GENCALL_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_sctr_gencall_disable (& self) -> bool { * self == SCTR_GENCALL_A :: SCTR_GENCALL_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_sctr_gencall_enable (& self) -> bool { * self == SCTR_GENCALL_A :: SCTR_GENCALL_ENABLE } } # [doc = "Field `SCTR_GENCALL` writer - General call response enable. This bit is only available in UCBxI2COA0. Modify only when UCSWRST = 1. 0b = Do not respond to a general call 1b = Respond to a general call"] pub type SCTR_GENCALL_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , SCTR_GENCALL_A > ; impl < 'a , REG , const O : u8 > SCTR_GENCALL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn sctr_gencall_disable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_GENCALL_A :: SCTR_GENCALL_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn sctr_gencall_enable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_GENCALL_A :: SCTR_GENCALL_ENABLE) } } # [doc = "Field `SCTR_SCLKSTRETCH` reader - Slave Clock Stretch Enable"] pub type SCTR_SCLKSTRETCH_R = crate :: BitReader < SCTR_SCLKSTRETCH_A > ; # [doc = "Slave Clock Stretch Enable\n\nValue on reset: 1"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum SCTR_SCLKSTRETCH_A { # [doc = "0: DISABLE"] SCTR_SCLKSTRETCH_DISABLE = 0 , # [doc = "1: ENABLE"] SCTR_SCLKSTRETCH_ENABLE = 1 , } impl From < SCTR_SCLKSTRETCH_A > for bool { # [inline (always)] fn from (variant : SCTR_SCLKSTRETCH_A) -> Self { variant as u8 != 0 } } impl SCTR_SCLKSTRETCH_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> SCTR_SCLKSTRETCH_A { match self . bits { false => SCTR_SCLKSTRETCH_A :: SCTR_SCLKSTRETCH_DISABLE , true => SCTR_SCLKSTRETCH_A :: SCTR_SCLKSTRETCH_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_sctr_sclkstretch_disable (& self) -> bool { * self == SCTR_SCLKSTRETCH_A :: SCTR_SCLKSTRETCH_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_sctr_sclkstretch_enable (& self) -> bool { * self == SCTR_SCLKSTRETCH_A :: SCTR_SCLKSTRETCH_ENABLE } } # [doc = "Field `SCTR_SCLKSTRETCH` writer - Slave Clock Stretch Enable"] pub type SCTR_SCLKSTRETCH_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , SCTR_SCLKSTRETCH_A > ; impl < 'a , REG , const O : u8 > SCTR_SCLKSTRETCH_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn sctr_sclkstretch_disable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_SCLKSTRETCH_A :: SCTR_SCLKSTRETCH_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn sctr_sclkstretch_enable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_SCLKSTRETCH_A :: SCTR_SCLKSTRETCH_ENABLE) } } # [doc = "Field `SCTR_TXEMPTY_ON_TREQ` reader - Tx Empty Interrupt on TREQ"] pub type SCTR_TXEMPTY_ON_TREQ_R = crate :: BitReader < SCTR_TXEMPTY_ON_TREQ_A > ; # [doc = "Tx Empty Interrupt on TREQ\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum SCTR_TXEMPTY_ON_TREQ_A { # [doc = "0: DISABLE"] SCTR_TXEMPTY_ON_TREQ_DISABLE = 0 , # [doc = "1: ENABLE"] SCTR_TXEMPTY_ON_TREQ_ENABLE = 1 , } impl From < SCTR_TXEMPTY_ON_TREQ_A > for bool { # [inline (always)] fn from (variant : SCTR_TXEMPTY_ON_TREQ_A) -> Self { variant as u8 != 0 } } impl SCTR_TXEMPTY_ON_TREQ_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> SCTR_TXEMPTY_ON_TREQ_A { match self . bits { false => SCTR_TXEMPTY_ON_TREQ_A :: SCTR_TXEMPTY_ON_TREQ_DISABLE , true => SCTR_TXEMPTY_ON_TREQ_A :: SCTR_TXEMPTY_ON_TREQ_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_sctr_txempty_on_treq_disable (& self) -> bool { * self == SCTR_TXEMPTY_ON_TREQ_A :: SCTR_TXEMPTY_ON_TREQ_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_sctr_txempty_on_treq_enable (& self) -> bool { * self == SCTR_TXEMPTY_ON_TREQ_A :: SCTR_TXEMPTY_ON_TREQ_ENABLE } } # [doc = "Field `SCTR_TXEMPTY_ON_TREQ` writer - Tx Empty Interrupt on TREQ"] pub type SCTR_TXEMPTY_ON_TREQ_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , SCTR_TXEMPTY_ON_TREQ_A > ; impl < 'a , REG , const O : u8 > SCTR_TXEMPTY_ON_TREQ_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn sctr_txempty_on_treq_disable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_TXEMPTY_ON_TREQ_A :: SCTR_TXEMPTY_ON_TREQ_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn sctr_txempty_on_treq_enable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_TXEMPTY_ON_TREQ_A :: SCTR_TXEMPTY_ON_TREQ_ENABLE) } } # [doc = "Field `SCTR_TXTRIG_TXMODE` reader - Tx Trigger when slave FSM is in Tx Mode"] pub type SCTR_TXTRIG_TXMODE_R = crate :: BitReader < SCTR_TXTRIG_TXMODE_A > ; # [doc = "Tx Trigger when slave FSM is in Tx Mode\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum SCTR_TXTRIG_TXMODE_A { # [doc = "0: DISABLE"] SCTR_TXTRIG_TXMODE_DISABLE = 0 , # [doc = "1: ENABLE"] SCTR_TXTRIG_TXMODE_ENABLE = 1 , } impl From < SCTR_TXTRIG_TXMODE_A > for bool { # [inline (always)] fn from (variant : SCTR_TXTRIG_TXMODE_A) -> Self { variant as u8 != 0 } } impl SCTR_TXTRIG_TXMODE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> SCTR_TXTRIG_TXMODE_A { match self . bits { false => SCTR_TXTRIG_TXMODE_A :: SCTR_TXTRIG_TXMODE_DISABLE , true => SCTR_TXTRIG_TXMODE_A :: SCTR_TXTRIG_TXMODE_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_sctr_txtrig_txmode_disable (& self) -> bool { * self == SCTR_TXTRIG_TXMODE_A :: SCTR_TXTRIG_TXMODE_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_sctr_txtrig_txmode_enable (& self) -> bool { * self == SCTR_TXTRIG_TXMODE_A :: SCTR_TXTRIG_TXMODE_ENABLE } } # [doc = "Field `SCTR_TXTRIG_TXMODE` writer - Tx Trigger when slave FSM is in Tx Mode"] pub type SCTR_TXTRIG_TXMODE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , SCTR_TXTRIG_TXMODE_A > ; impl < 'a , REG , const O : u8 > SCTR_TXTRIG_TXMODE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn sctr_txtrig_txmode_disable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_TXTRIG_TXMODE_A :: SCTR_TXTRIG_TXMODE_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn sctr_txtrig_txmode_enable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_TXTRIG_TXMODE_A :: SCTR_TXTRIG_TXMODE_ENABLE) } } # [doc = "Field `SCTR_TXWAIT_STALE_TXFIFO` reader - Tx transfer waits when stale data in Tx FIFO. This prevents stale bytes left in the TX FIFO from automatically being sent on the next I2C packet. Note: this should be used with TXEMPTY_ON_TREQ set to prevent the Slave State Machine from waiting for TX FIFO data without an interrupt notification when the FIFO data is stale."] pub type SCTR_TXWAIT_STALE_TXFIFO_R = crate :: BitReader < SCTR_TXWAIT_STALE_TXFIFO_A > ; # [doc = "Tx transfer waits when stale data in Tx FIFO. This prevents stale bytes left in the TX FIFO from automatically being sent on the next I2C packet. Note: this should be used with TXEMPTY_ON_TREQ set to prevent the Slave State Machine from waiting for TX FIFO data without an interrupt notification when the FIFO data is stale.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum SCTR_TXWAIT_STALE_TXFIFO_A { # [doc = "0: DISABLE"] SCTR_TXWAIT_STALE_TXFIFO_DISABLE = 0 , # [doc = "1: ENABLE"] SCTR_TXWAIT_STALE_TXFIFO_ENABLE = 1 , } impl From < SCTR_TXWAIT_STALE_TXFIFO_A > for bool { # [inline (always)] fn from (variant : SCTR_TXWAIT_STALE_TXFIFO_A) -> Self { variant as u8 != 0 } } impl SCTR_TXWAIT_STALE_TXFIFO_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> SCTR_TXWAIT_STALE_TXFIFO_A { match self . bits { false => SCTR_TXWAIT_STALE_TXFIFO_A :: SCTR_TXWAIT_STALE_TXFIFO_DISABLE , true => SCTR_TXWAIT_STALE_TXFIFO_A :: SCTR_TXWAIT_STALE_TXFIFO_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_sctr_txwait_stale_txfifo_disable (& self) -> bool { * self == SCTR_TXWAIT_STALE_TXFIFO_A :: SCTR_TXWAIT_STALE_TXFIFO_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_sctr_txwait_stale_txfifo_enable (& self) -> bool { * self == SCTR_TXWAIT_STALE_TXFIFO_A :: SCTR_TXWAIT_STALE_TXFIFO_ENABLE } } # [doc = "Field `SCTR_TXWAIT_STALE_TXFIFO` writer - Tx transfer waits when stale data in Tx FIFO. This prevents stale bytes left in the TX FIFO from automatically being sent on the next I2C packet. Note: this should be used with TXEMPTY_ON_TREQ set to prevent the Slave State Machine from waiting for TX FIFO data without an interrupt notification when the FIFO data is stale."] pub type SCTR_TXWAIT_STALE_TXFIFO_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , SCTR_TXWAIT_STALE_TXFIFO_A > ; impl < 'a , REG , const O : u8 > SCTR_TXWAIT_STALE_TXFIFO_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn sctr_txwait_stale_txfifo_disable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_TXWAIT_STALE_TXFIFO_A :: SCTR_TXWAIT_STALE_TXFIFO_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn sctr_txwait_stale_txfifo_enable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_TXWAIT_STALE_TXFIFO_A :: SCTR_TXWAIT_STALE_TXFIFO_ENABLE) } } # [doc = "Field `SCTR_RXFULL_ON_RREQ` reader - Rx full interrupt generated on RREQ condition as indicated in SSR"] pub type SCTR_RXFULL_ON_RREQ_R = crate :: BitReader < SCTR_RXFULL_ON_RREQ_A > ; # [doc = "Rx full interrupt generated on RREQ condition as indicated in SSR\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum SCTR_RXFULL_ON_RREQ_A { # [doc = "0: DISABLE"] SCTR_RXFULL_ON_RREQ_DISABLE = 0 , # [doc = "1: ENABLE"] SCTR_RXFULL_ON_RREQ_ENABLE = 1 , } impl From < SCTR_RXFULL_ON_RREQ_A > for bool { # [inline (always)] fn from (variant : SCTR_RXFULL_ON_RREQ_A) -> Self { variant as u8 != 0 } } impl SCTR_RXFULL_ON_RREQ_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> SCTR_RXFULL_ON_RREQ_A { match self . bits { false => SCTR_RXFULL_ON_RREQ_A :: SCTR_RXFULL_ON_RREQ_DISABLE , true => SCTR_RXFULL_ON_RREQ_A :: SCTR_RXFULL_ON_RREQ_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_sctr_rxfull_on_rreq_disable (& self) -> bool { * self == SCTR_RXFULL_ON_RREQ_A :: SCTR_RXFULL_ON_RREQ_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_sctr_rxfull_on_rreq_enable (& self) -> bool { * self == SCTR_RXFULL_ON_RREQ_A :: SCTR_RXFULL_ON_RREQ_ENABLE } } # [doc = "Field `SCTR_RXFULL_ON_RREQ` writer - Rx full interrupt generated on RREQ condition as indicated in SSR"] pub type SCTR_RXFULL_ON_RREQ_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , SCTR_RXFULL_ON_RREQ_A > ; impl < 'a , REG , const O : u8 > SCTR_RXFULL_ON_RREQ_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn sctr_rxfull_on_rreq_disable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_RXFULL_ON_RREQ_A :: SCTR_RXFULL_ON_RREQ_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn sctr_rxfull_on_rreq_enable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_RXFULL_ON_RREQ_A :: SCTR_RXFULL_ON_RREQ_ENABLE) } } # [doc = "Field `SCTR_EN_DEFHOSTADR` reader - Enable Default Host Address"] pub type SCTR_EN_DEFHOSTADR_R = crate :: BitReader < SCTR_EN_DEFHOSTADR_A > ; # [doc = "Enable Default Host Address\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum SCTR_EN_DEFHOSTADR_A { # [doc = "0: DISABLE"] SCTR_EN_DEFHOSTADR_DISABLE = 0 , # [doc = "1: ENABLE"] SCTR_EN_DEFHOSTADR_ENABLE = 1 , } impl From < SCTR_EN_DEFHOSTADR_A > for bool { # [inline (always)] fn from (variant : SCTR_EN_DEFHOSTADR_A) -> Self { variant as u8 != 0 } } impl SCTR_EN_DEFHOSTADR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> SCTR_EN_DEFHOSTADR_A { match self . bits { false => SCTR_EN_DEFHOSTADR_A :: SCTR_EN_DEFHOSTADR_DISABLE , true => SCTR_EN_DEFHOSTADR_A :: SCTR_EN_DEFHOSTADR_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_sctr_en_defhostadr_disable (& self) -> bool { * self == SCTR_EN_DEFHOSTADR_A :: SCTR_EN_DEFHOSTADR_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_sctr_en_defhostadr_enable (& self) -> bool { * self == SCTR_EN_DEFHOSTADR_A :: SCTR_EN_DEFHOSTADR_ENABLE } } # [doc = "Field `SCTR_EN_DEFHOSTADR` writer - Enable Default Host Address"] pub type SCTR_EN_DEFHOSTADR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , SCTR_EN_DEFHOSTADR_A > ; impl < 'a , REG , const O : u8 > SCTR_EN_DEFHOSTADR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn sctr_en_defhostadr_disable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_EN_DEFHOSTADR_A :: SCTR_EN_DEFHOSTADR_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn sctr_en_defhostadr_enable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_EN_DEFHOSTADR_A :: SCTR_EN_DEFHOSTADR_ENABLE) } } # [doc = "Field `SCTR_EN_ALRESPADR` reader - Enable Alert Response Address"] pub type SCTR_EN_ALRESPADR_R = crate :: BitReader < SCTR_EN_ALRESPADR_A > ; # [doc = "Enable Alert Response Address\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum SCTR_EN_ALRESPADR_A { # [doc = "0: DISABLE"] SCTR_EN_ALRESPADR_DISABLE = 0 , # [doc = "1: ENABLE"] SCTR_EN_ALRESPADR_ENABLE = 1 , } impl From < SCTR_EN_ALRESPADR_A > for bool { # [inline (always)] fn from (variant : SCTR_EN_ALRESPADR_A) -> Self { variant as u8 != 0 } } impl SCTR_EN_ALRESPADR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> SCTR_EN_ALRESPADR_A { match self . bits { false => SCTR_EN_ALRESPADR_A :: SCTR_EN_ALRESPADR_DISABLE , true => SCTR_EN_ALRESPADR_A :: SCTR_EN_ALRESPADR_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_sctr_en_alrespadr_disable (& self) -> bool { * self == SCTR_EN_ALRESPADR_A :: SCTR_EN_ALRESPADR_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_sctr_en_alrespadr_enable (& self) -> bool { * self == SCTR_EN_ALRESPADR_A :: SCTR_EN_ALRESPADR_ENABLE } } # [doc = "Field `SCTR_EN_ALRESPADR` writer - Enable Alert Response Address"] pub type SCTR_EN_ALRESPADR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , SCTR_EN_ALRESPADR_A > ; impl < 'a , REG , const O : u8 > SCTR_EN_ALRESPADR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn sctr_en_alrespadr_disable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_EN_ALRESPADR_A :: SCTR_EN_ALRESPADR_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn sctr_en_alrespadr_enable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_EN_ALRESPADR_A :: SCTR_EN_ALRESPADR_ENABLE) } } # [doc = "Field `SCTR_EN_DEFDEVADR` reader - Enable Deault device address"] pub type SCTR_EN_DEFDEVADR_R = crate :: BitReader < SCTR_EN_DEFDEVADR_A > ; # [doc = "Enable Deault device address\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum SCTR_EN_DEFDEVADR_A { # [doc = "0: DISABLE"] SCTR_EN_DEFDEVADR_DISABLE = 0 , # [doc = "1: ENABLE"] SCTR_EN_DEFDEVADR_ENABLE = 1 , } impl From < SCTR_EN_DEFDEVADR_A > for bool { # [inline (always)] fn from (variant : SCTR_EN_DEFDEVADR_A) -> Self { variant as u8 != 0 } } impl SCTR_EN_DEFDEVADR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> SCTR_EN_DEFDEVADR_A { match self . bits { false => SCTR_EN_DEFDEVADR_A :: SCTR_EN_DEFDEVADR_DISABLE , true => SCTR_EN_DEFDEVADR_A :: SCTR_EN_DEFDEVADR_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_sctr_en_defdevadr_disable (& self) -> bool { * self == SCTR_EN_DEFDEVADR_A :: SCTR_EN_DEFDEVADR_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_sctr_en_defdevadr_enable (& self) -> bool { * self == SCTR_EN_DEFDEVADR_A :: SCTR_EN_DEFDEVADR_ENABLE } } # [doc = "Field `SCTR_EN_DEFDEVADR` writer - Enable Deault device address"] pub type SCTR_EN_DEFDEVADR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , SCTR_EN_DEFDEVADR_A > ; impl < 'a , REG , const O : u8 > SCTR_EN_DEFDEVADR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn sctr_en_defdevadr_disable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_EN_DEFDEVADR_A :: SCTR_EN_DEFDEVADR_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn sctr_en_defdevadr_enable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_EN_DEFDEVADR_A :: SCTR_EN_DEFDEVADR_ENABLE) } } # [doc = "Field `SCTR_SWUEN` reader - Slave Wakeup Enable"] pub type SCTR_SWUEN_R = crate :: BitReader < SCTR_SWUEN_A > ; # [doc = "Slave Wakeup Enable\n\nValue on reset: 1"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum SCTR_SWUEN_A { # [doc = "0: DISABLE"] SCTR_SWUEN_DISABLE = 0 , # [doc = "1: ENABLE"] SCTR_SWUEN_ENABLE = 1 , } impl From < SCTR_SWUEN_A > for bool { # [inline (always)] fn from (variant : SCTR_SWUEN_A) -> Self { variant as u8 != 0 } } impl SCTR_SWUEN_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> SCTR_SWUEN_A { match self . bits { false => SCTR_SWUEN_A :: SCTR_SWUEN_DISABLE , true => SCTR_SWUEN_A :: SCTR_SWUEN_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_sctr_swuen_disable (& self) -> bool { * self == SCTR_SWUEN_A :: SCTR_SWUEN_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_sctr_swuen_enable (& self) -> bool { * self == SCTR_SWUEN_A :: SCTR_SWUEN_ENABLE } } # [doc = "Field `SCTR_SWUEN` writer - Slave Wakeup Enable"] pub type SCTR_SWUEN_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , SCTR_SWUEN_A > ; impl < 'a , REG , const O : u8 > SCTR_SWUEN_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn sctr_swuen_disable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_SWUEN_A :: SCTR_SWUEN_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn sctr_swuen_enable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_SWUEN_A :: SCTR_SWUEN_ENABLE) } } impl R { # [doc = "Bit 0 - Device Active. Setting this bit enables the slave functionality."] # [inline (always)] pub fn sctr_active (& self) -> SCTR_ACTIVE_R { SCTR_ACTIVE_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - General call response enable. This bit is only available in UCBxI2COA0. Modify only when UCSWRST = 1. 0b = Do not respond to a general call 1b = Respond to a general call"] # [inline (always)] pub fn sctr_gencall (& self) -> SCTR_GENCALL_R { SCTR_GENCALL_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - Slave Clock Stretch Enable"] # [inline (always)] pub fn sctr_sclkstretch (& self) -> SCTR_SCLKSTRETCH_R { SCTR_SCLKSTRETCH_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - Tx Empty Interrupt on TREQ"] # [inline (always)] pub fn sctr_txempty_on_treq (& self) -> SCTR_TXEMPTY_ON_TREQ_R { SCTR_TXEMPTY_ON_TREQ_R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - Tx Trigger when slave FSM is in Tx Mode"] # [inline (always)] pub fn sctr_txtrig_txmode (& self) -> SCTR_TXTRIG_TXMODE_R { SCTR_TXTRIG_TXMODE_R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - Tx transfer waits when stale data in Tx FIFO. This prevents stale bytes left in the TX FIFO from automatically being sent on the next I2C packet. Note: this should be used with TXEMPTY_ON_TREQ set to prevent the Slave State Machine from waiting for TX FIFO data without an interrupt notification when the FIFO data is stale."] # [inline (always)] pub fn sctr_txwait_stale_txfifo (& self) -> SCTR_TXWAIT_STALE_TXFIFO_R { SCTR_TXWAIT_STALE_TXFIFO_R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - Rx full interrupt generated on RREQ condition as indicated in SSR"] # [inline (always)] pub fn sctr_rxfull_on_rreq (& self) -> SCTR_RXFULL_ON_RREQ_R { SCTR_RXFULL_ON_RREQ_R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - Enable Default Host Address"] # [inline (always)] pub fn sctr_en_defhostadr (& self) -> SCTR_EN_DEFHOSTADR_R { SCTR_EN_DEFHOSTADR_R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - Enable Alert Response Address"] # [inline (always)] pub fn sctr_en_alrespadr (& self) -> SCTR_EN_ALRESPADR_R { SCTR_EN_ALRESPADR_R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - Enable Deault device address"] # [inline (always)] pub fn sctr_en_defdevadr (& self) -> SCTR_EN_DEFDEVADR_R { SCTR_EN_DEFDEVADR_R :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - Slave Wakeup Enable"] # [inline (always)] pub fn sctr_swuen (& self) -> SCTR_SWUEN_R { SCTR_SWUEN_R :: new (((self . bits >> 10) & 1) != 0) } } impl W { # [doc = "Bit 0 - Device Active. Setting this bit enables the slave functionality."] # [inline (always)] # [must_use] pub fn sctr_active (& mut self) -> SCTR_ACTIVE_W < SCTR_SPEC , 0 > { SCTR_ACTIVE_W :: new (self) } # [doc = "Bit 1 - General call response enable. This bit is only available in UCBxI2COA0. Modify only when UCSWRST = 1. 0b = Do not respond to a general call 1b = Respond to a general call"] # [inline (always)] # [must_use] pub fn sctr_gencall (& mut self) -> SCTR_GENCALL_W < SCTR_SPEC , 1 > { SCTR_GENCALL_W :: new (self) } # [doc = "Bit 2 - Slave Clock Stretch Enable"] # [inline (always)] # [must_use] pub fn sctr_sclkstretch (& mut self) -> SCTR_SCLKSTRETCH_W < SCTR_SPEC , 2 > { SCTR_SCLKSTRETCH_W :: new (self) } # [doc = "Bit 3 - Tx Empty Interrupt on TREQ"] # [inline (always)] # [must_use] pub fn sctr_txempty_on_treq (& mut self) -> SCTR_TXEMPTY_ON_TREQ_W < SCTR_SPEC , 3 > { SCTR_TXEMPTY_ON_TREQ_W :: new (self) } # [doc = "Bit 4 - Tx Trigger when slave FSM is in Tx Mode"] # [inline (always)] # [must_use] pub fn sctr_txtrig_txmode (& mut self) -> SCTR_TXTRIG_TXMODE_W < SCTR_SPEC , 4 > { SCTR_TXTRIG_TXMODE_W :: new (self) } # [doc = "Bit 5 - Tx transfer waits when stale data in Tx FIFO. This prevents stale bytes left in the TX FIFO from automatically being sent on the next I2C packet. Note: this should be used with TXEMPTY_ON_TREQ set to prevent the Slave State Machine from waiting for TX FIFO data without an interrupt notification when the FIFO data is stale."] # [inline (always)] # [must_use] pub fn sctr_txwait_stale_txfifo (& mut self) -> SCTR_TXWAIT_STALE_TXFIFO_W < SCTR_SPEC , 5 > { SCTR_TXWAIT_STALE_TXFIFO_W :: new (self) } # [doc = "Bit 6 - Rx full interrupt generated on RREQ condition as indicated in SSR"] # [inline (always)] # [must_use] pub fn sctr_rxfull_on_rreq (& mut self) -> SCTR_RXFULL_ON_RREQ_W < SCTR_SPEC , 6 > { SCTR_RXFULL_ON_RREQ_W :: new (self) } # [doc = "Bit 7 - Enable Default Host Address"] # [inline (always)] # [must_use] pub fn sctr_en_defhostadr (& mut self) -> SCTR_EN_DEFHOSTADR_W < SCTR_SPEC , 7 > { SCTR_EN_DEFHOSTADR_W :: new (self) } # [doc = "Bit 8 - Enable Alert Response Address"] # [inline (always)] # [must_use] pub fn sctr_en_alrespadr (& mut self) -> SCTR_EN_ALRESPADR_W < SCTR_SPEC , 8 > { SCTR_EN_ALRESPADR_W :: new (self) } # [doc = "Bit 9 - Enable Deault device address"] # [inline (always)] # [must_use] pub fn sctr_en_defdevadr (& mut self) -> SCTR_EN_DEFDEVADR_W < SCTR_SPEC , 9 > { SCTR_EN_DEFDEVADR_W :: new (self) } # [doc = "Bit 10 - Slave Wakeup Enable"] # [inline (always)] # [must_use] pub fn sctr_swuen (& mut self) -> SCTR_SWUEN_W <'_, SCTR_SPEC , 10 > { SCTR_SWUEN_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "I2C Slave Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sctr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sctr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct SCTR_SPEC ; impl crate :: RegisterSpec for SCTR_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`sctr::R`](R) reader structure"] impl crate :: Readable for SCTR_SPEC { } # [doc = "`write(|w| ..)` method takes [`sctr::W`](W) writer structure"] impl crate :: Writable for SCTR_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets SCTR to value 0x0404"] impl crate :: Resettable for SCTR_SPEC { const RESET_VALUE : Self :: Ux = 0x0404 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/uart0/int_event0_imask.rs:1:40969 [INFO] [stdout] | [INFO] [stdout] 1 | ..._imask_parerr (& mut self) -> INT_EVENT0_IMASK_PARERR_W < INT_EVENT0_IMASK_SPEC , 2 > { INT_EVENT0_IMASK_PARERR_W :: new (self) } # [d... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `INT_EVENT0_IMASK` reader"] pub type R = crate :: R < INT_EVENT0_IMASK_SPEC > ; # [doc = "Register `INT_EVENT0_IMASK` writer"] pub type W = crate :: W < INT_EVENT0_IMASK_SPEC > ; # [doc = "Field `INT_EVENT0_IMASK_RTOUT` reader - Enable UARTOUT Receive Time-Out Interrupt."] pub type INT_EVENT0_IMASK_RTOUT_R = crate :: BitReader < INT_EVENT0_IMASK_RTOUT_A > ; # [doc = "Enable UARTOUT Receive Time-Out Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_RTOUT_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_RTOUT_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_RTOUT_SET = 1 , } impl From < INT_EVENT0_IMASK_RTOUT_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_RTOUT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_RTOUT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_RTOUT_A { match self . bits { false => INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_CLR , true => INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_rtout_clr (& self) -> bool { * self == INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_rtout_set (& self) -> bool { * self == INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_SET } } # [doc = "Field `INT_EVENT0_IMASK_RTOUT` writer - Enable UARTOUT Receive Time-Out Interrupt."] pub type INT_EVENT0_IMASK_RTOUT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_RTOUT_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_RTOUT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_rtout_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_rtout_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_SET) } } # [doc = "Field `INT_EVENT0_IMASK_FRMERR` reader - Enable UART Framing Error Interrupt."] pub type INT_EVENT0_IMASK_FRMERR_R = crate :: BitReader < INT_EVENT0_IMASK_FRMERR_A > ; # [doc = "Enable UART Framing Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_FRMERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_FRMERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_FRMERR_SET = 1 , } impl From < INT_EVENT0_IMASK_FRMERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_FRMERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_FRMERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_FRMERR_A { match self . bits { false => INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_CLR , true => INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_frmerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_frmerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_FRMERR` writer - Enable UART Framing Error Interrupt."] pub type INT_EVENT0_IMASK_FRMERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_FRMERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_FRMERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_frmerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_frmerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_SET) } } # [doc = "Field `INT_EVENT0_IMASK_PARERR` reader - Enable UART Parity Error Interrupt."] pub type INT_EVENT0_IMASK_PARERR_R = crate :: BitReader < INT_EVENT0_IMASK_PARERR_A > ; # [doc = "Enable UART Parity Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_PARERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_PARERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_PARERR_SET = 1 , } impl From < INT_EVENT0_IMASK_PARERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_PARERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_PARERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_PARERR_A { match self . bits { false => INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_CLR , true => INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_parerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_parerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_PARERR` writer - Enable UART Parity Error Interrupt."] pub type INT_EVENT0_IMASK_PARERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_PARERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_PARERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_parerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_parerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_SET) } } # [doc = "Field `INT_EVENT0_IMASK_BRKERR` reader - Enable UART Break Error Interrupt."] pub type INT_EVENT0_IMASK_BRKERR_R = crate :: BitReader < INT_EVENT0_IMASK_BRKERR_A > ; # [doc = "Enable UART Break Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_BRKERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_BRKERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_BRKERR_SET = 1 , } impl From < INT_EVENT0_IMASK_BRKERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_BRKERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_BRKERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_BRKERR_A { match self . bits { false => INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_CLR , true => INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_brkerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_brkerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_BRKERR` writer - Enable UART Break Error Interrupt."] pub type INT_EVENT0_IMASK_BRKERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_BRKERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_BRKERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_brkerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_brkerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_SET) } } # [doc = "Field `INT_EVENT0_IMASK_OVRERR` reader - Enable UART Receive Overrun Error Interrupt."] pub type INT_EVENT0_IMASK_OVRERR_R = crate :: BitReader < INT_EVENT0_IMASK_OVRERR_A > ; # [doc = "Enable UART Receive Overrun Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_OVRERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_OVRERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_OVRERR_SET = 1 , } impl From < INT_EVENT0_IMASK_OVRERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_OVRERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_OVRERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_OVRERR_A { match self . bits { false => INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_CLR , true => INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_ovrerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_ovrerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_OVRERR` writer - Enable UART Receive Overrun Error Interrupt."] pub type INT_EVENT0_IMASK_OVRERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_OVRERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_OVRERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_ovrerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_ovrerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_SET) } } # [doc = "Field `INT_EVENT0_IMASK_RXNE` reader - Enable Negative Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_IMASK_RXNE_R = crate :: BitReader < INT_EVENT0_IMASK_RXNE_A > ; # [doc = "Enable Negative Edge on UARTxRXD Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_RXNE_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_RXNE_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_RXNE_SET = 1 , } impl From < INT_EVENT0_IMASK_RXNE_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_RXNE_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_RXNE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_RXNE_A { match self . bits { false => INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_CLR , true => INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_rxne_clr (& self) -> bool { * self == INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_rxne_set (& self) -> bool { * self == INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_SET } } # [doc = "Field `INT_EVENT0_IMASK_RXNE` writer - Enable Negative Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_IMASK_RXNE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_RXNE_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_RXNE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_rxne_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_rxne_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_SET) } } # [doc = "Field `INT_EVENT0_IMASK_RXPE` reader - Enable Positive Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_IMASK_RXPE_R = crate :: BitReader < INT_EVENT0_IMASK_RXPE_A > ; # [doc = "Enable Positive Edge on UARTxRXD Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_RXPE_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_RXPE_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_RXPE_SET = 1 , } impl From < INT_EVENT0_IMASK_RXPE_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_RXPE_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_RXPE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_RXPE_A { match self . bits { false => INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_CLR , true => INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_rxpe_clr (& self) -> bool { * self == INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_rxpe_set (& self) -> bool { * self == INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_SET } } # [doc = "Field `INT_EVENT0_IMASK_RXPE` writer - Enable Positive Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_IMASK_RXPE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_RXPE_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_RXPE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_rxpe_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_rxpe_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_SET) } } # [doc = "Field `INT_EVENT0_IMASK_LINC0` reader - Enable LIN Capture 0 / Match Interrupt ."] pub type INT_EVENT0_IMASK_LINC0_R = crate :: BitReader < INT_EVENT0_IMASK_LINC0_A > ; # [doc = "Enable LIN Capture 0 / Match Interrupt .\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_LINC0_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_LINC0_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_LINC0_SET = 1 , } impl From < INT_EVENT0_IMASK_LINC0_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_LINC0_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_LINC0_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_LINC0_A { match self . bits { false => INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_CLR , true => INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_linc0_clr (& self) -> bool { * self == INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_linc0_set (& self) -> bool { * self == INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_SET } } # [doc = "Field `INT_EVENT0_IMASK_LINC0` writer - Enable LIN Capture 0 / Match Interrupt ."] pub type INT_EVENT0_IMASK_LINC0_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_LINC0_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_LINC0_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_linc0_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_linc0_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_SET) } } # [doc = "Field `INT_EVENT0_IMASK_LINC1` reader - Enable LIN Capture 1 Interrupt."] pub type INT_EVENT0_IMASK_LINC1_R = crate :: BitReader < INT_EVENT0_IMASK_LINC1_A > ; # [doc = "Enable LIN Capture 1 Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_LINC1_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_LINC1_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_LINC1_SET = 1 , } impl From < INT_EVENT0_IMASK_LINC1_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_LINC1_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_LINC1_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_LINC1_A { match self . bits { false => INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_CLR , true => INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_linc1_clr (& self) -> bool { * self == INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_linc1_set (& self) -> bool { * self == INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_SET } } # [doc = "Field `INT_EVENT0_IMASK_LINC1` writer - Enable LIN Capture 1 Interrupt."] pub type INT_EVENT0_IMASK_LINC1_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_LINC1_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_LINC1_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_linc1_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_linc1_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_SET) } } # [doc = "Field `INT_EVENT0_IMASK_LINOVF` reader - Enable LIN Hardware Counter Overflow Interrupt."] pub type INT_EVENT0_IMASK_LINOVF_R = crate :: BitReader < INT_EVENT0_IMASK_LINOVF_A > ; # [doc = "Enable LIN Hardware Counter Overflow Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_LINOVF_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_LINOVF_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_LINOVF_SET = 1 , } impl From < INT_EVENT0_IMASK_LINOVF_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_LINOVF_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_LINOVF_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_LINOVF_A { match self . bits { false => INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_CLR , true => INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_linovf_clr (& self) -> bool { * self == INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_linovf_set (& self) -> bool { * self == INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_SET } } # [doc = "Field `INT_EVENT0_IMASK_LINOVF` writer - Enable LIN Hardware Counter Overflow Interrupt."] pub type INT_EVENT0_IMASK_LINOVF_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_LINOVF_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_LINOVF_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_linovf_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_linovf_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_SET) } } # [doc = "Field `INT_EVENT0_IMASK_RXINT` reader - Enable UART Receive Interrupt."] pub type INT_EVENT0_IMASK_RXINT_R = crate :: BitReader < INT_EVENT0_IMASK_RXINT_A > ; # [doc = "Enable UART Receive Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_RXINT_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_RXINT_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_RXINT_SET = 1 , } impl From < INT_EVENT0_IMASK_RXINT_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_RXINT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_RXINT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_RXINT_A { match self . bits { false => INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_CLR , true => INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_rxint_clr (& self) -> bool { * self == INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_rxint_set (& self) -> bool { * self == INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_SET } } # [doc = "Field `INT_EVENT0_IMASK_RXINT` writer - Enable UART Receive Interrupt."] pub type INT_EVENT0_IMASK_RXINT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_RXINT_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_RXINT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_rxint_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_rxint_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_SET) } } # [doc = "Field `INT_EVENT0_IMASK_TXINT` reader - Enable UART Transmit Interrupt."] pub type INT_EVENT0_IMASK_TXINT_R = crate :: BitReader < INT_EVENT0_IMASK_TXINT_A > ; # [doc = "Enable UART Transmit Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_TXINT_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_TXINT_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_TXINT_SET = 1 , } impl From < INT_EVENT0_IMASK_TXINT_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_TXINT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_TXINT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_TXINT_A { match self . bits { false => INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_CLR , true => INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_txint_clr (& self) -> bool { * self == INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_txint_set (& self) -> bool { * self == INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_SET } } # [doc = "Field `INT_EVENT0_IMASK_TXINT` writer - Enable UART Transmit Interrupt."] pub type INT_EVENT0_IMASK_TXINT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_TXINT_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_TXINT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_txint_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_txint_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_SET) } } # [doc = "Field `INT_EVENT0_IMASK_EOT` reader - Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] pub type INT_EVENT0_IMASK_EOT_R = crate :: BitReader < INT_EVENT0_IMASK_EOT_A > ; # [doc = "Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_EOT_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_EOT_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_EOT_SET = 1 , } impl From < INT_EVENT0_IMASK_EOT_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_EOT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_EOT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_EOT_A { match self . bits { false => INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_CLR , true => INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_eot_clr (& self) -> bool { * self == INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_eot_set (& self) -> bool { * self == INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_SET } } # [doc = "Field `INT_EVENT0_IMASK_EOT` writer - Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] pub type INT_EVENT0_IMASK_EOT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_EOT_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_EOT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_eot_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_eot_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_SET) } } # [doc = "Field `INT_EVENT0_IMASK_ADDR_MATCH` reader - Enable Address Match Interrupt."] pub type INT_EVENT0_IMASK_ADDR_MATCH_R = crate :: BitReader < INT_EVENT0_IMASK_ADDR_MATCH_A > ; # [doc = "Enable Address Match Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_ADDR_MATCH_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_ADDR_MATCH_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_ADDR_MATCH_SET = 1 , } impl From < INT_EVENT0_IMASK_ADDR_MATCH_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_ADDR_MATCH_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_ADDR_MATCH_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_ADDR_MATCH_A { match self . bits { false => INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_CLR , true => INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_addr_match_clr (& self) -> bool { * self == INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_addr_match_set (& self) -> bool { * self == INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_SET } } # [doc = "Field `INT_EVENT0_IMASK_ADDR_MATCH` writer - Enable Address Match Interrupt."] pub type INT_EVENT0_IMASK_ADDR_MATCH_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_ADDR_MATCH_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_ADDR_MATCH_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_addr_match_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_addr_match_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_SET) } } # [doc = "Field `INT_EVENT0_IMASK_CTS` reader - Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] pub type INT_EVENT0_IMASK_CTS_R = crate :: BitReader < INT_EVENT0_IMASK_CTS_A > ; # [doc = "Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_CTS_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_CTS_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_CTS_SET = 1 , } impl From < INT_EVENT0_IMASK_CTS_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_CTS_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_CTS_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_CTS_A { match self . bits { false => INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_CLR , true => INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_cts_clr (& self) -> bool { * self == INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_cts_set (& self) -> bool { * self == INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_SET } } # [doc = "Field `INT_EVENT0_IMASK_CTS` writer - Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] pub type INT_EVENT0_IMASK_CTS_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_CTS_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_CTS_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_cts_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_cts_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DMA_DONE_RX` reader - Enable DMA Done on RX Event Channel"] pub type INT_EVENT0_IMASK_DMA_DONE_RX_R = crate :: BitReader < INT_EVENT0_IMASK_DMA_DONE_RX_A > ; # [doc = "Enable DMA Done on RX Event Channel\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DMA_DONE_RX_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DMA_DONE_RX_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DMA_DONE_RX_SET = 1 , } impl From < INT_EVENT0_IMASK_DMA_DONE_RX_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DMA_DONE_RX_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DMA_DONE_RX_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DMA_DONE_RX_A { match self . bits { false => INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_CLR , true => INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dma_done_rx_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dma_done_rx_set (& self) -> bool { * self == INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_SET } } # [doc = "Field `INT_EVENT0_IMASK_DMA_DONE_RX` writer - Enable DMA Done on RX Event Channel"] pub type INT_EVENT0_IMASK_DMA_DONE_RX_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DMA_DONE_RX_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DMA_DONE_RX_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dma_done_rx_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dma_done_rx_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DMA_DONE_TX` reader - Enable DMA Done on TX Event Channel"] pub type INT_EVENT0_IMASK_DMA_DONE_TX_R = crate :: BitReader < INT_EVENT0_IMASK_DMA_DONE_TX_A > ; # [doc = "Enable DMA Done on TX Event Channel\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DMA_DONE_TX_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DMA_DONE_TX_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DMA_DONE_TX_SET = 1 , } impl From < INT_EVENT0_IMASK_DMA_DONE_TX_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DMA_DONE_TX_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DMA_DONE_TX_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DMA_DONE_TX_A { match self . bits { false => INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_CLR , true => INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dma_done_tx_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dma_done_tx_set (& self) -> bool { * self == INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_SET } } # [doc = "Field `INT_EVENT0_IMASK_DMA_DONE_TX` writer - Enable DMA Done on TX Event Channel"] pub type INT_EVENT0_IMASK_DMA_DONE_TX_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DMA_DONE_TX_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DMA_DONE_TX_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dma_done_tx_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dma_done_tx_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_SET) } } # [doc = "Field `INT_EVENT0_IMASK_NERR` reader - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] pub type INT_EVENT0_IMASK_NERR_R = crate :: BitReader < INT_EVENT0_IMASK_NERR_A > ; # [doc = "Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_NERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_NERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_NERR_SET = 1 , } impl From < INT_EVENT0_IMASK_NERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_NERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_NERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_NERR_A { match self . bits { false => INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_CLR , true => INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_nerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_nerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_NERR` writer - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] pub type INT_EVENT0_IMASK_NERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_NERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_NERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_nerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_nerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_SET) } } impl R { # [doc = "Bit 0 - Enable UARTOUT Receive Time-Out Interrupt."] # [inline (always)] pub fn int_event0_imask_rtout (& self) -> INT_EVENT0_IMASK_RTOUT_R { INT_EVENT0_IMASK_RTOUT_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - Enable UART Framing Error Interrupt."] # [inline (always)] pub fn int_event0_imask_frmerr (& self) -> INT_EVENT0_IMASK_FRMERR_R { INT_EVENT0_IMASK_FRMERR_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - Enable UART Parity Error Interrupt."] # [inline (always)] pub fn int_event0_imask_parerr (& self) -> INT_EVENT0_IMASK_PARERR_R { INT_EVENT0_IMASK_PARERR_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - Enable UART Break Error Interrupt."] # [inline (always)] pub fn int_event0_imask_brkerr (& self) -> INT_EVENT0_IMASK_BRKERR_R { INT_EVENT0_IMASK_BRKERR_R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - Enable UART Receive Overrun Error Interrupt."] # [inline (always)] pub fn int_event0_imask_ovrerr (& self) -> INT_EVENT0_IMASK_OVRERR_R { INT_EVENT0_IMASK_OVRERR_R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - Enable Negative Edge on UARTxRXD Interrupt."] # [inline (always)] pub fn int_event0_imask_rxne (& self) -> INT_EVENT0_IMASK_RXNE_R { INT_EVENT0_IMASK_RXNE_R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - Enable Positive Edge on UARTxRXD Interrupt."] # [inline (always)] pub fn int_event0_imask_rxpe (& self) -> INT_EVENT0_IMASK_RXPE_R { INT_EVENT0_IMASK_RXPE_R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - Enable LIN Capture 0 / Match Interrupt ."] # [inline (always)] pub fn int_event0_imask_linc0 (& self) -> INT_EVENT0_IMASK_LINC0_R { INT_EVENT0_IMASK_LINC0_R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - Enable LIN Capture 1 Interrupt."] # [inline (always)] pub fn int_event0_imask_linc1 (& self) -> INT_EVENT0_IMASK_LINC1_R { INT_EVENT0_IMASK_LINC1_R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - Enable LIN Hardware Counter Overflow Interrupt."] # [inline (always)] pub fn int_event0_imask_linovf (& self) -> INT_EVENT0_IMASK_LINOVF_R { INT_EVENT0_IMASK_LINOVF_R :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - Enable UART Receive Interrupt."] # [inline (always)] pub fn int_event0_imask_rxint (& self) -> INT_EVENT0_IMASK_RXINT_R { INT_EVENT0_IMASK_RXINT_R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - Enable UART Transmit Interrupt."] # [inline (always)] pub fn int_event0_imask_txint (& self) -> INT_EVENT0_IMASK_TXINT_R { INT_EVENT0_IMASK_TXINT_R :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] # [inline (always)] pub fn int_event0_imask_eot (& self) -> INT_EVENT0_IMASK_EOT_R { INT_EVENT0_IMASK_EOT_R :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - Enable Address Match Interrupt."] # [inline (always)] pub fn int_event0_imask_addr_match (& self) -> INT_EVENT0_IMASK_ADDR_MATCH_R { INT_EVENT0_IMASK_ADDR_MATCH_R :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 14 - Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] # [inline (always)] pub fn int_event0_imask_cts (& self) -> INT_EVENT0_IMASK_CTS_R { INT_EVENT0_IMASK_CTS_R :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - Enable DMA Done on RX Event Channel"] # [inline (always)] pub fn int_event0_imask_dma_done_rx (& self) -> INT_EVENT0_IMASK_DMA_DONE_RX_R { INT_EVENT0_IMASK_DMA_DONE_RX_R :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bit 16 - Enable DMA Done on TX Event Channel"] # [inline (always)] pub fn int_event0_imask_dma_done_tx (& self) -> INT_EVENT0_IMASK_DMA_DONE_TX_R { INT_EVENT0_IMASK_DMA_DONE_TX_R :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] # [inline (always)] pub fn int_event0_imask_nerr (& self) -> INT_EVENT0_IMASK_NERR_R { INT_EVENT0_IMASK_NERR_R :: new (((self . bits >> 17) & 1) != 0) } } impl W { # [doc = "Bit 0 - Enable UARTOUT Receive Time-Out Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_rtout (& mut self) -> INT_EVENT0_IMASK_RTOUT_W < INT_EVENT0_IMASK_SPEC , 0 > { INT_EVENT0_IMASK_RTOUT_W :: new (self) } # [doc = "Bit 1 - Enable UART Framing Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_frmerr (& mut self) -> INT_EVENT0_IMASK_FRMERR_W < INT_EVENT0_IMASK_SPEC , 1 > { INT_EVENT0_IMASK_FRMERR_W :: new (self) } # [doc = "Bit 2 - Enable UART Parity Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_parerr (& mut self) -> INT_EVENT0_IMASK_PARERR_W <'_, INT_EVENT0_IMASK_SPEC , 2 > { INT_EVENT0_IMASK_PARERR_W :: new (self) } # [doc = "Bit 3 - Enable UART Break Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_brkerr (& mut self) -> INT_EVENT0_IMASK_BRKERR_W < INT_EVENT0_IMASK_SPEC , 3 > { INT_EVENT0_IMASK_BRKERR_W :: new (self) } # [doc = "Bit 4 - Enable UART Receive Overrun Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_ovrerr (& mut self) -> INT_EVENT0_IMASK_OVRERR_W < INT_EVENT0_IMASK_SPEC , 4 > { INT_EVENT0_IMASK_OVRERR_W :: new (self) } # [doc = "Bit 5 - Enable Negative Edge on UARTxRXD Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_rxne (& mut self) -> INT_EVENT0_IMASK_RXNE_W < INT_EVENT0_IMASK_SPEC , 5 > { INT_EVENT0_IMASK_RXNE_W :: new (self) } # [doc = "Bit 6 - Enable Positive Edge on UARTxRXD Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_rxpe (& mut self) -> INT_EVENT0_IMASK_RXPE_W < INT_EVENT0_IMASK_SPEC , 6 > { INT_EVENT0_IMASK_RXPE_W :: new (self) } # [doc = "Bit 7 - Enable LIN Capture 0 / Match Interrupt ."] # [inline (always)] # [must_use] pub fn int_event0_imask_linc0 (& mut self) -> INT_EVENT0_IMASK_LINC0_W < INT_EVENT0_IMASK_SPEC , 7 > { INT_EVENT0_IMASK_LINC0_W :: new (self) } # [doc = "Bit 8 - Enable LIN Capture 1 Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_linc1 (& mut self) -> INT_EVENT0_IMASK_LINC1_W < INT_EVENT0_IMASK_SPEC , 8 > { INT_EVENT0_IMASK_LINC1_W :: new (self) } # [doc = "Bit 9 - Enable LIN Hardware Counter Overflow Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_linovf (& mut self) -> INT_EVENT0_IMASK_LINOVF_W < INT_EVENT0_IMASK_SPEC , 9 > { INT_EVENT0_IMASK_LINOVF_W :: new (self) } # [doc = "Bit 10 - Enable UART Receive Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_rxint (& mut self) -> INT_EVENT0_IMASK_RXINT_W < INT_EVENT0_IMASK_SPEC , 10 > { INT_EVENT0_IMASK_RXINT_W :: new (self) } # [doc = "Bit 11 - Enable UART Transmit Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_txint (& mut self) -> INT_EVENT0_IMASK_TXINT_W < INT_EVENT0_IMASK_SPEC , 11 > { INT_EVENT0_IMASK_TXINT_W :: new (self) } # [doc = "Bit 12 - Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] # [inline (always)] # [must_use] pub fn int_event0_imask_eot (& mut self) -> INT_EVENT0_IMASK_EOT_W < INT_EVENT0_IMASK_SPEC , 12 > { INT_EVENT0_IMASK_EOT_W :: new (self) } # [doc = "Bit 13 - Enable Address Match Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_addr_match (& mut self) -> INT_EVENT0_IMASK_ADDR_MATCH_W < INT_EVENT0_IMASK_SPEC , 13 > { INT_EVENT0_IMASK_ADDR_MATCH_W :: new (self) } # [doc = "Bit 14 - Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] # [inline (always)] # [must_use] pub fn int_event0_imask_cts (& mut self) -> INT_EVENT0_IMASK_CTS_W < INT_EVENT0_IMASK_SPEC , 14 > { INT_EVENT0_IMASK_CTS_W :: new (self) } # [doc = "Bit 15 - Enable DMA Done on RX Event Channel"] # [inline (always)] # [must_use] pub fn int_event0_imask_dma_done_rx (& mut self) -> INT_EVENT0_IMASK_DMA_DONE_RX_W < INT_EVENT0_IMASK_SPEC , 15 > { INT_EVENT0_IMASK_DMA_DONE_RX_W :: new (self) } # [doc = "Bit 16 - Enable DMA Done on TX Event Channel"] # [inline (always)] # [must_use] pub fn int_event0_imask_dma_done_tx (& mut self) -> INT_EVENT0_IMASK_DMA_DONE_TX_W < INT_EVENT0_IMASK_SPEC , 16 > { INT_EVENT0_IMASK_DMA_DONE_TX_W :: new (self) } # [doc = "Bit 17 - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] # [inline (always)] # [must_use] pub fn int_event0_imask_nerr (& mut self) -> INT_EVENT0_IMASK_NERR_W < INT_EVENT0_IMASK_SPEC , 17 > { INT_EVENT0_IMASK_NERR_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Interrupt mask\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_event0_imask::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_event0_imask::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct INT_EVENT0_IMASK_SPEC ; impl crate :: RegisterSpec for INT_EVENT0_IMASK_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`int_event0_imask::R`](R) reader structure"] impl crate :: Readable for INT_EVENT0_IMASK_SPEC { } # [doc = "`write(|w| ..)` method takes [`int_event0_imask::W`](W) writer structure"] impl crate :: Writable for INT_EVENT0_IMASK_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets INT_EVENT0_IMASK to value 0"] impl crate :: Resettable for INT_EVENT0_IMASK_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/i2c1/clkcfg.rs:1:3453 [INFO] [stdout] | [INFO] [stdout] 1 | ... fn clkcfg_blockasync (& mut self) -> CLKCFG_BLOCKASYNC_W < CLKCFG_SPEC , 8 > { CLKCFG_BLOCKASYNC_W :: new (self) } # [doc = "Bits 24:... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `CLKCFG` reader"] pub type R = crate :: R < CLKCFG_SPEC > ; # [doc = "Register `CLKCFG` writer"] pub type W = crate :: W < CLKCFG_SPEC > ; # [doc = "Field `CLKCFG_BLOCKASYNC` reader - Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz"] pub type CLKCFG_BLOCKASYNC_R = crate :: BitReader < CLKCFG_BLOCKASYNC_A > ; # [doc = "Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CLKCFG_BLOCKASYNC_A { # [doc = "0: DISABLE"] CLKCFG_BLOCKASYNC_DISABLE = 0 , # [doc = "1: ENABLE"] CLKCFG_BLOCKASYNC_ENABLE = 1 , } impl From < CLKCFG_BLOCKASYNC_A > for bool { # [inline (always)] fn from (variant : CLKCFG_BLOCKASYNC_A) -> Self { variant as u8 != 0 } } impl CLKCFG_BLOCKASYNC_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CLKCFG_BLOCKASYNC_A { match self . bits { false => CLKCFG_BLOCKASYNC_A :: CLKCFG_BLOCKASYNC_DISABLE , true => CLKCFG_BLOCKASYNC_A :: CLKCFG_BLOCKASYNC_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_clkcfg_blockasync_disable (& self) -> bool { * self == CLKCFG_BLOCKASYNC_A :: CLKCFG_BLOCKASYNC_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_clkcfg_blockasync_enable (& self) -> bool { * self == CLKCFG_BLOCKASYNC_A :: CLKCFG_BLOCKASYNC_ENABLE } } # [doc = "Field `CLKCFG_BLOCKASYNC` writer - Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz"] pub type CLKCFG_BLOCKASYNC_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CLKCFG_BLOCKASYNC_A > ; impl < 'a , REG , const O : u8 > CLKCFG_BLOCKASYNC_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn clkcfg_blockasync_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CLKCFG_BLOCKASYNC_A :: CLKCFG_BLOCKASYNC_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn clkcfg_blockasync_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CLKCFG_BLOCKASYNC_A :: CLKCFG_BLOCKASYNC_ENABLE) } } # [doc = "KEY to Allow State Change -- 0xA9\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum CLKCFG_KEY_AW { # [doc = "169: _UNLOCK_W_"] CLKCFG_KEY_UNLOCK = 169 , } impl From < CLKCFG_KEY_AW > for u8 { # [inline (always)] fn from (variant : CLKCFG_KEY_AW) -> Self { variant as _ } } impl crate :: FieldSpec for CLKCFG_KEY_AW { type Ux = u8 ; } # [doc = "Field `CLKCFG_KEY` writer - KEY to Allow State Change -- 0xA9"] pub type CLKCFG_KEY_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 8 , O , CLKCFG_KEY_AW > ; impl < 'a , REG , const O : u8 > CLKCFG_KEY_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "_UNLOCK_W_"] # [inline (always)] pub fn clkcfg_key_unlock (self) -> & 'a mut crate :: W < REG > { self . variant (CLKCFG_KEY_AW :: CLKCFG_KEY_UNLOCK) } } impl R { # [doc = "Bit 8 - Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz"] # [inline (always)] pub fn clkcfg_blockasync (& self) -> CLKCFG_BLOCKASYNC_R { CLKCFG_BLOCKASYNC_R :: new (((self . bits >> 8) & 1) != 0) } } impl W { # [doc = "Bit 8 - Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz"] # [inline (always)] # [must_use] pub fn clkcfg_blockasync (& mut self) -> CLKCFG_BLOCKASYNC_W <'_, CLKCFG_SPEC , 8 > { CLKCFG_BLOCKASYNC_W :: new (self) } # [doc = "Bits 24:31 - KEY to Allow State Change -- 0xA9"] # [inline (always)] # [must_use] pub fn clkcfg_key (& mut self) -> CLKCFG_KEY_W < CLKCFG_SPEC , 24 > { CLKCFG_KEY_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Peripheral Clock Configuration Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clkcfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clkcfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CLKCFG_SPEC ; impl crate :: RegisterSpec for CLKCFG_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`clkcfg::R`](R) reader structure"] impl crate :: Readable for CLKCFG_SPEC { } # [doc = "`write(|w| ..)` method takes [`clkcfg::W`](W) writer structure"] impl crate :: Writable for CLKCFG_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets CLKCFG to value 0"] impl crate :: Resettable for CLKCFG_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/sysctl/sysosccfg.rs:1:17621 [INFO] [stdout] | [INFO] [stdout] 1 | ...osccfg_use4mhzstop (& mut self) -> SYSOSCCFG_USE4MHZSTOP_W < SYSOSCCFG_SPEC , 8 > { SYSOSCCFG_USE4MHZSTOP_W :: new (self) } # [doc = "... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `SYSOSCCFG` reader"] pub type R = crate :: R < SYSOSCCFG_SPEC > ; # [doc = "Register `SYSOSCCFG` writer"] pub type W = crate :: W < SYSOSCCFG_SPEC > ; # [doc = "Field `SYSOSCCFG_FREQ` reader - Target operating frequency for the system oscillator (SYSOSC)"] pub type SYSOSCCFG_FREQ_R = crate :: FieldReader < SYSOSCCFG_FREQ_A > ; # [doc = "Target operating frequency for the system oscillator (SYSOSC)\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum SYSOSCCFG_FREQ_A { # [doc = "0: SYSOSCBASE"] SYSOSCCFG_FREQ_SYSOSCBASE = 0 , # [doc = "1: SYSOSC4M"] SYSOSCCFG_FREQ_SYSOSC4M = 1 , # [doc = "2: SYSOSCUSER"] SYSOSCCFG_FREQ_SYSOSCUSER = 2 , # [doc = "3: SYSOSCTURBO"] SYSOSCCFG_FREQ_SYSOSCTURBO = 3 , } impl From < SYSOSCCFG_FREQ_A > for u8 { # [inline (always)] fn from (variant : SYSOSCCFG_FREQ_A) -> Self { variant as _ } } impl crate :: FieldSpec for SYSOSCCFG_FREQ_A { type Ux = u8 ; } impl SYSOSCCFG_FREQ_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> SYSOSCCFG_FREQ_A { match self . bits { 0 => SYSOSCCFG_FREQ_A :: SYSOSCCFG_FREQ_SYSOSCBASE , 1 => SYSOSCCFG_FREQ_A :: SYSOSCCFG_FREQ_SYSOSC4M , 2 => SYSOSCCFG_FREQ_A :: SYSOSCCFG_FREQ_SYSOSCUSER , 3 => SYSOSCCFG_FREQ_A :: SYSOSCCFG_FREQ_SYSOSCTURBO , _ => unreachable ! () , } } # [doc = "SYSOSCBASE"] # [inline (always)] pub fn is_sysosccfg_freq_sysoscbase (& self) -> bool { * self == SYSOSCCFG_FREQ_A :: SYSOSCCFG_FREQ_SYSOSCBASE } # [doc = "SYSOSC4M"] # [inline (always)] pub fn is_sysosccfg_freq_sysosc4m (& self) -> bool { * self == SYSOSCCFG_FREQ_A :: SYSOSCCFG_FREQ_SYSOSC4M } # [doc = "SYSOSCUSER"] # [inline (always)] pub fn is_sysosccfg_freq_sysoscuser (& self) -> bool { * self == SYSOSCCFG_FREQ_A :: SYSOSCCFG_FREQ_SYSOSCUSER } # [doc = "SYSOSCTURBO"] # [inline (always)] pub fn is_sysosccfg_freq_sysoscturbo (& self) -> bool { * self == SYSOSCCFG_FREQ_A :: SYSOSCCFG_FREQ_SYSOSCTURBO } } # [doc = "Field `SYSOSCCFG_FREQ` writer - Target operating frequency for the system oscillator (SYSOSC)"] pub type SYSOSCCFG_FREQ_W < 'a , REG , const O : u8 > = crate :: FieldWriterSafe < 'a , REG , 2 , O , SYSOSCCFG_FREQ_A > ; impl < 'a , REG , const O : u8 > SYSOSCCFG_FREQ_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "SYSOSCBASE"] # [inline (always)] pub fn sysosccfg_freq_sysoscbase (self) -> & 'a mut crate :: W < REG > { self . variant (SYSOSCCFG_FREQ_A :: SYSOSCCFG_FREQ_SYSOSCBASE) } # [doc = "SYSOSC4M"] # [inline (always)] pub fn sysosccfg_freq_sysosc4m (self) -> & 'a mut crate :: W < REG > { self . variant (SYSOSCCFG_FREQ_A :: SYSOSCCFG_FREQ_SYSOSC4M) } # [doc = "SYSOSCUSER"] # [inline (always)] pub fn sysosccfg_freq_sysoscuser (self) -> & 'a mut crate :: W < REG > { self . variant (SYSOSCCFG_FREQ_A :: SYSOSCCFG_FREQ_SYSOSCUSER) } # [doc = "SYSOSCTURBO"] # [inline (always)] pub fn sysosccfg_freq_sysoscturbo (self) -> & 'a mut crate :: W < REG > { self . variant (SYSOSCCFG_FREQ_A :: SYSOSCCFG_FREQ_SYSOSCTURBO) } } # [doc = "Field `SYSOSCCFG_USE4MHZSTOP` reader - USE4MHZSTOP sets the SYSOSC stop mode frequency policy. When entering STOP mode, the SYSOSC frequency may be automatically switched to 4MHz to reduce SYSOSC power consumption."] pub type SYSOSCCFG_USE4MHZSTOP_R = crate :: BitReader < SYSOSCCFG_USE4MHZSTOP_A > ; # [doc = "USE4MHZSTOP sets the SYSOSC stop mode frequency policy. When entering STOP mode, the SYSOSC frequency may be automatically switched to 4MHz to reduce SYSOSC power consumption.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum SYSOSCCFG_USE4MHZSTOP_A { # [doc = "0: DISABLE"] SYSOSCCFG_USE4MHZSTOP_DISABLE = 0 , # [doc = "1: ENABLE"] SYSOSCCFG_USE4MHZSTOP_ENABLE = 1 , } impl From < SYSOSCCFG_USE4MHZSTOP_A > for bool { # [inline (always)] fn from (variant : SYSOSCCFG_USE4MHZSTOP_A) -> Self { variant as u8 != 0 } } impl SYSOSCCFG_USE4MHZSTOP_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> SYSOSCCFG_USE4MHZSTOP_A { match self . bits { false => SYSOSCCFG_USE4MHZSTOP_A :: SYSOSCCFG_USE4MHZSTOP_DISABLE , true => SYSOSCCFG_USE4MHZSTOP_A :: SYSOSCCFG_USE4MHZSTOP_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_sysosccfg_use4mhzstop_disable (& self) -> bool { * self == SYSOSCCFG_USE4MHZSTOP_A :: SYSOSCCFG_USE4MHZSTOP_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_sysosccfg_use4mhzstop_enable (& self) -> bool { * self == SYSOSCCFG_USE4MHZSTOP_A :: SYSOSCCFG_USE4MHZSTOP_ENABLE } } # [doc = "Field `SYSOSCCFG_USE4MHZSTOP` writer - USE4MHZSTOP sets the SYSOSC stop mode frequency policy. When entering STOP mode, the SYSOSC frequency may be automatically switched to 4MHz to reduce SYSOSC power consumption."] pub type SYSOSCCFG_USE4MHZSTOP_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , SYSOSCCFG_USE4MHZSTOP_A > ; impl < 'a , REG , const O : u8 > SYSOSCCFG_USE4MHZSTOP_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn sysosccfg_use4mhzstop_disable (self) -> & 'a mut crate :: W < REG > { self . variant (SYSOSCCFG_USE4MHZSTOP_A :: SYSOSCCFG_USE4MHZSTOP_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn sysosccfg_use4mhzstop_enable (self) -> & 'a mut crate :: W < REG > { self . variant (SYSOSCCFG_USE4MHZSTOP_A :: SYSOSCCFG_USE4MHZSTOP_ENABLE) } } # [doc = "Field `SYSOSCCFG_DISABLESTOP` reader - DISABLESTOP sets the SYSOSC stop mode enable/disable policy. When operating in STOP mode, the SYSOSC may be automatically disabled. When set, ULPCLK will run from LFCLK in STOP mode and SYSOSC will be disabled to reduce power consumption."] pub type SYSOSCCFG_DISABLESTOP_R = crate :: BitReader < SYSOSCCFG_DISABLESTOP_A > ; # [doc = "DISABLESTOP sets the SYSOSC stop mode enable/disable policy. When operating in STOP mode, the SYSOSC may be automatically disabled. When set, ULPCLK will run from LFCLK in STOP mode and SYSOSC will be disabled to reduce power consumption.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum SYSOSCCFG_DISABLESTOP_A { # [doc = "0: DISABLE"] SYSOSCCFG_DISABLESTOP_DISABLE = 0 , # [doc = "1: ENABLE"] SYSOSCCFG_DISABLESTOP_ENABLE = 1 , } impl From < SYSOSCCFG_DISABLESTOP_A > for bool { # [inline (always)] fn from (variant : SYSOSCCFG_DISABLESTOP_A) -> Self { variant as u8 != 0 } } impl SYSOSCCFG_DISABLESTOP_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> SYSOSCCFG_DISABLESTOP_A { match self . bits { false => SYSOSCCFG_DISABLESTOP_A :: SYSOSCCFG_DISABLESTOP_DISABLE , true => SYSOSCCFG_DISABLESTOP_A :: SYSOSCCFG_DISABLESTOP_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_sysosccfg_disablestop_disable (& self) -> bool { * self == SYSOSCCFG_DISABLESTOP_A :: SYSOSCCFG_DISABLESTOP_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_sysosccfg_disablestop_enable (& self) -> bool { * self == SYSOSCCFG_DISABLESTOP_A :: SYSOSCCFG_DISABLESTOP_ENABLE } } # [doc = "Field `SYSOSCCFG_DISABLESTOP` writer - DISABLESTOP sets the SYSOSC stop mode enable/disable policy. When operating in STOP mode, the SYSOSC may be automatically disabled. When set, ULPCLK will run from LFCLK in STOP mode and SYSOSC will be disabled to reduce power consumption."] pub type SYSOSCCFG_DISABLESTOP_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , SYSOSCCFG_DISABLESTOP_A > ; impl < 'a , REG , const O : u8 > SYSOSCCFG_DISABLESTOP_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn sysosccfg_disablestop_disable (self) -> & 'a mut crate :: W < REG > { self . variant (SYSOSCCFG_DISABLESTOP_A :: SYSOSCCFG_DISABLESTOP_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn sysosccfg_disablestop_enable (self) -> & 'a mut crate :: W < REG > { self . variant (SYSOSCCFG_DISABLESTOP_A :: SYSOSCCFG_DISABLESTOP_ENABLE) } } # [doc = "Field `SYSOSCCFG_DISABLE` reader - DISABLE sets the SYSOSC enable/disable policy. SYSOSC may be powered off in RUN, SLEEP, and STOP modes to reduce power consumption. When SYSOSC is disabled, MCLK and ULPCLK are sourced from LFCLK."] pub type SYSOSCCFG_DISABLE_R = crate :: BitReader < SYSOSCCFG_DISABLE_A > ; # [doc = "DISABLE sets the SYSOSC enable/disable policy. SYSOSC may be powered off in RUN, SLEEP, and STOP modes to reduce power consumption. When SYSOSC is disabled, MCLK and ULPCLK are sourced from LFCLK.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum SYSOSCCFG_DISABLE_A { # [doc = "0: DISABLE"] SYSOSCCFG_DISABLE_DISABLE = 0 , # [doc = "1: ENABLE"] SYSOSCCFG_DISABLE_ENABLE = 1 , } impl From < SYSOSCCFG_DISABLE_A > for bool { # [inline (always)] fn from (variant : SYSOSCCFG_DISABLE_A) -> Self { variant as u8 != 0 } } impl SYSOSCCFG_DISABLE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> SYSOSCCFG_DISABLE_A { match self . bits { false => SYSOSCCFG_DISABLE_A :: SYSOSCCFG_DISABLE_DISABLE , true => SYSOSCCFG_DISABLE_A :: SYSOSCCFG_DISABLE_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_sysosccfg_disable_disable (& self) -> bool { * self == SYSOSCCFG_DISABLE_A :: SYSOSCCFG_DISABLE_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_sysosccfg_disable_enable (& self) -> bool { * self == SYSOSCCFG_DISABLE_A :: SYSOSCCFG_DISABLE_ENABLE } } # [doc = "Field `SYSOSCCFG_DISABLE` writer - DISABLE sets the SYSOSC enable/disable policy. SYSOSC may be powered off in RUN, SLEEP, and STOP modes to reduce power consumption. When SYSOSC is disabled, MCLK and ULPCLK are sourced from LFCLK."] pub type SYSOSCCFG_DISABLE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , SYSOSCCFG_DISABLE_A > ; impl < 'a , REG , const O : u8 > SYSOSCCFG_DISABLE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn sysosccfg_disable_disable (self) -> & 'a mut crate :: W < REG > { self . variant (SYSOSCCFG_DISABLE_A :: SYSOSCCFG_DISABLE_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn sysosccfg_disable_enable (self) -> & 'a mut crate :: W < REG > { self . variant (SYSOSCCFG_DISABLE_A :: SYSOSCCFG_DISABLE_ENABLE) } } # [doc = "Field `SYSOSCCFG_BLOCKASYNCALL` reader - BLOCKASYNCALL may be used to mask block all asynchronous fast clock requests, preventing hardware from dynamically changing the active clock configuration when operating in a given mode."] pub type SYSOSCCFG_BLOCKASYNCALL_R = crate :: BitReader < SYSOSCCFG_BLOCKASYNCALL_A > ; # [doc = "BLOCKASYNCALL may be used to mask block all asynchronous fast clock requests, preventing hardware from dynamically changing the active clock configuration when operating in a given mode.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum SYSOSCCFG_BLOCKASYNCALL_A { # [doc = "0: DISABLE"] SYSOSCCFG_BLOCKASYNCALL_DISABLE = 0 , # [doc = "1: ENABLE"] SYSOSCCFG_BLOCKASYNCALL_ENABLE = 1 , } impl From < SYSOSCCFG_BLOCKASYNCALL_A > for bool { # [inline (always)] fn from (variant : SYSOSCCFG_BLOCKASYNCALL_A) -> Self { variant as u8 != 0 } } impl SYSOSCCFG_BLOCKASYNCALL_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> SYSOSCCFG_BLOCKASYNCALL_A { match self . bits { false => SYSOSCCFG_BLOCKASYNCALL_A :: SYSOSCCFG_BLOCKASYNCALL_DISABLE , true => SYSOSCCFG_BLOCKASYNCALL_A :: SYSOSCCFG_BLOCKASYNCALL_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_sysosccfg_blockasyncall_disable (& self) -> bool { * self == SYSOSCCFG_BLOCKASYNCALL_A :: SYSOSCCFG_BLOCKASYNCALL_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_sysosccfg_blockasyncall_enable (& self) -> bool { * self == SYSOSCCFG_BLOCKASYNCALL_A :: SYSOSCCFG_BLOCKASYNCALL_ENABLE } } # [doc = "Field `SYSOSCCFG_BLOCKASYNCALL` writer - BLOCKASYNCALL may be used to mask block all asynchronous fast clock requests, preventing hardware from dynamically changing the active clock configuration when operating in a given mode."] pub type SYSOSCCFG_BLOCKASYNCALL_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , SYSOSCCFG_BLOCKASYNCALL_A > ; impl < 'a , REG , const O : u8 > SYSOSCCFG_BLOCKASYNCALL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn sysosccfg_blockasyncall_disable (self) -> & 'a mut crate :: W < REG > { self . variant (SYSOSCCFG_BLOCKASYNCALL_A :: SYSOSCCFG_BLOCKASYNCALL_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn sysosccfg_blockasyncall_enable (self) -> & 'a mut crate :: W < REG > { self . variant (SYSOSCCFG_BLOCKASYNCALL_A :: SYSOSCCFG_BLOCKASYNCALL_ENABLE) } } # [doc = "Field `SYSOSCCFG_FASTCPUEVENT` reader - FASTCPUEVENT may be used to assert a fast clock request when an interrupt is asserted to the CPU, reducing interrupt latency."] pub type SYSOSCCFG_FASTCPUEVENT_R = crate :: BitReader < SYSOSCCFG_FASTCPUEVENT_A > ; # [doc = "FASTCPUEVENT may be used to assert a fast clock request when an interrupt is asserted to the CPU, reducing interrupt latency.\n\nValue on reset: 1"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum SYSOSCCFG_FASTCPUEVENT_A { # [doc = "0: DISABLE"] SYSOSCCFG_FASTCPUEVENT_DISABLE = 0 , # [doc = "1: ENABLE"] SYSOSCCFG_FASTCPUEVENT_ENABLE = 1 , } impl From < SYSOSCCFG_FASTCPUEVENT_A > for bool { # [inline (always)] fn from (variant : SYSOSCCFG_FASTCPUEVENT_A) -> Self { variant as u8 != 0 } } impl SYSOSCCFG_FASTCPUEVENT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> SYSOSCCFG_FASTCPUEVENT_A { match self . bits { false => SYSOSCCFG_FASTCPUEVENT_A :: SYSOSCCFG_FASTCPUEVENT_DISABLE , true => SYSOSCCFG_FASTCPUEVENT_A :: SYSOSCCFG_FASTCPUEVENT_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_sysosccfg_fastcpuevent_disable (& self) -> bool { * self == SYSOSCCFG_FASTCPUEVENT_A :: SYSOSCCFG_FASTCPUEVENT_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_sysosccfg_fastcpuevent_enable (& self) -> bool { * self == SYSOSCCFG_FASTCPUEVENT_A :: SYSOSCCFG_FASTCPUEVENT_ENABLE } } # [doc = "Field `SYSOSCCFG_FASTCPUEVENT` writer - FASTCPUEVENT may be used to assert a fast clock request when an interrupt is asserted to the CPU, reducing interrupt latency."] pub type SYSOSCCFG_FASTCPUEVENT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , SYSOSCCFG_FASTCPUEVENT_A > ; impl < 'a , REG , const O : u8 > SYSOSCCFG_FASTCPUEVENT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn sysosccfg_fastcpuevent_disable (self) -> & 'a mut crate :: W < REG > { self . variant (SYSOSCCFG_FASTCPUEVENT_A :: SYSOSCCFG_FASTCPUEVENT_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn sysosccfg_fastcpuevent_enable (self) -> & 'a mut crate :: W < REG > { self . variant (SYSOSCCFG_FASTCPUEVENT_A :: SYSOSCCFG_FASTCPUEVENT_ENABLE) } } impl R { # [doc = "Bits 0:1 - Target operating frequency for the system oscillator (SYSOSC)"] # [inline (always)] pub fn sysosccfg_freq (& self) -> SYSOSCCFG_FREQ_R { SYSOSCCFG_FREQ_R :: new ((self . bits & 3) as u8) } # [doc = "Bit 8 - USE4MHZSTOP sets the SYSOSC stop mode frequency policy. When entering STOP mode, the SYSOSC frequency may be automatically switched to 4MHz to reduce SYSOSC power consumption."] # [inline (always)] pub fn sysosccfg_use4mhzstop (& self) -> SYSOSCCFG_USE4MHZSTOP_R { SYSOSCCFG_USE4MHZSTOP_R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - DISABLESTOP sets the SYSOSC stop mode enable/disable policy. When operating in STOP mode, the SYSOSC may be automatically disabled. When set, ULPCLK will run from LFCLK in STOP mode and SYSOSC will be disabled to reduce power consumption."] # [inline (always)] pub fn sysosccfg_disablestop (& self) -> SYSOSCCFG_DISABLESTOP_R { SYSOSCCFG_DISABLESTOP_R :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - DISABLE sets the SYSOSC enable/disable policy. SYSOSC may be powered off in RUN, SLEEP, and STOP modes to reduce power consumption. When SYSOSC is disabled, MCLK and ULPCLK are sourced from LFCLK."] # [inline (always)] pub fn sysosccfg_disable (& self) -> SYSOSCCFG_DISABLE_R { SYSOSCCFG_DISABLE_R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 16 - BLOCKASYNCALL may be used to mask block all asynchronous fast clock requests, preventing hardware from dynamically changing the active clock configuration when operating in a given mode."] # [inline (always)] pub fn sysosccfg_blockasyncall (& self) -> SYSOSCCFG_BLOCKASYNCALL_R { SYSOSCCFG_BLOCKASYNCALL_R :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - FASTCPUEVENT may be used to assert a fast clock request when an interrupt is asserted to the CPU, reducing interrupt latency."] # [inline (always)] pub fn sysosccfg_fastcpuevent (& self) -> SYSOSCCFG_FASTCPUEVENT_R { SYSOSCCFG_FASTCPUEVENT_R :: new (((self . bits >> 17) & 1) != 0) } } impl W { # [doc = "Bits 0:1 - Target operating frequency for the system oscillator (SYSOSC)"] # [inline (always)] # [must_use] pub fn sysosccfg_freq (& mut self) -> SYSOSCCFG_FREQ_W < SYSOSCCFG_SPEC , 0 > { SYSOSCCFG_FREQ_W :: new (self) } # [doc = "Bit 8 - USE4MHZSTOP sets the SYSOSC stop mode frequency policy. When entering STOP mode, the SYSOSC frequency may be automatically switched to 4MHz to reduce SYSOSC power consumption."] # [inline (always)] # [must_use] pub fn sysosccfg_use4mhzstop (& mut self) -> SYSOSCCFG_USE4MHZSTOP_W <'_, SYSOSCCFG_SPEC , 8 > { SYSOSCCFG_USE4MHZSTOP_W :: new (self) } # [doc = "Bit 9 - DISABLESTOP sets the SYSOSC stop mode enable/disable policy. When operating in STOP mode, the SYSOSC may be automatically disabled. When set, ULPCLK will run from LFCLK in STOP mode and SYSOSC will be disabled to reduce power consumption."] # [inline (always)] # [must_use] pub fn sysosccfg_disablestop (& mut self) -> SYSOSCCFG_DISABLESTOP_W < SYSOSCCFG_SPEC , 9 > { SYSOSCCFG_DISABLESTOP_W :: new (self) } # [doc = "Bit 10 - DISABLE sets the SYSOSC enable/disable policy. SYSOSC may be powered off in RUN, SLEEP, and STOP modes to reduce power consumption. When SYSOSC is disabled, MCLK and ULPCLK are sourced from LFCLK."] # [inline (always)] # [must_use] pub fn sysosccfg_disable (& mut self) -> SYSOSCCFG_DISABLE_W < SYSOSCCFG_SPEC , 10 > { SYSOSCCFG_DISABLE_W :: new (self) } # [doc = "Bit 16 - BLOCKASYNCALL may be used to mask block all asynchronous fast clock requests, preventing hardware from dynamically changing the active clock configuration when operating in a given mode."] # [inline (always)] # [must_use] pub fn sysosccfg_blockasyncall (& mut self) -> SYSOSCCFG_BLOCKASYNCALL_W < SYSOSCCFG_SPEC , 16 > { SYSOSCCFG_BLOCKASYNCALL_W :: new (self) } # [doc = "Bit 17 - FASTCPUEVENT may be used to assert a fast clock request when an interrupt is asserted to the CPU, reducing interrupt latency."] # [inline (always)] # [must_use] pub fn sysosccfg_fastcpuevent (& mut self) -> SYSOSCCFG_FASTCPUEVENT_W < SYSOSCCFG_SPEC , 17 > { SYSOSCCFG_FASTCPUEVENT_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "SYSOSC configuration\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sysosccfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sysosccfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct SYSOSCCFG_SPEC ; impl crate :: RegisterSpec for SYSOSCCFG_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`sysosccfg::R`](R) reader structure"] impl crate :: Readable for SYSOSCCFG_SPEC { } # [doc = "`write(|w| ..)` method takes [`sysosccfg::W`](W) writer structure"] impl crate :: Writable for SYSOSCCFG_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets SYSOSCCFG to value 0x0002_0000"] impl crate :: Resettable for SYSOSCCFG_SPEC { const RESET_VALUE : Self :: Ux = 0x0002_0000 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/opa0/cfg.rs:1:17222 [INFO] [stdout] | [INFO] [stdout] 1 | ... [must_use] pub fn cfg_nsel (& mut self) -> CFG_NSEL_W < CFG_SPEC , 7 > { CFG_NSEL_W :: new (self) } # [doc = "Bits 10:12 - MSEL Mux s... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `CFG` reader"] pub type R = crate :: R < CFG_SPEC > ; # [doc = "Register `CFG` writer"] pub type W = crate :: W < CFG_SPEC > ; # [doc = "Field `CFG_CHOP` reader - Chopping enable."] pub type CFG_CHOP_R = crate :: FieldReader < CFG_CHOP_A > ; # [doc = "Chopping enable.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum CFG_CHOP_A { # [doc = "0: OFF"] CFG_CHOP_OFF = 0 , # [doc = "1: ON"] CFG_CHOP_ON = 1 , # [doc = "2: AVGON"] CFG_CHOP_AVGON = 2 , } impl From < CFG_CHOP_A > for u8 { # [inline (always)] fn from (variant : CFG_CHOP_A) -> Self { variant as _ } } impl crate :: FieldSpec for CFG_CHOP_A { type Ux = u8 ; } impl CFG_CHOP_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < CFG_CHOP_A > { match self . bits { 0 => Some (CFG_CHOP_A :: CFG_CHOP_OFF) , 1 => Some (CFG_CHOP_A :: CFG_CHOP_ON) , 2 => Some (CFG_CHOP_A :: CFG_CHOP_AVGON) , _ => None , } } # [doc = "OFF"] # [inline (always)] pub fn is_cfg_chop_off (& self) -> bool { * self == CFG_CHOP_A :: CFG_CHOP_OFF } # [doc = "ON"] # [inline (always)] pub fn is_cfg_chop_on (& self) -> bool { * self == CFG_CHOP_A :: CFG_CHOP_ON } # [doc = "AVGON"] # [inline (always)] pub fn is_cfg_chop_avgon (& self) -> bool { * self == CFG_CHOP_A :: CFG_CHOP_AVGON } } # [doc = "Field `CFG_CHOP` writer - Chopping enable."] pub type CFG_CHOP_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 2 , O , CFG_CHOP_A > ; impl < 'a , REG , const O : u8 > CFG_CHOP_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "OFF"] # [inline (always)] pub fn cfg_chop_off (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_CHOP_A :: CFG_CHOP_OFF) } # [doc = "ON"] # [inline (always)] pub fn cfg_chop_on (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_CHOP_A :: CFG_CHOP_ON) } # [doc = "AVGON"] # [inline (always)] pub fn cfg_chop_avgon (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_CHOP_A :: CFG_CHOP_AVGON) } } # [doc = "Field `CFG_OUTPIN` reader - Enable output pin"] pub type CFG_OUTPIN_R = crate :: BitReader < CFG_OUTPIN_A > ; # [doc = "Enable output pin\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CFG_OUTPIN_A { # [doc = "0: DISABLED"] CFG_OUTPIN_DISABLED = 0 , # [doc = "1: ENABLED"] CFG_OUTPIN_ENABLED = 1 , } impl From < CFG_OUTPIN_A > for bool { # [inline (always)] fn from (variant : CFG_OUTPIN_A) -> Self { variant as u8 != 0 } } impl CFG_OUTPIN_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CFG_OUTPIN_A { match self . bits { false => CFG_OUTPIN_A :: CFG_OUTPIN_DISABLED , true => CFG_OUTPIN_A :: CFG_OUTPIN_ENABLED , } } # [doc = "DISABLED"] # [inline (always)] pub fn is_cfg_outpin_disabled (& self) -> bool { * self == CFG_OUTPIN_A :: CFG_OUTPIN_DISABLED } # [doc = "ENABLED"] # [inline (always)] pub fn is_cfg_outpin_enabled (& self) -> bool { * self == CFG_OUTPIN_A :: CFG_OUTPIN_ENABLED } } # [doc = "Field `CFG_OUTPIN` writer - Enable output pin"] pub type CFG_OUTPIN_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CFG_OUTPIN_A > ; impl < 'a , REG , const O : u8 > CFG_OUTPIN_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLED"] # [inline (always)] pub fn cfg_outpin_disabled (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_OUTPIN_A :: CFG_OUTPIN_DISABLED) } # [doc = "ENABLED"] # [inline (always)] pub fn cfg_outpin_enabled (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_OUTPIN_A :: CFG_OUTPIN_ENABLED) } } # [doc = "Field `CFG_PSEL` reader - Positive OA input selection. Please refer to the device specific datasheet for exact channels available."] pub type CFG_PSEL_R = crate :: FieldReader < CFG_PSEL_A > ; # [doc = "Positive OA input selection. Please refer to the device specific datasheet for exact channels available.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum CFG_PSEL_A { # [doc = "0: NC"] CFG_PSEL_NC = 0 , # [doc = "1: EXTPIN0"] CFG_PSEL_EXTPIN0 = 1 , # [doc = "2: EXTPIN1"] CFG_PSEL_EXTPIN1 = 2 , # [doc = "3: DAC12OUT"] CFG_PSEL_DAC12OUT = 3 , # [doc = "4: DAC8OUT"] CFG_PSEL_DAC8OUT = 4 , # [doc = "5: VREF"] CFG_PSEL_VREF = 5 , # [doc = "6: OANM1RTOP"] CFG_PSEL_OANM1RTOP = 6 , # [doc = "7: GPAMP_OUT_INT"] CFG_PSEL_GPAMP_OUT_INT = 7 , # [doc = "8: VSS"] CFG_PSEL_VSS = 8 , } impl From < CFG_PSEL_A > for u8 { # [inline (always)] fn from (variant : CFG_PSEL_A) -> Self { variant as _ } } impl crate :: FieldSpec for CFG_PSEL_A { type Ux = u8 ; } impl CFG_PSEL_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < CFG_PSEL_A > { match self . bits { 0 => Some (CFG_PSEL_A :: CFG_PSEL_NC) , 1 => Some (CFG_PSEL_A :: CFG_PSEL_EXTPIN0) , 2 => Some (CFG_PSEL_A :: CFG_PSEL_EXTPIN1) , 3 => Some (CFG_PSEL_A :: CFG_PSEL_DAC12OUT) , 4 => Some (CFG_PSEL_A :: CFG_PSEL_DAC8OUT) , 5 => Some (CFG_PSEL_A :: CFG_PSEL_VREF) , 6 => Some (CFG_PSEL_A :: CFG_PSEL_OANM1RTOP) , 7 => Some (CFG_PSEL_A :: CFG_PSEL_GPAMP_OUT_INT) , 8 => Some (CFG_PSEL_A :: CFG_PSEL_VSS) , _ => None , } } # [doc = "NC"] # [inline (always)] pub fn is_cfg_psel_nc (& self) -> bool { * self == CFG_PSEL_A :: CFG_PSEL_NC } # [doc = "EXTPIN0"] # [inline (always)] pub fn is_cfg_psel_extpin0 (& self) -> bool { * self == CFG_PSEL_A :: CFG_PSEL_EXTPIN0 } # [doc = "EXTPIN1"] # [inline (always)] pub fn is_cfg_psel_extpin1 (& self) -> bool { * self == CFG_PSEL_A :: CFG_PSEL_EXTPIN1 } # [doc = "DAC12OUT"] # [inline (always)] pub fn is_cfg_psel_dac12out (& self) -> bool { * self == CFG_PSEL_A :: CFG_PSEL_DAC12OUT } # [doc = "DAC8OUT"] # [inline (always)] pub fn is_cfg_psel_dac8out (& self) -> bool { * self == CFG_PSEL_A :: CFG_PSEL_DAC8OUT } # [doc = "VREF"] # [inline (always)] pub fn is_cfg_psel_vref (& self) -> bool { * self == CFG_PSEL_A :: CFG_PSEL_VREF } # [doc = "OANM1RTOP"] # [inline (always)] pub fn is_cfg_psel_oanm1rtop (& self) -> bool { * self == CFG_PSEL_A :: CFG_PSEL_OANM1RTOP } # [doc = "GPAMP_OUT_INT"] # [inline (always)] pub fn is_cfg_psel_gpamp_out_int (& self) -> bool { * self == CFG_PSEL_A :: CFG_PSEL_GPAMP_OUT_INT } # [doc = "VSS"] # [inline (always)] pub fn is_cfg_psel_vss (& self) -> bool { * self == CFG_PSEL_A :: CFG_PSEL_VSS } } # [doc = "Field `CFG_PSEL` writer - Positive OA input selection. Please refer to the device specific datasheet for exact channels available."] pub type CFG_PSEL_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 4 , O , CFG_PSEL_A > ; impl < 'a , REG , const O : u8 > CFG_PSEL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "NC"] # [inline (always)] pub fn cfg_psel_nc (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_PSEL_A :: CFG_PSEL_NC) } # [doc = "EXTPIN0"] # [inline (always)] pub fn cfg_psel_extpin0 (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_PSEL_A :: CFG_PSEL_EXTPIN0) } # [doc = "EXTPIN1"] # [inline (always)] pub fn cfg_psel_extpin1 (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_PSEL_A :: CFG_PSEL_EXTPIN1) } # [doc = "DAC12OUT"] # [inline (always)] pub fn cfg_psel_dac12out (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_PSEL_A :: CFG_PSEL_DAC12OUT) } # [doc = "DAC8OUT"] # [inline (always)] pub fn cfg_psel_dac8out (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_PSEL_A :: CFG_PSEL_DAC8OUT) } # [doc = "VREF"] # [inline (always)] pub fn cfg_psel_vref (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_PSEL_A :: CFG_PSEL_VREF) } # [doc = "OANM1RTOP"] # [inline (always)] pub fn cfg_psel_oanm1rtop (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_PSEL_A :: CFG_PSEL_OANM1RTOP) } # [doc = "GPAMP_OUT_INT"] # [inline (always)] pub fn cfg_psel_gpamp_out_int (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_PSEL_A :: CFG_PSEL_GPAMP_OUT_INT) } # [doc = "VSS"] # [inline (always)] pub fn cfg_psel_vss (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_PSEL_A :: CFG_PSEL_VSS) } } # [doc = "Field `CFG_NSEL` reader - Negative OA input selection. Please refer to the device specific datasheet for exact channels available."] pub type CFG_NSEL_R = crate :: FieldReader < CFG_NSEL_A > ; # [doc = "Negative OA input selection. Please refer to the device specific datasheet for exact channels available.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum CFG_NSEL_A { # [doc = "0: NC"] CFG_NSEL_NC = 0 , # [doc = "1: EXTPIN0"] CFG_NSEL_EXTPIN0 = 1 , # [doc = "2: EXTPIN1"] CFG_NSEL_EXTPIN1 = 2 , # [doc = "3: OANP1RBOT"] CFG_NSEL_OANP1RBOT = 3 , # [doc = "4: OANRTAP"] CFG_NSEL_OANRTAP = 4 , # [doc = "5: OANRTOP"] CFG_NSEL_OANRTOP = 5 , # [doc = "6: SPARE"] CFG_NSEL_SPARE = 6 , } impl From < CFG_NSEL_A > for u8 { # [inline (always)] fn from (variant : CFG_NSEL_A) -> Self { variant as _ } } impl crate :: FieldSpec for CFG_NSEL_A { type Ux = u8 ; } impl CFG_NSEL_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < CFG_NSEL_A > { match self . bits { 0 => Some (CFG_NSEL_A :: CFG_NSEL_NC) , 1 => Some (CFG_NSEL_A :: CFG_NSEL_EXTPIN0) , 2 => Some (CFG_NSEL_A :: CFG_NSEL_EXTPIN1) , 3 => Some (CFG_NSEL_A :: CFG_NSEL_OANP1RBOT) , 4 => Some (CFG_NSEL_A :: CFG_NSEL_OANRTAP) , 5 => Some (CFG_NSEL_A :: CFG_NSEL_OANRTOP) , 6 => Some (CFG_NSEL_A :: CFG_NSEL_SPARE) , _ => None , } } # [doc = "NC"] # [inline (always)] pub fn is_cfg_nsel_nc (& self) -> bool { * self == CFG_NSEL_A :: CFG_NSEL_NC } # [doc = "EXTPIN0"] # [inline (always)] pub fn is_cfg_nsel_extpin0 (& self) -> bool { * self == CFG_NSEL_A :: CFG_NSEL_EXTPIN0 } # [doc = "EXTPIN1"] # [inline (always)] pub fn is_cfg_nsel_extpin1 (& self) -> bool { * self == CFG_NSEL_A :: CFG_NSEL_EXTPIN1 } # [doc = "OANP1RBOT"] # [inline (always)] pub fn is_cfg_nsel_oanp1rbot (& self) -> bool { * self == CFG_NSEL_A :: CFG_NSEL_OANP1RBOT } # [doc = "OANRTAP"] # [inline (always)] pub fn is_cfg_nsel_oanrtap (& self) -> bool { * self == CFG_NSEL_A :: CFG_NSEL_OANRTAP } # [doc = "OANRTOP"] # [inline (always)] pub fn is_cfg_nsel_oanrtop (& self) -> bool { * self == CFG_NSEL_A :: CFG_NSEL_OANRTOP } # [doc = "SPARE"] # [inline (always)] pub fn is_cfg_nsel_spare (& self) -> bool { * self == CFG_NSEL_A :: CFG_NSEL_SPARE } } # [doc = "Field `CFG_NSEL` writer - Negative OA input selection. Please refer to the device specific datasheet for exact channels available."] pub type CFG_NSEL_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 3 , O , CFG_NSEL_A > ; impl < 'a , REG , const O : u8 > CFG_NSEL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "NC"] # [inline (always)] pub fn cfg_nsel_nc (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_NSEL_A :: CFG_NSEL_NC) } # [doc = "EXTPIN0"] # [inline (always)] pub fn cfg_nsel_extpin0 (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_NSEL_A :: CFG_NSEL_EXTPIN0) } # [doc = "EXTPIN1"] # [inline (always)] pub fn cfg_nsel_extpin1 (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_NSEL_A :: CFG_NSEL_EXTPIN1) } # [doc = "OANP1RBOT"] # [inline (always)] pub fn cfg_nsel_oanp1rbot (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_NSEL_A :: CFG_NSEL_OANP1RBOT) } # [doc = "OANRTAP"] # [inline (always)] pub fn cfg_nsel_oanrtap (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_NSEL_A :: CFG_NSEL_OANRTAP) } # [doc = "OANRTOP"] # [inline (always)] pub fn cfg_nsel_oanrtop (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_NSEL_A :: CFG_NSEL_OANRTOP) } # [doc = "SPARE"] # [inline (always)] pub fn cfg_nsel_spare (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_NSEL_A :: CFG_NSEL_SPARE) } } # [doc = "Field `CFG_MSEL` reader - MSEL Mux selection. Please refer to the device specific datasheet for exact channels available."] pub type CFG_MSEL_R = crate :: FieldReader < CFG_MSEL_A > ; # [doc = "MSEL Mux selection. Please refer to the device specific datasheet for exact channels available.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum CFG_MSEL_A { # [doc = "0: NC"] CFG_MSEL_NC = 0 , # [doc = "1: EXTNPIN1"] CFG_MSEL_EXTNPIN1 = 1 , # [doc = "2: VSS"] CFG_MSEL_VSS = 2 , # [doc = "3: DAC12OUT"] CFG_MSEL_DAC12OUT = 3 , # [doc = "4: OANM1RTOP"] CFG_MSEL_OANM1RTOP = 4 , } impl From < CFG_MSEL_A > for u8 { # [inline (always)] fn from (variant : CFG_MSEL_A) -> Self { variant as _ } } impl crate :: FieldSpec for CFG_MSEL_A { type Ux = u8 ; } impl CFG_MSEL_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < CFG_MSEL_A > { match self . bits { 0 => Some (CFG_MSEL_A :: CFG_MSEL_NC) , 1 => Some (CFG_MSEL_A :: CFG_MSEL_EXTNPIN1) , 2 => Some (CFG_MSEL_A :: CFG_MSEL_VSS) , 3 => Some (CFG_MSEL_A :: CFG_MSEL_DAC12OUT) , 4 => Some (CFG_MSEL_A :: CFG_MSEL_OANM1RTOP) , _ => None , } } # [doc = "NC"] # [inline (always)] pub fn is_cfg_msel_nc (& self) -> bool { * self == CFG_MSEL_A :: CFG_MSEL_NC } # [doc = "EXTNPIN1"] # [inline (always)] pub fn is_cfg_msel_extnpin1 (& self) -> bool { * self == CFG_MSEL_A :: CFG_MSEL_EXTNPIN1 } # [doc = "VSS"] # [inline (always)] pub fn is_cfg_msel_vss (& self) -> bool { * self == CFG_MSEL_A :: CFG_MSEL_VSS } # [doc = "DAC12OUT"] # [inline (always)] pub fn is_cfg_msel_dac12out (& self) -> bool { * self == CFG_MSEL_A :: CFG_MSEL_DAC12OUT } # [doc = "OANM1RTOP"] # [inline (always)] pub fn is_cfg_msel_oanm1rtop (& self) -> bool { * self == CFG_MSEL_A :: CFG_MSEL_OANM1RTOP } } # [doc = "Field `CFG_MSEL` writer - MSEL Mux selection. Please refer to the device specific datasheet for exact channels available."] pub type CFG_MSEL_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 3 , O , CFG_MSEL_A > ; impl < 'a , REG , const O : u8 > CFG_MSEL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "NC"] # [inline (always)] pub fn cfg_msel_nc (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_MSEL_A :: CFG_MSEL_NC) } # [doc = "EXTNPIN1"] # [inline (always)] pub fn cfg_msel_extnpin1 (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_MSEL_A :: CFG_MSEL_EXTNPIN1) } # [doc = "VSS"] # [inline (always)] pub fn cfg_msel_vss (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_MSEL_A :: CFG_MSEL_VSS) } # [doc = "DAC12OUT"] # [inline (always)] pub fn cfg_msel_dac12out (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_MSEL_A :: CFG_MSEL_DAC12OUT) } # [doc = "OANM1RTOP"] # [inline (always)] pub fn cfg_msel_oanm1rtop (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_MSEL_A :: CFG_MSEL_OANM1RTOP) } } # [doc = "Field `CFG_GAIN` reader - Gain setting. Refer to TRM for enumeration information."] pub type CFG_GAIN_R = crate :: FieldReader ; # [doc = "Field `CFG_GAIN` writer - Gain setting. Refer to TRM for enumeration information."] pub type CFG_GAIN_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 3 , O > ; impl R { # [doc = "Bits 0:1 - Chopping enable."] # [inline (always)] pub fn cfg_chop (& self) -> CFG_CHOP_R { CFG_CHOP_R :: new ((self . bits & 3) as u8) } # [doc = "Bit 2 - Enable output pin"] # [inline (always)] pub fn cfg_outpin (& self) -> CFG_OUTPIN_R { CFG_OUTPIN_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bits 3:6 - Positive OA input selection. Please refer to the device specific datasheet for exact channels available."] # [inline (always)] pub fn cfg_psel (& self) -> CFG_PSEL_R { CFG_PSEL_R :: new (((self . bits >> 3) & 0x0f) as u8) } # [doc = "Bits 7:9 - Negative OA input selection. Please refer to the device specific datasheet for exact channels available."] # [inline (always)] pub fn cfg_nsel (& self) -> CFG_NSEL_R { CFG_NSEL_R :: new (((self . bits >> 7) & 7) as u8) } # [doc = "Bits 10:12 - MSEL Mux selection. Please refer to the device specific datasheet for exact channels available."] # [inline (always)] pub fn cfg_msel (& self) -> CFG_MSEL_R { CFG_MSEL_R :: new (((self . bits >> 10) & 7) as u8) } # [doc = "Bits 13:15 - Gain setting. Refer to TRM for enumeration information."] # [inline (always)] pub fn cfg_gain (& self) -> CFG_GAIN_R { CFG_GAIN_R :: new (((self . bits >> 13) & 7) as u8) } } impl W { # [doc = "Bits 0:1 - Chopping enable."] # [inline (always)] # [must_use] pub fn cfg_chop (& mut self) -> CFG_CHOP_W < CFG_SPEC , 0 > { CFG_CHOP_W :: new (self) } # [doc = "Bit 2 - Enable output pin"] # [inline (always)] # [must_use] pub fn cfg_outpin (& mut self) -> CFG_OUTPIN_W < CFG_SPEC , 2 > { CFG_OUTPIN_W :: new (self) } # [doc = "Bits 3:6 - Positive OA input selection. Please refer to the device specific datasheet for exact channels available."] # [inline (always)] # [must_use] pub fn cfg_psel (& mut self) -> CFG_PSEL_W < CFG_SPEC , 3 > { CFG_PSEL_W :: new (self) } # [doc = "Bits 7:9 - Negative OA input selection. Please refer to the device specific datasheet for exact channels available."] # [inline (always)] # [must_use] pub fn cfg_nsel (& mut self) -> CFG_NSEL_W <'_, CFG_SPEC , 7 > { CFG_NSEL_W :: new (self) } # [doc = "Bits 10:12 - MSEL Mux selection. Please refer to the device specific datasheet for exact channels available."] # [inline (always)] # [must_use] pub fn cfg_msel (& mut self) -> CFG_MSEL_W < CFG_SPEC , 10 > { CFG_MSEL_W :: new (self) } # [doc = "Bits 13:15 - Gain setting. Refer to TRM for enumeration information."] # [inline (always)] # [must_use] pub fn cfg_gain (& mut self) -> CFG_GAIN_W < CFG_SPEC , 13 > { CFG_GAIN_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Configuration Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CFG_SPEC ; impl crate :: RegisterSpec for CFG_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`cfg::R`](R) reader structure"] impl crate :: Readable for CFG_SPEC { } # [doc = "`write(|w| ..)` method takes [`cfg::W`](W) writer structure"] impl crate :: Writable for CFG_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets CFG to value 0"] impl crate :: Resettable for CFG_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/i2c0/master_i2cpecctl.rs:1:10529 [INFO] [stdout] | [INFO] [stdout] 1 | ...cpecctl_pecen (& mut self) -> MASTER_I2CPECCTL_PECEN_W < MASTER_I2CPECCTL_SPEC , 12 > { MASTER_I2CPECCTL_PECEN_W :: new (self) } # [do... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `MASTER_I2CPECCTL` reader"] pub type R = crate :: R < MASTER_I2CPECCTL_SPEC > ; # [doc = "Register `MASTER_I2CPECCTL` writer"] pub type W = crate :: W < MASTER_I2CPECCTL_SPEC > ; # [doc = "Field `MASTER_I2CPECCTL_PECCNT` reader - PEC Count When this field is non zero, the number of I2C bytes are counted (Note that although the PEC is calculated on the I2C address it is not counted at a byte). When the byte count = PECCNT and the state machine is transmitting, the contents of the LSFR is loaded into the shift register instead of the byte received from the Tx FIFO. When the state machine is receiving, after the last bit of this byte is received the LSFR is checked and if it is non-zero, a PEC RX Error interrupt is generated. The I2C packet must be padded to include the PEC byte for both transmit and receive. In transmit mode the FIFO must be loaded with a dummy PEC byte. In receive mode the PEC byte will be passed to the Rx FIFO. In the normal Master use case, FW would set PECEN=1 and PECCNT=SMB packet length (Not including Slave Address byte, but including the PEC byte). FW would then configure DMA to allow the packet to complete unassisted and write MCTR to initiate the transaction. Note that when the byte count = PEC CNT, the byte count is reset to 0 and multiple PEC calculation can automatically occur within a single I2C transaction. Note that any write to the MASTER_I2CPECCTL Register will clear the current PEC Byte Count in the Master State Machine."] pub type MASTER_I2CPECCTL_PECCNT_R = crate :: FieldReader < u16 > ; # [doc = "Field `MASTER_I2CPECCTL_PECCNT` writer - PEC Count When this field is non zero, the number of I2C bytes are counted (Note that although the PEC is calculated on the I2C address it is not counted at a byte). When the byte count = PECCNT and the state machine is transmitting, the contents of the LSFR is loaded into the shift register instead of the byte received from the Tx FIFO. When the state machine is receiving, after the last bit of this byte is received the LSFR is checked and if it is non-zero, a PEC RX Error interrupt is generated. The I2C packet must be padded to include the PEC byte for both transmit and receive. In transmit mode the FIFO must be loaded with a dummy PEC byte. In receive mode the PEC byte will be passed to the Rx FIFO. In the normal Master use case, FW would set PECEN=1 and PECCNT=SMB packet length (Not including Slave Address byte, but including the PEC byte). FW would then configure DMA to allow the packet to complete unassisted and write MCTR to initiate the transaction. Note that when the byte count = PEC CNT, the byte count is reset to 0 and multiple PEC calculation can automatically occur within a single I2C transaction. Note that any write to the MASTER_I2CPECCTL Register will clear the current PEC Byte Count in the Master State Machine."] pub type MASTER_I2CPECCTL_PECCNT_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 9 , O , u16 > ; # [doc = "Field `MASTER_I2CPECCTL_PECEN` reader - PEC Enable This bit enables the SMB Packet Error Checking (PEC). When enabled the PEC is calculated on all bits accept the Start, Stop, Ack and Nack. The PEC LSFR and the Byte Counter is set to 0 when the State Machine is in the IDLE state, which occur following a Stop or when a timeout occurs. The Counter is also set to 0 after the PEC byte is sent or received. Note that the NACK is automatically send following a PEC byte that results in a PEC error. The PEC Polynomial is x^8 + x^2 + x^1 + 1."] pub type MASTER_I2CPECCTL_PECEN_R = crate :: BitReader < MASTER_I2CPECCTL_PECEN_A > ; # [doc = "PEC Enable This bit enables the SMB Packet Error Checking (PEC). When enabled the PEC is calculated on all bits accept the Start, Stop, Ack and Nack. The PEC LSFR and the Byte Counter is set to 0 when the State Machine is in the IDLE state, which occur following a Stop or when a timeout occurs. The Counter is also set to 0 after the PEC byte is sent or received. Note that the NACK is automatically send following a PEC byte that results in a PEC error. The PEC Polynomial is x^8 + x^2 + x^1 + 1.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum MASTER_I2CPECCTL_PECEN_A { # [doc = "0: DISABLE"] MASTER_I2CPECCTL_PECEN_DISABLE = 0 , # [doc = "1: ENABLE"] MASTER_I2CPECCTL_PECEN_ENABLE = 1 , } impl From < MASTER_I2CPECCTL_PECEN_A > for bool { # [inline (always)] fn from (variant : MASTER_I2CPECCTL_PECEN_A) -> Self { variant as u8 != 0 } } impl MASTER_I2CPECCTL_PECEN_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> MASTER_I2CPECCTL_PECEN_A { match self . bits { false => MASTER_I2CPECCTL_PECEN_A :: MASTER_I2CPECCTL_PECEN_DISABLE , true => MASTER_I2CPECCTL_PECEN_A :: MASTER_I2CPECCTL_PECEN_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_master_i2cpecctl_pecen_disable (& self) -> bool { * self == MASTER_I2CPECCTL_PECEN_A :: MASTER_I2CPECCTL_PECEN_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_master_i2cpecctl_pecen_enable (& self) -> bool { * self == MASTER_I2CPECCTL_PECEN_A :: MASTER_I2CPECCTL_PECEN_ENABLE } } # [doc = "Field `MASTER_I2CPECCTL_PECEN` writer - PEC Enable This bit enables the SMB Packet Error Checking (PEC). When enabled the PEC is calculated on all bits accept the Start, Stop, Ack and Nack. The PEC LSFR and the Byte Counter is set to 0 when the State Machine is in the IDLE state, which occur following a Stop or when a timeout occurs. The Counter is also set to 0 after the PEC byte is sent or received. Note that the NACK is automatically send following a PEC byte that results in a PEC error. The PEC Polynomial is x^8 + x^2 + x^1 + 1."] pub type MASTER_I2CPECCTL_PECEN_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , MASTER_I2CPECCTL_PECEN_A > ; impl < 'a , REG , const O : u8 > MASTER_I2CPECCTL_PECEN_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn master_i2cpecctl_pecen_disable (self) -> & 'a mut crate :: W < REG > { self . variant (MASTER_I2CPECCTL_PECEN_A :: MASTER_I2CPECCTL_PECEN_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn master_i2cpecctl_pecen_enable (self) -> & 'a mut crate :: W < REG > { self . variant (MASTER_I2CPECCTL_PECEN_A :: MASTER_I2CPECCTL_PECEN_ENABLE) } } impl R { # [doc = "Bits 0:8 - PEC Count When this field is non zero, the number of I2C bytes are counted (Note that although the PEC is calculated on the I2C address it is not counted at a byte). When the byte count = PECCNT and the state machine is transmitting, the contents of the LSFR is loaded into the shift register instead of the byte received from the Tx FIFO. When the state machine is receiving, after the last bit of this byte is received the LSFR is checked and if it is non-zero, a PEC RX Error interrupt is generated. The I2C packet must be padded to include the PEC byte for both transmit and receive. In transmit mode the FIFO must be loaded with a dummy PEC byte. In receive mode the PEC byte will be passed to the Rx FIFO. In the normal Master use case, FW would set PECEN=1 and PECCNT=SMB packet length (Not including Slave Address byte, but including the PEC byte). FW would then configure DMA to allow the packet to complete unassisted and write MCTR to initiate the transaction. Note that when the byte count = PEC CNT, the byte count is reset to 0 and multiple PEC calculation can automatically occur within a single I2C transaction. Note that any write to the MASTER_I2CPECCTL Register will clear the current PEC Byte Count in the Master State Machine."] # [inline (always)] pub fn master_i2cpecctl_peccnt (& self) -> MASTER_I2CPECCTL_PECCNT_R { MASTER_I2CPECCTL_PECCNT_R :: new ((self . bits & 0x01ff) as u16) } # [doc = "Bit 12 - PEC Enable This bit enables the SMB Packet Error Checking (PEC). When enabled the PEC is calculated on all bits accept the Start, Stop, Ack and Nack. The PEC LSFR and the Byte Counter is set to 0 when the State Machine is in the IDLE state, which occur following a Stop or when a timeout occurs. The Counter is also set to 0 after the PEC byte is sent or received. Note that the NACK is automatically send following a PEC byte that results in a PEC error. The PEC Polynomial is x^8 + x^2 + x^1 + 1."] # [inline (always)] pub fn master_i2cpecctl_pecen (& self) -> MASTER_I2CPECCTL_PECEN_R { MASTER_I2CPECCTL_PECEN_R :: new (((self . bits >> 12) & 1) != 0) } } impl W { # [doc = "Bits 0:8 - PEC Count When this field is non zero, the number of I2C bytes are counted (Note that although the PEC is calculated on the I2C address it is not counted at a byte). When the byte count = PECCNT and the state machine is transmitting, the contents of the LSFR is loaded into the shift register instead of the byte received from the Tx FIFO. When the state machine is receiving, after the last bit of this byte is received the LSFR is checked and if it is non-zero, a PEC RX Error interrupt is generated. The I2C packet must be padded to include the PEC byte for both transmit and receive. In transmit mode the FIFO must be loaded with a dummy PEC byte. In receive mode the PEC byte will be passed to the Rx FIFO. In the normal Master use case, FW would set PECEN=1 and PECCNT=SMB packet length (Not including Slave Address byte, but including the PEC byte). FW would then configure DMA to allow the packet to complete unassisted and write MCTR to initiate the transaction. Note that when the byte count = PEC CNT, the byte count is reset to 0 and multiple PEC calculation can automatically occur within a single I2C transaction. Note that any write to the MASTER_I2CPECCTL Register will clear the current PEC Byte Count in the Master State Machine."] # [inline (always)] # [must_use] pub fn master_i2cpecctl_peccnt (& mut self) -> MASTER_I2CPECCTL_PECCNT_W < MASTER_I2CPECCTL_SPEC , 0 > { MASTER_I2CPECCTL_PECCNT_W :: new (self) } # [doc = "Bit 12 - PEC Enable This bit enables the SMB Packet Error Checking (PEC). When enabled the PEC is calculated on all bits accept the Start, Stop, Ack and Nack. The PEC LSFR and the Byte Counter is set to 0 when the State Machine is in the IDLE state, which occur following a Stop or when a timeout occurs. The Counter is also set to 0 after the PEC byte is sent or received. Note that the NACK is automatically send following a PEC byte that results in a PEC error. The PEC Polynomial is x^8 + x^2 + x^1 + 1."] # [inline (always)] # [must_use] pub fn master_i2cpecctl_pecen (& mut self) -> MASTER_I2CPECCTL_PECEN_W <'_, MASTER_I2CPECCTL_SPEC , 12 > { MASTER_I2CPECCTL_PECEN_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "I2C master PEC control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`master_i2cpecctl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`master_i2cpecctl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct MASTER_I2CPECCTL_SPEC ; impl crate :: RegisterSpec for MASTER_I2CPECCTL_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`master_i2cpecctl::R`](R) reader structure"] impl crate :: Readable for MASTER_I2CPECCTL_SPEC { } # [doc = "`write(|w| ..)` method takes [`master_i2cpecctl::W`](W) writer structure"] impl crate :: Writable for MASTER_I2CPECCTL_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets MASTER_I2CPECCTL to value 0"] impl crate :: Resettable for MASTER_I2CPECCTL_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/i2c1/int_event2_iset.rs:1:5877 [INFO] [stdout] | [INFO] [stdout] 1 | ...t_srxfifotrg (& mut self) -> INT_EVENT2_ISET_SRXFIFOTRG_W < INT_EVENT2_ISET_SPEC , 2 > { INT_EVENT2_ISET_SRXFIFOTRG_W :: new (self) } ... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `INT_EVENT2_ISET` writer"] pub type W = crate :: W < INT_EVENT2_ISET_SPEC > ; # [doc = "Master Receive FIFO Trigger Trigger when RX FIFO contains &gt;= defined bytes\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT2_ISET_MRXFIFOTRG_AW { # [doc = "0: NO_EFFECT"] INT_EVENT2_ISET_MRXFIFOTRG_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT2_ISET_MRXFIFOTRG_SET = 1 , } impl From < INT_EVENT2_ISET_MRXFIFOTRG_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT2_ISET_MRXFIFOTRG_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT2_ISET_MRXFIFOTRG` writer - Master Receive FIFO Trigger Trigger when RX FIFO contains &gt;= defined bytes"] pub type INT_EVENT2_ISET_MRXFIFOTRG_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT2_ISET_MRXFIFOTRG_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT2_ISET_MRXFIFOTRG_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event2_iset_mrxfifotrg_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT2_ISET_MRXFIFOTRG_AW :: INT_EVENT2_ISET_MRXFIFOTRG_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event2_iset_mrxfifotrg_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT2_ISET_MRXFIFOTRG_AW :: INT_EVENT2_ISET_MRXFIFOTRG_SET) } } # [doc = "Master Transmit FIFO Trigger Trigger when Transmit FIFO contains &lt;= defined bytes\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT2_ISET_MTXFIFOTRG_AW { # [doc = "0: NO_EFFECT"] INT_EVENT2_ISET_MTXFIFOTRG_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT2_ISET_MTXFIFOTRG_SET = 1 , } impl From < INT_EVENT2_ISET_MTXFIFOTRG_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT2_ISET_MTXFIFOTRG_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT2_ISET_MTXFIFOTRG` writer - Master Transmit FIFO Trigger Trigger when Transmit FIFO contains &lt;= defined bytes"] pub type INT_EVENT2_ISET_MTXFIFOTRG_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT2_ISET_MTXFIFOTRG_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT2_ISET_MTXFIFOTRG_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event2_iset_mtxfifotrg_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT2_ISET_MTXFIFOTRG_AW :: INT_EVENT2_ISET_MTXFIFOTRG_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event2_iset_mtxfifotrg_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT2_ISET_MTXFIFOTRG_AW :: INT_EVENT2_ISET_MTXFIFOTRG_SET) } } # [doc = "Slave Receive FIFO Trigger\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT2_ISET_SRXFIFOTRG_AW { # [doc = "0: NO_EFFECT"] INT_EVENT2_ISET_SRXFIFOTRG_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT2_ISET_SRXFIFOTRG_SET = 1 , } impl From < INT_EVENT2_ISET_SRXFIFOTRG_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT2_ISET_SRXFIFOTRG_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT2_ISET_SRXFIFOTRG` writer - Slave Receive FIFO Trigger"] pub type INT_EVENT2_ISET_SRXFIFOTRG_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT2_ISET_SRXFIFOTRG_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT2_ISET_SRXFIFOTRG_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event2_iset_srxfifotrg_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT2_ISET_SRXFIFOTRG_AW :: INT_EVENT2_ISET_SRXFIFOTRG_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event2_iset_srxfifotrg_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT2_ISET_SRXFIFOTRG_AW :: INT_EVENT2_ISET_SRXFIFOTRG_SET) } } # [doc = "Slave Transmit FIFO Trigger\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT2_ISET_STXFIFOTRG_AW { # [doc = "0: NO_EFFECT"] INT_EVENT2_ISET_STXFIFOTRG_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT2_ISET_STXFIFOTRG_SET = 1 , } impl From < INT_EVENT2_ISET_STXFIFOTRG_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT2_ISET_STXFIFOTRG_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT2_ISET_STXFIFOTRG` writer - Slave Transmit FIFO Trigger"] pub type INT_EVENT2_ISET_STXFIFOTRG_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT2_ISET_STXFIFOTRG_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT2_ISET_STXFIFOTRG_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event2_iset_stxfifotrg_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT2_ISET_STXFIFOTRG_AW :: INT_EVENT2_ISET_STXFIFOTRG_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event2_iset_stxfifotrg_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT2_ISET_STXFIFOTRG_AW :: INT_EVENT2_ISET_STXFIFOTRG_SET) } } impl W { # [doc = "Bit 0 - Master Receive FIFO Trigger Trigger when RX FIFO contains &gt;= defined bytes"] # [inline (always)] # [must_use] pub fn int_event2_iset_mrxfifotrg (& mut self) -> INT_EVENT2_ISET_MRXFIFOTRG_W < INT_EVENT2_ISET_SPEC , 0 > { INT_EVENT2_ISET_MRXFIFOTRG_W :: new (self) } # [doc = "Bit 1 - Master Transmit FIFO Trigger Trigger when Transmit FIFO contains &lt;= defined bytes"] # [inline (always)] # [must_use] pub fn int_event2_iset_mtxfifotrg (& mut self) -> INT_EVENT2_ISET_MTXFIFOTRG_W < INT_EVENT2_ISET_SPEC , 1 > { INT_EVENT2_ISET_MTXFIFOTRG_W :: new (self) } # [doc = "Bit 2 - Slave Receive FIFO Trigger"] # [inline (always)] # [must_use] pub fn int_event2_iset_srxfifotrg (& mut self) -> INT_EVENT2_ISET_SRXFIFOTRG_W <'_, INT_EVENT2_ISET_SPEC , 2 > { INT_EVENT2_ISET_SRXFIFOTRG_W :: new (self) } # [doc = "Bit 3 - Slave Transmit FIFO Trigger"] # [inline (always)] # [must_use] pub fn int_event2_iset_stxfifotrg (& mut self) -> INT_EVENT2_ISET_STXFIFOTRG_W < INT_EVENT2_ISET_SPEC , 3 > { INT_EVENT2_ISET_STXFIFOTRG_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Interrupt set\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_event2_iset::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct INT_EVENT2_ISET_SPEC ; impl crate :: RegisterSpec for INT_EVENT2_ISET_SPEC { type Ux = u32 ; } # [doc = "`write(|w| ..)` method takes [`int_event2_iset::W`](W) writer structure"] impl crate :: Writable for INT_EVENT2_ISET_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets INT_EVENT2_ISET to value 0"] impl crate :: Resettable for INT_EVENT2_ISET_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/i2c1/sctr.rs:1:24329 [INFO] [stdout] | [INFO] [stdout] 1 | ...t_use] pub fn sctr_active (& mut self) -> SCTR_ACTIVE_W < SCTR_SPEC , 0 > { SCTR_ACTIVE_W :: new (self) } # [doc = "Bit 1 - General ca... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `SCTR` reader"] pub type R = crate :: R < SCTR_SPEC > ; # [doc = "Register `SCTR` writer"] pub type W = crate :: W < SCTR_SPEC > ; # [doc = "Field `SCTR_ACTIVE` reader - Device Active. Setting this bit enables the slave functionality."] pub type SCTR_ACTIVE_R = crate :: BitReader < SCTR_ACTIVE_A > ; # [doc = "Device Active. Setting this bit enables the slave functionality.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum SCTR_ACTIVE_A { # [doc = "0: DISABLE"] SCTR_ACTIVE_DISABLE = 0 , # [doc = "1: ENABLE"] SCTR_ACTIVE_ENABLE = 1 , } impl From < SCTR_ACTIVE_A > for bool { # [inline (always)] fn from (variant : SCTR_ACTIVE_A) -> Self { variant as u8 != 0 } } impl SCTR_ACTIVE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> SCTR_ACTIVE_A { match self . bits { false => SCTR_ACTIVE_A :: SCTR_ACTIVE_DISABLE , true => SCTR_ACTIVE_A :: SCTR_ACTIVE_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_sctr_active_disable (& self) -> bool { * self == SCTR_ACTIVE_A :: SCTR_ACTIVE_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_sctr_active_enable (& self) -> bool { * self == SCTR_ACTIVE_A :: SCTR_ACTIVE_ENABLE } } # [doc = "Field `SCTR_ACTIVE` writer - Device Active. Setting this bit enables the slave functionality."] pub type SCTR_ACTIVE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , SCTR_ACTIVE_A > ; impl < 'a , REG , const O : u8 > SCTR_ACTIVE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn sctr_active_disable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_ACTIVE_A :: SCTR_ACTIVE_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn sctr_active_enable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_ACTIVE_A :: SCTR_ACTIVE_ENABLE) } } # [doc = "Field `SCTR_GENCALL` reader - General call response enable. This bit is only available in UCBxI2COA0. Modify only when UCSWRST = 1. 0b = Do not respond to a general call 1b = Respond to a general call"] pub type SCTR_GENCALL_R = crate :: BitReader < SCTR_GENCALL_A > ; # [doc = "General call response enable. This bit is only available in UCBxI2COA0. Modify only when UCSWRST = 1. 0b = Do not respond to a general call 1b = Respond to a general call\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum SCTR_GENCALL_A { # [doc = "0: DISABLE"] SCTR_GENCALL_DISABLE = 0 , # [doc = "1: ENABLE"] SCTR_GENCALL_ENABLE = 1 , } impl From < SCTR_GENCALL_A > for bool { # [inline (always)] fn from (variant : SCTR_GENCALL_A) -> Self { variant as u8 != 0 } } impl SCTR_GENCALL_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> SCTR_GENCALL_A { match self . bits { false => SCTR_GENCALL_A :: SCTR_GENCALL_DISABLE , true => SCTR_GENCALL_A :: SCTR_GENCALL_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_sctr_gencall_disable (& self) -> bool { * self == SCTR_GENCALL_A :: SCTR_GENCALL_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_sctr_gencall_enable (& self) -> bool { * self == SCTR_GENCALL_A :: SCTR_GENCALL_ENABLE } } # [doc = "Field `SCTR_GENCALL` writer - General call response enable. This bit is only available in UCBxI2COA0. Modify only when UCSWRST = 1. 0b = Do not respond to a general call 1b = Respond to a general call"] pub type SCTR_GENCALL_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , SCTR_GENCALL_A > ; impl < 'a , REG , const O : u8 > SCTR_GENCALL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn sctr_gencall_disable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_GENCALL_A :: SCTR_GENCALL_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn sctr_gencall_enable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_GENCALL_A :: SCTR_GENCALL_ENABLE) } } # [doc = "Field `SCTR_SCLKSTRETCH` reader - Slave Clock Stretch Enable"] pub type SCTR_SCLKSTRETCH_R = crate :: BitReader < SCTR_SCLKSTRETCH_A > ; # [doc = "Slave Clock Stretch Enable\n\nValue on reset: 1"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum SCTR_SCLKSTRETCH_A { # [doc = "0: DISABLE"] SCTR_SCLKSTRETCH_DISABLE = 0 , # [doc = "1: ENABLE"] SCTR_SCLKSTRETCH_ENABLE = 1 , } impl From < SCTR_SCLKSTRETCH_A > for bool { # [inline (always)] fn from (variant : SCTR_SCLKSTRETCH_A) -> Self { variant as u8 != 0 } } impl SCTR_SCLKSTRETCH_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> SCTR_SCLKSTRETCH_A { match self . bits { false => SCTR_SCLKSTRETCH_A :: SCTR_SCLKSTRETCH_DISABLE , true => SCTR_SCLKSTRETCH_A :: SCTR_SCLKSTRETCH_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_sctr_sclkstretch_disable (& self) -> bool { * self == SCTR_SCLKSTRETCH_A :: SCTR_SCLKSTRETCH_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_sctr_sclkstretch_enable (& self) -> bool { * self == SCTR_SCLKSTRETCH_A :: SCTR_SCLKSTRETCH_ENABLE } } # [doc = "Field `SCTR_SCLKSTRETCH` writer - Slave Clock Stretch Enable"] pub type SCTR_SCLKSTRETCH_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , SCTR_SCLKSTRETCH_A > ; impl < 'a , REG , const O : u8 > SCTR_SCLKSTRETCH_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn sctr_sclkstretch_disable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_SCLKSTRETCH_A :: SCTR_SCLKSTRETCH_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn sctr_sclkstretch_enable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_SCLKSTRETCH_A :: SCTR_SCLKSTRETCH_ENABLE) } } # [doc = "Field `SCTR_TXEMPTY_ON_TREQ` reader - Tx Empty Interrupt on TREQ"] pub type SCTR_TXEMPTY_ON_TREQ_R = crate :: BitReader < SCTR_TXEMPTY_ON_TREQ_A > ; # [doc = "Tx Empty Interrupt on TREQ\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum SCTR_TXEMPTY_ON_TREQ_A { # [doc = "0: DISABLE"] SCTR_TXEMPTY_ON_TREQ_DISABLE = 0 , # [doc = "1: ENABLE"] SCTR_TXEMPTY_ON_TREQ_ENABLE = 1 , } impl From < SCTR_TXEMPTY_ON_TREQ_A > for bool { # [inline (always)] fn from (variant : SCTR_TXEMPTY_ON_TREQ_A) -> Self { variant as u8 != 0 } } impl SCTR_TXEMPTY_ON_TREQ_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> SCTR_TXEMPTY_ON_TREQ_A { match self . bits { false => SCTR_TXEMPTY_ON_TREQ_A :: SCTR_TXEMPTY_ON_TREQ_DISABLE , true => SCTR_TXEMPTY_ON_TREQ_A :: SCTR_TXEMPTY_ON_TREQ_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_sctr_txempty_on_treq_disable (& self) -> bool { * self == SCTR_TXEMPTY_ON_TREQ_A :: SCTR_TXEMPTY_ON_TREQ_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_sctr_txempty_on_treq_enable (& self) -> bool { * self == SCTR_TXEMPTY_ON_TREQ_A :: SCTR_TXEMPTY_ON_TREQ_ENABLE } } # [doc = "Field `SCTR_TXEMPTY_ON_TREQ` writer - Tx Empty Interrupt on TREQ"] pub type SCTR_TXEMPTY_ON_TREQ_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , SCTR_TXEMPTY_ON_TREQ_A > ; impl < 'a , REG , const O : u8 > SCTR_TXEMPTY_ON_TREQ_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn sctr_txempty_on_treq_disable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_TXEMPTY_ON_TREQ_A :: SCTR_TXEMPTY_ON_TREQ_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn sctr_txempty_on_treq_enable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_TXEMPTY_ON_TREQ_A :: SCTR_TXEMPTY_ON_TREQ_ENABLE) } } # [doc = "Field `SCTR_TXTRIG_TXMODE` reader - Tx Trigger when slave FSM is in Tx Mode"] pub type SCTR_TXTRIG_TXMODE_R = crate :: BitReader < SCTR_TXTRIG_TXMODE_A > ; # [doc = "Tx Trigger when slave FSM is in Tx Mode\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum SCTR_TXTRIG_TXMODE_A { # [doc = "0: DISABLE"] SCTR_TXTRIG_TXMODE_DISABLE = 0 , # [doc = "1: ENABLE"] SCTR_TXTRIG_TXMODE_ENABLE = 1 , } impl From < SCTR_TXTRIG_TXMODE_A > for bool { # [inline (always)] fn from (variant : SCTR_TXTRIG_TXMODE_A) -> Self { variant as u8 != 0 } } impl SCTR_TXTRIG_TXMODE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> SCTR_TXTRIG_TXMODE_A { match self . bits { false => SCTR_TXTRIG_TXMODE_A :: SCTR_TXTRIG_TXMODE_DISABLE , true => SCTR_TXTRIG_TXMODE_A :: SCTR_TXTRIG_TXMODE_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_sctr_txtrig_txmode_disable (& self) -> bool { * self == SCTR_TXTRIG_TXMODE_A :: SCTR_TXTRIG_TXMODE_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_sctr_txtrig_txmode_enable (& self) -> bool { * self == SCTR_TXTRIG_TXMODE_A :: SCTR_TXTRIG_TXMODE_ENABLE } } # [doc = "Field `SCTR_TXTRIG_TXMODE` writer - Tx Trigger when slave FSM is in Tx Mode"] pub type SCTR_TXTRIG_TXMODE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , SCTR_TXTRIG_TXMODE_A > ; impl < 'a , REG , const O : u8 > SCTR_TXTRIG_TXMODE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn sctr_txtrig_txmode_disable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_TXTRIG_TXMODE_A :: SCTR_TXTRIG_TXMODE_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn sctr_txtrig_txmode_enable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_TXTRIG_TXMODE_A :: SCTR_TXTRIG_TXMODE_ENABLE) } } # [doc = "Field `SCTR_TXWAIT_STALE_TXFIFO` reader - Tx transfer waits when stale data in Tx FIFO. This prevents stale bytes left in the TX FIFO from automatically being sent on the next I2C packet. Note: this should be used with TXEMPTY_ON_TREQ set to prevent the Slave State Machine from waiting for TX FIFO data without an interrupt notification when the FIFO data is stale."] pub type SCTR_TXWAIT_STALE_TXFIFO_R = crate :: BitReader < SCTR_TXWAIT_STALE_TXFIFO_A > ; # [doc = "Tx transfer waits when stale data in Tx FIFO. This prevents stale bytes left in the TX FIFO from automatically being sent on the next I2C packet. Note: this should be used with TXEMPTY_ON_TREQ set to prevent the Slave State Machine from waiting for TX FIFO data without an interrupt notification when the FIFO data is stale.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum SCTR_TXWAIT_STALE_TXFIFO_A { # [doc = "0: DISABLE"] SCTR_TXWAIT_STALE_TXFIFO_DISABLE = 0 , # [doc = "1: ENABLE"] SCTR_TXWAIT_STALE_TXFIFO_ENABLE = 1 , } impl From < SCTR_TXWAIT_STALE_TXFIFO_A > for bool { # [inline (always)] fn from (variant : SCTR_TXWAIT_STALE_TXFIFO_A) -> Self { variant as u8 != 0 } } impl SCTR_TXWAIT_STALE_TXFIFO_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> SCTR_TXWAIT_STALE_TXFIFO_A { match self . bits { false => SCTR_TXWAIT_STALE_TXFIFO_A :: SCTR_TXWAIT_STALE_TXFIFO_DISABLE , true => SCTR_TXWAIT_STALE_TXFIFO_A :: SCTR_TXWAIT_STALE_TXFIFO_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_sctr_txwait_stale_txfifo_disable (& self) -> bool { * self == SCTR_TXWAIT_STALE_TXFIFO_A :: SCTR_TXWAIT_STALE_TXFIFO_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_sctr_txwait_stale_txfifo_enable (& self) -> bool { * self == SCTR_TXWAIT_STALE_TXFIFO_A :: SCTR_TXWAIT_STALE_TXFIFO_ENABLE } } # [doc = "Field `SCTR_TXWAIT_STALE_TXFIFO` writer - Tx transfer waits when stale data in Tx FIFO. This prevents stale bytes left in the TX FIFO from automatically being sent on the next I2C packet. Note: this should be used with TXEMPTY_ON_TREQ set to prevent the Slave State Machine from waiting for TX FIFO data without an interrupt notification when the FIFO data is stale."] pub type SCTR_TXWAIT_STALE_TXFIFO_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , SCTR_TXWAIT_STALE_TXFIFO_A > ; impl < 'a , REG , const O : u8 > SCTR_TXWAIT_STALE_TXFIFO_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn sctr_txwait_stale_txfifo_disable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_TXWAIT_STALE_TXFIFO_A :: SCTR_TXWAIT_STALE_TXFIFO_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn sctr_txwait_stale_txfifo_enable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_TXWAIT_STALE_TXFIFO_A :: SCTR_TXWAIT_STALE_TXFIFO_ENABLE) } } # [doc = "Field `SCTR_RXFULL_ON_RREQ` reader - Rx full interrupt generated on RREQ condition as indicated in SSR"] pub type SCTR_RXFULL_ON_RREQ_R = crate :: BitReader < SCTR_RXFULL_ON_RREQ_A > ; # [doc = "Rx full interrupt generated on RREQ condition as indicated in SSR\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum SCTR_RXFULL_ON_RREQ_A { # [doc = "0: DISABLE"] SCTR_RXFULL_ON_RREQ_DISABLE = 0 , # [doc = "1: ENABLE"] SCTR_RXFULL_ON_RREQ_ENABLE = 1 , } impl From < SCTR_RXFULL_ON_RREQ_A > for bool { # [inline (always)] fn from (variant : SCTR_RXFULL_ON_RREQ_A) -> Self { variant as u8 != 0 } } impl SCTR_RXFULL_ON_RREQ_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> SCTR_RXFULL_ON_RREQ_A { match self . bits { false => SCTR_RXFULL_ON_RREQ_A :: SCTR_RXFULL_ON_RREQ_DISABLE , true => SCTR_RXFULL_ON_RREQ_A :: SCTR_RXFULL_ON_RREQ_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_sctr_rxfull_on_rreq_disable (& self) -> bool { * self == SCTR_RXFULL_ON_RREQ_A :: SCTR_RXFULL_ON_RREQ_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_sctr_rxfull_on_rreq_enable (& self) -> bool { * self == SCTR_RXFULL_ON_RREQ_A :: SCTR_RXFULL_ON_RREQ_ENABLE } } # [doc = "Field `SCTR_RXFULL_ON_RREQ` writer - Rx full interrupt generated on RREQ condition as indicated in SSR"] pub type SCTR_RXFULL_ON_RREQ_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , SCTR_RXFULL_ON_RREQ_A > ; impl < 'a , REG , const O : u8 > SCTR_RXFULL_ON_RREQ_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn sctr_rxfull_on_rreq_disable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_RXFULL_ON_RREQ_A :: SCTR_RXFULL_ON_RREQ_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn sctr_rxfull_on_rreq_enable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_RXFULL_ON_RREQ_A :: SCTR_RXFULL_ON_RREQ_ENABLE) } } # [doc = "Field `SCTR_EN_DEFHOSTADR` reader - Enable Default Host Address"] pub type SCTR_EN_DEFHOSTADR_R = crate :: BitReader < SCTR_EN_DEFHOSTADR_A > ; # [doc = "Enable Default Host Address\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum SCTR_EN_DEFHOSTADR_A { # [doc = "0: DISABLE"] SCTR_EN_DEFHOSTADR_DISABLE = 0 , # [doc = "1: ENABLE"] SCTR_EN_DEFHOSTADR_ENABLE = 1 , } impl From < SCTR_EN_DEFHOSTADR_A > for bool { # [inline (always)] fn from (variant : SCTR_EN_DEFHOSTADR_A) -> Self { variant as u8 != 0 } } impl SCTR_EN_DEFHOSTADR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> SCTR_EN_DEFHOSTADR_A { match self . bits { false => SCTR_EN_DEFHOSTADR_A :: SCTR_EN_DEFHOSTADR_DISABLE , true => SCTR_EN_DEFHOSTADR_A :: SCTR_EN_DEFHOSTADR_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_sctr_en_defhostadr_disable (& self) -> bool { * self == SCTR_EN_DEFHOSTADR_A :: SCTR_EN_DEFHOSTADR_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_sctr_en_defhostadr_enable (& self) -> bool { * self == SCTR_EN_DEFHOSTADR_A :: SCTR_EN_DEFHOSTADR_ENABLE } } # [doc = "Field `SCTR_EN_DEFHOSTADR` writer - Enable Default Host Address"] pub type SCTR_EN_DEFHOSTADR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , SCTR_EN_DEFHOSTADR_A > ; impl < 'a , REG , const O : u8 > SCTR_EN_DEFHOSTADR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn sctr_en_defhostadr_disable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_EN_DEFHOSTADR_A :: SCTR_EN_DEFHOSTADR_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn sctr_en_defhostadr_enable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_EN_DEFHOSTADR_A :: SCTR_EN_DEFHOSTADR_ENABLE) } } # [doc = "Field `SCTR_EN_ALRESPADR` reader - Enable Alert Response Address"] pub type SCTR_EN_ALRESPADR_R = crate :: BitReader < SCTR_EN_ALRESPADR_A > ; # [doc = "Enable Alert Response Address\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum SCTR_EN_ALRESPADR_A { # [doc = "0: DISABLE"] SCTR_EN_ALRESPADR_DISABLE = 0 , # [doc = "1: ENABLE"] SCTR_EN_ALRESPADR_ENABLE = 1 , } impl From < SCTR_EN_ALRESPADR_A > for bool { # [inline (always)] fn from (variant : SCTR_EN_ALRESPADR_A) -> Self { variant as u8 != 0 } } impl SCTR_EN_ALRESPADR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> SCTR_EN_ALRESPADR_A { match self . bits { false => SCTR_EN_ALRESPADR_A :: SCTR_EN_ALRESPADR_DISABLE , true => SCTR_EN_ALRESPADR_A :: SCTR_EN_ALRESPADR_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_sctr_en_alrespadr_disable (& self) -> bool { * self == SCTR_EN_ALRESPADR_A :: SCTR_EN_ALRESPADR_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_sctr_en_alrespadr_enable (& self) -> bool { * self == SCTR_EN_ALRESPADR_A :: SCTR_EN_ALRESPADR_ENABLE } } # [doc = "Field `SCTR_EN_ALRESPADR` writer - Enable Alert Response Address"] pub type SCTR_EN_ALRESPADR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , SCTR_EN_ALRESPADR_A > ; impl < 'a , REG , const O : u8 > SCTR_EN_ALRESPADR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn sctr_en_alrespadr_disable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_EN_ALRESPADR_A :: SCTR_EN_ALRESPADR_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn sctr_en_alrespadr_enable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_EN_ALRESPADR_A :: SCTR_EN_ALRESPADR_ENABLE) } } # [doc = "Field `SCTR_EN_DEFDEVADR` reader - Enable Deault device address"] pub type SCTR_EN_DEFDEVADR_R = crate :: BitReader < SCTR_EN_DEFDEVADR_A > ; # [doc = "Enable Deault device address\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum SCTR_EN_DEFDEVADR_A { # [doc = "0: DISABLE"] SCTR_EN_DEFDEVADR_DISABLE = 0 , # [doc = "1: ENABLE"] SCTR_EN_DEFDEVADR_ENABLE = 1 , } impl From < SCTR_EN_DEFDEVADR_A > for bool { # [inline (always)] fn from (variant : SCTR_EN_DEFDEVADR_A) -> Self { variant as u8 != 0 } } impl SCTR_EN_DEFDEVADR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> SCTR_EN_DEFDEVADR_A { match self . bits { false => SCTR_EN_DEFDEVADR_A :: SCTR_EN_DEFDEVADR_DISABLE , true => SCTR_EN_DEFDEVADR_A :: SCTR_EN_DEFDEVADR_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_sctr_en_defdevadr_disable (& self) -> bool { * self == SCTR_EN_DEFDEVADR_A :: SCTR_EN_DEFDEVADR_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_sctr_en_defdevadr_enable (& self) -> bool { * self == SCTR_EN_DEFDEVADR_A :: SCTR_EN_DEFDEVADR_ENABLE } } # [doc = "Field `SCTR_EN_DEFDEVADR` writer - Enable Deault device address"] pub type SCTR_EN_DEFDEVADR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , SCTR_EN_DEFDEVADR_A > ; impl < 'a , REG , const O : u8 > SCTR_EN_DEFDEVADR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn sctr_en_defdevadr_disable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_EN_DEFDEVADR_A :: SCTR_EN_DEFDEVADR_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn sctr_en_defdevadr_enable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_EN_DEFDEVADR_A :: SCTR_EN_DEFDEVADR_ENABLE) } } # [doc = "Field `SCTR_SWUEN` reader - Slave Wakeup Enable"] pub type SCTR_SWUEN_R = crate :: BitReader < SCTR_SWUEN_A > ; # [doc = "Slave Wakeup Enable\n\nValue on reset: 1"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum SCTR_SWUEN_A { # [doc = "0: DISABLE"] SCTR_SWUEN_DISABLE = 0 , # [doc = "1: ENABLE"] SCTR_SWUEN_ENABLE = 1 , } impl From < SCTR_SWUEN_A > for bool { # [inline (always)] fn from (variant : SCTR_SWUEN_A) -> Self { variant as u8 != 0 } } impl SCTR_SWUEN_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> SCTR_SWUEN_A { match self . bits { false => SCTR_SWUEN_A :: SCTR_SWUEN_DISABLE , true => SCTR_SWUEN_A :: SCTR_SWUEN_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_sctr_swuen_disable (& self) -> bool { * self == SCTR_SWUEN_A :: SCTR_SWUEN_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_sctr_swuen_enable (& self) -> bool { * self == SCTR_SWUEN_A :: SCTR_SWUEN_ENABLE } } # [doc = "Field `SCTR_SWUEN` writer - Slave Wakeup Enable"] pub type SCTR_SWUEN_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , SCTR_SWUEN_A > ; impl < 'a , REG , const O : u8 > SCTR_SWUEN_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn sctr_swuen_disable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_SWUEN_A :: SCTR_SWUEN_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn sctr_swuen_enable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_SWUEN_A :: SCTR_SWUEN_ENABLE) } } impl R { # [doc = "Bit 0 - Device Active. Setting this bit enables the slave functionality."] # [inline (always)] pub fn sctr_active (& self) -> SCTR_ACTIVE_R { SCTR_ACTIVE_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - General call response enable. This bit is only available in UCBxI2COA0. Modify only when UCSWRST = 1. 0b = Do not respond to a general call 1b = Respond to a general call"] # [inline (always)] pub fn sctr_gencall (& self) -> SCTR_GENCALL_R { SCTR_GENCALL_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - Slave Clock Stretch Enable"] # [inline (always)] pub fn sctr_sclkstretch (& self) -> SCTR_SCLKSTRETCH_R { SCTR_SCLKSTRETCH_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - Tx Empty Interrupt on TREQ"] # [inline (always)] pub fn sctr_txempty_on_treq (& self) -> SCTR_TXEMPTY_ON_TREQ_R { SCTR_TXEMPTY_ON_TREQ_R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - Tx Trigger when slave FSM is in Tx Mode"] # [inline (always)] pub fn sctr_txtrig_txmode (& self) -> SCTR_TXTRIG_TXMODE_R { SCTR_TXTRIG_TXMODE_R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - Tx transfer waits when stale data in Tx FIFO. This prevents stale bytes left in the TX FIFO from automatically being sent on the next I2C packet. Note: this should be used with TXEMPTY_ON_TREQ set to prevent the Slave State Machine from waiting for TX FIFO data without an interrupt notification when the FIFO data is stale."] # [inline (always)] pub fn sctr_txwait_stale_txfifo (& self) -> SCTR_TXWAIT_STALE_TXFIFO_R { SCTR_TXWAIT_STALE_TXFIFO_R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - Rx full interrupt generated on RREQ condition as indicated in SSR"] # [inline (always)] pub fn sctr_rxfull_on_rreq (& self) -> SCTR_RXFULL_ON_RREQ_R { SCTR_RXFULL_ON_RREQ_R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - Enable Default Host Address"] # [inline (always)] pub fn sctr_en_defhostadr (& self) -> SCTR_EN_DEFHOSTADR_R { SCTR_EN_DEFHOSTADR_R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - Enable Alert Response Address"] # [inline (always)] pub fn sctr_en_alrespadr (& self) -> SCTR_EN_ALRESPADR_R { SCTR_EN_ALRESPADR_R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - Enable Deault device address"] # [inline (always)] pub fn sctr_en_defdevadr (& self) -> SCTR_EN_DEFDEVADR_R { SCTR_EN_DEFDEVADR_R :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - Slave Wakeup Enable"] # [inline (always)] pub fn sctr_swuen (& self) -> SCTR_SWUEN_R { SCTR_SWUEN_R :: new (((self . bits >> 10) & 1) != 0) } } impl W { # [doc = "Bit 0 - Device Active. Setting this bit enables the slave functionality."] # [inline (always)] # [must_use] pub fn sctr_active (& mut self) -> SCTR_ACTIVE_W <'_, SCTR_SPEC , 0 > { SCTR_ACTIVE_W :: new (self) } # [doc = "Bit 1 - General call response enable. This bit is only available in UCBxI2COA0. Modify only when UCSWRST = 1. 0b = Do not respond to a general call 1b = Respond to a general call"] # [inline (always)] # [must_use] pub fn sctr_gencall (& mut self) -> SCTR_GENCALL_W < SCTR_SPEC , 1 > { SCTR_GENCALL_W :: new (self) } # [doc = "Bit 2 - Slave Clock Stretch Enable"] # [inline (always)] # [must_use] pub fn sctr_sclkstretch (& mut self) -> SCTR_SCLKSTRETCH_W < SCTR_SPEC , 2 > { SCTR_SCLKSTRETCH_W :: new (self) } # [doc = "Bit 3 - Tx Empty Interrupt on TREQ"] # [inline (always)] # [must_use] pub fn sctr_txempty_on_treq (& mut self) -> SCTR_TXEMPTY_ON_TREQ_W < SCTR_SPEC , 3 > { SCTR_TXEMPTY_ON_TREQ_W :: new (self) } # [doc = "Bit 4 - Tx Trigger when slave FSM is in Tx Mode"] # [inline (always)] # [must_use] pub fn sctr_txtrig_txmode (& mut self) -> SCTR_TXTRIG_TXMODE_W < SCTR_SPEC , 4 > { SCTR_TXTRIG_TXMODE_W :: new (self) } # [doc = "Bit 5 - Tx transfer waits when stale data in Tx FIFO. This prevents stale bytes left in the TX FIFO from automatically being sent on the next I2C packet. Note: this should be used with TXEMPTY_ON_TREQ set to prevent the Slave State Machine from waiting for TX FIFO data without an interrupt notification when the FIFO data is stale."] # [inline (always)] # [must_use] pub fn sctr_txwait_stale_txfifo (& mut self) -> SCTR_TXWAIT_STALE_TXFIFO_W < SCTR_SPEC , 5 > { SCTR_TXWAIT_STALE_TXFIFO_W :: new (self) } # [doc = "Bit 6 - Rx full interrupt generated on RREQ condition as indicated in SSR"] # [inline (always)] # [must_use] pub fn sctr_rxfull_on_rreq (& mut self) -> SCTR_RXFULL_ON_RREQ_W < SCTR_SPEC , 6 > { SCTR_RXFULL_ON_RREQ_W :: new (self) } # [doc = "Bit 7 - Enable Default Host Address"] # [inline (always)] # [must_use] pub fn sctr_en_defhostadr (& mut self) -> SCTR_EN_DEFHOSTADR_W < SCTR_SPEC , 7 > { SCTR_EN_DEFHOSTADR_W :: new (self) } # [doc = "Bit 8 - Enable Alert Response Address"] # [inline (always)] # [must_use] pub fn sctr_en_alrespadr (& mut self) -> SCTR_EN_ALRESPADR_W < SCTR_SPEC , 8 > { SCTR_EN_ALRESPADR_W :: new (self) } # [doc = "Bit 9 - Enable Deault device address"] # [inline (always)] # [must_use] pub fn sctr_en_defdevadr (& mut self) -> SCTR_EN_DEFDEVADR_W < SCTR_SPEC , 9 > { SCTR_EN_DEFDEVADR_W :: new (self) } # [doc = "Bit 10 - Slave Wakeup Enable"] # [inline (always)] # [must_use] pub fn sctr_swuen (& mut self) -> SCTR_SWUEN_W < SCTR_SPEC , 10 > { SCTR_SWUEN_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "I2C Slave Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sctr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sctr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct SCTR_SPEC ; impl crate :: RegisterSpec for SCTR_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`sctr::R`](R) reader structure"] impl crate :: Readable for SCTR_SPEC { } # [doc = "`write(|w| ..)` method takes [`sctr::W`](W) writer structure"] impl crate :: Writable for SCTR_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets SCTR to value 0x0404"] impl crate :: Resettable for SCTR_SPEC { const RESET_VALUE : Self :: Ux = 0x0404 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/i2c0/int_event0_iset.rs:1:40144 [INFO] [stdout] | [INFO] [stdout] 1 | ...ent0_iset_mstop (& mut self) -> INT_EVENT0_ISET_MSTOP_W < INT_EVENT0_ISET_SPEC , 9 > { INT_EVENT0_ISET_MSTOP_W :: new (self) } # [doc ... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `INT_EVENT0_ISET` writer"] pub type W = crate :: W < INT_EVENT0_ISET_SPEC > ; # [doc = "Master Receive Data Interrupt Signals that a byte has been received\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_MRXDONE_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_MRXDONE_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_MRXDONE_SET = 1 , } impl From < INT_EVENT0_ISET_MRXDONE_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_MRXDONE_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_MRXDONE` writer - Master Receive Data Interrupt Signals that a byte has been received"] pub type INT_EVENT0_ISET_MRXDONE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_MRXDONE_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_MRXDONE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_mrxdone_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MRXDONE_AW :: INT_EVENT0_ISET_MRXDONE_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_mrxdone_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MRXDONE_AW :: INT_EVENT0_ISET_MRXDONE_SET) } } # [doc = "Master Transmit Transaction completed Interrupt\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_MTXDONE_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_MTXDONE_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_MTXDONE_SET = 1 , } impl From < INT_EVENT0_ISET_MTXDONE_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_MTXDONE_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_MTXDONE` writer - Master Transmit Transaction completed Interrupt"] pub type INT_EVENT0_ISET_MTXDONE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_MTXDONE_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_MTXDONE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_mtxdone_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MTXDONE_AW :: INT_EVENT0_ISET_MTXDONE_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_mtxdone_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MTXDONE_AW :: INT_EVENT0_ISET_MTXDONE_SET) } } # [doc = "Master Receive FIFO Trigger Trigger when RX FIFO contains &gt;= defined bytes\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_MRXFIFOTRG_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_MRXFIFOTRG_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_MRXFIFOTRG_SET = 1 , } impl From < INT_EVENT0_ISET_MRXFIFOTRG_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_MRXFIFOTRG_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_MRXFIFOTRG` writer - Master Receive FIFO Trigger Trigger when RX FIFO contains &gt;= defined bytes"] pub type INT_EVENT0_ISET_MRXFIFOTRG_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_MRXFIFOTRG_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_MRXFIFOTRG_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_mrxfifotrg_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MRXFIFOTRG_AW :: INT_EVENT0_ISET_MRXFIFOTRG_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_mrxfifotrg_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MRXFIFOTRG_AW :: INT_EVENT0_ISET_MRXFIFOTRG_SET) } } # [doc = "Master Transmit FIFO Trigger Trigger when Transmit FIFO contains &lt;= defined bytes\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_MTXFIFOTRG_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_MTXFIFOTRG_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_MTXFIFOTRG_SET = 1 , } impl From < INT_EVENT0_ISET_MTXFIFOTRG_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_MTXFIFOTRG_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_MTXFIFOTRG` writer - Master Transmit FIFO Trigger Trigger when Transmit FIFO contains &lt;= defined bytes"] pub type INT_EVENT0_ISET_MTXFIFOTRG_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_MTXFIFOTRG_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_MTXFIFOTRG_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_mtxfifotrg_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MTXFIFOTRG_AW :: INT_EVENT0_ISET_MTXFIFOTRG_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_mtxfifotrg_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MTXFIFOTRG_AW :: INT_EVENT0_ISET_MTXFIFOTRG_SET) } } # [doc = "RXFIFO full event.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_MRXFIFOFULL_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_MRXFIFOFULL_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_MRXFIFOFULL_SET = 1 , } impl From < INT_EVENT0_ISET_MRXFIFOFULL_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_MRXFIFOFULL_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_MRXFIFOFULL` writer - RXFIFO full event."] pub type INT_EVENT0_ISET_MRXFIFOFULL_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_MRXFIFOFULL_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_MRXFIFOFULL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_mrxfifofull_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MRXFIFOFULL_AW :: INT_EVENT0_ISET_MRXFIFOFULL_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_mrxfifofull_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MRXFIFOFULL_AW :: INT_EVENT0_ISET_MRXFIFOFULL_SET) } } # [doc = "Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_MTXEMPTY_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_MTXEMPTY_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_MTXEMPTY_SET = 1 , } impl From < INT_EVENT0_ISET_MTXEMPTY_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_MTXEMPTY_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_MTXEMPTY` writer - Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode."] pub type INT_EVENT0_ISET_MTXEMPTY_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_MTXEMPTY_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_MTXEMPTY_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_mtxempty_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MTXEMPTY_AW :: INT_EVENT0_ISET_MTXEMPTY_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_mtxempty_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MTXEMPTY_AW :: INT_EVENT0_ISET_MTXEMPTY_SET) } } # [doc = "Address/Data NACK Interrupt\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_MNACK_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_MNACK_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_MNACK_SET = 1 , } impl From < INT_EVENT0_ISET_MNACK_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_MNACK_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_MNACK` writer - Address/Data NACK Interrupt"] pub type INT_EVENT0_ISET_MNACK_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_MNACK_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_MNACK_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_mnack_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MNACK_AW :: INT_EVENT0_ISET_MNACK_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_mnack_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MNACK_AW :: INT_EVENT0_ISET_MNACK_SET) } } # [doc = "START Detection Interrupt\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_MSTART_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_MSTART_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_MSTART_SET = 1 , } impl From < INT_EVENT0_ISET_MSTART_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_MSTART_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_MSTART` writer - START Detection Interrupt"] pub type INT_EVENT0_ISET_MSTART_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_MSTART_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_MSTART_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_mstart_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MSTART_AW :: INT_EVENT0_ISET_MSTART_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_mstart_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MSTART_AW :: INT_EVENT0_ISET_MSTART_SET) } } # [doc = "STOP Detection Interrupt\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_MSTOP_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_MSTOP_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_MSTOP_SET = 1 , } impl From < INT_EVENT0_ISET_MSTOP_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_MSTOP_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_MSTOP` writer - STOP Detection Interrupt"] pub type INT_EVENT0_ISET_MSTOP_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_MSTOP_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_MSTOP_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_mstop_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MSTOP_AW :: INT_EVENT0_ISET_MSTOP_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_mstop_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MSTOP_AW :: INT_EVENT0_ISET_MSTOP_SET) } } # [doc = "Arbitration Lost Interrupt\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_MARBLOST_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_MARBLOST_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_MARBLOST_SET = 1 , } impl From < INT_EVENT0_ISET_MARBLOST_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_MARBLOST_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_MARBLOST` writer - Arbitration Lost Interrupt"] pub type INT_EVENT0_ISET_MARBLOST_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_MARBLOST_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_MARBLOST_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_marblost_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MARBLOST_AW :: INT_EVENT0_ISET_MARBLOST_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_marblost_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MARBLOST_AW :: INT_EVENT0_ISET_MARBLOST_SET) } } # [doc = "DMA Done 1 on Event Channel 2\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_MDMA_DONE1_2_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_MDMA_DONE1_2_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_MDMA_DONE1_2_SET = 1 , } impl From < INT_EVENT0_ISET_MDMA_DONE1_2_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_MDMA_DONE1_2_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_MDMA_DONE1_2` writer - DMA Done 1 on Event Channel 2"] pub type INT_EVENT0_ISET_MDMA_DONE1_2_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_MDMA_DONE1_2_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_MDMA_DONE1_2_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_mdma_done1_2_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MDMA_DONE1_2_AW :: INT_EVENT0_ISET_MDMA_DONE1_2_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_mdma_done1_2_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MDMA_DONE1_2_AW :: INT_EVENT0_ISET_MDMA_DONE1_2_SET) } } # [doc = "DMA Done 1 on Event Channel 3\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_MDMA_DONE1_3_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_MDMA_DONE1_3_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_MDMA_DONE1_3_SET = 1 , } impl From < INT_EVENT0_ISET_MDMA_DONE1_3_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_MDMA_DONE1_3_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_MDMA_DONE1_3` writer - DMA Done 1 on Event Channel 3"] pub type INT_EVENT0_ISET_MDMA_DONE1_3_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_MDMA_DONE1_3_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_MDMA_DONE1_3_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_mdma_done1_3_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MDMA_DONE1_3_AW :: INT_EVENT0_ISET_MDMA_DONE1_3_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_mdma_done1_3_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MDMA_DONE1_3_AW :: INT_EVENT0_ISET_MDMA_DONE1_3_SET) } } # [doc = "Master RX Pec Error Interrupt\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_MPEC_RX_ERR_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_MPEC_RX_ERR_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_MPEC_RX_ERR_SET = 1 , } impl From < INT_EVENT0_ISET_MPEC_RX_ERR_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_MPEC_RX_ERR_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_MPEC_RX_ERR` writer - Master RX Pec Error Interrupt"] pub type INT_EVENT0_ISET_MPEC_RX_ERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_MPEC_RX_ERR_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_MPEC_RX_ERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_mpec_rx_err_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MPEC_RX_ERR_AW :: INT_EVENT0_ISET_MPEC_RX_ERR_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_mpec_rx_err_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MPEC_RX_ERR_AW :: INT_EVENT0_ISET_MPEC_RX_ERR_SET) } } # [doc = "Timeout A interrupt\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_TIMEOUTA_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_TIMEOUTA_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_TIMEOUTA_SET = 1 , } impl From < INT_EVENT0_ISET_TIMEOUTA_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_TIMEOUTA_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_TIMEOUTA` writer - Timeout A interrupt"] pub type INT_EVENT0_ISET_TIMEOUTA_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_TIMEOUTA_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_TIMEOUTA_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_timeouta_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_TIMEOUTA_AW :: INT_EVENT0_ISET_TIMEOUTA_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_timeouta_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_TIMEOUTA_AW :: INT_EVENT0_ISET_TIMEOUTA_SET) } } # [doc = "Timeout B Interrupt\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_TIMEOUTB_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_TIMEOUTB_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_TIMEOUTB_SET = 1 , } impl From < INT_EVENT0_ISET_TIMEOUTB_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_TIMEOUTB_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_TIMEOUTB` writer - Timeout B Interrupt"] pub type INT_EVENT0_ISET_TIMEOUTB_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_TIMEOUTB_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_TIMEOUTB_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_timeoutb_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_TIMEOUTB_AW :: INT_EVENT0_ISET_TIMEOUTB_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_timeoutb_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_TIMEOUTB_AW :: INT_EVENT0_ISET_TIMEOUTB_SET) } } # [doc = "Slave Receive Data Interrupt Signals that a byte has been received\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_SRXDONE_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_SRXDONE_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_SRXDONE_SET = 1 , } impl From < INT_EVENT0_ISET_SRXDONE_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_SRXDONE_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_SRXDONE` writer - Slave Receive Data Interrupt Signals that a byte has been received"] pub type INT_EVENT0_ISET_SRXDONE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_SRXDONE_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_SRXDONE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_srxdone_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_SRXDONE_AW :: INT_EVENT0_ISET_SRXDONE_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_srxdone_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_SRXDONE_AW :: INT_EVENT0_ISET_SRXDONE_SET) } } # [doc = "Slave Transmit Transaction completed Interrupt\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_STXDONE_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_STXDONE_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_STXDONE_SET = 1 , } impl From < INT_EVENT0_ISET_STXDONE_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_STXDONE_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_STXDONE` writer - Slave Transmit Transaction completed Interrupt"] pub type INT_EVENT0_ISET_STXDONE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_STXDONE_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_STXDONE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_stxdone_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_STXDONE_AW :: INT_EVENT0_ISET_STXDONE_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_stxdone_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_STXDONE_AW :: INT_EVENT0_ISET_STXDONE_SET) } } # [doc = "Slave Receive FIFO Trigger\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_SRXFIFOTRG_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_SRXFIFOTRG_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_SRXFIFOTRG_SET = 1 , } impl From < INT_EVENT0_ISET_SRXFIFOTRG_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_SRXFIFOTRG_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_SRXFIFOTRG` writer - Slave Receive FIFO Trigger"] pub type INT_EVENT0_ISET_SRXFIFOTRG_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_SRXFIFOTRG_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_SRXFIFOTRG_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_srxfifotrg_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_SRXFIFOTRG_AW :: INT_EVENT0_ISET_SRXFIFOTRG_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_srxfifotrg_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_SRXFIFOTRG_AW :: INT_EVENT0_ISET_SRXFIFOTRG_SET) } } # [doc = "Slave Transmit FIFO Trigger\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_STXFIFOTRG_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_STXFIFOTRG_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_STXFIFOTRG_SET = 1 , } impl From < INT_EVENT0_ISET_STXFIFOTRG_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_STXFIFOTRG_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_STXFIFOTRG` writer - Slave Transmit FIFO Trigger"] pub type INT_EVENT0_ISET_STXFIFOTRG_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_STXFIFOTRG_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_STXFIFOTRG_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_stxfifotrg_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_STXFIFOTRG_AW :: INT_EVENT0_ISET_STXFIFOTRG_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_stxfifotrg_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_STXFIFOTRG_AW :: INT_EVENT0_ISET_STXFIFOTRG_SET) } } # [doc = "RXFIFO full event. This interrupt is set if an RX FIFO is full.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_SRXFIFOFULL_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_SRXFIFOFULL_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_SRXFIFOFULL_SET = 1 , } impl From < INT_EVENT0_ISET_SRXFIFOFULL_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_SRXFIFOFULL_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_SRXFIFOFULL` writer - RXFIFO full event. This interrupt is set if an RX FIFO is full."] pub type INT_EVENT0_ISET_SRXFIFOFULL_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_SRXFIFOFULL_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_SRXFIFOFULL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_srxfifofull_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_SRXFIFOFULL_AW :: INT_EVENT0_ISET_SRXFIFOFULL_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_srxfifofull_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_SRXFIFOFULL_AW :: INT_EVENT0_ISET_SRXFIFOFULL_SET) } } # [doc = "Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_STXEMPTY_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_STXEMPTY_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_STXEMPTY_SET = 1 , } impl From < INT_EVENT0_ISET_STXEMPTY_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_STXEMPTY_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_STXEMPTY` writer - Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode."] pub type INT_EVENT0_ISET_STXEMPTY_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_STXEMPTY_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_STXEMPTY_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_stxempty_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_STXEMPTY_AW :: INT_EVENT0_ISET_STXEMPTY_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_stxempty_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_STXEMPTY_AW :: INT_EVENT0_ISET_STXEMPTY_SET) } } # [doc = "Start Condition Interrupt\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_SSTART_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_SSTART_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_SSTART_SET = 1 , } impl From < INT_EVENT0_ISET_SSTART_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_SSTART_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_SSTART` writer - Start Condition Interrupt"] pub type INT_EVENT0_ISET_SSTART_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_SSTART_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_SSTART_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_sstart_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_SSTART_AW :: INT_EVENT0_ISET_SSTART_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_sstart_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_SSTART_AW :: INT_EVENT0_ISET_SSTART_SET) } } # [doc = "Stop Condition Interrupt\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_SSTOP_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_SSTOP_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_SSTOP_SET = 1 , } impl From < INT_EVENT0_ISET_SSTOP_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_SSTOP_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_SSTOP` writer - Stop Condition Interrupt"] pub type INT_EVENT0_ISET_SSTOP_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_SSTOP_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_SSTOP_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_sstop_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_SSTOP_AW :: INT_EVENT0_ISET_SSTOP_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_sstop_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_SSTOP_AW :: INT_EVENT0_ISET_SSTOP_SET) } } # [doc = "General Call Interrupt\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_SGENCALL_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_SGENCALL_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_SGENCALL_SET = 1 , } impl From < INT_EVENT0_ISET_SGENCALL_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_SGENCALL_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_SGENCALL` writer - General Call Interrupt"] pub type INT_EVENT0_ISET_SGENCALL_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_SGENCALL_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_SGENCALL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_sgencall_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_SGENCALL_AW :: INT_EVENT0_ISET_SGENCALL_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_sgencall_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_SGENCALL_AW :: INT_EVENT0_ISET_SGENCALL_SET) } } # [doc = "DMA Done 1 on Event Channel 2\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_SDMA_DONE1_2_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_SDMA_DONE1_2_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_SDMA_DONE1_2_SET = 1 , } impl From < INT_EVENT0_ISET_SDMA_DONE1_2_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_SDMA_DONE1_2_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_SDMA_DONE1_2` writer - DMA Done 1 on Event Channel 2"] pub type INT_EVENT0_ISET_SDMA_DONE1_2_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_SDMA_DONE1_2_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_SDMA_DONE1_2_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_sdma_done1_2_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_SDMA_DONE1_2_AW :: INT_EVENT0_ISET_SDMA_DONE1_2_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_sdma_done1_2_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_SDMA_DONE1_2_AW :: INT_EVENT0_ISET_SDMA_DONE1_2_SET) } } # [doc = "DMA Done 1 on Event Channel 3\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_SDMA_DONE1_3_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_SDMA_DONE1_3_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_SDMA_DONE1_3_SET = 1 , } impl From < INT_EVENT0_ISET_SDMA_DONE1_3_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_SDMA_DONE1_3_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_SDMA_DONE1_3` writer - DMA Done 1 on Event Channel 3"] pub type INT_EVENT0_ISET_SDMA_DONE1_3_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_SDMA_DONE1_3_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_SDMA_DONE1_3_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_sdma_done1_3_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_SDMA_DONE1_3_AW :: INT_EVENT0_ISET_SDMA_DONE1_3_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_sdma_done1_3_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_SDMA_DONE1_3_AW :: INT_EVENT0_ISET_SDMA_DONE1_3_SET) } } # [doc = "Slave RX Pec Error Interrupt\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_SPEC_RX_ERR_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_SPEC_RX_ERR_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_SPEC_RX_ERR_SET = 1 , } impl From < INT_EVENT0_ISET_SPEC_RX_ERR_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_SPEC_RX_ERR_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_SPEC_RX_ERR` writer - Slave RX Pec Error Interrupt"] pub type INT_EVENT0_ISET_SPEC_RX_ERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_SPEC_RX_ERR_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_SPEC_RX_ERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_spec_rx_err_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_SPEC_RX_ERR_AW :: INT_EVENT0_ISET_SPEC_RX_ERR_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_spec_rx_err_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_SPEC_RX_ERR_AW :: INT_EVENT0_ISET_SPEC_RX_ERR_SET) } } # [doc = "Slave TX FIFO underflow\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_STX_UNFL_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_STX_UNFL_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_STX_UNFL_SET = 1 , } impl From < INT_EVENT0_ISET_STX_UNFL_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_STX_UNFL_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_STX_UNFL` writer - Slave TX FIFO underflow"] pub type INT_EVENT0_ISET_STX_UNFL_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_STX_UNFL_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_STX_UNFL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_stx_unfl_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_STX_UNFL_AW :: INT_EVENT0_ISET_STX_UNFL_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_stx_unfl_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_STX_UNFL_AW :: INT_EVENT0_ISET_STX_UNFL_SET) } } # [doc = "Slave RX FIFO overflow\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_SRX_OVFL_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_SRX_OVFL_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_SRX_OVFL_SET = 1 , } impl From < INT_EVENT0_ISET_SRX_OVFL_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_SRX_OVFL_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_SRX_OVFL` writer - Slave RX FIFO overflow"] pub type INT_EVENT0_ISET_SRX_OVFL_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_SRX_OVFL_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_SRX_OVFL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_srx_ovfl_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_SRX_OVFL_AW :: INT_EVENT0_ISET_SRX_OVFL_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_srx_ovfl_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_SRX_OVFL_AW :: INT_EVENT0_ISET_SRX_OVFL_SET) } } # [doc = "Slave Arbitration Lost\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_SARBLOST_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_SARBLOST_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_SARBLOST_SET = 1 , } impl From < INT_EVENT0_ISET_SARBLOST_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_SARBLOST_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_SARBLOST` writer - Slave Arbitration Lost"] pub type INT_EVENT0_ISET_SARBLOST_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_SARBLOST_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_SARBLOST_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_sarblost_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_SARBLOST_AW :: INT_EVENT0_ISET_SARBLOST_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_sarblost_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_SARBLOST_AW :: INT_EVENT0_ISET_SARBLOST_SET) } } # [doc = "Interrupt overflow\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_ISET_INTR_OVFL_AW { # [doc = "0: NO_EFFECT"] INT_EVENT0_ISET_INTR_OVFL_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT0_ISET_INTR_OVFL_SET = 1 , } impl From < INT_EVENT0_ISET_INTR_OVFL_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT0_ISET_INTR_OVFL_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_INTR_OVFL` writer - Interrupt overflow"] pub type INT_EVENT0_ISET_INTR_OVFL_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_INTR_OVFL_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_INTR_OVFL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event0_iset_intr_ovfl_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_INTR_OVFL_AW :: INT_EVENT0_ISET_INTR_OVFL_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event0_iset_intr_ovfl_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_INTR_OVFL_AW :: INT_EVENT0_ISET_INTR_OVFL_SET) } } impl W { # [doc = "Bit 0 - Master Receive Data Interrupt Signals that a byte has been received"] # [inline (always)] # [must_use] pub fn int_event0_iset_mrxdone (& mut self) -> INT_EVENT0_ISET_MRXDONE_W < INT_EVENT0_ISET_SPEC , 0 > { INT_EVENT0_ISET_MRXDONE_W :: new (self) } # [doc = "Bit 1 - Master Transmit Transaction completed Interrupt"] # [inline (always)] # [must_use] pub fn int_event0_iset_mtxdone (& mut self) -> INT_EVENT0_ISET_MTXDONE_W < INT_EVENT0_ISET_SPEC , 1 > { INT_EVENT0_ISET_MTXDONE_W :: new (self) } # [doc = "Bit 2 - Master Receive FIFO Trigger Trigger when RX FIFO contains &gt;= defined bytes"] # [inline (always)] # [must_use] pub fn int_event0_iset_mrxfifotrg (& mut self) -> INT_EVENT0_ISET_MRXFIFOTRG_W < INT_EVENT0_ISET_SPEC , 2 > { INT_EVENT0_ISET_MRXFIFOTRG_W :: new (self) } # [doc = "Bit 3 - Master Transmit FIFO Trigger Trigger when Transmit FIFO contains &lt;= defined bytes"] # [inline (always)] # [must_use] pub fn int_event0_iset_mtxfifotrg (& mut self) -> INT_EVENT0_ISET_MTXFIFOTRG_W < INT_EVENT0_ISET_SPEC , 3 > { INT_EVENT0_ISET_MTXFIFOTRG_W :: new (self) } # [doc = "Bit 4 - RXFIFO full event."] # [inline (always)] # [must_use] pub fn int_event0_iset_mrxfifofull (& mut self) -> INT_EVENT0_ISET_MRXFIFOFULL_W < INT_EVENT0_ISET_SPEC , 4 > { INT_EVENT0_ISET_MRXFIFOFULL_W :: new (self) } # [doc = "Bit 5 - Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode."] # [inline (always)] # [must_use] pub fn int_event0_iset_mtxempty (& mut self) -> INT_EVENT0_ISET_MTXEMPTY_W < INT_EVENT0_ISET_SPEC , 5 > { INT_EVENT0_ISET_MTXEMPTY_W :: new (self) } # [doc = "Bit 7 - Address/Data NACK Interrupt"] # [inline (always)] # [must_use] pub fn int_event0_iset_mnack (& mut self) -> INT_EVENT0_ISET_MNACK_W < INT_EVENT0_ISET_SPEC , 7 > { INT_EVENT0_ISET_MNACK_W :: new (self) } # [doc = "Bit 8 - START Detection Interrupt"] # [inline (always)] # [must_use] pub fn int_event0_iset_mstart (& mut self) -> INT_EVENT0_ISET_MSTART_W < INT_EVENT0_ISET_SPEC , 8 > { INT_EVENT0_ISET_MSTART_W :: new (self) } # [doc = "Bit 9 - STOP Detection Interrupt"] # [inline (always)] # [must_use] pub fn int_event0_iset_mstop (& mut self) -> INT_EVENT0_ISET_MSTOP_W <'_, INT_EVENT0_ISET_SPEC , 9 > { INT_EVENT0_ISET_MSTOP_W :: new (self) } # [doc = "Bit 10 - Arbitration Lost Interrupt"] # [inline (always)] # [must_use] pub fn int_event0_iset_marblost (& mut self) -> INT_EVENT0_ISET_MARBLOST_W < INT_EVENT0_ISET_SPEC , 10 > { INT_EVENT0_ISET_MARBLOST_W :: new (self) } # [doc = "Bit 11 - DMA Done 1 on Event Channel 2"] # [inline (always)] # [must_use] pub fn int_event0_iset_mdma_done1_2 (& mut self) -> INT_EVENT0_ISET_MDMA_DONE1_2_W < INT_EVENT0_ISET_SPEC , 11 > { INT_EVENT0_ISET_MDMA_DONE1_2_W :: new (self) } # [doc = "Bit 12 - DMA Done 1 on Event Channel 3"] # [inline (always)] # [must_use] pub fn int_event0_iset_mdma_done1_3 (& mut self) -> INT_EVENT0_ISET_MDMA_DONE1_3_W < INT_EVENT0_ISET_SPEC , 12 > { INT_EVENT0_ISET_MDMA_DONE1_3_W :: new (self) } # [doc = "Bit 13 - Master RX Pec Error Interrupt"] # [inline (always)] # [must_use] pub fn int_event0_iset_mpec_rx_err (& mut self) -> INT_EVENT0_ISET_MPEC_RX_ERR_W < INT_EVENT0_ISET_SPEC , 13 > { INT_EVENT0_ISET_MPEC_RX_ERR_W :: new (self) } # [doc = "Bit 14 - Timeout A interrupt"] # [inline (always)] # [must_use] pub fn int_event0_iset_timeouta (& mut self) -> INT_EVENT0_ISET_TIMEOUTA_W < INT_EVENT0_ISET_SPEC , 14 > { INT_EVENT0_ISET_TIMEOUTA_W :: new (self) } # [doc = "Bit 15 - Timeout B Interrupt"] # [inline (always)] # [must_use] pub fn int_event0_iset_timeoutb (& mut self) -> INT_EVENT0_ISET_TIMEOUTB_W < INT_EVENT0_ISET_SPEC , 15 > { INT_EVENT0_ISET_TIMEOUTB_W :: new (self) } # [doc = "Bit 16 - Slave Receive Data Interrupt Signals that a byte has been received"] # [inline (always)] # [must_use] pub fn int_event0_iset_srxdone (& mut self) -> INT_EVENT0_ISET_SRXDONE_W < INT_EVENT0_ISET_SPEC , 16 > { INT_EVENT0_ISET_SRXDONE_W :: new (self) } # [doc = "Bit 17 - Slave Transmit Transaction completed Interrupt"] # [inline (always)] # [must_use] pub fn int_event0_iset_stxdone (& mut self) -> INT_EVENT0_ISET_STXDONE_W < INT_EVENT0_ISET_SPEC , 17 > { INT_EVENT0_ISET_STXDONE_W :: new (self) } # [doc = "Bit 18 - Slave Receive FIFO Trigger"] # [inline (always)] # [must_use] pub fn int_event0_iset_srxfifotrg (& mut self) -> INT_EVENT0_ISET_SRXFIFOTRG_W < INT_EVENT0_ISET_SPEC , 18 > { INT_EVENT0_ISET_SRXFIFOTRG_W :: new (self) } # [doc = "Bit 19 - Slave Transmit FIFO Trigger"] # [inline (always)] # [must_use] pub fn int_event0_iset_stxfifotrg (& mut self) -> INT_EVENT0_ISET_STXFIFOTRG_W < INT_EVENT0_ISET_SPEC , 19 > { INT_EVENT0_ISET_STXFIFOTRG_W :: new (self) } # [doc = "Bit 20 - RXFIFO full event. This interrupt is set if an RX FIFO is full."] # [inline (always)] # [must_use] pub fn int_event0_iset_srxfifofull (& mut self) -> INT_EVENT0_ISET_SRXFIFOFULL_W < INT_EVENT0_ISET_SPEC , 20 > { INT_EVENT0_ISET_SRXFIFOFULL_W :: new (self) } # [doc = "Bit 21 - Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode."] # [inline (always)] # [must_use] pub fn int_event0_iset_stxempty (& mut self) -> INT_EVENT0_ISET_STXEMPTY_W < INT_EVENT0_ISET_SPEC , 21 > { INT_EVENT0_ISET_STXEMPTY_W :: new (self) } # [doc = "Bit 22 - Start Condition Interrupt"] # [inline (always)] # [must_use] pub fn int_event0_iset_sstart (& mut self) -> INT_EVENT0_ISET_SSTART_W < INT_EVENT0_ISET_SPEC , 22 > { INT_EVENT0_ISET_SSTART_W :: new (self) } # [doc = "Bit 23 - Stop Condition Interrupt"] # [inline (always)] # [must_use] pub fn int_event0_iset_sstop (& mut self) -> INT_EVENT0_ISET_SSTOP_W < INT_EVENT0_ISET_SPEC , 23 > { INT_EVENT0_ISET_SSTOP_W :: new (self) } # [doc = "Bit 24 - General Call Interrupt"] # [inline (always)] # [must_use] pub fn int_event0_iset_sgencall (& mut self) -> INT_EVENT0_ISET_SGENCALL_W < INT_EVENT0_ISET_SPEC , 24 > { INT_EVENT0_ISET_SGENCALL_W :: new (self) } # [doc = "Bit 25 - DMA Done 1 on Event Channel 2"] # [inline (always)] # [must_use] pub fn int_event0_iset_sdma_done1_2 (& mut self) -> INT_EVENT0_ISET_SDMA_DONE1_2_W < INT_EVENT0_ISET_SPEC , 25 > { INT_EVENT0_ISET_SDMA_DONE1_2_W :: new (self) } # [doc = "Bit 26 - DMA Done 1 on Event Channel 3"] # [inline (always)] # [must_use] pub fn int_event0_iset_sdma_done1_3 (& mut self) -> INT_EVENT0_ISET_SDMA_DONE1_3_W < INT_EVENT0_ISET_SPEC , 26 > { INT_EVENT0_ISET_SDMA_DONE1_3_W :: new (self) } # [doc = "Bit 27 - Slave RX Pec Error Interrupt"] # [inline (always)] # [must_use] pub fn int_event0_iset_spec_rx_err (& mut self) -> INT_EVENT0_ISET_SPEC_RX_ERR_W < INT_EVENT0_ISET_SPEC , 27 > { INT_EVENT0_ISET_SPEC_RX_ERR_W :: new (self) } # [doc = "Bit 28 - Slave TX FIFO underflow"] # [inline (always)] # [must_use] pub fn int_event0_iset_stx_unfl (& mut self) -> INT_EVENT0_ISET_STX_UNFL_W < INT_EVENT0_ISET_SPEC , 28 > { INT_EVENT0_ISET_STX_UNFL_W :: new (self) } # [doc = "Bit 29 - Slave RX FIFO overflow"] # [inline (always)] # [must_use] pub fn int_event0_iset_srx_ovfl (& mut self) -> INT_EVENT0_ISET_SRX_OVFL_W < INT_EVENT0_ISET_SPEC , 29 > { INT_EVENT0_ISET_SRX_OVFL_W :: new (self) } # [doc = "Bit 30 - Slave Arbitration Lost"] # [inline (always)] # [must_use] pub fn int_event0_iset_sarblost (& mut self) -> INT_EVENT0_ISET_SARBLOST_W < INT_EVENT0_ISET_SPEC , 30 > { INT_EVENT0_ISET_SARBLOST_W :: new (self) } # [doc = "Bit 31 - Interrupt overflow"] # [inline (always)] # [must_use] pub fn int_event0_iset_intr_ovfl (& mut self) -> INT_EVENT0_ISET_INTR_OVFL_W < INT_EVENT0_ISET_SPEC , 31 > { INT_EVENT0_ISET_INTR_OVFL_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Interrupt set\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_event0_iset::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct INT_EVENT0_ISET_SPEC ; impl crate :: RegisterSpec for INT_EVENT0_ISET_SPEC { type Ux = u32 ; } # [doc = "`write(|w| ..)` method takes [`int_event0_iset::W`](W) writer structure"] impl crate :: Writable for INT_EVENT0_ISET_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets INT_EVENT0_ISET to value 0"] impl crate :: Resettable for INT_EVENT0_ISET_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/sysctl/sysosccfg.rs:1:18047 [INFO] [stdout] | [INFO] [stdout] 1 | ...osccfg_disablestop (& mut self) -> SYSOSCCFG_DISABLESTOP_W < SYSOSCCFG_SPEC , 9 > { SYSOSCCFG_DISABLESTOP_W :: new (self) } # [doc = "... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `SYSOSCCFG` reader"] pub type R = crate :: R < SYSOSCCFG_SPEC > ; # [doc = "Register `SYSOSCCFG` writer"] pub type W = crate :: W < SYSOSCCFG_SPEC > ; # [doc = "Field `SYSOSCCFG_FREQ` reader - Target operating frequency for the system oscillator (SYSOSC)"] pub type SYSOSCCFG_FREQ_R = crate :: FieldReader < SYSOSCCFG_FREQ_A > ; # [doc = "Target operating frequency for the system oscillator (SYSOSC)\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum SYSOSCCFG_FREQ_A { # [doc = "0: SYSOSCBASE"] SYSOSCCFG_FREQ_SYSOSCBASE = 0 , # [doc = "1: SYSOSC4M"] SYSOSCCFG_FREQ_SYSOSC4M = 1 , # [doc = "2: SYSOSCUSER"] SYSOSCCFG_FREQ_SYSOSCUSER = 2 , # [doc = "3: SYSOSCTURBO"] SYSOSCCFG_FREQ_SYSOSCTURBO = 3 , } impl From < SYSOSCCFG_FREQ_A > for u8 { # [inline (always)] fn from (variant : SYSOSCCFG_FREQ_A) -> Self { variant as _ } } impl crate :: FieldSpec for SYSOSCCFG_FREQ_A { type Ux = u8 ; } impl SYSOSCCFG_FREQ_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> SYSOSCCFG_FREQ_A { match self . bits { 0 => SYSOSCCFG_FREQ_A :: SYSOSCCFG_FREQ_SYSOSCBASE , 1 => SYSOSCCFG_FREQ_A :: SYSOSCCFG_FREQ_SYSOSC4M , 2 => SYSOSCCFG_FREQ_A :: SYSOSCCFG_FREQ_SYSOSCUSER , 3 => SYSOSCCFG_FREQ_A :: SYSOSCCFG_FREQ_SYSOSCTURBO , _ => unreachable ! () , } } # [doc = "SYSOSCBASE"] # [inline (always)] pub fn is_sysosccfg_freq_sysoscbase (& self) -> bool { * self == SYSOSCCFG_FREQ_A :: SYSOSCCFG_FREQ_SYSOSCBASE } # [doc = "SYSOSC4M"] # [inline (always)] pub fn is_sysosccfg_freq_sysosc4m (& self) -> bool { * self == SYSOSCCFG_FREQ_A :: SYSOSCCFG_FREQ_SYSOSC4M } # [doc = "SYSOSCUSER"] # [inline (always)] pub fn is_sysosccfg_freq_sysoscuser (& self) -> bool { * self == SYSOSCCFG_FREQ_A :: SYSOSCCFG_FREQ_SYSOSCUSER } # [doc = "SYSOSCTURBO"] # [inline (always)] pub fn is_sysosccfg_freq_sysoscturbo (& self) -> bool { * self == SYSOSCCFG_FREQ_A :: SYSOSCCFG_FREQ_SYSOSCTURBO } } # [doc = "Field `SYSOSCCFG_FREQ` writer - Target operating frequency for the system oscillator (SYSOSC)"] pub type SYSOSCCFG_FREQ_W < 'a , REG , const O : u8 > = crate :: FieldWriterSafe < 'a , REG , 2 , O , SYSOSCCFG_FREQ_A > ; impl < 'a , REG , const O : u8 > SYSOSCCFG_FREQ_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "SYSOSCBASE"] # [inline (always)] pub fn sysosccfg_freq_sysoscbase (self) -> & 'a mut crate :: W < REG > { self . variant (SYSOSCCFG_FREQ_A :: SYSOSCCFG_FREQ_SYSOSCBASE) } # [doc = "SYSOSC4M"] # [inline (always)] pub fn sysosccfg_freq_sysosc4m (self) -> & 'a mut crate :: W < REG > { self . variant (SYSOSCCFG_FREQ_A :: SYSOSCCFG_FREQ_SYSOSC4M) } # [doc = "SYSOSCUSER"] # [inline (always)] pub fn sysosccfg_freq_sysoscuser (self) -> & 'a mut crate :: W < REG > { self . variant (SYSOSCCFG_FREQ_A :: SYSOSCCFG_FREQ_SYSOSCUSER) } # [doc = "SYSOSCTURBO"] # [inline (always)] pub fn sysosccfg_freq_sysoscturbo (self) -> & 'a mut crate :: W < REG > { self . variant (SYSOSCCFG_FREQ_A :: SYSOSCCFG_FREQ_SYSOSCTURBO) } } # [doc = "Field `SYSOSCCFG_USE4MHZSTOP` reader - USE4MHZSTOP sets the SYSOSC stop mode frequency policy. When entering STOP mode, the SYSOSC frequency may be automatically switched to 4MHz to reduce SYSOSC power consumption."] pub type SYSOSCCFG_USE4MHZSTOP_R = crate :: BitReader < SYSOSCCFG_USE4MHZSTOP_A > ; # [doc = "USE4MHZSTOP sets the SYSOSC stop mode frequency policy. When entering STOP mode, the SYSOSC frequency may be automatically switched to 4MHz to reduce SYSOSC power consumption.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum SYSOSCCFG_USE4MHZSTOP_A { # [doc = "0: DISABLE"] SYSOSCCFG_USE4MHZSTOP_DISABLE = 0 , # [doc = "1: ENABLE"] SYSOSCCFG_USE4MHZSTOP_ENABLE = 1 , } impl From < SYSOSCCFG_USE4MHZSTOP_A > for bool { # [inline (always)] fn from (variant : SYSOSCCFG_USE4MHZSTOP_A) -> Self { variant as u8 != 0 } } impl SYSOSCCFG_USE4MHZSTOP_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> SYSOSCCFG_USE4MHZSTOP_A { match self . bits { false => SYSOSCCFG_USE4MHZSTOP_A :: SYSOSCCFG_USE4MHZSTOP_DISABLE , true => SYSOSCCFG_USE4MHZSTOP_A :: SYSOSCCFG_USE4MHZSTOP_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_sysosccfg_use4mhzstop_disable (& self) -> bool { * self == SYSOSCCFG_USE4MHZSTOP_A :: SYSOSCCFG_USE4MHZSTOP_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_sysosccfg_use4mhzstop_enable (& self) -> bool { * self == SYSOSCCFG_USE4MHZSTOP_A :: SYSOSCCFG_USE4MHZSTOP_ENABLE } } # [doc = "Field `SYSOSCCFG_USE4MHZSTOP` writer - USE4MHZSTOP sets the SYSOSC stop mode frequency policy. When entering STOP mode, the SYSOSC frequency may be automatically switched to 4MHz to reduce SYSOSC power consumption."] pub type SYSOSCCFG_USE4MHZSTOP_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , SYSOSCCFG_USE4MHZSTOP_A > ; impl < 'a , REG , const O : u8 > SYSOSCCFG_USE4MHZSTOP_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn sysosccfg_use4mhzstop_disable (self) -> & 'a mut crate :: W < REG > { self . variant (SYSOSCCFG_USE4MHZSTOP_A :: SYSOSCCFG_USE4MHZSTOP_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn sysosccfg_use4mhzstop_enable (self) -> & 'a mut crate :: W < REG > { self . variant (SYSOSCCFG_USE4MHZSTOP_A :: SYSOSCCFG_USE4MHZSTOP_ENABLE) } } # [doc = "Field `SYSOSCCFG_DISABLESTOP` reader - DISABLESTOP sets the SYSOSC stop mode enable/disable policy. When operating in STOP mode, the SYSOSC may be automatically disabled. When set, ULPCLK will run from LFCLK in STOP mode and SYSOSC will be disabled to reduce power consumption."] pub type SYSOSCCFG_DISABLESTOP_R = crate :: BitReader < SYSOSCCFG_DISABLESTOP_A > ; # [doc = "DISABLESTOP sets the SYSOSC stop mode enable/disable policy. When operating in STOP mode, the SYSOSC may be automatically disabled. When set, ULPCLK will run from LFCLK in STOP mode and SYSOSC will be disabled to reduce power consumption.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum SYSOSCCFG_DISABLESTOP_A { # [doc = "0: DISABLE"] SYSOSCCFG_DISABLESTOP_DISABLE = 0 , # [doc = "1: ENABLE"] SYSOSCCFG_DISABLESTOP_ENABLE = 1 , } impl From < SYSOSCCFG_DISABLESTOP_A > for bool { # [inline (always)] fn from (variant : SYSOSCCFG_DISABLESTOP_A) -> Self { variant as u8 != 0 } } impl SYSOSCCFG_DISABLESTOP_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> SYSOSCCFG_DISABLESTOP_A { match self . bits { false => SYSOSCCFG_DISABLESTOP_A :: SYSOSCCFG_DISABLESTOP_DISABLE , true => SYSOSCCFG_DISABLESTOP_A :: SYSOSCCFG_DISABLESTOP_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_sysosccfg_disablestop_disable (& self) -> bool { * self == SYSOSCCFG_DISABLESTOP_A :: SYSOSCCFG_DISABLESTOP_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_sysosccfg_disablestop_enable (& self) -> bool { * self == SYSOSCCFG_DISABLESTOP_A :: SYSOSCCFG_DISABLESTOP_ENABLE } } # [doc = "Field `SYSOSCCFG_DISABLESTOP` writer - DISABLESTOP sets the SYSOSC stop mode enable/disable policy. When operating in STOP mode, the SYSOSC may be automatically disabled. When set, ULPCLK will run from LFCLK in STOP mode and SYSOSC will be disabled to reduce power consumption."] pub type SYSOSCCFG_DISABLESTOP_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , SYSOSCCFG_DISABLESTOP_A > ; impl < 'a , REG , const O : u8 > SYSOSCCFG_DISABLESTOP_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn sysosccfg_disablestop_disable (self) -> & 'a mut crate :: W < REG > { self . variant (SYSOSCCFG_DISABLESTOP_A :: SYSOSCCFG_DISABLESTOP_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn sysosccfg_disablestop_enable (self) -> & 'a mut crate :: W < REG > { self . variant (SYSOSCCFG_DISABLESTOP_A :: SYSOSCCFG_DISABLESTOP_ENABLE) } } # [doc = "Field `SYSOSCCFG_DISABLE` reader - DISABLE sets the SYSOSC enable/disable policy. SYSOSC may be powered off in RUN, SLEEP, and STOP modes to reduce power consumption. When SYSOSC is disabled, MCLK and ULPCLK are sourced from LFCLK."] pub type SYSOSCCFG_DISABLE_R = crate :: BitReader < SYSOSCCFG_DISABLE_A > ; # [doc = "DISABLE sets the SYSOSC enable/disable policy. SYSOSC may be powered off in RUN, SLEEP, and STOP modes to reduce power consumption. When SYSOSC is disabled, MCLK and ULPCLK are sourced from LFCLK.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum SYSOSCCFG_DISABLE_A { # [doc = "0: DISABLE"] SYSOSCCFG_DISABLE_DISABLE = 0 , # [doc = "1: ENABLE"] SYSOSCCFG_DISABLE_ENABLE = 1 , } impl From < SYSOSCCFG_DISABLE_A > for bool { # [inline (always)] fn from (variant : SYSOSCCFG_DISABLE_A) -> Self { variant as u8 != 0 } } impl SYSOSCCFG_DISABLE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> SYSOSCCFG_DISABLE_A { match self . bits { false => SYSOSCCFG_DISABLE_A :: SYSOSCCFG_DISABLE_DISABLE , true => SYSOSCCFG_DISABLE_A :: SYSOSCCFG_DISABLE_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_sysosccfg_disable_disable (& self) -> bool { * self == SYSOSCCFG_DISABLE_A :: SYSOSCCFG_DISABLE_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_sysosccfg_disable_enable (& self) -> bool { * self == SYSOSCCFG_DISABLE_A :: SYSOSCCFG_DISABLE_ENABLE } } # [doc = "Field `SYSOSCCFG_DISABLE` writer - DISABLE sets the SYSOSC enable/disable policy. SYSOSC may be powered off in RUN, SLEEP, and STOP modes to reduce power consumption. When SYSOSC is disabled, MCLK and ULPCLK are sourced from LFCLK."] pub type SYSOSCCFG_DISABLE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , SYSOSCCFG_DISABLE_A > ; impl < 'a , REG , const O : u8 > SYSOSCCFG_DISABLE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn sysosccfg_disable_disable (self) -> & 'a mut crate :: W < REG > { self . variant (SYSOSCCFG_DISABLE_A :: SYSOSCCFG_DISABLE_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn sysosccfg_disable_enable (self) -> & 'a mut crate :: W < REG > { self . variant (SYSOSCCFG_DISABLE_A :: SYSOSCCFG_DISABLE_ENABLE) } } # [doc = "Field `SYSOSCCFG_BLOCKASYNCALL` reader - BLOCKASYNCALL may be used to mask block all asynchronous fast clock requests, preventing hardware from dynamically changing the active clock configuration when operating in a given mode."] pub type SYSOSCCFG_BLOCKASYNCALL_R = crate :: BitReader < SYSOSCCFG_BLOCKASYNCALL_A > ; # [doc = "BLOCKASYNCALL may be used to mask block all asynchronous fast clock requests, preventing hardware from dynamically changing the active clock configuration when operating in a given mode.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum SYSOSCCFG_BLOCKASYNCALL_A { # [doc = "0: DISABLE"] SYSOSCCFG_BLOCKASYNCALL_DISABLE = 0 , # [doc = "1: ENABLE"] SYSOSCCFG_BLOCKASYNCALL_ENABLE = 1 , } impl From < SYSOSCCFG_BLOCKASYNCALL_A > for bool { # [inline (always)] fn from (variant : SYSOSCCFG_BLOCKASYNCALL_A) -> Self { variant as u8 != 0 } } impl SYSOSCCFG_BLOCKASYNCALL_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> SYSOSCCFG_BLOCKASYNCALL_A { match self . bits { false => SYSOSCCFG_BLOCKASYNCALL_A :: SYSOSCCFG_BLOCKASYNCALL_DISABLE , true => SYSOSCCFG_BLOCKASYNCALL_A :: SYSOSCCFG_BLOCKASYNCALL_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_sysosccfg_blockasyncall_disable (& self) -> bool { * self == SYSOSCCFG_BLOCKASYNCALL_A :: SYSOSCCFG_BLOCKASYNCALL_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_sysosccfg_blockasyncall_enable (& self) -> bool { * self == SYSOSCCFG_BLOCKASYNCALL_A :: SYSOSCCFG_BLOCKASYNCALL_ENABLE } } # [doc = "Field `SYSOSCCFG_BLOCKASYNCALL` writer - BLOCKASYNCALL may be used to mask block all asynchronous fast clock requests, preventing hardware from dynamically changing the active clock configuration when operating in a given mode."] pub type SYSOSCCFG_BLOCKASYNCALL_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , SYSOSCCFG_BLOCKASYNCALL_A > ; impl < 'a , REG , const O : u8 > SYSOSCCFG_BLOCKASYNCALL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn sysosccfg_blockasyncall_disable (self) -> & 'a mut crate :: W < REG > { self . variant (SYSOSCCFG_BLOCKASYNCALL_A :: SYSOSCCFG_BLOCKASYNCALL_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn sysosccfg_blockasyncall_enable (self) -> & 'a mut crate :: W < REG > { self . variant (SYSOSCCFG_BLOCKASYNCALL_A :: SYSOSCCFG_BLOCKASYNCALL_ENABLE) } } # [doc = "Field `SYSOSCCFG_FASTCPUEVENT` reader - FASTCPUEVENT may be used to assert a fast clock request when an interrupt is asserted to the CPU, reducing interrupt latency."] pub type SYSOSCCFG_FASTCPUEVENT_R = crate :: BitReader < SYSOSCCFG_FASTCPUEVENT_A > ; # [doc = "FASTCPUEVENT may be used to assert a fast clock request when an interrupt is asserted to the CPU, reducing interrupt latency.\n\nValue on reset: 1"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum SYSOSCCFG_FASTCPUEVENT_A { # [doc = "0: DISABLE"] SYSOSCCFG_FASTCPUEVENT_DISABLE = 0 , # [doc = "1: ENABLE"] SYSOSCCFG_FASTCPUEVENT_ENABLE = 1 , } impl From < SYSOSCCFG_FASTCPUEVENT_A > for bool { # [inline (always)] fn from (variant : SYSOSCCFG_FASTCPUEVENT_A) -> Self { variant as u8 != 0 } } impl SYSOSCCFG_FASTCPUEVENT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> SYSOSCCFG_FASTCPUEVENT_A { match self . bits { false => SYSOSCCFG_FASTCPUEVENT_A :: SYSOSCCFG_FASTCPUEVENT_DISABLE , true => SYSOSCCFG_FASTCPUEVENT_A :: SYSOSCCFG_FASTCPUEVENT_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_sysosccfg_fastcpuevent_disable (& self) -> bool { * self == SYSOSCCFG_FASTCPUEVENT_A :: SYSOSCCFG_FASTCPUEVENT_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_sysosccfg_fastcpuevent_enable (& self) -> bool { * self == SYSOSCCFG_FASTCPUEVENT_A :: SYSOSCCFG_FASTCPUEVENT_ENABLE } } # [doc = "Field `SYSOSCCFG_FASTCPUEVENT` writer - FASTCPUEVENT may be used to assert a fast clock request when an interrupt is asserted to the CPU, reducing interrupt latency."] pub type SYSOSCCFG_FASTCPUEVENT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , SYSOSCCFG_FASTCPUEVENT_A > ; impl < 'a , REG , const O : u8 > SYSOSCCFG_FASTCPUEVENT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn sysosccfg_fastcpuevent_disable (self) -> & 'a mut crate :: W < REG > { self . variant (SYSOSCCFG_FASTCPUEVENT_A :: SYSOSCCFG_FASTCPUEVENT_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn sysosccfg_fastcpuevent_enable (self) -> & 'a mut crate :: W < REG > { self . variant (SYSOSCCFG_FASTCPUEVENT_A :: SYSOSCCFG_FASTCPUEVENT_ENABLE) } } impl R { # [doc = "Bits 0:1 - Target operating frequency for the system oscillator (SYSOSC)"] # [inline (always)] pub fn sysosccfg_freq (& self) -> SYSOSCCFG_FREQ_R { SYSOSCCFG_FREQ_R :: new ((self . bits & 3) as u8) } # [doc = "Bit 8 - USE4MHZSTOP sets the SYSOSC stop mode frequency policy. When entering STOP mode, the SYSOSC frequency may be automatically switched to 4MHz to reduce SYSOSC power consumption."] # [inline (always)] pub fn sysosccfg_use4mhzstop (& self) -> SYSOSCCFG_USE4MHZSTOP_R { SYSOSCCFG_USE4MHZSTOP_R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - DISABLESTOP sets the SYSOSC stop mode enable/disable policy. When operating in STOP mode, the SYSOSC may be automatically disabled. When set, ULPCLK will run from LFCLK in STOP mode and SYSOSC will be disabled to reduce power consumption."] # [inline (always)] pub fn sysosccfg_disablestop (& self) -> SYSOSCCFG_DISABLESTOP_R { SYSOSCCFG_DISABLESTOP_R :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - DISABLE sets the SYSOSC enable/disable policy. SYSOSC may be powered off in RUN, SLEEP, and STOP modes to reduce power consumption. When SYSOSC is disabled, MCLK and ULPCLK are sourced from LFCLK."] # [inline (always)] pub fn sysosccfg_disable (& self) -> SYSOSCCFG_DISABLE_R { SYSOSCCFG_DISABLE_R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 16 - BLOCKASYNCALL may be used to mask block all asynchronous fast clock requests, preventing hardware from dynamically changing the active clock configuration when operating in a given mode."] # [inline (always)] pub fn sysosccfg_blockasyncall (& self) -> SYSOSCCFG_BLOCKASYNCALL_R { SYSOSCCFG_BLOCKASYNCALL_R :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - FASTCPUEVENT may be used to assert a fast clock request when an interrupt is asserted to the CPU, reducing interrupt latency."] # [inline (always)] pub fn sysosccfg_fastcpuevent (& self) -> SYSOSCCFG_FASTCPUEVENT_R { SYSOSCCFG_FASTCPUEVENT_R :: new (((self . bits >> 17) & 1) != 0) } } impl W { # [doc = "Bits 0:1 - Target operating frequency for the system oscillator (SYSOSC)"] # [inline (always)] # [must_use] pub fn sysosccfg_freq (& mut self) -> SYSOSCCFG_FREQ_W < SYSOSCCFG_SPEC , 0 > { SYSOSCCFG_FREQ_W :: new (self) } # [doc = "Bit 8 - USE4MHZSTOP sets the SYSOSC stop mode frequency policy. When entering STOP mode, the SYSOSC frequency may be automatically switched to 4MHz to reduce SYSOSC power consumption."] # [inline (always)] # [must_use] pub fn sysosccfg_use4mhzstop (& mut self) -> SYSOSCCFG_USE4MHZSTOP_W < SYSOSCCFG_SPEC , 8 > { SYSOSCCFG_USE4MHZSTOP_W :: new (self) } # [doc = "Bit 9 - DISABLESTOP sets the SYSOSC stop mode enable/disable policy. When operating in STOP mode, the SYSOSC may be automatically disabled. When set, ULPCLK will run from LFCLK in STOP mode and SYSOSC will be disabled to reduce power consumption."] # [inline (always)] # [must_use] pub fn sysosccfg_disablestop (& mut self) -> SYSOSCCFG_DISABLESTOP_W <'_, SYSOSCCFG_SPEC , 9 > { SYSOSCCFG_DISABLESTOP_W :: new (self) } # [doc = "Bit 10 - DISABLE sets the SYSOSC enable/disable policy. SYSOSC may be powered off in RUN, SLEEP, and STOP modes to reduce power consumption. When SYSOSC is disabled, MCLK and ULPCLK are sourced from LFCLK."] # [inline (always)] # [must_use] pub fn sysosccfg_disable (& mut self) -> SYSOSCCFG_DISABLE_W < SYSOSCCFG_SPEC , 10 > { SYSOSCCFG_DISABLE_W :: new (self) } # [doc = "Bit 16 - BLOCKASYNCALL may be used to mask block all asynchronous fast clock requests, preventing hardware from dynamically changing the active clock configuration when operating in a given mode."] # [inline (always)] # [must_use] pub fn sysosccfg_blockasyncall (& mut self) -> SYSOSCCFG_BLOCKASYNCALL_W < SYSOSCCFG_SPEC , 16 > { SYSOSCCFG_BLOCKASYNCALL_W :: new (self) } # [doc = "Bit 17 - FASTCPUEVENT may be used to assert a fast clock request when an interrupt is asserted to the CPU, reducing interrupt latency."] # [inline (always)] # [must_use] pub fn sysosccfg_fastcpuevent (& mut self) -> SYSOSCCFG_FASTCPUEVENT_W < SYSOSCCFG_SPEC , 17 > { SYSOSCCFG_FASTCPUEVENT_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "SYSOSC configuration\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sysosccfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sysosccfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct SYSOSCCFG_SPEC ; impl crate :: RegisterSpec for SYSOSCCFG_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`sysosccfg::R`](R) reader structure"] impl crate :: Readable for SYSOSCCFG_SPEC { } # [doc = "`write(|w| ..)` method takes [`sysosccfg::W`](W) writer structure"] impl crate :: Writable for SYSOSCCFG_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets SYSOSCCFG to value 0x0002_0000"] impl crate :: Resettable for SYSOSCCFG_SPEC { const RESET_VALUE : Self :: Ux = 0x0002_0000 ; } [WARN] too much data in the log, truncating it